1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let hasSideEffects = 0 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let hasSideEffects = 0 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let hasSideEffects = 0 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
436 (v16i32 immAllZerosV), (i16 GR16:$mask))),
437 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
438 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
439 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
440 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
442 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
443 X86MemOperand x86memop, PatFrag ld_frag,
444 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
446 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
447 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
449 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
450 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
452 !strconcat(OpcodeStr,
453 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
455 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
458 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
459 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
461 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
462 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
464 !strconcat(OpcodeStr,
465 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
466 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
467 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
471 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
472 loadi32, VR512, v16i32, v4i32, VK16WM>,
473 EVEX_V512, EVEX_CD8<32, CD8VT1>;
474 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
475 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
476 EVEX_CD8<64, CD8VT1>;
478 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
479 (VPBROADCASTDZrr VR128X:$src)>;
480 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
481 (VPBROADCASTQZrr VR128X:$src)>;
483 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
484 (VBROADCASTSSZrr VR128X:$src)>;
485 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
486 (VBROADCASTSDZrr VR128X:$src)>;
488 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
489 (VBROADCASTSSZrr VR128X:$src)>;
490 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
491 (VBROADCASTSDZrr VR128X:$src)>;
493 // Provide fallback in case the load node that is used in the patterns above
494 // is used by additional users, which prevents the pattern selection.
495 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
496 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
497 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
498 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
501 let Predicates = [HasAVX512] in {
502 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
504 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
505 addr:$src)), sub_ymm)>;
507 //===----------------------------------------------------------------------===//
508 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
511 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
512 RegisterClass DstRC, RegisterClass KRC,
513 ValueType OpVT, ValueType SrcVT> {
514 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
515 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
519 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
520 VK16, v16i32, v16i1>, EVEX_V512;
521 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
522 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
524 //===----------------------------------------------------------------------===//
527 // -- immediate form --
528 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
529 SDNode OpNode, PatFrag mem_frag,
530 X86MemOperand x86memop, ValueType OpVT> {
531 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
532 (ins RC:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
538 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
539 (ins x86memop:$src1, i8imm:$src2),
540 !strconcat(OpcodeStr,
541 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
543 (OpVT (OpNode (mem_frag addr:$src1),
544 (i8 imm:$src2))))]>, EVEX;
547 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
548 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
549 let ExeDomain = SSEPackedDouble in
550 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
551 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
553 // -- VPERM - register form --
554 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
555 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
557 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
558 (ins RC:$src1, RC:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, x86memop:$src2),
566 !strconcat(OpcodeStr,
567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
569 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
573 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 let ExeDomain = SSEPackedSingle in
578 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
579 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
580 let ExeDomain = SSEPackedDouble in
581 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
582 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
584 // -- VPERM2I - 3 source operands form --
585 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
586 PatFrag mem_frag, X86MemOperand x86memop,
588 let Constraints = "$src1 = $dst" in {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins RC:$src1, RC:$src2, RC:$src3),
591 !strconcat(OpcodeStr,
592 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
594 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
597 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
598 (ins RC:$src1, RC:$src2, x86memop:$src3),
599 !strconcat(OpcodeStr,
600 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
602 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
603 (mem_frag addr:$src3))))]>, EVEX_4V;
606 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
607 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
608 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
609 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
610 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
611 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
612 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
613 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
615 //===----------------------------------------------------------------------===//
616 // AVX-512 - BLEND using mask
618 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
619 RegisterClass KRC, RegisterClass RC,
620 X86MemOperand x86memop, PatFrag mem_frag,
621 SDNode OpNode, ValueType vt> {
622 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
623 (ins KRC:$mask, RC:$src1, RC:$src2),
624 !strconcat(OpcodeStr,
625 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
626 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
627 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
633 []>, EVEX_4V, EVEX_K;
636 let ExeDomain = SSEPackedSingle in
637 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
638 VK16WM, VR512, f512mem,
639 memopv16f32, vselect, v16f32>,
640 EVEX_CD8<32, CD8VF>, EVEX_V512;
641 let ExeDomain = SSEPackedDouble in
642 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
643 VK8WM, VR512, f512mem,
644 memopv8f64, vselect, v8f64>,
645 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
647 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
648 (v16f32 VR512:$src2), (i16 GR16:$mask))),
649 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
650 VR512:$src1, VR512:$src2)>;
652 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
653 (v8f64 VR512:$src2), (i8 GR8:$mask))),
654 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
655 VR512:$src1, VR512:$src2)>;
657 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
658 VK16WM, VR512, f512mem,
659 memopv16i32, vselect, v16i32>,
660 EVEX_CD8<32, CD8VF>, EVEX_V512;
662 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
663 VK8WM, VR512, f512mem,
664 memopv8i64, vselect, v8i64>,
665 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
667 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
668 (v16i32 VR512:$src2), (i16 GR16:$mask))),
669 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
670 VR512:$src1, VR512:$src2)>;
672 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
673 (v8i64 VR512:$src2), (i8 GR8:$mask))),
674 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
675 VR512:$src1, VR512:$src2)>;
677 let Predicates = [HasAVX512] in {
678 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
679 (v8f32 VR256X:$src2))),
681 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
682 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
683 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
685 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
686 (v8i32 VR256X:$src2))),
688 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
689 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
690 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
692 //===----------------------------------------------------------------------===//
693 // Compare Instructions
694 //===----------------------------------------------------------------------===//
696 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
697 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
698 Operand CC, SDNode OpNode, ValueType VT,
699 PatFrag ld_frag, string asm, string asm_alt> {
700 def rr : AVX512Ii8<0xC2, MRMSrcReg,
701 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
702 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
703 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
704 def rm : AVX512Ii8<0xC2, MRMSrcMem,
705 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
706 [(set VK1:$dst, (OpNode (VT RC:$src1),
707 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
708 let isAsmParserOnly = 1, hasSideEffects = 0 in {
709 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
711 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
712 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
713 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
714 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
718 let Predicates = [HasAVX512] in {
719 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
720 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
721 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
724 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
725 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
729 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
730 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
731 SDNode OpNode, ValueType vt> {
732 def rr : AVX512BI<opc, MRMSrcReg,
733 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
734 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
735 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
736 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
737 def rm : AVX512BI<opc, MRMSrcMem,
738 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
739 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
740 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
741 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
744 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
745 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
746 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
747 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
749 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
750 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
751 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
752 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
754 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
755 (COPY_TO_REGCLASS (VPCMPGTDZrr
756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
757 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
759 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
760 (COPY_TO_REGCLASS (VPCMPEQDZrr
761 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
762 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
764 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
765 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
766 SDNode OpNode, ValueType vt, Operand CC, string asm,
768 def rri : AVX512AIi8<opc, MRMSrcReg,
769 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
770 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
771 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
772 def rmi : AVX512AIi8<opc, MRMSrcMem,
773 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
774 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
775 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
776 // Accept explicit immediate argument form instead of comparison code.
777 let isAsmParserOnly = 1, hasSideEffects = 0 in {
778 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
779 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
780 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
781 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
782 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
783 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
787 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
788 X86cmpm, v16i32, AVXCC,
789 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
790 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
791 EVEX_V512, EVEX_CD8<32, CD8VF>;
792 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
793 X86cmpmu, v16i32, AVXCC,
794 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
796 EVEX_V512, EVEX_CD8<32, CD8VF>;
798 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
799 X86cmpm, v8i64, AVXCC,
800 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
801 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
802 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
803 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
804 X86cmpmu, v8i64, AVXCC,
805 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
806 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
807 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
809 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
810 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
811 X86MemOperand x86memop, ValueType vt,
812 string suffix, Domain d> {
813 def rri : AVX512PIi8<0xC2, MRMSrcReg,
814 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
815 !strconcat("vcmp${cc}", suffix,
816 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
817 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
818 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
819 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
820 !strconcat("vcmp${cc}", suffix,
821 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
823 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
824 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
825 !strconcat("vcmp", suffix,
826 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
828 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
830 // Accept explicit immediate argument form instead of comparison code.
831 let isAsmParserOnly = 1, hasSideEffects = 0 in {
832 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
833 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
834 !strconcat("vcmp", suffix,
835 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
836 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
837 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
838 !strconcat("vcmp", suffix,
839 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
843 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
844 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
845 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
846 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
849 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
850 (COPY_TO_REGCLASS (VCMPPSZrri
851 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
852 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
854 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
855 (COPY_TO_REGCLASS (VPCMPDZrri
856 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
857 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
859 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
860 (COPY_TO_REGCLASS (VPCMPUDZrri
861 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
862 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
865 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
866 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
868 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
869 (I8Imm imm:$cc)), GR16)>;
871 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
872 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
874 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
875 (I8Imm imm:$cc)), GR8)>;
877 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
878 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
880 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
881 (I8Imm imm:$cc)), GR16)>;
883 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
884 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
886 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
887 (I8Imm imm:$cc)), GR8)>;
889 // Mask register copy, including
890 // - copy between mask registers
891 // - load/store mask registers
892 // - copy from GPR to mask register and vice versa
894 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
895 string OpcodeStr, RegisterClass KRC,
896 ValueType vt, X86MemOperand x86memop> {
897 let hasSideEffects = 0 in {
898 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
899 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
901 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
902 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
903 [(set KRC:$dst, (vt (load addr:$src)))]>;
905 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
906 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
910 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
912 RegisterClass KRC, RegisterClass GRC> {
913 let hasSideEffects = 0 in {
914 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
915 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
916 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
917 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
921 let Predicates = [HasAVX512] in {
922 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
924 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
928 let Predicates = [HasAVX512] in {
929 // GR16 from/to 16-bit mask
930 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
931 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
932 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
933 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
935 // Store kreg in memory
936 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
937 (KMOVWmk addr:$dst, VK16:$src)>;
939 def : Pat<(store VK8:$src, addr:$dst),
940 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
942 def : Pat<(i1 (load addr:$src)),
943 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
945 def : Pat<(v8i1 (load addr:$src)),
946 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
948 def : Pat<(i1 (trunc (i32 GR32:$src))),
949 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
951 def : Pat<(i1 (trunc (i8 GR8:$src))),
953 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
955 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
956 def : Pat<(i8 (zext VK1:$src)),
958 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
959 def : Pat<(i64 (zext VK1:$src)),
960 (SUBREG_TO_REG (i64 0),
961 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
964 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
965 let Predicates = [HasAVX512] in {
966 // GR from/to 8-bit mask without native support
967 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
969 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
971 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
973 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
976 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
977 (COPY_TO_REGCLASS VK16:$src, VK1)>;
978 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
979 (COPY_TO_REGCLASS VK8:$src, VK1)>;
983 // Mask unary operation
985 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
986 RegisterClass KRC, SDPatternOperator OpNode> {
987 let Predicates = [HasAVX512] in
988 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
990 [(set KRC:$dst, (OpNode KRC:$src))]>;
993 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
994 SDPatternOperator OpNode> {
995 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
999 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1001 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1002 let Predicates = [HasAVX512] in
1003 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1005 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1006 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1008 defm : avx512_mask_unop_int<"knot", "KNOT">;
1010 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1011 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1012 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1014 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1015 def : Pat<(not VK8:$src),
1017 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1019 // Mask binary operation
1020 // - KAND, KANDN, KOR, KXNOR, KXOR
1021 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1022 RegisterClass KRC, SDPatternOperator OpNode> {
1023 let Predicates = [HasAVX512] in
1024 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1025 !strconcat(OpcodeStr,
1026 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1027 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1030 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1031 SDPatternOperator OpNode> {
1032 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1036 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1037 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1039 let isCommutable = 1 in {
1040 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1041 let isCommutable = 0 in
1042 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1043 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1044 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1045 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1048 def : Pat<(xor VK1:$src1, VK1:$src2),
1049 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1050 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1052 def : Pat<(or VK1:$src1, VK1:$src2),
1053 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1054 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1056 def : Pat<(not VK1:$src),
1057 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1058 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1059 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1061 def : Pat<(and VK1:$src1, VK1:$src2),
1062 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1063 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1065 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1066 let Predicates = [HasAVX512] in
1067 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1068 (i16 GR16:$src1), (i16 GR16:$src2)),
1069 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1070 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1071 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1074 defm : avx512_mask_binop_int<"kand", "KAND">;
1075 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1076 defm : avx512_mask_binop_int<"kor", "KOR">;
1077 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1078 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1080 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1081 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1082 let Predicates = [HasAVX512] in
1083 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1085 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1086 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1089 defm : avx512_binop_pat<and, KANDWrr>;
1090 defm : avx512_binop_pat<andn, KANDNWrr>;
1091 defm : avx512_binop_pat<or, KORWrr>;
1092 defm : avx512_binop_pat<xnor, KXNORWrr>;
1093 defm : avx512_binop_pat<xor, KXORWrr>;
1096 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1097 RegisterClass KRC> {
1098 let Predicates = [HasAVX512] in
1099 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1100 !strconcat(OpcodeStr,
1101 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1104 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1105 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1109 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1110 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1111 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1112 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1115 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1116 let Predicates = [HasAVX512] in
1117 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1118 (i16 GR16:$src1), (i16 GR16:$src2)),
1119 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1120 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1121 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1123 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1126 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1128 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1129 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1130 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1131 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1134 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1135 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1139 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1141 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1142 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1143 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1146 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1148 let Predicates = [HasAVX512] in
1149 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1150 !strconcat(OpcodeStr,
1151 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1152 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1155 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1157 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1161 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1162 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1164 // Mask setting all 0s or 1s
1165 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1166 let Predicates = [HasAVX512] in
1167 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1168 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1169 [(set KRC:$dst, (VT Val))]>;
1172 multiclass avx512_mask_setop_w<PatFrag Val> {
1173 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1174 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1177 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1178 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1180 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1181 let Predicates = [HasAVX512] in {
1182 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1183 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1184 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1185 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1186 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1188 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1189 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1191 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1192 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1194 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1195 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1197 //===----------------------------------------------------------------------===//
1198 // AVX-512 - Aligned and unaligned load and store
1201 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1202 X86MemOperand x86memop, PatFrag ld_frag,
1203 string asm, Domain d> {
1204 let hasSideEffects = 0 in
1205 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1206 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1208 let canFoldAsLoad = 1 in
1209 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1210 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1211 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1212 let Constraints = "$src1 = $dst" in {
1213 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1214 (ins RC:$src1, KRC:$mask, RC:$src2),
1216 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1218 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1219 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1221 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1222 [], d>, EVEX, EVEX_K;
1226 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1227 "vmovaps", SSEPackedSingle>,
1228 EVEX_V512, EVEX_CD8<32, CD8VF>;
1229 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1230 "vmovapd", SSEPackedDouble>,
1231 PD, EVEX_V512, VEX_W,
1232 EVEX_CD8<64, CD8VF>;
1233 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1234 "vmovups", SSEPackedSingle>,
1235 EVEX_V512, EVEX_CD8<32, CD8VF>;
1236 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1237 "vmovupd", SSEPackedDouble>,
1238 PD, EVEX_V512, VEX_W,
1239 EVEX_CD8<64, CD8VF>;
1240 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1241 "vmovaps\t{$src, $dst|$dst, $src}",
1242 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1243 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1244 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1245 "vmovapd\t{$src, $dst|$dst, $src}",
1246 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1247 SSEPackedDouble>, EVEX, EVEX_V512,
1248 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1249 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1250 "vmovups\t{$src, $dst|$dst, $src}",
1251 [(store (v16f32 VR512:$src), addr:$dst)],
1252 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1253 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1254 "vmovupd\t{$src, $dst|$dst, $src}",
1255 [(store (v8f64 VR512:$src), addr:$dst)],
1256 SSEPackedDouble>, EVEX, EVEX_V512,
1257 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1259 let hasSideEffects = 0 in {
1260 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1262 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1264 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1266 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1267 EVEX, EVEX_V512, VEX_W;
1268 let mayStore = 1 in {
1269 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1270 (ins i512mem:$dst, VR512:$src),
1271 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1272 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1273 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1274 (ins i512mem:$dst, VR512:$src),
1275 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1276 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1278 let mayLoad = 1 in {
1279 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1281 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1282 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1283 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1285 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1286 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1290 // 512-bit aligned load/store
1291 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1292 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1294 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1295 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1296 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1297 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1299 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1300 RegisterClass RC, RegisterClass KRC,
1301 PatFrag ld_frag, X86MemOperand x86memop> {
1302 let hasSideEffects = 0 in
1303 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1304 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1305 let canFoldAsLoad = 1 in
1306 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1307 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1308 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1310 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1311 (ins x86memop:$dst, VR512:$src),
1312 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1313 let Constraints = "$src1 = $dst" in {
1314 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1315 (ins RC:$src1, KRC:$mask, RC:$src2),
1317 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1319 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1320 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1322 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1327 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1328 memopv16i32, i512mem>,
1329 EVEX_V512, EVEX_CD8<32, CD8VF>;
1330 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1331 memopv8i64, i512mem>,
1332 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1334 // 512-bit unaligned load/store
1335 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1336 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1338 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1339 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1340 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1341 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1343 let AddedComplexity = 20 in {
1344 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1345 (v16f32 VR512:$src2))),
1346 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1347 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1348 (v8f64 VR512:$src2))),
1349 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1350 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1351 (v16i32 VR512:$src2))),
1352 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1353 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1354 (v8i64 VR512:$src2))),
1355 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1357 // Move Int Doubleword to Packed Double Int
1359 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1360 "vmovd\t{$src, $dst|$dst, $src}",
1362 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1364 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1365 "vmovd\t{$src, $dst|$dst, $src}",
1367 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1368 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1369 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1370 "vmovq\t{$src, $dst|$dst, $src}",
1372 (v2i64 (scalar_to_vector GR64:$src)))],
1373 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1374 let isCodeGenOnly = 1 in {
1375 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1376 "vmovq\t{$src, $dst|$dst, $src}",
1377 [(set FR64:$dst, (bitconvert GR64:$src))],
1378 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1379 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1380 "vmovq\t{$src, $dst|$dst, $src}",
1381 [(set GR64:$dst, (bitconvert FR64:$src))],
1382 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1384 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1385 "vmovq\t{$src, $dst|$dst, $src}",
1386 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1387 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1388 EVEX_CD8<64, CD8VT1>;
1390 // Move Int Doubleword to Single Scalar
1392 let isCodeGenOnly = 1 in {
1393 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1394 "vmovd\t{$src, $dst|$dst, $src}",
1395 [(set FR32X:$dst, (bitconvert GR32:$src))],
1396 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1398 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1399 "vmovd\t{$src, $dst|$dst, $src}",
1400 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1401 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1404 // Move doubleword from xmm register to r/m32
1406 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1407 "vmovd\t{$src, $dst|$dst, $src}",
1408 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1409 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1411 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1412 (ins i32mem:$dst, VR128X:$src),
1413 "vmovd\t{$src, $dst|$dst, $src}",
1414 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1415 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1416 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1418 // Move quadword from xmm1 register to r/m64
1420 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1421 "vmovq\t{$src, $dst|$dst, $src}",
1422 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1424 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1425 Requires<[HasAVX512, In64BitMode]>;
1427 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1428 (ins i64mem:$dst, VR128X:$src),
1429 "vmovq\t{$src, $dst|$dst, $src}",
1430 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1431 addr:$dst)], IIC_SSE_MOVDQ>,
1432 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1433 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1435 // Move Scalar Single to Double Int
1437 let isCodeGenOnly = 1 in {
1438 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1440 "vmovd\t{$src, $dst|$dst, $src}",
1441 [(set GR32:$dst, (bitconvert FR32X:$src))],
1442 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1443 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1444 (ins i32mem:$dst, FR32X:$src),
1445 "vmovd\t{$src, $dst|$dst, $src}",
1446 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1447 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1450 // Move Quadword Int to Packed Quadword Int
1452 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1454 "vmovq\t{$src, $dst|$dst, $src}",
1456 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1457 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1459 //===----------------------------------------------------------------------===//
1460 // AVX-512 MOVSS, MOVSD
1461 //===----------------------------------------------------------------------===//
1463 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1464 SDNode OpNode, ValueType vt,
1465 X86MemOperand x86memop, PatFrag mem_pat> {
1466 let hasSideEffects = 0 in {
1467 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1468 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1469 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1470 (scalar_to_vector RC:$src2))))],
1471 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1472 let Constraints = "$src1 = $dst" in
1473 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1474 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1476 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1477 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1478 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1479 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1480 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1482 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1483 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1484 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1486 } //hasSideEffects = 0
1489 let ExeDomain = SSEPackedSingle in
1490 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1491 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1493 let ExeDomain = SSEPackedDouble in
1494 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1495 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1497 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1498 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1499 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1501 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1502 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1503 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1505 // For the disassembler
1506 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1507 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1508 (ins VR128X:$src1, FR32X:$src2),
1509 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1511 XS, EVEX_4V, VEX_LIG;
1512 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1513 (ins VR128X:$src1, FR64X:$src2),
1514 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1516 XD, EVEX_4V, VEX_LIG, VEX_W;
1519 let Predicates = [HasAVX512] in {
1520 let AddedComplexity = 15 in {
1521 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1522 // MOVS{S,D} to the lower bits.
1523 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1524 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1525 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1526 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1527 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1528 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1529 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1530 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1532 // Move low f32 and clear high bits.
1533 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1534 (SUBREG_TO_REG (i32 0),
1535 (VMOVSSZrr (v4f32 (V_SET0)),
1536 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1537 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1538 (SUBREG_TO_REG (i32 0),
1539 (VMOVSSZrr (v4i32 (V_SET0)),
1540 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1543 let AddedComplexity = 20 in {
1544 // MOVSSrm zeros the high parts of the register; represent this
1545 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1546 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1547 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1548 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1549 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1550 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1551 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1553 // MOVSDrm zeros the high parts of the register; represent this
1554 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1555 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1556 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1557 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1558 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1559 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1560 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1561 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1562 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1563 def : Pat<(v2f64 (X86vzload addr:$src)),
1564 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1566 // Represent the same patterns above but in the form they appear for
1568 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1569 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1570 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1571 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1572 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1573 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1574 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1575 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1576 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1578 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1579 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1580 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1581 FR32X:$src)), sub_xmm)>;
1582 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1583 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1584 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1585 FR64X:$src)), sub_xmm)>;
1586 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1587 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1588 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1590 // Move low f64 and clear high bits.
1591 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1592 (SUBREG_TO_REG (i32 0),
1593 (VMOVSDZrr (v2f64 (V_SET0)),
1594 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1596 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1597 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1598 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1600 // Extract and store.
1601 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1603 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1604 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1606 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1608 // Shuffle with VMOVSS
1609 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1610 (VMOVSSZrr (v4i32 VR128X:$src1),
1611 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1612 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1613 (VMOVSSZrr (v4f32 VR128X:$src1),
1614 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1617 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1618 (SUBREG_TO_REG (i32 0),
1619 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1620 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1622 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1623 (SUBREG_TO_REG (i32 0),
1624 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1625 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1628 // Shuffle with VMOVSD
1629 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1630 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1631 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1632 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1633 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1634 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1635 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1636 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1639 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1640 (SUBREG_TO_REG (i32 0),
1641 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1642 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1644 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1645 (SUBREG_TO_REG (i32 0),
1646 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1647 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1650 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1651 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1652 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1653 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1654 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1655 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1656 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1657 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1660 let AddedComplexity = 15 in
1661 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1663 "vmovq\t{$src, $dst|$dst, $src}",
1664 [(set VR128X:$dst, (v2i64 (X86vzmovl
1665 (v2i64 VR128X:$src))))],
1666 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1668 let AddedComplexity = 20 in
1669 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1671 "vmovq\t{$src, $dst|$dst, $src}",
1672 [(set VR128X:$dst, (v2i64 (X86vzmovl
1673 (loadv2i64 addr:$src))))],
1674 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1675 EVEX_CD8<8, CD8VT8>;
1677 let Predicates = [HasAVX512] in {
1678 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1679 let AddedComplexity = 20 in {
1680 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1681 (VMOVDI2PDIZrm addr:$src)>;
1682 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1683 (VMOV64toPQIZrr GR64:$src)>;
1684 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1685 (VMOVDI2PDIZrr GR32:$src)>;
1687 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1688 (VMOVDI2PDIZrm addr:$src)>;
1689 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1690 (VMOVDI2PDIZrm addr:$src)>;
1691 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1692 (VMOVZPQILo2PQIZrm addr:$src)>;
1693 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1694 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1695 def : Pat<(v2i64 (X86vzload addr:$src)),
1696 (VMOVZPQILo2PQIZrm addr:$src)>;
1699 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1700 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1701 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1702 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1703 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1704 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1705 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1708 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1709 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1711 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1712 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1714 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1715 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1717 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1718 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1720 //===----------------------------------------------------------------------===//
1721 // AVX-512 - Integer arithmetic
1723 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1724 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1725 X86MemOperand x86memop, PatFrag scalar_mfrag,
1726 X86MemOperand x86scalar_mop, string BrdcstStr,
1727 OpndItins itins, bit IsCommutable = 0> {
1728 let isCommutable = IsCommutable in
1729 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1730 (ins RC:$src1, RC:$src2),
1731 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1732 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1734 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1735 (ins RC:$src1, x86memop:$src2),
1736 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1737 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1739 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1740 (ins RC:$src1, x86scalar_mop:$src2),
1741 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1742 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1743 [(set RC:$dst, (OpNode RC:$src1,
1744 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1745 itins.rm>, EVEX_4V, EVEX_B;
1747 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1748 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1749 PatFrag memop_frag, X86MemOperand x86memop,
1751 bit IsCommutable = 0> {
1752 let isCommutable = IsCommutable in
1753 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1754 (ins RC:$src1, RC:$src2),
1755 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1756 []>, EVEX_4V, VEX_W;
1757 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1758 (ins RC:$src1, x86memop:$src2),
1759 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1760 []>, EVEX_4V, VEX_W;
1763 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1764 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1765 EVEX_V512, EVEX_CD8<32, CD8VF>;
1767 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1768 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1769 EVEX_V512, EVEX_CD8<32, CD8VF>;
1771 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1772 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1773 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1775 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1776 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1777 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1779 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1780 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1781 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1783 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1784 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1785 EVEX_V512, EVEX_CD8<64, CD8VF>;
1787 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1788 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1789 EVEX_CD8<64, CD8VF>;
1791 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1792 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1794 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1795 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1796 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1797 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1798 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1799 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1801 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1802 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1803 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1804 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1805 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1806 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1808 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1809 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1810 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1811 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1812 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1813 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1815 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1816 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1817 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1818 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1819 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1820 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1822 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1823 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1824 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1825 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1826 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1827 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1829 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1830 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1831 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1832 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1833 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1834 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1835 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1836 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1837 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1838 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1839 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1840 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1841 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1842 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1843 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1844 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1845 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1846 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1847 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1848 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1849 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1850 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1851 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1852 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1853 //===----------------------------------------------------------------------===//
1854 // AVX-512 - Unpack Instructions
1855 //===----------------------------------------------------------------------===//
1857 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1858 PatFrag mem_frag, RegisterClass RC,
1859 X86MemOperand x86memop, string asm,
1861 def rr : AVX512PI<opc, MRMSrcReg,
1862 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1864 (vt (OpNode RC:$src1, RC:$src2)))],
1866 def rm : AVX512PI<opc, MRMSrcMem,
1867 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1869 (vt (OpNode RC:$src1,
1870 (bitconvert (mem_frag addr:$src2)))))],
1874 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1875 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1876 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1877 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1878 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1879 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1880 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1881 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1882 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1883 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1884 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1885 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1887 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1888 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1889 X86MemOperand x86memop> {
1890 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1891 (ins RC:$src1, RC:$src2),
1892 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1893 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1894 IIC_SSE_UNPCK>, EVEX_4V;
1895 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1896 (ins RC:$src1, x86memop:$src2),
1897 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1898 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1899 (bitconvert (memop_frag addr:$src2)))))],
1900 IIC_SSE_UNPCK>, EVEX_4V;
1902 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1903 VR512, memopv16i32, i512mem>, EVEX_V512,
1904 EVEX_CD8<32, CD8VF>;
1905 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1906 VR512, memopv8i64, i512mem>, EVEX_V512,
1907 VEX_W, EVEX_CD8<64, CD8VF>;
1908 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1909 VR512, memopv16i32, i512mem>, EVEX_V512,
1910 EVEX_CD8<32, CD8VF>;
1911 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1912 VR512, memopv8i64, i512mem>, EVEX_V512,
1913 VEX_W, EVEX_CD8<64, CD8VF>;
1914 //===----------------------------------------------------------------------===//
1918 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1919 SDNode OpNode, PatFrag mem_frag,
1920 X86MemOperand x86memop, ValueType OpVT> {
1921 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1922 (ins RC:$src1, i8imm:$src2),
1923 !strconcat(OpcodeStr,
1924 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1926 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1928 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1929 (ins x86memop:$src1, i8imm:$src2),
1930 !strconcat(OpcodeStr,
1931 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1933 (OpVT (OpNode (mem_frag addr:$src1),
1934 (i8 imm:$src2))))]>, EVEX;
1937 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1938 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1940 let ExeDomain = SSEPackedSingle in
1941 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1942 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1943 EVEX_CD8<32, CD8VF>;
1944 let ExeDomain = SSEPackedDouble in
1945 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1946 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1947 VEX_W, EVEX_CD8<32, CD8VF>;
1949 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1950 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1951 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1952 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1954 //===----------------------------------------------------------------------===//
1955 // AVX-512 Logical Instructions
1956 //===----------------------------------------------------------------------===//
1958 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1959 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1960 EVEX_V512, EVEX_CD8<32, CD8VF>;
1961 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1962 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1963 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1964 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1965 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1966 EVEX_V512, EVEX_CD8<32, CD8VF>;
1967 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1968 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1969 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1970 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1971 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1972 EVEX_V512, EVEX_CD8<32, CD8VF>;
1973 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1974 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1975 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1976 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1977 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1978 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1979 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1980 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1981 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1983 //===----------------------------------------------------------------------===//
1984 // AVX-512 FP arithmetic
1985 //===----------------------------------------------------------------------===//
1987 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1989 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1990 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1991 EVEX_CD8<32, CD8VT1>;
1992 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1993 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1994 EVEX_CD8<64, CD8VT1>;
1997 let isCommutable = 1 in {
1998 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1999 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2000 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2001 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2003 let isCommutable = 0 in {
2004 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2005 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2008 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2009 RegisterClass RC, ValueType vt,
2010 X86MemOperand x86memop, PatFrag mem_frag,
2011 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2013 Domain d, OpndItins itins, bit commutable> {
2014 let isCommutable = commutable in
2015 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2016 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2017 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2019 let mayLoad = 1 in {
2020 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2021 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2022 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2023 itins.rm, d>, EVEX_4V, TB;
2024 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2025 (ins RC:$src1, x86scalar_mop:$src2),
2026 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2027 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2028 [(set RC:$dst, (OpNode RC:$src1,
2029 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2030 itins.rm, d>, EVEX_4V, EVEX_B, TB;
2034 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2035 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2036 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2038 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2039 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2040 SSE_ALU_ITINS_P.d, 1>,
2041 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2043 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2044 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2045 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2046 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2047 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2048 SSE_ALU_ITINS_P.d, 1>,
2049 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2051 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2052 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2053 SSE_ALU_ITINS_P.s, 1>,
2054 EVEX_V512, EVEX_CD8<32, CD8VF>;
2055 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2056 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2057 SSE_ALU_ITINS_P.s, 1>,
2058 EVEX_V512, EVEX_CD8<32, CD8VF>;
2060 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2061 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2062 SSE_ALU_ITINS_P.d, 1>,
2063 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2064 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2065 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2066 SSE_ALU_ITINS_P.d, 1>,
2067 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2069 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2070 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2071 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2072 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2073 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2074 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2076 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2077 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2078 SSE_ALU_ITINS_P.d, 0>,
2079 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2080 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2081 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2082 SSE_ALU_ITINS_P.d, 0>,
2083 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2085 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2086 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2087 (i16 -1), FROUND_CURRENT)),
2088 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2090 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2091 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2092 (i8 -1), FROUND_CURRENT)),
2093 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2095 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2096 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2097 (i16 -1), FROUND_CURRENT)),
2098 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2100 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2101 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2102 (i8 -1), FROUND_CURRENT)),
2103 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2104 //===----------------------------------------------------------------------===//
2105 // AVX-512 VPTESTM instructions
2106 //===----------------------------------------------------------------------===//
2108 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2109 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2110 SDNode OpNode, ValueType vt> {
2111 def rr : AVX5128I<opc, MRMSrcReg,
2112 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2113 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2114 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2115 def rm : AVX5128I<opc, MRMSrcMem,
2116 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2117 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2118 [(set KRC:$dst, (OpNode (vt RC:$src1),
2119 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2122 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2123 memopv16i32, X86testm, v16i32>, EVEX_V512,
2124 EVEX_CD8<32, CD8VF>;
2125 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2126 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2127 EVEX_CD8<64, CD8VF>;
2129 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2130 (v16i32 VR512:$src2), (i16 -1))),
2131 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2133 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2134 (v8i64 VR512:$src2), (i8 -1))),
2135 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR8)>;
2136 //===----------------------------------------------------------------------===//
2137 // AVX-512 Shift instructions
2138 //===----------------------------------------------------------------------===//
2139 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2140 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2141 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2142 RegisterClass KRC> {
2143 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2144 (ins RC:$src1, i8imm:$src2),
2145 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2146 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2147 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2148 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2149 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2150 !strconcat(OpcodeStr,
2151 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2152 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2153 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2154 (ins x86memop:$src1, i8imm:$src2),
2155 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2156 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2157 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2158 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2159 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2160 !strconcat(OpcodeStr,
2161 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2162 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2165 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2166 RegisterClass RC, ValueType vt, ValueType SrcVT,
2167 PatFrag bc_frag, RegisterClass KRC> {
2168 // src2 is always 128-bit
2169 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2170 (ins RC:$src1, VR128X:$src2),
2171 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2172 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2173 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2174 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2175 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2176 !strconcat(OpcodeStr,
2177 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2178 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2179 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2180 (ins RC:$src1, i128mem:$src2),
2181 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2182 [(set RC:$dst, (vt (OpNode RC:$src1,
2183 (bc_frag (memopv2i64 addr:$src2)))))],
2184 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2185 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2186 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2187 !strconcat(OpcodeStr,
2188 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2189 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2192 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2193 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2194 EVEX_V512, EVEX_CD8<32, CD8VF>;
2195 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2196 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2197 EVEX_CD8<32, CD8VQ>;
2199 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2200 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2201 EVEX_CD8<64, CD8VF>, VEX_W;
2202 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2203 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2204 EVEX_CD8<64, CD8VQ>, VEX_W;
2206 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2207 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2208 EVEX_CD8<32, CD8VF>;
2209 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2210 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2211 EVEX_CD8<32, CD8VQ>;
2213 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2214 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2215 EVEX_CD8<64, CD8VF>, VEX_W;
2216 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2217 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2218 EVEX_CD8<64, CD8VQ>, VEX_W;
2220 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2221 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2222 EVEX_V512, EVEX_CD8<32, CD8VF>;
2223 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2224 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2225 EVEX_CD8<32, CD8VQ>;
2227 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2228 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2229 EVEX_CD8<64, CD8VF>, VEX_W;
2230 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2231 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2232 EVEX_CD8<64, CD8VQ>, VEX_W;
2234 //===-------------------------------------------------------------------===//
2235 // Variable Bit Shifts
2236 //===-------------------------------------------------------------------===//
2237 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2238 RegisterClass RC, ValueType vt,
2239 X86MemOperand x86memop, PatFrag mem_frag> {
2240 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2241 (ins RC:$src1, RC:$src2),
2242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2244 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2246 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2247 (ins RC:$src1, x86memop:$src2),
2248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2250 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2254 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2255 i512mem, memopv16i32>, EVEX_V512,
2256 EVEX_CD8<32, CD8VF>;
2257 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2258 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2259 EVEX_CD8<64, CD8VF>;
2260 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2261 i512mem, memopv16i32>, EVEX_V512,
2262 EVEX_CD8<32, CD8VF>;
2263 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2264 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2265 EVEX_CD8<64, CD8VF>;
2266 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2267 i512mem, memopv16i32>, EVEX_V512,
2268 EVEX_CD8<32, CD8VF>;
2269 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2270 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2271 EVEX_CD8<64, CD8VF>;
2273 //===----------------------------------------------------------------------===//
2274 // AVX-512 - MOVDDUP
2275 //===----------------------------------------------------------------------===//
2277 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2278 X86MemOperand x86memop, PatFrag memop_frag> {
2279 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2280 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2281 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2282 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2283 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2285 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2288 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2289 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2290 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2291 (VMOVDDUPZrm addr:$src)>;
2293 //===---------------------------------------------------------------------===//
2294 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2295 //===---------------------------------------------------------------------===//
2296 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2297 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2298 X86MemOperand x86memop> {
2299 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2300 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2301 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2303 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2304 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2305 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2308 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2309 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2310 EVEX_CD8<32, CD8VF>;
2311 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2312 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2313 EVEX_CD8<32, CD8VF>;
2315 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2316 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2317 (VMOVSHDUPZrm addr:$src)>;
2318 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2319 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2320 (VMOVSLDUPZrm addr:$src)>;
2322 //===----------------------------------------------------------------------===//
2323 // Move Low to High and High to Low packed FP Instructions
2324 //===----------------------------------------------------------------------===//
2325 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2326 (ins VR128X:$src1, VR128X:$src2),
2327 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2328 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2329 IIC_SSE_MOV_LH>, EVEX_4V;
2330 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2331 (ins VR128X:$src1, VR128X:$src2),
2332 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2333 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2334 IIC_SSE_MOV_LH>, EVEX_4V;
2336 let Predicates = [HasAVX512] in {
2338 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2339 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2340 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2341 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2344 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2345 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2348 //===----------------------------------------------------------------------===//
2349 // FMA - Fused Multiply Operations
2351 let Constraints = "$src1 = $dst" in {
2352 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2353 RegisterClass RC, X86MemOperand x86memop,
2354 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2355 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2356 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2357 (ins RC:$src1, RC:$src2, RC:$src3),
2358 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2359 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2362 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2363 (ins RC:$src1, RC:$src2, x86memop:$src3),
2364 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2365 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2366 (mem_frag addr:$src3))))]>;
2367 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2368 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2369 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2370 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2371 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2372 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2374 } // Constraints = "$src1 = $dst"
2376 let ExeDomain = SSEPackedSingle in {
2377 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2378 memopv16f32, f32mem, loadf32, "{1to16}",
2379 X86Fmadd, v16f32>, EVEX_V512,
2380 EVEX_CD8<32, CD8VF>;
2381 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2382 memopv16f32, f32mem, loadf32, "{1to16}",
2383 X86Fmsub, v16f32>, EVEX_V512,
2384 EVEX_CD8<32, CD8VF>;
2385 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2386 memopv16f32, f32mem, loadf32, "{1to16}",
2387 X86Fmaddsub, v16f32>,
2388 EVEX_V512, EVEX_CD8<32, CD8VF>;
2389 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2390 memopv16f32, f32mem, loadf32, "{1to16}",
2391 X86Fmsubadd, v16f32>,
2392 EVEX_V512, EVEX_CD8<32, CD8VF>;
2393 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2394 memopv16f32, f32mem, loadf32, "{1to16}",
2395 X86Fnmadd, v16f32>, EVEX_V512,
2396 EVEX_CD8<32, CD8VF>;
2397 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2398 memopv16f32, f32mem, loadf32, "{1to16}",
2399 X86Fnmsub, v16f32>, EVEX_V512,
2400 EVEX_CD8<32, CD8VF>;
2402 let ExeDomain = SSEPackedDouble in {
2403 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2404 memopv8f64, f64mem, loadf64, "{1to8}",
2405 X86Fmadd, v8f64>, EVEX_V512,
2406 VEX_W, EVEX_CD8<64, CD8VF>;
2407 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2408 memopv8f64, f64mem, loadf64, "{1to8}",
2409 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2410 EVEX_CD8<64, CD8VF>;
2411 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2412 memopv8f64, f64mem, loadf64, "{1to8}",
2413 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2414 EVEX_CD8<64, CD8VF>;
2415 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2416 memopv8f64, f64mem, loadf64, "{1to8}",
2417 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2418 EVEX_CD8<64, CD8VF>;
2419 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2420 memopv8f64, f64mem, loadf64, "{1to8}",
2421 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2422 EVEX_CD8<64, CD8VF>;
2423 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2424 memopv8f64, f64mem, loadf64, "{1to8}",
2425 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2426 EVEX_CD8<64, CD8VF>;
2429 let Constraints = "$src1 = $dst" in {
2430 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2431 RegisterClass RC, X86MemOperand x86memop,
2432 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2433 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2435 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2436 (ins RC:$src1, RC:$src3, x86memop:$src2),
2437 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2438 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2439 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2440 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2441 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2442 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2443 [(set RC:$dst, (OpNode RC:$src1,
2444 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2446 } // Constraints = "$src1 = $dst"
2449 let ExeDomain = SSEPackedSingle in {
2450 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2451 memopv16f32, f32mem, loadf32, "{1to16}",
2452 X86Fmadd, v16f32>, EVEX_V512,
2453 EVEX_CD8<32, CD8VF>;
2454 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2455 memopv16f32, f32mem, loadf32, "{1to16}",
2456 X86Fmsub, v16f32>, EVEX_V512,
2457 EVEX_CD8<32, CD8VF>;
2458 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2459 memopv16f32, f32mem, loadf32, "{1to16}",
2460 X86Fmaddsub, v16f32>,
2461 EVEX_V512, EVEX_CD8<32, CD8VF>;
2462 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2463 memopv16f32, f32mem, loadf32, "{1to16}",
2464 X86Fmsubadd, v16f32>,
2465 EVEX_V512, EVEX_CD8<32, CD8VF>;
2466 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2467 memopv16f32, f32mem, loadf32, "{1to16}",
2468 X86Fnmadd, v16f32>, EVEX_V512,
2469 EVEX_CD8<32, CD8VF>;
2470 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2471 memopv16f32, f32mem, loadf32, "{1to16}",
2472 X86Fnmsub, v16f32>, EVEX_V512,
2473 EVEX_CD8<32, CD8VF>;
2475 let ExeDomain = SSEPackedDouble in {
2476 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2477 memopv8f64, f64mem, loadf64, "{1to8}",
2478 X86Fmadd, v8f64>, EVEX_V512,
2479 VEX_W, EVEX_CD8<64, CD8VF>;
2480 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2481 memopv8f64, f64mem, loadf64, "{1to8}",
2482 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2483 EVEX_CD8<64, CD8VF>;
2484 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2485 memopv8f64, f64mem, loadf64, "{1to8}",
2486 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2487 EVEX_CD8<64, CD8VF>;
2488 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2489 memopv8f64, f64mem, loadf64, "{1to8}",
2490 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2491 EVEX_CD8<64, CD8VF>;
2492 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2493 memopv8f64, f64mem, loadf64, "{1to8}",
2494 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2495 EVEX_CD8<64, CD8VF>;
2496 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2497 memopv8f64, f64mem, loadf64, "{1to8}",
2498 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2499 EVEX_CD8<64, CD8VF>;
2503 let Constraints = "$src1 = $dst" in {
2504 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2505 RegisterClass RC, ValueType OpVT,
2506 X86MemOperand x86memop, Operand memop,
2508 let isCommutable = 1 in
2509 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2510 (ins RC:$src1, RC:$src2, RC:$src3),
2511 !strconcat(OpcodeStr,
2512 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2514 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2516 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2517 (ins RC:$src1, RC:$src2, f128mem:$src3),
2518 !strconcat(OpcodeStr,
2519 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2521 (OpVT (OpNode RC:$src2, RC:$src1,
2522 (mem_frag addr:$src3))))]>;
2525 } // Constraints = "$src1 = $dst"
2527 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2528 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2529 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2530 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2531 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2532 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2533 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2534 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2535 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2536 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2537 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2538 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2539 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2540 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2541 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2542 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2544 //===----------------------------------------------------------------------===//
2545 // AVX-512 Scalar convert from sign integer to float/double
2546 //===----------------------------------------------------------------------===//
2548 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2549 X86MemOperand x86memop, string asm> {
2550 let hasSideEffects = 0 in {
2551 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2552 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2555 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2556 (ins DstRC:$src1, x86memop:$src),
2557 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2559 } // hasSideEffects = 0
2561 let Predicates = [HasAVX512] in {
2562 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2563 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2564 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2565 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2566 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2567 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2568 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2569 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2571 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2572 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2573 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2574 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2575 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2576 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2577 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2578 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2580 def : Pat<(f32 (sint_to_fp GR32:$src)),
2581 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2582 def : Pat<(f32 (sint_to_fp GR64:$src)),
2583 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2584 def : Pat<(f64 (sint_to_fp GR32:$src)),
2585 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2586 def : Pat<(f64 (sint_to_fp GR64:$src)),
2587 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2589 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2590 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2591 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2592 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2593 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2594 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2595 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2596 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2598 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2599 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2600 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2601 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2602 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2603 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2604 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2605 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2607 def : Pat<(f32 (uint_to_fp GR32:$src)),
2608 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2609 def : Pat<(f32 (uint_to_fp GR64:$src)),
2610 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2611 def : Pat<(f64 (uint_to_fp GR32:$src)),
2612 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2613 def : Pat<(f64 (uint_to_fp GR64:$src)),
2614 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2617 //===----------------------------------------------------------------------===//
2618 // AVX-512 Scalar convert from float/double to integer
2619 //===----------------------------------------------------------------------===//
2620 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2621 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2623 let hasSideEffects = 0 in {
2624 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2625 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2626 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2627 Requires<[HasAVX512]>;
2629 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2630 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2631 Requires<[HasAVX512]>;
2632 } // hasSideEffects = 0
2634 let Predicates = [HasAVX512] in {
2635 // Convert float/double to signed/unsigned int 32/64
2636 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2637 ssmem, sse_load_f32, "cvtss2si">,
2638 XS, EVEX_CD8<32, CD8VT1>;
2639 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2640 ssmem, sse_load_f32, "cvtss2si">,
2641 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2642 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2643 ssmem, sse_load_f32, "cvtss2usi">,
2644 XS, EVEX_CD8<32, CD8VT1>;
2645 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2646 int_x86_avx512_cvtss2usi64, ssmem,
2647 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2648 EVEX_CD8<32, CD8VT1>;
2649 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2650 sdmem, sse_load_f64, "cvtsd2si">,
2651 XD, EVEX_CD8<64, CD8VT1>;
2652 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2653 sdmem, sse_load_f64, "cvtsd2si">,
2654 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2655 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2656 sdmem, sse_load_f64, "cvtsd2usi">,
2657 XD, EVEX_CD8<64, CD8VT1>;
2658 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2659 int_x86_avx512_cvtsd2usi64, sdmem,
2660 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2661 EVEX_CD8<64, CD8VT1>;
2663 let isCodeGenOnly = 1 in {
2664 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2665 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2666 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2667 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2668 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2669 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2670 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2671 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2672 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2673 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2674 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2675 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2677 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2678 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2679 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2680 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2681 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2682 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2683 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2684 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2685 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2686 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2687 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2688 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2689 } // isCodeGenOnly = 1
2691 // Convert float/double to signed/unsigned int 32/64 with truncation
2692 let isCodeGenOnly = 1 in {
2693 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2694 ssmem, sse_load_f32, "cvttss2si">,
2695 XS, EVEX_CD8<32, CD8VT1>;
2696 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2697 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2698 "cvttss2si">, XS, VEX_W,
2699 EVEX_CD8<32, CD8VT1>;
2700 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2701 sdmem, sse_load_f64, "cvttsd2si">, XD,
2702 EVEX_CD8<64, CD8VT1>;
2703 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2704 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2705 "cvttsd2si">, XD, VEX_W,
2706 EVEX_CD8<64, CD8VT1>;
2707 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2708 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2709 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2710 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2711 int_x86_avx512_cvttss2usi64, ssmem,
2712 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2713 EVEX_CD8<32, CD8VT1>;
2714 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2715 int_x86_avx512_cvttsd2usi,
2716 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2717 EVEX_CD8<64, CD8VT1>;
2718 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2719 int_x86_avx512_cvttsd2usi64, sdmem,
2720 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2721 EVEX_CD8<64, CD8VT1>;
2722 } // isCodeGenOnly = 1
2724 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2725 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2727 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2728 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2729 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2730 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2731 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2732 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2735 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2736 loadf32, "cvttss2si">, XS,
2737 EVEX_CD8<32, CD8VT1>;
2738 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2739 loadf32, "cvttss2usi">, XS,
2740 EVEX_CD8<32, CD8VT1>;
2741 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2742 loadf32, "cvttss2si">, XS, VEX_W,
2743 EVEX_CD8<32, CD8VT1>;
2744 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2745 loadf32, "cvttss2usi">, XS, VEX_W,
2746 EVEX_CD8<32, CD8VT1>;
2747 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2748 loadf64, "cvttsd2si">, XD,
2749 EVEX_CD8<64, CD8VT1>;
2750 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2751 loadf64, "cvttsd2usi">, XD,
2752 EVEX_CD8<64, CD8VT1>;
2753 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2754 loadf64, "cvttsd2si">, XD, VEX_W,
2755 EVEX_CD8<64, CD8VT1>;
2756 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2757 loadf64, "cvttsd2usi">, XD, VEX_W,
2758 EVEX_CD8<64, CD8VT1>;
2760 //===----------------------------------------------------------------------===//
2761 // AVX-512 Convert form float to double and back
2762 //===----------------------------------------------------------------------===//
2763 let hasSideEffects = 0 in {
2764 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2765 (ins FR32X:$src1, FR32X:$src2),
2766 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2767 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2769 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2770 (ins FR32X:$src1, f32mem:$src2),
2771 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2772 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2773 EVEX_CD8<32, CD8VT1>;
2775 // Convert scalar double to scalar single
2776 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2777 (ins FR64X:$src1, FR64X:$src2),
2778 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2779 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2781 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2782 (ins FR64X:$src1, f64mem:$src2),
2783 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2784 []>, EVEX_4V, VEX_LIG, VEX_W,
2785 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2788 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2789 Requires<[HasAVX512]>;
2790 def : Pat<(fextend (loadf32 addr:$src)),
2791 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2793 def : Pat<(extloadf32 addr:$src),
2794 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2795 Requires<[HasAVX512, OptForSize]>;
2797 def : Pat<(extloadf32 addr:$src),
2798 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2799 Requires<[HasAVX512, OptForSpeed]>;
2801 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2802 Requires<[HasAVX512]>;
2804 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2805 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2806 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2808 let hasSideEffects = 0 in {
2809 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2810 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2812 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2813 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2814 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2815 [], d>, EVEX, EVEX_B, EVEX_RC;
2817 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2818 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2820 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2821 } // hasSideEffects = 0
2824 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2825 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2826 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2828 let hasSideEffects = 0 in {
2829 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2830 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2832 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2834 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2835 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2837 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2838 } // hasSideEffects = 0
2841 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2842 memopv8f64, f512mem, v8f32, v8f64,
2843 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2844 EVEX_CD8<64, CD8VF>;
2846 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2847 memopv4f64, f256mem, v8f64, v8f32,
2848 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2849 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2850 (VCVTPS2PDZrm addr:$src)>;
2852 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2853 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2854 (VCVTPD2PSZrr VR512:$src)>;
2856 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2857 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2858 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2860 //===----------------------------------------------------------------------===//
2861 // AVX-512 Vector convert from sign integer to float/double
2862 //===----------------------------------------------------------------------===//
2864 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2865 memopv8i64, i512mem, v16f32, v16i32,
2866 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2868 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2869 memopv4i64, i256mem, v8f64, v8i32,
2870 SSEPackedDouble>, EVEX_V512, XS,
2871 EVEX_CD8<32, CD8VH>;
2873 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2874 memopv16f32, f512mem, v16i32, v16f32,
2875 SSEPackedSingle>, EVEX_V512, XS,
2876 EVEX_CD8<32, CD8VF>;
2878 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2879 memopv8f64, f512mem, v8i32, v8f64,
2880 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2881 EVEX_CD8<64, CD8VF>;
2883 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2884 memopv16f32, f512mem, v16i32, v16f32,
2885 SSEPackedSingle>, EVEX_V512,
2886 EVEX_CD8<32, CD8VF>;
2888 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2889 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2890 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2891 (VCVTTPS2UDQZrr VR512:$src)>;
2893 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2894 memopv8f64, f512mem, v8i32, v8f64,
2895 SSEPackedDouble>, EVEX_V512, VEX_W,
2896 EVEX_CD8<64, CD8VF>;
2898 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2899 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2900 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2901 (VCVTTPD2UDQZrr VR512:$src)>;
2903 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2904 memopv4i64, f256mem, v8f64, v8i32,
2905 SSEPackedDouble>, EVEX_V512, XS,
2906 EVEX_CD8<32, CD8VH>;
2908 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2909 memopv16i32, f512mem, v16f32, v16i32,
2910 SSEPackedSingle>, EVEX_V512, XD,
2911 EVEX_CD8<32, CD8VF>;
2913 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2914 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2915 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2918 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2919 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2920 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2921 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2922 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2923 (VCVTDQ2PDZrr VR256X:$src)>;
2924 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2925 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2926 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2927 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2928 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2929 (VCVTUDQ2PDZrr VR256X:$src)>;
2931 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2932 RegisterClass DstRC, PatFrag mem_frag,
2933 X86MemOperand x86memop, Domain d> {
2934 let hasSideEffects = 0 in {
2935 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2936 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2938 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2939 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2940 [], d>, EVEX, EVEX_B, EVEX_RC;
2942 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2943 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2945 } // hasSideEffects = 0
2948 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2949 memopv16f32, f512mem, SSEPackedSingle>, PD,
2950 EVEX_V512, EVEX_CD8<32, CD8VF>;
2951 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2952 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2953 EVEX_V512, EVEX_CD8<64, CD8VF>;
2955 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2956 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2957 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2959 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2960 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2961 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2963 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2964 memopv16f32, f512mem, SSEPackedSingle>,
2965 EVEX_V512, EVEX_CD8<32, CD8VF>;
2966 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2967 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2968 EVEX_V512, EVEX_CD8<64, CD8VF>;
2970 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2971 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2972 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2974 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2975 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2976 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2978 let Predicates = [HasAVX512] in {
2979 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2980 (VCVTPD2PSZrm addr:$src)>;
2981 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2982 (VCVTPS2PDZrm addr:$src)>;
2985 //===----------------------------------------------------------------------===//
2986 // Half precision conversion instructions
2987 //===----------------------------------------------------------------------===//
2988 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2989 X86MemOperand x86memop, Intrinsic Int> {
2990 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2991 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2992 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2993 let hasSideEffects = 0, mayLoad = 1 in
2994 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2995 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2998 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2999 X86MemOperand x86memop, Intrinsic Int> {
3000 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3001 (ins srcRC:$src1, i32i8imm:$src2),
3002 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3003 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
3004 let hasSideEffects = 0, mayStore = 1 in
3005 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3006 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3007 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3010 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
3011 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
3012 EVEX_CD8<32, CD8VH>;
3013 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
3014 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
3015 EVEX_CD8<32, CD8VH>;
3017 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3018 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3019 "ucomiss">, TB, EVEX, VEX_LIG,
3020 EVEX_CD8<32, CD8VT1>;
3021 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3022 "ucomisd">, PD, EVEX,
3023 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3024 let Pattern = []<dag> in {
3025 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3026 "comiss">, TB, EVEX, VEX_LIG,
3027 EVEX_CD8<32, CD8VT1>;
3028 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3029 "comisd">, PD, EVEX,
3030 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3032 let isCodeGenOnly = 1 in {
3033 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3034 load, "ucomiss">, TB, EVEX, VEX_LIG,
3035 EVEX_CD8<32, CD8VT1>;
3036 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3037 load, "ucomisd">, PD, EVEX,
3038 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3040 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3041 load, "comiss">, TB, EVEX, VEX_LIG,
3042 EVEX_CD8<32, CD8VT1>;
3043 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3044 load, "comisd">, PD, EVEX,
3045 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3049 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3050 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3051 X86MemOperand x86memop> {
3052 let hasSideEffects = 0 in {
3053 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3054 (ins RC:$src1, RC:$src2),
3055 !strconcat(OpcodeStr,
3056 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3057 let mayLoad = 1 in {
3058 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3059 (ins RC:$src1, x86memop:$src2),
3060 !strconcat(OpcodeStr,
3061 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3066 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3067 EVEX_CD8<32, CD8VT1>;
3068 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3069 VEX_W, EVEX_CD8<64, CD8VT1>;
3070 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3071 EVEX_CD8<32, CD8VT1>;
3072 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3073 VEX_W, EVEX_CD8<64, CD8VT1>;
3075 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3076 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3077 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3078 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3080 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3081 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3082 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3083 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3085 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3086 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3087 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3088 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3090 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3091 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3092 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3093 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3095 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3096 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3097 RegisterClass RC, X86MemOperand x86memop,
3098 PatFrag mem_frag, ValueType OpVt> {
3099 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3100 !strconcat(OpcodeStr,
3101 "\t{$src, $dst|$dst, $src}"),
3102 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3104 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3106 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3109 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3110 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3111 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3112 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3113 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3114 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3115 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3116 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3118 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3119 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3120 (VRSQRT14PSZr VR512:$src)>;
3121 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3122 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3123 (VRSQRT14PDZr VR512:$src)>;
3125 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3126 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3127 (VRCP14PSZr VR512:$src)>;
3128 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3129 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3130 (VRCP14PDZr VR512:$src)>;
3132 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3133 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3134 X86MemOperand x86memop> {
3135 let hasSideEffects = 0, Predicates = [HasERI] in {
3136 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3137 (ins RC:$src1, RC:$src2),
3138 !strconcat(OpcodeStr,
3139 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3140 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3141 (ins RC:$src1, RC:$src2),
3142 !strconcat(OpcodeStr,
3143 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3144 []>, EVEX_4V, EVEX_B;
3145 let mayLoad = 1 in {
3146 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3147 (ins RC:$src1, x86memop:$src2),
3148 !strconcat(OpcodeStr,
3149 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3154 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3155 EVEX_CD8<32, CD8VT1>;
3156 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3157 VEX_W, EVEX_CD8<64, CD8VT1>;
3158 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3159 EVEX_CD8<32, CD8VT1>;
3160 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3161 VEX_W, EVEX_CD8<64, CD8VT1>;
3163 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3164 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3166 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3167 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3169 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3170 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3172 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3173 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3175 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3176 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3178 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3179 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3181 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3182 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3184 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3185 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3187 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3188 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3189 RegisterClass RC, X86MemOperand x86memop> {
3190 let hasSideEffects = 0, Predicates = [HasERI] in {
3191 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3192 !strconcat(OpcodeStr,
3193 "\t{$src, $dst|$dst, $src}"),
3195 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3196 !strconcat(OpcodeStr,
3197 "\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3199 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3200 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3204 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3205 EVEX_V512, EVEX_CD8<32, CD8VF>;
3206 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3207 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3208 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3209 EVEX_V512, EVEX_CD8<32, CD8VF>;
3210 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3211 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3213 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3214 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3215 (VRSQRT28PSZrb VR512:$src)>;
3216 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3217 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3218 (VRSQRT28PDZrb VR512:$src)>;
3220 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3221 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3222 (VRCP28PSZrb VR512:$src)>;
3223 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3224 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3225 (VRCP28PDZrb VR512:$src)>;
3227 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3228 Intrinsic V16F32Int, Intrinsic V8F64Int,
3229 OpndItins itins_s, OpndItins itins_d> {
3230 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3231 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3232 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3236 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3237 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3239 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3240 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3242 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3243 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3244 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3248 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3249 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3250 [(set VR512:$dst, (OpNode
3251 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3252 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3254 let isCodeGenOnly = 1 in {
3255 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3256 !strconcat(OpcodeStr,
3257 "ps\t{$src, $dst|$dst, $src}"),
3258 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3260 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3261 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3263 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3264 EVEX_V512, EVEX_CD8<32, CD8VF>;
3265 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3266 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3267 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3268 EVEX, EVEX_V512, VEX_W;
3269 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3270 !strconcat(OpcodeStr,
3271 "pd\t{$src, $dst|$dst, $src}"),
3272 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3273 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3274 } // isCodeGenOnly = 1
3277 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3278 Intrinsic F32Int, Intrinsic F64Int,
3279 OpndItins itins_s, OpndItins itins_d> {
3280 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3281 (ins FR32X:$src1, FR32X:$src2),
3282 !strconcat(OpcodeStr,
3283 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3284 [], itins_s.rr>, XS, EVEX_4V;
3285 let isCodeGenOnly = 1 in
3286 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3287 (ins VR128X:$src1, VR128X:$src2),
3288 !strconcat(OpcodeStr,
3289 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3291 (F32Int VR128X:$src1, VR128X:$src2))],
3292 itins_s.rr>, XS, EVEX_4V;
3293 let mayLoad = 1 in {
3294 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3295 (ins FR32X:$src1, f32mem:$src2),
3296 !strconcat(OpcodeStr,
3297 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3298 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3299 let isCodeGenOnly = 1 in
3300 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3301 (ins VR128X:$src1, ssmem:$src2),
3302 !strconcat(OpcodeStr,
3303 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3305 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3306 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3308 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3309 (ins FR64X:$src1, FR64X:$src2),
3310 !strconcat(OpcodeStr,
3311 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3313 let isCodeGenOnly = 1 in
3314 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3315 (ins VR128X:$src1, VR128X:$src2),
3316 !strconcat(OpcodeStr,
3317 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3319 (F64Int VR128X:$src1, VR128X:$src2))],
3320 itins_s.rr>, XD, EVEX_4V, VEX_W;
3321 let mayLoad = 1 in {
3322 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3323 (ins FR64X:$src1, f64mem:$src2),
3324 !strconcat(OpcodeStr,
3325 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3326 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3327 let isCodeGenOnly = 1 in
3328 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3329 (ins VR128X:$src1, sdmem:$src2),
3330 !strconcat(OpcodeStr,
3331 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3333 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3334 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3339 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3340 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3341 SSE_SQRTSS, SSE_SQRTSD>,
3342 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3343 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3344 SSE_SQRTPS, SSE_SQRTPD>;
3346 let Predicates = [HasAVX512] in {
3347 def : Pat<(f32 (fsqrt FR32X:$src)),
3348 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3349 def : Pat<(f32 (fsqrt (load addr:$src))),
3350 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3351 Requires<[OptForSize]>;
3352 def : Pat<(f64 (fsqrt FR64X:$src)),
3353 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3354 def : Pat<(f64 (fsqrt (load addr:$src))),
3355 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3356 Requires<[OptForSize]>;
3358 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3359 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3360 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3361 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3362 Requires<[OptForSize]>;
3364 def : Pat<(f32 (X86frcp FR32X:$src)),
3365 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3366 def : Pat<(f32 (X86frcp (load addr:$src))),
3367 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3368 Requires<[OptForSize]>;
3370 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3371 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3372 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3374 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3375 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3377 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3378 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3379 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3381 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3382 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3386 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3387 X86MemOperand x86memop, RegisterClass RC,
3388 PatFrag mem_frag32, PatFrag mem_frag64,
3389 Intrinsic V4F32Int, Intrinsic V2F64Int,
3391 let ExeDomain = SSEPackedSingle in {
3392 // Intrinsic operation, reg.
3393 // Vector intrinsic operation, reg
3394 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3395 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3396 !strconcat(OpcodeStr,
3397 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3398 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3400 // Vector intrinsic operation, mem
3401 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3402 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3403 !strconcat(OpcodeStr,
3404 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3406 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3407 EVEX_CD8<32, VForm>;
3408 } // ExeDomain = SSEPackedSingle
3410 let ExeDomain = SSEPackedDouble in {
3411 // Vector intrinsic operation, reg
3412 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3413 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3414 !strconcat(OpcodeStr,
3415 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3416 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3418 // Vector intrinsic operation, mem
3419 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3420 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3421 !strconcat(OpcodeStr,
3422 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3424 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3425 EVEX_CD8<64, VForm>;
3426 } // ExeDomain = SSEPackedDouble
3429 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3433 let ExeDomain = GenericDomain in {
3435 let hasSideEffects = 0 in
3436 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3437 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3438 !strconcat(OpcodeStr,
3439 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3442 // Intrinsic operation, reg.
3443 let isCodeGenOnly = 1 in
3444 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3445 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3446 !strconcat(OpcodeStr,
3447 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3448 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3450 // Intrinsic operation, mem.
3451 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3452 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3453 !strconcat(OpcodeStr,
3454 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3455 [(set VR128X:$dst, (F32Int VR128X:$src1,
3456 sse_load_f32:$src2, imm:$src3))]>,
3457 EVEX_CD8<32, CD8VT1>;
3460 let hasSideEffects = 0 in
3461 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3462 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3463 !strconcat(OpcodeStr,
3464 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3467 // Intrinsic operation, reg.
3468 let isCodeGenOnly = 1 in
3469 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3470 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3471 !strconcat(OpcodeStr,
3472 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3473 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3476 // Intrinsic operation, mem.
3477 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3478 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3479 !strconcat(OpcodeStr,
3480 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3482 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3483 VEX_W, EVEX_CD8<64, CD8VT1>;
3484 } // ExeDomain = GenericDomain
3487 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3488 X86MemOperand x86memop, RegisterClass RC,
3489 PatFrag mem_frag, Domain d> {
3490 let ExeDomain = d in {
3491 // Intrinsic operation, reg.
3492 // Vector intrinsic operation, reg
3493 def r : AVX512AIi8<opc, MRMSrcReg,
3494 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3495 !strconcat(OpcodeStr,
3496 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3499 // Vector intrinsic operation, mem
3500 def m : AVX512AIi8<opc, MRMSrcMem,
3501 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3502 !strconcat(OpcodeStr,
3503 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3509 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3510 memopv16f32, SSEPackedSingle>, EVEX_V512,
3511 EVEX_CD8<32, CD8VF>;
3513 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3514 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3516 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3519 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3520 memopv8f64, SSEPackedDouble>, EVEX_V512,
3521 VEX_W, EVEX_CD8<64, CD8VF>;
3523 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3524 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3526 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3528 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3529 Operand x86memop, RegisterClass RC, Domain d> {
3530 let ExeDomain = d in {
3531 def r : AVX512AIi8<opc, MRMSrcReg,
3532 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3533 !strconcat(OpcodeStr,
3534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3537 def m : AVX512AIi8<opc, MRMSrcMem,
3538 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3539 !strconcat(OpcodeStr,
3540 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3545 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3546 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3548 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3549 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3551 def : Pat<(ffloor FR32X:$src),
3552 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3553 def : Pat<(f64 (ffloor FR64X:$src)),
3554 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3555 def : Pat<(f32 (fnearbyint FR32X:$src)),
3556 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3557 def : Pat<(f64 (fnearbyint FR64X:$src)),
3558 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3559 def : Pat<(f32 (fceil FR32X:$src)),
3560 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3561 def : Pat<(f64 (fceil FR64X:$src)),
3562 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3563 def : Pat<(f32 (frint FR32X:$src)),
3564 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3565 def : Pat<(f64 (frint FR64X:$src)),
3566 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3567 def : Pat<(f32 (ftrunc FR32X:$src)),
3568 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3569 def : Pat<(f64 (ftrunc FR64X:$src)),
3570 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3572 def : Pat<(v16f32 (ffloor VR512:$src)),
3573 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3574 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3575 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3576 def : Pat<(v16f32 (fceil VR512:$src)),
3577 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3578 def : Pat<(v16f32 (frint VR512:$src)),
3579 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3580 def : Pat<(v16f32 (ftrunc VR512:$src)),
3581 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3583 def : Pat<(v8f64 (ffloor VR512:$src)),
3584 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3585 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3586 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3587 def : Pat<(v8f64 (fceil VR512:$src)),
3588 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3589 def : Pat<(v8f64 (frint VR512:$src)),
3590 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3591 def : Pat<(v8f64 (ftrunc VR512:$src)),
3592 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3594 //-------------------------------------------------
3595 // Integer truncate and extend operations
3596 //-------------------------------------------------
3598 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3599 RegisterClass dstRC, RegisterClass srcRC,
3600 RegisterClass KRC, X86MemOperand x86memop> {
3601 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3603 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3606 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3607 (ins KRC:$mask, srcRC:$src),
3608 !strconcat(OpcodeStr,
3609 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3612 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3616 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3617 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3618 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3619 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3620 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3621 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3622 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3623 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3624 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3625 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3626 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3627 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3628 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3629 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3630 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3631 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3632 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3633 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3634 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3635 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3636 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3637 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3638 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3639 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3640 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3641 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3642 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3643 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3644 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3645 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3647 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3648 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3649 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3650 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3651 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3653 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3654 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3655 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3656 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3657 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3658 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3659 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3660 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3663 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3664 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3665 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3667 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3669 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3670 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3671 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3672 (ins x86memop:$src),
3673 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3675 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3679 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3680 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3682 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3683 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3685 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3686 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3687 EVEX_CD8<16, CD8VH>;
3688 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3689 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3690 EVEX_CD8<16, CD8VQ>;
3691 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3692 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3693 EVEX_CD8<32, CD8VH>;
3695 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3696 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3698 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3699 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3701 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3702 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3703 EVEX_CD8<16, CD8VH>;
3704 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3705 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3706 EVEX_CD8<16, CD8VQ>;
3707 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3708 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3709 EVEX_CD8<32, CD8VH>;
3711 //===----------------------------------------------------------------------===//
3712 // GATHER - SCATTER Operations
3714 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3715 RegisterClass RC, X86MemOperand memop> {
3717 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3718 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3719 (ins RC:$src1, KRC:$mask, memop:$src2),
3720 !strconcat(OpcodeStr,
3721 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3724 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3725 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3726 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3727 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3729 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3730 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3731 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3732 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3734 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3735 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3736 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3737 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3739 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3740 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3741 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3742 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3744 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3745 RegisterClass RC, X86MemOperand memop> {
3746 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3747 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3748 (ins memop:$dst, KRC:$mask, RC:$src2),
3749 !strconcat(OpcodeStr,
3750 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3754 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3755 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3756 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3757 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3759 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3760 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3761 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3762 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3764 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3765 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3766 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3767 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3769 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3770 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3771 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3772 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3774 //===----------------------------------------------------------------------===//
3775 // VSHUFPS - VSHUFPD Operations
3777 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3778 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3780 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3781 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3782 !strconcat(OpcodeStr,
3783 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3784 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3785 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3786 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3787 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3788 (ins RC:$src1, RC:$src2, i8imm:$src3),
3789 !strconcat(OpcodeStr,
3790 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3791 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3792 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3793 EVEX_4V, Sched<[WriteShuffle]>;
3796 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3797 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3798 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3799 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3801 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3802 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3803 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3804 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3805 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3807 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3808 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3809 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3810 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3811 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3813 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3814 X86MemOperand x86memop> {
3815 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3816 (ins RC:$src1, RC:$src2, i8imm:$src3),
3817 !strconcat(OpcodeStr,
3818 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3821 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3822 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3823 !strconcat(OpcodeStr,
3824 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3827 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3828 EVEX_V512, EVEX_CD8<32, CD8VF>;
3829 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3830 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3832 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3833 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3834 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3835 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3836 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3837 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3838 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3839 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3841 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3842 X86MemOperand x86memop> {
3843 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3844 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3846 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3847 (ins x86memop:$src),
3848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3852 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3853 EVEX_CD8<32, CD8VF>;
3854 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3855 EVEX_CD8<64, CD8VF>;
3857 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3858 (v16i32 immAllZerosV), (i16 -1))),
3859 (VPABSDrr VR512:$src)>;
3860 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3861 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3862 (VPABSQrr VR512:$src)>;
3864 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3865 RegisterClass RC, RegisterClass KRC,
3866 X86MemOperand x86memop,
3867 X86MemOperand x86scalar_mop, string BrdcstStr> {
3868 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3870 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3872 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3873 (ins x86memop:$src),
3874 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3876 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3877 (ins x86scalar_mop:$src),
3878 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3879 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3881 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3882 (ins KRC:$mask, RC:$src),
3883 !strconcat(OpcodeStr,
3884 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3886 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3887 (ins KRC:$mask, x86memop:$src),
3888 !strconcat(OpcodeStr,
3889 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3891 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3892 (ins KRC:$mask, x86scalar_mop:$src),
3893 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3894 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3896 []>, EVEX, EVEX_KZ, EVEX_B;
3898 let Constraints = "$src1 = $dst" in {
3899 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3900 (ins RC:$src1, KRC:$mask, RC:$src2),
3901 !strconcat(OpcodeStr,
3902 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3904 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3905 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3906 !strconcat(OpcodeStr,
3907 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3909 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3910 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3911 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3912 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3913 []>, EVEX, EVEX_K, EVEX_B;
3917 let Predicates = [HasCDI] in {
3918 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3919 i512mem, i32mem, "{1to16}">,
3920 EVEX_V512, EVEX_CD8<32, CD8VF>;
3923 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3924 i512mem, i64mem, "{1to8}">,
3925 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3929 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3931 (VPCONFLICTDrrk VR512:$src1,
3932 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3934 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3936 (VPCONFLICTQrrk VR512:$src1,
3937 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;