1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
11 // Corresponding mask register class.
12 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
14 // Corresponding write-mask register class.
15 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
17 // The GPR register class that can hold the write mask. Use GR8 for fewer
18 // than 8 elements. Use shift-right and equal to work around the lack of
21 !cast<RegisterClass>("GR" #
22 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
24 // Suffix used in the instruction mnemonic.
25 string Suffix = suffix;
27 // VTName is a string name for vector VT. For vector types it will be
28 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
29 // It is a little bit complex for scalar types, where NumElts = 1.
30 // In this case we build v4f32 or v2f64
31 string VTName = "v" # !if (!eq (NumElts, 1),
32 !if (!eq (EltVT.Size, 32), 4,
33 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
36 ValueType VT = !cast<ValueType>(VTName);
38 string EltTypeName = !cast<string>(EltVT);
39 // Size of the element type in bits, e.g. 32 for v16i32.
40 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
41 int EltSize = EltVT.Size;
43 // "i" for integer types and "f" for floating-point types
44 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
46 // Size of RC in bits, e.g. 512 for VR512.
49 // The corresponding memory operand, e.g. i512mem for VR512.
50 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
51 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
54 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
55 // due to load promotion during legalization
56 PatFrag LdFrag = !cast<PatFrag>("load" #
57 !if (!eq (TypeVariantName, "i"),
58 !if (!eq (Size, 128), "v2i64",
59 !if (!eq (Size, 256), "v4i64",
61 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
63 // Load patterns used for memory operands. We only have this defined in
64 // case of i64 element types for sub-512 integer vectors. For now, keep
65 // MemOpFrag undefined in these cases.
67 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
68 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
69 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
70 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
73 // The corresponding float type, e.g. v16f32 for v16i32
74 // Note: For EltSize < 32, FloatVT is illegal and TableGen
75 // fails to compile, so we choose FloatVT = VT
76 ValueType FloatVT = !cast<ValueType>(
77 !if (!eq (!srl(EltSize,5),0),
79 !if (!eq(TypeVariantName, "i"),
80 "v" # NumElts # "f" # EltSize,
83 // The string to specify embedded broadcast in assembly.
84 string BroadcastStr = "{1to" # NumElts # "}";
86 // 8-bit compressed displacement tuple/subvector format. This is only
87 // defined for NumElts <= 8.
88 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
89 !cast<CD8VForm>("CD8VT" # NumElts), ?);
91 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
92 !if (!eq (Size, 256), sub_ymm, ?));
94 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
95 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
98 // A vector type of the same width with element type i32. This is used to
99 // create the canonical constant zero node ImmAllZerosV.
100 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
101 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
104 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
105 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
106 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
107 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
108 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
109 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
111 // "x" in v32i8x_info means RC = VR256X
112 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
113 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
114 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
115 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
116 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
117 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
119 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
120 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
121 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
122 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
123 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
124 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
126 // We map scalar types to the smallest (128-bit) vector type
127 // with the appropriate element type. This allows to use the same masking logic.
128 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
129 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
131 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
132 X86VectorVTInfo i128> {
133 X86VectorVTInfo info512 = i512;
134 X86VectorVTInfo info256 = i256;
135 X86VectorVTInfo info128 = i128;
138 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
140 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
142 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
144 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
146 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
148 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
151 // This multiclass generates the masking variants from the non-masking
152 // variant. It only provides the assembly pieces for the masking variants.
153 // It assumes custom ISel patterns for masking which can be provided as
154 // template arguments.
155 multiclass AVX512_maskable_custom<bits<8> O, Format F,
157 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
159 string AttSrcAsm, string IntelSrcAsm,
161 list<dag> MaskingPattern,
162 list<dag> ZeroMaskingPattern,
164 string MaskingConstraint = "",
165 InstrItinClass itin = NoItinerary,
166 bit IsCommutable = 0> {
167 let isCommutable = IsCommutable in
168 def NAME: AVX512<O, F, Outs, Ins,
169 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
170 "$dst "#Round#", "#IntelSrcAsm#"}",
173 // Prefer over VMOV*rrk Pat<>
174 let AddedComplexity = 20 in
175 def NAME#k: AVX512<O, F, Outs, MaskingIns,
176 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
177 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
178 MaskingPattern, itin>,
180 // In case of the 3src subclass this is overridden with a let.
181 string Constraints = MaskingConstraint;
183 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
184 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
185 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
186 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
193 // Common base class of AVX512_maskable and AVX512_maskable_3src.
194 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
196 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
198 string AttSrcAsm, string IntelSrcAsm,
199 dag RHS, dag MaskingRHS,
200 SDNode Select = vselect, string Round = "",
201 string MaskingConstraint = "",
202 InstrItinClass itin = NoItinerary,
203 bit IsCommutable = 0> :
204 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
205 AttSrcAsm, IntelSrcAsm,
206 [(set _.RC:$dst, RHS)],
207 [(set _.RC:$dst, MaskingRHS)],
209 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
210 Round, MaskingConstraint, NoItinerary, IsCommutable>;
212 // This multiclass generates the unconditional/non-masking, the masking and
213 // the zero-masking variant of the vector instruction. In the masking case, the
214 // perserved vector elements come from a new dummy input operand tied to $dst.
215 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
216 dag Outs, dag Ins, string OpcodeStr,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, string Round = "",
219 InstrItinClass itin = NoItinerary,
220 bit IsCommutable = 0> :
221 AVX512_maskable_common<O, F, _, Outs, Ins,
222 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
223 !con((ins _.KRCWM:$mask), Ins),
224 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
225 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
226 Round, "$src0 = $dst", itin, IsCommutable>;
228 // This multiclass generates the unconditional/non-masking, the masking and
229 // the zero-masking variant of the scalar instruction.
230 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
231 dag Outs, dag Ins, string OpcodeStr,
232 string AttSrcAsm, string IntelSrcAsm,
233 dag RHS, string Round = "",
234 InstrItinClass itin = NoItinerary,
235 bit IsCommutable = 0> :
236 AVX512_maskable_common<O, F, _, Outs, Ins,
237 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
238 !con((ins _.KRCWM:$mask), Ins),
239 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
240 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
241 Round, "$src0 = $dst", itin, IsCommutable>;
243 // Similar to AVX512_maskable but in this case one of the source operands
244 // ($src1) is already tied to $dst so we just use that for the preserved
245 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
247 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
248 dag Outs, dag NonTiedIns, string OpcodeStr,
249 string AttSrcAsm, string IntelSrcAsm,
251 AVX512_maskable_common<O, F, _, Outs,
252 !con((ins _.RC:$src1), NonTiedIns),
253 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
256 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
259 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
262 string AttSrcAsm, string IntelSrcAsm,
264 AVX512_maskable_custom<O, F, Outs, Ins,
265 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
266 !con((ins _.KRCWM:$mask), Ins),
267 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
270 // Bitcasts between 512-bit vector types. Return the original type since
271 // no instruction is needed for the conversion
272 let Predicates = [HasAVX512] in {
273 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
274 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
305 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
306 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
336 // Bitcasts between 256-bit vector types. Return the original type since
337 // no instruction is needed for the conversion
338 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
371 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
374 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
375 isPseudo = 1, Predicates = [HasAVX512] in {
376 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
377 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
380 let Predicates = [HasAVX512] in {
381 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
382 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
386 //===----------------------------------------------------------------------===//
387 // AVX-512 - VECTOR INSERT
390 multiclass vinsert_for_size_no_alt<int Opcode,
391 X86VectorVTInfo From, X86VectorVTInfo To,
392 PatFrag vinsert_insert,
393 SDNodeXForm INSERT_get_vinsert_imm> {
394 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
395 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
396 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
397 "vinsert" # From.EltTypeName # "x" # From.NumElts #
398 "\t{$src3, $src2, $src1, $dst|"
399 "$dst, $src1, $src2, $src3}",
400 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
401 (From.VT From.RC:$src2),
406 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
407 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
408 "vinsert" # From.EltTypeName # "x" # From.NumElts #
409 "\t{$src3, $src2, $src1, $dst|"
410 "$dst, $src1, $src2, $src3}",
412 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
416 multiclass vinsert_for_size<int Opcode,
417 X86VectorVTInfo From, X86VectorVTInfo To,
418 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
419 PatFrag vinsert_insert,
420 SDNodeXForm INSERT_get_vinsert_imm> :
421 vinsert_for_size_no_alt<Opcode, From, To,
422 vinsert_insert, INSERT_get_vinsert_imm> {
423 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
424 // vinserti32x4. Only add this if 64x2 and friends are not supported
425 // natively via AVX512DQ.
426 let Predicates = [NoDQI] in
427 def : Pat<(vinsert_insert:$ins
428 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
429 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
430 VR512:$src1, From.RC:$src2,
431 (INSERT_get_vinsert_imm VR512:$ins)))>;
434 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
435 ValueType EltVT64, int Opcode256> {
436 defm NAME # "32x4" : vinsert_for_size<Opcode128,
437 X86VectorVTInfo< 4, EltVT32, VR128X>,
438 X86VectorVTInfo<16, EltVT32, VR512>,
439 X86VectorVTInfo< 2, EltVT64, VR128X>,
440 X86VectorVTInfo< 8, EltVT64, VR512>,
442 INSERT_get_vinsert128_imm>;
443 let Predicates = [HasDQI] in
444 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
445 X86VectorVTInfo< 2, EltVT64, VR128X>,
446 X86VectorVTInfo< 8, EltVT64, VR512>,
448 INSERT_get_vinsert128_imm>, VEX_W;
449 defm NAME # "64x4" : vinsert_for_size<Opcode256,
450 X86VectorVTInfo< 4, EltVT64, VR256X>,
451 X86VectorVTInfo< 8, EltVT64, VR512>,
452 X86VectorVTInfo< 8, EltVT32, VR256>,
453 X86VectorVTInfo<16, EltVT32, VR512>,
455 INSERT_get_vinsert256_imm>, VEX_W;
456 let Predicates = [HasDQI] in
457 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
458 X86VectorVTInfo< 8, EltVT32, VR256X>,
459 X86VectorVTInfo<16, EltVT32, VR512>,
461 INSERT_get_vinsert256_imm>;
464 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
465 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
467 // vinsertps - insert f32 to XMM
468 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
469 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
470 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
471 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
473 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
474 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
475 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
476 [(set VR128X:$dst, (X86insertps VR128X:$src1,
477 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
478 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
480 //===----------------------------------------------------------------------===//
481 // AVX-512 VECTOR EXTRACT
484 multiclass vextract_for_size<int Opcode,
485 X86VectorVTInfo From, X86VectorVTInfo To,
486 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
487 PatFrag vextract_extract,
488 SDNodeXForm EXTRACT_get_vextract_imm> {
489 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
490 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
491 (ins VR512:$src1, i8imm:$idx),
492 "vextract" # To.EltTypeName # "x4",
493 "$idx, $src1", "$src1, $idx",
494 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
496 AVX512AIi8Base, EVEX, EVEX_V512;
498 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
499 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
500 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
501 "$dst, $src1, $src2}",
502 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
505 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
507 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
508 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
510 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
512 // A 128/256-bit subvector extract from the first 512-bit vector position is
513 // a subregister copy that needs no instruction.
514 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
516 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
518 // And for the alternative types.
519 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
521 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
523 // Intrinsic call with masking.
524 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
526 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
527 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
528 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
529 VR512:$src1, imm:$idx)>;
531 // Intrinsic call with zero-masking.
532 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
534 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
535 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
536 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
537 VR512:$src1, imm:$idx)>;
539 // Intrinsic call without masking.
540 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
542 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
543 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
544 VR512:$src1, imm:$idx)>;
547 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
548 ValueType EltVT64, int Opcode64> {
549 defm NAME # "32x4" : vextract_for_size<Opcode32,
550 X86VectorVTInfo<16, EltVT32, VR512>,
551 X86VectorVTInfo< 4, EltVT32, VR128X>,
552 X86VectorVTInfo< 8, EltVT64, VR512>,
553 X86VectorVTInfo< 2, EltVT64, VR128X>,
555 EXTRACT_get_vextract128_imm>;
556 defm NAME # "64x4" : vextract_for_size<Opcode64,
557 X86VectorVTInfo< 8, EltVT64, VR512>,
558 X86VectorVTInfo< 4, EltVT64, VR256X>,
559 X86VectorVTInfo<16, EltVT32, VR512>,
560 X86VectorVTInfo< 8, EltVT32, VR256>,
562 EXTRACT_get_vextract256_imm>, VEX_W;
565 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
566 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
568 // A 128-bit subvector insert to the first 512-bit vector position
569 // is a subregister copy that needs no instruction.
570 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
571 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
572 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
574 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
575 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
576 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
578 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
580 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
582 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
583 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
584 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
587 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
588 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
589 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
590 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
591 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
592 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
593 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
594 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
596 // vextractps - extract 32 bits from XMM
597 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
598 (ins VR128X:$src1, i32i8imm:$src2),
599 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
600 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
603 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
604 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
605 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
606 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
607 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
609 //===---------------------------------------------------------------------===//
612 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
613 ValueType svt, X86VectorVTInfo _> {
614 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
615 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
616 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
620 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
621 (ins _.ScalarMemOp:$src),
622 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
623 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
628 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
629 AVX512VLVectorVTInfo _> {
630 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
633 let Predicates = [HasVLX] in {
634 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
639 let ExeDomain = SSEPackedSingle in {
640 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
641 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
642 let Predicates = [HasVLX] in {
643 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
644 v4f32, v4f32x_info>, EVEX_V128,
645 EVEX_CD8<32, CD8VT1>;
649 let ExeDomain = SSEPackedDouble in {
650 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
651 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
654 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
655 (VBROADCASTSSZm addr:$src)>;
656 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
657 (VBROADCASTSDZm addr:$src)>;
659 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
660 (VBROADCASTSSZm addr:$src)>;
661 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
662 (VBROADCASTSDZm addr:$src)>;
664 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
665 RegisterClass SrcRC, RegisterClass KRC> {
666 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
667 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
668 []>, EVEX, EVEX_V512;
669 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
670 (ins KRC:$mask, SrcRC:$src),
671 !strconcat(OpcodeStr,
672 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
673 []>, EVEX, EVEX_V512, EVEX_KZ;
676 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
677 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
680 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
681 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
683 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
684 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
686 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
687 (VPBROADCASTDrZrr GR32:$src)>;
688 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
689 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
690 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
691 (VPBROADCASTQrZrr GR64:$src)>;
692 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
693 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
695 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
696 (VPBROADCASTDrZrr GR32:$src)>;
697 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
698 (VPBROADCASTQrZrr GR64:$src)>;
700 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
701 (v16i32 immAllZerosV), (i16 GR16:$mask))),
702 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
703 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
704 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
705 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
707 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
708 X86MemOperand x86memop, PatFrag ld_frag,
709 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
711 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
712 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
714 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
715 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
717 !strconcat(OpcodeStr,
718 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
720 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
723 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
726 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
727 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
729 !strconcat(OpcodeStr,
730 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
731 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
732 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
736 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
737 loadi32, VR512, v16i32, v4i32, VK16WM>,
738 EVEX_V512, EVEX_CD8<32, CD8VT1>;
739 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
740 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
741 EVEX_CD8<64, CD8VT1>;
743 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
744 X86MemOperand x86memop, PatFrag ld_frag,
747 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
748 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
750 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
752 !strconcat(OpcodeStr,
753 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
758 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
759 i128mem, loadv2i64, VK16WM>,
760 EVEX_V512, EVEX_CD8<32, CD8VT4>;
761 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
762 i256mem, loadv4i64, VK16WM>, VEX_W,
763 EVEX_V512, EVEX_CD8<64, CD8VT4>;
765 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
766 (VPBROADCASTDZrr VR128X:$src)>;
767 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
768 (VPBROADCASTQZrr VR128X:$src)>;
770 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
771 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
772 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
773 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
775 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
776 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
777 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
778 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
780 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
781 (VBROADCASTSSZr VR128X:$src)>;
782 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
783 (VBROADCASTSDZr VR128X:$src)>;
785 // Provide fallback in case the load node that is used in the patterns above
786 // is used by additional users, which prevents the pattern selection.
787 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
788 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
789 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
790 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
793 let Predicates = [HasAVX512] in {
794 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
796 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
797 addr:$src)), sub_ymm)>;
799 //===----------------------------------------------------------------------===//
800 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
803 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
805 let Predicates = [HasCDI] in
806 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
808 []>, EVEX, EVEX_V512;
810 let Predicates = [HasCDI, HasVLX] in {
811 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
812 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
813 []>, EVEX, EVEX_V128;
814 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
815 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
816 []>, EVEX, EVEX_V256;
820 let Predicates = [HasCDI] in {
821 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
823 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
827 //===----------------------------------------------------------------------===//
830 // -- immediate form --
831 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
833 let ExeDomain = _.ExeDomain in {
834 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
835 (ins _.RC:$src1, i8imm:$src2),
836 !strconcat(OpcodeStr,
837 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
839 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
841 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
842 (ins _.MemOp:$src1, i8imm:$src2),
843 !strconcat(OpcodeStr,
844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
846 (_.VT (OpNode (_.MemOpFrag addr:$src1),
848 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
852 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
853 X86VectorVTInfo Ctrl> :
854 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
855 let ExeDomain = _.ExeDomain in {
856 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
857 (ins _.RC:$src1, _.RC:$src2),
858 !strconcat("vpermil" # _.Suffix,
859 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
861 (_.VT (X86VPermilpv _.RC:$src1,
862 (Ctrl.VT Ctrl.RC:$src2))))]>,
864 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
865 (ins _.RC:$src1, Ctrl.MemOp:$src2),
866 !strconcat("vpermil" # _.Suffix,
867 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
869 (_.VT (X86VPermilpv _.RC:$src1,
870 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
875 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
877 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
880 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
882 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
885 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
886 (VPERMILPSZri VR512:$src1, imm:$imm)>;
887 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
888 (VPERMILPDZri VR512:$src1, imm:$imm)>;
890 // -- VPERM - register form --
891 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
892 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
894 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
895 (ins RC:$src1, RC:$src2),
896 !strconcat(OpcodeStr,
897 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
899 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
901 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
902 (ins RC:$src1, x86memop:$src2),
903 !strconcat(OpcodeStr,
904 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
906 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
910 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
911 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
912 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
913 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
914 let ExeDomain = SSEPackedSingle in
915 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
916 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
917 let ExeDomain = SSEPackedDouble in
918 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
919 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
921 // -- VPERM2I - 3 source operands form --
922 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
923 PatFrag mem_frag, X86MemOperand x86memop,
924 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
925 let Constraints = "$src1 = $dst" in {
926 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
927 (ins RC:$src1, RC:$src2, RC:$src3),
928 !strconcat(OpcodeStr,
929 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
931 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
934 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
935 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
936 !strconcat(OpcodeStr,
937 "\t{$src3, $src2, $dst {${mask}}|"
938 "$dst {${mask}}, $src2, $src3}"),
939 [(set RC:$dst, (OpVT (vselect KRC:$mask,
940 (OpNode RC:$src1, RC:$src2,
945 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
946 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
947 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
948 !strconcat(OpcodeStr,
949 "\t{$src3, $src2, $dst {${mask}} {z} |",
950 "$dst {${mask}} {z}, $src2, $src3}"),
951 [(set RC:$dst, (OpVT (vselect KRC:$mask,
952 (OpNode RC:$src1, RC:$src2,
955 (v16i32 immAllZerosV))))))]>,
958 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
959 (ins RC:$src1, RC:$src2, x86memop:$src3),
960 !strconcat(OpcodeStr,
961 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
963 (OpVT (OpNode RC:$src1, RC:$src2,
964 (mem_frag addr:$src3))))]>, EVEX_4V;
966 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
967 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
968 !strconcat(OpcodeStr,
969 "\t{$src3, $src2, $dst {${mask}}|"
970 "$dst {${mask}}, $src2, $src3}"),
972 (OpVT (vselect KRC:$mask,
973 (OpNode RC:$src1, RC:$src2,
974 (mem_frag addr:$src3)),
978 let AddedComplexity = 10 in // Prefer over the rrkz variant
979 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
980 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
981 !strconcat(OpcodeStr,
982 "\t{$src3, $src2, $dst {${mask}} {z}|"
983 "$dst {${mask}} {z}, $src2, $src3}"),
985 (OpVT (vselect KRC:$mask,
986 (OpNode RC:$src1, RC:$src2,
987 (mem_frag addr:$src3)),
989 (v16i32 immAllZerosV))))))]>,
993 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
994 i512mem, X86VPermiv3, v16i32, VK16WM>,
995 EVEX_V512, EVEX_CD8<32, CD8VF>;
996 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
997 i512mem, X86VPermiv3, v8i64, VK8WM>,
998 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
999 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1000 i512mem, X86VPermiv3, v16f32, VK16WM>,
1001 EVEX_V512, EVEX_CD8<32, CD8VF>;
1002 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1003 i512mem, X86VPermiv3, v8f64, VK8WM>,
1004 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1006 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1007 PatFrag mem_frag, X86MemOperand x86memop,
1008 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1009 ValueType MaskVT, RegisterClass MRC> :
1010 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1012 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1013 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1014 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1016 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1017 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1018 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1019 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1022 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1023 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1024 EVEX_V512, EVEX_CD8<32, CD8VF>;
1025 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1026 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1027 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1028 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1029 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1030 EVEX_V512, EVEX_CD8<32, CD8VF>;
1031 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1032 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1033 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1035 //===----------------------------------------------------------------------===//
1036 // AVX-512 - BLEND using mask
1038 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1039 RegisterClass KRC, RegisterClass RC,
1040 X86MemOperand x86memop, PatFrag mem_frag,
1041 SDNode OpNode, ValueType vt> {
1042 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1043 (ins KRC:$mask, RC:$src1, RC:$src2),
1044 !strconcat(OpcodeStr,
1045 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1046 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1047 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1049 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1050 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1051 !strconcat(OpcodeStr,
1052 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1053 []>, EVEX_4V, EVEX_K;
1056 let ExeDomain = SSEPackedSingle in
1057 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1058 VK16WM, VR512, f512mem,
1059 memopv16f32, vselect, v16f32>,
1060 EVEX_CD8<32, CD8VF>, EVEX_V512;
1061 let ExeDomain = SSEPackedDouble in
1062 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1063 VK8WM, VR512, f512mem,
1064 memopv8f64, vselect, v8f64>,
1065 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1067 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1068 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1069 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1070 VR512:$src1, VR512:$src2)>;
1072 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1073 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1074 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1075 VR512:$src1, VR512:$src2)>;
1077 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1078 VK16WM, VR512, f512mem,
1079 memopv16i32, vselect, v16i32>,
1080 EVEX_CD8<32, CD8VF>, EVEX_V512;
1082 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1083 VK8WM, VR512, f512mem,
1084 memopv8i64, vselect, v8i64>,
1085 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1087 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1088 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1089 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1090 VR512:$src1, VR512:$src2)>;
1092 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1093 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1094 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1095 VR512:$src1, VR512:$src2)>;
1097 let Predicates = [HasAVX512] in {
1098 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1099 (v8f32 VR256X:$src2))),
1101 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1102 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1103 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1105 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1106 (v8i32 VR256X:$src2))),
1108 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1109 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1110 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1112 //===----------------------------------------------------------------------===//
1113 // Compare Instructions
1114 //===----------------------------------------------------------------------===//
1116 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1117 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1118 Operand CC, SDNode OpNode, ValueType VT,
1119 PatFrag ld_frag, string asm, string asm_alt> {
1120 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1121 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1122 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1123 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1124 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1125 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1126 [(set VK1:$dst, (OpNode (VT RC:$src1),
1127 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1128 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1129 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1130 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1131 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1132 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1133 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1134 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1138 let Predicates = [HasAVX512] in {
1139 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1140 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1141 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1143 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1144 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1145 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1149 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1150 X86VectorVTInfo _> {
1151 def rr : AVX512BI<opc, MRMSrcReg,
1152 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1153 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1154 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1155 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1157 def rm : AVX512BI<opc, MRMSrcMem,
1158 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1159 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1160 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1161 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1162 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1163 def rrk : AVX512BI<opc, MRMSrcReg,
1164 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1165 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1166 "$dst {${mask}}, $src1, $src2}"),
1167 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1168 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1169 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1171 def rmk : AVX512BI<opc, MRMSrcMem,
1172 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1173 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1174 "$dst {${mask}}, $src1, $src2}"),
1175 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1176 (OpNode (_.VT _.RC:$src1),
1178 (_.LdFrag addr:$src2))))))],
1179 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1182 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1183 X86VectorVTInfo _> :
1184 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1185 let mayLoad = 1 in {
1186 def rmb : AVX512BI<opc, MRMSrcMem,
1187 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1188 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1189 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1190 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1191 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1192 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1193 def rmbk : AVX512BI<opc, MRMSrcMem,
1194 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1195 _.ScalarMemOp:$src2),
1196 !strconcat(OpcodeStr,
1197 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1198 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1199 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1200 (OpNode (_.VT _.RC:$src1),
1202 (_.ScalarLdFrag addr:$src2)))))],
1203 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1207 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1208 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1209 let Predicates = [prd] in
1210 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1213 let Predicates = [prd, HasVLX] in {
1214 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1216 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1221 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1222 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1224 let Predicates = [prd] in
1225 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1228 let Predicates = [prd, HasVLX] in {
1229 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1231 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1236 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1237 avx512vl_i8_info, HasBWI>,
1240 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1241 avx512vl_i16_info, HasBWI>,
1242 EVEX_CD8<16, CD8VF>;
1244 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1245 avx512vl_i32_info, HasAVX512>,
1246 EVEX_CD8<32, CD8VF>;
1248 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1249 avx512vl_i64_info, HasAVX512>,
1250 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1252 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1253 avx512vl_i8_info, HasBWI>,
1256 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1257 avx512vl_i16_info, HasBWI>,
1258 EVEX_CD8<16, CD8VF>;
1260 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1261 avx512vl_i32_info, HasAVX512>,
1262 EVEX_CD8<32, CD8VF>;
1264 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1265 avx512vl_i64_info, HasAVX512>,
1266 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1268 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1269 (COPY_TO_REGCLASS (VPCMPGTDZrr
1270 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1271 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1273 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1274 (COPY_TO_REGCLASS (VPCMPEQDZrr
1275 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1276 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1278 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1279 X86VectorVTInfo _> {
1280 def rri : AVX512AIi8<opc, MRMSrcReg,
1281 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1282 !strconcat("vpcmp${cc}", Suffix,
1283 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1284 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1286 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1288 def rmi : AVX512AIi8<opc, MRMSrcMem,
1289 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1290 !strconcat("vpcmp${cc}", Suffix,
1291 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1292 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1293 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1295 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1296 def rrik : AVX512AIi8<opc, MRMSrcReg,
1297 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1299 !strconcat("vpcmp${cc}", Suffix,
1300 "\t{$src2, $src1, $dst {${mask}}|",
1301 "$dst {${mask}}, $src1, $src2}"),
1302 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1303 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1305 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1307 def rmik : AVX512AIi8<opc, MRMSrcMem,
1308 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1310 !strconcat("vpcmp${cc}", Suffix,
1311 "\t{$src2, $src1, $dst {${mask}}|",
1312 "$dst {${mask}}, $src1, $src2}"),
1313 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1314 (OpNode (_.VT _.RC:$src1),
1315 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1317 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1319 // Accept explicit immediate argument form instead of comparison code.
1320 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1321 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1322 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1323 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1324 "$dst, $src1, $src2, $cc}"),
1325 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1326 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1327 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1328 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1329 "$dst, $src1, $src2, $cc}"),
1330 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1331 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1332 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1334 !strconcat("vpcmp", Suffix,
1335 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1336 "$dst {${mask}}, $src1, $src2, $cc}"),
1337 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1338 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1339 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1341 !strconcat("vpcmp", Suffix,
1342 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1343 "$dst {${mask}}, $src1, $src2, $cc}"),
1344 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1348 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1349 X86VectorVTInfo _> :
1350 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1351 let mayLoad = 1 in {
1352 def rmib : AVX512AIi8<opc, MRMSrcMem,
1353 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1355 !strconcat("vpcmp${cc}", Suffix,
1356 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1357 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1358 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1359 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1361 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1362 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1363 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1364 _.ScalarMemOp:$src2, AVXCC:$cc),
1365 !strconcat("vpcmp${cc}", Suffix,
1366 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1367 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1368 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1369 (OpNode (_.VT _.RC:$src1),
1370 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1372 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1375 // Accept explicit immediate argument form instead of comparison code.
1376 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1377 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1378 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1380 !strconcat("vpcmp", Suffix,
1381 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1382 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1383 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1384 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1385 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1386 _.ScalarMemOp:$src2, i8imm:$cc),
1387 !strconcat("vpcmp", Suffix,
1388 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1389 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1390 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1394 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1395 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1396 let Predicates = [prd] in
1397 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1399 let Predicates = [prd, HasVLX] in {
1400 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1401 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1405 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1406 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1407 let Predicates = [prd] in
1408 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1411 let Predicates = [prd, HasVLX] in {
1412 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1414 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1419 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1420 HasBWI>, EVEX_CD8<8, CD8VF>;
1421 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1422 HasBWI>, EVEX_CD8<8, CD8VF>;
1424 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1425 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1426 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1427 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1429 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1430 HasAVX512>, EVEX_CD8<32, CD8VF>;
1431 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1432 HasAVX512>, EVEX_CD8<32, CD8VF>;
1434 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1435 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1436 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1437 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1439 // avx512_cmp_packed - compare packed instructions
1440 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1441 X86MemOperand x86memop, ValueType vt,
1442 string suffix, Domain d> {
1443 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1444 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1445 !strconcat("vcmp${cc}", suffix,
1446 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1447 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1448 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1449 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1450 !strconcat("vcmp${cc}", suffix,
1451 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1453 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1454 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1455 !strconcat("vcmp${cc}", suffix,
1456 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1458 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1460 // Accept explicit immediate argument form instead of comparison code.
1461 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1462 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1463 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1464 !strconcat("vcmp", suffix,
1465 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1466 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1467 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1468 !strconcat("vcmp", suffix,
1469 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1473 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1474 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1475 EVEX_CD8<32, CD8VF>;
1476 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1477 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1478 EVEX_CD8<64, CD8VF>;
1480 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1481 (COPY_TO_REGCLASS (VCMPPSZrri
1482 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1483 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1485 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1486 (COPY_TO_REGCLASS (VPCMPDZrri
1487 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1488 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1490 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1491 (COPY_TO_REGCLASS (VPCMPUDZrri
1492 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1493 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1496 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1497 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1499 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1500 (I8Imm imm:$cc)), GR16)>;
1502 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1503 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1505 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1506 (I8Imm imm:$cc)), GR8)>;
1508 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1509 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1511 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1512 (I8Imm imm:$cc)), GR16)>;
1514 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1515 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1517 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1518 (I8Imm imm:$cc)), GR8)>;
1520 // Mask register copy, including
1521 // - copy between mask registers
1522 // - load/store mask registers
1523 // - copy from GPR to mask register and vice versa
1525 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1526 string OpcodeStr, RegisterClass KRC,
1527 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1528 let hasSideEffects = 0 in {
1529 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1530 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1532 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1533 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1534 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1536 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1541 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1543 RegisterClass KRC, RegisterClass GRC> {
1544 let hasSideEffects = 0 in {
1545 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1547 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1548 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1552 let Predicates = [HasDQI] in
1553 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1555 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1558 let Predicates = [HasAVX512] in
1559 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1561 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1564 let Predicates = [HasBWI] in {
1565 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1566 i32mem>, VEX, PD, VEX_W;
1567 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1571 let Predicates = [HasBWI] in {
1572 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1573 i64mem>, VEX, PS, VEX_W;
1574 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1578 // GR from/to mask register
1579 let Predicates = [HasDQI] in {
1580 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1581 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1582 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1583 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1585 let Predicates = [HasAVX512] in {
1586 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1587 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1588 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1589 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1591 let Predicates = [HasBWI] in {
1592 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1593 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1595 let Predicates = [HasBWI] in {
1596 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1597 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1601 let Predicates = [HasDQI] in {
1602 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1603 (KMOVBmk addr:$dst, VK8:$src)>;
1605 let Predicates = [HasAVX512] in {
1606 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1607 (KMOVWmk addr:$dst, VK16:$src)>;
1608 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1609 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1610 def : Pat<(i1 (load addr:$src)),
1611 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1612 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1613 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1615 let Predicates = [HasBWI] in {
1616 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1617 (KMOVDmk addr:$dst, VK32:$src)>;
1619 let Predicates = [HasBWI] in {
1620 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1621 (KMOVQmk addr:$dst, VK64:$src)>;
1624 let Predicates = [HasAVX512] in {
1625 def : Pat<(i1 (trunc (i64 GR64:$src))),
1626 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1629 def : Pat<(i1 (trunc (i32 GR32:$src))),
1630 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1632 def : Pat<(i1 (trunc (i8 GR8:$src))),
1634 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1636 def : Pat<(i1 (trunc (i16 GR16:$src))),
1638 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1641 def : Pat<(i32 (zext VK1:$src)),
1642 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1643 def : Pat<(i8 (zext VK1:$src)),
1646 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1647 def : Pat<(i64 (zext VK1:$src)),
1648 (AND64ri8 (SUBREG_TO_REG (i64 0),
1649 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1650 def : Pat<(i16 (zext VK1:$src)),
1652 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1654 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1655 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1656 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1657 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1659 let Predicates = [HasBWI] in {
1660 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1661 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1662 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1663 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1667 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1668 let Predicates = [HasAVX512] in {
1669 // GR from/to 8-bit mask without native support
1670 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1672 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1674 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1676 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1679 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1680 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1681 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1682 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1684 let Predicates = [HasBWI] in {
1685 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1686 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1687 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1688 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1691 // Mask unary operation
1693 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1694 RegisterClass KRC, SDPatternOperator OpNode,
1696 let Predicates = [prd] in
1697 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1698 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1699 [(set KRC:$dst, (OpNode KRC:$src))]>;
1702 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1703 SDPatternOperator OpNode> {
1704 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1706 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1707 HasAVX512>, VEX, PS;
1708 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1709 HasBWI>, VEX, PD, VEX_W;
1710 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1711 HasBWI>, VEX, PS, VEX_W;
1714 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1716 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1717 let Predicates = [HasAVX512] in
1718 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1720 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1721 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1723 defm : avx512_mask_unop_int<"knot", "KNOT">;
1725 let Predicates = [HasDQI] in
1726 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1727 let Predicates = [HasAVX512] in
1728 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1729 let Predicates = [HasBWI] in
1730 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1731 let Predicates = [HasBWI] in
1732 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1734 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1735 let Predicates = [HasAVX512] in {
1736 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1737 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1739 def : Pat<(not VK8:$src),
1741 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1744 // Mask binary operation
1745 // - KAND, KANDN, KOR, KXNOR, KXOR
1746 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1747 RegisterClass KRC, SDPatternOperator OpNode,
1749 let Predicates = [prd] in
1750 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1751 !strconcat(OpcodeStr,
1752 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1753 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1756 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1757 SDPatternOperator OpNode> {
1758 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1759 HasDQI>, VEX_4V, VEX_L, PD;
1760 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1761 HasAVX512>, VEX_4V, VEX_L, PS;
1762 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1763 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1764 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1765 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1768 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1769 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1771 let isCommutable = 1 in {
1772 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1773 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1774 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1775 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1777 let isCommutable = 0 in
1778 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1780 def : Pat<(xor VK1:$src1, VK1:$src2),
1781 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1782 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1784 def : Pat<(or VK1:$src1, VK1:$src2),
1785 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1786 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1788 def : Pat<(and VK1:$src1, VK1:$src2),
1789 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1790 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1792 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1793 let Predicates = [HasAVX512] in
1794 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1795 (i16 GR16:$src1), (i16 GR16:$src2)),
1796 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1797 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1798 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1801 defm : avx512_mask_binop_int<"kand", "KAND">;
1802 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1803 defm : avx512_mask_binop_int<"kor", "KOR">;
1804 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1805 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1807 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1808 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1809 let Predicates = [HasAVX512] in
1810 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1812 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1813 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1816 defm : avx512_binop_pat<and, KANDWrr>;
1817 defm : avx512_binop_pat<andn, KANDNWrr>;
1818 defm : avx512_binop_pat<or, KORWrr>;
1819 defm : avx512_binop_pat<xnor, KXNORWrr>;
1820 defm : avx512_binop_pat<xor, KXORWrr>;
1823 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1824 RegisterClass KRC> {
1825 let Predicates = [HasAVX512] in
1826 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1827 !strconcat(OpcodeStr,
1828 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1831 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1832 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1836 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1837 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1838 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1839 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1842 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1843 let Predicates = [HasAVX512] in
1844 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1845 (i16 GR16:$src1), (i16 GR16:$src2)),
1846 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1847 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1848 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1850 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1853 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1855 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1856 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1857 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1858 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1861 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1862 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1866 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1868 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1869 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1870 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1873 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1875 let Predicates = [HasAVX512] in
1876 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1877 !strconcat(OpcodeStr,
1878 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1879 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1882 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1884 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1888 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1889 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1891 // Mask setting all 0s or 1s
1892 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1893 let Predicates = [HasAVX512] in
1894 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1895 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1896 [(set KRC:$dst, (VT Val))]>;
1899 multiclass avx512_mask_setop_w<PatFrag Val> {
1900 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1901 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1904 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1905 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1907 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1908 let Predicates = [HasAVX512] in {
1909 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1910 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1911 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1912 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1913 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1915 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1916 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1918 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1919 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1921 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1922 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1924 let Predicates = [HasVLX] in {
1925 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1926 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1927 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1928 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1929 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1930 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1931 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1932 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1935 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1936 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1938 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1939 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1940 //===----------------------------------------------------------------------===//
1941 // AVX-512 - Aligned and unaligned load and store
1944 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1945 RegisterClass KRC, RegisterClass RC,
1946 ValueType vt, ValueType zvt, X86MemOperand memop,
1947 Domain d, bit IsReMaterializable = 1> {
1948 let hasSideEffects = 0 in {
1949 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1950 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1952 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1953 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1954 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1956 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1957 SchedRW = [WriteLoad] in
1958 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1959 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1960 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1963 let AddedComplexity = 20 in {
1964 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1965 let hasSideEffects = 0 in
1966 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1967 (ins RC:$src0, KRC:$mask, RC:$src1),
1968 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1969 "${dst} {${mask}}, $src1}"),
1970 [(set RC:$dst, (vt (vselect KRC:$mask,
1974 let mayLoad = 1, SchedRW = [WriteLoad] in
1975 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1976 (ins RC:$src0, KRC:$mask, memop:$src1),
1977 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1978 "${dst} {${mask}}, $src1}"),
1981 (vt (bitconvert (ld_frag addr:$src1))),
1985 let mayLoad = 1, SchedRW = [WriteLoad] in
1986 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1987 (ins KRC:$mask, memop:$src),
1988 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1989 "${dst} {${mask}} {z}, $src}"),
1992 (vt (bitconvert (ld_frag addr:$src))),
1993 (vt (bitconvert (zvt immAllZerosV))))))],
1998 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1999 string elty, string elsz, string vsz512,
2000 string vsz256, string vsz128, Domain d,
2001 Predicate prd, bit IsReMaterializable = 1> {
2002 let Predicates = [prd] in
2003 defm Z : avx512_load<opc, OpcodeStr,
2004 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2005 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2006 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2007 !cast<X86MemOperand>(elty##"512mem"), d,
2008 IsReMaterializable>, EVEX_V512;
2010 let Predicates = [prd, HasVLX] in {
2011 defm Z256 : avx512_load<opc, OpcodeStr,
2012 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2013 "v"##vsz256##elty##elsz, "v4i64")),
2014 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2015 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2016 !cast<X86MemOperand>(elty##"256mem"), d,
2017 IsReMaterializable>, EVEX_V256;
2019 defm Z128 : avx512_load<opc, OpcodeStr,
2020 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2021 "v"##vsz128##elty##elsz, "v2i64")),
2022 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2023 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2024 !cast<X86MemOperand>(elty##"128mem"), d,
2025 IsReMaterializable>, EVEX_V128;
2030 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2031 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2032 X86MemOperand memop, Domain d> {
2033 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2034 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2035 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2037 let Constraints = "$src1 = $dst" in
2038 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2039 (ins RC:$src1, KRC:$mask, RC:$src2),
2040 !strconcat(OpcodeStr,
2041 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2043 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2044 (ins KRC:$mask, RC:$src),
2045 !strconcat(OpcodeStr,
2046 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2047 [], d>, EVEX, EVEX_KZ;
2049 let mayStore = 1 in {
2050 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2051 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2052 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2053 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2054 (ins memop:$dst, KRC:$mask, RC:$src),
2055 !strconcat(OpcodeStr,
2056 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2057 [], d>, EVEX, EVEX_K;
2062 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2063 string st_suff_512, string st_suff_256,
2064 string st_suff_128, string elty, string elsz,
2065 string vsz512, string vsz256, string vsz128,
2066 Domain d, Predicate prd> {
2067 let Predicates = [prd] in
2068 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2069 !cast<ValueType>("v"##vsz512##elty##elsz),
2070 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2071 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2073 let Predicates = [prd, HasVLX] in {
2074 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2075 !cast<ValueType>("v"##vsz256##elty##elsz),
2076 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2077 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2079 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2080 !cast<ValueType>("v"##vsz128##elty##elsz),
2081 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2082 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2086 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2087 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2088 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2089 "512", "256", "", "f", "32", "16", "8", "4",
2090 SSEPackedSingle, HasAVX512>,
2091 PS, EVEX_CD8<32, CD8VF>;
2093 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2094 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2095 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2096 "512", "256", "", "f", "64", "8", "4", "2",
2097 SSEPackedDouble, HasAVX512>,
2098 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2100 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2101 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2102 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2103 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2104 PS, EVEX_CD8<32, CD8VF>;
2106 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2107 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2108 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2109 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2110 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2112 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2113 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2114 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2116 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2117 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2118 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2120 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2122 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2124 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2126 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2129 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2130 (VMOVUPSZmrk addr:$ptr,
2131 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2132 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2134 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2135 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2136 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2138 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2139 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2141 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2142 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2144 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2145 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2147 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2148 (bc_v16f32 (v16i32 immAllZerosV)))),
2149 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2151 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2152 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2154 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2155 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2157 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2158 (bc_v8f64 (v16i32 immAllZerosV)))),
2159 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2161 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2162 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2164 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2165 "16", "8", "4", SSEPackedInt, HasAVX512>,
2166 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2167 "512", "256", "", "i", "32", "16", "8", "4",
2168 SSEPackedInt, HasAVX512>,
2169 PD, EVEX_CD8<32, CD8VF>;
2171 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2172 "8", "4", "2", SSEPackedInt, HasAVX512>,
2173 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2174 "512", "256", "", "i", "64", "8", "4", "2",
2175 SSEPackedInt, HasAVX512>,
2176 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2178 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2179 "64", "32", "16", SSEPackedInt, HasBWI>,
2180 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2181 "i", "8", "64", "32", "16", SSEPackedInt,
2182 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2184 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2185 "32", "16", "8", SSEPackedInt, HasBWI>,
2186 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2187 "i", "16", "32", "16", "8", SSEPackedInt,
2188 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2190 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2191 "16", "8", "4", SSEPackedInt, HasAVX512>,
2192 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2193 "i", "32", "16", "8", "4", SSEPackedInt,
2194 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2196 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2197 "8", "4", "2", SSEPackedInt, HasAVX512>,
2198 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2199 "i", "64", "8", "4", "2", SSEPackedInt,
2200 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2202 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2203 (v16i32 immAllZerosV), GR16:$mask)),
2204 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2206 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2207 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2208 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2210 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2212 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2214 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2216 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2219 let AddedComplexity = 20 in {
2220 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2221 (bc_v8i64 (v16i32 immAllZerosV)))),
2222 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2224 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2225 (v8i64 VR512:$src))),
2226 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2229 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2230 (v16i32 immAllZerosV))),
2231 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2233 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2234 (v16i32 VR512:$src))),
2235 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2238 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2239 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2241 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2242 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2244 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2245 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2247 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2248 (bc_v8i64 (v16i32 immAllZerosV)))),
2249 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2251 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2252 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2254 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2255 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2257 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2258 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2260 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2261 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2264 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2265 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2268 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2269 (VMOVDQU32Zmrk addr:$ptr,
2270 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2271 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2273 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2274 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2275 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2278 // Move Int Doubleword to Packed Double Int
2280 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2281 "vmovd\t{$src, $dst|$dst, $src}",
2283 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2285 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2286 "vmovd\t{$src, $dst|$dst, $src}",
2288 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2289 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2290 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2291 "vmovq\t{$src, $dst|$dst, $src}",
2293 (v2i64 (scalar_to_vector GR64:$src)))],
2294 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2295 let isCodeGenOnly = 1 in {
2296 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2297 "vmovq\t{$src, $dst|$dst, $src}",
2298 [(set FR64:$dst, (bitconvert GR64:$src))],
2299 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2300 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2301 "vmovq\t{$src, $dst|$dst, $src}",
2302 [(set GR64:$dst, (bitconvert FR64:$src))],
2303 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2305 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2306 "vmovq\t{$src, $dst|$dst, $src}",
2307 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2308 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2309 EVEX_CD8<64, CD8VT1>;
2311 // Move Int Doubleword to Single Scalar
2313 let isCodeGenOnly = 1 in {
2314 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2315 "vmovd\t{$src, $dst|$dst, $src}",
2316 [(set FR32X:$dst, (bitconvert GR32:$src))],
2317 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2319 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2320 "vmovd\t{$src, $dst|$dst, $src}",
2321 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2322 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2325 // Move doubleword from xmm register to r/m32
2327 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2328 "vmovd\t{$src, $dst|$dst, $src}",
2329 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2330 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2332 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2333 (ins i32mem:$dst, VR128X:$src),
2334 "vmovd\t{$src, $dst|$dst, $src}",
2335 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2336 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2337 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2339 // Move quadword from xmm1 register to r/m64
2341 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2342 "vmovq\t{$src, $dst|$dst, $src}",
2343 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2345 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2346 Requires<[HasAVX512, In64BitMode]>;
2348 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2349 (ins i64mem:$dst, VR128X:$src),
2350 "vmovq\t{$src, $dst|$dst, $src}",
2351 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2352 addr:$dst)], IIC_SSE_MOVDQ>,
2353 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2354 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2356 // Move Scalar Single to Double Int
2358 let isCodeGenOnly = 1 in {
2359 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2361 "vmovd\t{$src, $dst|$dst, $src}",
2362 [(set GR32:$dst, (bitconvert FR32X:$src))],
2363 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2364 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2365 (ins i32mem:$dst, FR32X:$src),
2366 "vmovd\t{$src, $dst|$dst, $src}",
2367 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2368 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2371 // Move Quadword Int to Packed Quadword Int
2373 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2375 "vmovq\t{$src, $dst|$dst, $src}",
2377 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2378 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2380 //===----------------------------------------------------------------------===//
2381 // AVX-512 MOVSS, MOVSD
2382 //===----------------------------------------------------------------------===//
2384 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2385 SDNode OpNode, ValueType vt,
2386 X86MemOperand x86memop, PatFrag mem_pat> {
2387 let hasSideEffects = 0 in {
2388 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2389 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2390 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2391 (scalar_to_vector RC:$src2))))],
2392 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2393 let Constraints = "$src1 = $dst" in
2394 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2395 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2397 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2398 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2399 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2400 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2401 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2403 let mayStore = 1 in {
2404 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2405 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2406 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2408 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2409 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2410 [], IIC_SSE_MOV_S_MR>,
2411 EVEX, VEX_LIG, EVEX_K;
2413 } //hasSideEffects = 0
2416 let ExeDomain = SSEPackedSingle in
2417 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2418 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2420 let ExeDomain = SSEPackedDouble in
2421 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2422 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2424 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2425 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2426 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2428 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2429 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2430 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2432 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2433 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2434 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2436 // For the disassembler
2437 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2438 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2439 (ins VR128X:$src1, FR32X:$src2),
2440 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2442 XS, EVEX_4V, VEX_LIG;
2443 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2444 (ins VR128X:$src1, FR64X:$src2),
2445 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2447 XD, EVEX_4V, VEX_LIG, VEX_W;
2450 let Predicates = [HasAVX512] in {
2451 let AddedComplexity = 15 in {
2452 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2453 // MOVS{S,D} to the lower bits.
2454 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2455 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2456 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2457 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2458 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2459 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2460 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2461 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2463 // Move low f32 and clear high bits.
2464 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2465 (SUBREG_TO_REG (i32 0),
2466 (VMOVSSZrr (v4f32 (V_SET0)),
2467 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2468 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2469 (SUBREG_TO_REG (i32 0),
2470 (VMOVSSZrr (v4i32 (V_SET0)),
2471 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2474 let AddedComplexity = 20 in {
2475 // MOVSSrm zeros the high parts of the register; represent this
2476 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2477 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2478 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2479 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2480 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2481 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2482 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2484 // MOVSDrm zeros the high parts of the register; represent this
2485 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2486 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2487 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2488 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2489 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2490 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2491 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2492 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2493 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2494 def : Pat<(v2f64 (X86vzload addr:$src)),
2495 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2497 // Represent the same patterns above but in the form they appear for
2499 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2500 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2501 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2502 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2503 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2504 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2505 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2506 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2507 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2509 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2510 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2511 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2512 FR32X:$src)), sub_xmm)>;
2513 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2514 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2515 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2516 FR64X:$src)), sub_xmm)>;
2517 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2518 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2519 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2521 // Move low f64 and clear high bits.
2522 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2523 (SUBREG_TO_REG (i32 0),
2524 (VMOVSDZrr (v2f64 (V_SET0)),
2525 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2527 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2528 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2529 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2531 // Extract and store.
2532 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2534 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2535 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2537 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2539 // Shuffle with VMOVSS
2540 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2541 (VMOVSSZrr (v4i32 VR128X:$src1),
2542 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2543 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2544 (VMOVSSZrr (v4f32 VR128X:$src1),
2545 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2548 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2549 (SUBREG_TO_REG (i32 0),
2550 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2551 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2553 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2554 (SUBREG_TO_REG (i32 0),
2555 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2556 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2559 // Shuffle with VMOVSD
2560 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2561 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2562 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2563 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2564 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2565 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2566 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2567 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2570 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2571 (SUBREG_TO_REG (i32 0),
2572 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2573 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2575 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2576 (SUBREG_TO_REG (i32 0),
2577 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2578 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2581 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2582 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2583 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2584 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2585 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2586 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2587 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2588 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2591 let AddedComplexity = 15 in
2592 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2594 "vmovq\t{$src, $dst|$dst, $src}",
2595 [(set VR128X:$dst, (v2i64 (X86vzmovl
2596 (v2i64 VR128X:$src))))],
2597 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2599 let AddedComplexity = 20 in
2600 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2602 "vmovq\t{$src, $dst|$dst, $src}",
2603 [(set VR128X:$dst, (v2i64 (X86vzmovl
2604 (loadv2i64 addr:$src))))],
2605 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2606 EVEX_CD8<8, CD8VT8>;
2608 let Predicates = [HasAVX512] in {
2609 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2610 let AddedComplexity = 20 in {
2611 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2612 (VMOVDI2PDIZrm addr:$src)>;
2613 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2614 (VMOV64toPQIZrr GR64:$src)>;
2615 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2616 (VMOVDI2PDIZrr GR32:$src)>;
2618 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2619 (VMOVDI2PDIZrm addr:$src)>;
2620 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2621 (VMOVDI2PDIZrm addr:$src)>;
2622 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2623 (VMOVZPQILo2PQIZrm addr:$src)>;
2624 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2625 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2626 def : Pat<(v2i64 (X86vzload addr:$src)),
2627 (VMOVZPQILo2PQIZrm addr:$src)>;
2630 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2631 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2632 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2633 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2634 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2635 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2636 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2639 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2640 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2642 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2643 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2645 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2646 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2648 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2649 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2651 //===----------------------------------------------------------------------===//
2652 // AVX-512 - Non-temporals
2653 //===----------------------------------------------------------------------===//
2654 let SchedRW = [WriteLoad] in {
2655 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2656 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2657 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2658 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2659 EVEX_CD8<64, CD8VF>;
2661 let Predicates = [HasAVX512, HasVLX] in {
2662 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2664 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2665 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2666 EVEX_CD8<64, CD8VF>;
2668 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2670 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2671 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2672 EVEX_CD8<64, CD8VF>;
2676 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2677 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2678 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2679 let SchedRW = [WriteStore], mayStore = 1,
2680 AddedComplexity = 400 in
2681 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2682 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2683 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2686 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2687 string elty, string elsz, string vsz512,
2688 string vsz256, string vsz128, Domain d,
2689 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2690 let Predicates = [prd] in
2691 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2692 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2693 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2696 let Predicates = [prd, HasVLX] in {
2697 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2698 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2699 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2702 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2703 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2704 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2709 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2710 "i", "64", "8", "4", "2", SSEPackedInt,
2711 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2713 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2714 "f", "64", "8", "4", "2", SSEPackedDouble,
2715 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2717 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2718 "f", "32", "16", "8", "4", SSEPackedSingle,
2719 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2721 //===----------------------------------------------------------------------===//
2722 // AVX-512 - Integer arithmetic
2724 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2725 X86VectorVTInfo _, OpndItins itins,
2726 bit IsCommutable = 0> {
2727 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2728 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2729 "$src2, $src1", "$src1, $src2",
2730 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2731 "", itins.rr, IsCommutable>,
2732 AVX512BIBase, EVEX_4V;
2735 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2736 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2737 "$src2, $src1", "$src1, $src2",
2738 (_.VT (OpNode _.RC:$src1,
2739 (bitconvert (_.LdFrag addr:$src2)))),
2741 AVX512BIBase, EVEX_4V;
2744 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2745 X86VectorVTInfo _, OpndItins itins,
2746 bit IsCommutable = 0> :
2747 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2749 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2750 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2751 "${src2}"##_.BroadcastStr##", $src1",
2752 "$src1, ${src2}"##_.BroadcastStr,
2753 (_.VT (OpNode _.RC:$src1,
2755 (_.ScalarLdFrag addr:$src2)))),
2757 AVX512BIBase, EVEX_4V, EVEX_B;
2760 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2761 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2762 Predicate prd, bit IsCommutable = 0> {
2763 let Predicates = [prd] in
2764 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2765 IsCommutable>, EVEX_V512;
2767 let Predicates = [prd, HasVLX] in {
2768 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2769 IsCommutable>, EVEX_V256;
2770 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2771 IsCommutable>, EVEX_V128;
2775 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2776 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2777 Predicate prd, bit IsCommutable = 0> {
2778 let Predicates = [prd] in
2779 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2780 IsCommutable>, EVEX_V512;
2782 let Predicates = [prd, HasVLX] in {
2783 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2784 IsCommutable>, EVEX_V256;
2785 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2786 IsCommutable>, EVEX_V128;
2790 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2791 OpndItins itins, Predicate prd,
2792 bit IsCommutable = 0> {
2793 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2794 itins, prd, IsCommutable>,
2795 VEX_W, EVEX_CD8<64, CD8VF>;
2798 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2799 OpndItins itins, Predicate prd,
2800 bit IsCommutable = 0> {
2801 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2802 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2805 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2806 OpndItins itins, Predicate prd,
2807 bit IsCommutable = 0> {
2808 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2809 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2812 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2813 OpndItins itins, Predicate prd,
2814 bit IsCommutable = 0> {
2815 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2816 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2819 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2820 SDNode OpNode, OpndItins itins, Predicate prd,
2821 bit IsCommutable = 0> {
2822 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2825 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2829 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2830 SDNode OpNode, OpndItins itins, Predicate prd,
2831 bit IsCommutable = 0> {
2832 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2835 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2839 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2840 bits<8> opc_d, bits<8> opc_q,
2841 string OpcodeStr, SDNode OpNode,
2842 OpndItins itins, bit IsCommutable = 0> {
2843 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2844 itins, HasAVX512, IsCommutable>,
2845 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2846 itins, HasBWI, IsCommutable>;
2849 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2850 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2851 PatFrag memop_frag, X86MemOperand x86memop,
2852 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2853 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2854 let isCommutable = IsCommutable in
2856 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2857 (ins RC:$src1, RC:$src2),
2858 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2860 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2861 (ins KRC:$mask, RC:$src1, RC:$src2),
2862 !strconcat(OpcodeStr,
2863 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2864 [], itins.rr>, EVEX_4V, EVEX_K;
2865 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2866 (ins KRC:$mask, RC:$src1, RC:$src2),
2867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2868 "|$dst {${mask}} {z}, $src1, $src2}"),
2869 [], itins.rr>, EVEX_4V, EVEX_KZ;
2871 let mayLoad = 1 in {
2872 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2873 (ins RC:$src1, x86memop:$src2),
2874 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2876 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2877 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2878 !strconcat(OpcodeStr,
2879 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2880 [], itins.rm>, EVEX_4V, EVEX_K;
2881 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2882 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2883 !strconcat(OpcodeStr,
2884 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2885 [], itins.rm>, EVEX_4V, EVEX_KZ;
2886 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2887 (ins RC:$src1, x86scalar_mop:$src2),
2888 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2889 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2890 [], itins.rm>, EVEX_4V, EVEX_B;
2891 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2892 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2893 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2894 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2896 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2897 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2898 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2899 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2900 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2902 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2906 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2907 SSE_INTALU_ITINS_P, 1>;
2908 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2909 SSE_INTALU_ITINS_P, 0>;
2910 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2911 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2912 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2913 SSE_INTALU_ITINS_P, HasBWI, 1>;
2914 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2915 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2917 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2918 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2919 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2920 EVEX_CD8<64, CD8VF>, VEX_W;
2922 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2923 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2924 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2926 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2927 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2929 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2930 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2931 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2932 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2933 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2934 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2936 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2937 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2938 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2939 SSE_INTALU_ITINS_P, HasBWI, 1>;
2940 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2941 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2943 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2944 SSE_INTALU_ITINS_P, HasBWI, 1>;
2945 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2946 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2947 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2948 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2950 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2951 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2952 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2953 SSE_INTALU_ITINS_P, HasBWI, 1>;
2954 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2955 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2957 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2958 SSE_INTALU_ITINS_P, HasBWI, 1>;
2959 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2960 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2961 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2962 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2964 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2965 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2966 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2967 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2968 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2969 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2970 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2971 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2972 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2973 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2974 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2975 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2976 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2977 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2978 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2979 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2980 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2981 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2982 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2983 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2984 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2985 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2986 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2987 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2988 //===----------------------------------------------------------------------===//
2989 // AVX-512 - Unpack Instructions
2990 //===----------------------------------------------------------------------===//
2992 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2993 PatFrag mem_frag, RegisterClass RC,
2994 X86MemOperand x86memop, string asm,
2996 def rr : AVX512PI<opc, MRMSrcReg,
2997 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2999 (vt (OpNode RC:$src1, RC:$src2)))],
3001 def rm : AVX512PI<opc, MRMSrcMem,
3002 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3004 (vt (OpNode RC:$src1,
3005 (bitconvert (mem_frag addr:$src2)))))],
3009 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3010 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3011 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3012 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3013 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3014 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3015 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3016 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3017 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3018 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3019 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3020 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3022 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3023 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3024 X86MemOperand x86memop> {
3025 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3026 (ins RC:$src1, RC:$src2),
3027 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3028 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3029 IIC_SSE_UNPCK>, EVEX_4V;
3030 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3031 (ins RC:$src1, x86memop:$src2),
3032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3033 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3034 (bitconvert (memop_frag addr:$src2)))))],
3035 IIC_SSE_UNPCK>, EVEX_4V;
3037 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3038 VR512, memopv16i32, i512mem>, EVEX_V512,
3039 EVEX_CD8<32, CD8VF>;
3040 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3041 VR512, memopv8i64, i512mem>, EVEX_V512,
3042 VEX_W, EVEX_CD8<64, CD8VF>;
3043 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3044 VR512, memopv16i32, i512mem>, EVEX_V512,
3045 EVEX_CD8<32, CD8VF>;
3046 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3047 VR512, memopv8i64, i512mem>, EVEX_V512,
3048 VEX_W, EVEX_CD8<64, CD8VF>;
3049 //===----------------------------------------------------------------------===//
3053 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3054 SDNode OpNode, PatFrag mem_frag,
3055 X86MemOperand x86memop, ValueType OpVT> {
3056 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3057 (ins RC:$src1, i8imm:$src2),
3058 !strconcat(OpcodeStr,
3059 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3061 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3063 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3064 (ins x86memop:$src1, i8imm:$src2),
3065 !strconcat(OpcodeStr,
3066 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3068 (OpVT (OpNode (mem_frag addr:$src1),
3069 (i8 imm:$src2))))]>, EVEX;
3072 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3073 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3075 //===----------------------------------------------------------------------===//
3076 // AVX-512 Logical Instructions
3077 //===----------------------------------------------------------------------===//
3079 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3080 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3081 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3082 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3083 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3084 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3085 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3086 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3088 //===----------------------------------------------------------------------===//
3089 // AVX-512 FP arithmetic
3090 //===----------------------------------------------------------------------===//
3092 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3094 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3095 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3096 EVEX_CD8<32, CD8VT1>;
3097 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3098 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3099 EVEX_CD8<64, CD8VT1>;
3102 let isCommutable = 1 in {
3103 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3104 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3105 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3106 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3108 let isCommutable = 0 in {
3109 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3110 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3113 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3114 X86VectorVTInfo _, bit IsCommutable> {
3115 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3116 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3117 "$src2, $src1", "$src1, $src2",
3118 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3119 let mayLoad = 1 in {
3120 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3121 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3122 "$src2, $src1", "$src1, $src2",
3123 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3124 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3125 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3126 "${src2}"##_.BroadcastStr##", $src1",
3127 "$src1, ${src2}"##_.BroadcastStr,
3128 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3129 (_.ScalarLdFrag addr:$src2))))>,
3134 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3135 bit IsCommutable = 0> {
3136 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3137 IsCommutable>, EVEX_V512, PS,
3138 EVEX_CD8<32, CD8VF>;
3139 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3140 IsCommutable>, EVEX_V512, PD, VEX_W,
3141 EVEX_CD8<64, CD8VF>;
3143 // Define only if AVX512VL feature is present.
3144 let Predicates = [HasVLX] in {
3145 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3146 IsCommutable>, EVEX_V128, PS,
3147 EVEX_CD8<32, CD8VF>;
3148 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3149 IsCommutable>, EVEX_V256, PS,
3150 EVEX_CD8<32, CD8VF>;
3151 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3152 IsCommutable>, EVEX_V128, PD, VEX_W,
3153 EVEX_CD8<64, CD8VF>;
3154 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3155 IsCommutable>, EVEX_V256, PD, VEX_W,
3156 EVEX_CD8<64, CD8VF>;
3160 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3161 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3162 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3163 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3164 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3165 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3167 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3168 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3169 (i16 -1), FROUND_CURRENT)),
3170 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3172 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3173 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3174 (i8 -1), FROUND_CURRENT)),
3175 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3177 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3178 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3179 (i16 -1), FROUND_CURRENT)),
3180 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3182 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3183 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3184 (i8 -1), FROUND_CURRENT)),
3185 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3186 //===----------------------------------------------------------------------===//
3187 // AVX-512 VPTESTM instructions
3188 //===----------------------------------------------------------------------===//
3190 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3191 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3192 SDNode OpNode, ValueType vt> {
3193 def rr : AVX512PI<opc, MRMSrcReg,
3194 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3196 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3197 SSEPackedInt>, EVEX_4V;
3198 def rm : AVX512PI<opc, MRMSrcMem,
3199 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3200 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3201 [(set KRC:$dst, (OpNode (vt RC:$src1),
3202 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3205 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3206 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3207 EVEX_CD8<32, CD8VF>;
3208 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3209 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3210 EVEX_CD8<64, CD8VF>;
3212 let Predicates = [HasCDI] in {
3213 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3214 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3215 EVEX_CD8<32, CD8VF>;
3216 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3217 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3218 EVEX_CD8<64, CD8VF>;
3221 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3222 (v16i32 VR512:$src2), (i16 -1))),
3223 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3225 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3226 (v8i64 VR512:$src2), (i8 -1))),
3227 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3229 //===----------------------------------------------------------------------===//
3230 // AVX-512 Shift instructions
3231 //===----------------------------------------------------------------------===//
3232 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3233 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3234 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3235 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3236 "$src2, $src1", "$src1, $src2",
3237 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3238 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3239 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3240 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3241 "$src2, $src1", "$src1, $src2",
3242 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3243 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3246 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3247 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3248 // src2 is always 128-bit
3249 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3250 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3251 "$src2, $src1", "$src1, $src2",
3252 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3253 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3254 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3255 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3256 "$src2, $src1", "$src1, $src2",
3257 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3258 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3261 multiclass avx512_varshift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3262 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3263 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3266 multiclass avx512_varshift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3268 defm D : avx512_varshift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3269 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3270 defm Q : avx512_varshift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3271 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3274 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3276 EVEX_V512, EVEX_CD8<32, CD8VF>;
3277 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3278 v8i64_info>, EVEX_V512,
3279 EVEX_CD8<64, CD8VF>, VEX_W;
3281 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3282 v16i32_info>, EVEX_V512,
3283 EVEX_CD8<32, CD8VF>;
3284 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3285 v8i64_info>, EVEX_V512,
3286 EVEX_CD8<64, CD8VF>, VEX_W;
3288 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3290 EVEX_V512, EVEX_CD8<32, CD8VF>;
3291 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3292 v8i64_info>, EVEX_V512,
3293 EVEX_CD8<64, CD8VF>, VEX_W;
3295 defm VPSRL : avx512_varshift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3296 defm VPSLL : avx512_varshift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3297 defm VPSRA : avx512_varshift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3299 //===-------------------------------------------------------------------===//
3300 // Variable Bit Shifts
3301 //===-------------------------------------------------------------------===//
3302 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3303 RegisterClass RC, ValueType vt,
3304 X86MemOperand x86memop, PatFrag mem_frag> {
3305 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3306 (ins RC:$src1, RC:$src2),
3307 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3309 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3311 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3312 (ins RC:$src1, x86memop:$src2),
3313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3315 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3319 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3320 i512mem, memopv16i32>, EVEX_V512,
3321 EVEX_CD8<32, CD8VF>;
3322 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3323 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3324 EVEX_CD8<64, CD8VF>;
3325 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3326 i512mem, memopv16i32>, EVEX_V512,
3327 EVEX_CD8<32, CD8VF>;
3328 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3329 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3330 EVEX_CD8<64, CD8VF>;
3331 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3332 i512mem, memopv16i32>, EVEX_V512,
3333 EVEX_CD8<32, CD8VF>;
3334 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3335 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3336 EVEX_CD8<64, CD8VF>;
3338 //===----------------------------------------------------------------------===//
3339 // AVX-512 - MOVDDUP
3340 //===----------------------------------------------------------------------===//
3342 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3343 X86MemOperand x86memop, PatFrag memop_frag> {
3344 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3345 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3346 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3347 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3348 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3350 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3353 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3354 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3355 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3356 (VMOVDDUPZrm addr:$src)>;
3358 //===---------------------------------------------------------------------===//
3359 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3360 //===---------------------------------------------------------------------===//
3361 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3362 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3363 X86MemOperand x86memop> {
3364 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3366 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3368 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3369 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3370 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3373 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3374 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3375 EVEX_CD8<32, CD8VF>;
3376 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3377 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3378 EVEX_CD8<32, CD8VF>;
3380 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3381 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3382 (VMOVSHDUPZrm addr:$src)>;
3383 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3384 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3385 (VMOVSLDUPZrm addr:$src)>;
3387 //===----------------------------------------------------------------------===//
3388 // Move Low to High and High to Low packed FP Instructions
3389 //===----------------------------------------------------------------------===//
3390 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3391 (ins VR128X:$src1, VR128X:$src2),
3392 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3393 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3394 IIC_SSE_MOV_LH>, EVEX_4V;
3395 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3396 (ins VR128X:$src1, VR128X:$src2),
3397 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3398 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3399 IIC_SSE_MOV_LH>, EVEX_4V;
3401 let Predicates = [HasAVX512] in {
3403 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3404 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3405 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3406 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3409 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3410 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3413 //===----------------------------------------------------------------------===//
3414 // FMA - Fused Multiply Operations
3417 let Constraints = "$src1 = $dst" in {
3418 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3419 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3420 SDPatternOperator OpNode = null_frag> {
3421 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3422 (ins _.RC:$src2, _.RC:$src3),
3423 OpcodeStr, "$src3, $src2", "$src2, $src3",
3424 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3428 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3429 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3430 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3431 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3432 (_.MemOpFrag addr:$src3))))]>;
3433 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3434 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3435 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
3436 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3437 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3438 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3440 } // Constraints = "$src1 = $dst"
3442 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3443 string OpcodeStr, X86VectorVTInfo VTI,
3444 SDPatternOperator OpNode> {
3445 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3447 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3449 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3451 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3454 let ExeDomain = SSEPackedSingle in {
3455 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3456 v16f32_info, X86Fmadd>;
3457 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3458 v16f32_info, X86Fmsub>;
3459 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3460 v16f32_info, X86Fmaddsub>;
3461 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3462 v16f32_info, X86Fmsubadd>;
3463 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3464 v16f32_info, X86Fnmadd>;
3465 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3466 v16f32_info, X86Fnmsub>;
3468 let ExeDomain = SSEPackedDouble in {
3469 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3470 v8f64_info, X86Fmadd>, VEX_W;
3471 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3472 v8f64_info, X86Fmsub>, VEX_W;
3473 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3474 v8f64_info, X86Fmaddsub>, VEX_W;
3475 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3476 v8f64_info, X86Fmsubadd>, VEX_W;
3477 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3478 v8f64_info, X86Fnmadd>, VEX_W;
3479 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3480 v8f64_info, X86Fnmsub>, VEX_W;
3483 let Constraints = "$src1 = $dst" in {
3484 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3485 X86VectorVTInfo _> {
3487 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3488 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3489 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3490 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3492 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3493 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3494 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3495 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3497 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3498 (_.ScalarLdFrag addr:$src2))),
3499 _.RC:$src3))]>, EVEX_B;
3501 } // Constraints = "$src1 = $dst"
3504 let ExeDomain = SSEPackedSingle in {
3505 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3507 EVEX_V512, EVEX_CD8<32, CD8VF>;
3508 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3510 EVEX_V512, EVEX_CD8<32, CD8VF>;
3511 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3513 EVEX_V512, EVEX_CD8<32, CD8VF>;
3514 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3516 EVEX_V512, EVEX_CD8<32, CD8VF>;
3517 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3519 EVEX_V512, EVEX_CD8<32, CD8VF>;
3520 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3522 EVEX_V512, EVEX_CD8<32, CD8VF>;
3524 let ExeDomain = SSEPackedDouble in {
3525 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3527 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3528 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3530 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3531 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3533 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3534 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3536 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3537 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3539 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3540 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3542 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3546 let Constraints = "$src1 = $dst" in {
3547 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3548 RegisterClass RC, ValueType OpVT,
3549 X86MemOperand x86memop, Operand memop,
3551 let isCommutable = 1 in
3552 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3553 (ins RC:$src1, RC:$src2, RC:$src3),
3554 !strconcat(OpcodeStr,
3555 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3557 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3559 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3560 (ins RC:$src1, RC:$src2, f128mem:$src3),
3561 !strconcat(OpcodeStr,
3562 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3564 (OpVT (OpNode RC:$src2, RC:$src1,
3565 (mem_frag addr:$src3))))]>;
3568 } // Constraints = "$src1 = $dst"
3570 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3571 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3572 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3573 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3574 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3575 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3576 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3577 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3578 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3579 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3580 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3581 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3582 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3583 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3584 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3585 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3587 //===----------------------------------------------------------------------===//
3588 // AVX-512 Scalar convert from sign integer to float/double
3589 //===----------------------------------------------------------------------===//
3591 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3592 X86MemOperand x86memop, string asm> {
3593 let hasSideEffects = 0 in {
3594 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3595 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3598 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3599 (ins DstRC:$src1, x86memop:$src),
3600 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3602 } // hasSideEffects = 0
3604 let Predicates = [HasAVX512] in {
3605 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3606 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3607 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3608 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3609 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3610 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3611 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3612 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3614 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3615 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3616 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3617 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3618 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3619 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3620 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3621 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3623 def : Pat<(f32 (sint_to_fp GR32:$src)),
3624 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3625 def : Pat<(f32 (sint_to_fp GR64:$src)),
3626 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3627 def : Pat<(f64 (sint_to_fp GR32:$src)),
3628 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3629 def : Pat<(f64 (sint_to_fp GR64:$src)),
3630 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3632 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3633 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3634 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3635 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3636 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3637 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3638 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3639 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3641 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3642 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3643 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3644 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3645 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3646 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3647 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3648 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3650 def : Pat<(f32 (uint_to_fp GR32:$src)),
3651 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3652 def : Pat<(f32 (uint_to_fp GR64:$src)),
3653 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3654 def : Pat<(f64 (uint_to_fp GR32:$src)),
3655 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3656 def : Pat<(f64 (uint_to_fp GR64:$src)),
3657 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3660 //===----------------------------------------------------------------------===//
3661 // AVX-512 Scalar convert from float/double to integer
3662 //===----------------------------------------------------------------------===//
3663 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3664 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3666 let hasSideEffects = 0 in {
3667 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3668 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3669 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3670 Requires<[HasAVX512]>;
3672 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3673 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3674 Requires<[HasAVX512]>;
3675 } // hasSideEffects = 0
3677 let Predicates = [HasAVX512] in {
3678 // Convert float/double to signed/unsigned int 32/64
3679 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3680 ssmem, sse_load_f32, "cvtss2si">,
3681 XS, EVEX_CD8<32, CD8VT1>;
3682 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3683 ssmem, sse_load_f32, "cvtss2si">,
3684 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3685 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3686 ssmem, sse_load_f32, "cvtss2usi">,
3687 XS, EVEX_CD8<32, CD8VT1>;
3688 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3689 int_x86_avx512_cvtss2usi64, ssmem,
3690 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3691 EVEX_CD8<32, CD8VT1>;
3692 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3693 sdmem, sse_load_f64, "cvtsd2si">,
3694 XD, EVEX_CD8<64, CD8VT1>;
3695 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3696 sdmem, sse_load_f64, "cvtsd2si">,
3697 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3698 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3699 sdmem, sse_load_f64, "cvtsd2usi">,
3700 XD, EVEX_CD8<64, CD8VT1>;
3701 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3702 int_x86_avx512_cvtsd2usi64, sdmem,
3703 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3704 EVEX_CD8<64, CD8VT1>;
3706 let isCodeGenOnly = 1 in {
3707 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3708 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3709 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3710 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3711 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3712 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3713 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3714 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3715 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3716 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3717 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3718 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3720 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3721 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3722 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3723 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3724 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3725 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3726 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3727 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3728 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3729 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3730 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3731 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3732 } // isCodeGenOnly = 1
3734 // Convert float/double to signed/unsigned int 32/64 with truncation
3735 let isCodeGenOnly = 1 in {
3736 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3737 ssmem, sse_load_f32, "cvttss2si">,
3738 XS, EVEX_CD8<32, CD8VT1>;
3739 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3740 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3741 "cvttss2si">, XS, VEX_W,
3742 EVEX_CD8<32, CD8VT1>;
3743 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3744 sdmem, sse_load_f64, "cvttsd2si">, XD,
3745 EVEX_CD8<64, CD8VT1>;
3746 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3748 "cvttsd2si">, XD, VEX_W,
3749 EVEX_CD8<64, CD8VT1>;
3750 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3751 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3752 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3753 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3754 int_x86_avx512_cvttss2usi64, ssmem,
3755 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3756 EVEX_CD8<32, CD8VT1>;
3757 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3758 int_x86_avx512_cvttsd2usi,
3759 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3760 EVEX_CD8<64, CD8VT1>;
3761 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3762 int_x86_avx512_cvttsd2usi64, sdmem,
3763 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3764 EVEX_CD8<64, CD8VT1>;
3765 } // isCodeGenOnly = 1
3767 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3768 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3770 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3771 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3772 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3773 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3774 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3775 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3778 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3779 loadf32, "cvttss2si">, XS,
3780 EVEX_CD8<32, CD8VT1>;
3781 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3782 loadf32, "cvttss2usi">, XS,
3783 EVEX_CD8<32, CD8VT1>;
3784 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3785 loadf32, "cvttss2si">, XS, VEX_W,
3786 EVEX_CD8<32, CD8VT1>;
3787 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3788 loadf32, "cvttss2usi">, XS, VEX_W,
3789 EVEX_CD8<32, CD8VT1>;
3790 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3791 loadf64, "cvttsd2si">, XD,
3792 EVEX_CD8<64, CD8VT1>;
3793 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3794 loadf64, "cvttsd2usi">, XD,
3795 EVEX_CD8<64, CD8VT1>;
3796 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3797 loadf64, "cvttsd2si">, XD, VEX_W,
3798 EVEX_CD8<64, CD8VT1>;
3799 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3800 loadf64, "cvttsd2usi">, XD, VEX_W,
3801 EVEX_CD8<64, CD8VT1>;
3803 //===----------------------------------------------------------------------===//
3804 // AVX-512 Convert form float to double and back
3805 //===----------------------------------------------------------------------===//
3806 let hasSideEffects = 0 in {
3807 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3808 (ins FR32X:$src1, FR32X:$src2),
3809 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3810 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3812 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3813 (ins FR32X:$src1, f32mem:$src2),
3814 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3815 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3816 EVEX_CD8<32, CD8VT1>;
3818 // Convert scalar double to scalar single
3819 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3820 (ins FR64X:$src1, FR64X:$src2),
3821 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3822 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3824 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3825 (ins FR64X:$src1, f64mem:$src2),
3826 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3827 []>, EVEX_4V, VEX_LIG, VEX_W,
3828 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3831 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3832 Requires<[HasAVX512]>;
3833 def : Pat<(fextend (loadf32 addr:$src)),
3834 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3836 def : Pat<(extloadf32 addr:$src),
3837 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3838 Requires<[HasAVX512, OptForSize]>;
3840 def : Pat<(extloadf32 addr:$src),
3841 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3842 Requires<[HasAVX512, OptForSpeed]>;
3844 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3845 Requires<[HasAVX512]>;
3847 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3848 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3849 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3851 let hasSideEffects = 0 in {
3852 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3853 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3855 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3856 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3857 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3858 [], d>, EVEX, EVEX_B, EVEX_RC;
3860 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3861 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3863 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3864 } // hasSideEffects = 0
3867 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3868 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3869 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3871 let hasSideEffects = 0 in {
3872 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3873 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3875 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3877 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3878 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3880 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3881 } // hasSideEffects = 0
3884 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3885 memopv8f64, f512mem, v8f32, v8f64,
3886 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3887 EVEX_CD8<64, CD8VF>;
3889 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3890 memopv4f64, f256mem, v8f64, v8f32,
3891 SSEPackedDouble>, EVEX_V512, PS,
3892 EVEX_CD8<32, CD8VH>;
3893 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3894 (VCVTPS2PDZrm addr:$src)>;
3896 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3897 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3898 (VCVTPD2PSZrr VR512:$src)>;
3900 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3901 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3902 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3904 //===----------------------------------------------------------------------===//
3905 // AVX-512 Vector convert from sign integer to float/double
3906 //===----------------------------------------------------------------------===//
3908 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3909 memopv8i64, i512mem, v16f32, v16i32,
3910 SSEPackedSingle>, EVEX_V512, PS,
3911 EVEX_CD8<32, CD8VF>;
3913 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3914 memopv4i64, i256mem, v8f64, v8i32,
3915 SSEPackedDouble>, EVEX_V512, XS,
3916 EVEX_CD8<32, CD8VH>;
3918 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3919 memopv16f32, f512mem, v16i32, v16f32,
3920 SSEPackedSingle>, EVEX_V512, XS,
3921 EVEX_CD8<32, CD8VF>;
3923 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3924 memopv8f64, f512mem, v8i32, v8f64,
3925 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3926 EVEX_CD8<64, CD8VF>;
3928 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3929 memopv16f32, f512mem, v16i32, v16f32,
3930 SSEPackedSingle>, EVEX_V512, PS,
3931 EVEX_CD8<32, CD8VF>;
3933 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3934 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3935 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3936 (VCVTTPS2UDQZrr VR512:$src)>;
3938 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3939 memopv8f64, f512mem, v8i32, v8f64,
3940 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3941 EVEX_CD8<64, CD8VF>;
3943 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3944 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3945 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3946 (VCVTTPD2UDQZrr VR512:$src)>;
3948 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3949 memopv4i64, f256mem, v8f64, v8i32,
3950 SSEPackedDouble>, EVEX_V512, XS,
3951 EVEX_CD8<32, CD8VH>;
3953 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3954 memopv16i32, f512mem, v16f32, v16i32,
3955 SSEPackedSingle>, EVEX_V512, XD,
3956 EVEX_CD8<32, CD8VF>;
3958 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3959 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3960 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3962 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3963 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3964 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3966 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3967 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3968 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3970 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3971 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3972 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3974 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3975 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3976 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3978 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3979 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3980 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3981 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3982 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3983 (VCVTDQ2PDZrr VR256X:$src)>;
3984 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3985 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3986 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3987 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3988 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3989 (VCVTUDQ2PDZrr VR256X:$src)>;
3991 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3992 RegisterClass DstRC, PatFrag mem_frag,
3993 X86MemOperand x86memop, Domain d> {
3994 let hasSideEffects = 0 in {
3995 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3996 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3998 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3999 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4000 [], d>, EVEX, EVEX_B, EVEX_RC;
4002 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4003 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4005 } // hasSideEffects = 0
4008 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4009 memopv16f32, f512mem, SSEPackedSingle>, PD,
4010 EVEX_V512, EVEX_CD8<32, CD8VF>;
4011 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4012 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4013 EVEX_V512, EVEX_CD8<64, CD8VF>;
4015 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4016 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4017 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4019 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4020 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4021 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4023 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4024 memopv16f32, f512mem, SSEPackedSingle>,
4025 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4026 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4027 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4028 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4030 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4031 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4032 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4034 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4035 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4036 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4038 let Predicates = [HasAVX512] in {
4039 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4040 (VCVTPD2PSZrm addr:$src)>;
4041 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4042 (VCVTPS2PDZrm addr:$src)>;
4045 //===----------------------------------------------------------------------===//
4046 // Half precision conversion instructions
4047 //===----------------------------------------------------------------------===//
4048 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4049 X86MemOperand x86memop> {
4050 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4051 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4053 let hasSideEffects = 0, mayLoad = 1 in
4054 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4055 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4058 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4059 X86MemOperand x86memop> {
4060 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4061 (ins srcRC:$src1, i32i8imm:$src2),
4062 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4064 let hasSideEffects = 0, mayStore = 1 in
4065 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4066 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4067 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4070 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4071 EVEX_CD8<32, CD8VH>;
4072 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4073 EVEX_CD8<32, CD8VH>;
4075 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4076 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4077 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4079 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4080 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4081 (VCVTPH2PSZrr VR256X:$src)>;
4083 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4084 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4085 "ucomiss">, PS, EVEX, VEX_LIG,
4086 EVEX_CD8<32, CD8VT1>;
4087 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4088 "ucomisd">, PD, EVEX,
4089 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4090 let Pattern = []<dag> in {
4091 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4092 "comiss">, PS, EVEX, VEX_LIG,
4093 EVEX_CD8<32, CD8VT1>;
4094 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4095 "comisd">, PD, EVEX,
4096 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4098 let isCodeGenOnly = 1 in {
4099 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4100 load, "ucomiss">, PS, EVEX, VEX_LIG,
4101 EVEX_CD8<32, CD8VT1>;
4102 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4103 load, "ucomisd">, PD, EVEX,
4104 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4106 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4107 load, "comiss">, PS, EVEX, VEX_LIG,
4108 EVEX_CD8<32, CD8VT1>;
4109 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4110 load, "comisd">, PD, EVEX,
4111 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4115 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4116 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4117 X86MemOperand x86memop> {
4118 let hasSideEffects = 0 in {
4119 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4120 (ins RC:$src1, RC:$src2),
4121 !strconcat(OpcodeStr,
4122 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4123 let mayLoad = 1 in {
4124 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4125 (ins RC:$src1, x86memop:$src2),
4126 !strconcat(OpcodeStr,
4127 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4132 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4133 EVEX_CD8<32, CD8VT1>;
4134 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4135 VEX_W, EVEX_CD8<64, CD8VT1>;
4136 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4137 EVEX_CD8<32, CD8VT1>;
4138 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4139 VEX_W, EVEX_CD8<64, CD8VT1>;
4141 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4142 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4143 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4144 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4146 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4147 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4148 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4149 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4151 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4152 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4153 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4154 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4156 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4157 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4158 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4159 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4161 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4162 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4163 X86VectorVTInfo _> {
4164 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4165 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4166 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4167 let mayLoad = 1 in {
4168 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4169 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4171 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4172 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4173 (ins _.ScalarMemOp:$src), OpcodeStr,
4174 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4176 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4181 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4182 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4183 EVEX_V512, EVEX_CD8<32, CD8VF>;
4184 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4185 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4187 // Define only if AVX512VL feature is present.
4188 let Predicates = [HasVLX] in {
4189 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4190 OpNode, v4f32x_info>,
4191 EVEX_V128, EVEX_CD8<32, CD8VF>;
4192 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4193 OpNode, v8f32x_info>,
4194 EVEX_V256, EVEX_CD8<32, CD8VF>;
4195 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4196 OpNode, v2f64x_info>,
4197 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4198 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4199 OpNode, v4f64x_info>,
4200 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4204 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4205 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4207 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4208 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4209 (VRSQRT14PSZr VR512:$src)>;
4210 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4211 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4212 (VRSQRT14PDZr VR512:$src)>;
4214 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4215 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4216 (VRCP14PSZr VR512:$src)>;
4217 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4218 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4219 (VRCP14PDZr VR512:$src)>;
4221 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4222 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4225 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4226 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4227 "$src2, $src1", "$src1, $src2",
4228 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4229 (i32 FROUND_CURRENT))>;
4231 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4232 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4233 "$src2, $src1", "$src1, $src2",
4234 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4235 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4237 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4238 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4239 "$src2, $src1", "$src1, $src2",
4240 (OpNode (_.VT _.RC:$src1),
4241 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4242 (i32 FROUND_CURRENT))>;
4245 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4246 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4247 EVEX_CD8<32, CD8VT1>;
4248 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4249 EVEX_CD8<64, CD8VT1>, VEX_W;
4252 let hasSideEffects = 0, Predicates = [HasERI] in {
4253 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4254 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4256 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4258 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4261 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4262 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4263 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4265 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4266 (ins _.RC:$src), OpcodeStr,
4268 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4271 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4272 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4274 (bitconvert (_.LdFrag addr:$src))),
4275 (i32 FROUND_CURRENT))>;
4277 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4278 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4280 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4281 (i32 FROUND_CURRENT))>, EVEX_B;
4284 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4285 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4286 EVEX_CD8<32, CD8VF>;
4287 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4288 VEX_W, EVEX_CD8<32, CD8VF>;
4291 let Predicates = [HasERI], hasSideEffects = 0 in {
4293 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4294 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4295 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4298 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4299 SDNode OpNode, X86VectorVTInfo _>{
4300 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4301 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4302 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4303 let mayLoad = 1 in {
4304 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4305 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4307 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4309 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4310 (ins _.ScalarMemOp:$src), OpcodeStr,
4311 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4313 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4318 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4319 Intrinsic F32Int, Intrinsic F64Int,
4320 OpndItins itins_s, OpndItins itins_d> {
4321 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4322 (ins FR32X:$src1, FR32X:$src2),
4323 !strconcat(OpcodeStr,
4324 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4325 [], itins_s.rr>, XS, EVEX_4V;
4326 let isCodeGenOnly = 1 in
4327 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4328 (ins VR128X:$src1, VR128X:$src2),
4329 !strconcat(OpcodeStr,
4330 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4332 (F32Int VR128X:$src1, VR128X:$src2))],
4333 itins_s.rr>, XS, EVEX_4V;
4334 let mayLoad = 1 in {
4335 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4336 (ins FR32X:$src1, f32mem:$src2),
4337 !strconcat(OpcodeStr,
4338 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4339 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4340 let isCodeGenOnly = 1 in
4341 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4342 (ins VR128X:$src1, ssmem:$src2),
4343 !strconcat(OpcodeStr,
4344 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4346 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4347 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4349 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4350 (ins FR64X:$src1, FR64X:$src2),
4351 !strconcat(OpcodeStr,
4352 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4354 let isCodeGenOnly = 1 in
4355 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4356 (ins VR128X:$src1, VR128X:$src2),
4357 !strconcat(OpcodeStr,
4358 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4360 (F64Int VR128X:$src1, VR128X:$src2))],
4361 itins_s.rr>, XD, EVEX_4V, VEX_W;
4362 let mayLoad = 1 in {
4363 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4364 (ins FR64X:$src1, f64mem:$src2),
4365 !strconcat(OpcodeStr,
4366 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4367 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4368 let isCodeGenOnly = 1 in
4369 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4370 (ins VR128X:$src1, sdmem:$src2),
4371 !strconcat(OpcodeStr,
4372 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4374 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4375 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4379 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4381 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4383 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4384 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4386 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4387 // Define only if AVX512VL feature is present.
4388 let Predicates = [HasVLX] in {
4389 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4390 OpNode, v4f32x_info>,
4391 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4392 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4393 OpNode, v8f32x_info>,
4394 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4395 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4396 OpNode, v2f64x_info>,
4397 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4398 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4399 OpNode, v4f64x_info>,
4400 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4404 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4406 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4407 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4408 SSE_SQRTSS, SSE_SQRTSD>;
4410 let Predicates = [HasAVX512] in {
4411 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4412 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4413 (VSQRTPSZr VR512:$src1)>;
4414 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4415 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4416 (VSQRTPDZr VR512:$src1)>;
4418 def : Pat<(f32 (fsqrt FR32X:$src)),
4419 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4420 def : Pat<(f32 (fsqrt (load addr:$src))),
4421 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4422 Requires<[OptForSize]>;
4423 def : Pat<(f64 (fsqrt FR64X:$src)),
4424 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4425 def : Pat<(f64 (fsqrt (load addr:$src))),
4426 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4427 Requires<[OptForSize]>;
4429 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4430 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4431 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4432 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4433 Requires<[OptForSize]>;
4435 def : Pat<(f32 (X86frcp FR32X:$src)),
4436 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4437 def : Pat<(f32 (X86frcp (load addr:$src))),
4438 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4439 Requires<[OptForSize]>;
4441 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4442 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4443 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4445 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4446 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4448 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4449 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4450 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4452 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4453 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4457 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4458 X86MemOperand x86memop, RegisterClass RC,
4459 PatFrag mem_frag32, PatFrag mem_frag64,
4460 Intrinsic V4F32Int, Intrinsic V2F64Int,
4462 let ExeDomain = SSEPackedSingle in {
4463 // Intrinsic operation, reg.
4464 // Vector intrinsic operation, reg
4465 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4466 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4467 !strconcat(OpcodeStr,
4468 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4469 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4471 // Vector intrinsic operation, mem
4472 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4473 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4474 !strconcat(OpcodeStr,
4475 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4477 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4478 EVEX_CD8<32, VForm>;
4479 } // ExeDomain = SSEPackedSingle
4481 let ExeDomain = SSEPackedDouble in {
4482 // Vector intrinsic operation, reg
4483 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4484 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4485 !strconcat(OpcodeStr,
4486 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4487 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4489 // Vector intrinsic operation, mem
4490 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4491 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4492 !strconcat(OpcodeStr,
4493 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4495 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4496 EVEX_CD8<64, VForm>;
4497 } // ExeDomain = SSEPackedDouble
4500 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4504 let ExeDomain = GenericDomain in {
4506 let hasSideEffects = 0 in
4507 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4508 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4509 !strconcat(OpcodeStr,
4510 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4513 // Intrinsic operation, reg.
4514 let isCodeGenOnly = 1 in
4515 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4516 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4517 !strconcat(OpcodeStr,
4518 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4519 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4521 // Intrinsic operation, mem.
4522 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4523 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4524 !strconcat(OpcodeStr,
4525 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4526 [(set VR128X:$dst, (F32Int VR128X:$src1,
4527 sse_load_f32:$src2, imm:$src3))]>,
4528 EVEX_CD8<32, CD8VT1>;
4531 let hasSideEffects = 0 in
4532 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4533 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4534 !strconcat(OpcodeStr,
4535 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4538 // Intrinsic operation, reg.
4539 let isCodeGenOnly = 1 in
4540 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4541 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4542 !strconcat(OpcodeStr,
4543 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4544 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4547 // Intrinsic operation, mem.
4548 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4549 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4550 !strconcat(OpcodeStr,
4551 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4553 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4554 VEX_W, EVEX_CD8<64, CD8VT1>;
4555 } // ExeDomain = GenericDomain
4558 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4559 X86MemOperand x86memop, RegisterClass RC,
4560 PatFrag mem_frag, Domain d> {
4561 let ExeDomain = d in {
4562 // Intrinsic operation, reg.
4563 // Vector intrinsic operation, reg
4564 def r : AVX512AIi8<opc, MRMSrcReg,
4565 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4566 !strconcat(OpcodeStr,
4567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4570 // Vector intrinsic operation, mem
4571 def m : AVX512AIi8<opc, MRMSrcMem,
4572 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4573 !strconcat(OpcodeStr,
4574 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4580 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4581 memopv16f32, SSEPackedSingle>, EVEX_V512,
4582 EVEX_CD8<32, CD8VF>;
4584 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4585 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4587 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4590 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4591 memopv8f64, SSEPackedDouble>, EVEX_V512,
4592 VEX_W, EVEX_CD8<64, CD8VF>;
4594 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4595 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4597 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4599 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4600 Operand x86memop, RegisterClass RC, Domain d> {
4601 let ExeDomain = d in {
4602 def r : AVX512AIi8<opc, MRMSrcReg,
4603 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4604 !strconcat(OpcodeStr,
4605 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4608 def m : AVX512AIi8<opc, MRMSrcMem,
4609 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4610 !strconcat(OpcodeStr,
4611 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4616 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4617 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4619 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4620 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4622 def : Pat<(ffloor FR32X:$src),
4623 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4624 def : Pat<(f64 (ffloor FR64X:$src)),
4625 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4626 def : Pat<(f32 (fnearbyint FR32X:$src)),
4627 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4628 def : Pat<(f64 (fnearbyint FR64X:$src)),
4629 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4630 def : Pat<(f32 (fceil FR32X:$src)),
4631 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4632 def : Pat<(f64 (fceil FR64X:$src)),
4633 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4634 def : Pat<(f32 (frint FR32X:$src)),
4635 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4636 def : Pat<(f64 (frint FR64X:$src)),
4637 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4638 def : Pat<(f32 (ftrunc FR32X:$src)),
4639 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4640 def : Pat<(f64 (ftrunc FR64X:$src)),
4641 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4643 def : Pat<(v16f32 (ffloor VR512:$src)),
4644 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4645 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4646 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4647 def : Pat<(v16f32 (fceil VR512:$src)),
4648 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4649 def : Pat<(v16f32 (frint VR512:$src)),
4650 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4651 def : Pat<(v16f32 (ftrunc VR512:$src)),
4652 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4654 def : Pat<(v8f64 (ffloor VR512:$src)),
4655 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4656 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4657 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4658 def : Pat<(v8f64 (fceil VR512:$src)),
4659 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4660 def : Pat<(v8f64 (frint VR512:$src)),
4661 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4662 def : Pat<(v8f64 (ftrunc VR512:$src)),
4663 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4665 //-------------------------------------------------
4666 // Integer truncate and extend operations
4667 //-------------------------------------------------
4669 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4670 RegisterClass dstRC, RegisterClass srcRC,
4671 RegisterClass KRC, X86MemOperand x86memop> {
4672 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4674 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4677 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4678 (ins KRC:$mask, srcRC:$src),
4679 !strconcat(OpcodeStr,
4680 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4683 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4684 (ins KRC:$mask, srcRC:$src),
4685 !strconcat(OpcodeStr,
4686 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4689 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4690 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4693 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4694 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4695 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4699 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4700 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4701 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4702 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4703 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4704 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4705 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4706 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4707 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4708 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4709 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4710 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4711 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4712 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4713 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4714 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4715 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4716 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4717 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4718 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4719 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4720 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4721 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4722 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4723 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4724 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4725 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4726 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4727 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4728 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4730 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4731 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4732 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4733 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4734 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4736 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4737 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4738 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4739 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4740 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4741 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4742 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4743 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4746 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4747 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4748 PatFrag mem_frag, X86MemOperand x86memop,
4749 ValueType OpVT, ValueType InVT> {
4751 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4753 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4754 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4756 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4757 (ins KRC:$mask, SrcRC:$src),
4758 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4761 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4762 (ins KRC:$mask, SrcRC:$src),
4763 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4766 let mayLoad = 1 in {
4767 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4768 (ins x86memop:$src),
4769 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4771 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4774 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4775 (ins KRC:$mask, x86memop:$src),
4776 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4780 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4781 (ins KRC:$mask, x86memop:$src),
4782 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4788 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4789 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4791 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4792 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4794 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4795 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4796 EVEX_CD8<16, CD8VH>;
4797 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4798 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4799 EVEX_CD8<16, CD8VQ>;
4800 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4801 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4802 EVEX_CD8<32, CD8VH>;
4804 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4805 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4807 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4808 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4810 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4811 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4812 EVEX_CD8<16, CD8VH>;
4813 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4814 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4815 EVEX_CD8<16, CD8VQ>;
4816 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4817 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4818 EVEX_CD8<32, CD8VH>;
4820 //===----------------------------------------------------------------------===//
4821 // GATHER - SCATTER Operations
4823 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4824 RegisterClass RC, X86MemOperand memop> {
4826 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4827 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4828 (ins RC:$src1, KRC:$mask, memop:$src2),
4829 !strconcat(OpcodeStr,
4830 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4834 let ExeDomain = SSEPackedDouble in {
4835 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4836 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4837 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4838 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4841 let ExeDomain = SSEPackedSingle in {
4842 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4843 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4844 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4845 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4848 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4849 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4850 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4851 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4853 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4854 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4855 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4856 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4858 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4859 RegisterClass RC, X86MemOperand memop> {
4860 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4861 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4862 (ins memop:$dst, KRC:$mask, RC:$src2),
4863 !strconcat(OpcodeStr,
4864 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4868 let ExeDomain = SSEPackedDouble in {
4869 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4870 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4871 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4872 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4875 let ExeDomain = SSEPackedSingle in {
4876 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4877 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4878 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4879 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4882 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4883 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4884 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4885 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4887 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4888 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4889 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4890 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4893 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4894 RegisterClass KRC, X86MemOperand memop> {
4895 let Predicates = [HasPFI], hasSideEffects = 1 in
4896 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4897 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4901 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4902 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4904 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4905 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4907 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4908 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4910 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4911 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4913 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4914 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4916 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4917 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4919 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4920 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4922 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4923 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4925 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4926 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4928 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4929 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4931 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4932 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4934 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4935 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4937 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4938 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4940 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4941 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4943 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4944 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4946 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4947 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4948 //===----------------------------------------------------------------------===//
4949 // VSHUFPS - VSHUFPD Operations
4951 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4952 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4954 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4955 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4956 !strconcat(OpcodeStr,
4957 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4958 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4959 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4960 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4961 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4962 (ins RC:$src1, RC:$src2, i8imm:$src3),
4963 !strconcat(OpcodeStr,
4964 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4965 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4966 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4967 EVEX_4V, Sched<[WriteShuffle]>;
4970 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4971 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4972 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4973 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4975 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4976 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4977 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4978 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4979 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4981 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4982 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4983 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4984 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4985 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4987 multiclass avx512_valign<X86VectorVTInfo _> {
4988 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4989 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4991 "$src3, $src2, $src1", "$src1, $src2, $src3",
4992 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4994 AVX512AIi8Base, EVEX_4V;
4996 // Also match valign of packed floats.
4997 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4998 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5001 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5002 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5003 !strconcat("valign"##_.Suffix,
5004 "\t{$src3, $src2, $src1, $dst|"
5005 "$dst, $src1, $src2, $src3}"),
5008 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5009 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5011 // Helper fragments to match sext vXi1 to vXiY.
5012 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5013 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5015 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5016 RegisterClass KRC, RegisterClass RC,
5017 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5019 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5020 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5022 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5023 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5025 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5026 !strconcat(OpcodeStr,
5027 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5029 let mayLoad = 1 in {
5030 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5031 (ins x86memop:$src),
5032 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5034 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5035 (ins KRC:$mask, x86memop:$src),
5036 !strconcat(OpcodeStr,
5037 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5039 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5040 (ins KRC:$mask, x86memop:$src),
5041 !strconcat(OpcodeStr,
5042 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5044 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5045 (ins x86scalar_mop:$src),
5046 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5047 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5049 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5050 (ins KRC:$mask, x86scalar_mop:$src),
5051 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5052 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5053 []>, EVEX, EVEX_B, EVEX_K;
5054 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5055 (ins KRC:$mask, x86scalar_mop:$src),
5056 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5057 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5059 []>, EVEX, EVEX_B, EVEX_KZ;
5063 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5064 i512mem, i32mem, "{1to16}">, EVEX_V512,
5065 EVEX_CD8<32, CD8VF>;
5066 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5067 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5068 EVEX_CD8<64, CD8VF>;
5071 (bc_v16i32 (v16i1sextv16i32)),
5072 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5073 (VPABSDZrr VR512:$src)>;
5075 (bc_v8i64 (v8i1sextv8i64)),
5076 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5077 (VPABSQZrr VR512:$src)>;
5079 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5080 (v16i32 immAllZerosV), (i16 -1))),
5081 (VPABSDZrr VR512:$src)>;
5082 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5083 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5084 (VPABSQZrr VR512:$src)>;
5086 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5087 RegisterClass RC, RegisterClass KRC,
5088 X86MemOperand x86memop,
5089 X86MemOperand x86scalar_mop, string BrdcstStr> {
5090 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5092 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5094 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5095 (ins x86memop:$src),
5096 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5098 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5099 (ins x86scalar_mop:$src),
5100 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5101 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5103 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5104 (ins KRC:$mask, RC:$src),
5105 !strconcat(OpcodeStr,
5106 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5108 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5109 (ins KRC:$mask, x86memop:$src),
5110 !strconcat(OpcodeStr,
5111 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5113 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5114 (ins KRC:$mask, x86scalar_mop:$src),
5115 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5116 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5118 []>, EVEX, EVEX_KZ, EVEX_B;
5120 let Constraints = "$src1 = $dst" in {
5121 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5122 (ins RC:$src1, KRC:$mask, RC:$src2),
5123 !strconcat(OpcodeStr,
5124 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5126 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5127 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5128 !strconcat(OpcodeStr,
5129 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5131 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5132 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5133 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5134 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5135 []>, EVEX, EVEX_K, EVEX_B;
5139 let Predicates = [HasCDI] in {
5140 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5141 i512mem, i32mem, "{1to16}">,
5142 EVEX_V512, EVEX_CD8<32, CD8VF>;
5145 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5146 i512mem, i64mem, "{1to8}">,
5147 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5151 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5153 (VPCONFLICTDrrk VR512:$src1,
5154 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5156 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5158 (VPCONFLICTQrrk VR512:$src1,
5159 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5161 let Predicates = [HasCDI] in {
5162 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5163 i512mem, i32mem, "{1to16}">,
5164 EVEX_V512, EVEX_CD8<32, CD8VF>;
5167 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5168 i512mem, i64mem, "{1to8}">,
5169 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5173 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5175 (VPLZCNTDrrk VR512:$src1,
5176 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5178 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5180 (VPLZCNTQrrk VR512:$src1,
5181 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5183 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5184 (VPLZCNTDrm addr:$src)>;
5185 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5186 (VPLZCNTDrr VR512:$src)>;
5187 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5188 (VPLZCNTQrm addr:$src)>;
5189 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5190 (VPLZCNTQrr VR512:$src)>;
5192 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5193 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5194 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5196 def : Pat<(store VK1:$src, addr:$dst),
5197 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5199 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5200 (truncstore node:$val, node:$ptr), [{
5201 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5204 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5205 (MOV8mr addr:$dst, GR8:$src)>;
5207 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5208 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5209 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5210 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5213 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5214 string OpcodeStr, Predicate prd> {
5215 let Predicates = [prd] in
5216 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5218 let Predicates = [prd, HasVLX] in {
5219 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5220 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5224 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5225 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5227 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5229 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5231 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5235 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;