1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // Codegen pattern for the alternative types
681 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
682 X86VectorVTInfo To, PatFrag vextract_extract,
683 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
684 vextract_for_size_first_position_lowering<From, To> {
686 let Predicates = p in
687 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
688 (To.VT (!cast<Instruction>(InstrStr#"rr")
690 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
693 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
694 ValueType EltVT64, int Opcode256> {
695 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
696 X86VectorVTInfo<16, EltVT32, VR512>,
697 X86VectorVTInfo< 4, EltVT32, VR128X>,
698 vextract128_extract>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
701 X86VectorVTInfo< 8, EltVT64, VR512>,
702 X86VectorVTInfo< 4, EltVT64, VR256X>,
703 vextract256_extract>,
704 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
705 let Predicates = [HasVLX] in
706 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
707 X86VectorVTInfo< 8, EltVT32, VR256X>,
708 X86VectorVTInfo< 4, EltVT32, VR128X>,
709 vextract128_extract>,
710 EVEX_V256, EVEX_CD8<32, CD8VT4>;
711 let Predicates = [HasVLX, HasDQI] in
712 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo< 2, EltVT64, VR128X>,
715 vextract128_extract>,
716 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
717 let Predicates = [HasDQI] in {
718 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
719 X86VectorVTInfo< 8, EltVT64, VR512>,
720 X86VectorVTInfo< 2, EltVT64, VR128X>,
721 vextract128_extract>,
722 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
723 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
724 X86VectorVTInfo<16, EltVT32, VR512>,
725 X86VectorVTInfo< 8, EltVT32, VR256X>,
726 vextract256_extract>,
727 EVEX_V512, EVEX_CD8<32, CD8VT8>;
731 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
732 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
734 // extract_subvector codegen patterns with the alternative types.
735 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
736 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
737 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
738 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
739 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
741 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
742 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
743 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
744 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
746 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
747 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
748 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
749 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
751 // Codegen pattern with the alternative types extract VEC128 from VEC512
752 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
756 // Codegen pattern with the alternative types extract VEC256 from VEC512
757 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
762 // A 128-bit subvector insert to the first 512-bit vector position
763 // is a subregister copy that needs no instruction.
764 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
765 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
766 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
768 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
769 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
770 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
772 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
774 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
776 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
778 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
781 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
782 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
783 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
784 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
785 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
786 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
787 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
789 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
790 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
791 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
792 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
794 // vextractps - extract 32 bits from XMM
795 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
796 (ins VR128X:$src1, u8imm:$src2),
797 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
798 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
801 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
802 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
803 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
805 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
807 //===---------------------------------------------------------------------===//
810 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
811 ValueType svt, X86VectorVTInfo _> {
812 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
813 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
814 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
818 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
819 (ins _.ScalarMemOp:$src),
820 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
821 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
826 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
827 AVX512VLVectorVTInfo _> {
828 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
831 let Predicates = [HasVLX] in {
832 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
837 let ExeDomain = SSEPackedSingle in {
838 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
839 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
840 let Predicates = [HasVLX] in {
841 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
842 v4f32, v4f32x_info>, EVEX_V128,
843 EVEX_CD8<32, CD8VT1>;
847 let ExeDomain = SSEPackedDouble in {
848 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
849 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
852 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
853 // Later, we can canonize broadcast instructions before ISel phase and
854 // eliminate additional patterns on ISel.
855 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
856 // representations of source
857 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
858 X86VectorVTInfo _, RegisterClass SrcRC_v,
859 RegisterClass SrcRC_s> {
860 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
861 (!cast<Instruction>(InstName##"r")
862 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
864 let AddedComplexity = 30 in {
865 def : Pat<(_.VT (vselect _.KRCWM:$mask,
866 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
867 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
868 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
870 def : Pat<(_.VT(vselect _.KRCWM:$mask,
871 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
872 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
873 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
877 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
879 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
882 let Predicates = [HasVLX] in {
883 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
884 v8f32x_info, VR128X, FR32X>;
885 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
886 v4f32x_info, VR128X, FR32X>;
887 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
888 v4f64x_info, VR128X, FR64X>;
891 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
892 (VBROADCASTSSZm addr:$src)>;
893 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
894 (VBROADCASTSDZm addr:$src)>;
896 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
897 (VBROADCASTSSZm addr:$src)>;
898 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
899 (VBROADCASTSDZm addr:$src)>;
901 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
902 RegisterClass SrcRC> {
903 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
904 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
905 "$src", "$src", []>, T8PD, EVEX;
908 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
909 RegisterClass SrcRC, Predicate prd> {
910 let Predicates = [prd] in
911 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
912 let Predicates = [prd, HasVLX] in {
913 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
914 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
918 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
920 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
922 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
924 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
927 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
928 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
930 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
931 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
933 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
934 (VPBROADCASTDrZr GR32:$src)>;
935 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
936 (VPBROADCASTQrZr GR64:$src)>;
938 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
939 (VPBROADCASTDrZr GR32:$src)>;
940 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
941 (VPBROADCASTQrZr GR64:$src)>;
943 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
944 (v16i32 immAllZerosV), (i16 GR16:$mask))),
945 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
946 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
947 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
948 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
950 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
951 X86MemOperand x86memop, PatFrag ld_frag,
952 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
954 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
957 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
958 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
960 !strconcat(OpcodeStr,
961 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
963 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
965 !strconcat(OpcodeStr,
966 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
969 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
970 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
972 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
973 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
975 !strconcat(OpcodeStr,
976 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
978 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
980 !strconcat(OpcodeStr,
981 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
982 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
983 (X86VBroadcast (ld_frag addr:$src)),
984 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
988 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
989 loadi32, VR512, v16i32, v4i32, VK16WM>,
990 EVEX_V512, EVEX_CD8<32, CD8VT1>;
991 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
992 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
993 EVEX_CD8<64, CD8VT1>;
995 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
996 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
998 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
999 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1001 (_Dst.VT (X86SubVBroadcast
1002 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
1003 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1005 !strconcat(OpcodeStr,
1006 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1008 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1010 !strconcat(OpcodeStr,
1011 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1016 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1017 v16i32_info, v4i32x_info>,
1018 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1019 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1020 v16f32_info, v4f32x_info>,
1021 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1022 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1023 v8i64_info, v4i64x_info>, VEX_W,
1024 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1025 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1026 v8f64_info, v4f64x_info>, VEX_W,
1027 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1029 let Predicates = [HasVLX] in {
1030 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1031 v8i32x_info, v4i32x_info>,
1032 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1033 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1034 v8f32x_info, v4f32x_info>,
1035 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1037 let Predicates = [HasVLX, HasDQI] in {
1038 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1039 v4i64x_info, v2i64x_info>, VEX_W,
1040 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1041 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1042 v4f64x_info, v2f64x_info>, VEX_W,
1043 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1045 let Predicates = [HasDQI] in {
1046 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1047 v8i64_info, v2i64x_info>, VEX_W,
1048 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1049 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1050 v16i32_info, v8i32x_info>,
1051 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1052 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1053 v8f64_info, v2f64x_info>, VEX_W,
1054 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1055 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1056 v16f32_info, v8f32x_info>,
1057 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1060 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
1061 (VPBROADCASTDZrr VR128X:$src)>;
1062 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
1063 (VPBROADCASTQZrr VR128X:$src)>;
1065 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1066 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1067 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1068 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1070 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1071 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1072 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1073 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1075 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
1076 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
1077 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
1078 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
1080 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
1081 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
1082 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
1083 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
1085 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1086 (VBROADCASTSSZr VR128X:$src)>;
1087 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1088 (VBROADCASTSDZr VR128X:$src)>;
1090 // Provide fallback in case the load node that is used in the patterns above
1091 // is used by additional users, which prevents the pattern selection.
1092 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1093 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1094 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1095 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1098 //===----------------------------------------------------------------------===//
1099 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1102 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1103 RegisterClass KRC> {
1104 let Predicates = [HasCDI] in
1105 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
1106 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1107 []>, EVEX, EVEX_V512;
1109 let Predicates = [HasCDI, HasVLX] in {
1110 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
1111 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1112 []>, EVEX, EVEX_V128;
1113 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
1114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1115 []>, EVEX, EVEX_V256;
1119 let Predicates = [HasCDI] in {
1120 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1122 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1126 //===----------------------------------------------------------------------===//
1127 // -- VPERM2I - 3 source operands form --
1128 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1129 SDNode OpNode, X86VectorVTInfo _> {
1130 let Constraints = "$src1 = $dst" in {
1131 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1132 (ins _.RC:$src2, _.RC:$src3),
1133 OpcodeStr, "$src3, $src2", "$src2, $src3",
1134 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1138 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1139 (ins _.RC:$src2, _.MemOp:$src3),
1140 OpcodeStr, "$src3, $src2", "$src2, $src3",
1141 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1142 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1143 EVEX_4V, AVX5128IBase;
1146 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1147 SDNode OpNode, X86VectorVTInfo _> {
1148 let mayLoad = 1, Constraints = "$src1 = $dst" in
1149 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1150 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1151 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1152 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1153 (_.VT (OpNode _.RC:$src1,
1154 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1155 AVX5128IBase, EVEX_4V, EVEX_B;
1158 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1159 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1160 let Predicates = [HasAVX512] in
1161 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1162 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1163 let Predicates = [HasVLX] in {
1164 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1165 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1167 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1168 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1172 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1173 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1174 let Predicates = [HasBWI] in
1175 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1176 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1178 let Predicates = [HasBWI, HasVLX] in {
1179 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1180 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1182 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1183 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1187 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1188 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1189 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1190 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1191 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1192 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1193 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1194 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1196 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1197 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1198 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1199 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1200 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1201 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1202 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1203 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1205 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1206 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1207 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1208 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1210 //===----------------------------------------------------------------------===//
1211 // AVX-512 - BLEND using mask
1213 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1214 let ExeDomain = _.ExeDomain in {
1215 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1216 (ins _.RC:$src1, _.RC:$src2),
1217 !strconcat(OpcodeStr,
1218 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1220 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1221 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1222 !strconcat(OpcodeStr,
1223 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1224 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1225 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1226 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1227 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1228 !strconcat(OpcodeStr,
1229 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1230 []>, EVEX_4V, EVEX_KZ;
1231 let mayLoad = 1 in {
1232 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1233 (ins _.RC:$src1, _.MemOp:$src2),
1234 !strconcat(OpcodeStr,
1235 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1236 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1237 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1238 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1239 !strconcat(OpcodeStr,
1240 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1241 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1242 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1243 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1244 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1245 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1246 !strconcat(OpcodeStr,
1247 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1248 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1252 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1254 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1255 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1256 !strconcat(OpcodeStr,
1257 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1258 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1259 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1260 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1261 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1263 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1264 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1265 !strconcat(OpcodeStr,
1266 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1267 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1268 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1272 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1273 AVX512VLVectorVTInfo VTInfo> {
1274 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1275 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1277 let Predicates = [HasVLX] in {
1278 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1279 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1280 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1281 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1285 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1286 AVX512VLVectorVTInfo VTInfo> {
1287 let Predicates = [HasBWI] in
1288 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1290 let Predicates = [HasBWI, HasVLX] in {
1291 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1292 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1297 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1298 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1299 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1300 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1301 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1302 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1305 let Predicates = [HasAVX512] in {
1306 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1307 (v8f32 VR256X:$src2))),
1309 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1310 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1311 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1313 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1314 (v8i32 VR256X:$src2))),
1316 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1317 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1320 //===----------------------------------------------------------------------===//
1321 // Compare Instructions
1322 //===----------------------------------------------------------------------===//
1324 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1326 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1328 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1330 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1331 "vcmp${cc}"#_.Suffix,
1332 "$src2, $src1", "$src1, $src2",
1333 (OpNode (_.VT _.RC:$src1),
1337 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1339 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1340 "vcmp${cc}"#_.Suffix,
1341 "$src2, $src1", "$src1, $src2",
1342 (OpNode (_.VT _.RC:$src1),
1343 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1344 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1346 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1348 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1349 "vcmp${cc}"#_.Suffix,
1350 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1351 (OpNodeRnd (_.VT _.RC:$src1),
1354 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1355 // Accept explicit immediate argument form instead of comparison code.
1356 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1357 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1359 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1361 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1362 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1364 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1366 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1367 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1369 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1371 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1373 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1375 }// let isAsmParserOnly = 1, hasSideEffects = 0
1377 let isCodeGenOnly = 1 in {
1378 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1379 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1380 !strconcat("vcmp${cc}", _.Suffix,
1381 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1382 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1385 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1387 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1389 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1390 !strconcat("vcmp${cc}", _.Suffix,
1391 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1392 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1393 (_.ScalarLdFrag addr:$src2),
1395 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1399 let Predicates = [HasAVX512] in {
1400 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1402 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1403 AVX512XDIi8Base, VEX_W;
1406 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1407 X86VectorVTInfo _> {
1408 def rr : AVX512BI<opc, MRMSrcReg,
1409 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1410 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1411 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1412 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1414 def rm : AVX512BI<opc, MRMSrcMem,
1415 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1417 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1418 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1419 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1420 def rrk : AVX512BI<opc, MRMSrcReg,
1421 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1423 "$dst {${mask}}, $src1, $src2}"),
1424 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1425 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1426 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1428 def rmk : AVX512BI<opc, MRMSrcMem,
1429 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1430 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1431 "$dst {${mask}}, $src1, $src2}"),
1432 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1433 (OpNode (_.VT _.RC:$src1),
1435 (_.LdFrag addr:$src2))))))],
1436 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1439 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1440 X86VectorVTInfo _> :
1441 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1442 let mayLoad = 1 in {
1443 def rmb : AVX512BI<opc, MRMSrcMem,
1444 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1445 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1446 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1447 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1448 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1449 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1450 def rmbk : AVX512BI<opc, MRMSrcMem,
1451 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1452 _.ScalarMemOp:$src2),
1453 !strconcat(OpcodeStr,
1454 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1455 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1456 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1457 (OpNode (_.VT _.RC:$src1),
1459 (_.ScalarLdFrag addr:$src2)))))],
1460 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1464 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1465 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1466 let Predicates = [prd] in
1467 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1470 let Predicates = [prd, HasVLX] in {
1471 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1473 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1478 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1479 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1481 let Predicates = [prd] in
1482 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1485 let Predicates = [prd, HasVLX] in {
1486 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1488 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1493 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1494 avx512vl_i8_info, HasBWI>,
1497 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1498 avx512vl_i16_info, HasBWI>,
1499 EVEX_CD8<16, CD8VF>;
1501 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1502 avx512vl_i32_info, HasAVX512>,
1503 EVEX_CD8<32, CD8VF>;
1505 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1506 avx512vl_i64_info, HasAVX512>,
1507 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1509 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1510 avx512vl_i8_info, HasBWI>,
1513 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1514 avx512vl_i16_info, HasBWI>,
1515 EVEX_CD8<16, CD8VF>;
1517 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1518 avx512vl_i32_info, HasAVX512>,
1519 EVEX_CD8<32, CD8VF>;
1521 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1522 avx512vl_i64_info, HasAVX512>,
1523 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1525 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1526 (COPY_TO_REGCLASS (VPCMPGTDZrr
1527 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1528 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1530 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1531 (COPY_TO_REGCLASS (VPCMPEQDZrr
1532 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1533 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1535 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1536 X86VectorVTInfo _> {
1537 def rri : AVX512AIi8<opc, MRMSrcReg,
1538 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1539 !strconcat("vpcmp${cc}", Suffix,
1540 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1541 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1543 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1545 def rmi : AVX512AIi8<opc, MRMSrcMem,
1546 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1547 !strconcat("vpcmp${cc}", Suffix,
1548 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1549 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1550 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1552 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1553 def rrik : AVX512AIi8<opc, MRMSrcReg,
1554 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1556 !strconcat("vpcmp${cc}", Suffix,
1557 "\t{$src2, $src1, $dst {${mask}}|",
1558 "$dst {${mask}}, $src1, $src2}"),
1559 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1560 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1562 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1564 def rmik : AVX512AIi8<opc, MRMSrcMem,
1565 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1567 !strconcat("vpcmp${cc}", Suffix,
1568 "\t{$src2, $src1, $dst {${mask}}|",
1569 "$dst {${mask}}, $src1, $src2}"),
1570 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1571 (OpNode (_.VT _.RC:$src1),
1572 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1574 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1576 // Accept explicit immediate argument form instead of comparison code.
1577 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1578 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1579 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1580 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1581 "$dst, $src1, $src2, $cc}"),
1582 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1584 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1585 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1586 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1587 "$dst, $src1, $src2, $cc}"),
1588 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1589 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1590 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1592 !strconcat("vpcmp", Suffix,
1593 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1594 "$dst {${mask}}, $src1, $src2, $cc}"),
1595 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1597 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1598 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1600 !strconcat("vpcmp", Suffix,
1601 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1602 "$dst {${mask}}, $src1, $src2, $cc}"),
1603 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1607 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1608 X86VectorVTInfo _> :
1609 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1610 def rmib : AVX512AIi8<opc, MRMSrcMem,
1611 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1613 !strconcat("vpcmp${cc}", Suffix,
1614 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1615 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1616 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1617 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1619 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1620 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1621 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1622 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1623 !strconcat("vpcmp${cc}", Suffix,
1624 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1625 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1626 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1627 (OpNode (_.VT _.RC:$src1),
1628 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1630 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1632 // Accept explicit immediate argument form instead of comparison code.
1633 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1634 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1635 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1637 !strconcat("vpcmp", Suffix,
1638 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1639 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1640 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1641 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1642 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1643 _.ScalarMemOp:$src2, u8imm:$cc),
1644 !strconcat("vpcmp", Suffix,
1645 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1646 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1647 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1651 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1652 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1653 let Predicates = [prd] in
1654 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1656 let Predicates = [prd, HasVLX] in {
1657 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1658 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1662 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1663 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1664 let Predicates = [prd] in
1665 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1668 let Predicates = [prd, HasVLX] in {
1669 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1671 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1676 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1677 HasBWI>, EVEX_CD8<8, CD8VF>;
1678 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1679 HasBWI>, EVEX_CD8<8, CD8VF>;
1681 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1682 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1683 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1684 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1686 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1687 HasAVX512>, EVEX_CD8<32, CD8VF>;
1688 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1689 HasAVX512>, EVEX_CD8<32, CD8VF>;
1691 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1692 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1693 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1694 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1696 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1698 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1699 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1700 "vcmp${cc}"#_.Suffix,
1701 "$src2, $src1", "$src1, $src2",
1702 (X86cmpm (_.VT _.RC:$src1),
1706 let mayLoad = 1 in {
1707 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1708 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1709 "vcmp${cc}"#_.Suffix,
1710 "$src2, $src1", "$src1, $src2",
1711 (X86cmpm (_.VT _.RC:$src1),
1712 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1715 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1717 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1718 "vcmp${cc}"#_.Suffix,
1719 "${src2}"##_.BroadcastStr##", $src1",
1720 "$src1, ${src2}"##_.BroadcastStr,
1721 (X86cmpm (_.VT _.RC:$src1),
1722 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1725 // Accept explicit immediate argument form instead of comparison code.
1726 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1727 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1729 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1731 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1733 let mayLoad = 1 in {
1734 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1736 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1738 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1740 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1742 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1744 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1745 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1750 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1751 // comparison code form (VCMP[EQ/LT/LE/...]
1752 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1753 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1754 "vcmp${cc}"#_.Suffix,
1755 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1756 (X86cmpmRnd (_.VT _.RC:$src1),
1759 (i32 FROUND_NO_EXC))>, EVEX_B;
1761 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1762 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1764 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1766 "$cc,{sae}, $src2, $src1",
1767 "$src1, $src2,{sae}, $cc">, EVEX_B;
1771 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1772 let Predicates = [HasAVX512] in {
1773 defm Z : avx512_vcmp_common<_.info512>,
1774 avx512_vcmp_sae<_.info512>, EVEX_V512;
1777 let Predicates = [HasAVX512,HasVLX] in {
1778 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1779 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1783 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1784 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1785 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1786 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1788 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1789 (COPY_TO_REGCLASS (VCMPPSZrri
1790 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1791 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1793 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1794 (COPY_TO_REGCLASS (VPCMPDZrri
1795 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1796 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1798 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1799 (COPY_TO_REGCLASS (VPCMPUDZrri
1800 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1801 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1804 // ----------------------------------------------------------------
1806 //handle fpclass instruction mask = op(reg_scalar,imm)
1807 // op(mem_scalar,imm)
1808 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1809 X86VectorVTInfo _, Predicate prd> {
1810 let Predicates = [prd] in {
1811 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1812 (ins _.RC:$src1, i32u8imm:$src2),
1813 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1814 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1815 (i32 imm:$src2)))], NoItinerary>;
1816 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1817 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1818 OpcodeStr##_.Suffix#
1819 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1820 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1821 (OpNode (_.VT _.RC:$src1),
1822 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1823 let mayLoad = 1, AddedComplexity = 20 in {
1824 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1825 (ins _.MemOp:$src1, i32u8imm:$src2),
1826 OpcodeStr##_.Suffix##
1827 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1829 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1830 (i32 imm:$src2)))], NoItinerary>;
1831 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1832 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1833 OpcodeStr##_.Suffix##
1834 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1835 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1836 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1837 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1842 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1843 // fpclass(reg_vec, mem_vec, imm)
1844 // fpclass(reg_vec, broadcast(eltVt), imm)
1845 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1846 X86VectorVTInfo _, string mem, string broadcast>{
1847 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1848 (ins _.RC:$src1, i32u8imm:$src2),
1849 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1850 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1851 (i32 imm:$src2)))], NoItinerary>;
1852 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1853 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1854 OpcodeStr##_.Suffix#
1855 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1856 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1857 (OpNode (_.VT _.RC:$src1),
1858 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1859 let mayLoad = 1 in {
1860 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1861 (ins _.MemOp:$src1, i32u8imm:$src2),
1862 OpcodeStr##_.Suffix##mem#
1863 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1864 [(set _.KRC:$dst,(OpNode
1865 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1866 (i32 imm:$src2)))], NoItinerary>;
1867 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1868 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1869 OpcodeStr##_.Suffix##mem#
1870 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1871 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1872 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1873 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1874 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1875 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1876 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1877 _.BroadcastStr##", $dst | $dst, ${src1}"
1878 ##_.BroadcastStr##", $src2}",
1879 [(set _.KRC:$dst,(OpNode
1880 (_.VT (X86VBroadcast
1881 (_.ScalarLdFrag addr:$src1))),
1882 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1883 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1884 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1885 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1886 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1887 _.BroadcastStr##", $src2}",
1888 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1889 (_.VT (X86VBroadcast
1890 (_.ScalarLdFrag addr:$src1))),
1891 (i32 imm:$src2))))], NoItinerary>,
1896 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1897 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1899 let Predicates = [prd] in {
1900 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1901 broadcast>, EVEX_V512;
1903 let Predicates = [prd, HasVLX] in {
1904 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1905 broadcast>, EVEX_V128;
1906 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1907 broadcast>, EVEX_V256;
1911 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1912 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1913 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1914 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1915 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1916 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1917 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1918 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1919 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1920 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
1923 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
1924 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
1926 //-----------------------------------------------------------------
1927 // Mask register copy, including
1928 // - copy between mask registers
1929 // - load/store mask registers
1930 // - copy from GPR to mask register and vice versa
1932 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1933 string OpcodeStr, RegisterClass KRC,
1934 ValueType vvt, X86MemOperand x86memop> {
1935 let hasSideEffects = 0 in {
1936 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1937 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1939 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1940 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1941 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1943 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1944 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1945 [(store KRC:$src, addr:$dst)]>;
1949 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1951 RegisterClass KRC, RegisterClass GRC> {
1952 let hasSideEffects = 0 in {
1953 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1954 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1955 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1956 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1960 let Predicates = [HasDQI] in
1961 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1962 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1965 let Predicates = [HasAVX512] in
1966 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1967 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1970 let Predicates = [HasBWI] in {
1971 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1973 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1977 let Predicates = [HasBWI] in {
1978 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1980 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1984 // GR from/to mask register
1985 let Predicates = [HasDQI] in {
1986 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1987 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1988 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1989 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1991 let Predicates = [HasAVX512] in {
1992 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1993 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1994 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1995 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1997 let Predicates = [HasBWI] in {
1998 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1999 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2001 let Predicates = [HasBWI] in {
2002 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2003 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2007 let Predicates = [HasDQI] in {
2008 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2009 (KMOVBmk addr:$dst, VK8:$src)>;
2010 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2011 (KMOVBkm addr:$src)>;
2013 def : Pat<(store VK4:$src, addr:$dst),
2014 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2015 def : Pat<(store VK2:$src, addr:$dst),
2016 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2018 let Predicates = [HasAVX512, NoDQI] in {
2019 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2020 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2021 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2022 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2024 let Predicates = [HasAVX512] in {
2025 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2026 (KMOVWmk addr:$dst, VK16:$src)>;
2027 def : Pat<(i1 (load addr:$src)),
2028 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2029 (MOV8rm addr:$src), sub_8bit)),
2031 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2032 (KMOVWkm addr:$src)>;
2034 let Predicates = [HasBWI] in {
2035 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2036 (KMOVDmk addr:$dst, VK32:$src)>;
2037 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2038 (KMOVDkm addr:$src)>;
2040 let Predicates = [HasBWI] in {
2041 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2042 (KMOVQmk addr:$dst, VK64:$src)>;
2043 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2044 (KMOVQkm addr:$src)>;
2047 let Predicates = [HasAVX512] in {
2048 def : Pat<(i1 (trunc (i64 GR64:$src))),
2049 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2052 def : Pat<(i1 (trunc (i32 GR32:$src))),
2053 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2055 def : Pat<(i1 (trunc (i8 GR8:$src))),
2057 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2059 def : Pat<(i1 (trunc (i16 GR16:$src))),
2061 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2064 def : Pat<(i32 (zext VK1:$src)),
2065 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2066 def : Pat<(i32 (anyext VK1:$src)),
2067 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2069 def : Pat<(i8 (zext VK1:$src)),
2072 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2073 def : Pat<(i8 (anyext VK1:$src)),
2075 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2077 def : Pat<(i64 (zext VK1:$src)),
2078 (AND64ri8 (SUBREG_TO_REG (i64 0),
2079 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2080 def : Pat<(i16 (zext VK1:$src)),
2082 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2084 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2085 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2086 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2087 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2089 let Predicates = [HasBWI] in {
2090 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2091 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2092 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2093 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2097 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2098 let Predicates = [HasAVX512, NoDQI] in {
2099 // GR from/to 8-bit mask without native support
2100 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2102 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2103 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2105 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2109 let Predicates = [HasAVX512] in {
2110 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2111 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2112 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2113 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2115 let Predicates = [HasBWI] in {
2116 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2117 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2118 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2119 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2122 // Mask unary operation
2124 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2125 RegisterClass KRC, SDPatternOperator OpNode,
2127 let Predicates = [prd] in
2128 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2129 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2130 [(set KRC:$dst, (OpNode KRC:$src))]>;
2133 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2134 SDPatternOperator OpNode> {
2135 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2137 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2138 HasAVX512>, VEX, PS;
2139 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2140 HasBWI>, VEX, PD, VEX_W;
2141 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2142 HasBWI>, VEX, PS, VEX_W;
2145 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2147 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2148 let Predicates = [HasAVX512] in
2149 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2151 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2152 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2154 defm : avx512_mask_unop_int<"knot", "KNOT">;
2156 let Predicates = [HasDQI] in
2157 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2158 let Predicates = [HasAVX512] in
2159 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2160 let Predicates = [HasBWI] in
2161 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2162 let Predicates = [HasBWI] in
2163 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2165 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2166 let Predicates = [HasAVX512, NoDQI] in {
2167 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2168 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2169 def : Pat<(not VK8:$src),
2171 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2173 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2174 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2175 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2176 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2178 // Mask binary operation
2179 // - KAND, KANDN, KOR, KXNOR, KXOR
2180 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2181 RegisterClass KRC, SDPatternOperator OpNode,
2182 Predicate prd, bit IsCommutable> {
2183 let Predicates = [prd], isCommutable = IsCommutable in
2184 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2185 !strconcat(OpcodeStr,
2186 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2187 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2190 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2191 SDPatternOperator OpNode, bit IsCommutable,
2192 Predicate prdW = HasAVX512> {
2193 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2194 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2195 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2196 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2197 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2198 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2199 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2200 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2203 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2204 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2206 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2207 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2208 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2209 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2210 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2211 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2213 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2214 let Predicates = [HasAVX512] in
2215 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2216 (i16 GR16:$src1), (i16 GR16:$src2)),
2217 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2218 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2219 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2222 defm : avx512_mask_binop_int<"kand", "KAND">;
2223 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2224 defm : avx512_mask_binop_int<"kor", "KOR">;
2225 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2226 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2228 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2229 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2230 // for the DQI set, this type is legal and KxxxB instruction is used
2231 let Predicates = [NoDQI] in
2232 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2234 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2235 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2237 // All types smaller than 8 bits require conversion anyway
2238 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2239 (COPY_TO_REGCLASS (Inst
2240 (COPY_TO_REGCLASS VK1:$src1, VK16),
2241 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2242 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2243 (COPY_TO_REGCLASS (Inst
2244 (COPY_TO_REGCLASS VK2:$src1, VK16),
2245 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2246 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2247 (COPY_TO_REGCLASS (Inst
2248 (COPY_TO_REGCLASS VK4:$src1, VK16),
2249 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2252 defm : avx512_binop_pat<and, KANDWrr>;
2253 defm : avx512_binop_pat<andn, KANDNWrr>;
2254 defm : avx512_binop_pat<or, KORWrr>;
2255 defm : avx512_binop_pat<xnor, KXNORWrr>;
2256 defm : avx512_binop_pat<xor, KXORWrr>;
2258 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2259 (KXNORWrr VK16:$src1, VK16:$src2)>;
2260 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2261 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2262 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2263 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2264 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2265 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2267 let Predicates = [NoDQI] in
2268 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2269 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2270 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2272 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2273 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2274 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2276 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2277 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2278 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2280 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2281 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2282 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2285 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2286 RegisterClass KRCSrc, Predicate prd> {
2287 let Predicates = [prd] in {
2288 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2289 (ins KRC:$src1, KRC:$src2),
2290 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2293 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2294 (!cast<Instruction>(NAME##rr)
2295 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2296 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2300 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2301 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2302 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2304 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2305 let Predicates = [HasAVX512] in
2306 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2307 (i16 GR16:$src1), (i16 GR16:$src2)),
2308 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2309 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2310 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2312 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2315 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2316 SDNode OpNode, Predicate prd> {
2317 let Predicates = [prd], Defs = [EFLAGS] in
2318 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2319 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2320 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2323 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2324 Predicate prdW = HasAVX512> {
2325 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2327 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2329 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2331 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2335 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2336 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2339 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2341 let Predicates = [HasAVX512] in
2342 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2343 !strconcat(OpcodeStr,
2344 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2345 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2348 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2350 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2352 let Predicates = [HasDQI] in
2353 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2355 let Predicates = [HasBWI] in {
2356 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2358 let Predicates = [HasDQI] in
2359 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2364 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2365 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2367 // Mask setting all 0s or 1s
2368 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2369 let Predicates = [HasAVX512] in
2370 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2371 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2372 [(set KRC:$dst, (VT Val))]>;
2375 multiclass avx512_mask_setop_w<PatFrag Val> {
2376 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2377 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2378 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2379 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2382 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2383 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2385 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2386 let Predicates = [HasAVX512] in {
2387 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2388 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2389 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2390 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2391 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2392 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2393 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2395 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2396 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2398 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2399 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2401 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2402 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2404 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2405 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2407 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2408 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2410 let Predicates = [HasVLX] in {
2411 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2412 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2413 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2414 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2415 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2416 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2417 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2418 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2419 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2420 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2423 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2424 (v8i1 (COPY_TO_REGCLASS
2425 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2426 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2428 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2429 (v8i1 (COPY_TO_REGCLASS
2430 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2431 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2433 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2434 (v4i1 (COPY_TO_REGCLASS
2435 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2436 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2438 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2439 (v4i1 (COPY_TO_REGCLASS
2440 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2441 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2443 //===----------------------------------------------------------------------===//
2444 // AVX-512 - Aligned and unaligned load and store
2448 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2449 PatFrag ld_frag, PatFrag mload,
2450 bit IsReMaterializable = 1> {
2451 let hasSideEffects = 0 in {
2452 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2453 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2455 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2456 (ins _.KRCWM:$mask, _.RC:$src),
2457 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2458 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2461 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2462 SchedRW = [WriteLoad] in
2463 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2464 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2465 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2468 let Constraints = "$src0 = $dst" in {
2469 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2470 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2471 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2472 "${dst} {${mask}}, $src1}"),
2473 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2475 (_.VT _.RC:$src0))))], _.ExeDomain>,
2477 let mayLoad = 1, SchedRW = [WriteLoad] in
2478 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2479 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2480 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2481 "${dst} {${mask}}, $src1}"),
2482 [(set _.RC:$dst, (_.VT
2483 (vselect _.KRCWM:$mask,
2484 (_.VT (bitconvert (ld_frag addr:$src1))),
2485 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2487 let mayLoad = 1, SchedRW = [WriteLoad] in
2488 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2489 (ins _.KRCWM:$mask, _.MemOp:$src),
2490 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2491 "${dst} {${mask}} {z}, $src}",
2492 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2493 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2494 _.ExeDomain>, EVEX, EVEX_KZ;
2496 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2497 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2499 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2500 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2502 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2503 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2504 _.KRCWM:$mask, addr:$ptr)>;
2507 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2508 AVX512VLVectorVTInfo _,
2510 bit IsReMaterializable = 1> {
2511 let Predicates = [prd] in
2512 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2513 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2515 let Predicates = [prd, HasVLX] in {
2516 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2517 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2518 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2519 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2523 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2524 AVX512VLVectorVTInfo _,
2526 bit IsReMaterializable = 1> {
2527 let Predicates = [prd] in
2528 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2529 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2531 let Predicates = [prd, HasVLX] in {
2532 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2533 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2534 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2535 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2539 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2540 PatFrag st_frag, PatFrag mstore> {
2541 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2542 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2543 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2545 let Constraints = "$src1 = $dst" in
2546 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2547 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2549 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2550 [], _.ExeDomain>, EVEX, EVEX_K;
2551 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2552 (ins _.KRCWM:$mask, _.RC:$src),
2554 "\t{$src, ${dst} {${mask}} {z}|" #
2555 "${dst} {${mask}} {z}, $src}",
2556 [], _.ExeDomain>, EVEX, EVEX_KZ;
2558 let mayStore = 1 in {
2559 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2560 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2561 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2562 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2563 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2564 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2565 [], _.ExeDomain>, EVEX, EVEX_K;
2568 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2569 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2570 _.KRCWM:$mask, _.RC:$src)>;
2574 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2575 AVX512VLVectorVTInfo _, Predicate prd> {
2576 let Predicates = [prd] in
2577 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2578 masked_store_unaligned>, EVEX_V512;
2580 let Predicates = [prd, HasVLX] in {
2581 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2582 masked_store_unaligned>, EVEX_V256;
2583 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2584 masked_store_unaligned>, EVEX_V128;
2588 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2589 AVX512VLVectorVTInfo _, Predicate prd> {
2590 let Predicates = [prd] in
2591 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2592 masked_store_aligned512>, EVEX_V512;
2594 let Predicates = [prd, HasVLX] in {
2595 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2596 masked_store_aligned256>, EVEX_V256;
2597 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2598 masked_store_aligned128>, EVEX_V128;
2602 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2604 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2605 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2607 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2609 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2610 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2612 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2613 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2614 PS, EVEX_CD8<32, CD8VF>;
2616 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2617 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2618 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2620 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2621 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2622 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2624 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2625 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2626 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2628 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2629 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2630 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2632 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2633 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2634 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2636 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2637 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2638 (VMOVAPDZrm addr:$ptr)>;
2640 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2641 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2642 (VMOVAPSZrm addr:$ptr)>;
2644 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2646 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2648 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2650 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2653 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2655 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2657 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2659 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2662 let Predicates = [HasAVX512, NoVLX] in {
2663 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2664 (VMOVUPSZmrk addr:$ptr,
2665 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2666 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2668 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2669 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2670 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2672 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2673 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2674 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2675 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2678 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2680 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2681 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2683 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2685 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2686 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2688 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2689 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2690 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2692 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2693 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2694 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2696 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2697 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2698 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2700 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2701 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2702 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2704 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2705 (v16i32 immAllZerosV), GR16:$mask)),
2706 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2708 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2709 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2710 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2712 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2714 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2716 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2718 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2721 let AddedComplexity = 20 in {
2722 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2723 (bc_v8i64 (v16i32 immAllZerosV)))),
2724 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2726 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2727 (v8i64 VR512:$src))),
2728 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2731 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2732 (v16i32 immAllZerosV))),
2733 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2735 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2736 (v16i32 VR512:$src))),
2737 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2740 let Predicates = [HasAVX512, NoVLX] in {
2741 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2742 (VMOVDQU32Zmrk addr:$ptr,
2743 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2744 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2746 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2747 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2748 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2751 // Move Int Doubleword to Packed Double Int
2753 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2754 "vmovd\t{$src, $dst|$dst, $src}",
2756 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2758 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2759 "vmovd\t{$src, $dst|$dst, $src}",
2761 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2762 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2763 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2764 "vmovq\t{$src, $dst|$dst, $src}",
2766 (v2i64 (scalar_to_vector GR64:$src)))],
2767 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2768 let isCodeGenOnly = 1 in {
2769 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2770 "vmovq\t{$src, $dst|$dst, $src}",
2771 [(set FR64:$dst, (bitconvert GR64:$src))],
2772 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2773 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2774 "vmovq\t{$src, $dst|$dst, $src}",
2775 [(set GR64:$dst, (bitconvert FR64:$src))],
2776 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2778 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2779 "vmovq\t{$src, $dst|$dst, $src}",
2780 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2781 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2782 EVEX_CD8<64, CD8VT1>;
2784 // Move Int Doubleword to Single Scalar
2786 let isCodeGenOnly = 1 in {
2787 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2788 "vmovd\t{$src, $dst|$dst, $src}",
2789 [(set FR32X:$dst, (bitconvert GR32:$src))],
2790 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2792 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2793 "vmovd\t{$src, $dst|$dst, $src}",
2794 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2795 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2798 // Move doubleword from xmm register to r/m32
2800 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2801 "vmovd\t{$src, $dst|$dst, $src}",
2802 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2803 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2805 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2806 (ins i32mem:$dst, VR128X:$src),
2807 "vmovd\t{$src, $dst|$dst, $src}",
2808 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2809 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2810 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2812 // Move quadword from xmm1 register to r/m64
2814 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2815 "vmovq\t{$src, $dst|$dst, $src}",
2816 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2818 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2819 Requires<[HasAVX512, In64BitMode]>;
2821 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2822 (ins i64mem:$dst, VR128X:$src),
2823 "vmovq\t{$src, $dst|$dst, $src}",
2824 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2825 addr:$dst)], IIC_SSE_MOVDQ>,
2826 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2827 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2829 // Move Scalar Single to Double Int
2831 let isCodeGenOnly = 1 in {
2832 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2834 "vmovd\t{$src, $dst|$dst, $src}",
2835 [(set GR32:$dst, (bitconvert FR32X:$src))],
2836 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2837 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2838 (ins i32mem:$dst, FR32X:$src),
2839 "vmovd\t{$src, $dst|$dst, $src}",
2840 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2841 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2844 // Move Quadword Int to Packed Quadword Int
2846 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2848 "vmovq\t{$src, $dst|$dst, $src}",
2850 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2851 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2853 //===----------------------------------------------------------------------===//
2854 // AVX-512 MOVSS, MOVSD
2855 //===----------------------------------------------------------------------===//
2857 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2858 SDNode OpNode, ValueType vt,
2859 X86MemOperand x86memop, PatFrag mem_pat> {
2860 let hasSideEffects = 0 in {
2861 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2862 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2863 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2864 (scalar_to_vector RC:$src2))))],
2865 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2866 let Constraints = "$src1 = $dst" in
2867 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2868 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2870 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2871 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2872 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2873 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2874 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2876 let mayStore = 1 in {
2877 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2878 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2879 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2881 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2882 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2883 [], IIC_SSE_MOV_S_MR>,
2884 EVEX, VEX_LIG, EVEX_K;
2886 } //hasSideEffects = 0
2889 let ExeDomain = SSEPackedSingle in
2890 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2891 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2893 let ExeDomain = SSEPackedDouble in
2894 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2895 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2897 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2898 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2899 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2901 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2902 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2903 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2905 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2906 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2907 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2909 // For the disassembler
2910 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2911 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2912 (ins VR128X:$src1, FR32X:$src2),
2913 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2915 XS, EVEX_4V, VEX_LIG;
2916 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2917 (ins VR128X:$src1, FR64X:$src2),
2918 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2920 XD, EVEX_4V, VEX_LIG, VEX_W;
2923 let Predicates = [HasAVX512] in {
2924 let AddedComplexity = 15 in {
2925 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2926 // MOVS{S,D} to the lower bits.
2927 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2928 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2929 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2930 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2931 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2932 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2933 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2934 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2936 // Move low f32 and clear high bits.
2937 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2938 (SUBREG_TO_REG (i32 0),
2939 (VMOVSSZrr (v4f32 (V_SET0)),
2940 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2941 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2942 (SUBREG_TO_REG (i32 0),
2943 (VMOVSSZrr (v4i32 (V_SET0)),
2944 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2947 let AddedComplexity = 20 in {
2948 // MOVSSrm zeros the high parts of the register; represent this
2949 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2950 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2951 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2952 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2953 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2954 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2955 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2957 // MOVSDrm zeros the high parts of the register; represent this
2958 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2959 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2960 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2961 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2962 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2963 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2964 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2965 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2966 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2967 def : Pat<(v2f64 (X86vzload addr:$src)),
2968 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2970 // Represent the same patterns above but in the form they appear for
2972 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2973 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2974 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2975 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2976 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2977 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2978 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2979 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2980 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2982 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2983 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2984 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2985 FR32X:$src)), sub_xmm)>;
2986 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2987 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2988 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2989 FR64X:$src)), sub_xmm)>;
2990 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2991 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2992 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2994 // Move low f64 and clear high bits.
2995 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2996 (SUBREG_TO_REG (i32 0),
2997 (VMOVSDZrr (v2f64 (V_SET0)),
2998 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3000 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3001 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3002 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3004 // Extract and store.
3005 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3007 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3008 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3010 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3012 // Shuffle with VMOVSS
3013 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3014 (VMOVSSZrr (v4i32 VR128X:$src1),
3015 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3016 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3017 (VMOVSSZrr (v4f32 VR128X:$src1),
3018 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3021 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3022 (SUBREG_TO_REG (i32 0),
3023 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3024 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3026 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3027 (SUBREG_TO_REG (i32 0),
3028 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3029 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3032 // Shuffle with VMOVSD
3033 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3034 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3035 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3036 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3037 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3038 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3039 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3040 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3043 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3044 (SUBREG_TO_REG (i32 0),
3045 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3046 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3048 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3049 (SUBREG_TO_REG (i32 0),
3050 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3051 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3054 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3055 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3056 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3057 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3058 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3059 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3060 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3061 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3064 let AddedComplexity = 15 in
3065 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3067 "vmovq\t{$src, $dst|$dst, $src}",
3068 [(set VR128X:$dst, (v2i64 (X86vzmovl
3069 (v2i64 VR128X:$src))))],
3070 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3072 let AddedComplexity = 20 in
3073 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3075 "vmovq\t{$src, $dst|$dst, $src}",
3076 [(set VR128X:$dst, (v2i64 (X86vzmovl
3077 (loadv2i64 addr:$src))))],
3078 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3079 EVEX_CD8<8, CD8VT8>;
3081 let Predicates = [HasAVX512] in {
3082 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3083 let AddedComplexity = 20 in {
3084 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3085 (VMOVDI2PDIZrm addr:$src)>;
3086 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3087 (VMOV64toPQIZrr GR64:$src)>;
3088 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3089 (VMOVDI2PDIZrr GR32:$src)>;
3091 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3092 (VMOVDI2PDIZrm addr:$src)>;
3093 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3094 (VMOVDI2PDIZrm addr:$src)>;
3095 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3096 (VMOVZPQILo2PQIZrm addr:$src)>;
3097 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3098 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3099 def : Pat<(v2i64 (X86vzload addr:$src)),
3100 (VMOVZPQILo2PQIZrm addr:$src)>;
3103 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3104 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3105 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3106 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3107 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3108 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3109 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3112 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3113 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3115 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3116 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3118 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3119 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3121 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3122 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3124 //===----------------------------------------------------------------------===//
3125 // AVX-512 - Non-temporals
3126 //===----------------------------------------------------------------------===//
3127 let SchedRW = [WriteLoad] in {
3128 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3129 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3130 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3131 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3132 EVEX_CD8<64, CD8VF>;
3134 let Predicates = [HasAVX512, HasVLX] in {
3135 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3137 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3138 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3139 EVEX_CD8<64, CD8VF>;
3141 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3143 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3144 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3145 EVEX_CD8<64, CD8VF>;
3149 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3150 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3151 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3152 let SchedRW = [WriteStore], mayStore = 1,
3153 AddedComplexity = 400 in
3154 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3155 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3156 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3159 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3160 string elty, string elsz, string vsz512,
3161 string vsz256, string vsz128, Domain d,
3162 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3163 let Predicates = [prd] in
3164 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3165 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3166 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3169 let Predicates = [prd, HasVLX] in {
3170 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3171 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3172 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3175 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3176 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3177 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3182 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3183 "i", "64", "8", "4", "2", SSEPackedInt,
3184 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3186 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3187 "f", "64", "8", "4", "2", SSEPackedDouble,
3188 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3190 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3191 "f", "32", "16", "8", "4", SSEPackedSingle,
3192 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3194 //===----------------------------------------------------------------------===//
3195 // AVX-512 - Integer arithmetic
3197 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3198 X86VectorVTInfo _, OpndItins itins,
3199 bit IsCommutable = 0> {
3200 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3201 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3202 "$src2, $src1", "$src1, $src2",
3203 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3204 itins.rr, IsCommutable>,
3205 AVX512BIBase, EVEX_4V;
3208 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3209 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3210 "$src2, $src1", "$src1, $src2",
3211 (_.VT (OpNode _.RC:$src1,
3212 (bitconvert (_.LdFrag addr:$src2)))),
3214 AVX512BIBase, EVEX_4V;
3217 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3218 X86VectorVTInfo _, OpndItins itins,
3219 bit IsCommutable = 0> :
3220 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3222 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3223 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3224 "${src2}"##_.BroadcastStr##", $src1",
3225 "$src1, ${src2}"##_.BroadcastStr,
3226 (_.VT (OpNode _.RC:$src1,
3228 (_.ScalarLdFrag addr:$src2)))),
3230 AVX512BIBase, EVEX_4V, EVEX_B;
3233 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3234 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3235 Predicate prd, bit IsCommutable = 0> {
3236 let Predicates = [prd] in
3237 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3238 IsCommutable>, EVEX_V512;
3240 let Predicates = [prd, HasVLX] in {
3241 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3242 IsCommutable>, EVEX_V256;
3243 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3244 IsCommutable>, EVEX_V128;
3248 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3249 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3250 Predicate prd, bit IsCommutable = 0> {
3251 let Predicates = [prd] in
3252 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3253 IsCommutable>, EVEX_V512;
3255 let Predicates = [prd, HasVLX] in {
3256 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3257 IsCommutable>, EVEX_V256;
3258 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3259 IsCommutable>, EVEX_V128;
3263 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3264 OpndItins itins, Predicate prd,
3265 bit IsCommutable = 0> {
3266 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3267 itins, prd, IsCommutable>,
3268 VEX_W, EVEX_CD8<64, CD8VF>;
3271 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3272 OpndItins itins, Predicate prd,
3273 bit IsCommutable = 0> {
3274 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3275 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3278 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3279 OpndItins itins, Predicate prd,
3280 bit IsCommutable = 0> {
3281 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3282 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3285 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3286 OpndItins itins, Predicate prd,
3287 bit IsCommutable = 0> {
3288 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3289 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3292 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3293 SDNode OpNode, OpndItins itins, Predicate prd,
3294 bit IsCommutable = 0> {
3295 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3298 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3302 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3303 SDNode OpNode, OpndItins itins, Predicate prd,
3304 bit IsCommutable = 0> {
3305 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3308 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3312 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3313 bits<8> opc_d, bits<8> opc_q,
3314 string OpcodeStr, SDNode OpNode,
3315 OpndItins itins, bit IsCommutable = 0> {
3316 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3317 itins, HasAVX512, IsCommutable>,
3318 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3319 itins, HasBWI, IsCommutable>;
3322 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3323 SDNode OpNode,X86VectorVTInfo _Src,
3324 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3325 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3326 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3327 "$src2, $src1","$src1, $src2",
3329 (_Src.VT _Src.RC:$src1),
3330 (_Src.VT _Src.RC:$src2))),
3331 itins.rr, IsCommutable>,
3332 AVX512BIBase, EVEX_4V;
3333 let mayLoad = 1 in {
3334 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3335 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3336 "$src2, $src1", "$src1, $src2",
3337 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3338 (bitconvert (_Src.LdFrag addr:$src2)))),
3340 AVX512BIBase, EVEX_4V;
3342 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3343 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3345 "${src2}"##_Dst.BroadcastStr##", $src1",
3346 "$src1, ${src2}"##_Dst.BroadcastStr,
3347 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3348 (_Dst.VT (X86VBroadcast
3349 (_Dst.ScalarLdFrag addr:$src2)))))),
3351 AVX512BIBase, EVEX_4V, EVEX_B;
3355 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3356 SSE_INTALU_ITINS_P, 1>;
3357 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3358 SSE_INTALU_ITINS_P, 0>;
3359 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3360 SSE_INTALU_ITINS_P, HasBWI, 1>;
3361 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3362 SSE_INTALU_ITINS_P, HasBWI, 0>;
3363 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3364 SSE_INTALU_ITINS_P, HasBWI, 1>;
3365 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3366 SSE_INTALU_ITINS_P, HasBWI, 0>;
3367 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3368 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3369 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3370 SSE_INTALU_ITINS_P, HasBWI, 1>;
3371 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3372 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3373 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3375 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3377 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3379 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3380 SSE_INTALU_ITINS_P, HasBWI, 1>;
3382 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3383 SDNode OpNode, bit IsCommutable = 0> {
3385 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3386 v16i32_info, v8i64_info, IsCommutable>,
3387 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3388 let Predicates = [HasVLX] in {
3389 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3390 v8i32x_info, v4i64x_info, IsCommutable>,
3391 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3392 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3393 v4i32x_info, v2i64x_info, IsCommutable>,
3394 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3398 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3400 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3403 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3404 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3405 let mayLoad = 1 in {
3406 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3407 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3409 "${src2}"##_Src.BroadcastStr##", $src1",
3410 "$src1, ${src2}"##_Src.BroadcastStr,
3411 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3412 (_Src.VT (X86VBroadcast
3413 (_Src.ScalarLdFrag addr:$src2))))))>,
3414 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3418 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3419 SDNode OpNode,X86VectorVTInfo _Src,
3420 X86VectorVTInfo _Dst> {
3421 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3422 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3423 "$src2, $src1","$src1, $src2",
3425 (_Src.VT _Src.RC:$src1),
3426 (_Src.VT _Src.RC:$src2)))>,
3427 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3428 let mayLoad = 1 in {
3429 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3430 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3431 "$src2, $src1", "$src1, $src2",
3432 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3433 (bitconvert (_Src.LdFrag addr:$src2))))>,
3434 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3438 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3440 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3442 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3443 v32i16_info>, EVEX_V512;
3444 let Predicates = [HasVLX] in {
3445 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3447 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3448 v16i16x_info>, EVEX_V256;
3449 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3451 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3452 v8i16x_info>, EVEX_V128;
3455 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3457 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3458 v64i8_info>, EVEX_V512;
3459 let Predicates = [HasVLX] in {
3460 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3461 v32i8x_info>, EVEX_V256;
3462 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3463 v16i8x_info>, EVEX_V128;
3467 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3468 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3469 AVX512VLVectorVTInfo _Dst> {
3470 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3471 _Dst.info512>, EVEX_V512;
3472 let Predicates = [HasVLX] in {
3473 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3474 _Dst.info256>, EVEX_V256;
3475 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3476 _Dst.info128>, EVEX_V128;
3480 let Predicates = [HasBWI] in {
3481 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3482 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3483 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3484 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3486 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3487 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3488 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3489 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3492 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3493 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3494 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3495 SSE_INTALU_ITINS_P, HasBWI, 1>;
3496 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3497 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3499 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3500 SSE_INTALU_ITINS_P, HasBWI, 1>;
3501 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3502 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3503 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3504 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3506 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3507 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3508 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3509 SSE_INTALU_ITINS_P, HasBWI, 1>;
3510 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3511 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3513 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3514 SSE_INTALU_ITINS_P, HasBWI, 1>;
3515 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3516 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3517 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3518 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3519 //===----------------------------------------------------------------------===//
3520 // AVX-512 Logical Instructions
3521 //===----------------------------------------------------------------------===//
3523 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3524 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3525 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3526 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3527 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3528 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3529 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3530 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3532 //===----------------------------------------------------------------------===//
3533 // AVX-512 FP arithmetic
3534 //===----------------------------------------------------------------------===//
3535 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3536 SDNode OpNode, SDNode VecNode, OpndItins itins,
3539 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3540 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3541 "$src2, $src1", "$src1, $src2",
3542 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3543 (i32 FROUND_CURRENT)),
3544 itins.rr, IsCommutable>;
3546 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3547 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3548 "$src2, $src1", "$src1, $src2",
3549 (VecNode (_.VT _.RC:$src1),
3550 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3551 (i32 FROUND_CURRENT)),
3552 itins.rm, IsCommutable>;
3553 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3554 Predicates = [HasAVX512] in {
3555 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3556 (ins _.FRC:$src1, _.FRC:$src2),
3557 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3558 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3560 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3561 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3562 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3563 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3564 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3568 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3569 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3571 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3572 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3573 "$rc, $src2, $src1", "$src1, $src2, $rc",
3574 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3575 (i32 imm:$rc)), itins.rr, IsCommutable>,
3578 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3579 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3581 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3582 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3583 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3584 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3585 (i32 FROUND_NO_EXC))>, EVEX_B;
3588 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3590 SizeItins itins, bit IsCommutable> {
3591 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3592 itins.s, IsCommutable>,
3593 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3594 itins.s, IsCommutable>,
3595 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3596 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3597 itins.d, IsCommutable>,
3598 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3599 itins.d, IsCommutable>,
3600 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3603 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3605 SizeItins itins, bit IsCommutable> {
3606 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3607 itins.s, IsCommutable>,
3608 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3609 itins.s, IsCommutable>,
3610 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3611 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3612 itins.d, IsCommutable>,
3613 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3614 itins.d, IsCommutable>,
3615 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3617 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3618 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3619 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3620 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3621 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3622 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3624 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3625 X86VectorVTInfo _, bit IsCommutable> {
3626 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3627 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3628 "$src2, $src1", "$src1, $src2",
3629 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3630 let mayLoad = 1 in {
3631 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3632 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3633 "$src2, $src1", "$src1, $src2",
3634 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3635 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3636 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3637 "${src2}"##_.BroadcastStr##", $src1",
3638 "$src1, ${src2}"##_.BroadcastStr,
3639 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3640 (_.ScalarLdFrag addr:$src2))))>,
3645 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3646 X86VectorVTInfo _> {
3647 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3648 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3649 "$rc, $src2, $src1", "$src1, $src2, $rc",
3650 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3651 EVEX_4V, EVEX_B, EVEX_RC;
3655 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3656 X86VectorVTInfo _> {
3657 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3658 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3659 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3660 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3664 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3665 bit IsCommutable = 0> {
3666 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3667 IsCommutable>, EVEX_V512, PS,
3668 EVEX_CD8<32, CD8VF>;
3669 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3670 IsCommutable>, EVEX_V512, PD, VEX_W,
3671 EVEX_CD8<64, CD8VF>;
3673 // Define only if AVX512VL feature is present.
3674 let Predicates = [HasVLX] in {
3675 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3676 IsCommutable>, EVEX_V128, PS,
3677 EVEX_CD8<32, CD8VF>;
3678 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3679 IsCommutable>, EVEX_V256, PS,
3680 EVEX_CD8<32, CD8VF>;
3681 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3682 IsCommutable>, EVEX_V128, PD, VEX_W,
3683 EVEX_CD8<64, CD8VF>;
3684 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3685 IsCommutable>, EVEX_V256, PD, VEX_W,
3686 EVEX_CD8<64, CD8VF>;
3690 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3691 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3692 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3693 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3694 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3697 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3698 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3699 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3700 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3701 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3704 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3705 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3706 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3707 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3708 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3709 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3710 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3711 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3712 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3713 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3714 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3715 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3716 let Predicates = [HasDQI] in {
3717 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3718 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3719 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3720 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3723 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3724 X86VectorVTInfo _> {
3725 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3726 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3727 "$src2, $src1", "$src1, $src2",
3728 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3729 let mayLoad = 1 in {
3730 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3731 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3732 "$src2, $src1", "$src1, $src2",
3733 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3734 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3735 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3736 "${src2}"##_.BroadcastStr##", $src1",
3737 "$src1, ${src2}"##_.BroadcastStr,
3738 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3739 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3744 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3745 X86VectorVTInfo _> {
3746 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3747 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3748 "$src2, $src1", "$src1, $src2",
3749 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3750 let mayLoad = 1 in {
3751 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3752 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3753 "$src2, $src1", "$src1, $src2",
3754 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3758 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3759 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3760 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3761 EVEX_V512, EVEX_CD8<32, CD8VF>;
3762 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3763 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3764 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3765 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3766 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3767 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3768 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3769 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3770 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3772 // Define only if AVX512VL feature is present.
3773 let Predicates = [HasVLX] in {
3774 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3775 EVEX_V128, EVEX_CD8<32, CD8VF>;
3776 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3777 EVEX_V256, EVEX_CD8<32, CD8VF>;
3778 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3779 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3780 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3781 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3784 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3786 //===----------------------------------------------------------------------===//
3787 // AVX-512 VPTESTM instructions
3788 //===----------------------------------------------------------------------===//
3790 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3791 X86VectorVTInfo _> {
3792 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3793 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3794 "$src2, $src1", "$src1, $src2",
3795 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3798 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3799 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3800 "$src2, $src1", "$src1, $src2",
3801 (OpNode (_.VT _.RC:$src1),
3802 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3804 EVEX_CD8<_.EltSize, CD8VF>;
3807 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3808 X86VectorVTInfo _> {
3810 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3811 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3812 "${src2}"##_.BroadcastStr##", $src1",
3813 "$src1, ${src2}"##_.BroadcastStr,
3814 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3815 (_.ScalarLdFrag addr:$src2))))>,
3816 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3818 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3819 AVX512VLVectorVTInfo _> {
3820 let Predicates = [HasAVX512] in
3821 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3822 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3824 let Predicates = [HasAVX512, HasVLX] in {
3825 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3826 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3827 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3828 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3832 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3833 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3835 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3836 avx512vl_i64_info>, VEX_W;
3839 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3841 let Predicates = [HasBWI] in {
3842 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3844 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3847 let Predicates = [HasVLX, HasBWI] in {
3849 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3851 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3853 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3855 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3860 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3862 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3863 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3865 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3866 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3868 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3869 (v16i32 VR512:$src2), (i16 -1))),
3870 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3872 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3873 (v8i64 VR512:$src2), (i8 -1))),
3874 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3876 //===----------------------------------------------------------------------===//
3877 // AVX-512 Shift instructions
3878 //===----------------------------------------------------------------------===//
3879 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3880 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3881 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3882 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3883 "$src2, $src1", "$src1, $src2",
3884 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3885 SSE_INTSHIFT_ITINS_P.rr>;
3887 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3888 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3889 "$src2, $src1", "$src1, $src2",
3890 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3892 SSE_INTSHIFT_ITINS_P.rm>;
3895 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3896 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3898 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3899 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3900 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3901 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3902 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3905 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3906 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3907 // src2 is always 128-bit
3908 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3909 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3910 "$src2, $src1", "$src1, $src2",
3911 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3912 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3913 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3914 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3915 "$src2, $src1", "$src1, $src2",
3916 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3917 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3921 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3922 ValueType SrcVT, PatFrag bc_frag,
3923 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3924 let Predicates = [prd] in
3925 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3926 VTInfo.info512>, EVEX_V512,
3927 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3928 let Predicates = [prd, HasVLX] in {
3929 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3930 VTInfo.info256>, EVEX_V256,
3931 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3932 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3933 VTInfo.info128>, EVEX_V128,
3934 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3938 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3939 string OpcodeStr, SDNode OpNode> {
3940 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3941 avx512vl_i32_info, HasAVX512>;
3942 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3943 avx512vl_i64_info, HasAVX512>, VEX_W;
3944 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3945 avx512vl_i16_info, HasBWI>;
3948 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3949 string OpcodeStr, SDNode OpNode,
3950 AVX512VLVectorVTInfo VTInfo> {
3951 let Predicates = [HasAVX512] in
3952 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3954 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3955 VTInfo.info512>, EVEX_V512;
3956 let Predicates = [HasAVX512, HasVLX] in {
3957 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3959 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3960 VTInfo.info256>, EVEX_V256;
3961 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3963 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3964 VTInfo.info128>, EVEX_V128;
3968 multiclass avx512_shift_rmi_w<bits<8> opcw,
3969 Format ImmFormR, Format ImmFormM,
3970 string OpcodeStr, SDNode OpNode> {
3971 let Predicates = [HasBWI] in
3972 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3973 v32i16_info>, EVEX_V512;
3974 let Predicates = [HasVLX, HasBWI] in {
3975 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3976 v16i16x_info>, EVEX_V256;
3977 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3978 v8i16x_info>, EVEX_V128;
3982 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3983 Format ImmFormR, Format ImmFormM,
3984 string OpcodeStr, SDNode OpNode> {
3985 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3986 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3987 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3988 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3991 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3992 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3994 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3995 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3997 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3998 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4000 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4001 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4003 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4004 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4005 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4007 //===-------------------------------------------------------------------===//
4008 // Variable Bit Shifts
4009 //===-------------------------------------------------------------------===//
4010 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4011 X86VectorVTInfo _> {
4012 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4013 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4014 "$src2, $src1", "$src1, $src2",
4015 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4016 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4018 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4019 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4020 "$src2, $src1", "$src1, $src2",
4021 (_.VT (OpNode _.RC:$src1,
4022 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4023 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4024 EVEX_CD8<_.EltSize, CD8VF>;
4027 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4028 X86VectorVTInfo _> {
4030 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4031 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4032 "${src2}"##_.BroadcastStr##", $src1",
4033 "$src1, ${src2}"##_.BroadcastStr,
4034 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4035 (_.ScalarLdFrag addr:$src2))))),
4036 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4037 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4039 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4040 AVX512VLVectorVTInfo _> {
4041 let Predicates = [HasAVX512] in
4042 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4043 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4045 let Predicates = [HasAVX512, HasVLX] in {
4046 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4047 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4048 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4049 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4053 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4055 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4057 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4058 avx512vl_i64_info>, VEX_W;
4061 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4063 let Predicates = [HasBWI] in
4064 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4066 let Predicates = [HasVLX, HasBWI] in {
4068 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4070 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4075 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4076 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4077 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4078 avx512_var_shift_w<0x11, "vpsravw", sra>;
4079 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4080 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4081 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4082 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4084 //===-------------------------------------------------------------------===//
4085 // 1-src variable permutation VPERMW/D/Q
4086 //===-------------------------------------------------------------------===//
4087 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4088 AVX512VLVectorVTInfo _> {
4089 let Predicates = [HasAVX512] in
4090 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4091 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4093 let Predicates = [HasAVX512, HasVLX] in
4094 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4095 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4098 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4099 string OpcodeStr, SDNode OpNode,
4100 AVX512VLVectorVTInfo VTInfo> {
4101 let Predicates = [HasAVX512] in
4102 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4104 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4105 VTInfo.info512>, EVEX_V512;
4106 let Predicates = [HasAVX512, HasVLX] in
4107 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4109 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4110 VTInfo.info256>, EVEX_V256;
4114 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4116 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4118 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4119 avx512vl_i64_info>, VEX_W;
4120 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4122 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4123 avx512vl_f64_info>, VEX_W;
4125 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4126 X86VPermi, avx512vl_i64_info>,
4127 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4128 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4129 X86VPermi, avx512vl_f64_info>,
4130 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4131 //===----------------------------------------------------------------------===//
4132 // AVX-512 - VPERMIL
4133 //===----------------------------------------------------------------------===//
4135 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4136 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4137 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4138 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4139 "$src2, $src1", "$src1, $src2",
4140 (_.VT (OpNode _.RC:$src1,
4141 (Ctrl.VT Ctrl.RC:$src2)))>,
4143 let mayLoad = 1 in {
4144 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4145 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4146 "$src2, $src1", "$src1, $src2",
4149 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4150 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4151 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4152 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4153 "${src2}"##_.BroadcastStr##", $src1",
4154 "$src1, ${src2}"##_.BroadcastStr,
4157 (Ctrl.VT (X86VBroadcast
4158 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4159 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4163 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4164 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4165 let Predicates = [HasAVX512] in {
4166 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4167 Ctrl.info512>, EVEX_V512;
4169 let Predicates = [HasAVX512, HasVLX] in {
4170 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4171 Ctrl.info128>, EVEX_V128;
4172 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4173 Ctrl.info256>, EVEX_V256;
4177 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4178 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4180 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4181 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4183 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4185 let isCodeGenOnly = 1 in {
4186 // lowering implementation with the alternative types
4187 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4188 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4189 OpcodeStr, X86VPermilpi, Ctrl>,
4190 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4194 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4196 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4197 avx512vl_i64_info>, VEX_W;
4198 //===----------------------------------------------------------------------===//
4199 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4200 //===----------------------------------------------------------------------===//
4202 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4203 X86PShufd, avx512vl_i32_info>,
4204 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4205 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4206 X86PShufhw>, EVEX, AVX512XSIi8Base;
4207 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4208 X86PShuflw>, EVEX, AVX512XDIi8Base;
4210 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4211 let Predicates = [HasBWI] in
4212 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4214 let Predicates = [HasVLX, HasBWI] in {
4215 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4216 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4220 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4222 //===----------------------------------------------------------------------===//
4223 // AVX-512 - MOVDDUP
4224 //===----------------------------------------------------------------------===//
4226 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
4227 X86MemOperand x86memop, PatFrag memop_frag> {
4228 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4229 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4230 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
4231 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4232 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4234 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
4237 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
4238 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4239 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
4240 (VMOVDDUPZrm addr:$src)>;
4242 //===---------------------------------------------------------------------===//
4243 // Replicate Single FP - MOVSHDUP and MOVSLDUP
4244 //===---------------------------------------------------------------------===//
4245 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4246 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4247 X86MemOperand x86memop> {
4248 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4249 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4250 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
4252 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4253 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4254 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
4257 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4258 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4259 EVEX_CD8<32, CD8VF>;
4260 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4261 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4262 EVEX_CD8<32, CD8VF>;
4264 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
4265 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
4266 (VMOVSHDUPZrm addr:$src)>;
4267 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
4268 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
4269 (VMOVSLDUPZrm addr:$src)>;
4271 //===----------------------------------------------------------------------===//
4272 // Move Low to High and High to Low packed FP Instructions
4273 //===----------------------------------------------------------------------===//
4274 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4275 (ins VR128X:$src1, VR128X:$src2),
4276 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4277 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4278 IIC_SSE_MOV_LH>, EVEX_4V;
4279 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4280 (ins VR128X:$src1, VR128X:$src2),
4281 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4282 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4283 IIC_SSE_MOV_LH>, EVEX_4V;
4285 let Predicates = [HasAVX512] in {
4287 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4288 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4289 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4290 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4293 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4294 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4297 //===----------------------------------------------------------------------===//
4298 // FMA - Fused Multiply Operations
4301 let Constraints = "$src1 = $dst" in {
4302 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4303 X86VectorVTInfo _> {
4304 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4305 (ins _.RC:$src2, _.RC:$src3),
4306 OpcodeStr, "$src3, $src2", "$src2, $src3",
4307 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4310 let mayLoad = 1 in {
4311 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4312 (ins _.RC:$src2, _.MemOp:$src3),
4313 OpcodeStr, "$src3, $src2", "$src2, $src3",
4314 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4317 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4318 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4319 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4320 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4322 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4323 AVX512FMA3Base, EVEX_B;
4327 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4328 X86VectorVTInfo _> {
4329 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4330 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4331 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4332 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4333 AVX512FMA3Base, EVEX_B, EVEX_RC;
4335 } // Constraints = "$src1 = $dst"
4337 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4338 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4339 let Predicates = [HasAVX512] in {
4340 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4341 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4342 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4344 let Predicates = [HasVLX, HasAVX512] in {
4345 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4346 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4347 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4348 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4352 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4353 SDNode OpNodeRnd > {
4354 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4356 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4357 avx512vl_f64_info>, VEX_W;
4360 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4361 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4362 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4363 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4364 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4365 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4368 let Constraints = "$src1 = $dst" in {
4369 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4370 X86VectorVTInfo _> {
4371 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4372 (ins _.RC:$src2, _.RC:$src3),
4373 OpcodeStr, "$src3, $src2", "$src2, $src3",
4374 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4377 let mayLoad = 1 in {
4378 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4379 (ins _.RC:$src2, _.MemOp:$src3),
4380 OpcodeStr, "$src3, $src2", "$src2, $src3",
4381 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4384 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4385 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4386 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4387 "$src2, ${src3}"##_.BroadcastStr,
4388 (_.VT (OpNode _.RC:$src2,
4389 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4390 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4394 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4395 X86VectorVTInfo _> {
4396 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4397 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4398 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4399 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4400 AVX512FMA3Base, EVEX_B, EVEX_RC;
4402 } // Constraints = "$src1 = $dst"
4404 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4405 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4406 let Predicates = [HasAVX512] in {
4407 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4408 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4409 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4411 let Predicates = [HasVLX, HasAVX512] in {
4412 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4413 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4414 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4415 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4419 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4420 SDNode OpNodeRnd > {
4421 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4423 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4424 avx512vl_f64_info>, VEX_W;
4427 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4428 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4429 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4430 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4431 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4432 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4434 let Constraints = "$src1 = $dst" in {
4435 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4436 X86VectorVTInfo _> {
4437 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4438 (ins _.RC:$src3, _.RC:$src2),
4439 OpcodeStr, "$src2, $src3", "$src3, $src2",
4440 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4443 let mayLoad = 1 in {
4444 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4445 (ins _.RC:$src3, _.MemOp:$src2),
4446 OpcodeStr, "$src2, $src3", "$src3, $src2",
4447 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4450 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4451 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4452 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4453 "$src3, ${src2}"##_.BroadcastStr,
4454 (_.VT (OpNode _.RC:$src1,
4455 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4456 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4460 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4461 X86VectorVTInfo _> {
4462 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4463 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4464 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4465 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4466 AVX512FMA3Base, EVEX_B, EVEX_RC;
4468 } // Constraints = "$src1 = $dst"
4470 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4471 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4472 let Predicates = [HasAVX512] in {
4473 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4474 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4475 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4477 let Predicates = [HasVLX, HasAVX512] in {
4478 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4479 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4480 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4481 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4485 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4486 SDNode OpNodeRnd > {
4487 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4489 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4490 avx512vl_f64_info>, VEX_W;
4493 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4494 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4495 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4496 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4497 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4498 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4501 let Constraints = "$src1 = $dst" in {
4502 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4503 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4504 dag RHS_r, dag RHS_m > {
4505 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4506 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4507 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4510 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4511 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4512 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4514 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4515 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4516 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4517 AVX512FMA3Base, EVEX_B, EVEX_RC;
4519 let isCodeGenOnly = 1 in {
4520 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4521 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4522 !strconcat(OpcodeStr,
4523 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4526 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4527 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4528 !strconcat(OpcodeStr,
4529 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4531 }// isCodeGenOnly = 1
4533 }// Constraints = "$src1 = $dst"
4535 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4536 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4539 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4540 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4541 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4542 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4543 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4545 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4547 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4548 (_.ScalarLdFrag addr:$src3))))>;
4550 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4551 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4552 (_.VT (OpNode _.RC:$src2,
4553 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4555 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4557 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4559 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4560 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4562 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4563 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4564 (_.VT (OpNode _.RC:$src1,
4565 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4567 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4569 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4571 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4572 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4575 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4576 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4577 let Predicates = [HasAVX512] in {
4578 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4579 OpNodeRnd, f32x_info, "SS">,
4580 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4581 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4582 OpNodeRnd, f64x_info, "SD">,
4583 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4587 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4588 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4589 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4590 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4592 //===----------------------------------------------------------------------===//
4593 // AVX-512 Scalar convert from sign integer to float/double
4594 //===----------------------------------------------------------------------===//
4596 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4597 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4598 PatFrag ld_frag, string asm> {
4599 let hasSideEffects = 0 in {
4600 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4601 (ins DstVT.FRC:$src1, SrcRC:$src),
4602 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4605 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4606 (ins DstVT.FRC:$src1, x86memop:$src),
4607 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4609 } // hasSideEffects = 0
4610 let isCodeGenOnly = 1 in {
4611 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4612 (ins DstVT.RC:$src1, SrcRC:$src2),
4613 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4614 [(set DstVT.RC:$dst,
4615 (OpNode (DstVT.VT DstVT.RC:$src1),
4617 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4619 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4620 (ins DstVT.RC:$src1, x86memop:$src2),
4621 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4622 [(set DstVT.RC:$dst,
4623 (OpNode (DstVT.VT DstVT.RC:$src1),
4624 (ld_frag addr:$src2),
4625 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4626 }//isCodeGenOnly = 1
4629 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4630 X86VectorVTInfo DstVT, string asm> {
4631 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4632 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4634 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4635 [(set DstVT.RC:$dst,
4636 (OpNode (DstVT.VT DstVT.RC:$src1),
4638 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4641 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4642 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4643 PatFrag ld_frag, string asm> {
4644 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4645 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4649 let Predicates = [HasAVX512] in {
4650 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4651 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4652 XS, EVEX_CD8<32, CD8VT1>;
4653 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4654 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4655 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4656 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4657 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4658 XD, EVEX_CD8<32, CD8VT1>;
4659 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4660 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4661 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4663 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4664 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4665 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4666 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4667 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4668 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4669 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4670 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4672 def : Pat<(f32 (sint_to_fp GR32:$src)),
4673 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4674 def : Pat<(f32 (sint_to_fp GR64:$src)),
4675 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4676 def : Pat<(f64 (sint_to_fp GR32:$src)),
4677 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4678 def : Pat<(f64 (sint_to_fp GR64:$src)),
4679 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4681 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4682 v4f32x_info, i32mem, loadi32,
4683 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4684 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4685 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4686 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4687 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4688 i32mem, loadi32, "cvtusi2sd{l}">,
4689 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4690 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4691 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4692 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4694 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4695 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4696 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4697 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4698 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4699 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4700 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4701 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4703 def : Pat<(f32 (uint_to_fp GR32:$src)),
4704 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4705 def : Pat<(f32 (uint_to_fp GR64:$src)),
4706 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4707 def : Pat<(f64 (uint_to_fp GR32:$src)),
4708 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4709 def : Pat<(f64 (uint_to_fp GR64:$src)),
4710 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4713 //===----------------------------------------------------------------------===//
4714 // AVX-512 Scalar convert from float/double to integer
4715 //===----------------------------------------------------------------------===//
4716 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4717 RegisterClass DstRC, Intrinsic Int,
4718 Operand memop, ComplexPattern mem_cpat, string asm> {
4719 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4720 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4721 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4722 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4723 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4724 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4725 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4727 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4728 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4729 } // hasSideEffects = 0, Predicates = [HasAVX512]
4732 // Convert float/double to signed/unsigned int 32/64
4733 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4734 ssmem, sse_load_f32, "cvtss2si">,
4735 XS, EVEX_CD8<32, CD8VT1>;
4736 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4737 int_x86_sse_cvtss2si64,
4738 ssmem, sse_load_f32, "cvtss2si">,
4739 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4740 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4741 int_x86_avx512_cvtss2usi,
4742 ssmem, sse_load_f32, "cvtss2usi">,
4743 XS, EVEX_CD8<32, CD8VT1>;
4744 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4745 int_x86_avx512_cvtss2usi64, ssmem,
4746 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4747 EVEX_CD8<32, CD8VT1>;
4748 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4749 sdmem, sse_load_f64, "cvtsd2si">,
4750 XD, EVEX_CD8<64, CD8VT1>;
4751 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4752 int_x86_sse2_cvtsd2si64,
4753 sdmem, sse_load_f64, "cvtsd2si">,
4754 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4755 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4756 int_x86_avx512_cvtsd2usi,
4757 sdmem, sse_load_f64, "cvtsd2usi">,
4758 XD, EVEX_CD8<64, CD8VT1>;
4759 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4760 int_x86_avx512_cvtsd2usi64, sdmem,
4761 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4762 EVEX_CD8<64, CD8VT1>;
4764 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4765 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4766 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4767 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4768 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4769 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4770 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4771 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4772 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4773 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4774 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4775 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4776 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4778 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4779 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4780 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4781 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4783 // Convert float/double to signed/unsigned int 32/64 with truncation
4784 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4785 X86VectorVTInfo _DstRC, SDNode OpNode,
4787 let Predicates = [HasAVX512] in {
4788 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4789 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4790 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4791 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4792 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4794 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4795 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4796 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4799 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4800 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4801 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4802 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4803 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4804 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4805 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4806 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4807 (i32 FROUND_NO_EXC)))]>,
4808 EVEX,VEX_LIG , EVEX_B;
4810 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4811 (ins _SrcRC.MemOp:$src),
4812 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4815 } // isCodeGenOnly = 1, hasSideEffects = 0
4820 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4821 fp_to_sint,X86cvttss2IntRnd>,
4822 XS, EVEX_CD8<32, CD8VT1>;
4823 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4824 fp_to_sint,X86cvttss2IntRnd>,
4825 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4826 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4827 fp_to_sint,X86cvttsd2IntRnd>,
4828 XD, EVEX_CD8<64, CD8VT1>;
4829 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4830 fp_to_sint,X86cvttsd2IntRnd>,
4831 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4833 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4834 fp_to_uint,X86cvttss2UIntRnd>,
4835 XS, EVEX_CD8<32, CD8VT1>;
4836 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4837 fp_to_uint,X86cvttss2UIntRnd>,
4838 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4839 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4840 fp_to_uint,X86cvttsd2UIntRnd>,
4841 XD, EVEX_CD8<64, CD8VT1>;
4842 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4843 fp_to_uint,X86cvttsd2UIntRnd>,
4844 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4845 let Predicates = [HasAVX512] in {
4846 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4847 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4848 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4849 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4850 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4851 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4852 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4853 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4856 //===----------------------------------------------------------------------===//
4857 // AVX-512 Convert form float to double and back
4858 //===----------------------------------------------------------------------===//
4859 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4860 X86VectorVTInfo _Src, SDNode OpNode> {
4861 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4862 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4863 "$src2, $src1", "$src1, $src2",
4864 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4865 (_Src.VT _Src.RC:$src2)))>,
4866 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4867 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4868 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4869 "$src2, $src1", "$src1, $src2",
4870 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4871 (_Src.VT (scalar_to_vector
4872 (_Src.ScalarLdFrag addr:$src2)))))>,
4873 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4876 // Scalar Coversion with SAE - suppress all exceptions
4877 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4878 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4879 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4880 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4881 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4882 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4883 (_Src.VT _Src.RC:$src2),
4884 (i32 FROUND_NO_EXC)))>,
4885 EVEX_4V, VEX_LIG, EVEX_B;
4888 // Scalar Conversion with rounding control (RC)
4889 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4890 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4891 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4892 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4893 "$rc, $src2, $src1", "$src1, $src2, $rc",
4894 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4895 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4896 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4899 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4900 SDNode OpNodeRnd, X86VectorVTInfo _src,
4901 X86VectorVTInfo _dst> {
4902 let Predicates = [HasAVX512] in {
4903 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4904 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4905 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
4910 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4911 SDNode OpNodeRnd, X86VectorVTInfo _src,
4912 X86VectorVTInfo _dst> {
4913 let Predicates = [HasAVX512] in {
4914 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4915 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
4916 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
4919 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
4920 X86froundRnd, f64x_info, f32x_info>;
4921 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
4922 X86fpextRnd,f32x_info, f64x_info >;
4924 def : Pat<(f64 (fextend FR32X:$src)),
4925 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
4926 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
4927 Requires<[HasAVX512]>;
4928 def : Pat<(f64 (fextend (loadf32 addr:$src))),
4929 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4930 Requires<[HasAVX512]>;
4932 def : Pat<(f64 (extloadf32 addr:$src)),
4933 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4934 Requires<[HasAVX512, OptForSize]>;
4936 def : Pat<(f64 (extloadf32 addr:$src)),
4937 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
4938 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
4939 Requires<[HasAVX512, OptForSpeed]>;
4941 def : Pat<(f32 (fround FR64X:$src)),
4942 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
4943 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
4944 Requires<[HasAVX512]>;
4945 //===----------------------------------------------------------------------===//
4946 // AVX-512 Vector convert from signed/unsigned integer to float/double
4947 // and from float/double to signed/unsigned integer
4948 //===----------------------------------------------------------------------===//
4950 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4951 X86VectorVTInfo _Src, SDNode OpNode,
4952 string Broadcast = _.BroadcastStr,
4953 string Alias = ""> {
4955 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4956 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4957 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4959 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4960 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4961 (_.VT (OpNode (_Src.VT
4962 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4964 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4965 (ins _Src.MemOp:$src), OpcodeStr,
4966 "${src}"##Broadcast, "${src}"##Broadcast,
4967 (_.VT (OpNode (_Src.VT
4968 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4971 // Coversion with SAE - suppress all exceptions
4972 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4973 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4974 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4975 (ins _Src.RC:$src), OpcodeStr,
4976 "{sae}, $src", "$src, {sae}",
4977 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4978 (i32 FROUND_NO_EXC)))>,
4982 // Conversion with rounding control (RC)
4983 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4984 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4985 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4986 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
4987 "$rc, $src", "$src, $rc",
4988 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
4989 EVEX, EVEX_B, EVEX_RC;
4992 // Extend Float to Double
4993 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
4994 let Predicates = [HasAVX512] in {
4995 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
4996 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
4997 X86vfpextRnd>, EVEX_V512;
4999 let Predicates = [HasVLX] in {
5000 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5001 X86vfpext, "{1to2}">, EVEX_V128;
5002 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5007 // Truncate Double to Float
5008 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5009 let Predicates = [HasAVX512] in {
5010 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5011 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5012 X86vfproundRnd>, EVEX_V512;
5014 let Predicates = [HasVLX] in {
5015 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5016 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5017 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5018 "{1to4}", "{y}">, EVEX_V256;
5022 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5023 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5024 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5025 PS, EVEX_CD8<32, CD8VH>;
5027 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5028 (VCVTPS2PDZrm addr:$src)>;
5030 let Predicates = [HasVLX] in {
5031 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5032 (VCVTPS2PDZ256rm addr:$src)>;
5035 // Convert Signed/Unsigned Doubleword to Double
5036 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5038 // No rounding in this op
5039 let Predicates = [HasAVX512] in
5040 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5043 let Predicates = [HasVLX] in {
5044 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5045 OpNode128, "{1to2}">, EVEX_V128;
5046 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5051 // Convert Signed/Unsigned Doubleword to Float
5052 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5054 let Predicates = [HasAVX512] in
5055 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5056 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5057 OpNodeRnd>, EVEX_V512;
5059 let Predicates = [HasVLX] in {
5060 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5062 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5067 // Convert Float to Signed/Unsigned Doubleword with truncation
5068 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5069 SDNode OpNode, SDNode OpNodeRnd> {
5070 let Predicates = [HasAVX512] in {
5071 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5072 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5073 OpNodeRnd>, EVEX_V512;
5075 let Predicates = [HasVLX] in {
5076 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5078 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5083 // Convert Float to Signed/Unsigned Doubleword
5084 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5085 SDNode OpNode, SDNode OpNodeRnd> {
5086 let Predicates = [HasAVX512] in {
5087 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5088 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5089 OpNodeRnd>, EVEX_V512;
5091 let Predicates = [HasVLX] in {
5092 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5094 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5099 // Convert Double to Signed/Unsigned Doubleword with truncation
5100 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5101 SDNode OpNode, SDNode OpNodeRnd> {
5102 let Predicates = [HasAVX512] in {
5103 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5104 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5105 OpNodeRnd>, EVEX_V512;
5107 let Predicates = [HasVLX] in {
5108 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5109 // memory forms of these instructions in Asm Parcer. They have the same
5110 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5111 // due to the same reason.
5112 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5113 "{1to2}", "{x}">, EVEX_V128;
5114 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5115 "{1to4}", "{y}">, EVEX_V256;
5119 // Convert Double to Signed/Unsigned Doubleword
5120 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5121 SDNode OpNode, SDNode OpNodeRnd> {
5122 let Predicates = [HasAVX512] in {
5123 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5124 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5125 OpNodeRnd>, EVEX_V512;
5127 let Predicates = [HasVLX] in {
5128 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5129 // memory forms of these instructions in Asm Parcer. They have the same
5130 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5131 // due to the same reason.
5132 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5133 "{1to2}", "{x}">, EVEX_V128;
5134 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5135 "{1to4}", "{y}">, EVEX_V256;
5139 // Convert Double to Signed/Unsigned Quardword
5140 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5141 SDNode OpNode, SDNode OpNodeRnd> {
5142 let Predicates = [HasDQI] in {
5143 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5144 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5145 OpNodeRnd>, EVEX_V512;
5147 let Predicates = [HasDQI, HasVLX] in {
5148 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5150 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5155 // Convert Double to Signed/Unsigned Quardword with truncation
5156 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5157 SDNode OpNode, SDNode OpNodeRnd> {
5158 let Predicates = [HasDQI] in {
5159 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5160 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5161 OpNodeRnd>, EVEX_V512;
5163 let Predicates = [HasDQI, HasVLX] in {
5164 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5166 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5171 // Convert Signed/Unsigned Quardword to Double
5172 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5173 SDNode OpNode, SDNode OpNodeRnd> {
5174 let Predicates = [HasDQI] in {
5175 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5176 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5177 OpNodeRnd>, EVEX_V512;
5179 let Predicates = [HasDQI, HasVLX] in {
5180 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5182 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5187 // Convert Float to Signed/Unsigned Quardword
5188 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5189 SDNode OpNode, SDNode OpNodeRnd> {
5190 let Predicates = [HasDQI] in {
5191 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5192 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5193 OpNodeRnd>, EVEX_V512;
5195 let Predicates = [HasDQI, HasVLX] in {
5196 // Explicitly specified broadcast string, since we take only 2 elements
5197 // from v4f32x_info source
5198 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5199 "{1to2}">, EVEX_V128;
5200 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5205 // Convert Float to Signed/Unsigned Quardword with truncation
5206 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5207 SDNode OpNode, SDNode OpNodeRnd> {
5208 let Predicates = [HasDQI] in {
5209 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5210 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5211 OpNodeRnd>, EVEX_V512;
5213 let Predicates = [HasDQI, HasVLX] in {
5214 // Explicitly specified broadcast string, since we take only 2 elements
5215 // from v4f32x_info source
5216 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5217 "{1to2}">, EVEX_V128;
5218 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5223 // Convert Signed/Unsigned Quardword to Float
5224 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5225 SDNode OpNode, SDNode OpNodeRnd> {
5226 let Predicates = [HasDQI] in {
5227 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5228 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5229 OpNodeRnd>, EVEX_V512;
5231 let Predicates = [HasDQI, HasVLX] in {
5232 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5233 // memory forms of these instructions in Asm Parcer. They have the same
5234 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5235 // due to the same reason.
5236 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5237 "{1to2}", "{x}">, EVEX_V128;
5238 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5239 "{1to4}", "{y}">, EVEX_V256;
5243 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5244 EVEX_CD8<32, CD8VH>;
5246 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5248 PS, EVEX_CD8<32, CD8VF>;
5250 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5252 XS, EVEX_CD8<32, CD8VF>;
5254 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5256 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5258 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5259 X86VFpToUintRnd>, PS,
5260 EVEX_CD8<32, CD8VF>;
5262 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5263 X86VFpToUintRnd>, PS, VEX_W,
5264 EVEX_CD8<64, CD8VF>;
5266 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5267 XS, EVEX_CD8<32, CD8VH>;
5269 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5270 X86VUintToFpRnd>, XD,
5271 EVEX_CD8<32, CD8VF>;
5273 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5274 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5276 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5277 X86cvtpd2IntRnd>, XD, VEX_W,
5278 EVEX_CD8<64, CD8VF>;
5280 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5282 PS, EVEX_CD8<32, CD8VF>;
5283 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5284 X86cvtpd2UIntRnd>, VEX_W,
5285 PS, EVEX_CD8<64, CD8VF>;
5287 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5288 X86cvtpd2IntRnd>, VEX_W,
5289 PD, EVEX_CD8<64, CD8VF>;
5291 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5292 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5294 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5295 X86cvtpd2UIntRnd>, VEX_W,
5296 PD, EVEX_CD8<64, CD8VF>;
5298 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5299 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5301 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5302 X86VFpToSlongRnd>, VEX_W,
5303 PD, EVEX_CD8<64, CD8VF>;
5305 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5306 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5308 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5309 X86VFpToUlongRnd>, VEX_W,
5310 PD, EVEX_CD8<64, CD8VF>;
5312 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5313 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5315 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5316 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5318 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5319 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5321 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5322 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5324 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5325 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5327 let Predicates = [NoVLX] in {
5328 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5329 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5330 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5332 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5333 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5334 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5336 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5337 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5338 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5340 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5341 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5342 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5344 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5345 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5346 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5349 let Predicates = [HasAVX512] in {
5350 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5351 (VCVTPD2PSZrm addr:$src)>;
5352 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5353 (VCVTPS2PDZrm addr:$src)>;
5356 //===----------------------------------------------------------------------===//
5357 // Half precision conversion instructions
5358 //===----------------------------------------------------------------------===//
5359 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5360 X86MemOperand x86memop> {
5361 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5362 "vcvtph2ps\t{$src, $dst|$dst, $src}",
5364 let hasSideEffects = 0, mayLoad = 1 in
5365 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5366 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5369 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
5370 X86MemOperand x86memop> {
5371 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
5372 (ins srcRC:$src1, i32u8imm:$src2),
5373 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5375 let hasSideEffects = 0, mayStore = 1 in
5376 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5377 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
5378 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
5381 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5382 EVEX_CD8<32, CD8VH>;
5383 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
5384 EVEX_CD8<32, CD8VH>;
5386 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
5387 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
5388 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
5390 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5391 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5392 (VCVTPH2PSZrr VR256X:$src)>;
5394 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5395 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5396 "ucomiss">, PS, EVEX, VEX_LIG,
5397 EVEX_CD8<32, CD8VT1>;
5398 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5399 "ucomisd">, PD, EVEX,
5400 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5401 let Pattern = []<dag> in {
5402 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5403 "comiss">, PS, EVEX, VEX_LIG,
5404 EVEX_CD8<32, CD8VT1>;
5405 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5406 "comisd">, PD, EVEX,
5407 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5409 let isCodeGenOnly = 1 in {
5410 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5411 load, "ucomiss">, PS, EVEX, VEX_LIG,
5412 EVEX_CD8<32, CD8VT1>;
5413 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5414 load, "ucomisd">, PD, EVEX,
5415 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5417 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5418 load, "comiss">, PS, EVEX, VEX_LIG,
5419 EVEX_CD8<32, CD8VT1>;
5420 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5421 load, "comisd">, PD, EVEX,
5422 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5426 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5427 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5428 X86VectorVTInfo _> {
5429 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5430 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5431 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5432 "$src2, $src1", "$src1, $src2",
5433 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5434 let mayLoad = 1 in {
5435 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5436 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5437 "$src2, $src1", "$src1, $src2",
5438 (OpNode (_.VT _.RC:$src1),
5439 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5444 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5445 EVEX_CD8<32, CD8VT1>, T8PD;
5446 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5447 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5448 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5449 EVEX_CD8<32, CD8VT1>, T8PD;
5450 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5451 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5453 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5454 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5455 X86VectorVTInfo _> {
5456 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5457 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5458 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5459 let mayLoad = 1 in {
5460 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5461 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5463 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5464 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5465 (ins _.ScalarMemOp:$src), OpcodeStr,
5466 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5468 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5473 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5474 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5475 EVEX_V512, EVEX_CD8<32, CD8VF>;
5476 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5477 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5479 // Define only if AVX512VL feature is present.
5480 let Predicates = [HasVLX] in {
5481 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5482 OpNode, v4f32x_info>,
5483 EVEX_V128, EVEX_CD8<32, CD8VF>;
5484 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5485 OpNode, v8f32x_info>,
5486 EVEX_V256, EVEX_CD8<32, CD8VF>;
5487 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5488 OpNode, v2f64x_info>,
5489 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5490 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5491 OpNode, v4f64x_info>,
5492 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5496 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5497 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5499 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5500 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5501 (VRSQRT14PSZr VR512:$src)>;
5502 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5503 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5504 (VRSQRT14PDZr VR512:$src)>;
5506 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5507 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5508 (VRCP14PSZr VR512:$src)>;
5509 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5510 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5511 (VRCP14PDZr VR512:$src)>;
5513 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5514 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5517 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5518 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5519 "$src2, $src1", "$src1, $src2",
5520 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5521 (i32 FROUND_CURRENT))>;
5523 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5524 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5525 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5526 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5527 (i32 FROUND_NO_EXC))>, EVEX_B;
5529 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5530 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5531 "$src2, $src1", "$src1, $src2",
5532 (OpNode (_.VT _.RC:$src1),
5533 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5534 (i32 FROUND_CURRENT))>;
5537 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5538 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5539 EVEX_CD8<32, CD8VT1>;
5540 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5541 EVEX_CD8<64, CD8VT1>, VEX_W;
5544 let hasSideEffects = 0, Predicates = [HasERI] in {
5545 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5546 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5549 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5550 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5552 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5555 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5556 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5557 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5559 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5560 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5562 (bitconvert (_.LdFrag addr:$src))),
5563 (i32 FROUND_CURRENT))>;
5565 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5566 (ins _.MemOp:$src), OpcodeStr,
5567 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5569 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5570 (i32 FROUND_CURRENT))>, EVEX_B;
5572 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5574 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5575 (ins _.RC:$src), OpcodeStr,
5576 "{sae}, $src", "$src, {sae}",
5577 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5580 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5581 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5582 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5583 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5584 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5585 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5586 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5589 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5591 // Define only if AVX512VL feature is present.
5592 let Predicates = [HasVLX] in {
5593 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5594 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5595 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5596 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5597 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5598 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5599 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5600 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5603 let Predicates = [HasERI], hasSideEffects = 0 in {
5605 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5606 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5607 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5609 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5610 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5612 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5613 SDNode OpNodeRnd, X86VectorVTInfo _>{
5614 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5615 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5616 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5617 EVEX, EVEX_B, EVEX_RC;
5620 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5621 SDNode OpNode, X86VectorVTInfo _>{
5622 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5623 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5624 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5625 let mayLoad = 1 in {
5626 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5627 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5629 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5631 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5632 (ins _.ScalarMemOp:$src), OpcodeStr,
5633 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5635 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5640 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5642 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5644 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5645 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5647 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5648 // Define only if AVX512VL feature is present.
5649 let Predicates = [HasVLX] in {
5650 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5651 OpNode, v4f32x_info>,
5652 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5653 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5654 OpNode, v8f32x_info>,
5655 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5656 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5657 OpNode, v2f64x_info>,
5658 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5659 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5660 OpNode, v4f64x_info>,
5661 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5665 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5667 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5668 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5669 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5670 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5673 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5674 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5676 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5677 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5678 "$src2, $src1", "$src1, $src2",
5679 (OpNodeRnd (_.VT _.RC:$src1),
5681 (i32 FROUND_CURRENT))>;
5683 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5684 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5685 "$src2, $src1", "$src1, $src2",
5686 (OpNodeRnd (_.VT _.RC:$src1),
5687 (_.VT (scalar_to_vector
5688 (_.ScalarLdFrag addr:$src2))),
5689 (i32 FROUND_CURRENT))>;
5691 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5692 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5693 "$rc, $src2, $src1", "$src1, $src2, $rc",
5694 (OpNodeRnd (_.VT _.RC:$src1),
5699 let isCodeGenOnly = 1 in {
5700 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5701 (ins _.FRC:$src1, _.FRC:$src2),
5702 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5705 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5706 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5707 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5710 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5711 (!cast<Instruction>(NAME#SUFF#Zr)
5712 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5714 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5715 (!cast<Instruction>(NAME#SUFF#Zm)
5716 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5719 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5720 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5721 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5722 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5723 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5726 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5727 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5729 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5731 let Predicates = [HasAVX512] in {
5732 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5733 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5734 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5735 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5736 Requires<[OptForSize]>;
5737 def : Pat<(f32 (X86frcp FR32X:$src)),
5738 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5739 def : Pat<(f32 (X86frcp (load addr:$src))),
5740 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5741 Requires<[OptForSize]>;
5745 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5747 let ExeDomain = _.ExeDomain in {
5748 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5749 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5750 "$src3, $src2, $src1", "$src1, $src2, $src3",
5751 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5752 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5754 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5755 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5756 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5757 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5758 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5761 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5762 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5763 "$src3, $src2, $src1", "$src1, $src2, $src3",
5764 (_.VT (X86RndScales (_.VT _.RC:$src1),
5765 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5766 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5768 let Predicates = [HasAVX512] in {
5769 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5770 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5771 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5772 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5773 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5774 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5775 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5776 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5777 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5778 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5779 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5780 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5781 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5782 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5783 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5785 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5786 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5787 addr:$src, (i32 0x1))), _.FRC)>;
5788 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5789 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5790 addr:$src, (i32 0x2))), _.FRC)>;
5791 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5792 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5793 addr:$src, (i32 0x3))), _.FRC)>;
5794 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5795 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5796 addr:$src, (i32 0x4))), _.FRC)>;
5797 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5798 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5799 addr:$src, (i32 0xc))), _.FRC)>;
5803 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5804 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5806 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5807 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5809 //-------------------------------------------------
5810 // Integer truncate and extend operations
5811 //-------------------------------------------------
5813 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5814 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5815 X86MemOperand x86memop> {
5817 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5818 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5819 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5822 // for intrinsic patter match
5823 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5824 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5826 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5829 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5830 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5831 DestInfo.ImmAllZerosV)),
5832 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5835 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5836 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5837 DestInfo.RC:$src0)),
5838 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5839 DestInfo.KRCWM:$mask ,
5842 let mayStore = 1 in {
5843 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5844 (ins x86memop:$dst, SrcInfo.RC:$src),
5845 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5848 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5849 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5850 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5855 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5856 X86VectorVTInfo DestInfo,
5857 PatFrag truncFrag, PatFrag mtruncFrag > {
5859 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5860 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5861 addr:$dst, SrcInfo.RC:$src)>;
5863 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5864 (SrcInfo.VT SrcInfo.RC:$src)),
5865 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5866 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5869 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5870 X86VectorVTInfo DestInfo, string sat > {
5872 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5873 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5874 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5875 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5876 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5877 (SrcInfo.VT SrcInfo.RC:$src))>;
5879 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5880 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5881 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5882 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5883 (SrcInfo.VT SrcInfo.RC:$src))>;
5886 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5887 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5888 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5889 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5890 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5891 Predicate prd = HasAVX512>{
5893 let Predicates = [HasVLX, prd] in {
5894 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5895 DestInfoZ128, x86memopZ128>,
5896 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5897 truncFrag, mtruncFrag>, EVEX_V128;
5899 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5900 DestInfoZ256, x86memopZ256>,
5901 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5902 truncFrag, mtruncFrag>, EVEX_V256;
5904 let Predicates = [prd] in
5905 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5906 DestInfoZ, x86memopZ>,
5907 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5908 truncFrag, mtruncFrag>, EVEX_V512;
5911 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5912 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5913 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5914 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5915 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5917 let Predicates = [HasVLX, prd] in {
5918 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5919 DestInfoZ128, x86memopZ128>,
5920 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5923 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5924 DestInfoZ256, x86memopZ256>,
5925 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5928 let Predicates = [prd] in
5929 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5930 DestInfoZ, x86memopZ>,
5931 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5935 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5936 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5937 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5938 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5940 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5941 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5942 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5943 sat>, EVEX_CD8<8, CD8VO>;
5946 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5947 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5948 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5949 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
5951 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
5952 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
5953 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5954 sat>, EVEX_CD8<16, CD8VQ>;
5957 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5958 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5959 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5960 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
5962 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
5963 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
5964 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5965 sat>, EVEX_CD8<32, CD8VH>;
5968 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5969 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5970 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5971 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
5973 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
5974 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
5975 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5976 sat>, EVEX_CD8<8, CD8VQ>;
5979 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5980 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5981 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5982 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
5984 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
5985 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
5986 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5987 sat>, EVEX_CD8<16, CD8VH>;
5990 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5991 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
5992 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5993 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
5995 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
5996 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
5997 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5998 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6001 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6002 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6003 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6005 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6006 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6007 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6009 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6010 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6011 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6013 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6014 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6015 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6017 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6018 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6019 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6021 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6022 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6023 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6025 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6026 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6027 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6029 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6030 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6031 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6034 let mayLoad = 1 in {
6035 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6036 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6037 (DestInfo.VT (LdFrag addr:$src))>,
6042 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6043 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6044 let Predicates = [HasVLX, HasBWI] in {
6045 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6046 v16i8x_info, i64mem, LdFrag, OpNode>,
6047 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6049 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6050 v16i8x_info, i128mem, LdFrag, OpNode>,
6051 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6053 let Predicates = [HasBWI] in {
6054 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6055 v32i8x_info, i256mem, LdFrag, OpNode>,
6056 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6060 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6061 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6062 let Predicates = [HasVLX, HasAVX512] in {
6063 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6064 v16i8x_info, i32mem, LdFrag, OpNode>,
6065 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6067 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6068 v16i8x_info, i64mem, LdFrag, OpNode>,
6069 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6071 let Predicates = [HasAVX512] in {
6072 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6073 v16i8x_info, i128mem, LdFrag, OpNode>,
6074 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6078 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6079 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6080 let Predicates = [HasVLX, HasAVX512] in {
6081 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6082 v16i8x_info, i16mem, LdFrag, OpNode>,
6083 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6085 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6086 v16i8x_info, i32mem, LdFrag, OpNode>,
6087 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6089 let Predicates = [HasAVX512] in {
6090 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6091 v16i8x_info, i64mem, LdFrag, OpNode>,
6092 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6096 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6097 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6098 let Predicates = [HasVLX, HasAVX512] in {
6099 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6100 v8i16x_info, i64mem, LdFrag, OpNode>,
6101 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6103 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6104 v8i16x_info, i128mem, LdFrag, OpNode>,
6105 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6107 let Predicates = [HasAVX512] in {
6108 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6109 v16i16x_info, i256mem, LdFrag, OpNode>,
6110 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6114 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6115 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6116 let Predicates = [HasVLX, HasAVX512] in {
6117 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6118 v8i16x_info, i32mem, LdFrag, OpNode>,
6119 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6121 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6122 v8i16x_info, i64mem, LdFrag, OpNode>,
6123 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6125 let Predicates = [HasAVX512] in {
6126 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6127 v8i16x_info, i128mem, LdFrag, OpNode>,
6128 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6132 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6133 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6135 let Predicates = [HasVLX, HasAVX512] in {
6136 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6137 v4i32x_info, i64mem, LdFrag, OpNode>,
6138 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6140 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6141 v4i32x_info, i128mem, LdFrag, OpNode>,
6142 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6144 let Predicates = [HasAVX512] in {
6145 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6146 v8i32x_info, i256mem, LdFrag, OpNode>,
6147 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6151 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6152 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6153 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6154 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6155 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6156 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6159 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6160 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6161 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6162 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6163 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6164 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6166 //===----------------------------------------------------------------------===//
6167 // GATHER - SCATTER Operations
6169 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6170 X86MemOperand memop, PatFrag GatherNode> {
6171 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6172 ExeDomain = _.ExeDomain in
6173 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6174 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6175 !strconcat(OpcodeStr#_.Suffix,
6176 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6177 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6178 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6179 vectoraddr:$src2))]>, EVEX, EVEX_K,
6180 EVEX_CD8<_.EltSize, CD8VT1>;
6183 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6184 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6185 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6186 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6187 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6188 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6189 let Predicates = [HasVLX] in {
6190 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6191 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6192 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6193 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6194 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6195 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6196 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6197 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6201 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6202 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6203 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6204 mgatherv16i32>, EVEX_V512;
6205 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6206 mgatherv8i64>, EVEX_V512;
6207 let Predicates = [HasVLX] in {
6208 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6209 vy32xmem, mgatherv8i32>, EVEX_V256;
6210 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6211 vy64xmem, mgatherv4i64>, EVEX_V256;
6212 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6213 vx32xmem, mgatherv4i32>, EVEX_V128;
6214 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6215 vx64xmem, mgatherv2i64>, EVEX_V128;
6220 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6221 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6223 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6224 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6226 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6227 X86MemOperand memop, PatFrag ScatterNode> {
6229 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6231 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6232 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6233 !strconcat(OpcodeStr#_.Suffix,
6234 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6235 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6236 _.KRCWM:$mask, vectoraddr:$dst))]>,
6237 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6240 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6241 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6242 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6243 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6244 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6245 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6246 let Predicates = [HasVLX] in {
6247 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6248 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6249 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6250 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6251 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6252 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6253 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6254 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6258 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6259 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6260 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6261 mscatterv16i32>, EVEX_V512;
6262 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6263 mscatterv8i64>, EVEX_V512;
6264 let Predicates = [HasVLX] in {
6265 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6266 vy32xmem, mscatterv8i32>, EVEX_V256;
6267 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6268 vy64xmem, mscatterv4i64>, EVEX_V256;
6269 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6270 vx32xmem, mscatterv4i32>, EVEX_V128;
6271 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6272 vx64xmem, mscatterv2i64>, EVEX_V128;
6276 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6277 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6279 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6280 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6283 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6284 RegisterClass KRC, X86MemOperand memop> {
6285 let Predicates = [HasPFI], hasSideEffects = 1 in
6286 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6287 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6291 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6292 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6294 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6295 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6297 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6298 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6300 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6301 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6303 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6304 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6306 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6307 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6309 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6310 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6312 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6313 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6315 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6316 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6318 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6319 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6321 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6322 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6324 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6325 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6327 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6328 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6330 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6331 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6333 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6334 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6336 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6337 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6339 // Helper fragments to match sext vXi1 to vXiY.
6340 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6341 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6343 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6344 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6345 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6347 def : Pat<(store VK1:$src, addr:$dst),
6349 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6350 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6352 def : Pat<(store VK8:$src, addr:$dst),
6354 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6355 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6357 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6358 (truncstore node:$val, node:$ptr), [{
6359 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6362 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6363 (MOV8mr addr:$dst, GR8:$src)>;
6365 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6366 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6367 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6368 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6371 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6372 string OpcodeStr, Predicate prd> {
6373 let Predicates = [prd] in
6374 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6376 let Predicates = [prd, HasVLX] in {
6377 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6378 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6382 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6383 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6385 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6387 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6389 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6393 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6395 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6396 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6398 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6401 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6402 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6403 let Predicates = [prd] in
6404 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6407 let Predicates = [prd, HasVLX] in {
6408 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6410 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6415 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6416 avx512vl_i8_info, HasBWI>;
6417 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6418 avx512vl_i16_info, HasBWI>, VEX_W;
6419 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6420 avx512vl_i32_info, HasDQI>;
6421 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6422 avx512vl_i64_info, HasDQI>, VEX_W;
6424 //===----------------------------------------------------------------------===//
6425 // AVX-512 - COMPRESS and EXPAND
6428 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6430 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6431 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6432 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6434 let mayStore = 1 in {
6435 def mr : AVX5128I<opc, MRMDestMem, (outs),
6436 (ins _.MemOp:$dst, _.RC:$src),
6437 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6438 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6440 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6441 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6442 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6443 [(store (_.VT (vselect _.KRCWM:$mask,
6444 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6446 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6450 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6451 AVX512VLVectorVTInfo VTInfo> {
6452 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6454 let Predicates = [HasVLX] in {
6455 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6456 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6460 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6462 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6464 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6466 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6470 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6472 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6473 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6474 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6477 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6478 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6479 (_.VT (X86expand (_.VT (bitconvert
6480 (_.LdFrag addr:$src1)))))>,
6481 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6484 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6485 AVX512VLVectorVTInfo VTInfo> {
6486 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6488 let Predicates = [HasVLX] in {
6489 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6490 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6494 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6496 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6498 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6500 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6503 //handle instruction reg_vec1 = op(reg_vec,imm)
6505 // op(broadcast(eltVt),imm)
6506 //all instruction created with FROUND_CURRENT
6507 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6509 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6510 (ins _.RC:$src1, i32u8imm:$src2),
6511 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6512 (OpNode (_.VT _.RC:$src1),
6514 (i32 FROUND_CURRENT))>;
6515 let mayLoad = 1 in {
6516 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6517 (ins _.MemOp:$src1, i32u8imm:$src2),
6518 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6519 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6521 (i32 FROUND_CURRENT))>;
6522 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6523 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6524 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6525 "${src1}"##_.BroadcastStr##", $src2",
6526 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6528 (i32 FROUND_CURRENT))>, EVEX_B;
6532 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6533 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6534 SDNode OpNode, X86VectorVTInfo _>{
6535 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6536 (ins _.RC:$src1, i32u8imm:$src2),
6537 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6538 "$src1, {sae}, $src2",
6539 (OpNode (_.VT _.RC:$src1),
6541 (i32 FROUND_NO_EXC))>, EVEX_B;
6544 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6545 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6546 let Predicates = [prd] in {
6547 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6548 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6551 let Predicates = [prd, HasVLX] in {
6552 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6554 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6559 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6560 // op(reg_vec2,mem_vec,imm)
6561 // op(reg_vec2,broadcast(eltVt),imm)
6562 //all instruction created with FROUND_CURRENT
6563 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6565 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6566 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6567 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6568 (OpNode (_.VT _.RC:$src1),
6571 (i32 FROUND_CURRENT))>;
6572 let mayLoad = 1 in {
6573 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6574 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6575 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6576 (OpNode (_.VT _.RC:$src1),
6577 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6579 (i32 FROUND_CURRENT))>;
6580 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6581 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6582 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6583 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6584 (OpNode (_.VT _.RC:$src1),
6585 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6587 (i32 FROUND_CURRENT))>, EVEX_B;
6591 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6592 // op(reg_vec2,mem_vec,imm)
6593 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6594 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6596 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6597 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6598 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6599 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6600 (SrcInfo.VT SrcInfo.RC:$src2),
6603 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6604 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6605 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6606 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6607 (SrcInfo.VT (bitconvert
6608 (SrcInfo.LdFrag addr:$src2))),
6612 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6613 // op(reg_vec2,mem_vec,imm)
6614 // op(reg_vec2,broadcast(eltVt),imm)
6615 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6617 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6620 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6621 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6622 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6623 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6624 (OpNode (_.VT _.RC:$src1),
6625 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6626 (i8 imm:$src3))>, EVEX_B;
6629 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6630 // op(reg_vec2,mem_scalar,imm)
6631 //all instruction created with FROUND_CURRENT
6632 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6633 X86VectorVTInfo _> {
6635 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6636 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6637 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6638 (OpNode (_.VT _.RC:$src1),
6641 (i32 FROUND_CURRENT))>;
6642 let mayLoad = 1 in {
6643 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6644 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6645 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6646 (OpNode (_.VT _.RC:$src1),
6647 (_.VT (scalar_to_vector
6648 (_.ScalarLdFrag addr:$src2))),
6650 (i32 FROUND_CURRENT))>;
6652 let isAsmParserOnly = 1 in {
6653 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6654 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6655 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6661 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6662 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6663 SDNode OpNode, X86VectorVTInfo _>{
6664 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6665 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6666 OpcodeStr, "$src3,{sae}, $src2, $src1",
6667 "$src1, $src2,{sae}, $src3",
6668 (OpNode (_.VT _.RC:$src1),
6671 (i32 FROUND_NO_EXC))>, EVEX_B;
6673 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6674 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6675 SDNode OpNode, X86VectorVTInfo _> {
6676 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6677 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6678 OpcodeStr, "$src3,{sae}, $src2, $src1",
6679 "$src1, $src2,{sae}, $src3",
6680 (OpNode (_.VT _.RC:$src1),
6683 (i32 FROUND_NO_EXC))>, EVEX_B;
6686 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6687 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6688 let Predicates = [prd] in {
6689 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6690 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6694 let Predicates = [prd, HasVLX] in {
6695 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6697 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6702 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6703 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6704 let Predicates = [HasBWI] in {
6705 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6706 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6708 let Predicates = [HasBWI, HasVLX] in {
6709 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6710 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6711 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6712 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6716 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6717 bits<8> opc, SDNode OpNode>{
6718 let Predicates = [HasAVX512] in {
6719 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6721 let Predicates = [HasAVX512, HasVLX] in {
6722 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6723 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6727 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6728 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6729 let Predicates = [prd] in {
6730 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6731 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6735 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6736 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6737 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6738 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6739 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6740 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6743 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6744 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6745 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6746 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6747 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6748 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6750 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6751 0x55, X86VFixupimm, HasAVX512>,
6752 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6753 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6754 0x55, X86VFixupimm, HasAVX512>,
6755 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6757 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6758 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6759 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6760 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6761 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6762 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6765 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6766 0x50, X86VRange, HasDQI>,
6767 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6768 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6769 0x50, X86VRange, HasDQI>,
6770 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6772 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6773 0x51, X86VRange, HasDQI>,
6774 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6775 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6776 0x51, X86VRange, HasDQI>,
6777 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6779 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6780 0x57, X86Reduces, HasDQI>,
6781 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6782 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6783 0x57, X86Reduces, HasDQI>,
6784 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6786 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6787 0x27, X86GetMants, HasAVX512>,
6788 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6789 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6790 0x27, X86GetMants, HasAVX512>,
6791 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6793 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6794 bits<8> opc, SDNode OpNode = X86Shuf128>{
6795 let Predicates = [HasAVX512] in {
6796 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6799 let Predicates = [HasAVX512, HasVLX] in {
6800 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6803 let Predicates = [HasAVX512] in {
6804 def : Pat<(v16f32 (ffloor VR512:$src)),
6805 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6806 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6807 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6808 def : Pat<(v16f32 (fceil VR512:$src)),
6809 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6810 def : Pat<(v16f32 (frint VR512:$src)),
6811 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6812 def : Pat<(v16f32 (ftrunc VR512:$src)),
6813 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6815 def : Pat<(v8f64 (ffloor VR512:$src)),
6816 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6817 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6818 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6819 def : Pat<(v8f64 (fceil VR512:$src)),
6820 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6821 def : Pat<(v8f64 (frint VR512:$src)),
6822 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6823 def : Pat<(v8f64 (ftrunc VR512:$src)),
6824 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6827 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6828 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6829 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6830 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6831 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6832 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6833 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6834 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6836 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6837 AVX512VLVectorVTInfo VTInfo_FP>{
6838 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6839 AVX512AIi8Base, EVEX_4V;
6840 let isCodeGenOnly = 1 in {
6841 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6842 AVX512AIi8Base, EVEX_4V;
6846 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6847 EVEX_CD8<32, CD8VF>;
6848 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6849 EVEX_CD8<64, CD8VF>, VEX_W;
6851 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6852 let Predicates = p in
6853 def NAME#_.VTName#rri:
6854 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6855 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6856 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6859 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6860 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6861 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6862 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6864 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6865 avx512vl_i8_info, avx512vl_i8_info>,
6866 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6867 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6868 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6869 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6870 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6873 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
6874 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
6876 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6877 X86VectorVTInfo _> {
6878 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6879 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6881 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6884 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6885 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6887 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6888 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6891 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6892 X86VectorVTInfo _> :
6893 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6895 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6896 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6897 "${src1}"##_.BroadcastStr,
6898 "${src1}"##_.BroadcastStr,
6899 (_.VT (OpNode (X86VBroadcast
6900 (_.ScalarLdFrag addr:$src1))))>,
6901 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6904 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6905 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6906 let Predicates = [prd] in
6907 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6909 let Predicates = [prd, HasVLX] in {
6910 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6912 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6917 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6918 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6919 let Predicates = [prd] in
6920 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6923 let Predicates = [prd, HasVLX] in {
6924 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6926 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6931 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6932 SDNode OpNode, Predicate prd> {
6933 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6935 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6938 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6939 SDNode OpNode, Predicate prd> {
6940 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6941 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6944 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6945 bits<8> opc_d, bits<8> opc_q,
6946 string OpcodeStr, SDNode OpNode> {
6947 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6949 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6953 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6956 (bc_v16i32 (v16i1sextv16i32)),
6957 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6958 (VPABSDZrr VR512:$src)>;
6960 (bc_v8i64 (v8i1sextv8i64)),
6961 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6962 (VPABSQZrr VR512:$src)>;
6964 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
6966 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
6967 let isCodeGenOnly = 1 in
6968 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
6969 ctlz_zero_undef, prd>;
6972 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
6973 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
6975 //===----------------------------------------------------------------------===//
6976 // AVX-512 - Unpack Instructions
6977 //===----------------------------------------------------------------------===//
6978 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
6979 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
6981 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
6982 SSE_INTALU_ITINS_P, HasBWI>;
6983 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
6984 SSE_INTALU_ITINS_P, HasBWI>;
6985 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
6986 SSE_INTALU_ITINS_P, HasBWI>;
6987 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
6988 SSE_INTALU_ITINS_P, HasBWI>;
6990 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
6991 SSE_INTALU_ITINS_P, HasAVX512>;
6992 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
6993 SSE_INTALU_ITINS_P, HasAVX512>;
6994 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
6995 SSE_INTALU_ITINS_P, HasAVX512>;
6996 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
6997 SSE_INTALU_ITINS_P, HasAVX512>;
6999 //===----------------------------------------------------------------------===//
7000 // AVX-512 - Extract & Insert Integer Instructions
7001 //===----------------------------------------------------------------------===//
7003 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7004 X86VectorVTInfo _> {
7006 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7007 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7008 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7009 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7012 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7015 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7016 let Predicates = [HasBWI] in {
7017 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7018 (ins _.RC:$src1, u8imm:$src2),
7019 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7020 [(set GR32orGR64:$dst,
7021 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7024 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7028 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7029 let Predicates = [HasBWI] in {
7030 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7031 (ins _.RC:$src1, u8imm:$src2),
7032 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7033 [(set GR32orGR64:$dst,
7034 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7037 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7041 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7042 RegisterClass GRC> {
7043 let Predicates = [HasDQI] in {
7044 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7045 (ins _.RC:$src1, u8imm:$src2),
7046 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7048 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7052 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7053 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7054 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7055 [(store (extractelt (_.VT _.RC:$src1),
7056 imm:$src2),addr:$dst)]>,
7057 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7061 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7062 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7063 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7064 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7066 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7067 X86VectorVTInfo _, PatFrag LdFrag> {
7068 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7069 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7070 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7072 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7073 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7076 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7077 X86VectorVTInfo _, PatFrag LdFrag> {
7078 let Predicates = [HasBWI] in {
7079 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7080 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7081 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7083 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7085 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7089 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7090 X86VectorVTInfo _, RegisterClass GRC> {
7091 let Predicates = [HasDQI] in {
7092 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7093 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7094 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7096 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7099 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7100 _.ScalarLdFrag>, TAPD;
7104 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7106 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7108 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7109 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7110 //===----------------------------------------------------------------------===//
7111 // VSHUFPS - VSHUFPD Operations
7112 //===----------------------------------------------------------------------===//
7113 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7114 AVX512VLVectorVTInfo VTInfo_FP>{
7115 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7116 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7117 AVX512AIi8Base, EVEX_4V;
7118 let isCodeGenOnly = 1 in {
7119 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7120 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7121 AVX512AIi8Base, EVEX_4V;
7125 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7126 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7127 //===----------------------------------------------------------------------===//
7128 // AVX-512 - Byte shift Left/Right
7129 //===----------------------------------------------------------------------===//
7131 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7132 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7133 def rr : AVX512<opc, MRMr,
7134 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7135 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7136 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7138 def rm : AVX512<opc, MRMm,
7139 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7140 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7141 [(set _.RC:$dst,(_.VT (OpNode
7142 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7145 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7146 Format MRMm, string OpcodeStr, Predicate prd>{
7147 let Predicates = [prd] in
7148 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7149 OpcodeStr, v8i64_info>, EVEX_V512;
7150 let Predicates = [prd, HasVLX] in {
7151 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7152 OpcodeStr, v4i64x_info>, EVEX_V256;
7153 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7154 OpcodeStr, v2i64x_info>, EVEX_V128;
7157 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7158 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7159 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7160 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7163 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7164 string OpcodeStr, X86VectorVTInfo _src>{
7165 def rr : AVX512BI<opc, MRMSrcReg,
7166 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7168 [(set _src.RC:$dst,(_src.VT
7169 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
7171 def rm : AVX512BI<opc, MRMSrcMem,
7172 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7173 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7174 [(set _src.RC:$dst,(_src.VT
7175 (OpNode _src.RC:$src1,
7176 (_src.VT (bitconvert
7177 (_src.LdFrag addr:$src2))))))]>;
7180 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7181 string OpcodeStr, Predicate prd> {
7182 let Predicates = [prd] in
7183 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
7185 let Predicates = [prd, HasVLX] in {
7186 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
7188 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
7193 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7196 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7198 let Constraints = "$src1 = $dst" in {
7199 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7200 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7201 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7202 (OpNode (_.VT _.RC:$src1),
7205 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7206 let mayLoad = 1 in {
7207 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7208 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7209 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7210 (OpNode (_.VT _.RC:$src1),
7212 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7214 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7215 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7216 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7217 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7218 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7219 (OpNode (_.VT _.RC:$src1),
7221 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7222 (i8 imm:$src4))>, EVEX_B,
7223 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7225 }// Constraints = "$src1 = $dst"
7228 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7229 let Predicates = [HasAVX512] in
7230 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7231 let Predicates = [HasAVX512, HasVLX] in {
7232 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7233 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7237 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7238 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;