1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
278 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_custom<O, F, Outs, Ins,
284 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
285 !con((ins _.KRCWM:$mask), Ins),
286 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
290 // Instruction with mask that puts result in mask register,
291 // like "compare" and "vptest"
292 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
294 dag Ins, dag MaskingIns,
296 string AttSrcAsm, string IntelSrcAsm,
298 list<dag> MaskingPattern,
300 InstrItinClass itin = NoItinerary> {
301 def NAME: AVX512<O, F, Outs, Ins,
302 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
303 "$dst "#Round#", "#IntelSrcAsm#"}",
306 def NAME#k: AVX512<O, F, Outs, MaskingIns,
307 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
308 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
309 MaskingPattern, itin>, EVEX_K;
312 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
314 dag Ins, dag MaskingIns,
316 string AttSrcAsm, string IntelSrcAsm,
317 dag RHS, dag MaskingRHS,
319 InstrItinClass itin = NoItinerary> :
320 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
321 AttSrcAsm, IntelSrcAsm,
322 [(set _.KRC:$dst, RHS)],
323 [(set _.KRC:$dst, MaskingRHS)],
326 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
327 dag Outs, dag Ins, string OpcodeStr,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, string Round = "",
330 InstrItinClass itin = NoItinerary> :
331 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
332 !con((ins _.KRCWM:$mask), Ins),
333 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
334 (and _.KRCWM:$mask, RHS),
337 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
338 dag Outs, dag Ins, string OpcodeStr,
339 string AttSrcAsm, string IntelSrcAsm> :
340 AVX512_maskable_custom_cmp<O, F, Outs,
341 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
342 AttSrcAsm, IntelSrcAsm,
343 [],[],"", NoItinerary>;
345 // Bitcasts between 512-bit vector types. Return the original type since
346 // no instruction is needed for the conversion
347 let Predicates = [HasAVX512] in {
348 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
349 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
350 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
351 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
352 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
353 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
354 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
355 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
356 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
357 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
358 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
359 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
360 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
361 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
362 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
363 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
364 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
365 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
366 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
367 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
368 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
369 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
370 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
371 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
372 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
373 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
374 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
375 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
376 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
377 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
378 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
380 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
381 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
382 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
383 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
384 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
385 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
386 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
387 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
388 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
389 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
390 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
391 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
392 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
393 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
394 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
395 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
396 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
397 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
398 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
399 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
400 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
401 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
402 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
403 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
404 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
405 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
406 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
407 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
408 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
409 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
411 // Bitcasts between 256-bit vector types. Return the original type since
412 // no instruction is needed for the conversion
413 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
414 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
415 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
416 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
417 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
418 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
420 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
421 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
422 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
424 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
425 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
426 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
427 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
429 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
431 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
432 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
433 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
434 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
435 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
436 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
437 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
439 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
440 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
441 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
442 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
446 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
449 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
450 isPseudo = 1, Predicates = [HasAVX512] in {
451 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
452 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
455 let Predicates = [HasAVX512] in {
456 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
457 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
458 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
461 //===----------------------------------------------------------------------===//
462 // AVX-512 - VECTOR INSERT
465 multiclass vinsert_for_size_no_alt<int Opcode,
466 X86VectorVTInfo From, X86VectorVTInfo To,
467 PatFrag vinsert_insert,
468 SDNodeXForm INSERT_get_vinsert_imm> {
469 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
470 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
471 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
472 "vinsert" # From.EltTypeName # "x" # From.NumElts #
473 "\t{$src3, $src2, $src1, $dst|"
474 "$dst, $src1, $src2, $src3}",
475 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
476 (From.VT From.RC:$src2),
481 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
482 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
483 "vinsert" # From.EltTypeName # "x" # From.NumElts #
484 "\t{$src3, $src2, $src1, $dst|"
485 "$dst, $src1, $src2, $src3}",
487 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
491 multiclass vinsert_for_size<int Opcode,
492 X86VectorVTInfo From, X86VectorVTInfo To,
493 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
494 PatFrag vinsert_insert,
495 SDNodeXForm INSERT_get_vinsert_imm> :
496 vinsert_for_size_no_alt<Opcode, From, To,
497 vinsert_insert, INSERT_get_vinsert_imm> {
498 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
499 // vinserti32x4. Only add this if 64x2 and friends are not supported
500 // natively via AVX512DQ.
501 let Predicates = [NoDQI] in
502 def : Pat<(vinsert_insert:$ins
503 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
505 VR512:$src1, From.RC:$src2,
506 (INSERT_get_vinsert_imm VR512:$ins)))>;
509 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
510 ValueType EltVT64, int Opcode256> {
511 defm NAME # "32x4" : vinsert_for_size<Opcode128,
512 X86VectorVTInfo< 4, EltVT32, VR128X>,
513 X86VectorVTInfo<16, EltVT32, VR512>,
514 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 X86VectorVTInfo< 8, EltVT64, VR512>,
517 INSERT_get_vinsert128_imm>;
518 let Predicates = [HasDQI] in
519 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
520 X86VectorVTInfo< 2, EltVT64, VR128X>,
521 X86VectorVTInfo< 8, EltVT64, VR512>,
523 INSERT_get_vinsert128_imm>, VEX_W;
524 defm NAME # "64x4" : vinsert_for_size<Opcode256,
525 X86VectorVTInfo< 4, EltVT64, VR256X>,
526 X86VectorVTInfo< 8, EltVT64, VR512>,
527 X86VectorVTInfo< 8, EltVT32, VR256>,
528 X86VectorVTInfo<16, EltVT32, VR512>,
530 INSERT_get_vinsert256_imm>, VEX_W;
531 let Predicates = [HasDQI] in
532 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
533 X86VectorVTInfo< 8, EltVT32, VR256X>,
534 X86VectorVTInfo<16, EltVT32, VR512>,
536 INSERT_get_vinsert256_imm>;
539 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
540 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
542 // vinsertps - insert f32 to XMM
543 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
544 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
545 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
546 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
548 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
549 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
550 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
551 [(set VR128X:$dst, (X86insertps VR128X:$src1,
552 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
553 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
555 //===----------------------------------------------------------------------===//
556 // AVX-512 VECTOR EXTRACT
559 multiclass vextract_for_size<int Opcode,
560 X86VectorVTInfo From, X86VectorVTInfo To,
561 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
562 PatFrag vextract_extract,
563 SDNodeXForm EXTRACT_get_vextract_imm> {
564 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
565 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
566 (ins VR512:$src1, u8imm:$idx),
567 "vextract" # To.EltTypeName # "x4",
568 "$idx, $src1", "$src1, $idx",
569 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
571 AVX512AIi8Base, EVEX, EVEX_V512;
573 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
574 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
575 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
576 "$dst, $src1, $src2}",
577 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
580 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
582 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
583 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
585 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
587 // A 128/256-bit subvector extract from the first 512-bit vector position is
588 // a subregister copy that needs no instruction.
589 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
591 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
593 // And for the alternative types.
594 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
596 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
598 // Intrinsic call with masking.
599 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
601 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
602 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
603 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
604 VR512:$src1, imm:$idx)>;
606 // Intrinsic call with zero-masking.
607 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
609 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
610 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
611 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
612 VR512:$src1, imm:$idx)>;
614 // Intrinsic call without masking.
615 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
617 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
618 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
619 VR512:$src1, imm:$idx)>;
622 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
623 ValueType EltVT64, int Opcode64> {
624 defm NAME # "32x4" : vextract_for_size<Opcode32,
625 X86VectorVTInfo<16, EltVT32, VR512>,
626 X86VectorVTInfo< 4, EltVT32, VR128X>,
627 X86VectorVTInfo< 8, EltVT64, VR512>,
628 X86VectorVTInfo< 2, EltVT64, VR128X>,
630 EXTRACT_get_vextract128_imm>;
631 defm NAME # "64x4" : vextract_for_size<Opcode64,
632 X86VectorVTInfo< 8, EltVT64, VR512>,
633 X86VectorVTInfo< 4, EltVT64, VR256X>,
634 X86VectorVTInfo<16, EltVT32, VR512>,
635 X86VectorVTInfo< 8, EltVT32, VR256>,
637 EXTRACT_get_vextract256_imm>, VEX_W;
640 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
641 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
643 // A 128-bit subvector insert to the first 512-bit vector position
644 // is a subregister copy that needs no instruction.
645 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
646 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
647 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
649 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
650 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
651 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
653 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
654 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
655 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
657 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
658 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
659 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
662 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
663 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
664 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
665 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
666 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
667 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
668 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
669 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
671 // vextractps - extract 32 bits from XMM
672 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
673 (ins VR128X:$src1, u8imm:$src2),
674 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
675 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
678 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
679 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
680 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
681 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
682 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
684 //===---------------------------------------------------------------------===//
687 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
688 ValueType svt, X86VectorVTInfo _> {
689 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
690 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
691 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
695 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
696 (ins _.ScalarMemOp:$src),
697 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
698 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
703 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
704 AVX512VLVectorVTInfo _> {
705 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
708 let Predicates = [HasVLX] in {
709 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
714 let ExeDomain = SSEPackedSingle in {
715 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
716 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
717 let Predicates = [HasVLX] in {
718 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
719 v4f32, v4f32x_info>, EVEX_V128,
720 EVEX_CD8<32, CD8VT1>;
724 let ExeDomain = SSEPackedDouble in {
725 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
726 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
729 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
730 // Later, we can canonize broadcast instructions before ISel phase and
731 // eliminate additional patterns on ISel.
732 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
733 // representations of source
734 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
735 X86VectorVTInfo _, RegisterClass SrcRC_v,
736 RegisterClass SrcRC_s> {
737 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
738 (!cast<Instruction>(InstName##"r")
739 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
741 let AddedComplexity = 30 in {
742 def : Pat<(_.VT (vselect _.KRCWM:$mask,
743 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
744 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
745 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
747 def : Pat<(_.VT(vselect _.KRCWM:$mask,
748 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
749 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
750 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
754 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
756 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
759 let Predicates = [HasVLX] in {
760 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
761 v8f32x_info, VR128X, FR32X>;
762 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
763 v4f32x_info, VR128X, FR32X>;
764 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
765 v4f64x_info, VR128X, FR64X>;
768 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
769 (VBROADCASTSSZm addr:$src)>;
770 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
771 (VBROADCASTSDZm addr:$src)>;
773 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
774 (VBROADCASTSSZm addr:$src)>;
775 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
776 (VBROADCASTSDZm addr:$src)>;
778 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
779 RegisterClass SrcRC> {
780 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
781 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
782 "$src", "$src", []>, T8PD, EVEX;
785 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
786 RegisterClass SrcRC, Predicate prd> {
787 let Predicates = [prd] in
788 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
789 let Predicates = [prd, HasVLX] in {
790 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
791 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
795 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
797 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
799 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
801 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
804 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
805 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
807 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
808 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
810 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
811 (VPBROADCASTDrZr GR32:$src)>;
812 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
813 (VPBROADCASTQrZr GR64:$src)>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
816 (VPBROADCASTDrZr GR32:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
818 (VPBROADCASTQrZr GR64:$src)>;
820 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
821 (v16i32 immAllZerosV), (i16 GR16:$mask))),
822 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
823 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
824 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
825 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
827 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86MemOperand x86memop, PatFrag ld_frag,
829 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
831 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
834 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
835 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
837 !strconcat(OpcodeStr,
838 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
840 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
842 !strconcat(OpcodeStr,
843 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
846 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
849 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
850 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
855 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
857 !strconcat(OpcodeStr,
858 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
859 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
860 (X86VBroadcast (ld_frag addr:$src)),
861 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
865 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
866 loadi32, VR512, v16i32, v4i32, VK16WM>,
867 EVEX_V512, EVEX_CD8<32, CD8VT1>;
868 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
869 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
870 EVEX_CD8<64, CD8VT1>;
872 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
873 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
875 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
878 (_Dst.VT (X86SubVBroadcast
879 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
880 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
882 !strconcat(OpcodeStr,
883 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
885 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
887 !strconcat(OpcodeStr,
888 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
893 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
894 v16i32_info, v4i32x_info>,
895 EVEX_V512, EVEX_CD8<32, CD8VT4>;
896 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
897 v16f32_info, v4f32x_info>,
898 EVEX_V512, EVEX_CD8<32, CD8VT4>;
899 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
900 v8i64_info, v4i64x_info>, VEX_W,
901 EVEX_V512, EVEX_CD8<64, CD8VT4>;
902 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
903 v8f64_info, v4f64x_info>, VEX_W,
904 EVEX_V512, EVEX_CD8<64, CD8VT4>;
906 let Predicates = [HasVLX] in {
907 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
908 v8i32x_info, v4i32x_info>,
909 EVEX_V256, EVEX_CD8<32, CD8VT4>;
910 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
911 v8f32x_info, v4f32x_info>,
912 EVEX_V256, EVEX_CD8<32, CD8VT4>;
914 let Predicates = [HasVLX, HasDQI] in {
915 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
916 v4i64x_info, v2i64x_info>, VEX_W,
917 EVEX_V256, EVEX_CD8<64, CD8VT2>;
918 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
919 v4f64x_info, v2f64x_info>, VEX_W,
920 EVEX_V256, EVEX_CD8<64, CD8VT2>;
922 let Predicates = [HasDQI] in {
923 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
924 v8i64_info, v2i64x_info>, VEX_W,
925 EVEX_V512, EVEX_CD8<64, CD8VT2>;
926 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
927 v16i32_info, v8i32x_info>,
928 EVEX_V512, EVEX_CD8<32, CD8VT8>;
929 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
930 v8f64_info, v2f64x_info>, VEX_W,
931 EVEX_V512, EVEX_CD8<64, CD8VT2>;
932 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
933 v16f32_info, v8f32x_info>,
934 EVEX_V512, EVEX_CD8<32, CD8VT8>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
938 (VPBROADCASTDZrr VR128X:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
940 (VPBROADCASTQZrr VR128X:$src)>;
942 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
943 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
944 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
945 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
947 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
948 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
949 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
950 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
952 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
953 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
954 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
955 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
957 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
958 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
959 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
960 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
962 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
963 (VBROADCASTSSZr VR128X:$src)>;
964 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
965 (VBROADCASTSDZr VR128X:$src)>;
967 // Provide fallback in case the load node that is used in the patterns above
968 // is used by additional users, which prevents the pattern selection.
969 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
970 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
971 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
972 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
975 //===----------------------------------------------------------------------===//
976 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
979 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
981 let Predicates = [HasCDI] in
982 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
984 []>, EVEX, EVEX_V512;
986 let Predicates = [HasCDI, HasVLX] in {
987 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
988 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
989 []>, EVEX, EVEX_V128;
990 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
991 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
992 []>, EVEX, EVEX_V256;
996 let Predicates = [HasCDI] in {
997 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
999 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1003 //===----------------------------------------------------------------------===//
1006 // -- immediate form --
1007 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1008 X86VectorVTInfo _> {
1009 let ExeDomain = _.ExeDomain in {
1010 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1011 (ins _.RC:$src1, u8imm:$src2),
1012 !strconcat(OpcodeStr,
1013 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1015 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1017 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1018 (ins _.MemOp:$src1, u8imm:$src2),
1019 !strconcat(OpcodeStr,
1020 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1022 (_.VT (OpNode (_.LdFrag addr:$src1),
1023 (i8 imm:$src2))))]>,
1024 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1028 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1029 X86VectorVTInfo Ctrl> :
1030 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1031 let ExeDomain = _.ExeDomain in {
1032 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1033 (ins _.RC:$src1, _.RC:$src2),
1034 !strconcat("vpermil" # _.Suffix,
1035 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 (_.VT (X86VPermilpv _.RC:$src1,
1038 (Ctrl.VT Ctrl.RC:$src2))))]>,
1040 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1041 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1042 !strconcat("vpermil" # _.Suffix,
1043 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1045 (_.VT (X86VPermilpv _.RC:$src1,
1046 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1050 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1052 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1055 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1056 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1057 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1058 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1060 // -- VPERM2I - 3 source operands form --
1061 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
1062 PatFrag mem_frag, X86MemOperand x86memop,
1063 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
1064 let Constraints = "$src1 = $dst" in {
1065 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1066 (ins RC:$src1, RC:$src2, RC:$src3),
1067 !strconcat(OpcodeStr,
1068 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1070 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
1073 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1074 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1075 !strconcat(OpcodeStr,
1076 "\t{$src3, $src2, $dst {${mask}}|"
1077 "$dst {${mask}}, $src2, $src3}"),
1078 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1079 (OpNode RC:$src1, RC:$src2,
1084 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1085 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1086 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1087 !strconcat(OpcodeStr,
1088 "\t{$src3, $src2, $dst {${mask}} {z} |",
1089 "$dst {${mask}} {z}, $src2, $src3}"),
1090 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1091 (OpNode RC:$src1, RC:$src2,
1094 (v16i32 immAllZerosV))))))]>,
1097 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1098 (ins RC:$src1, RC:$src2, x86memop:$src3),
1099 !strconcat(OpcodeStr,
1100 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1102 (OpVT (OpNode RC:$src1, RC:$src2,
1103 (mem_frag addr:$src3))))]>, EVEX_4V;
1105 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1106 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1107 !strconcat(OpcodeStr,
1108 "\t{$src3, $src2, $dst {${mask}}|"
1109 "$dst {${mask}}, $src2, $src3}"),
1111 (OpVT (vselect KRC:$mask,
1112 (OpNode RC:$src1, RC:$src2,
1113 (mem_frag addr:$src3)),
1117 let AddedComplexity = 10 in // Prefer over the rrkz variant
1118 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1119 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1120 !strconcat(OpcodeStr,
1121 "\t{$src3, $src2, $dst {${mask}} {z}|"
1122 "$dst {${mask}} {z}, $src2, $src3}"),
1124 (OpVT (vselect KRC:$mask,
1125 (OpNode RC:$src1, RC:$src2,
1126 (mem_frag addr:$src3)),
1128 (v16i32 immAllZerosV))))))]>,
1132 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1133 i512mem, X86VPermiv3, v16i32, VK16WM>,
1134 EVEX_V512, EVEX_CD8<32, CD8VF>;
1135 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1136 i512mem, X86VPermiv3, v8i64, VK8WM>,
1137 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1138 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1139 i512mem, X86VPermiv3, v16f32, VK16WM>,
1140 EVEX_V512, EVEX_CD8<32, CD8VF>;
1141 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1142 i512mem, X86VPermiv3, v8f64, VK8WM>,
1143 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1145 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1146 PatFrag mem_frag, X86MemOperand x86memop,
1147 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1148 ValueType MaskVT, RegisterClass MRC> :
1149 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1151 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1152 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1153 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1155 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1156 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1157 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1158 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1161 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1162 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1163 EVEX_V512, EVEX_CD8<32, CD8VF>;
1164 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1165 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1166 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1167 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1168 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1169 EVEX_V512, EVEX_CD8<32, CD8VF>;
1170 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1171 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1172 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1174 //===----------------------------------------------------------------------===//
1175 // AVX-512 - BLEND using mask
1177 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1178 let ExeDomain = _.ExeDomain in {
1179 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1180 (ins _.RC:$src1, _.RC:$src2),
1181 !strconcat(OpcodeStr,
1182 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1184 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1185 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1186 !strconcat(OpcodeStr,
1187 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1188 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1189 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1190 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1191 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1192 !strconcat(OpcodeStr,
1193 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1194 []>, EVEX_4V, EVEX_KZ;
1195 let mayLoad = 1 in {
1196 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1197 (ins _.RC:$src1, _.MemOp:$src2),
1198 !strconcat(OpcodeStr,
1199 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1200 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1201 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1202 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1203 !strconcat(OpcodeStr,
1204 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1205 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1206 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1207 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1208 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1209 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1210 !strconcat(OpcodeStr,
1211 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1212 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1216 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1218 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1219 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1220 !strconcat(OpcodeStr,
1221 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1222 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1223 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1224 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1225 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1227 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1228 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1229 !strconcat(OpcodeStr,
1230 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1231 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1232 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1236 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1237 AVX512VLVectorVTInfo VTInfo> {
1238 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1239 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1241 let Predicates = [HasVLX] in {
1242 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1243 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1244 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1245 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1249 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1250 AVX512VLVectorVTInfo VTInfo> {
1251 let Predicates = [HasBWI] in
1252 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1254 let Predicates = [HasBWI, HasVLX] in {
1255 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1256 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1261 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1262 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1263 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1264 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1265 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1266 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1269 let Predicates = [HasAVX512] in {
1270 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1271 (v8f32 VR256X:$src2))),
1273 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1274 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1275 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1277 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1278 (v8i32 VR256X:$src2))),
1280 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1281 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1282 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1284 //===----------------------------------------------------------------------===//
1285 // Compare Instructions
1286 //===----------------------------------------------------------------------===//
1288 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1289 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1290 SDNode OpNode, ValueType VT,
1291 PatFrag ld_frag, string Suffix> {
1292 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1293 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1294 !strconcat("vcmp${cc}", Suffix,
1295 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1296 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1297 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1298 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1299 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1300 !strconcat("vcmp${cc}", Suffix,
1301 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1302 [(set VK1:$dst, (OpNode (VT RC:$src1),
1303 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1304 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1305 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1306 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1307 !strconcat("vcmp", Suffix,
1308 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1309 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1311 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1312 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1313 !strconcat("vcmp", Suffix,
1314 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1315 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1319 let Predicates = [HasAVX512] in {
1320 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1322 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1326 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1327 X86VectorVTInfo _> {
1328 def rr : AVX512BI<opc, MRMSrcReg,
1329 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1330 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1331 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1332 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1334 def rm : AVX512BI<opc, MRMSrcMem,
1335 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1337 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1338 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1339 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1340 def rrk : AVX512BI<opc, MRMSrcReg,
1341 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1343 "$dst {${mask}}, $src1, $src2}"),
1344 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1345 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1346 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1348 def rmk : AVX512BI<opc, MRMSrcMem,
1349 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1350 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1351 "$dst {${mask}}, $src1, $src2}"),
1352 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1353 (OpNode (_.VT _.RC:$src1),
1355 (_.LdFrag addr:$src2))))))],
1356 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1359 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1360 X86VectorVTInfo _> :
1361 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1362 let mayLoad = 1 in {
1363 def rmb : AVX512BI<opc, MRMSrcMem,
1364 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1365 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1366 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1367 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1368 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1369 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1370 def rmbk : AVX512BI<opc, MRMSrcMem,
1371 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1372 _.ScalarMemOp:$src2),
1373 !strconcat(OpcodeStr,
1374 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1375 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1376 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1377 (OpNode (_.VT _.RC:$src1),
1379 (_.ScalarLdFrag addr:$src2)))))],
1380 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1384 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1385 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1386 let Predicates = [prd] in
1387 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1390 let Predicates = [prd, HasVLX] in {
1391 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1393 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1398 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1399 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1401 let Predicates = [prd] in
1402 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1405 let Predicates = [prd, HasVLX] in {
1406 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1408 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1413 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1414 avx512vl_i8_info, HasBWI>,
1417 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1418 avx512vl_i16_info, HasBWI>,
1419 EVEX_CD8<16, CD8VF>;
1421 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1422 avx512vl_i32_info, HasAVX512>,
1423 EVEX_CD8<32, CD8VF>;
1425 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1426 avx512vl_i64_info, HasAVX512>,
1427 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1429 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1430 avx512vl_i8_info, HasBWI>,
1433 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1434 avx512vl_i16_info, HasBWI>,
1435 EVEX_CD8<16, CD8VF>;
1437 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1438 avx512vl_i32_info, HasAVX512>,
1439 EVEX_CD8<32, CD8VF>;
1441 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1442 avx512vl_i64_info, HasAVX512>,
1443 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1445 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1446 (COPY_TO_REGCLASS (VPCMPGTDZrr
1447 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1448 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1450 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1451 (COPY_TO_REGCLASS (VPCMPEQDZrr
1452 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1453 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1455 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1456 X86VectorVTInfo _> {
1457 def rri : AVX512AIi8<opc, MRMSrcReg,
1458 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1459 !strconcat("vpcmp${cc}", Suffix,
1460 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1461 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1463 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1465 def rmi : AVX512AIi8<opc, MRMSrcMem,
1466 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1467 !strconcat("vpcmp${cc}", Suffix,
1468 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1469 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1470 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1472 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1473 def rrik : AVX512AIi8<opc, MRMSrcReg,
1474 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1476 !strconcat("vpcmp${cc}", Suffix,
1477 "\t{$src2, $src1, $dst {${mask}}|",
1478 "$dst {${mask}}, $src1, $src2}"),
1479 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1480 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1482 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1484 def rmik : AVX512AIi8<opc, MRMSrcMem,
1485 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1487 !strconcat("vpcmp${cc}", Suffix,
1488 "\t{$src2, $src1, $dst {${mask}}|",
1489 "$dst {${mask}}, $src1, $src2}"),
1490 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1491 (OpNode (_.VT _.RC:$src1),
1492 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1494 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1496 // Accept explicit immediate argument form instead of comparison code.
1497 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1498 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1499 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1500 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1501 "$dst, $src1, $src2, $cc}"),
1502 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1504 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1505 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1506 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1507 "$dst, $src1, $src2, $cc}"),
1508 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1509 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1510 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1512 !strconcat("vpcmp", Suffix,
1513 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1514 "$dst {${mask}}, $src1, $src2, $cc}"),
1515 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1517 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1518 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1520 !strconcat("vpcmp", Suffix,
1521 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1522 "$dst {${mask}}, $src1, $src2, $cc}"),
1523 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1527 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1528 X86VectorVTInfo _> :
1529 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1530 def rmib : AVX512AIi8<opc, MRMSrcMem,
1531 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1533 !strconcat("vpcmp${cc}", Suffix,
1534 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1535 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1536 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1537 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1539 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1540 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1541 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1542 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1543 !strconcat("vpcmp${cc}", Suffix,
1544 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1545 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1546 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1547 (OpNode (_.VT _.RC:$src1),
1548 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1550 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1552 // Accept explicit immediate argument form instead of comparison code.
1553 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1554 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1555 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1557 !strconcat("vpcmp", Suffix,
1558 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1559 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1560 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1561 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1562 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1563 _.ScalarMemOp:$src2, u8imm:$cc),
1564 !strconcat("vpcmp", Suffix,
1565 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1566 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1567 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1571 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1572 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1573 let Predicates = [prd] in
1574 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1576 let Predicates = [prd, HasVLX] in {
1577 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1578 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1582 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1583 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1584 let Predicates = [prd] in
1585 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1588 let Predicates = [prd, HasVLX] in {
1589 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1591 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1596 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1597 HasBWI>, EVEX_CD8<8, CD8VF>;
1598 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1599 HasBWI>, EVEX_CD8<8, CD8VF>;
1601 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1602 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1603 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1604 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1606 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1607 HasAVX512>, EVEX_CD8<32, CD8VF>;
1608 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1609 HasAVX512>, EVEX_CD8<32, CD8VF>;
1611 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1612 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1613 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1614 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1616 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1618 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1619 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1620 "vcmp${cc}"#_.Suffix,
1621 "$src2, $src1", "$src1, $src2",
1622 (X86cmpm (_.VT _.RC:$src1),
1626 let mayLoad = 1 in {
1627 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1628 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1629 "vcmp${cc}"#_.Suffix,
1630 "$src2, $src1", "$src1, $src2",
1631 (X86cmpm (_.VT _.RC:$src1),
1632 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1635 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1637 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1638 "vcmp${cc}"#_.Suffix,
1639 "${src2}"##_.BroadcastStr##", $src1",
1640 "$src1, ${src2}"##_.BroadcastStr,
1641 (X86cmpm (_.VT _.RC:$src1),
1642 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1645 // Accept explicit immediate argument form instead of comparison code.
1646 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1647 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1649 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1651 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1653 let mayLoad = 1 in {
1654 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1656 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1658 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1660 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1662 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1664 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1665 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1670 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1671 // comparison code form (VCMP[EQ/LT/LE/...]
1672 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1673 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1674 "vcmp${cc}"#_.Suffix,
1675 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1676 (X86cmpmRnd (_.VT _.RC:$src1),
1679 (i32 FROUND_NO_EXC))>, EVEX_B;
1681 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1682 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1684 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1686 "$cc,{sae}, $src2, $src1",
1687 "$src1, $src2,{sae}, $cc">, EVEX_B;
1691 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1692 let Predicates = [HasAVX512] in {
1693 defm Z : avx512_vcmp_common<_.info512>,
1694 avx512_vcmp_sae<_.info512>, EVEX_V512;
1697 let Predicates = [HasAVX512,HasVLX] in {
1698 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1699 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1703 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1704 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1705 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1706 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1708 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1709 (COPY_TO_REGCLASS (VCMPPSZrri
1710 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1711 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1713 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1714 (COPY_TO_REGCLASS (VPCMPDZrri
1715 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1716 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1718 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1719 (COPY_TO_REGCLASS (VPCMPUDZrri
1720 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1721 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1724 //-----------------------------------------------------------------
1725 // Mask register copy, including
1726 // - copy between mask registers
1727 // - load/store mask registers
1728 // - copy from GPR to mask register and vice versa
1730 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1731 string OpcodeStr, RegisterClass KRC,
1732 ValueType vvt, X86MemOperand x86memop> {
1733 let hasSideEffects = 0 in {
1734 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1735 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1737 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1738 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1739 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1741 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1742 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1743 [(store KRC:$src, addr:$dst)]>;
1747 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1749 RegisterClass KRC, RegisterClass GRC> {
1750 let hasSideEffects = 0 in {
1751 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1752 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1753 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1754 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1758 let Predicates = [HasDQI] in
1759 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1760 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1763 let Predicates = [HasAVX512] in
1764 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1765 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1768 let Predicates = [HasBWI] in {
1769 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1771 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1775 let Predicates = [HasBWI] in {
1776 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1778 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1782 // GR from/to mask register
1783 let Predicates = [HasDQI] in {
1784 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1785 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1786 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1787 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1789 let Predicates = [HasAVX512] in {
1790 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1791 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1792 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1793 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1795 let Predicates = [HasBWI] in {
1796 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1797 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1799 let Predicates = [HasBWI] in {
1800 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1801 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1805 let Predicates = [HasDQI] in {
1806 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1807 (KMOVBmk addr:$dst, VK8:$src)>;
1808 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1809 (KMOVBkm addr:$src)>;
1811 let Predicates = [HasAVX512, NoDQI] in {
1812 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1813 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1814 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1815 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1817 let Predicates = [HasAVX512] in {
1818 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1819 (KMOVWmk addr:$dst, VK16:$src)>;
1820 def : Pat<(i1 (load addr:$src)),
1821 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1822 (MOV8rm addr:$src), sub_8bit)),
1824 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1825 (KMOVWkm addr:$src)>;
1827 let Predicates = [HasBWI] in {
1828 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1829 (KMOVDmk addr:$dst, VK32:$src)>;
1830 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1831 (KMOVDkm addr:$src)>;
1833 let Predicates = [HasBWI] in {
1834 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1835 (KMOVQmk addr:$dst, VK64:$src)>;
1836 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1837 (KMOVQkm addr:$src)>;
1840 let Predicates = [HasAVX512] in {
1841 def : Pat<(i1 (trunc (i64 GR64:$src))),
1842 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1845 def : Pat<(i1 (trunc (i32 GR32:$src))),
1846 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1848 def : Pat<(i1 (trunc (i8 GR8:$src))),
1850 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1852 def : Pat<(i1 (trunc (i16 GR16:$src))),
1854 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1857 def : Pat<(i32 (zext VK1:$src)),
1858 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1859 def : Pat<(i32 (anyext VK1:$src)),
1860 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
1861 def : Pat<(i8 (zext VK1:$src)),
1864 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1865 def : Pat<(i64 (zext VK1:$src)),
1866 (AND64ri8 (SUBREG_TO_REG (i64 0),
1867 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1868 def : Pat<(i16 (zext VK1:$src)),
1870 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1872 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1873 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1874 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1875 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1877 let Predicates = [HasBWI] in {
1878 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1879 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1880 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1881 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1885 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1886 let Predicates = [HasAVX512, NoDQI] in {
1887 // GR from/to 8-bit mask without native support
1888 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1890 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1891 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1893 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1897 let Predicates = [HasAVX512] in {
1898 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1899 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1900 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1901 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1903 let Predicates = [HasBWI] in {
1904 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1905 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1906 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1907 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1910 // Mask unary operation
1912 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1913 RegisterClass KRC, SDPatternOperator OpNode,
1915 let Predicates = [prd] in
1916 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1917 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1918 [(set KRC:$dst, (OpNode KRC:$src))]>;
1921 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1922 SDPatternOperator OpNode> {
1923 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1925 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1926 HasAVX512>, VEX, PS;
1927 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1928 HasBWI>, VEX, PD, VEX_W;
1929 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1930 HasBWI>, VEX, PS, VEX_W;
1933 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1935 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1936 let Predicates = [HasAVX512] in
1937 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1939 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1940 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1942 defm : avx512_mask_unop_int<"knot", "KNOT">;
1944 let Predicates = [HasDQI] in
1945 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1946 let Predicates = [HasAVX512] in
1947 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1948 let Predicates = [HasBWI] in
1949 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1950 let Predicates = [HasBWI] in
1951 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1953 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1954 let Predicates = [HasAVX512, NoDQI] in {
1955 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1956 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1957 def : Pat<(not VK8:$src),
1959 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1961 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1962 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1963 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1964 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
1966 // Mask binary operation
1967 // - KAND, KANDN, KOR, KXNOR, KXOR
1968 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1969 RegisterClass KRC, SDPatternOperator OpNode,
1970 Predicate prd, bit IsCommutable> {
1971 let Predicates = [prd], isCommutable = IsCommutable in
1972 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1973 !strconcat(OpcodeStr,
1974 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1975 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1978 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1979 SDPatternOperator OpNode, bit IsCommutable> {
1980 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1981 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
1982 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1983 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
1984 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1985 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
1986 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1987 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
1990 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1991 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1993 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
1994 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
1995 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
1996 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
1997 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
1999 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2000 let Predicates = [HasAVX512] in
2001 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2002 (i16 GR16:$src1), (i16 GR16:$src2)),
2003 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2004 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2005 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2008 defm : avx512_mask_binop_int<"kand", "KAND">;
2009 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2010 defm : avx512_mask_binop_int<"kor", "KOR">;
2011 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2012 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2014 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2015 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2016 // for the DQI set, this type is legal and KxxxB instruction is used
2017 let Predicates = [NoDQI] in
2018 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2020 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2021 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2023 // All types smaller than 8 bits require conversion anyway
2024 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2025 (COPY_TO_REGCLASS (Inst
2026 (COPY_TO_REGCLASS VK1:$src1, VK16),
2027 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2028 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2029 (COPY_TO_REGCLASS (Inst
2030 (COPY_TO_REGCLASS VK2:$src1, VK16),
2031 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2032 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2033 (COPY_TO_REGCLASS (Inst
2034 (COPY_TO_REGCLASS VK4:$src1, VK16),
2035 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2038 defm : avx512_binop_pat<and, KANDWrr>;
2039 defm : avx512_binop_pat<andn, KANDNWrr>;
2040 defm : avx512_binop_pat<or, KORWrr>;
2041 defm : avx512_binop_pat<xnor, KXNORWrr>;
2042 defm : avx512_binop_pat<xor, KXORWrr>;
2044 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2045 (KXNORWrr VK16:$src1, VK16:$src2)>;
2046 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2047 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2048 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2049 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2050 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2051 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2053 let Predicates = [NoDQI] in
2054 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2055 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2056 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2058 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2059 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2060 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2062 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2063 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2064 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2066 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2067 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2068 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2071 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2072 RegisterClass KRC> {
2073 let Predicates = [HasAVX512] in
2074 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2075 !strconcat(OpcodeStr,
2076 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2079 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2080 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2084 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2085 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2086 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2087 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2090 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2091 let Predicates = [HasAVX512] in
2092 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2093 (i16 GR16:$src1), (i16 GR16:$src2)),
2094 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2095 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2096 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2098 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2101 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2103 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2104 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2105 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2106 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2109 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2110 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2112 let Predicates = [HasDQI] in
2113 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2115 let Predicates = [HasBWI] in {
2116 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2118 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2123 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2126 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2128 let Predicates = [HasAVX512] in
2129 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2130 !strconcat(OpcodeStr,
2131 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2132 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2135 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2137 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2139 let Predicates = [HasDQI] in
2140 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2142 let Predicates = [HasBWI] in {
2143 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2145 let Predicates = [HasDQI] in
2146 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2151 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2152 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2154 // Mask setting all 0s or 1s
2155 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2156 let Predicates = [HasAVX512] in
2157 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2158 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2159 [(set KRC:$dst, (VT Val))]>;
2162 multiclass avx512_mask_setop_w<PatFrag Val> {
2163 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2164 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2165 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2166 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2169 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2170 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2172 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2173 let Predicates = [HasAVX512] in {
2174 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2175 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2176 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2177 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2178 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2179 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2180 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2182 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2183 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2185 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2186 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2188 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2189 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2191 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2192 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2194 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2195 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2197 let Predicates = [HasVLX] in {
2198 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2199 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2200 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2201 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2202 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2203 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2204 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2205 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2206 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2207 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2210 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2211 (v8i1 (COPY_TO_REGCLASS
2212 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2213 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2215 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2216 (v8i1 (COPY_TO_REGCLASS
2217 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2218 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2220 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2221 (v4i1 (COPY_TO_REGCLASS
2222 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2223 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2225 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2226 (v4i1 (COPY_TO_REGCLASS
2227 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2228 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2230 //===----------------------------------------------------------------------===//
2231 // AVX-512 - Aligned and unaligned load and store
2235 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2236 PatFrag ld_frag, PatFrag mload,
2237 bit IsReMaterializable = 1> {
2238 let hasSideEffects = 0 in {
2239 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2240 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2242 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2243 (ins _.KRCWM:$mask, _.RC:$src),
2244 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2245 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2248 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2249 SchedRW = [WriteLoad] in
2250 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2251 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2252 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2255 let Constraints = "$src0 = $dst" in {
2256 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2257 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2258 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2259 "${dst} {${mask}}, $src1}"),
2260 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2262 (_.VT _.RC:$src0))))], _.ExeDomain>,
2264 let mayLoad = 1, SchedRW = [WriteLoad] in
2265 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2266 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2267 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2268 "${dst} {${mask}}, $src1}"),
2269 [(set _.RC:$dst, (_.VT
2270 (vselect _.KRCWM:$mask,
2271 (_.VT (bitconvert (ld_frag addr:$src1))),
2272 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2274 let mayLoad = 1, SchedRW = [WriteLoad] in
2275 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2276 (ins _.KRCWM:$mask, _.MemOp:$src),
2277 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2278 "${dst} {${mask}} {z}, $src}",
2279 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2280 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2281 _.ExeDomain>, EVEX, EVEX_KZ;
2283 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2284 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2286 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2287 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2289 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2290 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2291 _.KRCWM:$mask, addr:$ptr)>;
2294 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2295 AVX512VLVectorVTInfo _,
2297 bit IsReMaterializable = 1> {
2298 let Predicates = [prd] in
2299 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2300 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2302 let Predicates = [prd, HasVLX] in {
2303 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2304 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2305 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2306 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2310 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2311 AVX512VLVectorVTInfo _,
2313 bit IsReMaterializable = 1> {
2314 let Predicates = [prd] in
2315 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2316 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2318 let Predicates = [prd, HasVLX] in {
2319 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2320 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2321 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2322 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2326 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2327 PatFrag st_frag, PatFrag mstore> {
2328 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2329 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2330 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2332 let Constraints = "$src1 = $dst" in
2333 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2334 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2336 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2337 [], _.ExeDomain>, EVEX, EVEX_K;
2338 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2339 (ins _.KRCWM:$mask, _.RC:$src),
2341 "\t{$src, ${dst} {${mask}} {z}|" #
2342 "${dst} {${mask}} {z}, $src}",
2343 [], _.ExeDomain>, EVEX, EVEX_KZ;
2345 let mayStore = 1 in {
2346 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2347 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2348 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2349 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2350 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2351 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2352 [], _.ExeDomain>, EVEX, EVEX_K;
2355 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2356 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2357 _.KRCWM:$mask, _.RC:$src)>;
2361 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2362 AVX512VLVectorVTInfo _, Predicate prd> {
2363 let Predicates = [prd] in
2364 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2365 masked_store_unaligned>, EVEX_V512;
2367 let Predicates = [prd, HasVLX] in {
2368 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2369 masked_store_unaligned>, EVEX_V256;
2370 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2371 masked_store_unaligned>, EVEX_V128;
2375 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2376 AVX512VLVectorVTInfo _, Predicate prd> {
2377 let Predicates = [prd] in
2378 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2379 masked_store_aligned512>, EVEX_V512;
2381 let Predicates = [prd, HasVLX] in {
2382 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2383 masked_store_aligned256>, EVEX_V256;
2384 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2385 masked_store_aligned128>, EVEX_V128;
2389 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2391 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2392 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2394 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2396 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2397 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2399 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2400 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2401 PS, EVEX_CD8<32, CD8VF>;
2403 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2404 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2405 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2407 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2408 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2409 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2411 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2412 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2413 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2415 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2416 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2417 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2419 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2420 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2421 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2423 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2424 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2425 (VMOVAPDZrm addr:$ptr)>;
2427 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2428 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2429 (VMOVAPSZrm addr:$ptr)>;
2431 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2433 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2435 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2437 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2440 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2442 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2444 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2446 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2449 let Predicates = [HasAVX512, NoVLX] in {
2450 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2451 (VMOVUPSZmrk addr:$ptr,
2452 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2453 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2455 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2456 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2457 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2459 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2460 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2461 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2462 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2465 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2467 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2468 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2470 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2472 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2473 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2475 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2476 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2477 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2479 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2480 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2481 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2483 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2484 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2485 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2487 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2488 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2489 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2491 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2492 (v16i32 immAllZerosV), GR16:$mask)),
2493 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2495 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2496 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2497 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2499 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2501 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2503 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2505 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2508 let AddedComplexity = 20 in {
2509 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2510 (bc_v8i64 (v16i32 immAllZerosV)))),
2511 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2513 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2514 (v8i64 VR512:$src))),
2515 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2518 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2519 (v16i32 immAllZerosV))),
2520 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2522 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2523 (v16i32 VR512:$src))),
2524 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2527 let Predicates = [HasAVX512, NoVLX] in {
2528 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2529 (VMOVDQU32Zmrk addr:$ptr,
2530 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2531 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2533 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2534 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2535 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2538 // Move Int Doubleword to Packed Double Int
2540 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2541 "vmovd\t{$src, $dst|$dst, $src}",
2543 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2545 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2546 "vmovd\t{$src, $dst|$dst, $src}",
2548 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2549 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2550 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2551 "vmovq\t{$src, $dst|$dst, $src}",
2553 (v2i64 (scalar_to_vector GR64:$src)))],
2554 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2555 let isCodeGenOnly = 1 in {
2556 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2557 "vmovq\t{$src, $dst|$dst, $src}",
2558 [(set FR64:$dst, (bitconvert GR64:$src))],
2559 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2560 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2561 "vmovq\t{$src, $dst|$dst, $src}",
2562 [(set GR64:$dst, (bitconvert FR64:$src))],
2563 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2565 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2566 "vmovq\t{$src, $dst|$dst, $src}",
2567 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2568 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2569 EVEX_CD8<64, CD8VT1>;
2571 // Move Int Doubleword to Single Scalar
2573 let isCodeGenOnly = 1 in {
2574 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2575 "vmovd\t{$src, $dst|$dst, $src}",
2576 [(set FR32X:$dst, (bitconvert GR32:$src))],
2577 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2579 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2580 "vmovd\t{$src, $dst|$dst, $src}",
2581 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2582 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2585 // Move doubleword from xmm register to r/m32
2587 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2588 "vmovd\t{$src, $dst|$dst, $src}",
2589 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2590 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2592 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2593 (ins i32mem:$dst, VR128X:$src),
2594 "vmovd\t{$src, $dst|$dst, $src}",
2595 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2596 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2597 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2599 // Move quadword from xmm1 register to r/m64
2601 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2602 "vmovq\t{$src, $dst|$dst, $src}",
2603 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2605 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2606 Requires<[HasAVX512, In64BitMode]>;
2608 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2609 (ins i64mem:$dst, VR128X:$src),
2610 "vmovq\t{$src, $dst|$dst, $src}",
2611 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2612 addr:$dst)], IIC_SSE_MOVDQ>,
2613 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2614 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2616 // Move Scalar Single to Double Int
2618 let isCodeGenOnly = 1 in {
2619 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2621 "vmovd\t{$src, $dst|$dst, $src}",
2622 [(set GR32:$dst, (bitconvert FR32X:$src))],
2623 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2624 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2625 (ins i32mem:$dst, FR32X:$src),
2626 "vmovd\t{$src, $dst|$dst, $src}",
2627 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2628 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2631 // Move Quadword Int to Packed Quadword Int
2633 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2635 "vmovq\t{$src, $dst|$dst, $src}",
2637 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2638 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2640 //===----------------------------------------------------------------------===//
2641 // AVX-512 MOVSS, MOVSD
2642 //===----------------------------------------------------------------------===//
2644 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2645 SDNode OpNode, ValueType vt,
2646 X86MemOperand x86memop, PatFrag mem_pat> {
2647 let hasSideEffects = 0 in {
2648 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2649 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2650 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2651 (scalar_to_vector RC:$src2))))],
2652 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2653 let Constraints = "$src1 = $dst" in
2654 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2655 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2657 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2658 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2659 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2660 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2661 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2663 let mayStore = 1 in {
2664 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2665 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2666 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2668 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2669 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2670 [], IIC_SSE_MOV_S_MR>,
2671 EVEX, VEX_LIG, EVEX_K;
2673 } //hasSideEffects = 0
2676 let ExeDomain = SSEPackedSingle in
2677 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2678 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2680 let ExeDomain = SSEPackedDouble in
2681 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2682 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2684 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2685 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2686 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2688 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2689 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2690 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2692 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2693 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2694 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2696 // For the disassembler
2697 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2698 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2699 (ins VR128X:$src1, FR32X:$src2),
2700 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2702 XS, EVEX_4V, VEX_LIG;
2703 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2704 (ins VR128X:$src1, FR64X:$src2),
2705 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2707 XD, EVEX_4V, VEX_LIG, VEX_W;
2710 let Predicates = [HasAVX512] in {
2711 let AddedComplexity = 15 in {
2712 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2713 // MOVS{S,D} to the lower bits.
2714 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2715 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2716 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2717 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2718 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2719 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2720 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2721 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2723 // Move low f32 and clear high bits.
2724 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2725 (SUBREG_TO_REG (i32 0),
2726 (VMOVSSZrr (v4f32 (V_SET0)),
2727 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2728 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2729 (SUBREG_TO_REG (i32 0),
2730 (VMOVSSZrr (v4i32 (V_SET0)),
2731 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2734 let AddedComplexity = 20 in {
2735 // MOVSSrm zeros the high parts of the register; represent this
2736 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2737 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2738 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2739 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2740 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2741 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2742 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2744 // MOVSDrm zeros the high parts of the register; represent this
2745 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2746 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2747 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2748 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2749 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2750 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2751 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2752 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2753 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2754 def : Pat<(v2f64 (X86vzload addr:$src)),
2755 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2757 // Represent the same patterns above but in the form they appear for
2759 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2760 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2761 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2762 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2763 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2764 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2765 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2766 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2767 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2769 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2770 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2771 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2772 FR32X:$src)), sub_xmm)>;
2773 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2774 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2775 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2776 FR64X:$src)), sub_xmm)>;
2777 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2778 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2779 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2781 // Move low f64 and clear high bits.
2782 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2783 (SUBREG_TO_REG (i32 0),
2784 (VMOVSDZrr (v2f64 (V_SET0)),
2785 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2787 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2788 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2789 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2791 // Extract and store.
2792 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2794 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2795 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2797 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2799 // Shuffle with VMOVSS
2800 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2801 (VMOVSSZrr (v4i32 VR128X:$src1),
2802 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2803 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2804 (VMOVSSZrr (v4f32 VR128X:$src1),
2805 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2808 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2809 (SUBREG_TO_REG (i32 0),
2810 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2811 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2813 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2814 (SUBREG_TO_REG (i32 0),
2815 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2816 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2819 // Shuffle with VMOVSD
2820 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2821 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2822 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2823 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2824 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2825 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2826 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2827 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2830 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2831 (SUBREG_TO_REG (i32 0),
2832 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2833 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2835 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2836 (SUBREG_TO_REG (i32 0),
2837 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2838 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2841 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2842 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2843 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2844 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2845 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2846 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2847 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2848 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2851 let AddedComplexity = 15 in
2852 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2854 "vmovq\t{$src, $dst|$dst, $src}",
2855 [(set VR128X:$dst, (v2i64 (X86vzmovl
2856 (v2i64 VR128X:$src))))],
2857 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2859 let AddedComplexity = 20 in
2860 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2862 "vmovq\t{$src, $dst|$dst, $src}",
2863 [(set VR128X:$dst, (v2i64 (X86vzmovl
2864 (loadv2i64 addr:$src))))],
2865 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2866 EVEX_CD8<8, CD8VT8>;
2868 let Predicates = [HasAVX512] in {
2869 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2870 let AddedComplexity = 20 in {
2871 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2872 (VMOVDI2PDIZrm addr:$src)>;
2873 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2874 (VMOV64toPQIZrr GR64:$src)>;
2875 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2876 (VMOVDI2PDIZrr GR32:$src)>;
2878 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2879 (VMOVDI2PDIZrm addr:$src)>;
2880 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2881 (VMOVDI2PDIZrm addr:$src)>;
2882 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2883 (VMOVZPQILo2PQIZrm addr:$src)>;
2884 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2885 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2886 def : Pat<(v2i64 (X86vzload addr:$src)),
2887 (VMOVZPQILo2PQIZrm addr:$src)>;
2890 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2891 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2892 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2893 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2894 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2895 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2896 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2899 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2900 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2902 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2903 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2905 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2906 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2908 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2909 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2911 //===----------------------------------------------------------------------===//
2912 // AVX-512 - Non-temporals
2913 //===----------------------------------------------------------------------===//
2914 let SchedRW = [WriteLoad] in {
2915 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2916 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2917 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2918 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2919 EVEX_CD8<64, CD8VF>;
2921 let Predicates = [HasAVX512, HasVLX] in {
2922 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2924 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2925 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2926 EVEX_CD8<64, CD8VF>;
2928 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2930 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2931 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2932 EVEX_CD8<64, CD8VF>;
2936 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2937 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2938 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2939 let SchedRW = [WriteStore], mayStore = 1,
2940 AddedComplexity = 400 in
2941 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2942 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2943 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2946 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2947 string elty, string elsz, string vsz512,
2948 string vsz256, string vsz128, Domain d,
2949 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2950 let Predicates = [prd] in
2951 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2952 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2953 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2956 let Predicates = [prd, HasVLX] in {
2957 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2958 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2959 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2962 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2963 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2964 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2969 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2970 "i", "64", "8", "4", "2", SSEPackedInt,
2971 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2973 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2974 "f", "64", "8", "4", "2", SSEPackedDouble,
2975 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2977 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2978 "f", "32", "16", "8", "4", SSEPackedSingle,
2979 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2981 //===----------------------------------------------------------------------===//
2982 // AVX-512 - Integer arithmetic
2984 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2985 X86VectorVTInfo _, OpndItins itins,
2986 bit IsCommutable = 0> {
2987 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2988 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2989 "$src2, $src1", "$src1, $src2",
2990 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2991 itins.rr, IsCommutable>,
2992 AVX512BIBase, EVEX_4V;
2995 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2996 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2997 "$src2, $src1", "$src1, $src2",
2998 (_.VT (OpNode _.RC:$src1,
2999 (bitconvert (_.LdFrag addr:$src2)))),
3001 AVX512BIBase, EVEX_4V;
3004 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3005 X86VectorVTInfo _, OpndItins itins,
3006 bit IsCommutable = 0> :
3007 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3009 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3010 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3011 "${src2}"##_.BroadcastStr##", $src1",
3012 "$src1, ${src2}"##_.BroadcastStr,
3013 (_.VT (OpNode _.RC:$src1,
3015 (_.ScalarLdFrag addr:$src2)))),
3017 AVX512BIBase, EVEX_4V, EVEX_B;
3020 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3021 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3022 Predicate prd, bit IsCommutable = 0> {
3023 let Predicates = [prd] in
3024 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3025 IsCommutable>, EVEX_V512;
3027 let Predicates = [prd, HasVLX] in {
3028 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3029 IsCommutable>, EVEX_V256;
3030 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3031 IsCommutable>, EVEX_V128;
3035 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3036 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3037 Predicate prd, bit IsCommutable = 0> {
3038 let Predicates = [prd] in
3039 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3040 IsCommutable>, EVEX_V512;
3042 let Predicates = [prd, HasVLX] in {
3043 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3044 IsCommutable>, EVEX_V256;
3045 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3046 IsCommutable>, EVEX_V128;
3050 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3051 OpndItins itins, Predicate prd,
3052 bit IsCommutable = 0> {
3053 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3054 itins, prd, IsCommutable>,
3055 VEX_W, EVEX_CD8<64, CD8VF>;
3058 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3059 OpndItins itins, Predicate prd,
3060 bit IsCommutable = 0> {
3061 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3062 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3065 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3066 OpndItins itins, Predicate prd,
3067 bit IsCommutable = 0> {
3068 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3069 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3072 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3073 OpndItins itins, Predicate prd,
3074 bit IsCommutable = 0> {
3075 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3076 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3079 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3080 SDNode OpNode, OpndItins itins, Predicate prd,
3081 bit IsCommutable = 0> {
3082 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
3085 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
3089 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3090 SDNode OpNode, OpndItins itins, Predicate prd,
3091 bit IsCommutable = 0> {
3092 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
3095 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
3099 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3100 bits<8> opc_d, bits<8> opc_q,
3101 string OpcodeStr, SDNode OpNode,
3102 OpndItins itins, bit IsCommutable = 0> {
3103 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3104 itins, HasAVX512, IsCommutable>,
3105 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3106 itins, HasBWI, IsCommutable>;
3109 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3110 SDNode OpNode,X86VectorVTInfo _Src,
3111 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3112 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3113 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3114 "$src2, $src1","$src1, $src2",
3116 (_Src.VT _Src.RC:$src1),
3117 (_Src.VT _Src.RC:$src2))),
3118 itins.rr, IsCommutable>,
3119 AVX512BIBase, EVEX_4V;
3120 let mayLoad = 1 in {
3121 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3122 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3123 "$src2, $src1", "$src1, $src2",
3124 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3125 (bitconvert (_Src.LdFrag addr:$src2)))),
3127 AVX512BIBase, EVEX_4V;
3129 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3130 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3132 "${src2}"##_Dst.BroadcastStr##", $src1",
3133 "$src1, ${src2}"##_Dst.BroadcastStr,
3134 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3135 (_Dst.VT (X86VBroadcast
3136 (_Dst.ScalarLdFrag addr:$src2)))))),
3138 AVX512BIBase, EVEX_4V, EVEX_B;
3142 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3143 SSE_INTALU_ITINS_P, 1>;
3144 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3145 SSE_INTALU_ITINS_P, 0>;
3146 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3147 SSE_INTALU_ITINS_P, HasBWI, 1>;
3148 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3149 SSE_INTALU_ITINS_P, HasBWI, 0>;
3150 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3151 SSE_INTALU_ITINS_P, HasBWI, 1>;
3152 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3153 SSE_INTALU_ITINS_P, HasBWI, 0>;
3154 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3155 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3156 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3157 SSE_INTALU_ITINS_P, HasBWI, 1>;
3158 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3159 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3162 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3163 SDNode OpNode, bit IsCommutable = 0> {
3165 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3166 v16i32_info, v8i64_info, IsCommutable>,
3167 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3168 let Predicates = [HasVLX] in {
3169 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3170 v8i32x_info, v4i64x_info, IsCommutable>,
3171 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3172 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3173 v4i32x_info, v2i64x_info, IsCommutable>,
3174 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3178 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3180 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3183 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3184 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3185 let mayLoad = 1 in {
3186 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3187 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3189 "${src2}"##_Src.BroadcastStr##", $src1",
3190 "$src1, ${src2}"##_Src.BroadcastStr,
3191 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3192 (_Src.VT (X86VBroadcast
3193 (_Src.ScalarLdFrag addr:$src2))))))>,
3194 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3198 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3199 SDNode OpNode,X86VectorVTInfo _Src,
3200 X86VectorVTInfo _Dst> {
3201 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3202 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3203 "$src2, $src1","$src1, $src2",
3205 (_Src.VT _Src.RC:$src1),
3206 (_Src.VT _Src.RC:$src2)))>,
3207 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3208 let mayLoad = 1 in {
3209 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3210 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3211 "$src2, $src1", "$src1, $src2",
3212 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3213 (bitconvert (_Src.LdFrag addr:$src2))))>,
3214 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3218 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3220 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3222 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3223 v32i16_info>, EVEX_V512;
3224 let Predicates = [HasVLX] in {
3225 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3227 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3228 v16i16x_info>, EVEX_V256;
3229 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3231 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3232 v8i16x_info>, EVEX_V128;
3235 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3237 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3238 v64i8_info>, EVEX_V512;
3239 let Predicates = [HasVLX] in {
3240 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3241 v32i8x_info>, EVEX_V256;
3242 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3243 v16i8x_info>, EVEX_V128;
3246 let Predicates = [HasBWI] in {
3247 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3248 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3249 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3250 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3253 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3254 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3255 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3256 SSE_INTALU_ITINS_P, HasBWI, 1>;
3257 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3258 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3260 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3261 SSE_INTALU_ITINS_P, HasBWI, 1>;
3262 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3263 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3264 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3265 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3267 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3268 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3269 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3270 SSE_INTALU_ITINS_P, HasBWI, 1>;
3271 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3272 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3274 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3275 SSE_INTALU_ITINS_P, HasBWI, 1>;
3276 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3277 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3278 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3279 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3281 //===----------------------------------------------------------------------===//
3282 // AVX-512 - Unpack Instructions
3283 //===----------------------------------------------------------------------===//
3285 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3286 PatFrag mem_frag, RegisterClass RC,
3287 X86MemOperand x86memop, string asm,
3289 def rr : AVX512PI<opc, MRMSrcReg,
3290 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3292 (vt (OpNode RC:$src1, RC:$src2)))],
3294 def rm : AVX512PI<opc, MRMSrcMem,
3295 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3297 (vt (OpNode RC:$src1,
3298 (bitconvert (mem_frag addr:$src2)))))],
3302 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3303 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3304 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3305 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3306 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3307 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3308 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3309 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3310 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3311 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3312 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3313 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3315 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3316 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3317 X86MemOperand x86memop> {
3318 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3319 (ins RC:$src1, RC:$src2),
3320 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3321 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3322 IIC_SSE_UNPCK>, EVEX_4V;
3323 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3324 (ins RC:$src1, x86memop:$src2),
3325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3326 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3327 (bitconvert (memop_frag addr:$src2)))))],
3328 IIC_SSE_UNPCK>, EVEX_4V;
3330 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3331 VR512, loadv16i32, i512mem>, EVEX_V512,
3332 EVEX_CD8<32, CD8VF>;
3333 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3334 VR512, loadv8i64, i512mem>, EVEX_V512,
3335 VEX_W, EVEX_CD8<64, CD8VF>;
3336 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3337 VR512, loadv16i32, i512mem>, EVEX_V512,
3338 EVEX_CD8<32, CD8VF>;
3339 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3340 VR512, loadv8i64, i512mem>, EVEX_V512,
3341 VEX_W, EVEX_CD8<64, CD8VF>;
3342 //===----------------------------------------------------------------------===//
3343 // AVX-512 Logical Instructions
3344 //===----------------------------------------------------------------------===//
3346 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3347 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3348 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3349 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3350 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3351 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3352 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3353 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3355 //===----------------------------------------------------------------------===//
3356 // AVX-512 FP arithmetic
3357 //===----------------------------------------------------------------------===//
3358 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3359 SDNode OpNode, SDNode VecNode, OpndItins itins,
3362 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3363 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3364 "$src2, $src1", "$src1, $src2",
3365 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3366 (i32 FROUND_CURRENT)),
3367 itins.rr, IsCommutable>;
3369 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3370 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3371 "$src2, $src1", "$src1, $src2",
3372 (VecNode (_.VT _.RC:$src1),
3373 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3374 (i32 FROUND_CURRENT)),
3375 itins.rm, IsCommutable>;
3376 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3377 Predicates = [HasAVX512] in {
3378 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3379 (ins _.FRC:$src1, _.FRC:$src2),
3380 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3381 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3383 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3384 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3385 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3386 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3387 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3391 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3392 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3394 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3395 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3396 "$rc, $src2, $src1", "$src1, $src2, $rc",
3397 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3398 (i32 imm:$rc)), itins.rr, IsCommutable>,
3401 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3402 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3404 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3405 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3406 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3407 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3408 (i32 FROUND_NO_EXC))>, EVEX_B;
3411 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3413 SizeItins itins, bit IsCommutable> {
3414 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3415 itins.s, IsCommutable>,
3416 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3417 itins.s, IsCommutable>,
3418 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3419 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3420 itins.d, IsCommutable>,
3421 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3422 itins.d, IsCommutable>,
3423 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3426 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3428 SizeItins itins, bit IsCommutable> {
3429 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3430 itins.s, IsCommutable>,
3431 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3432 itins.s, IsCommutable>,
3433 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3434 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3435 itins.d, IsCommutable>,
3436 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3437 itins.d, IsCommutable>,
3438 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3440 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3441 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3442 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3443 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3444 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3445 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3447 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3448 X86VectorVTInfo _, bit IsCommutable> {
3449 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3450 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3451 "$src2, $src1", "$src1, $src2",
3452 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3453 let mayLoad = 1 in {
3454 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3455 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3456 "$src2, $src1", "$src1, $src2",
3457 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3458 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3459 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3460 "${src2}"##_.BroadcastStr##", $src1",
3461 "$src1, ${src2}"##_.BroadcastStr,
3462 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3463 (_.ScalarLdFrag addr:$src2))))>,
3468 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3469 X86VectorVTInfo _, bit IsCommutable> {
3470 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3471 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3472 "$rc, $src2, $src1", "$src1, $src2, $rc",
3473 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3474 EVEX_4V, EVEX_B, EVEX_RC;
3478 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3479 X86VectorVTInfo _, bit IsCommutable> {
3480 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3481 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3482 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3483 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3487 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3488 bit IsCommutable = 0> {
3489 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3490 IsCommutable>, EVEX_V512, PS,
3491 EVEX_CD8<32, CD8VF>;
3492 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3493 IsCommutable>, EVEX_V512, PD, VEX_W,
3494 EVEX_CD8<64, CD8VF>;
3496 // Define only if AVX512VL feature is present.
3497 let Predicates = [HasVLX] in {
3498 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3499 IsCommutable>, EVEX_V128, PS,
3500 EVEX_CD8<32, CD8VF>;
3501 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3502 IsCommutable>, EVEX_V256, PS,
3503 EVEX_CD8<32, CD8VF>;
3504 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3505 IsCommutable>, EVEX_V128, PD, VEX_W,
3506 EVEX_CD8<64, CD8VF>;
3507 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3508 IsCommutable>, EVEX_V256, PD, VEX_W,
3509 EVEX_CD8<64, CD8VF>;
3513 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3514 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3515 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3516 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3517 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3520 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3521 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3522 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3523 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3524 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3527 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3528 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3529 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3530 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3531 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3532 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3533 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3534 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3535 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3536 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3537 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3538 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3539 let Predicates = [HasDQI] in {
3540 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3541 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3542 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3543 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3546 //===----------------------------------------------------------------------===//
3547 // AVX-512 VPTESTM instructions
3548 //===----------------------------------------------------------------------===//
3550 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3551 X86VectorVTInfo _> {
3552 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3553 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3554 "$src2, $src1", "$src1, $src2",
3555 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3558 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3559 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3560 "$src2, $src1", "$src1, $src2",
3561 (OpNode (_.VT _.RC:$src1),
3562 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3564 EVEX_CD8<_.EltSize, CD8VF>;
3567 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3568 X86VectorVTInfo _> {
3570 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3571 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3572 "${src2}"##_.BroadcastStr##", $src1",
3573 "$src1, ${src2}"##_.BroadcastStr,
3574 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3575 (_.ScalarLdFrag addr:$src2))))>,
3576 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3578 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3579 AVX512VLVectorVTInfo _> {
3580 let Predicates = [HasAVX512] in
3581 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3582 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3584 let Predicates = [HasAVX512, HasVLX] in {
3585 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3586 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3587 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3588 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3592 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3593 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3595 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3596 avx512vl_i64_info>, VEX_W;
3599 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3601 let Predicates = [HasBWI] in {
3602 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3604 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3607 let Predicates = [HasVLX, HasBWI] in {
3609 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3611 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3613 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3615 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3620 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3622 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3623 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3625 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3626 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3628 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3629 (v16i32 VR512:$src2), (i16 -1))),
3630 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3632 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3633 (v8i64 VR512:$src2), (i8 -1))),
3634 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3636 //===----------------------------------------------------------------------===//
3637 // AVX-512 Shift instructions
3638 //===----------------------------------------------------------------------===//
3639 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3640 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3641 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3642 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3643 "$src2, $src1", "$src1, $src2",
3644 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3645 SSE_INTSHIFT_ITINS_P.rr>;
3647 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3648 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3649 "$src2, $src1", "$src1, $src2",
3650 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3652 SSE_INTSHIFT_ITINS_P.rm>;
3655 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3656 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3658 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3659 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3660 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3661 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3662 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3665 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3666 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3667 // src2 is always 128-bit
3668 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3669 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3670 "$src2, $src1", "$src1, $src2",
3671 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3672 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3673 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3674 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3675 "$src2, $src1", "$src1, $src2",
3676 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3677 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3681 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3682 ValueType SrcVT, PatFrag bc_frag,
3683 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3684 let Predicates = [prd] in
3685 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3686 VTInfo.info512>, EVEX_V512,
3687 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3688 let Predicates = [prd, HasVLX] in {
3689 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3690 VTInfo.info256>, EVEX_V256,
3691 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3692 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3693 VTInfo.info128>, EVEX_V128,
3694 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3698 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3699 string OpcodeStr, SDNode OpNode> {
3700 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3701 avx512vl_i32_info, HasAVX512>;
3702 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3703 avx512vl_i64_info, HasAVX512>, VEX_W;
3704 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3705 avx512vl_i16_info, HasBWI>;
3708 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3709 string OpcodeStr, SDNode OpNode,
3710 AVX512VLVectorVTInfo VTInfo> {
3711 let Predicates = [HasAVX512] in
3712 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3714 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3715 VTInfo.info512>, EVEX_V512;
3716 let Predicates = [HasAVX512, HasVLX] in {
3717 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3719 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3720 VTInfo.info256>, EVEX_V256;
3721 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3723 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3724 VTInfo.info128>, EVEX_V128;
3728 multiclass avx512_shift_rmi_w<bits<8> opcw,
3729 Format ImmFormR, Format ImmFormM,
3730 string OpcodeStr, SDNode OpNode> {
3731 let Predicates = [HasBWI] in
3732 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3733 v32i16_info>, EVEX_V512;
3734 let Predicates = [HasVLX, HasBWI] in {
3735 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3736 v16i16x_info>, EVEX_V256;
3737 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3738 v8i16x_info>, EVEX_V128;
3742 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3743 Format ImmFormR, Format ImmFormM,
3744 string OpcodeStr, SDNode OpNode> {
3745 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3746 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3747 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3748 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3751 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3752 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3754 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3755 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3757 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3758 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3760 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3761 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3763 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3764 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3765 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3767 //===-------------------------------------------------------------------===//
3768 // Variable Bit Shifts
3769 //===-------------------------------------------------------------------===//
3770 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3771 X86VectorVTInfo _> {
3772 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3773 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3774 "$src2, $src1", "$src1, $src2",
3775 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3776 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3778 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3779 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3780 "$src2, $src1", "$src1, $src2",
3781 (_.VT (OpNode _.RC:$src1,
3782 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3783 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3784 EVEX_CD8<_.EltSize, CD8VF>;
3787 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3788 X86VectorVTInfo _> {
3790 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3791 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3792 "${src2}"##_.BroadcastStr##", $src1",
3793 "$src1, ${src2}"##_.BroadcastStr,
3794 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3795 (_.ScalarLdFrag addr:$src2))))),
3796 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3797 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3799 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3800 AVX512VLVectorVTInfo _> {
3801 let Predicates = [HasAVX512] in
3802 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3803 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3805 let Predicates = [HasAVX512, HasVLX] in {
3806 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3807 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3808 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3809 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3813 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3815 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3817 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3818 avx512vl_i64_info>, VEX_W;
3821 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3823 let Predicates = [HasBWI] in
3824 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3826 let Predicates = [HasVLX, HasBWI] in {
3828 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3830 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3835 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3836 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3837 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3838 avx512_var_shift_w<0x11, "vpsravw", sra>;
3839 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3840 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3841 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3842 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3844 //===-------------------------------------------------------------------===//
3845 // 1-src variable permutation VPERMW/D/Q
3846 //===-------------------------------------------------------------------===//
3847 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3848 AVX512VLVectorVTInfo _> {
3849 let Predicates = [HasAVX512] in
3850 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3851 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3853 let Predicates = [HasAVX512, HasVLX] in
3854 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3855 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3858 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3859 string OpcodeStr, SDNode OpNode,
3860 AVX512VLVectorVTInfo VTInfo> {
3861 let Predicates = [HasAVX512] in
3862 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3864 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3865 VTInfo.info512>, EVEX_V512;
3866 let Predicates = [HasAVX512, HasVLX] in
3867 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3869 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3870 VTInfo.info256>, EVEX_V256;
3874 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
3876 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
3878 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
3879 avx512vl_i64_info>, VEX_W;
3880 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
3882 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
3883 avx512vl_f64_info>, VEX_W;
3885 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
3886 X86VPermi, avx512vl_i64_info>,
3887 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3888 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
3889 X86VPermi, avx512vl_f64_info>,
3890 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3892 //===----------------------------------------------------------------------===//
3893 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
3894 //===----------------------------------------------------------------------===//
3896 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
3897 X86PShufd, avx512vl_i32_info>,
3898 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
3899 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
3900 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
3901 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
3902 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
3903 //===----------------------------------------------------------------------===//
3904 // AVX-512 - MOVDDUP
3905 //===----------------------------------------------------------------------===//
3907 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3908 X86MemOperand x86memop, PatFrag memop_frag> {
3909 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3910 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3911 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3912 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3913 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3915 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3918 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3919 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3920 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3921 (VMOVDDUPZrm addr:$src)>;
3923 //===---------------------------------------------------------------------===//
3924 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3925 //===---------------------------------------------------------------------===//
3926 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3927 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3928 X86MemOperand x86memop> {
3929 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3930 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3931 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3933 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3934 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3935 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3938 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3939 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3940 EVEX_CD8<32, CD8VF>;
3941 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3942 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3943 EVEX_CD8<32, CD8VF>;
3945 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3946 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3947 (VMOVSHDUPZrm addr:$src)>;
3948 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3949 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3950 (VMOVSLDUPZrm addr:$src)>;
3952 //===----------------------------------------------------------------------===//
3953 // Move Low to High and High to Low packed FP Instructions
3954 //===----------------------------------------------------------------------===//
3955 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3956 (ins VR128X:$src1, VR128X:$src2),
3957 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3958 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3959 IIC_SSE_MOV_LH>, EVEX_4V;
3960 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3961 (ins VR128X:$src1, VR128X:$src2),
3962 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3963 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3964 IIC_SSE_MOV_LH>, EVEX_4V;
3966 let Predicates = [HasAVX512] in {
3968 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3969 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3970 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3971 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3974 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3975 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3978 //===----------------------------------------------------------------------===//
3979 // FMA - Fused Multiply Operations
3982 let Constraints = "$src1 = $dst" in {
3983 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3984 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3985 SDPatternOperator OpNode = null_frag> {
3986 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3987 (ins _.RC:$src2, _.RC:$src3),
3988 OpcodeStr, "$src3, $src2", "$src2, $src3",
3989 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3993 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3994 (ins _.RC:$src2, _.MemOp:$src3),
3995 OpcodeStr, "$src3, $src2", "$src2, $src3",
3996 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3999 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4000 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4001 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4002 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4004 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4005 AVX512FMA3Base, EVEX_B;
4007 } // Constraints = "$src1 = $dst"
4009 let Constraints = "$src1 = $dst" in {
4010 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
4011 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
4013 SDPatternOperator OpNode> {
4014 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4015 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4016 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4017 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4018 AVX512FMA3Base, EVEX_B, EVEX_RC;
4020 } // Constraints = "$src1 = $dst"
4022 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
4023 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
4024 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4025 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4028 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
4029 string OpcodeStr, X86VectorVTInfo VTI,
4030 SDPatternOperator OpNode> {
4031 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4032 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4033 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
4034 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
4037 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
4039 SDPatternOperator OpNode,
4040 SDPatternOperator OpNodeRnd> {
4041 let ExeDomain = SSEPackedSingle in {
4042 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4043 v16f32_info, OpNode>,
4044 avx512_fma3_round_forms<opc213, OpcodeStr,
4045 v16f32_info, OpNodeRnd>, EVEX_V512;
4046 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4047 v8f32x_info, OpNode>, EVEX_V256;
4048 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4049 v4f32x_info, OpNode>, EVEX_V128;
4051 let ExeDomain = SSEPackedDouble in {
4052 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4053 v8f64_info, OpNode>,
4054 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
4055 OpNodeRnd>, EVEX_V512, VEX_W;
4056 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4057 v4f64x_info, OpNode>,
4059 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4060 v2f64x_info, OpNode>,
4065 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
4066 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
4067 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
4068 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
4069 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4070 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4072 let Constraints = "$src1 = $dst" in {
4073 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
4074 X86VectorVTInfo _> {
4076 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4077 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
4078 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
4079 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
4081 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4082 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
4083 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
4084 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
4086 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4087 (_.ScalarLdFrag addr:$src2))),
4088 _.RC:$src3))]>, EVEX_B;
4090 } // Constraints = "$src1 = $dst"
4092 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4094 let ExeDomain = SSEPackedSingle in {
4095 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
4096 OpNode,v16f32_info>, EVEX_V512,
4097 EVEX_CD8<32, CD8VF>;
4098 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4099 OpNode, v8f32x_info>, EVEX_V256,
4100 EVEX_CD8<32, CD8VF>;
4101 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4102 OpNode, v4f32x_info>, EVEX_V128,
4103 EVEX_CD8<32, CD8VF>;
4105 let ExeDomain = SSEPackedDouble in {
4106 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
4107 OpNode, v8f64_info>, EVEX_V512,
4108 VEX_W, EVEX_CD8<32, CD8VF>;
4109 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4110 OpNode, v4f64x_info>, EVEX_V256,
4111 VEX_W, EVEX_CD8<32, CD8VF>;
4112 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4113 OpNode, v2f64x_info>, EVEX_V128,
4114 VEX_W, EVEX_CD8<32, CD8VF>;
4118 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
4119 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
4120 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
4121 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
4122 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
4123 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
4126 let Constraints = "$src1 = $dst" in {
4127 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4128 RegisterClass RC, ValueType OpVT,
4129 X86MemOperand x86memop, Operand memop,
4131 let isCommutable = 1 in
4132 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
4133 (ins RC:$src1, RC:$src2, RC:$src3),
4134 !strconcat(OpcodeStr,
4135 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4137 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
4139 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
4140 (ins RC:$src1, RC:$src2, f128mem:$src3),
4141 !strconcat(OpcodeStr,
4142 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4144 (OpVT (OpNode RC:$src2, RC:$src1,
4145 (mem_frag addr:$src3))))]>;
4147 } // Constraints = "$src1 = $dst"
4149 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
4150 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4151 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
4152 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4153 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
4154 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4155 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
4156 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4157 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
4158 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4159 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
4160 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4161 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
4162 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4163 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
4164 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4166 //===----------------------------------------------------------------------===//
4167 // AVX-512 Scalar convert from sign integer to float/double
4168 //===----------------------------------------------------------------------===//
4170 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4171 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4172 PatFrag ld_frag, string asm> {
4173 let hasSideEffects = 0 in {
4174 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4175 (ins DstVT.FRC:$src1, SrcRC:$src),
4176 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4179 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4180 (ins DstVT.FRC:$src1, x86memop:$src),
4181 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4183 } // hasSideEffects = 0
4184 let isCodeGenOnly = 1 in {
4185 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4186 (ins DstVT.RC:$src1, SrcRC:$src2),
4187 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4188 [(set DstVT.RC:$dst,
4189 (OpNode (DstVT.VT DstVT.RC:$src1),
4191 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4193 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4194 (ins DstVT.RC:$src1, x86memop:$src2),
4195 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4196 [(set DstVT.RC:$dst,
4197 (OpNode (DstVT.VT DstVT.RC:$src1),
4198 (ld_frag addr:$src2),
4199 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4200 }//isCodeGenOnly = 1
4203 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4204 X86VectorVTInfo DstVT, string asm> {
4205 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4206 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4208 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4209 [(set DstVT.RC:$dst,
4210 (OpNode (DstVT.VT DstVT.RC:$src1),
4212 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4215 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4216 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4217 PatFrag ld_frag, string asm> {
4218 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4219 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4223 let Predicates = [HasAVX512] in {
4224 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4225 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4226 XS, EVEX_CD8<32, CD8VT1>;
4227 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4228 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4229 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4230 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4231 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4232 XD, EVEX_CD8<32, CD8VT1>;
4233 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4234 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4235 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4237 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4238 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4239 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4240 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4241 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4242 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4243 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4244 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4246 def : Pat<(f32 (sint_to_fp GR32:$src)),
4247 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4248 def : Pat<(f32 (sint_to_fp GR64:$src)),
4249 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4250 def : Pat<(f64 (sint_to_fp GR32:$src)),
4251 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4252 def : Pat<(f64 (sint_to_fp GR64:$src)),
4253 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4255 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR32,
4256 v4f32x_info, i32mem, loadi32,
4257 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4258 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
4259 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4260 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4261 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86SuintToFpRnd, GR32, v2f64x_info,
4262 i32mem, loadi32, "cvtusi2sd{l}">,
4263 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4264 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
4265 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4266 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4268 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4269 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4270 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4271 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4272 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4273 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4274 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4275 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4277 def : Pat<(f32 (uint_to_fp GR32:$src)),
4278 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4279 def : Pat<(f32 (uint_to_fp GR64:$src)),
4280 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4281 def : Pat<(f64 (uint_to_fp GR32:$src)),
4282 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4283 def : Pat<(f64 (uint_to_fp GR64:$src)),
4284 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4287 //===----------------------------------------------------------------------===//
4288 // AVX-512 Scalar convert from float/double to integer
4289 //===----------------------------------------------------------------------===//
4290 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4291 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4293 let hasSideEffects = 0 in {
4294 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4295 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4296 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4297 Requires<[HasAVX512]>;
4299 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4300 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4301 Requires<[HasAVX512]>;
4302 } // hasSideEffects = 0
4304 let Predicates = [HasAVX512] in {
4305 // Convert float/double to signed/unsigned int 32/64
4306 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4307 ssmem, sse_load_f32, "cvtss2si">,
4308 XS, EVEX_CD8<32, CD8VT1>;
4309 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4310 ssmem, sse_load_f32, "cvtss2si">,
4311 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4312 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4313 ssmem, sse_load_f32, "cvtss2usi">,
4314 XS, EVEX_CD8<32, CD8VT1>;
4315 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4316 int_x86_avx512_cvtss2usi64, ssmem,
4317 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4318 EVEX_CD8<32, CD8VT1>;
4319 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4320 sdmem, sse_load_f64, "cvtsd2si">,
4321 XD, EVEX_CD8<64, CD8VT1>;
4322 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4323 sdmem, sse_load_f64, "cvtsd2si">,
4324 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4325 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4326 sdmem, sse_load_f64, "cvtsd2usi">,
4327 XD, EVEX_CD8<64, CD8VT1>;
4328 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4329 int_x86_avx512_cvtsd2usi64, sdmem,
4330 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4331 EVEX_CD8<64, CD8VT1>;
4333 let isCodeGenOnly = 1 in {
4334 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4335 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4336 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4337 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4338 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4339 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4340 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4341 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4342 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4343 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4344 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4345 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4347 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4348 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4349 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4350 } // isCodeGenOnly = 1
4352 // Convert float/double to signed/unsigned int 32/64 with truncation
4353 let isCodeGenOnly = 1 in {
4354 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4355 ssmem, sse_load_f32, "cvttss2si">,
4356 XS, EVEX_CD8<32, CD8VT1>;
4357 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4358 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4359 "cvttss2si">, XS, VEX_W,
4360 EVEX_CD8<32, CD8VT1>;
4361 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4362 sdmem, sse_load_f64, "cvttsd2si">, XD,
4363 EVEX_CD8<64, CD8VT1>;
4364 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4365 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4366 "cvttsd2si">, XD, VEX_W,
4367 EVEX_CD8<64, CD8VT1>;
4368 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4369 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4370 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4371 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4372 int_x86_avx512_cvttss2usi64, ssmem,
4373 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4374 EVEX_CD8<32, CD8VT1>;
4375 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4376 int_x86_avx512_cvttsd2usi,
4377 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4378 EVEX_CD8<64, CD8VT1>;
4379 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4380 int_x86_avx512_cvttsd2usi64, sdmem,
4381 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4382 EVEX_CD8<64, CD8VT1>;
4383 } // isCodeGenOnly = 1
4385 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4386 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4388 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4389 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4390 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4391 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4392 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4393 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4396 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4397 loadf32, "cvttss2si">, XS,
4398 EVEX_CD8<32, CD8VT1>;
4399 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4400 loadf32, "cvttss2usi">, XS,
4401 EVEX_CD8<32, CD8VT1>;
4402 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4403 loadf32, "cvttss2si">, XS, VEX_W,
4404 EVEX_CD8<32, CD8VT1>;
4405 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4406 loadf32, "cvttss2usi">, XS, VEX_W,
4407 EVEX_CD8<32, CD8VT1>;
4408 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4409 loadf64, "cvttsd2si">, XD,
4410 EVEX_CD8<64, CD8VT1>;
4411 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4412 loadf64, "cvttsd2usi">, XD,
4413 EVEX_CD8<64, CD8VT1>;
4414 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4415 loadf64, "cvttsd2si">, XD, VEX_W,
4416 EVEX_CD8<64, CD8VT1>;
4417 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4418 loadf64, "cvttsd2usi">, XD, VEX_W,
4419 EVEX_CD8<64, CD8VT1>;
4421 //===----------------------------------------------------------------------===//
4422 // AVX-512 Convert form float to double and back
4423 //===----------------------------------------------------------------------===//
4424 let hasSideEffects = 0 in {
4425 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4426 (ins FR32X:$src1, FR32X:$src2),
4427 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4428 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4430 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4431 (ins FR32X:$src1, f32mem:$src2),
4432 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4433 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4434 EVEX_CD8<32, CD8VT1>;
4436 // Convert scalar double to scalar single
4437 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4438 (ins FR64X:$src1, FR64X:$src2),
4439 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4440 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4442 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4443 (ins FR64X:$src1, f64mem:$src2),
4444 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4445 []>, EVEX_4V, VEX_LIG, VEX_W,
4446 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4449 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4450 Requires<[HasAVX512]>;
4451 def : Pat<(fextend (loadf32 addr:$src)),
4452 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4454 def : Pat<(extloadf32 addr:$src),
4455 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4456 Requires<[HasAVX512, OptForSize]>;
4458 def : Pat<(extloadf32 addr:$src),
4459 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4460 Requires<[HasAVX512, OptForSpeed]>;
4462 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4463 Requires<[HasAVX512]>;
4465 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4466 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4467 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4469 let hasSideEffects = 0 in {
4470 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4471 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4473 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4474 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4475 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4476 [], d>, EVEX, EVEX_B, EVEX_RC;
4478 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4479 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4481 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4482 } // hasSideEffects = 0
4485 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4486 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4487 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4489 let hasSideEffects = 0 in {
4490 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4491 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4493 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4495 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4496 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4498 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4499 } // hasSideEffects = 0
4502 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4503 loadv8f64, f512mem, v8f32, v8f64,
4504 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4505 EVEX_CD8<64, CD8VF>;
4507 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4508 loadv4f64, f256mem, v8f64, v8f32,
4509 SSEPackedDouble>, EVEX_V512, PS,
4510 EVEX_CD8<32, CD8VH>;
4511 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4512 (VCVTPS2PDZrm addr:$src)>;
4514 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4515 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4516 (VCVTPD2PSZrr VR512:$src)>;
4518 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4519 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4520 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4522 //===----------------------------------------------------------------------===//
4523 // AVX-512 Vector convert from sign integer to float/double
4524 //===----------------------------------------------------------------------===//
4526 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4527 loadv8i64, i512mem, v16f32, v16i32,
4528 SSEPackedSingle>, EVEX_V512, PS,
4529 EVEX_CD8<32, CD8VF>;
4531 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4532 loadv4i64, i256mem, v8f64, v8i32,
4533 SSEPackedDouble>, EVEX_V512, XS,
4534 EVEX_CD8<32, CD8VH>;
4536 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4537 loadv16f32, f512mem, v16i32, v16f32,
4538 SSEPackedSingle>, EVEX_V512, XS,
4539 EVEX_CD8<32, CD8VF>;
4541 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4542 loadv8f64, f512mem, v8i32, v8f64,
4543 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4544 EVEX_CD8<64, CD8VF>;
4546 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4547 loadv16f32, f512mem, v16i32, v16f32,
4548 SSEPackedSingle>, EVEX_V512, PS,
4549 EVEX_CD8<32, CD8VF>;
4551 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4552 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4553 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4554 (VCVTTPS2UDQZrr VR512:$src)>;
4556 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4557 loadv8f64, f512mem, v8i32, v8f64,
4558 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4559 EVEX_CD8<64, CD8VF>;
4561 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4562 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4563 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4564 (VCVTTPD2UDQZrr VR512:$src)>;
4566 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4567 loadv4i64, f256mem, v8f64, v8i32,
4568 SSEPackedDouble>, EVEX_V512, XS,
4569 EVEX_CD8<32, CD8VH>;
4571 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4572 loadv16i32, f512mem, v16f32, v16i32,
4573 SSEPackedSingle>, EVEX_V512, XD,
4574 EVEX_CD8<32, CD8VF>;
4576 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4577 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4578 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4580 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4581 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4582 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4584 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4585 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4586 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4588 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4589 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4590 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4592 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4593 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4594 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4596 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4597 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4598 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4599 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4600 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4601 (VCVTDQ2PDZrr VR256X:$src)>;
4602 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4603 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4604 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4605 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4606 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4607 (VCVTUDQ2PDZrr VR256X:$src)>;
4609 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4610 RegisterClass DstRC, PatFrag mem_frag,
4611 X86MemOperand x86memop, Domain d> {
4612 let hasSideEffects = 0 in {
4613 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4614 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4616 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4617 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4618 [], d>, EVEX, EVEX_B, EVEX_RC;
4620 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4621 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4623 } // hasSideEffects = 0
4626 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4627 loadv16f32, f512mem, SSEPackedSingle>, PD,
4628 EVEX_V512, EVEX_CD8<32, CD8VF>;
4629 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4630 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4631 EVEX_V512, EVEX_CD8<64, CD8VF>;
4633 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4634 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4635 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4637 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4638 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4639 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4641 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4642 loadv16f32, f512mem, SSEPackedSingle>,
4643 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4644 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4645 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4646 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4648 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4649 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4650 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4652 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4653 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4654 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4656 let Predicates = [HasAVX512] in {
4657 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4658 (VCVTPD2PSZrm addr:$src)>;
4659 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4660 (VCVTPS2PDZrm addr:$src)>;
4663 //===----------------------------------------------------------------------===//
4664 // Half precision conversion instructions
4665 //===----------------------------------------------------------------------===//
4666 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4667 X86MemOperand x86memop> {
4668 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4669 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4671 let hasSideEffects = 0, mayLoad = 1 in
4672 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4673 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4676 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4677 X86MemOperand x86memop> {
4678 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4679 (ins srcRC:$src1, i32u8imm:$src2),
4680 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4682 let hasSideEffects = 0, mayStore = 1 in
4683 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4684 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4685 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4688 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4689 EVEX_CD8<32, CD8VH>;
4690 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4691 EVEX_CD8<32, CD8VH>;
4693 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4694 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4695 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4697 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4698 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4699 (VCVTPH2PSZrr VR256X:$src)>;
4701 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4702 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4703 "ucomiss">, PS, EVEX, VEX_LIG,
4704 EVEX_CD8<32, CD8VT1>;
4705 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4706 "ucomisd">, PD, EVEX,
4707 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4708 let Pattern = []<dag> in {
4709 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4710 "comiss">, PS, EVEX, VEX_LIG,
4711 EVEX_CD8<32, CD8VT1>;
4712 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4713 "comisd">, PD, EVEX,
4714 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4716 let isCodeGenOnly = 1 in {
4717 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4718 load, "ucomiss">, PS, EVEX, VEX_LIG,
4719 EVEX_CD8<32, CD8VT1>;
4720 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4721 load, "ucomisd">, PD, EVEX,
4722 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4724 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4725 load, "comiss">, PS, EVEX, VEX_LIG,
4726 EVEX_CD8<32, CD8VT1>;
4727 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4728 load, "comisd">, PD, EVEX,
4729 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4733 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4734 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4735 X86MemOperand x86memop> {
4736 let hasSideEffects = 0 in {
4737 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4738 (ins RC:$src1, RC:$src2),
4739 !strconcat(OpcodeStr,
4740 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4741 let mayLoad = 1 in {
4742 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4743 (ins RC:$src1, x86memop:$src2),
4744 !strconcat(OpcodeStr,
4745 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4750 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4751 EVEX_CD8<32, CD8VT1>;
4752 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4753 VEX_W, EVEX_CD8<64, CD8VT1>;
4754 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4755 EVEX_CD8<32, CD8VT1>;
4756 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4757 VEX_W, EVEX_CD8<64, CD8VT1>;
4759 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4760 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4761 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4762 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4764 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4765 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4766 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4767 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4769 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4770 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4771 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4772 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4774 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4775 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4776 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4777 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4779 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4780 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4781 X86VectorVTInfo _> {
4782 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4783 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4784 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4785 let mayLoad = 1 in {
4786 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4787 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4789 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4790 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4791 (ins _.ScalarMemOp:$src), OpcodeStr,
4792 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4794 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4799 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4800 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4801 EVEX_V512, EVEX_CD8<32, CD8VF>;
4802 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4803 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4805 // Define only if AVX512VL feature is present.
4806 let Predicates = [HasVLX] in {
4807 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4808 OpNode, v4f32x_info>,
4809 EVEX_V128, EVEX_CD8<32, CD8VF>;
4810 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4811 OpNode, v8f32x_info>,
4812 EVEX_V256, EVEX_CD8<32, CD8VF>;
4813 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4814 OpNode, v2f64x_info>,
4815 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4816 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4817 OpNode, v4f64x_info>,
4818 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4822 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4823 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4825 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4826 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4827 (VRSQRT14PSZr VR512:$src)>;
4828 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4829 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4830 (VRSQRT14PDZr VR512:$src)>;
4832 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4833 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4834 (VRCP14PSZr VR512:$src)>;
4835 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4836 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4837 (VRCP14PDZr VR512:$src)>;
4839 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4840 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4843 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4844 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4845 "$src2, $src1", "$src1, $src2",
4846 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4847 (i32 FROUND_CURRENT))>;
4849 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4850 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4851 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4852 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4853 (i32 FROUND_NO_EXC))>, EVEX_B;
4855 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4856 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4857 "$src2, $src1", "$src1, $src2",
4858 (OpNode (_.VT _.RC:$src1),
4859 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4860 (i32 FROUND_CURRENT))>;
4863 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4864 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4865 EVEX_CD8<32, CD8VT1>;
4866 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4867 EVEX_CD8<64, CD8VT1>, VEX_W;
4870 let hasSideEffects = 0, Predicates = [HasERI] in {
4871 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4872 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4874 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4876 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4879 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4880 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4881 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4883 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4884 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4886 (bitconvert (_.LdFrag addr:$src))),
4887 (i32 FROUND_CURRENT))>;
4889 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4890 (ins _.MemOp:$src), OpcodeStr,
4891 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4893 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4894 (i32 FROUND_CURRENT))>, EVEX_B;
4896 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4898 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4899 (ins _.RC:$src), OpcodeStr,
4900 "{sae}, $src", "$src, {sae}",
4901 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
4904 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4905 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4906 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4907 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
4908 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4909 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4910 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4913 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
4915 // Define only if AVX512VL feature is present.
4916 let Predicates = [HasVLX] in {
4917 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
4918 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
4919 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
4920 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
4921 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
4922 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
4923 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
4924 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
4927 let Predicates = [HasERI], hasSideEffects = 0 in {
4929 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
4930 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
4931 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
4933 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
4934 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
4936 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
4937 SDNode OpNodeRnd, X86VectorVTInfo _>{
4938 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4939 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
4940 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
4941 EVEX, EVEX_B, EVEX_RC;
4944 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4945 SDNode OpNode, X86VectorVTInfo _>{
4946 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4947 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4948 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4949 let mayLoad = 1 in {
4950 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4951 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4953 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4955 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4956 (ins _.ScalarMemOp:$src), OpcodeStr,
4957 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4959 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4964 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4965 Intrinsic F32Int, Intrinsic F64Int,
4966 OpndItins itins_s, OpndItins itins_d> {
4967 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4968 (ins FR32X:$src1, FR32X:$src2),
4969 !strconcat(OpcodeStr,
4970 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4971 [], itins_s.rr>, XS, EVEX_4V;
4972 let isCodeGenOnly = 1 in
4973 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4974 (ins VR128X:$src1, VR128X:$src2),
4975 !strconcat(OpcodeStr,
4976 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4978 (F32Int VR128X:$src1, VR128X:$src2))],
4979 itins_s.rr>, XS, EVEX_4V;
4980 let mayLoad = 1 in {
4981 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4982 (ins FR32X:$src1, f32mem:$src2),
4983 !strconcat(OpcodeStr,
4984 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4985 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4986 let isCodeGenOnly = 1 in
4987 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4988 (ins VR128X:$src1, ssmem:$src2),
4989 !strconcat(OpcodeStr,
4990 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4992 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4993 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4995 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4996 (ins FR64X:$src1, FR64X:$src2),
4997 !strconcat(OpcodeStr,
4998 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5000 let isCodeGenOnly = 1 in
5001 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
5002 (ins VR128X:$src1, VR128X:$src2),
5003 !strconcat(OpcodeStr,
5004 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5006 (F64Int VR128X:$src1, VR128X:$src2))],
5007 itins_s.rr>, XD, EVEX_4V, VEX_W;
5008 let mayLoad = 1 in {
5009 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
5010 (ins FR64X:$src1, f64mem:$src2),
5011 !strconcat(OpcodeStr,
5012 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5013 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5014 let isCodeGenOnly = 1 in
5015 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
5016 (ins VR128X:$src1, sdmem:$src2),
5017 !strconcat(OpcodeStr,
5018 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5020 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
5021 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5025 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5027 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5029 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5030 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5032 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5033 // Define only if AVX512VL feature is present.
5034 let Predicates = [HasVLX] in {
5035 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5036 OpNode, v4f32x_info>,
5037 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5038 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5039 OpNode, v8f32x_info>,
5040 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5041 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5042 OpNode, v2f64x_info>,
5043 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5044 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5045 OpNode, v4f64x_info>,
5046 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5050 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5052 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5053 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5054 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5055 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5058 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5059 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5061 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
5062 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
5063 SSE_SQRTSS, SSE_SQRTSD>;
5065 let Predicates = [HasAVX512] in {
5066 def : Pat<(f32 (fsqrt FR32X:$src)),
5067 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5068 def : Pat<(f32 (fsqrt (load addr:$src))),
5069 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5070 Requires<[OptForSize]>;
5071 def : Pat<(f64 (fsqrt FR64X:$src)),
5072 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5073 def : Pat<(f64 (fsqrt (load addr:$src))),
5074 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5075 Requires<[OptForSize]>;
5077 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5078 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5079 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5080 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5081 Requires<[OptForSize]>;
5083 def : Pat<(f32 (X86frcp FR32X:$src)),
5084 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5085 def : Pat<(f32 (X86frcp (load addr:$src))),
5086 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5087 Requires<[OptForSize]>;
5089 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5090 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5091 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5093 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5094 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5096 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5097 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5098 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5100 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5101 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5105 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
5106 X86MemOperand x86memop, RegisterClass RC,
5107 PatFrag mem_frag, Domain d> {
5108 let ExeDomain = d in {
5109 // Intrinsic operation, reg.
5110 // Vector intrinsic operation, reg
5111 def r : AVX512AIi8<opc, MRMSrcReg,
5112 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
5113 !strconcat(OpcodeStr,
5114 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5117 // Vector intrinsic operation, mem
5118 def m : AVX512AIi8<opc, MRMSrcMem,
5119 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
5120 !strconcat(OpcodeStr,
5121 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5126 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
5127 loadv16f32, SSEPackedSingle>, EVEX_V512,
5128 EVEX_CD8<32, CD8VF>;
5130 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
5131 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
5133 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
5136 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
5137 loadv8f64, SSEPackedDouble>, EVEX_V512,
5138 VEX_W, EVEX_CD8<64, CD8VF>;
5140 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
5141 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
5143 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
5146 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5148 let ExeDomain = _.ExeDomain in {
5149 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5150 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5151 "$src3, $src2, $src1", "$src1, $src2, $src3",
5152 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5153 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5155 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5156 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5157 "{sae}, $src3, $src2, $src1", "$src1, $src2, $src3, {sae}",
5158 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5159 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5162 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5163 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5164 "$src3, $src2, $src1", "$src1, $src2, $src3",
5165 (_.VT (X86RndScale (_.VT _.RC:$src1),
5166 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5167 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5169 let Predicates = [HasAVX512] in {
5170 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5171 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5172 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5173 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5174 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5175 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5176 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5177 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5178 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5179 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5180 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5181 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5182 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5183 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5184 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5186 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5187 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5188 addr:$src, (i32 0x1))), _.FRC)>;
5189 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5190 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5191 addr:$src, (i32 0x2))), _.FRC)>;
5192 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5193 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5194 addr:$src, (i32 0x3))), _.FRC)>;
5195 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5196 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5197 addr:$src, (i32 0x4))), _.FRC)>;
5198 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5199 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5200 addr:$src, (i32 0xc))), _.FRC)>;
5204 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5205 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5207 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5208 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5210 let Predicates = [HasAVX512] in {
5211 def : Pat<(v16f32 (ffloor VR512:$src)),
5212 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
5213 def : Pat<(v16f32 (fnearbyint VR512:$src)),
5214 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
5215 def : Pat<(v16f32 (fceil VR512:$src)),
5216 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
5217 def : Pat<(v16f32 (frint VR512:$src)),
5218 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
5219 def : Pat<(v16f32 (ftrunc VR512:$src)),
5220 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
5222 def : Pat<(v8f64 (ffloor VR512:$src)),
5223 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
5224 def : Pat<(v8f64 (fnearbyint VR512:$src)),
5225 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
5226 def : Pat<(v8f64 (fceil VR512:$src)),
5227 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
5228 def : Pat<(v8f64 (frint VR512:$src)),
5229 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
5230 def : Pat<(v8f64 (ftrunc VR512:$src)),
5231 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
5233 //-------------------------------------------------
5234 // Integer truncate and extend operations
5235 //-------------------------------------------------
5237 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
5238 RegisterClass dstRC, RegisterClass srcRC,
5239 RegisterClass KRC, X86MemOperand x86memop> {
5240 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5242 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5245 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5246 (ins KRC:$mask, srcRC:$src),
5247 !strconcat(OpcodeStr,
5248 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5251 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5252 (ins KRC:$mask, srcRC:$src),
5253 !strconcat(OpcodeStr,
5254 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5257 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
5258 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5261 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5262 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
5263 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
5267 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
5268 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5269 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
5270 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5271 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
5272 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5273 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
5274 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5275 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
5276 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5277 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
5278 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5279 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
5280 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5281 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
5282 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5283 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
5284 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5285 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
5286 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5287 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
5288 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5289 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
5290 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5291 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
5292 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5293 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
5294 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5295 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
5296 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5298 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
5299 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
5300 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
5301 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
5302 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
5304 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5305 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
5306 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5307 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
5308 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5309 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
5310 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5311 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
5314 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5315 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5316 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5318 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5319 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5320 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5323 let mayLoad = 1 in {
5324 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5325 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5326 (DestInfo.VT (LdFrag addr:$src))>,
5331 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5332 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5333 let Predicates = [HasVLX, HasBWI] in {
5334 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5335 v16i8x_info, i64mem, LdFrag, OpNode>,
5336 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5338 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5339 v16i8x_info, i128mem, LdFrag, OpNode>,
5340 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5342 let Predicates = [HasBWI] in {
5343 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
5344 v32i8x_info, i256mem, LdFrag, OpNode>,
5345 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
5349 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5350 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5351 let Predicates = [HasVLX, HasAVX512] in {
5352 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5353 v16i8x_info, i32mem, LdFrag, OpNode>,
5354 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
5356 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5357 v16i8x_info, i64mem, LdFrag, OpNode>,
5358 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
5360 let Predicates = [HasAVX512] in {
5361 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5362 v16i8x_info, i128mem, LdFrag, OpNode>,
5363 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
5367 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5368 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5369 let Predicates = [HasVLX, HasAVX512] in {
5370 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5371 v16i8x_info, i16mem, LdFrag, OpNode>,
5372 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
5374 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5375 v16i8x_info, i32mem, LdFrag, OpNode>,
5376 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
5378 let Predicates = [HasAVX512] in {
5379 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5380 v16i8x_info, i64mem, LdFrag, OpNode>,
5381 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
5385 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5386 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5387 let Predicates = [HasVLX, HasAVX512] in {
5388 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5389 v8i16x_info, i64mem, LdFrag, OpNode>,
5390 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
5392 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5393 v8i16x_info, i128mem, LdFrag, OpNode>,
5394 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
5396 let Predicates = [HasAVX512] in {
5397 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5398 v16i16x_info, i256mem, LdFrag, OpNode>,
5399 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
5403 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5404 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5405 let Predicates = [HasVLX, HasAVX512] in {
5406 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5407 v8i16x_info, i32mem, LdFrag, OpNode>,
5408 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
5410 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5411 v8i16x_info, i64mem, LdFrag, OpNode>,
5412 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
5414 let Predicates = [HasAVX512] in {
5415 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5416 v8i16x_info, i128mem, LdFrag, OpNode>,
5417 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
5421 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5422 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
5424 let Predicates = [HasVLX, HasAVX512] in {
5425 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5426 v4i32x_info, i64mem, LdFrag, OpNode>,
5427 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
5429 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5430 v4i32x_info, i128mem, LdFrag, OpNode>,
5431 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
5433 let Predicates = [HasAVX512] in {
5434 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5435 v8i32x_info, i256mem, LdFrag, OpNode>,
5436 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
5440 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
5441 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
5442 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
5443 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
5444 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
5445 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
5448 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
5449 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
5450 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
5451 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
5452 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
5453 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
5455 //===----------------------------------------------------------------------===//
5456 // GATHER - SCATTER Operations
5458 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5459 X86MemOperand memop, PatFrag GatherNode> {
5460 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5461 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5462 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5463 !strconcat(OpcodeStr,
5464 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5465 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5466 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5467 vectoraddr:$src2))]>, EVEX, EVEX_K,
5468 EVEX_CD8<_.EltSize, CD8VT1>;
5471 let ExeDomain = SSEPackedDouble in {
5472 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", v8f64_info, vy64xmem,
5473 mgatherv8i32>, EVEX_V512, VEX_W;
5474 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", v8f64_info, vz64mem,
5475 mgatherv8i64>, EVEX_V512, VEX_W;
5478 let ExeDomain = SSEPackedSingle in {
5479 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", v16f32_info, vz32mem,
5480 mgatherv16i32>, EVEX_V512;
5481 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", v8f32x_info, vz64mem,
5482 mgatherv8i64>, EVEX_V512;
5485 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", v8i64_info, vy64xmem,
5486 mgatherv8i32>, EVEX_V512, VEX_W;
5487 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", v16i32_info, vz32mem,
5488 mgatherv16i32>, EVEX_V512;
5490 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", v8i64_info, vz64mem,
5491 mgatherv8i64>, EVEX_V512, VEX_W;
5492 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", v8i32x_info, vz64mem,
5493 mgatherv8i64>, EVEX_V512;
5495 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5496 X86MemOperand memop, PatFrag ScatterNode> {
5498 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5500 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5501 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5502 !strconcat(OpcodeStr,
5503 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5504 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5505 _.KRCWM:$mask, vectoraddr:$dst))]>,
5506 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5509 let ExeDomain = SSEPackedDouble in {
5510 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", v8f64_info, vy64xmem,
5511 mscatterv8i32>, EVEX_V512, VEX_W;
5512 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", v8f64_info, vz64mem,
5513 mscatterv8i64>, EVEX_V512, VEX_W;
5516 let ExeDomain = SSEPackedSingle in {
5517 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", v16f32_info, vz32mem,
5518 mscatterv16i32>, EVEX_V512;
5519 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", v8f32x_info, vz64mem,
5520 mscatterv8i64>, EVEX_V512;
5523 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", v8i64_info, vy64xmem,
5524 mscatterv8i32>, EVEX_V512, VEX_W;
5525 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", v16i32_info, vz32mem,
5526 mscatterv16i32>, EVEX_V512;
5528 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", v8i64_info, vz64mem,
5529 mscatterv8i64>, EVEX_V512, VEX_W;
5530 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", v8i32x_info, vz64mem,
5531 mscatterv8i64>, EVEX_V512;
5534 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5535 RegisterClass KRC, X86MemOperand memop> {
5536 let Predicates = [HasPFI], hasSideEffects = 1 in
5537 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5538 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5542 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5543 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5545 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5546 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5548 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5549 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5551 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5552 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5554 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5555 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5557 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5558 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5560 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5561 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5563 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5564 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5566 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5567 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5569 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5570 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5572 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5573 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5575 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5576 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5578 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5579 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5581 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5582 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5584 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5585 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5587 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5588 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5589 //===----------------------------------------------------------------------===//
5590 // VSHUFPS - VSHUFPD Operations
5592 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5593 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5595 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5596 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5597 !strconcat(OpcodeStr,
5598 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5599 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5600 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5601 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5602 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5603 (ins RC:$src1, RC:$src2, u8imm:$src3),
5604 !strconcat(OpcodeStr,
5605 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5606 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5607 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5608 EVEX_4V, Sched<[WriteShuffle]>;
5611 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5612 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5613 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5614 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5616 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5617 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5618 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5619 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5620 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5622 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5623 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5624 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5625 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5626 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5628 // Helper fragments to match sext vXi1 to vXiY.
5629 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5630 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5632 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5633 RegisterClass KRC, RegisterClass RC,
5634 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5636 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5637 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5639 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5640 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5642 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5643 !strconcat(OpcodeStr,
5644 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5646 let mayLoad = 1 in {
5647 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5648 (ins x86memop:$src),
5649 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5651 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5652 (ins KRC:$mask, x86memop:$src),
5653 !strconcat(OpcodeStr,
5654 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5656 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5657 (ins KRC:$mask, x86memop:$src),
5658 !strconcat(OpcodeStr,
5659 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5661 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5662 (ins x86scalar_mop:$src),
5663 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5664 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5666 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5667 (ins KRC:$mask, x86scalar_mop:$src),
5668 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5669 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5670 []>, EVEX, EVEX_B, EVEX_K;
5671 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5672 (ins KRC:$mask, x86scalar_mop:$src),
5673 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5674 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5676 []>, EVEX, EVEX_B, EVEX_KZ;
5680 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5681 i512mem, i32mem, "{1to16}">, EVEX_V512,
5682 EVEX_CD8<32, CD8VF>;
5683 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5684 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5685 EVEX_CD8<64, CD8VF>;
5688 (bc_v16i32 (v16i1sextv16i32)),
5689 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5690 (VPABSDZrr VR512:$src)>;
5692 (bc_v8i64 (v8i1sextv8i64)),
5693 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5694 (VPABSQZrr VR512:$src)>;
5696 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5697 (v16i32 immAllZerosV), (i16 -1))),
5698 (VPABSDZrr VR512:$src)>;
5699 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5700 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5701 (VPABSQZrr VR512:$src)>;
5703 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5704 RegisterClass RC, RegisterClass KRC,
5705 X86MemOperand x86memop,
5706 X86MemOperand x86scalar_mop, string BrdcstStr> {
5707 let hasSideEffects = 0 in {
5708 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5710 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5713 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5714 (ins x86memop:$src),
5715 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5718 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5719 (ins x86scalar_mop:$src),
5720 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5721 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5723 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5724 (ins KRC:$mask, RC:$src),
5725 !strconcat(OpcodeStr,
5726 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5729 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5730 (ins KRC:$mask, x86memop:$src),
5731 !strconcat(OpcodeStr,
5732 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5735 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5736 (ins KRC:$mask, x86scalar_mop:$src),
5737 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5738 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5740 []>, EVEX, EVEX_KZ, EVEX_B;
5742 let Constraints = "$src1 = $dst" in {
5743 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5744 (ins RC:$src1, KRC:$mask, RC:$src2),
5745 !strconcat(OpcodeStr,
5746 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5749 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5750 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5751 !strconcat(OpcodeStr,
5752 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5755 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5756 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5757 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5758 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5759 []>, EVEX, EVEX_K, EVEX_B;
5764 let Predicates = [HasCDI] in {
5765 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5766 i512mem, i32mem, "{1to16}">,
5767 EVEX_V512, EVEX_CD8<32, CD8VF>;
5770 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5771 i512mem, i64mem, "{1to8}">,
5772 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5776 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5778 (VPCONFLICTDrrk VR512:$src1,
5779 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5781 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5783 (VPCONFLICTQrrk VR512:$src1,
5784 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5786 let Predicates = [HasCDI] in {
5787 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5788 i512mem, i32mem, "{1to16}">,
5789 EVEX_V512, EVEX_CD8<32, CD8VF>;
5792 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5793 i512mem, i64mem, "{1to8}">,
5794 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5798 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5800 (VPLZCNTDrrk VR512:$src1,
5801 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5803 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5805 (VPLZCNTQrrk VR512:$src1,
5806 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5808 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5809 (VPLZCNTDrm addr:$src)>;
5810 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5811 (VPLZCNTDrr VR512:$src)>;
5812 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5813 (VPLZCNTQrm addr:$src)>;
5814 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5815 (VPLZCNTQrr VR512:$src)>;
5817 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5818 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5819 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5821 def : Pat<(store VK1:$src, addr:$dst),
5823 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5824 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5826 def : Pat<(store VK8:$src, addr:$dst),
5828 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5829 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5831 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5832 (truncstore node:$val, node:$ptr), [{
5833 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5836 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5837 (MOV8mr addr:$dst, GR8:$src)>;
5839 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5840 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5841 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5842 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5845 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5846 string OpcodeStr, Predicate prd> {
5847 let Predicates = [prd] in
5848 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5850 let Predicates = [prd, HasVLX] in {
5851 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5852 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5856 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5857 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5859 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5861 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5863 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5867 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5869 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
5870 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
5871 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5872 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
5875 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
5876 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
5877 let Predicates = [prd] in
5878 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
5881 let Predicates = [prd, HasVLX] in {
5882 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
5884 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
5889 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
5890 avx512vl_i8_info, HasBWI>;
5891 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
5892 avx512vl_i16_info, HasBWI>, VEX_W;
5893 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
5894 avx512vl_i32_info, HasDQI>;
5895 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
5896 avx512vl_i64_info, HasDQI>, VEX_W;
5898 //===----------------------------------------------------------------------===//
5899 // AVX-512 - COMPRESS and EXPAND
5901 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5903 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5904 (ins _.KRCWM:$mask, _.RC:$src),
5905 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5906 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5907 _.ImmAllZerosV)))]>, EVEX_KZ;
5909 let Constraints = "$src0 = $dst" in
5910 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5911 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5912 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5913 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5914 _.RC:$src0)))]>, EVEX_K;
5916 let mayStore = 1 in {
5917 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5918 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5919 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5920 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5922 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5926 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5927 AVX512VLVectorVTInfo VTInfo> {
5928 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5930 let Predicates = [HasVLX] in {
5931 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5932 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5936 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5938 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5940 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5942 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5946 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5948 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5949 (ins _.KRCWM:$mask, _.RC:$src),
5950 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5951 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5952 _.ImmAllZerosV)))]>, EVEX_KZ;
5954 let Constraints = "$src0 = $dst" in
5955 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5956 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5957 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5958 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5959 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5961 let mayLoad = 1, Constraints = "$src0 = $dst" in
5962 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5963 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5964 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5965 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5967 (_.LdFrag addr:$src))),
5969 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5972 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5973 (ins _.KRCWM:$mask, _.MemOp:$src),
5974 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5975 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5976 (_.VT (bitconvert (_.LdFrag addr:$src))),
5977 _.ImmAllZerosV)))]>,
5978 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5981 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5982 AVX512VLVectorVTInfo VTInfo> {
5983 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5985 let Predicates = [HasVLX] in {
5986 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5987 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5991 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5993 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5995 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5997 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6000 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6001 // op(reg_vec2,mem_vec,imm)
6002 // op(reg_vec2,broadcast(eltVt),imm)
6003 //all instruction created with FROUND_CURRENT
6004 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6006 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6007 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6008 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6009 (OpNode (_.VT _.RC:$src1),
6012 (i32 FROUND_CURRENT))>;
6013 let mayLoad = 1 in {
6014 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6015 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
6016 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6017 (OpNode (_.VT _.RC:$src1),
6018 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6020 (i32 FROUND_CURRENT))>;
6021 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6022 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6023 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6024 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6025 (OpNode (_.VT _.RC:$src1),
6026 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6028 (i32 FROUND_CURRENT))>, EVEX_B;
6032 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6033 // op(reg_vec2,mem_vec,imm)
6034 // op(reg_vec2,broadcast(eltVt),imm)
6035 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6037 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6038 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6039 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6040 (OpNode (_.VT _.RC:$src1),
6043 let mayLoad = 1 in {
6044 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6045 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
6046 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6047 (OpNode (_.VT _.RC:$src1),
6048 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6050 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6051 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6052 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6053 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6054 (OpNode (_.VT _.RC:$src1),
6055 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6056 (i8 imm:$src3))>, EVEX_B;
6060 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6061 // op(reg_vec2,mem_scalar,imm)
6062 //all instruction created with FROUND_CURRENT
6063 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6064 X86VectorVTInfo _> {
6066 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6067 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6068 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6069 (OpNode (_.VT _.RC:$src1),
6072 (i32 FROUND_CURRENT))>;
6073 let mayLoad = 1 in {
6074 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6075 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
6076 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6077 (OpNode (_.VT _.RC:$src1),
6078 (_.VT (scalar_to_vector
6079 (_.ScalarLdFrag addr:$src2))),
6081 (i32 FROUND_CURRENT))>;
6083 let isAsmParserOnly = 1 in {
6084 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6085 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6086 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6092 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6093 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6094 SDNode OpNode, X86VectorVTInfo _>{
6095 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6096 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6097 OpcodeStr, "$src3,{sae}, $src2, $src1",
6098 "$src1, $src2,{sae}, $src3",
6099 (OpNode (_.VT _.RC:$src1),
6102 (i32 FROUND_NO_EXC))>, EVEX_B;
6104 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6105 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6106 SDNode OpNode, X86VectorVTInfo _> {
6107 defm NAME: avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _>;
6110 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6111 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6112 let Predicates = [prd] in {
6113 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6114 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6118 let Predicates = [prd, HasVLX] in {
6119 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6121 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6126 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6127 bits<8> opc, SDNode OpNode>{
6128 let Predicates = [HasAVX512] in {
6129 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6131 let Predicates = [HasAVX512, HasVLX] in {
6132 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6133 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6137 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6138 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6139 let Predicates = [prd] in {
6140 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6141 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6145 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6146 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6147 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6148 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6149 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6150 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6152 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6153 0x55, X86VFixupimm, HasAVX512>,
6154 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6155 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6156 0x55, X86VFixupimm, HasAVX512>,
6157 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6159 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6160 0x50, X86VRange, HasDQI>,
6161 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6162 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6163 0x50, X86VRange, HasDQI>,
6164 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6166 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6167 0x51, X86VRange, HasDQI>,
6168 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6169 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6170 0x51, X86VRange, HasDQI>,
6171 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6174 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6175 bits<8> opc, SDNode OpNode = X86Shuf128>{
6176 let Predicates = [HasAVX512] in {
6177 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6180 let Predicates = [HasAVX512, HasVLX] in {
6181 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6185 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6186 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6187 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6188 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6189 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6190 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6191 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6192 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6194 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6195 AVX512VLVectorVTInfo VTInfo_FP>{
6196 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6197 AVX512AIi8Base, EVEX_4V;
6198 let isCodeGenOnly = 1 in {
6199 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6200 AVX512AIi8Base, EVEX_4V;
6204 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6205 EVEX_CD8<32, CD8VF>;
6206 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6207 EVEX_CD8<64, CD8VF>, VEX_W;