1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
25 string VTName = "v" # NumElts # EltVT;
28 ValueType VT = !cast<ValueType>(VTName);
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
35 // "i" for integer types and "f" for floating-point types
36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
38 // Size of RC in bits, e.g. 512 for VR512.
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
63 // The corresponding float type, e.g. v16f32 for v16i32
64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
84 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
85 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
86 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
87 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
88 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
89 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
91 // "x" in v32i8x_info means RC = VR256X
92 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
93 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
94 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
95 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
97 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
98 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
99 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
100 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
102 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
103 X86VectorVTInfo i128> {
104 X86VectorVTInfo info512 = i512;
105 X86VectorVTInfo info256 = i256;
106 X86VectorVTInfo info128 = i128;
109 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
111 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
113 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
115 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
119 // Common base class of AVX512_masking and AVX512_masking_3src.
120 multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
122 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
124 string AttSrcAsm, string IntelSrcAsm,
125 dag RHS, dag MaskingRHS,
126 string MaskingConstraint = "",
127 InstrItinClass itin = NoItinerary,
128 bit IsCommutable = 0> {
129 let isCommutable = IsCommutable in
130 def NAME: AVX512<O, F, Outs, Ins,
131 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
132 "$dst, "#IntelSrcAsm#"}",
133 [(set _.RC:$dst, RHS)], itin>;
135 // Prefer over VMOV*rrk Pat<>
136 let AddedComplexity = 20 in
137 def NAME#k: AVX512<O, F, Outs, MaskingIns,
138 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
139 "$dst {${mask}}, "#IntelSrcAsm#"}",
140 [(set _.RC:$dst, MaskingRHS)], itin>,
142 // In case of the 3src subclass this is overridden with a let.
143 string Constraints = MaskingConstraint;
145 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
146 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
147 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
148 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
150 (vselect _.KRCWM:$mask, RHS,
152 (v16i32 immAllZerosV)))))],
157 // This multiclass generates the unconditional/non-masking, the masking and
158 // the zero-masking variant of the instruction. In the masking case, the
159 // perserved vector elements come from a new dummy input operand tied to $dst.
160 multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
161 dag Outs, dag Ins, string OpcodeStr,
162 string AttSrcAsm, string IntelSrcAsm,
163 dag RHS, InstrItinClass itin = NoItinerary,
164 bit IsCommutable = 0> :
165 AVX512_masking_common<O, F, _, Outs, Ins,
166 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
167 !con((ins _.KRCWM:$mask), Ins),
168 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
169 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
170 "$src0 = $dst", itin, IsCommutable>;
172 // Similar to AVX512_masking but in this case one of the source operands
173 // ($src1) is already tied to $dst so we just use that for the preserved
174 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
176 multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
177 dag Outs, dag NonTiedIns, string OpcodeStr,
178 string AttSrcAsm, string IntelSrcAsm,
180 AVX512_masking_common<O, F, _, Outs,
181 !con((ins _.RC:$src1), NonTiedIns),
182 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
183 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
184 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
185 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
187 // Bitcasts between 512-bit vector types. Return the original type since
188 // no instruction is needed for the conversion
189 let Predicates = [HasAVX512] in {
190 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
191 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
192 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
193 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
194 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
195 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
196 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
197 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
198 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
199 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
200 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
201 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
202 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
203 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
204 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
205 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
206 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
207 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
208 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
209 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
210 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
211 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
212 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
213 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
214 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
215 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
216 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
217 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
218 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
219 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
220 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
222 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
223 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
224 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
225 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
226 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
227 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
228 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
229 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
230 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
231 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
232 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
233 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
234 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
235 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
236 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
237 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
238 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
239 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
240 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
241 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
242 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
243 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
244 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
245 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
246 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
247 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
248 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
249 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
250 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
251 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
253 // Bitcasts between 256-bit vector types. Return the original type since
254 // no instruction is needed for the conversion
255 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
256 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
257 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
258 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
259 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
260 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
261 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
262 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
263 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
264 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
265 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
266 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
267 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
268 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
269 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
270 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
271 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
272 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
273 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
274 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
275 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
276 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
277 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
278 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
279 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
280 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
281 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
282 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
283 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
284 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
288 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
291 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
292 isPseudo = 1, Predicates = [HasAVX512] in {
293 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
294 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
297 let Predicates = [HasAVX512] in {
298 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
299 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
300 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
303 //===----------------------------------------------------------------------===//
304 // AVX-512 - VECTOR INSERT
307 multiclass vinsert_for_size<int Opcode,
308 X86VectorVTInfo From, X86VectorVTInfo To,
309 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
310 PatFrag vinsert_insert,
311 SDNodeXForm INSERT_get_vinsert_imm> {
312 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
313 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
314 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
315 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
316 "$dst, $src1, $src2, $src3}",
317 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
318 (From.VT From.RC:$src2),
323 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
324 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
325 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
326 "$dst, $src1, $src2, $src3}",
327 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
330 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
332 def : Pat<(vinsert_insert:$ins
333 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
334 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
335 VR512:$src1, From.RC:$src2,
336 (INSERT_get_vinsert_imm VR512:$ins)))>;
339 multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
340 ValueType EltVT64, int Opcode64> {
341 defm NAME # "32x4" : vinsert_for_size<Opcode32,
342 X86VectorVTInfo< 4, EltVT32, VR128X>,
343 X86VectorVTInfo<16, EltVT32, VR512>,
344 X86VectorVTInfo< 2, EltVT64, VR128X>,
345 X86VectorVTInfo< 8, EltVT64, VR512>,
347 INSERT_get_vinsert128_imm>;
348 defm NAME # "64x4" : vinsert_for_size<Opcode64,
349 X86VectorVTInfo< 4, EltVT64, VR256X>,
350 X86VectorVTInfo< 8, EltVT64, VR512>,
351 X86VectorVTInfo< 8, EltVT32, VR256>,
352 X86VectorVTInfo<16, EltVT32, VR512>,
354 INSERT_get_vinsert256_imm>, VEX_W;
357 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
358 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
360 // vinsertps - insert f32 to XMM
361 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
362 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
363 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
364 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
366 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
367 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
368 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
369 [(set VR128X:$dst, (X86insertps VR128X:$src1,
370 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
371 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
373 //===----------------------------------------------------------------------===//
374 // AVX-512 VECTOR EXTRACT
377 multiclass vextract_for_size<int Opcode,
378 X86VectorVTInfo From, X86VectorVTInfo To,
379 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
380 PatFrag vextract_extract,
381 SDNodeXForm EXTRACT_get_vextract_imm> {
382 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
383 def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
384 (ins VR512:$src1, i8imm:$idx),
385 "vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
386 "$dst, $src1, $idx}",
387 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
391 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
392 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
393 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
394 "$dst, $src1, $src2}",
395 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
398 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
400 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
401 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
403 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
405 // A 128/256-bit subvector extract from the first 512-bit vector position is
406 // a subregister copy that needs no instruction.
407 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
409 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
411 // And for the alternative types.
412 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
414 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
417 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
418 ValueType EltVT64, int Opcode64> {
419 defm NAME # "32x4" : vextract_for_size<Opcode32,
420 X86VectorVTInfo<16, EltVT32, VR512>,
421 X86VectorVTInfo< 4, EltVT32, VR128X>,
422 X86VectorVTInfo< 8, EltVT64, VR512>,
423 X86VectorVTInfo< 2, EltVT64, VR128X>,
425 EXTRACT_get_vextract128_imm>;
426 defm NAME # "64x4" : vextract_for_size<Opcode64,
427 X86VectorVTInfo< 8, EltVT64, VR512>,
428 X86VectorVTInfo< 4, EltVT64, VR256X>,
429 X86VectorVTInfo<16, EltVT32, VR512>,
430 X86VectorVTInfo< 8, EltVT32, VR256>,
432 EXTRACT_get_vextract256_imm>, VEX_W;
435 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
436 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
438 // A 128-bit subvector insert to the first 512-bit vector position
439 // is a subregister copy that needs no instruction.
440 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
441 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
442 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
444 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
445 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
446 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
448 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
449 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
450 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
452 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
453 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
454 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
457 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
458 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
459 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
460 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
461 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
462 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
463 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
464 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
466 // vextractps - extract 32 bits from XMM
467 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
468 (ins VR128X:$src1, i32i8imm:$src2),
469 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
470 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
473 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
474 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
475 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
476 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
477 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
479 //===---------------------------------------------------------------------===//
482 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
483 RegisterClass DestRC,
484 RegisterClass SrcRC, X86MemOperand x86memop> {
485 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
486 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
488 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
489 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
491 let ExeDomain = SSEPackedSingle in {
492 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
494 EVEX_V512, EVEX_CD8<32, CD8VT1>;
497 let ExeDomain = SSEPackedDouble in {
498 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
500 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
503 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
504 (VBROADCASTSSZrm addr:$src)>;
505 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
506 (VBROADCASTSDZrm addr:$src)>;
508 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
509 (VBROADCASTSSZrm addr:$src)>;
510 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
511 (VBROADCASTSDZrm addr:$src)>;
513 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
514 RegisterClass SrcRC, RegisterClass KRC> {
515 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
517 []>, EVEX, EVEX_V512;
518 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
519 (ins KRC:$mask, SrcRC:$src),
520 !strconcat(OpcodeStr,
521 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
522 []>, EVEX, EVEX_V512, EVEX_KZ;
525 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
526 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
529 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
530 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
532 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
533 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
535 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
536 (VPBROADCASTDrZrr GR32:$src)>;
537 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
538 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
539 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
540 (VPBROADCASTQrZrr GR64:$src)>;
541 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
542 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
544 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
545 (VPBROADCASTDrZrr GR32:$src)>;
546 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
547 (VPBROADCASTQrZrr GR64:$src)>;
549 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
550 (v16i32 immAllZerosV), (i16 GR16:$mask))),
551 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
552 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
553 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
554 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
556 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
557 X86MemOperand x86memop, PatFrag ld_frag,
558 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
560 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
561 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
563 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
564 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
566 !strconcat(OpcodeStr,
567 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
569 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
572 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
573 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
575 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
576 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
578 !strconcat(OpcodeStr,
579 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
580 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
581 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
585 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
586 loadi32, VR512, v16i32, v4i32, VK16WM>,
587 EVEX_V512, EVEX_CD8<32, CD8VT1>;
588 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
589 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
590 EVEX_CD8<64, CD8VT1>;
592 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
593 X86MemOperand x86memop, PatFrag ld_frag,
596 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
597 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
599 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
601 !strconcat(OpcodeStr,
602 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
607 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
608 i128mem, loadv2i64, VK16WM>,
609 EVEX_V512, EVEX_CD8<32, CD8VT4>;
610 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
611 i256mem, loadv4i64, VK16WM>, VEX_W,
612 EVEX_V512, EVEX_CD8<64, CD8VT4>;
614 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
615 (VPBROADCASTDZrr VR128X:$src)>;
616 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
617 (VPBROADCASTQZrr VR128X:$src)>;
619 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
620 (VBROADCASTSSZrr VR128X:$src)>;
621 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
622 (VBROADCASTSDZrr VR128X:$src)>;
624 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
625 (VBROADCASTSSZrr VR128X:$src)>;
626 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
627 (VBROADCASTSDZrr VR128X:$src)>;
629 // Provide fallback in case the load node that is used in the patterns above
630 // is used by additional users, which prevents the pattern selection.
631 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
632 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
633 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
634 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
637 let Predicates = [HasAVX512] in {
638 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
640 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
641 addr:$src)), sub_ymm)>;
643 //===----------------------------------------------------------------------===//
644 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
647 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
648 RegisterClass DstRC, RegisterClass KRC,
649 ValueType OpVT, ValueType SrcVT> {
650 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
651 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
655 let Predicates = [HasCDI] in {
656 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
657 VK16, v16i32, v16i1>, EVEX_V512;
658 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
659 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
662 //===----------------------------------------------------------------------===//
665 // -- immediate form --
666 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
667 SDNode OpNode, PatFrag mem_frag,
668 X86MemOperand x86memop, ValueType OpVT> {
669 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
670 (ins RC:$src1, i8imm:$src2),
671 !strconcat(OpcodeStr,
672 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
674 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
676 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
677 (ins x86memop:$src1, i8imm:$src2),
678 !strconcat(OpcodeStr,
679 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
681 (OpVT (OpNode (mem_frag addr:$src1),
682 (i8 imm:$src2))))]>, EVEX;
685 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
686 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
687 let ExeDomain = SSEPackedDouble in
688 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
689 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
691 // -- VPERM - register form --
692 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
693 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
695 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
696 (ins RC:$src1, RC:$src2),
697 !strconcat(OpcodeStr,
698 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
700 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
702 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
703 (ins RC:$src1, x86memop:$src2),
704 !strconcat(OpcodeStr,
705 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
707 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
711 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
712 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
713 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
714 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
715 let ExeDomain = SSEPackedSingle in
716 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
717 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
718 let ExeDomain = SSEPackedDouble in
719 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
720 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
722 // -- VPERM2I - 3 source operands form --
723 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
724 PatFrag mem_frag, X86MemOperand x86memop,
725 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
726 let Constraints = "$src1 = $dst" in {
727 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
728 (ins RC:$src1, RC:$src2, RC:$src3),
729 !strconcat(OpcodeStr,
730 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
732 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
735 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
736 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
737 !strconcat(OpcodeStr,
738 " \t{$src3, $src2, $dst {${mask}}|"
739 "$dst {${mask}}, $src2, $src3}"),
740 [(set RC:$dst, (OpVT (vselect KRC:$mask,
741 (OpNode RC:$src1, RC:$src2,
746 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
747 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
748 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
749 !strconcat(OpcodeStr,
750 " \t{$src3, $src2, $dst {${mask}} {z} |",
751 "$dst {${mask}} {z}, $src2, $src3}"),
752 [(set RC:$dst, (OpVT (vselect KRC:$mask,
753 (OpNode RC:$src1, RC:$src2,
756 (v16i32 immAllZerosV))))))]>,
759 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
760 (ins RC:$src1, RC:$src2, x86memop:$src3),
761 !strconcat(OpcodeStr,
762 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
764 (OpVT (OpNode RC:$src1, RC:$src2,
765 (mem_frag addr:$src3))))]>, EVEX_4V;
767 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
768 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
769 !strconcat(OpcodeStr,
770 " \t{$src3, $src2, $dst {${mask}}|"
771 "$dst {${mask}}, $src2, $src3}"),
773 (OpVT (vselect KRC:$mask,
774 (OpNode RC:$src1, RC:$src2,
775 (mem_frag addr:$src3)),
779 let AddedComplexity = 10 in // Prefer over the rrkz variant
780 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
781 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
782 !strconcat(OpcodeStr,
783 " \t{$src3, $src2, $dst {${mask}} {z}|"
784 "$dst {${mask}} {z}, $src2, $src3}"),
786 (OpVT (vselect KRC:$mask,
787 (OpNode RC:$src1, RC:$src2,
788 (mem_frag addr:$src3)),
790 (v16i32 immAllZerosV))))))]>,
794 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
795 i512mem, X86VPermiv3, v16i32, VK16WM>,
796 EVEX_V512, EVEX_CD8<32, CD8VF>;
797 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
798 i512mem, X86VPermiv3, v8i64, VK8WM>,
799 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
800 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
801 i512mem, X86VPermiv3, v16f32, VK16WM>,
802 EVEX_V512, EVEX_CD8<32, CD8VF>;
803 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
804 i512mem, X86VPermiv3, v8f64, VK8WM>,
805 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
807 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
808 PatFrag mem_frag, X86MemOperand x86memop,
809 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
810 ValueType MaskVT, RegisterClass MRC> :
811 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
813 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
814 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
815 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
817 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
818 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
819 (!cast<Instruction>(NAME#rrk) VR512:$src1,
820 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
823 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
824 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
825 EVEX_V512, EVEX_CD8<32, CD8VF>;
826 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
827 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
828 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
829 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
830 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
831 EVEX_V512, EVEX_CD8<32, CD8VF>;
832 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
833 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
834 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
836 //===----------------------------------------------------------------------===//
837 // AVX-512 - BLEND using mask
839 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
840 RegisterClass KRC, RegisterClass RC,
841 X86MemOperand x86memop, PatFrag mem_frag,
842 SDNode OpNode, ValueType vt> {
843 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
844 (ins KRC:$mask, RC:$src1, RC:$src2),
845 !strconcat(OpcodeStr,
846 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
847 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
848 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
850 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
851 (ins KRC:$mask, RC:$src1, x86memop:$src2),
852 !strconcat(OpcodeStr,
853 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
854 []>, EVEX_4V, EVEX_K;
857 let ExeDomain = SSEPackedSingle in
858 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
859 VK16WM, VR512, f512mem,
860 memopv16f32, vselect, v16f32>,
861 EVEX_CD8<32, CD8VF>, EVEX_V512;
862 let ExeDomain = SSEPackedDouble in
863 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
864 VK8WM, VR512, f512mem,
865 memopv8f64, vselect, v8f64>,
866 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
868 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
869 (v16f32 VR512:$src2), (i16 GR16:$mask))),
870 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
871 VR512:$src1, VR512:$src2)>;
873 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
874 (v8f64 VR512:$src2), (i8 GR8:$mask))),
875 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
876 VR512:$src1, VR512:$src2)>;
878 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
879 VK16WM, VR512, f512mem,
880 memopv16i32, vselect, v16i32>,
881 EVEX_CD8<32, CD8VF>, EVEX_V512;
883 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
884 VK8WM, VR512, f512mem,
885 memopv8i64, vselect, v8i64>,
886 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
888 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
889 (v16i32 VR512:$src2), (i16 GR16:$mask))),
890 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
891 VR512:$src1, VR512:$src2)>;
893 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
894 (v8i64 VR512:$src2), (i8 GR8:$mask))),
895 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
896 VR512:$src1, VR512:$src2)>;
898 let Predicates = [HasAVX512] in {
899 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
900 (v8f32 VR256X:$src2))),
902 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
903 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
904 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
906 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
907 (v8i32 VR256X:$src2))),
909 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
910 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
911 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
913 //===----------------------------------------------------------------------===//
914 // Compare Instructions
915 //===----------------------------------------------------------------------===//
917 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
918 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
919 Operand CC, SDNode OpNode, ValueType VT,
920 PatFrag ld_frag, string asm, string asm_alt> {
921 def rr : AVX512Ii8<0xC2, MRMSrcReg,
922 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
923 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
924 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
925 def rm : AVX512Ii8<0xC2, MRMSrcMem,
926 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
927 [(set VK1:$dst, (OpNode (VT RC:$src1),
928 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
929 let isAsmParserOnly = 1, hasSideEffects = 0 in {
930 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
931 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
932 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
933 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
934 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
935 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
939 let Predicates = [HasAVX512] in {
940 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
941 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
942 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
944 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
945 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
946 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
950 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
952 def rr : AVX512BI<opc, MRMSrcReg,
953 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
954 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
955 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
956 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
958 def rm : AVX512BI<opc, MRMSrcMem,
959 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
960 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
961 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
962 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
963 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
964 def rrk : AVX512BI<opc, MRMSrcReg,
965 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
967 "$dst {${mask}}, $src1, $src2}"),
968 [(set _.KRC:$dst, (and _.KRCWM:$mask,
969 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
970 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
972 def rmk : AVX512BI<opc, MRMSrcMem,
973 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
974 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
975 "$dst {${mask}}, $src1, $src2}"),
976 [(set _.KRC:$dst, (and _.KRCWM:$mask,
977 (OpNode (_.VT _.RC:$src1),
979 (_.LdFrag addr:$src2))))))],
980 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
983 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
985 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
987 def rmb : AVX512BI<opc, MRMSrcMem,
988 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
989 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
990 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
991 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
992 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
993 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
994 def rmbk : AVX512BI<opc, MRMSrcMem,
995 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
996 _.ScalarMemOp:$src2),
997 !strconcat(OpcodeStr,
998 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
999 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1000 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1001 (OpNode (_.VT _.RC:$src1),
1003 (_.ScalarLdFrag addr:$src2)))))],
1004 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1008 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1009 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1010 let Predicates = [prd] in
1011 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1014 let Predicates = [prd, HasVLX] in {
1015 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1017 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1022 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1023 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1025 let Predicates = [prd] in
1026 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1029 let Predicates = [prd, HasVLX] in {
1030 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1032 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1037 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1038 avx512vl_i8_info, HasBWI>,
1041 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1042 avx512vl_i16_info, HasBWI>,
1043 EVEX_CD8<16, CD8VF>;
1045 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1046 avx512vl_i32_info, HasAVX512>,
1047 EVEX_CD8<32, CD8VF>;
1049 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1050 avx512vl_i64_info, HasAVX512>,
1051 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1053 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1054 avx512vl_i8_info, HasBWI>,
1057 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1058 avx512vl_i16_info, HasBWI>,
1059 EVEX_CD8<16, CD8VF>;
1061 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1062 avx512vl_i32_info, HasAVX512>,
1063 EVEX_CD8<32, CD8VF>;
1065 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1066 avx512vl_i64_info, HasAVX512>,
1067 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1069 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1070 (COPY_TO_REGCLASS (VPCMPGTDZrr
1071 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1072 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1074 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1075 (COPY_TO_REGCLASS (VPCMPEQDZrr
1076 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1077 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1079 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1080 X86VectorVTInfo _> {
1081 def rri : AVX512AIi8<opc, MRMSrcReg,
1082 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1083 !strconcat("vpcmp${cc}", Suffix,
1084 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1085 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1087 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1089 def rmi : AVX512AIi8<opc, MRMSrcMem,
1090 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1091 !strconcat("vpcmp${cc}", Suffix,
1092 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1093 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1094 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1096 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1097 def rrik : AVX512AIi8<opc, MRMSrcReg,
1098 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1100 !strconcat("vpcmp${cc}", Suffix,
1101 "\t{$src2, $src1, $dst {${mask}}|",
1102 "$dst {${mask}}, $src1, $src2}"),
1103 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1104 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1106 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1108 def rmik : AVX512AIi8<opc, MRMSrcMem,
1109 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1111 !strconcat("vpcmp${cc}", Suffix,
1112 "\t{$src2, $src1, $dst {${mask}}|",
1113 "$dst {${mask}}, $src1, $src2}"),
1114 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1115 (OpNode (_.VT _.RC:$src1),
1116 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1118 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1120 // Accept explicit immediate argument form instead of comparison code.
1121 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1122 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1123 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1124 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1125 "$dst, $src1, $src2, $cc}"),
1126 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1127 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1128 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1129 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1130 "$dst, $src1, $src2, $cc}"),
1131 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1132 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1133 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1135 !strconcat("vpcmp", Suffix,
1136 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1137 "$dst {${mask}}, $src1, $src2, $cc}"),
1138 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1139 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1140 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1142 !strconcat("vpcmp", Suffix,
1143 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1144 "$dst {${mask}}, $src1, $src2, $cc}"),
1145 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1149 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1150 X86VectorVTInfo _> :
1151 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1152 let mayLoad = 1 in {
1153 def rmib : AVX512AIi8<opc, MRMSrcMem,
1154 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1156 !strconcat("vpcmp${cc}", Suffix,
1157 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1158 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1159 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1160 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1162 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1163 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1164 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1165 _.ScalarMemOp:$src2, AVXCC:$cc),
1166 !strconcat("vpcmp${cc}", Suffix,
1167 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1168 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1169 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1170 (OpNode (_.VT _.RC:$src1),
1171 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1173 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1176 // Accept explicit immediate argument form instead of comparison code.
1177 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1178 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1179 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1181 !strconcat("vpcmp", Suffix,
1182 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1183 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1184 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1185 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1186 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1187 _.ScalarMemOp:$src2, i8imm:$cc),
1188 !strconcat("vpcmp", Suffix,
1189 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1190 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1191 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1195 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1196 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1197 let Predicates = [prd] in
1198 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1200 let Predicates = [prd, HasVLX] in {
1201 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1202 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1206 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1207 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1208 let Predicates = [prd] in
1209 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1212 let Predicates = [prd, HasVLX] in {
1213 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1215 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1220 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1221 HasBWI>, EVEX_CD8<8, CD8VF>;
1222 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1223 HasBWI>, EVEX_CD8<8, CD8VF>;
1225 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1226 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1227 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1228 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1230 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1231 HasAVX512>, EVEX_CD8<32, CD8VF>;
1232 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1233 HasAVX512>, EVEX_CD8<32, CD8VF>;
1235 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1236 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1237 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1238 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1240 // avx512_cmp_packed - compare packed instructions
1241 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1242 X86MemOperand x86memop, ValueType vt,
1243 string suffix, Domain d> {
1244 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1245 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1246 !strconcat("vcmp${cc}", suffix,
1247 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1248 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1249 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1250 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1251 !strconcat("vcmp${cc}", suffix,
1252 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1254 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1255 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1256 !strconcat("vcmp${cc}", suffix,
1257 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1259 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1261 // Accept explicit immediate argument form instead of comparison code.
1262 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1263 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1264 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1265 !strconcat("vcmp", suffix,
1266 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1267 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1268 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1269 !strconcat("vcmp", suffix,
1270 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1274 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1275 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1276 EVEX_CD8<32, CD8VF>;
1277 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1278 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1279 EVEX_CD8<64, CD8VF>;
1281 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1282 (COPY_TO_REGCLASS (VCMPPSZrri
1283 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1284 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1286 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1287 (COPY_TO_REGCLASS (VPCMPDZrri
1288 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1289 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1291 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1292 (COPY_TO_REGCLASS (VPCMPUDZrri
1293 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1294 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1297 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1298 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1300 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1301 (I8Imm imm:$cc)), GR16)>;
1303 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1304 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1306 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1307 (I8Imm imm:$cc)), GR8)>;
1309 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1310 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1312 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1313 (I8Imm imm:$cc)), GR16)>;
1315 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1316 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1318 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1319 (I8Imm imm:$cc)), GR8)>;
1321 // Mask register copy, including
1322 // - copy between mask registers
1323 // - load/store mask registers
1324 // - copy from GPR to mask register and vice versa
1326 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1327 string OpcodeStr, RegisterClass KRC,
1328 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1329 let hasSideEffects = 0 in {
1330 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1331 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1333 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1334 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1335 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1337 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1338 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1342 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1344 RegisterClass KRC, RegisterClass GRC> {
1345 let hasSideEffects = 0 in {
1346 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1347 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1348 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1349 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1353 let Predicates = [HasDQI] in
1354 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1356 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1359 let Predicates = [HasAVX512] in
1360 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1362 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1365 let Predicates = [HasBWI] in {
1366 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1367 i32mem>, VEX, PD, VEX_W;
1368 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1372 let Predicates = [HasBWI] in {
1373 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1374 i64mem>, VEX, PS, VEX_W;
1375 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1379 // GR from/to mask register
1380 let Predicates = [HasDQI] in {
1381 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1382 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1383 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1384 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1386 let Predicates = [HasAVX512] in {
1387 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1388 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1389 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1390 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1392 let Predicates = [HasBWI] in {
1393 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1394 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1396 let Predicates = [HasBWI] in {
1397 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1398 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1402 let Predicates = [HasDQI] in {
1403 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1404 (KMOVBmk addr:$dst, VK8:$src)>;
1406 let Predicates = [HasAVX512] in {
1407 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1408 (KMOVWmk addr:$dst, VK16:$src)>;
1409 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1410 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1411 def : Pat<(i1 (load addr:$src)),
1412 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1413 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1414 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1416 let Predicates = [HasBWI] in {
1417 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1418 (KMOVDmk addr:$dst, VK32:$src)>;
1420 let Predicates = [HasBWI] in {
1421 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1422 (KMOVQmk addr:$dst, VK64:$src)>;
1425 let Predicates = [HasAVX512] in {
1426 def : Pat<(i1 (trunc (i64 GR64:$src))),
1427 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1430 def : Pat<(i1 (trunc (i32 GR32:$src))),
1431 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1433 def : Pat<(i1 (trunc (i8 GR8:$src))),
1435 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1437 def : Pat<(i1 (trunc (i16 GR16:$src))),
1439 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1442 def : Pat<(i32 (zext VK1:$src)),
1443 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1444 def : Pat<(i8 (zext VK1:$src)),
1447 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1448 def : Pat<(i64 (zext VK1:$src)),
1449 (AND64ri8 (SUBREG_TO_REG (i64 0),
1450 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1451 def : Pat<(i16 (zext VK1:$src)),
1453 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1455 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1456 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1457 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1458 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1460 let Predicates = [HasBWI] in {
1461 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1462 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1463 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1464 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1468 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1469 let Predicates = [HasAVX512] in {
1470 // GR from/to 8-bit mask without native support
1471 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1473 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1475 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1477 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1480 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1481 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1482 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1483 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1485 let Predicates = [HasBWI] in {
1486 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1487 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1488 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1489 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1492 // Mask unary operation
1494 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1495 RegisterClass KRC, SDPatternOperator OpNode,
1497 let Predicates = [prd] in
1498 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1499 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1500 [(set KRC:$dst, (OpNode KRC:$src))]>;
1503 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1504 SDPatternOperator OpNode> {
1505 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1507 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1508 HasAVX512>, VEX, PS;
1509 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1510 HasBWI>, VEX, PD, VEX_W;
1511 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1512 HasBWI>, VEX, PS, VEX_W;
1515 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1517 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1518 let Predicates = [HasAVX512] in
1519 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1521 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1522 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1524 defm : avx512_mask_unop_int<"knot", "KNOT">;
1526 let Predicates = [HasDQI] in
1527 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1528 let Predicates = [HasAVX512] in
1529 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1530 let Predicates = [HasBWI] in
1531 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1532 let Predicates = [HasBWI] in
1533 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1535 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1536 let Predicates = [HasAVX512] in {
1537 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1538 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1540 def : Pat<(not VK8:$src),
1542 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1545 // Mask binary operation
1546 // - KAND, KANDN, KOR, KXNOR, KXOR
1547 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1548 RegisterClass KRC, SDPatternOperator OpNode,
1550 let Predicates = [prd] in
1551 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1552 !strconcat(OpcodeStr,
1553 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1554 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1557 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1558 SDPatternOperator OpNode> {
1559 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1560 HasDQI>, VEX_4V, VEX_L, PD;
1561 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1562 HasAVX512>, VEX_4V, VEX_L, PS;
1563 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1564 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1565 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1566 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1569 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1570 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1572 let isCommutable = 1 in {
1573 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1574 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1575 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1576 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1578 let isCommutable = 0 in
1579 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1581 def : Pat<(xor VK1:$src1, VK1:$src2),
1582 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1583 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1585 def : Pat<(or VK1:$src1, VK1:$src2),
1586 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1587 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1589 def : Pat<(and VK1:$src1, VK1:$src2),
1590 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1591 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1593 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1594 let Predicates = [HasAVX512] in
1595 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1596 (i16 GR16:$src1), (i16 GR16:$src2)),
1597 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1598 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1599 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1602 defm : avx512_mask_binop_int<"kand", "KAND">;
1603 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1604 defm : avx512_mask_binop_int<"kor", "KOR">;
1605 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1606 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1608 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1609 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1610 let Predicates = [HasAVX512] in
1611 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1613 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1614 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1617 defm : avx512_binop_pat<and, KANDWrr>;
1618 defm : avx512_binop_pat<andn, KANDNWrr>;
1619 defm : avx512_binop_pat<or, KORWrr>;
1620 defm : avx512_binop_pat<xnor, KXNORWrr>;
1621 defm : avx512_binop_pat<xor, KXORWrr>;
1624 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1625 RegisterClass KRC> {
1626 let Predicates = [HasAVX512] in
1627 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1628 !strconcat(OpcodeStr,
1629 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1632 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1633 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1637 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1638 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1639 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1640 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1643 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1644 let Predicates = [HasAVX512] in
1645 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1646 (i16 GR16:$src1), (i16 GR16:$src2)),
1647 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1648 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1649 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1651 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1654 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1656 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1657 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1658 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1659 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1662 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1663 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1667 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1669 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1670 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1671 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1674 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1676 let Predicates = [HasAVX512] in
1677 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1678 !strconcat(OpcodeStr,
1679 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1680 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1683 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1685 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1689 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1690 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1692 // Mask setting all 0s or 1s
1693 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1694 let Predicates = [HasAVX512] in
1695 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1696 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1697 [(set KRC:$dst, (VT Val))]>;
1700 multiclass avx512_mask_setop_w<PatFrag Val> {
1701 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1702 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1705 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1706 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1708 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1709 let Predicates = [HasAVX512] in {
1710 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1711 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1712 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1713 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1714 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1716 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1717 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1719 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1720 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1722 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1723 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1725 let Predicates = [HasVLX] in {
1726 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1727 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1728 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1729 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1730 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1731 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1732 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1733 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1736 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1737 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1739 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1740 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1741 //===----------------------------------------------------------------------===//
1742 // AVX-512 - Aligned and unaligned load and store
1745 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1746 RegisterClass KRC, RegisterClass RC,
1747 ValueType vt, ValueType zvt, X86MemOperand memop,
1748 Domain d, bit IsReMaterializable = 1> {
1749 let hasSideEffects = 0 in {
1750 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1753 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1754 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1755 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1757 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1758 SchedRW = [WriteLoad] in
1759 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1760 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1761 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1764 let AddedComplexity = 20 in {
1765 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1766 let hasSideEffects = 0 in
1767 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1768 (ins RC:$src0, KRC:$mask, RC:$src1),
1769 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1770 "${dst} {${mask}}, $src1}"),
1771 [(set RC:$dst, (vt (vselect KRC:$mask,
1775 let mayLoad = 1, SchedRW = [WriteLoad] in
1776 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1777 (ins RC:$src0, KRC:$mask, memop:$src1),
1778 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1779 "${dst} {${mask}}, $src1}"),
1782 (vt (bitconvert (ld_frag addr:$src1))),
1786 let mayLoad = 1, SchedRW = [WriteLoad] in
1787 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1788 (ins KRC:$mask, memop:$src),
1789 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1790 "${dst} {${mask}} {z}, $src}"),
1793 (vt (bitconvert (ld_frag addr:$src))),
1794 (vt (bitconvert (zvt immAllZerosV))))))],
1799 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1800 string elty, string elsz, string vsz512,
1801 string vsz256, string vsz128, Domain d,
1802 Predicate prd, bit IsReMaterializable = 1> {
1803 let Predicates = [prd] in
1804 defm Z : avx512_load<opc, OpcodeStr,
1805 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1806 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1807 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1808 !cast<X86MemOperand>(elty##"512mem"), d,
1809 IsReMaterializable>, EVEX_V512;
1811 let Predicates = [prd, HasVLX] in {
1812 defm Z256 : avx512_load<opc, OpcodeStr,
1813 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1814 "v"##vsz256##elty##elsz, "v4i64")),
1815 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1816 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1817 !cast<X86MemOperand>(elty##"256mem"), d,
1818 IsReMaterializable>, EVEX_V256;
1820 defm Z128 : avx512_load<opc, OpcodeStr,
1821 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1822 "v"##vsz128##elty##elsz, "v2i64")),
1823 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1824 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1825 !cast<X86MemOperand>(elty##"128mem"), d,
1826 IsReMaterializable>, EVEX_V128;
1831 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1832 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1833 X86MemOperand memop, Domain d> {
1834 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1835 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1836 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1838 let Constraints = "$src1 = $dst" in
1839 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1840 (ins RC:$src1, KRC:$mask, RC:$src2),
1841 !strconcat(OpcodeStr,
1842 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1844 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1845 (ins KRC:$mask, RC:$src),
1846 !strconcat(OpcodeStr,
1847 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1848 [], d>, EVEX, EVEX_KZ;
1850 let mayStore = 1 in {
1851 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1852 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1853 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1854 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1855 (ins memop:$dst, KRC:$mask, RC:$src),
1856 !strconcat(OpcodeStr,
1857 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1858 [], d>, EVEX, EVEX_K;
1863 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1864 string st_suff_512, string st_suff_256,
1865 string st_suff_128, string elty, string elsz,
1866 string vsz512, string vsz256, string vsz128,
1867 Domain d, Predicate prd> {
1868 let Predicates = [prd] in
1869 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1870 !cast<ValueType>("v"##vsz512##elty##elsz),
1871 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1872 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1874 let Predicates = [prd, HasVLX] in {
1875 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1876 !cast<ValueType>("v"##vsz256##elty##elsz),
1877 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1878 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1880 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1881 !cast<ValueType>("v"##vsz128##elty##elsz),
1882 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1883 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1887 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1888 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1889 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1890 "512", "256", "", "f", "32", "16", "8", "4",
1891 SSEPackedSingle, HasAVX512>,
1892 PS, EVEX_CD8<32, CD8VF>;
1894 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1895 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1896 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1897 "512", "256", "", "f", "64", "8", "4", "2",
1898 SSEPackedDouble, HasAVX512>,
1899 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1901 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1902 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1903 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1904 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1905 PS, EVEX_CD8<32, CD8VF>;
1907 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1908 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1909 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1910 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1911 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1913 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1914 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1915 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1917 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1918 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1919 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1921 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1923 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1925 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1927 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1930 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1931 "16", "8", "4", SSEPackedInt, HasAVX512>,
1932 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1933 "512", "256", "", "i", "32", "16", "8", "4",
1934 SSEPackedInt, HasAVX512>,
1935 PD, EVEX_CD8<32, CD8VF>;
1937 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1938 "8", "4", "2", SSEPackedInt, HasAVX512>,
1939 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1940 "512", "256", "", "i", "64", "8", "4", "2",
1941 SSEPackedInt, HasAVX512>,
1942 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1944 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1945 "64", "32", "16", SSEPackedInt, HasBWI>,
1946 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1947 "i", "8", "64", "32", "16", SSEPackedInt,
1948 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1950 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1951 "32", "16", "8", SSEPackedInt, HasBWI>,
1952 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1953 "i", "16", "32", "16", "8", SSEPackedInt,
1954 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1956 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1957 "16", "8", "4", SSEPackedInt, HasAVX512>,
1958 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1959 "i", "32", "16", "8", "4", SSEPackedInt,
1960 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1962 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1963 "8", "4", "2", SSEPackedInt, HasAVX512>,
1964 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1965 "i", "64", "8", "4", "2", SSEPackedInt,
1966 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1968 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1969 (v16i32 immAllZerosV), GR16:$mask)),
1970 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1972 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1973 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1974 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1976 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1978 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1980 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1982 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1985 let AddedComplexity = 20 in {
1986 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1987 (bc_v8i64 (v16i32 immAllZerosV)))),
1988 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
1990 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1991 (v8i64 VR512:$src))),
1992 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1995 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1996 (v16i32 immAllZerosV))),
1997 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
1999 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2000 (v16i32 VR512:$src))),
2001 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2004 // Move Int Doubleword to Packed Double Int
2006 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2007 "vmovd\t{$src, $dst|$dst, $src}",
2009 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2011 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2012 "vmovd\t{$src, $dst|$dst, $src}",
2014 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2015 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2016 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2017 "vmovq\t{$src, $dst|$dst, $src}",
2019 (v2i64 (scalar_to_vector GR64:$src)))],
2020 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2021 let isCodeGenOnly = 1 in {
2022 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2023 "vmovq\t{$src, $dst|$dst, $src}",
2024 [(set FR64:$dst, (bitconvert GR64:$src))],
2025 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2026 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2027 "vmovq\t{$src, $dst|$dst, $src}",
2028 [(set GR64:$dst, (bitconvert FR64:$src))],
2029 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2031 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2032 "vmovq\t{$src, $dst|$dst, $src}",
2033 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2034 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2035 EVEX_CD8<64, CD8VT1>;
2037 // Move Int Doubleword to Single Scalar
2039 let isCodeGenOnly = 1 in {
2040 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2041 "vmovd\t{$src, $dst|$dst, $src}",
2042 [(set FR32X:$dst, (bitconvert GR32:$src))],
2043 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2045 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2046 "vmovd\t{$src, $dst|$dst, $src}",
2047 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2048 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2051 // Move doubleword from xmm register to r/m32
2053 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2054 "vmovd\t{$src, $dst|$dst, $src}",
2055 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2056 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2058 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2059 (ins i32mem:$dst, VR128X:$src),
2060 "vmovd\t{$src, $dst|$dst, $src}",
2061 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2062 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2063 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2065 // Move quadword from xmm1 register to r/m64
2067 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2068 "vmovq\t{$src, $dst|$dst, $src}",
2069 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2071 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2072 Requires<[HasAVX512, In64BitMode]>;
2074 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2075 (ins i64mem:$dst, VR128X:$src),
2076 "vmovq\t{$src, $dst|$dst, $src}",
2077 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2078 addr:$dst)], IIC_SSE_MOVDQ>,
2079 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2080 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2082 // Move Scalar Single to Double Int
2084 let isCodeGenOnly = 1 in {
2085 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2087 "vmovd\t{$src, $dst|$dst, $src}",
2088 [(set GR32:$dst, (bitconvert FR32X:$src))],
2089 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2090 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2091 (ins i32mem:$dst, FR32X:$src),
2092 "vmovd\t{$src, $dst|$dst, $src}",
2093 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2094 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2097 // Move Quadword Int to Packed Quadword Int
2099 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2101 "vmovq\t{$src, $dst|$dst, $src}",
2103 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2104 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2106 //===----------------------------------------------------------------------===//
2107 // AVX-512 MOVSS, MOVSD
2108 //===----------------------------------------------------------------------===//
2110 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2111 SDNode OpNode, ValueType vt,
2112 X86MemOperand x86memop, PatFrag mem_pat> {
2113 let hasSideEffects = 0 in {
2114 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2115 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2116 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2117 (scalar_to_vector RC:$src2))))],
2118 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2119 let Constraints = "$src1 = $dst" in
2120 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2121 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2123 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2124 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2125 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2126 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2127 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2129 let mayStore = 1 in {
2130 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2131 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2132 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2134 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2135 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2136 [], IIC_SSE_MOV_S_MR>,
2137 EVEX, VEX_LIG, EVEX_K;
2139 } //hasSideEffects = 0
2142 let ExeDomain = SSEPackedSingle in
2143 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2144 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2146 let ExeDomain = SSEPackedDouble in
2147 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2148 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2150 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2151 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2152 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2154 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2155 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2156 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2158 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2159 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2160 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2162 // For the disassembler
2163 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2164 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2165 (ins VR128X:$src1, FR32X:$src2),
2166 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2168 XS, EVEX_4V, VEX_LIG;
2169 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2170 (ins VR128X:$src1, FR64X:$src2),
2171 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2173 XD, EVEX_4V, VEX_LIG, VEX_W;
2176 let Predicates = [HasAVX512] in {
2177 let AddedComplexity = 15 in {
2178 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2179 // MOVS{S,D} to the lower bits.
2180 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2181 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2182 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2183 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2184 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2185 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2186 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2187 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2189 // Move low f32 and clear high bits.
2190 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2191 (SUBREG_TO_REG (i32 0),
2192 (VMOVSSZrr (v4f32 (V_SET0)),
2193 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2194 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2195 (SUBREG_TO_REG (i32 0),
2196 (VMOVSSZrr (v4i32 (V_SET0)),
2197 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2200 let AddedComplexity = 20 in {
2201 // MOVSSrm zeros the high parts of the register; represent this
2202 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2203 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2204 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2205 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2206 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2207 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2208 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2210 // MOVSDrm zeros the high parts of the register; represent this
2211 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2212 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2213 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2214 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2215 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2216 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2217 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2218 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2219 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2220 def : Pat<(v2f64 (X86vzload addr:$src)),
2221 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2223 // Represent the same patterns above but in the form they appear for
2225 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2226 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2227 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2228 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2229 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2230 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2231 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2232 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2233 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2235 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2236 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2237 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2238 FR32X:$src)), sub_xmm)>;
2239 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2240 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2241 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2242 FR64X:$src)), sub_xmm)>;
2243 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2244 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2245 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2247 // Move low f64 and clear high bits.
2248 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2249 (SUBREG_TO_REG (i32 0),
2250 (VMOVSDZrr (v2f64 (V_SET0)),
2251 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2253 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2254 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2255 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2257 // Extract and store.
2258 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2260 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2261 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2263 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2265 // Shuffle with VMOVSS
2266 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2267 (VMOVSSZrr (v4i32 VR128X:$src1),
2268 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2269 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2270 (VMOVSSZrr (v4f32 VR128X:$src1),
2271 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2274 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2275 (SUBREG_TO_REG (i32 0),
2276 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2277 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2279 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2280 (SUBREG_TO_REG (i32 0),
2281 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2282 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2285 // Shuffle with VMOVSD
2286 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2287 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2288 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2289 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2290 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2291 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2292 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2293 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2296 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2297 (SUBREG_TO_REG (i32 0),
2298 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2299 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2301 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2302 (SUBREG_TO_REG (i32 0),
2303 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2304 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2307 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2308 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2309 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2310 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2311 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2312 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2313 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2314 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2317 let AddedComplexity = 15 in
2318 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2320 "vmovq\t{$src, $dst|$dst, $src}",
2321 [(set VR128X:$dst, (v2i64 (X86vzmovl
2322 (v2i64 VR128X:$src))))],
2323 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2325 let AddedComplexity = 20 in
2326 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2328 "vmovq\t{$src, $dst|$dst, $src}",
2329 [(set VR128X:$dst, (v2i64 (X86vzmovl
2330 (loadv2i64 addr:$src))))],
2331 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2332 EVEX_CD8<8, CD8VT8>;
2334 let Predicates = [HasAVX512] in {
2335 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2336 let AddedComplexity = 20 in {
2337 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2338 (VMOVDI2PDIZrm addr:$src)>;
2339 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2340 (VMOV64toPQIZrr GR64:$src)>;
2341 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2342 (VMOVDI2PDIZrr GR32:$src)>;
2344 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2345 (VMOVDI2PDIZrm addr:$src)>;
2346 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2347 (VMOVDI2PDIZrm addr:$src)>;
2348 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2349 (VMOVZPQILo2PQIZrm addr:$src)>;
2350 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2351 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2352 def : Pat<(v2i64 (X86vzload addr:$src)),
2353 (VMOVZPQILo2PQIZrm addr:$src)>;
2356 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2357 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2358 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2359 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2360 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2361 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2362 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2365 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2366 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2368 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2369 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2371 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2372 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2374 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2375 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2377 //===----------------------------------------------------------------------===//
2378 // AVX-512 - Non-temporals
2379 //===----------------------------------------------------------------------===//
2380 let SchedRW = [WriteLoad] in {
2381 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2382 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2383 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2384 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2385 EVEX_CD8<64, CD8VF>;
2387 let Predicates = [HasAVX512, HasVLX] in {
2388 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2390 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2391 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2392 EVEX_CD8<64, CD8VF>;
2394 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2396 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2397 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2398 EVEX_CD8<64, CD8VF>;
2402 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2403 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2404 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2405 let SchedRW = [WriteStore], mayStore = 1,
2406 AddedComplexity = 400 in
2407 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2408 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2409 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2412 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2413 string elty, string elsz, string vsz512,
2414 string vsz256, string vsz128, Domain d,
2415 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2416 let Predicates = [prd] in
2417 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2418 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2419 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2422 let Predicates = [prd, HasVLX] in {
2423 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2424 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2425 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2428 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2429 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2430 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2435 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2436 "i", "64", "8", "4", "2", SSEPackedInt,
2437 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2439 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2440 "f", "64", "8", "4", "2", SSEPackedDouble,
2441 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2443 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2444 "f", "32", "16", "8", "4", SSEPackedSingle,
2445 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2447 //===----------------------------------------------------------------------===//
2448 // AVX-512 - Integer arithmetic
2450 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2451 X86VectorVTInfo _, OpndItins itins,
2452 bit IsCommutable = 0> {
2453 defm rr : AVX512_masking<opc, MRMSrcReg, _, (outs _.RC:$dst),
2454 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2455 "$src2, $src1", "$src1, $src2",
2456 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2457 itins.rr, IsCommutable>,
2458 AVX512BIBase, EVEX_4V;
2460 let mayLoad = 1 in {
2461 defm rm : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2462 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2463 "$src2, $src1", "$src1, $src2",
2464 (_.VT (OpNode _.RC:$src1,
2465 (bitconvert (_.LdFrag addr:$src2)))),
2467 AVX512BIBase, EVEX_4V;
2468 defm rmb : AVX512_masking<opc, MRMSrcMem, _, (outs _.RC:$dst),
2469 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2470 "${src2}"##_.BroadcastStr##", $src1",
2471 "$src1, ${src2}"##_.BroadcastStr,
2472 (_.VT (OpNode _.RC:$src1,
2474 (_.ScalarLdFrag addr:$src2)))),
2476 AVX512BIBase, EVEX_4V, EVEX_B;
2480 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2481 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2482 PatFrag memop_frag, X86MemOperand x86memop,
2483 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2484 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2485 let isCommutable = IsCommutable in
2487 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2488 (ins RC:$src1, RC:$src2),
2489 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2491 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2492 (ins KRC:$mask, RC:$src1, RC:$src2),
2493 !strconcat(OpcodeStr,
2494 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2495 [], itins.rr>, EVEX_4V, EVEX_K;
2496 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2497 (ins KRC:$mask, RC:$src1, RC:$src2),
2498 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2499 "|$dst {${mask}} {z}, $src1, $src2}"),
2500 [], itins.rr>, EVEX_4V, EVEX_KZ;
2502 let mayLoad = 1 in {
2503 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2504 (ins RC:$src1, x86memop:$src2),
2505 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2507 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2508 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2509 !strconcat(OpcodeStr,
2510 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2511 [], itins.rm>, EVEX_4V, EVEX_K;
2512 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2513 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2514 !strconcat(OpcodeStr,
2515 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2516 [], itins.rm>, EVEX_4V, EVEX_KZ;
2517 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2518 (ins RC:$src1, x86scalar_mop:$src2),
2519 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2520 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2521 [], itins.rm>, EVEX_4V, EVEX_B;
2522 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2523 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2524 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2525 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2527 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2528 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2529 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2530 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2531 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2533 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2537 defm VPADDDZ : avx512_binop_rm<0xFE, "vpadd", add, v16i32_info,
2538 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2540 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsub", sub, v16i32_info,
2541 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2543 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmull", mul, v16i32_info,
2544 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2546 defm VPADDQZ : avx512_binop_rm<0xD4, "vpadd", add, v8i64_info,
2547 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2549 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsub", sub, v8i64_info,
2550 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2552 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2553 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2554 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2555 EVEX_CD8<64, CD8VF>, VEX_W;
2557 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2558 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2559 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2561 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2562 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2564 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2565 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2566 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2567 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2568 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2569 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2571 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v16i32_info,
2572 SSE_INTALU_ITINS_P, 1>,
2573 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2574 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxu", X86umax, v8i64_info,
2575 SSE_INTALU_ITINS_P, 0>,
2576 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2578 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v16i32_info,
2579 SSE_INTALU_ITINS_P, 1>,
2580 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2581 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxs", X86smax, v8i64_info,
2582 SSE_INTALU_ITINS_P, 0>,
2583 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2585 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v16i32_info,
2586 SSE_INTALU_ITINS_P, 1>,
2587 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2588 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminu", X86umin, v8i64_info,
2589 SSE_INTALU_ITINS_P, 0>,
2590 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2592 defm VPMINSDZ : avx512_binop_rm<0x39, "vpmins", X86smin, v16i32_info,
2593 SSE_INTALU_ITINS_P, 1>,
2594 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2595 defm VPMINSQZ : avx512_binop_rm<0x39, "vpmins", X86smin, v8i64_info,
2596 SSE_INTALU_ITINS_P, 0>,
2597 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2599 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2600 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2601 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2602 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2603 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2604 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2605 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2606 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2607 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2608 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2609 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2610 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2611 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2612 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2613 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2614 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2615 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2616 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2617 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2618 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2619 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2620 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2621 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2622 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2623 //===----------------------------------------------------------------------===//
2624 // AVX-512 - Unpack Instructions
2625 //===----------------------------------------------------------------------===//
2627 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2628 PatFrag mem_frag, RegisterClass RC,
2629 X86MemOperand x86memop, string asm,
2631 def rr : AVX512PI<opc, MRMSrcReg,
2632 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2634 (vt (OpNode RC:$src1, RC:$src2)))],
2636 def rm : AVX512PI<opc, MRMSrcMem,
2637 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2639 (vt (OpNode RC:$src1,
2640 (bitconvert (mem_frag addr:$src2)))))],
2644 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2645 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2646 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2647 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2648 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2649 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2650 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2651 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2652 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2653 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2654 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2655 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2657 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2658 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2659 X86MemOperand x86memop> {
2660 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2661 (ins RC:$src1, RC:$src2),
2662 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2663 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2664 IIC_SSE_UNPCK>, EVEX_4V;
2665 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2666 (ins RC:$src1, x86memop:$src2),
2667 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2668 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2669 (bitconvert (memop_frag addr:$src2)))))],
2670 IIC_SSE_UNPCK>, EVEX_4V;
2672 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2673 VR512, memopv16i32, i512mem>, EVEX_V512,
2674 EVEX_CD8<32, CD8VF>;
2675 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2676 VR512, memopv8i64, i512mem>, EVEX_V512,
2677 VEX_W, EVEX_CD8<64, CD8VF>;
2678 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2679 VR512, memopv16i32, i512mem>, EVEX_V512,
2680 EVEX_CD8<32, CD8VF>;
2681 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2682 VR512, memopv8i64, i512mem>, EVEX_V512,
2683 VEX_W, EVEX_CD8<64, CD8VF>;
2684 //===----------------------------------------------------------------------===//
2688 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2689 SDNode OpNode, PatFrag mem_frag,
2690 X86MemOperand x86memop, ValueType OpVT> {
2691 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2692 (ins RC:$src1, i8imm:$src2),
2693 !strconcat(OpcodeStr,
2694 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2696 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2698 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2699 (ins x86memop:$src1, i8imm:$src2),
2700 !strconcat(OpcodeStr,
2701 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2703 (OpVT (OpNode (mem_frag addr:$src1),
2704 (i8 imm:$src2))))]>, EVEX;
2707 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2708 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2710 let ExeDomain = SSEPackedSingle in
2711 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
2712 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2713 EVEX_CD8<32, CD8VF>;
2714 let ExeDomain = SSEPackedDouble in
2715 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
2716 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2717 VEX_W, EVEX_CD8<32, CD8VF>;
2719 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2720 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2721 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
2722 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2724 //===----------------------------------------------------------------------===//
2725 // AVX-512 Logical Instructions
2726 //===----------------------------------------------------------------------===//
2728 defm VPANDDZ : avx512_binop_rm<0xDB, "vpand", and, v16i32_info, SSE_BIT_ITINS_P, 1>,
2729 EVEX_V512, EVEX_CD8<32, CD8VF>;
2730 defm VPANDQZ : avx512_binop_rm<0xDB, "vpand", and, v8i64_info, SSE_BIT_ITINS_P, 1>,
2731 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2732 defm VPORDZ : avx512_binop_rm<0xEB, "vpor", or, v16i32_info, SSE_BIT_ITINS_P, 1>,
2733 EVEX_V512, EVEX_CD8<32, CD8VF>;
2734 defm VPORQZ : avx512_binop_rm<0xEB, "vpor", or, v8i64_info, SSE_BIT_ITINS_P, 1>,
2735 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2736 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxor", xor, v16i32_info, SSE_BIT_ITINS_P, 1>,
2737 EVEX_V512, EVEX_CD8<32, CD8VF>;
2738 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxor", xor, v8i64_info, SSE_BIT_ITINS_P, 1>,
2739 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2740 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v16i32_info,
2741 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2742 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandn", X86andnp, v8i64_info,
2743 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2745 //===----------------------------------------------------------------------===//
2746 // AVX-512 FP arithmetic
2747 //===----------------------------------------------------------------------===//
2749 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2751 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2752 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2753 EVEX_CD8<32, CD8VT1>;
2754 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2755 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2756 EVEX_CD8<64, CD8VT1>;
2759 let isCommutable = 1 in {
2760 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2761 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2762 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2763 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2765 let isCommutable = 0 in {
2766 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2767 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2770 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2772 RegisterClass RC, ValueType vt,
2773 X86MemOperand x86memop, PatFrag mem_frag,
2774 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2776 Domain d, OpndItins itins, bit commutable> {
2777 let isCommutable = commutable in {
2778 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2779 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2780 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2783 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2784 !strconcat(OpcodeStr,
2785 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2786 [], itins.rr, d>, EVEX_4V, EVEX_K;
2788 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2789 !strconcat(OpcodeStr,
2790 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2791 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2794 let mayLoad = 1 in {
2795 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2796 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2797 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2798 itins.rm, d>, EVEX_4V;
2800 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2801 (ins RC:$src1, x86scalar_mop:$src2),
2802 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2803 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2804 [(set RC:$dst, (OpNode RC:$src1,
2805 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2806 itins.rm, d>, EVEX_4V, EVEX_B;
2808 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2809 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2810 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2811 [], itins.rm, d>, EVEX_4V, EVEX_K;
2813 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2814 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2815 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2816 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2818 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2819 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2820 " \t{${src2}", BrdcstStr,
2821 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2822 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2824 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2825 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2826 " \t{${src2}", BrdcstStr,
2827 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2829 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2833 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2834 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2835 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2837 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2838 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2839 SSE_ALU_ITINS_P.d, 1>,
2840 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2842 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2843 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2844 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2845 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2846 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2847 SSE_ALU_ITINS_P.d, 1>,
2848 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2850 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2851 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2852 SSE_ALU_ITINS_P.s, 1>,
2853 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2854 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2855 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2856 SSE_ALU_ITINS_P.s, 1>,
2857 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2859 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2860 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2861 SSE_ALU_ITINS_P.d, 1>,
2862 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2863 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2864 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2865 SSE_ALU_ITINS_P.d, 1>,
2866 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2868 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2869 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2870 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2871 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2872 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2873 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2875 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2876 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2877 SSE_ALU_ITINS_P.d, 0>,
2878 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2879 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2880 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2881 SSE_ALU_ITINS_P.d, 0>,
2882 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2884 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2885 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2886 (i16 -1), FROUND_CURRENT)),
2887 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2889 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2890 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2891 (i8 -1), FROUND_CURRENT)),
2892 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2894 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2895 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2896 (i16 -1), FROUND_CURRENT)),
2897 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2899 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2900 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2901 (i8 -1), FROUND_CURRENT)),
2902 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2903 //===----------------------------------------------------------------------===//
2904 // AVX-512 VPTESTM instructions
2905 //===----------------------------------------------------------------------===//
2907 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2908 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2909 SDNode OpNode, ValueType vt> {
2910 def rr : AVX512PI<opc, MRMSrcReg,
2911 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2912 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2913 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2914 SSEPackedInt>, EVEX_4V;
2915 def rm : AVX512PI<opc, MRMSrcMem,
2916 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2917 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2918 [(set KRC:$dst, (OpNode (vt RC:$src1),
2919 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2922 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2923 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2924 EVEX_CD8<32, CD8VF>;
2925 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2926 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2927 EVEX_CD8<64, CD8VF>;
2929 let Predicates = [HasCDI] in {
2930 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2931 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2932 EVEX_CD8<32, CD8VF>;
2933 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2934 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2935 EVEX_CD8<64, CD8VF>;
2938 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2939 (v16i32 VR512:$src2), (i16 -1))),
2940 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2942 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2943 (v8i64 VR512:$src2), (i8 -1))),
2944 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2945 //===----------------------------------------------------------------------===//
2946 // AVX-512 Shift instructions
2947 //===----------------------------------------------------------------------===//
2948 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2949 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2950 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2951 RegisterClass KRC> {
2952 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2953 (ins RC:$src1, i8imm:$src2),
2954 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2955 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2956 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2957 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2958 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2959 !strconcat(OpcodeStr,
2960 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2961 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2962 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2963 (ins x86memop:$src1, i8imm:$src2),
2964 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2965 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2966 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2967 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2968 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2969 !strconcat(OpcodeStr,
2970 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2971 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2974 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2975 RegisterClass RC, ValueType vt, ValueType SrcVT,
2976 PatFrag bc_frag, RegisterClass KRC> {
2977 // src2 is always 128-bit
2978 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2979 (ins RC:$src1, VR128X:$src2),
2980 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2981 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2982 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2983 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2984 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2985 !strconcat(OpcodeStr,
2986 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2987 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2988 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2989 (ins RC:$src1, i128mem:$src2),
2990 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2991 [(set RC:$dst, (vt (OpNode RC:$src1,
2992 (bc_frag (memopv2i64 addr:$src2)))))],
2993 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2994 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2995 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2996 !strconcat(OpcodeStr,
2997 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2998 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3001 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3002 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3003 EVEX_V512, EVEX_CD8<32, CD8VF>;
3004 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3005 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3006 EVEX_CD8<32, CD8VQ>;
3008 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3009 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3010 EVEX_CD8<64, CD8VF>, VEX_W;
3011 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3012 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3013 EVEX_CD8<64, CD8VQ>, VEX_W;
3015 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3016 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3017 EVEX_CD8<32, CD8VF>;
3018 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3019 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3020 EVEX_CD8<32, CD8VQ>;
3022 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3023 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3024 EVEX_CD8<64, CD8VF>, VEX_W;
3025 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3026 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3027 EVEX_CD8<64, CD8VQ>, VEX_W;
3029 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3030 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3031 EVEX_V512, EVEX_CD8<32, CD8VF>;
3032 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3033 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3034 EVEX_CD8<32, CD8VQ>;
3036 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3037 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3038 EVEX_CD8<64, CD8VF>, VEX_W;
3039 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3040 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3041 EVEX_CD8<64, CD8VQ>, VEX_W;
3043 //===-------------------------------------------------------------------===//
3044 // Variable Bit Shifts
3045 //===-------------------------------------------------------------------===//
3046 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3047 RegisterClass RC, ValueType vt,
3048 X86MemOperand x86memop, PatFrag mem_frag> {
3049 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3050 (ins RC:$src1, RC:$src2),
3051 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3053 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3055 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3056 (ins RC:$src1, x86memop:$src2),
3057 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3059 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3063 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3064 i512mem, memopv16i32>, EVEX_V512,
3065 EVEX_CD8<32, CD8VF>;
3066 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3067 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3068 EVEX_CD8<64, CD8VF>;
3069 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3070 i512mem, memopv16i32>, EVEX_V512,
3071 EVEX_CD8<32, CD8VF>;
3072 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3073 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3074 EVEX_CD8<64, CD8VF>;
3075 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3076 i512mem, memopv16i32>, EVEX_V512,
3077 EVEX_CD8<32, CD8VF>;
3078 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3079 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3080 EVEX_CD8<64, CD8VF>;
3082 //===----------------------------------------------------------------------===//
3083 // AVX-512 - MOVDDUP
3084 //===----------------------------------------------------------------------===//
3086 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3087 X86MemOperand x86memop, PatFrag memop_frag> {
3088 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3089 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3090 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3091 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3092 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3094 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3097 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3098 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3099 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3100 (VMOVDDUPZrm addr:$src)>;
3102 //===---------------------------------------------------------------------===//
3103 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3104 //===---------------------------------------------------------------------===//
3105 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3106 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3107 X86MemOperand x86memop> {
3108 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3109 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3110 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3112 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3113 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3114 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3117 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3118 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3119 EVEX_CD8<32, CD8VF>;
3120 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3121 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3122 EVEX_CD8<32, CD8VF>;
3124 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3125 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3126 (VMOVSHDUPZrm addr:$src)>;
3127 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3128 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3129 (VMOVSLDUPZrm addr:$src)>;
3131 //===----------------------------------------------------------------------===//
3132 // Move Low to High and High to Low packed FP Instructions
3133 //===----------------------------------------------------------------------===//
3134 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3135 (ins VR128X:$src1, VR128X:$src2),
3136 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3137 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3138 IIC_SSE_MOV_LH>, EVEX_4V;
3139 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3140 (ins VR128X:$src1, VR128X:$src2),
3141 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3142 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3143 IIC_SSE_MOV_LH>, EVEX_4V;
3145 let Predicates = [HasAVX512] in {
3147 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3148 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3149 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3150 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3153 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3154 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3157 //===----------------------------------------------------------------------===//
3158 // FMA - Fused Multiply Operations
3160 let Constraints = "$src1 = $dst" in {
3161 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3162 X86VectorVTInfo _> {
3163 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3164 (ins _.RC:$src2, _.RC:$src3),
3165 OpcodeStr, "$src3, $src2", "$src2, $src3",
3166 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3170 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3171 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3172 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3173 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3174 (_.MemOpFrag addr:$src3))))]>;
3175 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3176 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3177 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3178 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3179 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3180 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3182 } // Constraints = "$src1 = $dst"
3184 let ExeDomain = SSEPackedSingle in {
3185 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3187 EVEX_V512, EVEX_CD8<32, CD8VF>;
3188 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3190 EVEX_V512, EVEX_CD8<32, CD8VF>;
3191 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3193 EVEX_V512, EVEX_CD8<32, CD8VF>;
3194 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3196 EVEX_V512, EVEX_CD8<32, CD8VF>;
3197 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3199 EVEX_V512, EVEX_CD8<32, CD8VF>;
3200 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3202 EVEX_V512, EVEX_CD8<32, CD8VF>;
3204 let ExeDomain = SSEPackedDouble in {
3205 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3207 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3208 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3210 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3211 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3213 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3214 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3216 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3217 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3219 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3220 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3222 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3225 let Constraints = "$src1 = $dst" in {
3226 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3227 X86VectorVTInfo _> {
3229 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3230 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3231 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3232 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3234 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3235 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3236 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3237 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3239 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3240 (_.ScalarLdFrag addr:$src2))),
3241 _.RC:$src3))]>, EVEX_B;
3243 } // Constraints = "$src1 = $dst"
3246 let ExeDomain = SSEPackedSingle in {
3247 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3249 EVEX_V512, EVEX_CD8<32, CD8VF>;
3250 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3252 EVEX_V512, EVEX_CD8<32, CD8VF>;
3253 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3255 EVEX_V512, EVEX_CD8<32, CD8VF>;
3256 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3258 EVEX_V512, EVEX_CD8<32, CD8VF>;
3259 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3261 EVEX_V512, EVEX_CD8<32, CD8VF>;
3262 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3264 EVEX_V512, EVEX_CD8<32, CD8VF>;
3266 let ExeDomain = SSEPackedDouble in {
3267 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3269 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3270 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3272 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3273 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3275 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3276 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3278 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3279 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3281 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3282 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3284 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3288 let Constraints = "$src1 = $dst" in {
3289 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3290 RegisterClass RC, ValueType OpVT,
3291 X86MemOperand x86memop, Operand memop,
3293 let isCommutable = 1 in
3294 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3295 (ins RC:$src1, RC:$src2, RC:$src3),
3296 !strconcat(OpcodeStr,
3297 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3299 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3301 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3302 (ins RC:$src1, RC:$src2, f128mem:$src3),
3303 !strconcat(OpcodeStr,
3304 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3306 (OpVT (OpNode RC:$src2, RC:$src1,
3307 (mem_frag addr:$src3))))]>;
3310 } // Constraints = "$src1 = $dst"
3312 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3313 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3314 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3315 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3316 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3317 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3318 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3319 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3320 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3321 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3322 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3323 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3324 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3325 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3326 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3327 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3329 //===----------------------------------------------------------------------===//
3330 // AVX-512 Scalar convert from sign integer to float/double
3331 //===----------------------------------------------------------------------===//
3333 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3334 X86MemOperand x86memop, string asm> {
3335 let hasSideEffects = 0 in {
3336 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3337 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3340 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3341 (ins DstRC:$src1, x86memop:$src),
3342 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3344 } // hasSideEffects = 0
3346 let Predicates = [HasAVX512] in {
3347 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3348 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3349 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3350 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3351 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3352 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3353 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3354 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3356 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3357 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3358 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3359 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3360 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3361 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3362 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3363 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3365 def : Pat<(f32 (sint_to_fp GR32:$src)),
3366 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3367 def : Pat<(f32 (sint_to_fp GR64:$src)),
3368 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3369 def : Pat<(f64 (sint_to_fp GR32:$src)),
3370 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3371 def : Pat<(f64 (sint_to_fp GR64:$src)),
3372 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3374 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3375 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3376 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3377 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3378 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3379 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3380 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3381 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3383 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3384 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3385 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3386 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3387 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3388 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3389 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3390 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3392 def : Pat<(f32 (uint_to_fp GR32:$src)),
3393 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3394 def : Pat<(f32 (uint_to_fp GR64:$src)),
3395 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3396 def : Pat<(f64 (uint_to_fp GR32:$src)),
3397 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3398 def : Pat<(f64 (uint_to_fp GR64:$src)),
3399 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3402 //===----------------------------------------------------------------------===//
3403 // AVX-512 Scalar convert from float/double to integer
3404 //===----------------------------------------------------------------------===//
3405 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3406 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3408 let hasSideEffects = 0 in {
3409 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3410 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3411 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3412 Requires<[HasAVX512]>;
3414 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3415 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3416 Requires<[HasAVX512]>;
3417 } // hasSideEffects = 0
3419 let Predicates = [HasAVX512] in {
3420 // Convert float/double to signed/unsigned int 32/64
3421 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3422 ssmem, sse_load_f32, "cvtss2si">,
3423 XS, EVEX_CD8<32, CD8VT1>;
3424 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3425 ssmem, sse_load_f32, "cvtss2si">,
3426 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3427 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3428 ssmem, sse_load_f32, "cvtss2usi">,
3429 XS, EVEX_CD8<32, CD8VT1>;
3430 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3431 int_x86_avx512_cvtss2usi64, ssmem,
3432 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3433 EVEX_CD8<32, CD8VT1>;
3434 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3435 sdmem, sse_load_f64, "cvtsd2si">,
3436 XD, EVEX_CD8<64, CD8VT1>;
3437 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3438 sdmem, sse_load_f64, "cvtsd2si">,
3439 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3440 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3441 sdmem, sse_load_f64, "cvtsd2usi">,
3442 XD, EVEX_CD8<64, CD8VT1>;
3443 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3444 int_x86_avx512_cvtsd2usi64, sdmem,
3445 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3446 EVEX_CD8<64, CD8VT1>;
3448 let isCodeGenOnly = 1 in {
3449 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3450 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3451 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3452 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3453 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3454 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3455 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3456 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3457 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3458 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3459 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3460 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3462 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3463 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3464 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3465 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3466 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3467 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3468 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3469 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3470 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3471 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3472 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3473 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3474 } // isCodeGenOnly = 1
3476 // Convert float/double to signed/unsigned int 32/64 with truncation
3477 let isCodeGenOnly = 1 in {
3478 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3479 ssmem, sse_load_f32, "cvttss2si">,
3480 XS, EVEX_CD8<32, CD8VT1>;
3481 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3482 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3483 "cvttss2si">, XS, VEX_W,
3484 EVEX_CD8<32, CD8VT1>;
3485 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3486 sdmem, sse_load_f64, "cvttsd2si">, XD,
3487 EVEX_CD8<64, CD8VT1>;
3488 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3489 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3490 "cvttsd2si">, XD, VEX_W,
3491 EVEX_CD8<64, CD8VT1>;
3492 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3493 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3494 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3495 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3496 int_x86_avx512_cvttss2usi64, ssmem,
3497 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3498 EVEX_CD8<32, CD8VT1>;
3499 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3500 int_x86_avx512_cvttsd2usi,
3501 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3502 EVEX_CD8<64, CD8VT1>;
3503 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3504 int_x86_avx512_cvttsd2usi64, sdmem,
3505 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3506 EVEX_CD8<64, CD8VT1>;
3507 } // isCodeGenOnly = 1
3509 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3510 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3512 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3513 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3514 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3515 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3516 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3517 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3520 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3521 loadf32, "cvttss2si">, XS,
3522 EVEX_CD8<32, CD8VT1>;
3523 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3524 loadf32, "cvttss2usi">, XS,
3525 EVEX_CD8<32, CD8VT1>;
3526 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3527 loadf32, "cvttss2si">, XS, VEX_W,
3528 EVEX_CD8<32, CD8VT1>;
3529 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3530 loadf32, "cvttss2usi">, XS, VEX_W,
3531 EVEX_CD8<32, CD8VT1>;
3532 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3533 loadf64, "cvttsd2si">, XD,
3534 EVEX_CD8<64, CD8VT1>;
3535 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3536 loadf64, "cvttsd2usi">, XD,
3537 EVEX_CD8<64, CD8VT1>;
3538 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3539 loadf64, "cvttsd2si">, XD, VEX_W,
3540 EVEX_CD8<64, CD8VT1>;
3541 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3542 loadf64, "cvttsd2usi">, XD, VEX_W,
3543 EVEX_CD8<64, CD8VT1>;
3545 //===----------------------------------------------------------------------===//
3546 // AVX-512 Convert form float to double and back
3547 //===----------------------------------------------------------------------===//
3548 let hasSideEffects = 0 in {
3549 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3550 (ins FR32X:$src1, FR32X:$src2),
3551 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3552 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3554 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3555 (ins FR32X:$src1, f32mem:$src2),
3556 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3557 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3558 EVEX_CD8<32, CD8VT1>;
3560 // Convert scalar double to scalar single
3561 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3562 (ins FR64X:$src1, FR64X:$src2),
3563 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3564 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3566 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3567 (ins FR64X:$src1, f64mem:$src2),
3568 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3569 []>, EVEX_4V, VEX_LIG, VEX_W,
3570 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3573 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3574 Requires<[HasAVX512]>;
3575 def : Pat<(fextend (loadf32 addr:$src)),
3576 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3578 def : Pat<(extloadf32 addr:$src),
3579 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3580 Requires<[HasAVX512, OptForSize]>;
3582 def : Pat<(extloadf32 addr:$src),
3583 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3584 Requires<[HasAVX512, OptForSpeed]>;
3586 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3587 Requires<[HasAVX512]>;
3589 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3590 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3591 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3593 let hasSideEffects = 0 in {
3594 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3595 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3597 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3598 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3599 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3600 [], d>, EVEX, EVEX_B, EVEX_RC;
3602 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3603 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3605 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3606 } // hasSideEffects = 0
3609 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3610 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3611 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3613 let hasSideEffects = 0 in {
3614 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3615 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3617 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3619 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3620 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3622 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3623 } // hasSideEffects = 0
3626 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3627 memopv8f64, f512mem, v8f32, v8f64,
3628 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3629 EVEX_CD8<64, CD8VF>;
3631 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3632 memopv4f64, f256mem, v8f64, v8f32,
3633 SSEPackedDouble>, EVEX_V512, PS,
3634 EVEX_CD8<32, CD8VH>;
3635 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3636 (VCVTPS2PDZrm addr:$src)>;
3638 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3639 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3640 (VCVTPD2PSZrr VR512:$src)>;
3642 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3643 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3644 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3646 //===----------------------------------------------------------------------===//
3647 // AVX-512 Vector convert from sign integer to float/double
3648 //===----------------------------------------------------------------------===//
3650 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3651 memopv8i64, i512mem, v16f32, v16i32,
3652 SSEPackedSingle>, EVEX_V512, PS,
3653 EVEX_CD8<32, CD8VF>;
3655 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3656 memopv4i64, i256mem, v8f64, v8i32,
3657 SSEPackedDouble>, EVEX_V512, XS,
3658 EVEX_CD8<32, CD8VH>;
3660 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3661 memopv16f32, f512mem, v16i32, v16f32,
3662 SSEPackedSingle>, EVEX_V512, XS,
3663 EVEX_CD8<32, CD8VF>;
3665 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3666 memopv8f64, f512mem, v8i32, v8f64,
3667 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3668 EVEX_CD8<64, CD8VF>;
3670 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3671 memopv16f32, f512mem, v16i32, v16f32,
3672 SSEPackedSingle>, EVEX_V512, PS,
3673 EVEX_CD8<32, CD8VF>;
3675 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3676 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3677 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3678 (VCVTTPS2UDQZrr VR512:$src)>;
3680 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3681 memopv8f64, f512mem, v8i32, v8f64,
3682 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3683 EVEX_CD8<64, CD8VF>;
3685 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3686 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3687 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3688 (VCVTTPD2UDQZrr VR512:$src)>;
3690 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3691 memopv4i64, f256mem, v8f64, v8i32,
3692 SSEPackedDouble>, EVEX_V512, XS,
3693 EVEX_CD8<32, CD8VH>;
3695 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3696 memopv16i32, f512mem, v16f32, v16i32,
3697 SSEPackedSingle>, EVEX_V512, XD,
3698 EVEX_CD8<32, CD8VF>;
3700 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3701 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3702 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3704 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3705 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3706 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3708 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3709 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3710 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3712 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3713 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3714 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3716 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3717 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3718 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3720 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3721 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3722 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3723 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3724 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3725 (VCVTDQ2PDZrr VR256X:$src)>;
3726 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3727 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3728 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3729 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3730 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3731 (VCVTUDQ2PDZrr VR256X:$src)>;
3733 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3734 RegisterClass DstRC, PatFrag mem_frag,
3735 X86MemOperand x86memop, Domain d> {
3736 let hasSideEffects = 0 in {
3737 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3738 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3740 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3741 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3742 [], d>, EVEX, EVEX_B, EVEX_RC;
3744 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3745 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3747 } // hasSideEffects = 0
3750 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3751 memopv16f32, f512mem, SSEPackedSingle>, PD,
3752 EVEX_V512, EVEX_CD8<32, CD8VF>;
3753 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3754 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3755 EVEX_V512, EVEX_CD8<64, CD8VF>;
3757 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3758 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3759 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3761 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3762 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3763 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3765 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3766 memopv16f32, f512mem, SSEPackedSingle>,
3767 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3768 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3769 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3770 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3772 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3773 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3774 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3776 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3777 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3778 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3780 let Predicates = [HasAVX512] in {
3781 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3782 (VCVTPD2PSZrm addr:$src)>;
3783 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3784 (VCVTPS2PDZrm addr:$src)>;
3787 //===----------------------------------------------------------------------===//
3788 // Half precision conversion instructions
3789 //===----------------------------------------------------------------------===//
3790 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3791 X86MemOperand x86memop> {
3792 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3793 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3795 let hasSideEffects = 0, mayLoad = 1 in
3796 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3797 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3800 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3801 X86MemOperand x86memop> {
3802 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3803 (ins srcRC:$src1, i32i8imm:$src2),
3804 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3806 let hasSideEffects = 0, mayStore = 1 in
3807 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3808 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3809 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3812 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3813 EVEX_CD8<32, CD8VH>;
3814 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3815 EVEX_CD8<32, CD8VH>;
3817 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3818 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3819 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3821 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3822 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3823 (VCVTPH2PSZrr VR256X:$src)>;
3825 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3826 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3827 "ucomiss">, PS, EVEX, VEX_LIG,
3828 EVEX_CD8<32, CD8VT1>;
3829 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3830 "ucomisd">, PD, EVEX,
3831 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3832 let Pattern = []<dag> in {
3833 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3834 "comiss">, PS, EVEX, VEX_LIG,
3835 EVEX_CD8<32, CD8VT1>;
3836 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3837 "comisd">, PD, EVEX,
3838 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3840 let isCodeGenOnly = 1 in {
3841 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3842 load, "ucomiss">, PS, EVEX, VEX_LIG,
3843 EVEX_CD8<32, CD8VT1>;
3844 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3845 load, "ucomisd">, PD, EVEX,
3846 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3848 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3849 load, "comiss">, PS, EVEX, VEX_LIG,
3850 EVEX_CD8<32, CD8VT1>;
3851 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3852 load, "comisd">, PD, EVEX,
3853 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3857 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3858 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3859 X86MemOperand x86memop> {
3860 let hasSideEffects = 0 in {
3861 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3862 (ins RC:$src1, RC:$src2),
3863 !strconcat(OpcodeStr,
3864 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3865 let mayLoad = 1 in {
3866 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3867 (ins RC:$src1, x86memop:$src2),
3868 !strconcat(OpcodeStr,
3869 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3874 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3875 EVEX_CD8<32, CD8VT1>;
3876 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3877 VEX_W, EVEX_CD8<64, CD8VT1>;
3878 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3879 EVEX_CD8<32, CD8VT1>;
3880 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3881 VEX_W, EVEX_CD8<64, CD8VT1>;
3883 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3884 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3885 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3886 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3888 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3889 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3890 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3891 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3893 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3894 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3895 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3896 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3898 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3899 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3900 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3901 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3903 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3904 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3905 RegisterClass RC, X86MemOperand x86memop,
3906 PatFrag mem_frag, ValueType OpVt> {
3907 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3908 !strconcat(OpcodeStr,
3909 " \t{$src, $dst|$dst, $src}"),
3910 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3912 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3913 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3914 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3917 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3918 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3919 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3920 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3921 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3922 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3923 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3924 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3926 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3927 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3928 (VRSQRT14PSZr VR512:$src)>;
3929 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3930 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3931 (VRSQRT14PDZr VR512:$src)>;
3933 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3934 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3935 (VRCP14PSZr VR512:$src)>;
3936 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3937 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3938 (VRCP14PDZr VR512:$src)>;
3940 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3941 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3942 X86MemOperand x86memop> {
3943 let hasSideEffects = 0, Predicates = [HasERI] in {
3944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3945 (ins RC:$src1, RC:$src2),
3946 !strconcat(OpcodeStr,
3947 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3948 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3949 (ins RC:$src1, RC:$src2),
3950 !strconcat(OpcodeStr,
3951 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3952 []>, EVEX_4V, EVEX_B;
3953 let mayLoad = 1 in {
3954 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3955 (ins RC:$src1, x86memop:$src2),
3956 !strconcat(OpcodeStr,
3957 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3962 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3963 EVEX_CD8<32, CD8VT1>;
3964 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3965 VEX_W, EVEX_CD8<64, CD8VT1>;
3966 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3967 EVEX_CD8<32, CD8VT1>;
3968 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3969 VEX_W, EVEX_CD8<64, CD8VT1>;
3971 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3972 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3974 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3975 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3977 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3978 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3980 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3981 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3983 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3984 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3986 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3987 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3989 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3990 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3992 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3993 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3995 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3996 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3997 RegisterClass RC, X86MemOperand x86memop> {
3998 let hasSideEffects = 0, Predicates = [HasERI] in {
3999 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4000 !strconcat(OpcodeStr,
4001 " \t{$src, $dst|$dst, $src}"),
4003 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4004 !strconcat(OpcodeStr,
4005 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4007 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4008 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4012 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4013 EVEX_V512, EVEX_CD8<32, CD8VF>;
4014 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4015 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4016 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4017 EVEX_V512, EVEX_CD8<32, CD8VF>;
4018 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4019 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4021 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4022 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4023 (VRSQRT28PSZrb VR512:$src)>;
4024 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4025 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4026 (VRSQRT28PDZrb VR512:$src)>;
4028 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4029 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4030 (VRCP28PSZrb VR512:$src)>;
4031 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4032 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4033 (VRCP28PDZrb VR512:$src)>;
4035 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4036 OpndItins itins_s, OpndItins itins_d> {
4037 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4038 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4039 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4043 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4044 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
4046 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4047 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4049 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
4050 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4051 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4055 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
4056 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
4057 [(set VR512:$dst, (OpNode
4058 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4059 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4063 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4064 Intrinsic F32Int, Intrinsic F64Int,
4065 OpndItins itins_s, OpndItins itins_d> {
4066 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4067 (ins FR32X:$src1, FR32X:$src2),
4068 !strconcat(OpcodeStr,
4069 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4070 [], itins_s.rr>, XS, EVEX_4V;
4071 let isCodeGenOnly = 1 in
4072 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4073 (ins VR128X:$src1, VR128X:$src2),
4074 !strconcat(OpcodeStr,
4075 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4077 (F32Int VR128X:$src1, VR128X:$src2))],
4078 itins_s.rr>, XS, EVEX_4V;
4079 let mayLoad = 1 in {
4080 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4081 (ins FR32X:$src1, f32mem:$src2),
4082 !strconcat(OpcodeStr,
4083 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4084 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4085 let isCodeGenOnly = 1 in
4086 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4087 (ins VR128X:$src1, ssmem:$src2),
4088 !strconcat(OpcodeStr,
4089 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4091 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4092 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4094 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4095 (ins FR64X:$src1, FR64X:$src2),
4096 !strconcat(OpcodeStr,
4097 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4099 let isCodeGenOnly = 1 in
4100 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4101 (ins VR128X:$src1, VR128X:$src2),
4102 !strconcat(OpcodeStr,
4103 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4105 (F64Int VR128X:$src1, VR128X:$src2))],
4106 itins_s.rr>, XD, EVEX_4V, VEX_W;
4107 let mayLoad = 1 in {
4108 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4109 (ins FR64X:$src1, f64mem:$src2),
4110 !strconcat(OpcodeStr,
4111 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4112 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4113 let isCodeGenOnly = 1 in
4114 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4115 (ins VR128X:$src1, sdmem:$src2),
4116 !strconcat(OpcodeStr,
4117 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4119 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4120 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4125 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4126 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4127 SSE_SQRTSS, SSE_SQRTSD>,
4128 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
4129 SSE_SQRTPS, SSE_SQRTPD>;
4131 let Predicates = [HasAVX512] in {
4132 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4133 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4134 (VSQRTPSZrr VR512:$src1)>;
4135 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4136 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4137 (VSQRTPDZrr VR512:$src1)>;
4139 def : Pat<(f32 (fsqrt FR32X:$src)),
4140 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4141 def : Pat<(f32 (fsqrt (load addr:$src))),
4142 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4143 Requires<[OptForSize]>;
4144 def : Pat<(f64 (fsqrt FR64X:$src)),
4145 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4146 def : Pat<(f64 (fsqrt (load addr:$src))),
4147 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4148 Requires<[OptForSize]>;
4150 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4151 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4152 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4153 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4154 Requires<[OptForSize]>;
4156 def : Pat<(f32 (X86frcp FR32X:$src)),
4157 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4158 def : Pat<(f32 (X86frcp (load addr:$src))),
4159 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4160 Requires<[OptForSize]>;
4162 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4163 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4164 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4166 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4167 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4169 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4170 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4171 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4173 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4174 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4178 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4179 X86MemOperand x86memop, RegisterClass RC,
4180 PatFrag mem_frag32, PatFrag mem_frag64,
4181 Intrinsic V4F32Int, Intrinsic V2F64Int,
4183 let ExeDomain = SSEPackedSingle in {
4184 // Intrinsic operation, reg.
4185 // Vector intrinsic operation, reg
4186 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4187 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4188 !strconcat(OpcodeStr,
4189 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4190 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4192 // Vector intrinsic operation, mem
4193 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4194 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4195 !strconcat(OpcodeStr,
4196 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4198 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4199 EVEX_CD8<32, VForm>;
4200 } // ExeDomain = SSEPackedSingle
4202 let ExeDomain = SSEPackedDouble in {
4203 // Vector intrinsic operation, reg
4204 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4205 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4206 !strconcat(OpcodeStr,
4207 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4208 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4210 // Vector intrinsic operation, mem
4211 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4212 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4213 !strconcat(OpcodeStr,
4214 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4216 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4217 EVEX_CD8<64, VForm>;
4218 } // ExeDomain = SSEPackedDouble
4221 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4225 let ExeDomain = GenericDomain in {
4227 let hasSideEffects = 0 in
4228 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4229 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4230 !strconcat(OpcodeStr,
4231 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4234 // Intrinsic operation, reg.
4235 let isCodeGenOnly = 1 in
4236 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4237 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4238 !strconcat(OpcodeStr,
4239 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4240 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4242 // Intrinsic operation, mem.
4243 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4244 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4245 !strconcat(OpcodeStr,
4246 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4247 [(set VR128X:$dst, (F32Int VR128X:$src1,
4248 sse_load_f32:$src2, imm:$src3))]>,
4249 EVEX_CD8<32, CD8VT1>;
4252 let hasSideEffects = 0 in
4253 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4254 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4255 !strconcat(OpcodeStr,
4256 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4259 // Intrinsic operation, reg.
4260 let isCodeGenOnly = 1 in
4261 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4262 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4263 !strconcat(OpcodeStr,
4264 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4265 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4268 // Intrinsic operation, mem.
4269 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4270 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4271 !strconcat(OpcodeStr,
4272 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4274 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4275 VEX_W, EVEX_CD8<64, CD8VT1>;
4276 } // ExeDomain = GenericDomain
4279 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4280 X86MemOperand x86memop, RegisterClass RC,
4281 PatFrag mem_frag, Domain d> {
4282 let ExeDomain = d in {
4283 // Intrinsic operation, reg.
4284 // Vector intrinsic operation, reg
4285 def r : AVX512AIi8<opc, MRMSrcReg,
4286 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4287 !strconcat(OpcodeStr,
4288 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4291 // Vector intrinsic operation, mem
4292 def m : AVX512AIi8<opc, MRMSrcMem,
4293 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4294 !strconcat(OpcodeStr,
4295 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4301 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4302 memopv16f32, SSEPackedSingle>, EVEX_V512,
4303 EVEX_CD8<32, CD8VF>;
4305 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4306 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4308 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4311 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4312 memopv8f64, SSEPackedDouble>, EVEX_V512,
4313 VEX_W, EVEX_CD8<64, CD8VF>;
4315 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4316 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4318 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4320 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4321 Operand x86memop, RegisterClass RC, Domain d> {
4322 let ExeDomain = d in {
4323 def r : AVX512AIi8<opc, MRMSrcReg,
4324 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4325 !strconcat(OpcodeStr,
4326 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4329 def m : AVX512AIi8<opc, MRMSrcMem,
4330 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4331 !strconcat(OpcodeStr,
4332 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4337 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4338 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4340 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4341 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4343 def : Pat<(ffloor FR32X:$src),
4344 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4345 def : Pat<(f64 (ffloor FR64X:$src)),
4346 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4347 def : Pat<(f32 (fnearbyint FR32X:$src)),
4348 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4349 def : Pat<(f64 (fnearbyint FR64X:$src)),
4350 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4351 def : Pat<(f32 (fceil FR32X:$src)),
4352 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4353 def : Pat<(f64 (fceil FR64X:$src)),
4354 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4355 def : Pat<(f32 (frint FR32X:$src)),
4356 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4357 def : Pat<(f64 (frint FR64X:$src)),
4358 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4359 def : Pat<(f32 (ftrunc FR32X:$src)),
4360 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4361 def : Pat<(f64 (ftrunc FR64X:$src)),
4362 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4364 def : Pat<(v16f32 (ffloor VR512:$src)),
4365 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4366 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4367 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4368 def : Pat<(v16f32 (fceil VR512:$src)),
4369 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4370 def : Pat<(v16f32 (frint VR512:$src)),
4371 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4372 def : Pat<(v16f32 (ftrunc VR512:$src)),
4373 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4375 def : Pat<(v8f64 (ffloor VR512:$src)),
4376 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4377 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4378 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4379 def : Pat<(v8f64 (fceil VR512:$src)),
4380 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4381 def : Pat<(v8f64 (frint VR512:$src)),
4382 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4383 def : Pat<(v8f64 (ftrunc VR512:$src)),
4384 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4386 //-------------------------------------------------
4387 // Integer truncate and extend operations
4388 //-------------------------------------------------
4390 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4391 RegisterClass dstRC, RegisterClass srcRC,
4392 RegisterClass KRC, X86MemOperand x86memop> {
4393 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4395 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4398 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4399 (ins KRC:$mask, srcRC:$src),
4400 !strconcat(OpcodeStr,
4401 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4404 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4405 (ins KRC:$mask, srcRC:$src),
4406 !strconcat(OpcodeStr,
4407 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4410 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4411 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4414 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4415 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4416 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4420 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4421 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4422 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4423 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4424 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4425 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4426 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4427 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4428 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4429 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4430 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4431 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4432 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4433 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4434 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4435 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4436 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4437 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4438 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4439 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4440 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4441 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4442 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4443 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4444 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4445 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4446 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4447 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4448 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4449 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4451 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4452 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4453 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4454 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4455 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4457 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4458 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4459 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4460 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4461 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4462 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4463 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4464 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4467 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4468 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4469 PatFrag mem_frag, X86MemOperand x86memop,
4470 ValueType OpVT, ValueType InVT> {
4472 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4474 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4475 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4477 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4478 (ins KRC:$mask, SrcRC:$src),
4479 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4482 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4483 (ins KRC:$mask, SrcRC:$src),
4484 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4487 let mayLoad = 1 in {
4488 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4489 (ins x86memop:$src),
4490 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4492 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4495 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4496 (ins KRC:$mask, x86memop:$src),
4497 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4501 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4502 (ins KRC:$mask, x86memop:$src),
4503 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4509 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4510 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4512 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4513 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4515 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4516 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4517 EVEX_CD8<16, CD8VH>;
4518 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4519 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4520 EVEX_CD8<16, CD8VQ>;
4521 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4522 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4523 EVEX_CD8<32, CD8VH>;
4525 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4526 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4528 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4529 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4531 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4532 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4533 EVEX_CD8<16, CD8VH>;
4534 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4535 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4536 EVEX_CD8<16, CD8VQ>;
4537 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4538 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4539 EVEX_CD8<32, CD8VH>;
4541 //===----------------------------------------------------------------------===//
4542 // GATHER - SCATTER Operations
4544 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4545 RegisterClass RC, X86MemOperand memop> {
4547 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4548 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4549 (ins RC:$src1, KRC:$mask, memop:$src2),
4550 !strconcat(OpcodeStr,
4551 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4555 let ExeDomain = SSEPackedDouble in {
4556 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4557 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4558 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4559 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4562 let ExeDomain = SSEPackedSingle in {
4563 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4564 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4565 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4566 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4569 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4570 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4571 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4572 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4574 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4575 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4576 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4577 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4579 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4580 RegisterClass RC, X86MemOperand memop> {
4581 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4582 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4583 (ins memop:$dst, KRC:$mask, RC:$src2),
4584 !strconcat(OpcodeStr,
4585 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4589 let ExeDomain = SSEPackedDouble in {
4590 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4591 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4592 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4593 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4596 let ExeDomain = SSEPackedSingle in {
4597 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4598 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4599 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4600 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4603 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4604 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4605 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4606 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4608 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4609 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4610 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4611 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4614 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4615 RegisterClass KRC, X86MemOperand memop> {
4616 let Predicates = [HasPFI], hasSideEffects = 1 in
4617 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4618 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4622 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4623 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4625 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4626 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4628 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4629 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4631 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4632 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4634 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4635 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4637 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4638 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4640 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4641 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4643 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4644 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4646 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4647 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4649 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4650 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4652 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4653 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4655 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4656 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4658 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4659 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4661 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4662 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4664 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4665 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4667 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4668 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4669 //===----------------------------------------------------------------------===//
4670 // VSHUFPS - VSHUFPD Operations
4672 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4673 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4675 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4676 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4677 !strconcat(OpcodeStr,
4678 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4679 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4680 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4681 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4682 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4683 (ins RC:$src1, RC:$src2, i8imm:$src3),
4684 !strconcat(OpcodeStr,
4685 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4686 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4687 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4688 EVEX_4V, Sched<[WriteShuffle]>;
4691 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4692 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4693 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4694 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4696 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4697 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4698 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4699 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4700 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4702 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4703 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4704 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4705 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4706 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4708 multiclass avx512_valign<X86VectorVTInfo _> {
4709 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4710 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4712 "$src3, $src2, $src1", "$src1, $src2, $src3",
4713 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4715 AVX512AIi8Base, EVEX_4V;
4717 // Also match valign of packed floats.
4718 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4719 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4722 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4723 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4724 !strconcat("valign"##_.Suffix,
4725 " \t{$src3, $src2, $src1, $dst|"
4726 "$dst, $src1, $src2, $src3}"),
4729 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4730 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4732 // Helper fragments to match sext vXi1 to vXiY.
4733 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4734 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4736 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4737 RegisterClass KRC, RegisterClass RC,
4738 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4740 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4741 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4743 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4744 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4746 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4747 !strconcat(OpcodeStr,
4748 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4750 let mayLoad = 1 in {
4751 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4752 (ins x86memop:$src),
4753 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4755 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4756 (ins KRC:$mask, x86memop:$src),
4757 !strconcat(OpcodeStr,
4758 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4760 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4761 (ins KRC:$mask, x86memop:$src),
4762 !strconcat(OpcodeStr,
4763 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4765 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4766 (ins x86scalar_mop:$src),
4767 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4768 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4770 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4771 (ins KRC:$mask, x86scalar_mop:$src),
4772 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4773 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4774 []>, EVEX, EVEX_B, EVEX_K;
4775 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4776 (ins KRC:$mask, x86scalar_mop:$src),
4777 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4778 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4780 []>, EVEX, EVEX_B, EVEX_KZ;
4784 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4785 i512mem, i32mem, "{1to16}">, EVEX_V512,
4786 EVEX_CD8<32, CD8VF>;
4787 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4788 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4789 EVEX_CD8<64, CD8VF>;
4792 (bc_v16i32 (v16i1sextv16i32)),
4793 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4794 (VPABSDZrr VR512:$src)>;
4796 (bc_v8i64 (v8i1sextv8i64)),
4797 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4798 (VPABSQZrr VR512:$src)>;
4800 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4801 (v16i32 immAllZerosV), (i16 -1))),
4802 (VPABSDZrr VR512:$src)>;
4803 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4804 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4805 (VPABSQZrr VR512:$src)>;
4807 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4808 RegisterClass RC, RegisterClass KRC,
4809 X86MemOperand x86memop,
4810 X86MemOperand x86scalar_mop, string BrdcstStr> {
4811 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4813 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4815 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4816 (ins x86memop:$src),
4817 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4819 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4820 (ins x86scalar_mop:$src),
4821 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4822 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4824 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4825 (ins KRC:$mask, RC:$src),
4826 !strconcat(OpcodeStr,
4827 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4829 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4830 (ins KRC:$mask, x86memop:$src),
4831 !strconcat(OpcodeStr,
4832 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4834 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4835 (ins KRC:$mask, x86scalar_mop:$src),
4836 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4837 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4839 []>, EVEX, EVEX_KZ, EVEX_B;
4841 let Constraints = "$src1 = $dst" in {
4842 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4843 (ins RC:$src1, KRC:$mask, RC:$src2),
4844 !strconcat(OpcodeStr,
4845 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4847 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4848 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4849 !strconcat(OpcodeStr,
4850 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4852 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4853 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4854 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4855 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4856 []>, EVEX, EVEX_K, EVEX_B;
4860 let Predicates = [HasCDI] in {
4861 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4862 i512mem, i32mem, "{1to16}">,
4863 EVEX_V512, EVEX_CD8<32, CD8VF>;
4866 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4867 i512mem, i64mem, "{1to8}">,
4868 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4872 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4874 (VPCONFLICTDrrk VR512:$src1,
4875 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4877 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4879 (VPCONFLICTQrrk VR512:$src1,
4880 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4882 let Predicates = [HasCDI] in {
4883 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4884 i512mem, i32mem, "{1to16}">,
4885 EVEX_V512, EVEX_CD8<32, CD8VF>;
4888 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4889 i512mem, i64mem, "{1to8}">,
4890 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4894 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4896 (VPLZCNTDrrk VR512:$src1,
4897 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4899 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4901 (VPLZCNTQrrk VR512:$src1,
4902 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4904 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4905 (VPLZCNTDrm addr:$src)>;
4906 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4907 (VPLZCNTDrr VR512:$src)>;
4908 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4909 (VPLZCNTQrm addr:$src)>;
4910 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4911 (VPLZCNTQrr VR512:$src)>;
4913 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4914 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4915 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4917 def : Pat<(store VK1:$src, addr:$dst),
4918 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4920 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4921 (truncstore node:$val, node:$ptr), [{
4922 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4925 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4926 (MOV8mr addr:$dst, GR8:$src)>;
4928 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
4929 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
4930 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
4931 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
4934 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
4935 string OpcodeStr, Predicate prd> {
4936 let Predicates = [prd] in
4937 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
4939 let Predicates = [prd, HasVLX] in {
4940 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
4941 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
4945 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
4946 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
4948 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
4950 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
4952 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
4956 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;