1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
406 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
410 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
413 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
416 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
421 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
422 X86MemOperand x86memop, PatFrag ld_frag,
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
431 !strconcat(OpcodeStr,
432 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
442 !strconcat(OpcodeStr,
443 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
448 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
451 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
453 EVEX_CD8<64, CD8VT1>;
455 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
456 (VBROADCASTSSZrr VR128X:$src)>;
457 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
458 (VBROADCASTSDZrr VR128X:$src)>;
460 // Provide fallback in case the load node that is used in the patterns above
461 // is used by additional users, which prevents the pattern selection.
462 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
464 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
468 let Predicates = [HasAVX512] in {
469 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
472 addr:$src)), sub_ymm)>;
474 //===----------------------------------------------------------------------===//
475 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
478 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
479 RegisterClass DstRC, RegisterClass KRC,
480 ValueType OpVT, ValueType SrcVT> {
481 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
486 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
487 VK16, v16i32, v16i1>, EVEX_V512;
488 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
491 //===----------------------------------------------------------------------===//
494 // -- immediate form --
495 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
496 SDNode OpNode, PatFrag mem_frag,
497 X86MemOperand x86memop, ValueType OpVT> {
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
499 (ins RC:$src1, i8imm:$src2),
500 !strconcat(OpcodeStr,
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
506 (ins x86memop:$src1, i8imm:$src2),
507 !strconcat(OpcodeStr,
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
510 (OpVT (OpNode (mem_frag addr:$src1),
511 (i8 imm:$src2))))]>, EVEX;
514 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
516 let ExeDomain = SSEPackedDouble in
517 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
520 // -- VPERM - register form --
521 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, RC:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
532 (ins RC:$src1, x86memop:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
540 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
542 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
544 let ExeDomain = SSEPackedSingle in
545 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
547 let ExeDomain = SSEPackedDouble in
548 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
551 // -- VPERM2I - 3 source operands form --
552 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
553 PatFrag mem_frag, X86MemOperand x86memop,
555 let Constraints = "$src1 = $dst" in {
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, RC:$src2, RC:$src3),
558 !strconcat(OpcodeStr,
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
566 !strconcat(OpcodeStr,
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
570 (mem_frag addr:$src3))))]>, EVEX_4V;
573 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
582 //===----------------------------------------------------------------------===//
583 // AVX-512 - BLEND using mask
585 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
586 RegisterClass KRC, RegisterClass RC,
587 X86MemOperand x86memop, PatFrag mem_frag,
588 SDNode OpNode, ValueType vt> {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins KRC:$mask, RC:$src1, RC:$src2),
591 !strconcat(OpcodeStr,
592 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
598 !strconcat(OpcodeStr,
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
604 let ExeDomain = SSEPackedSingle in
605 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
606 memopv16f32, vselect, v16f32>,
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
608 let ExeDomain = SSEPackedDouble in
609 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
610 memopv8f64, vselect, v8f64>,
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
613 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
614 memopv8i64, vselect, v16i32>,
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
617 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
618 memopv8i64, vselect, v8i64>, VEX_W,
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
621 let Predicates = [HasAVX512] in {
622 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
623 (v8f32 VR256X:$src2))),
625 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
626 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
629 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
630 (v8i32 VR256X:$src2))),
632 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
633 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
637 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
638 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
639 SDNode OpNode, ValueType vt> {
640 def rr : AVX512BI<opc, MRMSrcReg,
641 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
643 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
644 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
645 def rm : AVX512BI<opc, MRMSrcMem,
646 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
648 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
649 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
652 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
653 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
654 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
655 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
657 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
658 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
659 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
660 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
662 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
663 (COPY_TO_REGCLASS (VPCMPGTDZrr
664 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
667 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
668 (COPY_TO_REGCLASS (VPCMPEQDZrr
669 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
672 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
673 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
674 SDNode OpNode, ValueType vt, Operand CC, string asm,
676 def rri : AVX512AIi8<opc, MRMSrcReg,
677 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
678 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
679 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
680 def rmi : AVX512AIi8<opc, MRMSrcMem,
681 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
682 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
683 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
684 // Accept explicit immediate argument form instead of comparison code.
685 let neverHasSideEffects = 1 in {
686 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
687 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
688 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
689 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
690 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
691 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
695 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
696 X86cmpm, v16i32, AVXCC,
697 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
699 EVEX_V512, EVEX_CD8<32, CD8VF>;
700 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
701 X86cmpmu, v16i32, AVXCC,
702 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
703 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
704 EVEX_V512, EVEX_CD8<32, CD8VF>;
706 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
707 X86cmpm, v8i64, AVXCC,
708 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
709 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
710 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
711 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
712 X86cmpmu, v8i64, AVXCC,
713 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
714 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
715 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
717 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
718 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
719 X86MemOperand x86memop, Operand CC,
720 SDNode OpNode, ValueType vt, string asm,
721 string asm_alt, Domain d> {
722 def rri : AVX512PIi8<0xC2, MRMSrcReg,
723 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
724 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
725 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
726 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
728 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
730 // Accept explicit immediate argument form instead of comparison code.
731 let neverHasSideEffects = 1 in {
732 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
733 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
735 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
736 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
741 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
742 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
743 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
744 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
745 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
746 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
747 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
748 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
751 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
752 (COPY_TO_REGCLASS (VCMPPSZrri
753 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
756 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
757 (COPY_TO_REGCLASS (VPCMPDZrri
758 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
761 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
762 (COPY_TO_REGCLASS (VPCMPUDZrri
763 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
767 // Mask register copy, including
768 // - copy between mask registers
769 // - load/store mask registers
770 // - copy from GPR to mask register and vice versa
772 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
773 string OpcodeStr, RegisterClass KRC,
774 ValueType vt, X86MemOperand x86memop> {
775 let neverHasSideEffects = 1 in {
776 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
777 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
779 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
780 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
781 [(set KRC:$dst, (vt (load addr:$src)))]>;
783 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
788 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
790 RegisterClass KRC, RegisterClass GRC> {
791 let neverHasSideEffects = 1 in {
792 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
793 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
794 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
799 let Predicates = [HasAVX512] in {
800 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
802 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
806 let Predicates = [HasAVX512] in {
807 // GR16 from/to 16-bit mask
808 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
809 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
810 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
811 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
813 // Store kreg in memory
814 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
815 (KMOVWmk addr:$dst, VK16:$src)>;
817 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
818 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
820 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
821 let Predicates = [HasAVX512] in {
822 // GR from/to 8-bit mask without native support
823 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
825 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
827 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
829 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
833 // Mask unary operation
835 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
836 RegisterClass KRC, SDPatternOperator OpNode> {
837 let Predicates = [HasAVX512] in
838 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
840 [(set KRC:$dst, (OpNode KRC:$src))]>;
843 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
844 SDPatternOperator OpNode> {
845 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
849 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
851 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
852 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
853 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
855 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
856 def : Pat<(not VK8:$src),
858 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
860 // Mask binary operation
861 // - KADD, KAND, KANDN, KOR, KXNOR, KXOR
862 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
863 RegisterClass KRC, SDPatternOperator OpNode> {
864 let Predicates = [HasAVX512] in
865 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
866 !strconcat(OpcodeStr,
867 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
868 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
871 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
872 SDPatternOperator OpNode> {
873 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
877 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
878 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
880 let isCommutable = 1 in {
881 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
882 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
883 let isCommutable = 0 in
884 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
885 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
886 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
887 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
890 multiclass avx512_mask_binop_int<string IntName, string InstName> {
891 let Predicates = [HasAVX512] in
892 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
893 VK16:$src1, VK16:$src2),
894 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
897 defm : avx512_mask_binop_int<"kadd", "KADD">;
898 defm : avx512_mask_binop_int<"kand", "KAND">;
899 defm : avx512_mask_binop_int<"kandn", "KANDN">;
900 defm : avx512_mask_binop_int<"kor", "KOR">;
901 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
902 defm : avx512_mask_binop_int<"kxor", "KXOR">;
903 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
904 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
905 let Predicates = [HasAVX512] in
906 def : Pat<(OpNode VK8:$src1, VK8:$src2),
908 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
909 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
912 defm : avx512_binop_pat<and, KANDWrr>;
913 defm : avx512_binop_pat<andn, KANDNWrr>;
914 defm : avx512_binop_pat<or, KORWrr>;
915 defm : avx512_binop_pat<xnor, KXNORWrr>;
916 defm : avx512_binop_pat<xor, KXORWrr>;
919 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
920 RegisterClass KRC1, RegisterClass KRC2> {
921 let Predicates = [HasAVX512] in
922 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
923 !strconcat(OpcodeStr,
924 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
927 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
928 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
929 VEX_4V, VEX_L, OpSize, TB;
932 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
934 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
935 let Predicates = [HasAVX512] in
936 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
937 VK8:$src1, VK8:$src2),
938 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
941 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
943 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
945 let Predicates = [HasAVX512], Defs = [EFLAGS] in
946 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
947 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
948 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
951 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
952 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
956 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
957 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
960 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
962 let Predicates = [HasAVX512] in
963 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
964 !strconcat(OpcodeStr,
965 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
966 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
969 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
971 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
972 VEX, OpSize, TA, VEX_W;
975 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
976 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
978 // Mask setting all 0s or 1s
979 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
980 let Predicates = [HasAVX512] in
981 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
982 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
983 [(set KRC:$dst, (VT Val))]>;
986 multiclass avx512_mask_setop_w<PatFrag Val> {
987 defm B : avx512_mask_setop<VK8, v8i1, Val>;
988 defm W : avx512_mask_setop<VK16, v16i1, Val>;
991 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
992 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
994 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
995 let Predicates = [HasAVX512] in {
996 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
997 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
999 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1000 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1002 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1003 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1005 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1006 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1008 //===----------------------------------------------------------------------===//
1009 // AVX-512 - Aligned and unaligned load and store
1012 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1013 X86MemOperand x86memop, PatFrag ld_frag,
1014 string asm, Domain d> {
1015 let neverHasSideEffects = 1 in
1016 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1017 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1019 let canFoldAsLoad = 1 in
1020 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1021 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1022 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1023 let Constraints = "$src1 = $dst" in {
1024 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1025 (ins RC:$src1, KRC:$mask, RC:$src2),
1027 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1029 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1032 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1033 [], d>, EVEX, EVEX_K;
1037 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1038 "vmovaps", SSEPackedSingle>,
1039 EVEX_V512, EVEX_CD8<32, CD8VF>;
1040 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1041 "vmovapd", SSEPackedDouble>,
1042 OpSize, EVEX_V512, VEX_W,
1043 EVEX_CD8<64, CD8VF>;
1044 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1045 "vmovups", SSEPackedSingle>,
1046 EVEX_V512, EVEX_CD8<32, CD8VF>;
1047 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1048 "vmovupd", SSEPackedDouble>,
1049 OpSize, EVEX_V512, VEX_W,
1050 EVEX_CD8<64, CD8VF>;
1051 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1052 "vmovaps\t{$src, $dst|$dst, $src}",
1053 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1054 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1055 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1056 "vmovapd\t{$src, $dst|$dst, $src}",
1057 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1058 SSEPackedDouble>, EVEX, EVEX_V512,
1059 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1060 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1061 "vmovups\t{$src, $dst|$dst, $src}",
1062 [(store (v16f32 VR512:$src), addr:$dst)],
1063 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1064 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1065 "vmovupd\t{$src, $dst|$dst, $src}",
1066 [(store (v8f64 VR512:$src), addr:$dst)],
1067 SSEPackedDouble>, EVEX, EVEX_V512,
1068 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1070 // Use vmovaps/vmovups for AVX-512 integer load/store.
1071 // 512-bit load/store
1072 def : Pat<(alignedloadv8i64 addr:$src),
1073 (VMOVAPSZrm addr:$src)>;
1074 def : Pat<(loadv8i64 addr:$src),
1075 (VMOVUPSZrm addr:$src)>;
1077 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1078 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1079 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1080 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1082 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1083 (VMOVUPDZmr addr:$dst, VR512:$src)>;
1084 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1085 (VMOVUPSZmr addr:$dst, VR512:$src)>;
1087 let neverHasSideEffects = 1 in {
1088 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1090 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1092 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1094 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1095 EVEX, EVEX_V512, VEX_W;
1096 let mayStore = 1 in {
1097 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1098 (ins i512mem:$dst, VR512:$src),
1099 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1100 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1101 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1102 (ins i512mem:$dst, VR512:$src),
1103 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1104 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1106 let mayLoad = 1 in {
1107 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1109 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1110 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1111 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1113 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1114 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1118 multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
1120 PatFrag ld_frag, X86MemOperand x86memop> {
1121 let neverHasSideEffects = 1 in
1122 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1123 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
1125 let canFoldAsLoad = 1 in
1126 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1127 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1128 [(set RC:$dst, (ld_frag addr:$src))]>,
1130 let Constraints = "$src1 = $dst" in {
1131 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
1132 (ins RC:$src1, KRC:$mask, RC:$src2),
1134 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1136 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
1137 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1139 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1144 defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
1145 EVEX_V512, EVEX_CD8<32, CD8VF>;
1146 defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
1147 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1149 let AddedComplexity = 20 in {
1150 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1151 (v16f32 VR512:$src2))),
1152 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1153 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1154 (v8f64 VR512:$src2))),
1155 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1156 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1157 (v16i32 VR512:$src2))),
1158 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1159 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1160 (v8i64 VR512:$src2))),
1161 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1163 // Move Int Doubleword to Packed Double Int
1165 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1166 "vmovd{z}\t{$src, $dst|$dst, $src}",
1168 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1170 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1171 "vmovd{z}\t{$src, $dst|$dst, $src}",
1173 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1174 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1175 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1176 "vmovq{z}\t{$src, $dst|$dst, $src}",
1178 (v2i64 (scalar_to_vector GR64:$src)))],
1179 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1180 let isCodeGenOnly = 1 in {
1181 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1182 "vmovq{z}\t{$src, $dst|$dst, $src}",
1183 [(set FR64:$dst, (bitconvert GR64:$src))],
1184 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1185 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1186 "vmovq{z}\t{$src, $dst|$dst, $src}",
1187 [(set GR64:$dst, (bitconvert FR64:$src))],
1188 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1190 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1191 "vmovq{z}\t{$src, $dst|$dst, $src}",
1192 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1193 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1194 EVEX_CD8<64, CD8VT1>;
1196 // Move Int Doubleword to Single Scalar
1198 let isCodeGenOnly = 1 in {
1199 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1200 "vmovd{z}\t{$src, $dst|$dst, $src}",
1201 [(set FR32X:$dst, (bitconvert GR32:$src))],
1202 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1204 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1205 "vmovd{z}\t{$src, $dst|$dst, $src}",
1206 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1210 // Move Packed Doubleword Int to Packed Double Int
1212 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1213 "vmovd{z}\t{$src, $dst|$dst, $src}",
1214 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1215 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1217 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1218 (ins i32mem:$dst, VR128X:$src),
1219 "vmovd{z}\t{$src, $dst|$dst, $src}",
1220 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1221 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1222 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1224 // Move Packed Doubleword Int first element to Doubleword Int
1226 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1227 "vmovq{z}\t{$src, $dst|$dst, $src}",
1228 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1230 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1231 Requires<[HasAVX512, In64BitMode]>;
1233 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1234 (ins i64mem:$dst, VR128X:$src),
1235 "vmovq{z}\t{$src, $dst|$dst, $src}",
1236 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1237 addr:$dst)], IIC_SSE_MOVDQ>,
1238 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1239 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1241 // Move Scalar Single to Double Int
1243 let isCodeGenOnly = 1 in {
1244 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1246 "vmovd{z}\t{$src, $dst|$dst, $src}",
1247 [(set GR32:$dst, (bitconvert FR32X:$src))],
1248 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1249 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1250 (ins i32mem:$dst, FR32X:$src),
1251 "vmovd{z}\t{$src, $dst|$dst, $src}",
1252 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1253 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1256 // Move Quadword Int to Packed Quadword Int
1258 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1260 "vmovq{z}\t{$src, $dst|$dst, $src}",
1262 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1263 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1265 //===----------------------------------------------------------------------===//
1266 // AVX-512 MOVSS, MOVSD
1267 //===----------------------------------------------------------------------===//
1269 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1270 SDNode OpNode, ValueType vt,
1271 X86MemOperand x86memop, PatFrag mem_pat> {
1272 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1273 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1274 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1275 (scalar_to_vector RC:$src2))))],
1276 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1277 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1278 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1279 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1281 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1282 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1283 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1287 let ExeDomain = SSEPackedSingle in
1288 defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1289 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1291 let ExeDomain = SSEPackedDouble in
1292 defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1293 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1296 // For the disassembler
1297 let isCodeGenOnly = 1 in {
1298 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1299 (ins VR128X:$src1, FR32X:$src2),
1300 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1302 XS, EVEX_4V, VEX_LIG;
1303 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1304 (ins VR128X:$src1, FR64X:$src2),
1305 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1307 XD, EVEX_4V, VEX_LIG, VEX_W;
1310 let Predicates = [HasAVX512] in {
1311 let AddedComplexity = 15 in {
1312 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1313 // MOVS{S,D} to the lower bits.
1314 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1315 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1316 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1317 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1318 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1319 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1320 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1321 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1323 // Move low f32 and clear high bits.
1324 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1325 (SUBREG_TO_REG (i32 0),
1326 (VMOVSSZrr (v4f32 (V_SET0)),
1327 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1328 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1329 (SUBREG_TO_REG (i32 0),
1330 (VMOVSSZrr (v4i32 (V_SET0)),
1331 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1334 let AddedComplexity = 20 in {
1335 // MOVSSrm zeros the high parts of the register; represent this
1336 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1337 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1338 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1339 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1340 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1341 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1342 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1344 // MOVSDrm zeros the high parts of the register; represent this
1345 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1346 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1347 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1348 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1349 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1350 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1351 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1352 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1353 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1354 def : Pat<(v2f64 (X86vzload addr:$src)),
1355 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1357 // Represent the same patterns above but in the form they appear for
1359 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1360 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1361 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1362 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1363 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1364 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1365 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1366 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1367 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1369 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1370 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1371 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1372 FR32X:$src)), sub_xmm)>;
1373 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1374 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1375 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1376 FR64X:$src)), sub_xmm)>;
1377 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1378 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1379 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1381 // Move low f64 and clear high bits.
1382 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1383 (SUBREG_TO_REG (i32 0),
1384 (VMOVSDZrr (v2f64 (V_SET0)),
1385 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1387 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1388 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1389 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1391 // Extract and store.
1392 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1394 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1395 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1397 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1399 // Shuffle with VMOVSS
1400 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1401 (VMOVSSZrr (v4i32 VR128X:$src1),
1402 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1403 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1404 (VMOVSSZrr (v4f32 VR128X:$src1),
1405 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1408 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1409 (SUBREG_TO_REG (i32 0),
1410 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1411 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1413 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1414 (SUBREG_TO_REG (i32 0),
1415 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1416 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1419 // Shuffle with VMOVSD
1420 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1421 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1422 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1423 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1424 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1425 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1426 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1427 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1430 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1431 (SUBREG_TO_REG (i32 0),
1432 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1433 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1435 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1436 (SUBREG_TO_REG (i32 0),
1437 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1438 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1441 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1442 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1443 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1444 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1445 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1446 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1447 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1448 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1451 let AddedComplexity = 15 in
1452 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1454 "vmovq{z}\t{$src, $dst|$dst, $src}",
1455 [(set VR128X:$dst, (v2i64 (X86vzmovl
1456 (v2i64 VR128X:$src))))],
1457 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1459 let AddedComplexity = 20 in
1460 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1462 "vmovq{z}\t{$src, $dst|$dst, $src}",
1463 [(set VR128X:$dst, (v2i64 (X86vzmovl
1464 (loadv2i64 addr:$src))))],
1465 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1466 EVEX_CD8<8, CD8VT8>;
1468 let Predicates = [HasAVX512] in {
1469 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1470 let AddedComplexity = 20 in {
1471 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1472 (VMOVDI2PDIZrm addr:$src)>;
1473 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1474 (VMOV64toPQIZrr GR64:$src)>;
1475 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1476 (VMOVDI2PDIZrr GR32:$src)>;
1478 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1479 (VMOVDI2PDIZrm addr:$src)>;
1480 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1481 (VMOVDI2PDIZrm addr:$src)>;
1482 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1483 (VMOVZPQILo2PQIZrm addr:$src)>;
1484 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1485 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1488 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1489 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1490 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1491 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1492 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1493 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1494 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1497 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1498 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1500 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1501 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1503 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1504 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1506 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1507 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1509 //===----------------------------------------------------------------------===//
1510 // AVX-512 - Integer arithmetic
1512 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1513 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1514 X86MemOperand x86memop, PatFrag scalar_mfrag,
1515 X86MemOperand x86scalar_mop, string BrdcstStr,
1516 OpndItins itins, bit IsCommutable = 0> {
1517 let isCommutable = IsCommutable in
1518 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1519 (ins RC:$src1, RC:$src2),
1520 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1521 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1523 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1524 (ins RC:$src1, x86memop:$src2),
1525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1526 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1528 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1529 (ins RC:$src1, x86scalar_mop:$src2),
1530 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1531 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1532 [(set RC:$dst, (OpNode RC:$src1,
1533 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1534 itins.rm>, EVEX_4V, EVEX_B;
1536 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1537 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1538 PatFrag memop_frag, X86MemOperand x86memop,
1540 bit IsCommutable = 0> {
1541 let isCommutable = IsCommutable in
1542 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1543 (ins RC:$src1, RC:$src2),
1544 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1545 []>, EVEX_4V, VEX_W;
1546 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1547 (ins RC:$src1, x86memop:$src2),
1548 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1549 []>, EVEX_4V, VEX_W;
1552 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1553 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1554 EVEX_V512, EVEX_CD8<32, CD8VF>;
1556 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1557 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1558 EVEX_V512, EVEX_CD8<32, CD8VF>;
1560 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1561 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1562 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1564 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1565 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1566 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1568 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1569 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1570 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1572 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1573 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1574 EVEX_V512, EVEX_CD8<64, CD8VF>;
1576 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1577 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1578 EVEX_CD8<64, CD8VF>;
1580 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1581 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1583 //===----------------------------------------------------------------------===//
1584 // AVX-512 - Unpack Instructions
1585 //===----------------------------------------------------------------------===//
1587 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1588 PatFrag mem_frag, RegisterClass RC,
1589 X86MemOperand x86memop, string asm,
1591 def rr : AVX512PI<opc, MRMSrcReg,
1592 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1594 (vt (OpNode RC:$src1, RC:$src2)))],
1596 def rm : AVX512PI<opc, MRMSrcMem,
1597 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1599 (vt (OpNode RC:$src1,
1600 (bitconvert (mem_frag addr:$src2)))))],
1604 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1605 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1606 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1607 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1608 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1609 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1610 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1611 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1612 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1613 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1614 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1615 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1617 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1618 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1619 X86MemOperand x86memop> {
1620 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1621 (ins RC:$src1, RC:$src2),
1622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1623 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1624 IIC_SSE_UNPCK>, EVEX_4V;
1625 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1626 (ins RC:$src1, x86memop:$src2),
1627 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1628 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1629 (bitconvert (memop_frag addr:$src2)))))],
1630 IIC_SSE_UNPCK>, EVEX_4V;
1632 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1633 VR512, memopv16i32, i512mem>, EVEX_V512,
1634 EVEX_CD8<32, CD8VF>;
1635 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1636 VR512, memopv8i64, i512mem>, EVEX_V512,
1637 VEX_W, EVEX_CD8<64, CD8VF>;
1638 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1639 VR512, memopv16i32, i512mem>, EVEX_V512,
1640 EVEX_CD8<32, CD8VF>;
1641 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1642 VR512, memopv8i64, i512mem>, EVEX_V512,
1643 VEX_W, EVEX_CD8<64, CD8VF>;
1644 //===----------------------------------------------------------------------===//
1648 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1649 SDNode OpNode, PatFrag mem_frag,
1650 X86MemOperand x86memop, ValueType OpVT> {
1651 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1652 (ins RC:$src1, i8imm:$src2),
1653 !strconcat(OpcodeStr,
1654 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1656 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1658 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1659 (ins x86memop:$src1, i8imm:$src2),
1660 !strconcat(OpcodeStr,
1661 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1663 (OpVT (OpNode (mem_frag addr:$src1),
1664 (i8 imm:$src2))))]>, EVEX;
1667 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1668 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1670 let ExeDomain = SSEPackedSingle in
1671 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1672 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1673 EVEX_CD8<32, CD8VF>;
1674 let ExeDomain = SSEPackedDouble in
1675 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1676 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1677 VEX_W, EVEX_CD8<32, CD8VF>;
1679 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1680 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1681 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1682 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1684 //===----------------------------------------------------------------------===//
1685 // AVX-512 Logical Instructions
1686 //===----------------------------------------------------------------------===//
1688 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1689 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1690 EVEX_V512, EVEX_CD8<32, CD8VF>;
1691 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1692 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1693 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1694 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1695 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1696 EVEX_V512, EVEX_CD8<32, CD8VF>;
1697 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1698 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1699 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1700 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1701 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1702 EVEX_V512, EVEX_CD8<32, CD8VF>;
1703 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1704 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1705 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1706 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1707 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1708 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1709 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1710 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1711 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1713 //===----------------------------------------------------------------------===//
1714 // AVX-512 FP arithmetic
1715 //===----------------------------------------------------------------------===//
1717 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1719 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1720 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1721 EVEX_CD8<32, CD8VT1>;
1722 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1723 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1724 EVEX_CD8<64, CD8VT1>;
1727 let isCommutable = 1 in {
1728 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1729 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1730 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1731 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1733 let isCommutable = 0 in {
1734 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1735 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1738 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1739 RegisterClass RC, ValueType vt,
1740 X86MemOperand x86memop, PatFrag mem_frag,
1741 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1743 Domain d, OpndItins itins, bit commutable> {
1744 let isCommutable = commutable in
1745 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1747 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1749 let mayLoad = 1 in {
1750 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1751 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1752 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1753 itins.rm, d>, EVEX_4V, TB;
1754 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1755 (ins RC:$src1, x86scalar_mop:$src2),
1756 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1757 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1758 [(set RC:$dst, (OpNode RC:$src1,
1759 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1760 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1764 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1765 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1766 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1768 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1769 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1770 SSE_ALU_ITINS_P.d, 1>,
1771 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1773 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1774 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1775 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1776 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1777 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1778 SSE_ALU_ITINS_P.d, 1>,
1779 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1781 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1782 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1783 SSE_ALU_ITINS_P.s, 1>,
1784 EVEX_V512, EVEX_CD8<32, CD8VF>;
1785 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1786 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1787 SSE_ALU_ITINS_P.s, 1>,
1788 EVEX_V512, EVEX_CD8<32, CD8VF>;
1790 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1791 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1792 SSE_ALU_ITINS_P.d, 1>,
1793 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1794 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1795 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1796 SSE_ALU_ITINS_P.d, 1>,
1797 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1799 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1800 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1801 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1802 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1803 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1804 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1806 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1807 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1808 SSE_ALU_ITINS_P.d, 0>,
1809 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1810 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1811 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1812 SSE_ALU_ITINS_P.d, 0>,
1813 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1815 //===----------------------------------------------------------------------===//
1816 // AVX-512 VPTESTM instructions
1817 //===----------------------------------------------------------------------===//
1819 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1820 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1821 SDNode OpNode, ValueType vt> {
1822 def rr : AVX5128I<opc, MRMSrcReg,
1823 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1824 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1825 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1826 def rm : AVX5128I<opc, MRMSrcMem,
1827 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1828 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1829 [(set KRC:$dst, (OpNode (vt RC:$src1),
1830 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1833 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1834 memopv16i32, X86testm, v16i32>, EVEX_V512,
1835 EVEX_CD8<32, CD8VF>;
1836 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1837 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1838 EVEX_CD8<64, CD8VF>;
1840 //===----------------------------------------------------------------------===//
1841 // AVX-512 Shift instructions
1842 //===----------------------------------------------------------------------===//
1843 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1844 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1845 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1846 RegisterClass KRC> {
1847 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1848 (ins RC:$src1, i8imm:$src2),
1849 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1850 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
1851 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1852 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1853 (ins KRC:$mask, RC:$src1, i8imm:$src2),
1854 !strconcat(OpcodeStr,
1855 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1856 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1857 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1858 (ins x86memop:$src1, i8imm:$src2),
1859 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1860 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1861 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1862 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1863 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
1864 !strconcat(OpcodeStr,
1865 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1866 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1869 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1870 RegisterClass RC, ValueType vt, ValueType SrcVT,
1871 PatFrag bc_frag, RegisterClass KRC> {
1872 // src2 is always 128-bit
1873 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1874 (ins RC:$src1, VR128X:$src2),
1875 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1876 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1877 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1878 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1879 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1880 !strconcat(OpcodeStr,
1881 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1882 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1883 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1884 (ins RC:$src1, i128mem:$src2),
1885 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1886 [(set RC:$dst, (vt (OpNode RC:$src1,
1887 (bc_frag (memopv2i64 addr:$src2)))))],
1888 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1889 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1890 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1891 !strconcat(OpcodeStr,
1892 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1893 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1896 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1897 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1898 EVEX_V512, EVEX_CD8<32, CD8VF>;
1899 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1900 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1901 EVEX_CD8<32, CD8VQ>;
1903 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1904 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1905 EVEX_CD8<64, CD8VF>, VEX_W;
1906 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1907 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1908 EVEX_CD8<64, CD8VQ>, VEX_W;
1910 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1911 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1912 EVEX_CD8<32, CD8VF>;
1913 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1914 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1915 EVEX_CD8<32, CD8VQ>;
1917 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1918 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1919 EVEX_CD8<64, CD8VF>, VEX_W;
1920 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1921 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1922 EVEX_CD8<64, CD8VQ>, VEX_W;
1924 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1925 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1926 EVEX_V512, EVEX_CD8<32, CD8VF>;
1927 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1928 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1929 EVEX_CD8<32, CD8VQ>;
1931 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1932 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1933 EVEX_CD8<64, CD8VF>, VEX_W;
1934 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1935 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1936 EVEX_CD8<64, CD8VQ>, VEX_W;
1938 //===-------------------------------------------------------------------===//
1939 // Variable Bit Shifts
1940 //===-------------------------------------------------------------------===//
1941 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1942 RegisterClass RC, ValueType vt,
1943 X86MemOperand x86memop, PatFrag mem_frag> {
1944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1945 (ins RC:$src1, RC:$src2),
1946 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1948 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1950 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1951 (ins RC:$src1, x86memop:$src2),
1952 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1954 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1958 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1959 i512mem, memopv16i32>, EVEX_V512,
1960 EVEX_CD8<32, CD8VF>;
1961 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1962 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1963 EVEX_CD8<64, CD8VF>;
1964 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1965 i512mem, memopv16i32>, EVEX_V512,
1966 EVEX_CD8<32, CD8VF>;
1967 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1968 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1969 EVEX_CD8<64, CD8VF>;
1970 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1971 i512mem, memopv16i32>, EVEX_V512,
1972 EVEX_CD8<32, CD8VF>;
1973 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1974 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1975 EVEX_CD8<64, CD8VF>;
1977 //===----------------------------------------------------------------------===//
1978 // AVX-512 - MOVDDUP
1979 //===----------------------------------------------------------------------===//
1981 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1982 X86MemOperand x86memop, PatFrag memop_frag> {
1983 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1984 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1985 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
1986 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1987 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1989 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
1992 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
1993 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1994 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
1995 (VMOVDDUPZrm addr:$src)>;
1997 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
1998 (ins VR128X:$src1, VR128X:$src2),
1999 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2000 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2001 IIC_SSE_MOV_LH>, EVEX_4V;
2002 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2003 (ins VR128X:$src1, VR128X:$src2),
2004 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2005 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2006 IIC_SSE_MOV_LH>, EVEX_4V;
2008 let Predicates = [HasAVX512] in {
2010 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2011 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2012 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2013 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2016 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2017 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2020 //===----------------------------------------------------------------------===//
2021 // FMA - Fused Multiply Operations
2023 let Constraints = "$src1 = $dst" in {
2024 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2025 RegisterClass RC, X86MemOperand x86memop,
2026 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2027 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2028 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2029 (ins RC:$src1, RC:$src2, RC:$src3),
2030 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2031 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2034 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2035 (ins RC:$src1, RC:$src2, x86memop:$src3),
2036 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2037 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2038 (mem_frag addr:$src3))))]>;
2039 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2040 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2041 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2042 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2043 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2044 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2046 } // Constraints = "$src1 = $dst"
2048 let ExeDomain = SSEPackedSingle in {
2049 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2050 memopv16f32, f32mem, loadf32, "{1to16}",
2051 X86Fmadd, v16f32>, EVEX_V512,
2052 EVEX_CD8<32, CD8VF>;
2053 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2054 memopv16f32, f32mem, loadf32, "{1to16}",
2055 X86Fmsub, v16f32>, EVEX_V512,
2056 EVEX_CD8<32, CD8VF>;
2057 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2058 memopv16f32, f32mem, loadf32, "{1to16}",
2059 X86Fmaddsub, v16f32>,
2060 EVEX_V512, EVEX_CD8<32, CD8VF>;
2061 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2062 memopv16f32, f32mem, loadf32, "{1to16}",
2063 X86Fmsubadd, v16f32>,
2064 EVEX_V512, EVEX_CD8<32, CD8VF>;
2065 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2066 memopv16f32, f32mem, loadf32, "{1to16}",
2067 X86Fnmadd, v16f32>, EVEX_V512,
2068 EVEX_CD8<32, CD8VF>;
2069 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2070 memopv16f32, f32mem, loadf32, "{1to16}",
2071 X86Fnmsub, v16f32>, EVEX_V512,
2072 EVEX_CD8<32, CD8VF>;
2074 let ExeDomain = SSEPackedDouble in {
2075 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2076 memopv8f64, f64mem, loadf64, "{1to8}",
2077 X86Fmadd, v8f64>, EVEX_V512,
2078 VEX_W, EVEX_CD8<64, CD8VF>;
2079 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2080 memopv8f64, f64mem, loadf64, "{1to8}",
2081 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2082 EVEX_CD8<64, CD8VF>;
2083 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2084 memopv8f64, f64mem, loadf64, "{1to8}",
2085 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2086 EVEX_CD8<64, CD8VF>;
2087 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2088 memopv8f64, f64mem, loadf64, "{1to8}",
2089 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2090 EVEX_CD8<64, CD8VF>;
2091 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2092 memopv8f64, f64mem, loadf64, "{1to8}",
2093 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2094 EVEX_CD8<64, CD8VF>;
2095 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2096 memopv8f64, f64mem, loadf64, "{1to8}",
2097 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2098 EVEX_CD8<64, CD8VF>;
2101 let Constraints = "$src1 = $dst" in {
2102 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2103 RegisterClass RC, X86MemOperand x86memop,
2104 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2105 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2107 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2108 (ins RC:$src1, RC:$src3, x86memop:$src2),
2109 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2110 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2111 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2112 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2113 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2114 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2115 [(set RC:$dst, (OpNode RC:$src1,
2116 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2118 } // Constraints = "$src1 = $dst"
2121 let ExeDomain = SSEPackedSingle in {
2122 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2123 memopv16f32, f32mem, loadf32, "{1to16}",
2124 X86Fmadd, v16f32>, EVEX_V512,
2125 EVEX_CD8<32, CD8VF>;
2126 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2127 memopv16f32, f32mem, loadf32, "{1to16}",
2128 X86Fmsub, v16f32>, EVEX_V512,
2129 EVEX_CD8<32, CD8VF>;
2130 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2131 memopv16f32, f32mem, loadf32, "{1to16}",
2132 X86Fmaddsub, v16f32>,
2133 EVEX_V512, EVEX_CD8<32, CD8VF>;
2134 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2135 memopv16f32, f32mem, loadf32, "{1to16}",
2136 X86Fmsubadd, v16f32>,
2137 EVEX_V512, EVEX_CD8<32, CD8VF>;
2138 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2139 memopv16f32, f32mem, loadf32, "{1to16}",
2140 X86Fnmadd, v16f32>, EVEX_V512,
2141 EVEX_CD8<32, CD8VF>;
2142 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2143 memopv16f32, f32mem, loadf32, "{1to16}",
2144 X86Fnmsub, v16f32>, EVEX_V512,
2145 EVEX_CD8<32, CD8VF>;
2147 let ExeDomain = SSEPackedDouble in {
2148 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2149 memopv8f64, f64mem, loadf64, "{1to8}",
2150 X86Fmadd, v8f64>, EVEX_V512,
2151 VEX_W, EVEX_CD8<64, CD8VF>;
2152 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2153 memopv8f64, f64mem, loadf64, "{1to8}",
2154 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2155 EVEX_CD8<64, CD8VF>;
2156 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2157 memopv8f64, f64mem, loadf64, "{1to8}",
2158 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2159 EVEX_CD8<64, CD8VF>;
2160 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2161 memopv8f64, f64mem, loadf64, "{1to8}",
2162 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2163 EVEX_CD8<64, CD8VF>;
2164 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2165 memopv8f64, f64mem, loadf64, "{1to8}",
2166 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2167 EVEX_CD8<64, CD8VF>;
2168 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2169 memopv8f64, f64mem, loadf64, "{1to8}",
2170 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2171 EVEX_CD8<64, CD8VF>;
2175 let Constraints = "$src1 = $dst" in {
2176 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2177 RegisterClass RC, ValueType OpVT,
2178 X86MemOperand x86memop, Operand memop,
2180 let isCommutable = 1 in
2181 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2182 (ins RC:$src1, RC:$src2, RC:$src3),
2183 !strconcat(OpcodeStr,
2184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2186 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2188 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2189 (ins RC:$src1, RC:$src2, f128mem:$src3),
2190 !strconcat(OpcodeStr,
2191 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2193 (OpVT (OpNode RC:$src2, RC:$src1,
2194 (mem_frag addr:$src3))))]>;
2197 } // Constraints = "$src1 = $dst"
2199 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2200 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2201 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2202 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2203 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2204 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2205 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2206 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2207 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2208 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2209 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2210 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2211 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2212 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2213 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2214 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2216 //===----------------------------------------------------------------------===//
2217 // AVX-512 Scalar convert from sign integer to float/double
2218 //===----------------------------------------------------------------------===//
2220 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2221 X86MemOperand x86memop, string asm> {
2222 let neverHasSideEffects = 1 in {
2223 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2224 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2227 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2228 (ins DstRC:$src1, x86memop:$src),
2229 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2231 } // neverHasSideEffects = 1
2233 let Predicates = [HasAVX512] in {
2234 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2235 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2236 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
2237 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2238 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2239 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2240 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
2241 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2243 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2244 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2245 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2246 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2247 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2248 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2249 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2250 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2252 def : Pat<(f32 (sint_to_fp GR32:$src)),
2253 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2254 def : Pat<(f32 (sint_to_fp GR64:$src)),
2255 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2256 def : Pat<(f64 (sint_to_fp GR32:$src)),
2257 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2258 def : Pat<(f64 (sint_to_fp GR64:$src)),
2259 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2261 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2262 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2263 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2264 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2265 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2266 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2267 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2268 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2270 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2271 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2272 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2273 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2274 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2275 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2276 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2277 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2279 def : Pat<(f32 (uint_to_fp GR32:$src)),
2280 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2281 def : Pat<(f32 (uint_to_fp GR64:$src)),
2282 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2283 def : Pat<(f64 (uint_to_fp GR32:$src)),
2284 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2285 def : Pat<(f64 (uint_to_fp GR64:$src)),
2286 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2289 //===----------------------------------------------------------------------===//
2290 // AVX-512 Scalar convert from float/double to integer
2291 //===----------------------------------------------------------------------===//
2292 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2293 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2295 let neverHasSideEffects = 1 in {
2296 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2297 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2298 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2300 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2301 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2302 } // neverHasSideEffects = 1
2304 let Predicates = [HasAVX512] in {
2305 // Convert float/double to signed/unsigned int 32/64
2306 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2307 ssmem, sse_load_f32, "cvtss2si{z}">,
2308 XS, EVEX_CD8<32, CD8VT1>;
2309 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2310 ssmem, sse_load_f32, "cvtss2si{z}">,
2311 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2312 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2313 ssmem, sse_load_f32, "cvtss2usi{z}">,
2314 XS, EVEX_CD8<32, CD8VT1>;
2315 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2316 int_x86_avx512_cvtss2usi64, ssmem,
2317 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2318 EVEX_CD8<32, CD8VT1>;
2319 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2320 sdmem, sse_load_f64, "cvtsd2si{z}">,
2321 XD, EVEX_CD8<64, CD8VT1>;
2322 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2323 sdmem, sse_load_f64, "cvtsd2si{z}">,
2324 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2325 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2326 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2327 XD, EVEX_CD8<64, CD8VT1>;
2328 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2329 int_x86_avx512_cvtsd2usi64, sdmem,
2330 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2331 EVEX_CD8<64, CD8VT1>;
2333 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2334 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2335 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2336 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2337 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2338 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2339 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2340 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2341 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2342 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2343 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2344 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2346 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2347 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2348 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2349 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2350 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2351 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2352 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2353 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2354 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2355 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2356 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2357 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2359 // Convert float/double to signed/unsigned int 32/64 with truncation
2360 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2361 ssmem, sse_load_f32, "cvttss2si{z}">,
2362 XS, EVEX_CD8<32, CD8VT1>;
2363 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2364 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2365 "cvttss2si{z}">, XS, VEX_W,
2366 EVEX_CD8<32, CD8VT1>;
2367 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2368 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2369 EVEX_CD8<64, CD8VT1>;
2370 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2371 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2372 "cvttsd2si{z}">, XD, VEX_W,
2373 EVEX_CD8<64, CD8VT1>;
2374 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2375 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2376 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2377 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2378 int_x86_avx512_cvttss2usi64, ssmem,
2379 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2380 EVEX_CD8<32, CD8VT1>;
2381 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2382 int_x86_avx512_cvttsd2usi,
2383 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2384 EVEX_CD8<64, CD8VT1>;
2385 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2386 int_x86_avx512_cvttsd2usi64, sdmem,
2387 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2388 EVEX_CD8<64, CD8VT1>;
2391 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2392 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2394 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2395 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2396 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2397 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2398 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2399 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2402 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2403 loadf32, "cvttss2si{z}">, XS,
2404 EVEX_CD8<32, CD8VT1>;
2405 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2406 loadf32, "cvttss2usi{z}">, XS,
2407 EVEX_CD8<32, CD8VT1>;
2408 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2409 loadf32, "cvttss2si{z}">, XS, VEX_W,
2410 EVEX_CD8<32, CD8VT1>;
2411 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2412 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2413 EVEX_CD8<32, CD8VT1>;
2414 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2415 loadf64, "cvttsd2si{z}">, XD,
2416 EVEX_CD8<64, CD8VT1>;
2417 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2418 loadf64, "cvttsd2usi{z}">, XD,
2419 EVEX_CD8<64, CD8VT1>;
2420 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2421 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2422 EVEX_CD8<64, CD8VT1>;
2423 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2424 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2425 EVEX_CD8<64, CD8VT1>;
2426 //===----------------------------------------------------------------------===//
2427 // AVX-512 Convert form float to double and back
2428 //===----------------------------------------------------------------------===//
2429 let neverHasSideEffects = 1 in {
2430 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2431 (ins FR32X:$src1, FR32X:$src2),
2432 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2433 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2435 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2436 (ins FR32X:$src1, f32mem:$src2),
2437 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2438 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2439 EVEX_CD8<32, CD8VT1>;
2441 // Convert scalar double to scalar single
2442 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2443 (ins FR64X:$src1, FR64X:$src2),
2444 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2445 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2447 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2448 (ins FR64X:$src1, f64mem:$src2),
2449 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2450 []>, EVEX_4V, VEX_LIG, VEX_W,
2451 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2454 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2455 Requires<[HasAVX512]>;
2456 def : Pat<(fextend (loadf32 addr:$src)),
2457 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2459 def : Pat<(extloadf32 addr:$src),
2460 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2461 Requires<[HasAVX512, OptForSize]>;
2463 def : Pat<(extloadf32 addr:$src),
2464 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2465 Requires<[HasAVX512, OptForSpeed]>;
2467 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2468 Requires<[HasAVX512]>;
2470 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2471 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2472 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2474 let neverHasSideEffects = 1 in {
2475 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2476 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2478 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2480 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2481 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2483 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2484 } // neverHasSideEffects = 1
2487 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2488 memopv8f64, f512mem, v8f32, v8f64,
2489 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2490 EVEX_CD8<64, CD8VF>;
2492 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2493 memopv4f64, f256mem, v8f64, v8f32,
2494 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2495 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2496 (VCVTPS2PDZrm addr:$src)>;
2498 //===----------------------------------------------------------------------===//
2499 // AVX-512 Vector convert from sign integer to float/double
2500 //===----------------------------------------------------------------------===//
2502 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2503 memopv8i64, i512mem, v16f32, v16i32,
2504 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2506 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2507 memopv4i64, i256mem, v8f64, v8i32,
2508 SSEPackedDouble>, EVEX_V512, XS,
2509 EVEX_CD8<32, CD8VH>;
2511 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2512 memopv16f32, f512mem, v16i32, v16f32,
2513 SSEPackedSingle>, EVEX_V512, XS,
2514 EVEX_CD8<32, CD8VF>;
2516 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2517 memopv8f64, f512mem, v8i32, v8f64,
2518 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2519 EVEX_CD8<64, CD8VF>;
2521 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2522 memopv16f32, f512mem, v16i32, v16f32,
2523 SSEPackedSingle>, EVEX_V512,
2524 EVEX_CD8<32, CD8VF>;
2526 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2527 memopv8f64, f512mem, v8i32, v8f64,
2528 SSEPackedDouble>, EVEX_V512, VEX_W,
2529 EVEX_CD8<64, CD8VF>;
2531 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2532 memopv4i64, f256mem, v8f64, v8i32,
2533 SSEPackedDouble>, EVEX_V512, XS,
2534 EVEX_CD8<32, CD8VH>;
2536 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2537 memopv16i32, f512mem, v16f32, v16i32,
2538 SSEPackedSingle>, EVEX_V512, XD,
2539 EVEX_CD8<32, CD8VF>;
2541 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2542 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2543 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2546 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2547 (VCVTDQ2PSZrr VR512:$src)>;
2548 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2549 (VCVTDQ2PSZrm addr:$src)>;
2551 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2552 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2554 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2555 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2556 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2557 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2559 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2560 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2563 let Predicates = [HasAVX512] in {
2564 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2565 (VCVTPD2PSZrm addr:$src)>;
2566 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2567 (VCVTPS2PDZrm addr:$src)>;
2570 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2571 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2572 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2573 EVEX_CD8<32, CD8VT1>;
2574 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2575 "ucomisd{z}">, TB, OpSize, EVEX,
2576 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2577 let Pattern = []<dag> in {
2578 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2579 "comiss{z}">, TB, EVEX, VEX_LIG,
2580 EVEX_CD8<32, CD8VT1>;
2581 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2582 "comisd{z}">, TB, OpSize, EVEX,
2583 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2585 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2586 load, "ucomiss">, TB, EVEX, VEX_LIG,
2587 EVEX_CD8<32, CD8VT1>;
2588 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2589 load, "ucomisd">, TB, OpSize, EVEX,
2590 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2592 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2593 load, "comiss">, TB, EVEX, VEX_LIG,
2594 EVEX_CD8<32, CD8VT1>;
2595 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2596 load, "comisd">, TB, OpSize, EVEX,
2597 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2600 /// avx512_unop_p - AVX-512 unops in packed form.
2601 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2602 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2603 !strconcat(OpcodeStr,
2604 "ps\t{$src, $dst|$dst, $src}"),
2605 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2607 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2608 !strconcat(OpcodeStr,
2609 "ps\t{$src, $dst|$dst, $src}"),
2610 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2611 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2612 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2613 !strconcat(OpcodeStr,
2614 "pd\t{$src, $dst|$dst, $src}"),
2615 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2616 EVEX, EVEX_V512, VEX_W;
2617 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2618 !strconcat(OpcodeStr,
2619 "pd\t{$src, $dst|$dst, $src}"),
2620 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2621 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2624 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2625 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2626 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2627 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2628 !strconcat(OpcodeStr,
2629 "ps\t{$src, $dst|$dst, $src}"),
2630 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2632 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2633 !strconcat(OpcodeStr,
2634 "ps\t{$src, $dst|$dst, $src}"),
2636 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2637 EVEX_V512, EVEX_CD8<32, CD8VF>;
2638 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2639 !strconcat(OpcodeStr,
2640 "pd\t{$src, $dst|$dst, $src}"),
2641 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2642 EVEX, EVEX_V512, VEX_W;
2643 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2644 !strconcat(OpcodeStr,
2645 "pd\t{$src, $dst|$dst, $src}"),
2647 (V8F64Int (memopv8f64 addr:$src)))]>,
2648 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2651 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2652 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2653 let hasSideEffects = 0 in {
2654 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2655 (ins FR32X:$src1, FR32X:$src2),
2656 !strconcat(OpcodeStr,
2657 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2659 let mayLoad = 1 in {
2660 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2661 (ins FR32X:$src1, f32mem:$src2),
2662 !strconcat(OpcodeStr,
2663 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2664 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2665 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2666 (ins VR128X:$src1, ssmem:$src2),
2667 !strconcat(OpcodeStr,
2668 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2669 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2671 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2672 (ins FR64X:$src1, FR64X:$src2),
2673 !strconcat(OpcodeStr,
2674 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2676 let mayLoad = 1 in {
2677 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2678 (ins FR64X:$src1, f64mem:$src2),
2679 !strconcat(OpcodeStr,
2680 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2681 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2682 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2683 (ins VR128X:$src1, sdmem:$src2),
2684 !strconcat(OpcodeStr,
2685 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2686 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2691 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2692 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2693 avx512_fp_unop_p_int<0x4C, "vrcp14",
2694 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2696 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2697 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2698 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2699 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2701 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2702 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2703 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2705 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2706 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2708 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2709 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2710 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2712 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2713 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2715 let AddedComplexity = 20, Predicates = [HasERI] in {
2716 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2717 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2718 avx512_fp_unop_p_int<0xCA, "vrcp28",
2719 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2721 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2722 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2723 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2724 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2727 let Predicates = [HasERI] in {
2728 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2729 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2730 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2732 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2733 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2735 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2736 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2737 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2739 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2740 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2742 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2743 Intrinsic V16F32Int, Intrinsic V8F64Int,
2744 OpndItins itins_s, OpndItins itins_d> {
2745 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2746 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2747 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2751 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2752 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2754 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2755 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2757 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2758 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2759 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2763 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2765 [(set VR512:$dst, (OpNode
2766 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2767 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2769 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2770 !strconcat(OpcodeStr,
2771 "ps\t{$src, $dst|$dst, $src}"),
2772 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2774 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2775 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2777 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2778 EVEX_V512, EVEX_CD8<32, CD8VF>;
2779 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2780 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2781 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2782 EVEX, EVEX_V512, VEX_W;
2783 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2784 !strconcat(OpcodeStr,
2785 "pd\t{$src, $dst|$dst, $src}"),
2786 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2787 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2790 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2791 Intrinsic F32Int, Intrinsic F64Int,
2792 OpndItins itins_s, OpndItins itins_d> {
2793 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2794 (ins FR32X:$src1, FR32X:$src2),
2795 !strconcat(OpcodeStr,
2796 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2797 [], itins_s.rr>, XS, EVEX_4V;
2798 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2799 (ins VR128X:$src1, VR128X:$src2),
2800 !strconcat(OpcodeStr,
2801 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2803 (F32Int VR128X:$src1, VR128X:$src2))],
2804 itins_s.rr>, XS, EVEX_4V;
2805 let mayLoad = 1 in {
2806 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2807 (ins FR32X:$src1, f32mem:$src2),
2808 !strconcat(OpcodeStr,
2809 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2810 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2811 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2812 (ins VR128X:$src1, ssmem:$src2),
2813 !strconcat(OpcodeStr,
2814 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2816 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2817 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2819 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2820 (ins FR64X:$src1, FR64X:$src2),
2821 !strconcat(OpcodeStr,
2822 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2824 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2825 (ins VR128X:$src1, VR128X:$src2),
2826 !strconcat(OpcodeStr,
2827 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2829 (F64Int VR128X:$src1, VR128X:$src2))],
2830 itins_s.rr>, XD, EVEX_4V, VEX_W;
2831 let mayLoad = 1 in {
2832 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2833 (ins FR64X:$src1, f64mem:$src2),
2834 !strconcat(OpcodeStr,
2835 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2836 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2837 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2838 (ins VR128X:$src1, sdmem:$src2),
2839 !strconcat(OpcodeStr,
2840 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2842 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2843 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2848 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2849 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2850 SSE_SQRTSS, SSE_SQRTSD>,
2851 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2852 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2853 SSE_SQRTPS, SSE_SQRTPD>;
2855 let Predicates = [HasAVX512] in {
2856 def : Pat<(f32 (fsqrt FR32X:$src)),
2857 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2858 def : Pat<(f32 (fsqrt (load addr:$src))),
2859 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2860 Requires<[OptForSize]>;
2861 def : Pat<(f64 (fsqrt FR64X:$src)),
2862 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2863 def : Pat<(f64 (fsqrt (load addr:$src))),
2864 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2865 Requires<[OptForSize]>;
2867 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2868 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2869 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2870 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2871 Requires<[OptForSize]>;
2873 def : Pat<(f32 (X86frcp FR32X:$src)),
2874 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2875 def : Pat<(f32 (X86frcp (load addr:$src))),
2876 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2877 Requires<[OptForSize]>;
2879 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2880 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2881 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2883 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2884 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2886 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
2887 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
2888 (COPY_TO_REGCLASS VR128X:$src, FR64)),
2890 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2891 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2895 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2896 X86MemOperand x86memop, RegisterClass RC,
2897 PatFrag mem_frag32, PatFrag mem_frag64,
2898 Intrinsic V4F32Int, Intrinsic V2F64Int,
2900 let ExeDomain = SSEPackedSingle in {
2901 // Intrinsic operation, reg.
2902 // Vector intrinsic operation, reg
2903 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2904 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2905 !strconcat(OpcodeStr,
2906 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2907 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2909 // Vector intrinsic operation, mem
2910 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2911 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2912 !strconcat(OpcodeStr,
2913 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2915 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2916 EVEX_CD8<32, VForm>;
2917 } // ExeDomain = SSEPackedSingle
2919 let ExeDomain = SSEPackedDouble in {
2920 // Vector intrinsic operation, reg
2921 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2922 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2923 !strconcat(OpcodeStr,
2924 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2925 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2927 // Vector intrinsic operation, mem
2928 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2929 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2930 !strconcat(OpcodeStr,
2931 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2933 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2934 EVEX_CD8<64, VForm>;
2935 } // ExeDomain = SSEPackedDouble
2938 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2942 let ExeDomain = GenericDomain in {
2944 let hasSideEffects = 0 in
2945 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2946 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2947 !strconcat(OpcodeStr,
2948 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2951 // Intrinsic operation, reg.
2952 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2953 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2954 !strconcat(OpcodeStr,
2955 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2956 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
2958 // Intrinsic operation, mem.
2959 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
2960 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
2961 !strconcat(OpcodeStr,
2962 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2963 [(set VR128X:$dst, (F32Int VR128X:$src1,
2964 sse_load_f32:$src2, imm:$src3))]>,
2965 EVEX_CD8<32, CD8VT1>;
2968 let hasSideEffects = 0 in
2969 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
2970 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
2971 !strconcat(OpcodeStr,
2972 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2975 // Intrinsic operation, reg.
2976 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
2977 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2978 !strconcat(OpcodeStr,
2979 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2980 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
2983 // Intrinsic operation, mem.
2984 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
2985 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
2986 !strconcat(OpcodeStr,
2987 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2989 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
2990 VEX_W, EVEX_CD8<64, CD8VT1>;
2991 } // ExeDomain = GenericDomain
2994 let Predicates = [HasAVX512] in {
2995 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
2996 int_x86_avx512_rndscale_ss,
2997 int_x86_avx512_rndscale_sd>, EVEX_4V;
2999 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3000 memopv16f32, memopv8f64,
3001 int_x86_avx512_rndscale_ps_512,
3002 int_x86_avx512_rndscale_pd_512, CD8VF>,
3006 def : Pat<(ffloor FR32X:$src),
3007 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3008 def : Pat<(f64 (ffloor FR64X:$src)),
3009 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3010 def : Pat<(f32 (fnearbyint FR32X:$src)),
3011 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3012 def : Pat<(f64 (fnearbyint FR64X:$src)),
3013 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3014 def : Pat<(f32 (fceil FR32X:$src)),
3015 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3016 def : Pat<(f64 (fceil FR64X:$src)),
3017 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3018 def : Pat<(f32 (frint FR32X:$src)),
3019 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3020 def : Pat<(f64 (frint FR64X:$src)),
3021 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3022 def : Pat<(f32 (ftrunc FR32X:$src)),
3023 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3024 def : Pat<(f64 (ftrunc FR64X:$src)),
3025 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3027 def : Pat<(v16f32 (ffloor VR512:$src)),
3028 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3029 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3030 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3031 def : Pat<(v16f32 (fceil VR512:$src)),
3032 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3033 def : Pat<(v16f32 (frint VR512:$src)),
3034 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3035 def : Pat<(v16f32 (ftrunc VR512:$src)),
3036 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3038 def : Pat<(v8f64 (ffloor VR512:$src)),
3039 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3040 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3041 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3042 def : Pat<(v8f64 (fceil VR512:$src)),
3043 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3044 def : Pat<(v8f64 (frint VR512:$src)),
3045 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3046 def : Pat<(v8f64 (ftrunc VR512:$src)),
3047 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3049 //-------------------------------------------------
3050 // Integer truncate and extend operations
3051 //-------------------------------------------------
3053 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3054 RegisterClass dstRC, RegisterClass srcRC,
3055 RegisterClass KRC, X86MemOperand x86memop> {
3056 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3058 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3061 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3062 (ins KRC:$mask, srcRC:$src),
3063 !strconcat(OpcodeStr,
3064 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3067 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3068 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3071 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3072 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3073 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3074 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3075 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3076 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3077 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3078 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3079 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3080 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3081 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3082 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3083 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3084 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3085 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3086 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3087 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3088 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3089 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3090 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3091 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3092 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3093 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3094 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3095 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3096 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3097 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3098 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3099 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3100 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3102 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3103 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3104 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3105 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3106 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3108 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3109 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3110 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3111 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3112 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3113 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3114 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3115 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3118 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3119 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3120 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3122 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3124 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3125 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3126 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3127 (ins x86memop:$src),
3128 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3130 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3134 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3135 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3137 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3138 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3140 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3141 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3142 EVEX_CD8<16, CD8VH>;
3143 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3144 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3145 EVEX_CD8<16, CD8VQ>;
3146 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3147 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3148 EVEX_CD8<32, CD8VH>;
3150 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3151 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3153 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3154 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3156 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3157 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3158 EVEX_CD8<16, CD8VH>;
3159 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3160 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3161 EVEX_CD8<16, CD8VQ>;
3162 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3163 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3164 EVEX_CD8<32, CD8VH>;
3166 //===----------------------------------------------------------------------===//
3167 // GATHER - SCATTER Operations
3169 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3170 RegisterClass RC, X86MemOperand memop> {
3172 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3173 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3174 (ins RC:$src1, KRC:$mask, memop:$src2),
3175 !strconcat(OpcodeStr,
3176 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3179 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3180 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3181 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3182 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3184 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3185 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3186 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3187 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3189 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3190 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3191 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3192 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3194 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3195 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3196 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3197 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3199 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3200 RegisterClass RC, X86MemOperand memop> {
3201 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3202 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3203 (ins memop:$dst, KRC:$mask, RC:$src2),
3204 !strconcat(OpcodeStr,
3205 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3209 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3210 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3211 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3212 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3214 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3215 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3216 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3217 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3219 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3220 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3221 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3222 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3224 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3225 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3226 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3227 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3229 //===----------------------------------------------------------------------===//
3230 // VSHUFPS - VSHUFPD Operations
3232 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3233 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3235 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3236 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3237 !strconcat(OpcodeStr,
3238 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3239 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3240 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3241 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3242 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3243 (ins RC:$src1, RC:$src2, i8imm:$src3),
3244 !strconcat(OpcodeStr,
3245 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3246 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3247 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3248 EVEX_4V, Sched<[WriteShuffle]>;
3251 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3252 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3253 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3254 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3256 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3257 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3258 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3259 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3260 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3262 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3263 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3264 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3265 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3266 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3268 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3269 X86MemOperand x86memop> {
3270 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3271 (ins RC:$src1, RC:$src2, i8imm:$src3),
3272 !strconcat(OpcodeStr,
3273 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3275 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3276 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3277 !strconcat(OpcodeStr,
3278 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3281 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3282 EVEX_V512, EVEX_CD8<32, CD8VF>;
3283 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3284 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3286 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3287 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3288 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3289 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3290 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3291 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3292 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3293 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3295 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3296 X86MemOperand x86memop> {
3297 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3298 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3300 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3301 (ins x86memop:$src),
3302 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3306 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3307 EVEX_CD8<32, CD8VF>;
3308 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3309 EVEX_CD8<64, CD8VF>;