1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printlea64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions.
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, X86mul_imm, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
46 def i64immSExt8 : PatLeaf<(i64 imm), [{
47 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
48 // sign extended field.
49 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
52 def i64immSExt32 : PatLeaf<(i64 imm), [{
53 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // sign extended field.
55 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
58 def i64immZExt32 : PatLeaf<(i64 imm), [{
59 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
60 // unsignedsign extended field.
61 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
64 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
65 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
66 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
68 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
69 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
70 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
71 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
73 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
74 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
75 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
76 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
78 //===----------------------------------------------------------------------===//
79 // Instruction list...
82 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
83 // a stack adjustment and the codegen must know that they may modify the stack
84 // pointer before prolog-epilog rewriting occurs.
85 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
86 // sub / add which can clobber EFLAGS.
87 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
90 [(X86callseq_start timm:$amt)]>,
91 Requires<[In64BitMode]>;
92 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
94 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
95 Requires<[In64BitMode]>;
98 //===----------------------------------------------------------------------===//
99 // Call Instructions...
102 // All calls clobber the non-callee saved registers. RSP is marked as
103 // a use to prevent stack-pointer assignments that appear immediately
104 // before calls from potentially appearing dead. Uses for argument
105 // registers are added manually.
106 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
107 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
108 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
109 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
110 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
113 // NOTE: this pattern doesn't match "X86call imm", because we do not know
114 // that the offset between an arbitrary immediate and the call will fit in
115 // the 32-bit pcrel field that we have.
116 def CALL64pcrel32 : I<0xE8, RawFrm,
117 (outs), (ins i64i32imm:$dst, variable_ops),
118 "call\t${dst:call}", []>,
119 Requires<[In64BitMode]>;
120 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
121 "call\t{*}$dst", [(X86call GR64:$dst)]>;
122 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
123 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>;
128 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
129 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
131 "#TC_RETURN $dst $offset",
134 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
135 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
137 "#TC_RETURN $dst $offset",
141 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
142 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
143 "jmp{q}\t{*}$dst # TAILCALL",
147 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
148 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
149 [(brind GR64:$dst)]>;
150 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
151 [(brind (loadi64 addr:$dst))]>;
154 //===----------------------------------------------------------------------===//
155 // EH Pseudo Instructions
157 let isTerminator = 1, isReturn = 1, isBarrier = 1,
159 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
160 "ret\t#eh_return, addr: $addr",
161 [(X86ehret GR64:$addr)]>;
165 //===----------------------------------------------------------------------===//
166 // Miscellaneous Instructions...
168 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
169 def LEAVE64 : I<0xC9, RawFrm,
170 (outs), (ins), "leave", []>;
171 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
173 def POP64r : I<0x58, AddRegFrm,
174 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
176 def PUSH64r : I<0x50, AddRegFrm,
177 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
180 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
181 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
182 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
183 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
185 def LEA64_32r : I<0x8D, MRMSrcMem,
186 (outs GR32:$dst), (ins lea64_32mem:$src),
187 "lea{l}\t{$src|$dst}, {$dst|$src}",
188 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
190 let isReMaterializable = 1 in
191 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
192 "lea{q}\t{$src|$dst}, {$dst|$src}",
193 [(set GR64:$dst, lea64addr:$src)]>;
195 let isTwoAddress = 1 in
196 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
198 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
200 // Bit scan instructions.
201 let Defs = [EFLAGS] in {
202 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
203 "bsf{q}\t{$src, $dst|$dst, $src}",
204 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
205 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
206 "bsf{q}\t{$src, $dst|$dst, $src}",
207 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
208 (implicit EFLAGS)]>, TB;
210 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
211 "bsr{q}\t{$src, $dst|$dst, $src}",
212 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
213 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
214 "bsr{q}\t{$src, $dst|$dst, $src}",
215 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
216 (implicit EFLAGS)]>, TB;
220 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
221 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
222 [(X86rep_movs i64)]>, REP;
223 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
224 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
225 [(X86rep_stos i64)]>, REP;
227 //===----------------------------------------------------------------------===//
228 // Move Instructions...
231 let neverHasSideEffects = 1 in
232 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
233 "mov{q}\t{$src, $dst|$dst, $src}", []>;
235 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
236 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
237 "movabs{q}\t{$src, $dst|$dst, $src}",
238 [(set GR64:$dst, imm:$src)]>;
239 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
240 "mov{q}\t{$src, $dst|$dst, $src}",
241 [(set GR64:$dst, i64immSExt32:$src)]>;
244 let canFoldAsLoad = 1 in
245 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
246 "mov{q}\t{$src, $dst|$dst, $src}",
247 [(set GR64:$dst, (load addr:$src))]>;
249 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
250 "mov{q}\t{$src, $dst|$dst, $src}",
251 [(store GR64:$src, addr:$dst)]>;
252 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
253 "mov{q}\t{$src, $dst|$dst, $src}",
254 [(store i64immSExt32:$src, addr:$dst)]>;
256 // Sign/Zero extenders
258 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
259 // operand, which makes it a rare instruction with an 8-bit register
260 // operand that can never access an h register. If support for h registers
261 // were generalized, this would require a special register class.
262 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
263 "movs{bq|x}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (sext GR8:$src))]>, TB;
265 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
266 "movs{bq|x}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
268 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
269 "movs{wq|x}\t{$src, $dst|$dst, $src}",
270 [(set GR64:$dst, (sext GR16:$src))]>, TB;
271 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
272 "movs{wq|x}\t{$src, $dst|$dst, $src}",
273 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
274 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
275 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
276 [(set GR64:$dst, (sext GR32:$src))]>;
277 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
278 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
279 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
281 // Use movzbl instead of movzbq when the destination is a register; it's
282 // equivalent due to implicit zero-extending, and it has a smaller encoding.
283 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
284 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
285 [(set GR64:$dst, (zext GR8:$src))]>, TB;
286 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
287 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
288 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
289 // Use movzwl instead of movzwq when the destination is a register; it's
290 // equivalent due to implicit zero-extending, and it has a smaller encoding.
291 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
292 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
293 [(set GR64:$dst, (zext GR16:$src))]>, TB;
294 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
295 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
296 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
298 // There's no movzlq instruction, but movl can be used for this purpose, using
299 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
300 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
301 // zero-extension, however this isn't possible when the 32-bit value is
302 // defined by a truncate or is copied from something where the high bits aren't
303 // necessarily all zero. In such cases, we fall back to these explicit zext
305 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
306 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
307 [(set GR64:$dst, (zext GR32:$src))]>;
308 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
309 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
310 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
312 // Any instruction that defines a 32-bit result leaves the high half of the
313 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
314 // be copying from a truncate, but any other 32-bit operation will zero-extend
316 def def32 : PatLeaf<(i32 GR32:$src), [{
317 return N->getOpcode() != ISD::TRUNCATE &&
318 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
319 N->getOpcode() != ISD::CopyFromReg;
322 // In the case of a 32-bit def that is known to implicitly zero-extend,
323 // we can use a SUBREG_TO_REG.
324 def : Pat<(i64 (zext def32:$src)),
325 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
327 let neverHasSideEffects = 1 in {
328 let Defs = [RAX], Uses = [EAX] in
329 def CDQE : RI<0x98, RawFrm, (outs), (ins),
330 "{cltq|cdqe}", []>; // RAX = signext(EAX)
332 let Defs = [RAX,RDX], Uses = [RAX] in
333 def CQO : RI<0x99, RawFrm, (outs), (ins),
334 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
337 //===----------------------------------------------------------------------===//
338 // Arithmetic Instructions...
341 let Defs = [EFLAGS] in {
342 let isTwoAddress = 1 in {
343 let isConvertibleToThreeAddress = 1 in {
344 let isCommutable = 1 in
345 // Register-Register Addition
346 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
347 "add{q}\t{$src2, $dst|$dst, $src2}",
348 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
351 // Register-Integer Addition
352 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
353 "add{q}\t{$src2, $dst|$dst, $src2}",
354 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
356 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
357 "add{q}\t{$src2, $dst|$dst, $src2}",
358 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
360 } // isConvertibleToThreeAddress
362 // Register-Memory Addition
363 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
364 "add{q}\t{$src2, $dst|$dst, $src2}",
365 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
369 // Memory-Register Addition
370 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
371 "add{q}\t{$src2, $dst|$dst, $src2}",
372 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
374 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
375 "add{q}\t{$src2, $dst|$dst, $src2}",
376 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
378 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
379 "add{q}\t{$src2, $dst|$dst, $src2}",
380 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
383 let Uses = [EFLAGS] in {
384 let isTwoAddress = 1 in {
385 let isCommutable = 1 in
386 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
387 "adc{q}\t{$src2, $dst|$dst, $src2}",
388 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
390 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
391 "adc{q}\t{$src2, $dst|$dst, $src2}",
392 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
394 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
395 "adc{q}\t{$src2, $dst|$dst, $src2}",
396 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
397 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
398 "adc{q}\t{$src2, $dst|$dst, $src2}",
399 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
402 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
403 "adc{q}\t{$src2, $dst|$dst, $src2}",
404 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
405 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
406 "adc{q}\t{$src2, $dst|$dst, $src2}",
407 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
408 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
409 "adc{q}\t{$src2, $dst|$dst, $src2}",
410 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
413 let isTwoAddress = 1 in {
414 // Register-Register Subtraction
415 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
416 "sub{q}\t{$src2, $dst|$dst, $src2}",
417 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
420 // Register-Memory Subtraction
421 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
422 "sub{q}\t{$src2, $dst|$dst, $src2}",
423 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
426 // Register-Integer Subtraction
427 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
428 (ins GR64:$src1, i64i8imm:$src2),
429 "sub{q}\t{$src2, $dst|$dst, $src2}",
430 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
432 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
433 (ins GR64:$src1, i64i32imm:$src2),
434 "sub{q}\t{$src2, $dst|$dst, $src2}",
435 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
439 // Memory-Register Subtraction
440 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
441 "sub{q}\t{$src2, $dst|$dst, $src2}",
442 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
445 // Memory-Integer Subtraction
446 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
447 "sub{q}\t{$src2, $dst|$dst, $src2}",
448 [(store (sub (load addr:$dst), i64immSExt8:$src2),
451 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
452 "sub{q}\t{$src2, $dst|$dst, $src2}",
453 [(store (sub (load addr:$dst), i64immSExt32:$src2),
457 let Uses = [EFLAGS] in {
458 let isTwoAddress = 1 in {
459 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
460 "sbb{q}\t{$src2, $dst|$dst, $src2}",
461 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
463 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
464 "sbb{q}\t{$src2, $dst|$dst, $src2}",
465 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
467 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
468 "sbb{q}\t{$src2, $dst|$dst, $src2}",
469 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
470 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
471 "sbb{q}\t{$src2, $dst|$dst, $src2}",
472 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
475 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
476 "sbb{q}\t{$src2, $dst|$dst, $src2}",
477 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
478 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
479 "sbb{q}\t{$src2, $dst|$dst, $src2}",
480 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
481 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
482 "sbb{q}\t{$src2, $dst|$dst, $src2}",
483 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
487 // Unsigned multiplication
488 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
489 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
490 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
492 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
493 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
495 // Signed multiplication
496 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
497 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
499 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
500 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
503 let Defs = [EFLAGS] in {
504 let isTwoAddress = 1 in {
505 let isCommutable = 1 in
506 // Register-Register Signed Integer Multiplication
507 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
508 (ins GR64:$src1, GR64:$src2),
509 "imul{q}\t{$src2, $dst|$dst, $src2}",
510 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
511 (implicit EFLAGS)]>, TB;
513 // Register-Memory Signed Integer Multiplication
514 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
515 (ins GR64:$src1, i64mem:$src2),
516 "imul{q}\t{$src2, $dst|$dst, $src2}",
517 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
518 (implicit EFLAGS)]>, TB;
521 // Suprisingly enough, these are not two address instructions!
523 // Register-Integer Signed Integer Multiplication
524 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
525 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
526 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
527 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
529 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
530 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
531 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
532 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
535 // Memory-Integer Signed Integer Multiplication
536 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
537 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
538 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
539 [(set GR64:$dst, (mul (load addr:$src1),
542 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
543 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
544 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
545 [(set GR64:$dst, (mul (load addr:$src1),
546 i64immSExt32:$src2)),
550 // Unsigned division / remainder
551 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
552 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
554 // Signed division / remainder
555 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
556 "idiv{q}\t$src", []>;
558 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
560 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
561 "idiv{q}\t$src", []>;
565 // Unary instructions
566 let Defs = [EFLAGS], CodeSize = 2 in {
567 let isTwoAddress = 1 in
568 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
569 [(set GR64:$dst, (ineg GR64:$src)),
571 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
572 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
575 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
576 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
577 [(set GR64:$dst, (add GR64:$src, 1)),
579 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
580 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
583 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
584 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
585 [(set GR64:$dst, (add GR64:$src, -1)),
587 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
588 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
591 // In 64-bit mode, single byte INC and DEC cannot be encoded.
592 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
593 // Can transform into LEA.
594 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
595 [(set GR16:$dst, (add GR16:$src, 1)),
597 OpSize, Requires<[In64BitMode]>;
598 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
599 [(set GR32:$dst, (add GR32:$src, 1)),
601 Requires<[In64BitMode]>;
602 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
603 [(set GR16:$dst, (add GR16:$src, -1)),
605 OpSize, Requires<[In64BitMode]>;
606 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
607 [(set GR32:$dst, (add GR32:$src, -1)),
609 Requires<[In64BitMode]>;
610 } // isConvertibleToThreeAddress
612 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
613 // how to unfold them.
614 let isTwoAddress = 0, CodeSize = 2 in {
615 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
616 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
618 OpSize, Requires<[In64BitMode]>;
619 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
620 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
622 Requires<[In64BitMode]>;
623 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
624 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
626 OpSize, Requires<[In64BitMode]>;
627 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
628 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
630 Requires<[In64BitMode]>;
632 } // Defs = [EFLAGS], CodeSize
635 let Defs = [EFLAGS] in {
636 // Shift instructions
637 let isTwoAddress = 1 in {
639 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
640 "shl{q}\t{%cl, $dst|$dst, %CL}",
641 [(set GR64:$dst, (shl GR64:$src, CL))]>;
642 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
643 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
644 "shl{q}\t{$src2, $dst|$dst, $src2}",
645 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
646 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
651 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
652 "shl{q}\t{%cl, $dst|$dst, %CL}",
653 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
654 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
655 "shl{q}\t{$src, $dst|$dst, $src}",
656 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
657 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
659 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
661 let isTwoAddress = 1 in {
663 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
664 "shr{q}\t{%cl, $dst|$dst, %CL}",
665 [(set GR64:$dst, (srl GR64:$src, CL))]>;
666 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
667 "shr{q}\t{$src2, $dst|$dst, $src2}",
668 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
669 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
671 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
675 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
676 "shr{q}\t{%cl, $dst|$dst, %CL}",
677 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
678 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
679 "shr{q}\t{$src, $dst|$dst, $src}",
680 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
681 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
683 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
685 let isTwoAddress = 1 in {
687 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
688 "sar{q}\t{%cl, $dst|$dst, %CL}",
689 [(set GR64:$dst, (sra GR64:$src, CL))]>;
690 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
691 "sar{q}\t{$src2, $dst|$dst, $src2}",
692 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
693 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
695 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
699 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
700 "sar{q}\t{%cl, $dst|$dst, %CL}",
701 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
702 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
703 "sar{q}\t{$src, $dst|$dst, $src}",
704 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
705 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
707 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
709 // Rotate instructions
710 let isTwoAddress = 1 in {
712 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
713 "rol{q}\t{%cl, $dst|$dst, %CL}",
714 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
715 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
716 "rol{q}\t{$src2, $dst|$dst, $src2}",
717 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
718 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
720 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
724 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
725 "rol{q}\t{%cl, $dst|$dst, %CL}",
726 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
727 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
728 "rol{q}\t{$src, $dst|$dst, $src}",
729 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
730 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
732 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
734 let isTwoAddress = 1 in {
736 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
737 "ror{q}\t{%cl, $dst|$dst, %CL}",
738 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
739 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
740 "ror{q}\t{$src2, $dst|$dst, $src2}",
741 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
742 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
744 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
748 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
749 "ror{q}\t{%cl, $dst|$dst, %CL}",
750 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
751 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
752 "ror{q}\t{$src, $dst|$dst, $src}",
753 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
754 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
756 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
758 // Double shift instructions (generalizations of rotate)
759 let isTwoAddress = 1 in {
761 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
762 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
763 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
764 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
765 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
766 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
769 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
770 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
771 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
772 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
773 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
776 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
777 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
778 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
779 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
786 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
787 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
788 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
790 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
791 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
792 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
795 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
796 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
797 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
798 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
799 (i8 imm:$src3)), addr:$dst)]>,
801 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
802 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
803 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
804 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
805 (i8 imm:$src3)), addr:$dst)]>,
809 //===----------------------------------------------------------------------===//
810 // Logical Instructions...
813 let isTwoAddress = 1 , AddedComplexity = 15 in
814 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
815 [(set GR64:$dst, (not GR64:$src))]>;
816 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
817 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
819 let Defs = [EFLAGS] in {
820 let isTwoAddress = 1 in {
821 let isCommutable = 1 in
822 def AND64rr : RI<0x21, MRMDestReg,
823 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
824 "and{q}\t{$src2, $dst|$dst, $src2}",
825 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
827 def AND64rm : RI<0x23, MRMSrcMem,
828 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
829 "and{q}\t{$src2, $dst|$dst, $src2}",
830 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
832 def AND64ri8 : RIi8<0x83, MRM4r,
833 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
834 "and{q}\t{$src2, $dst|$dst, $src2}",
835 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
837 def AND64ri32 : RIi32<0x81, MRM4r,
838 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
839 "and{q}\t{$src2, $dst|$dst, $src2}",
840 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
844 def AND64mr : RI<0x21, MRMDestMem,
845 (outs), (ins i64mem:$dst, GR64:$src),
846 "and{q}\t{$src, $dst|$dst, $src}",
847 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
849 def AND64mi8 : RIi8<0x83, MRM4m,
850 (outs), (ins i64mem:$dst, i64i8imm :$src),
851 "and{q}\t{$src, $dst|$dst, $src}",
852 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
854 def AND64mi32 : RIi32<0x81, MRM4m,
855 (outs), (ins i64mem:$dst, i64i32imm:$src),
856 "and{q}\t{$src, $dst|$dst, $src}",
857 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
860 let isTwoAddress = 1 in {
861 let isCommutable = 1 in
862 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
863 "or{q}\t{$src2, $dst|$dst, $src2}",
864 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
866 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
867 "or{q}\t{$src2, $dst|$dst, $src2}",
868 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
870 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
871 "or{q}\t{$src2, $dst|$dst, $src2}",
872 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
874 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
875 "or{q}\t{$src2, $dst|$dst, $src2}",
876 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
880 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
881 "or{q}\t{$src, $dst|$dst, $src}",
882 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
884 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
885 "or{q}\t{$src, $dst|$dst, $src}",
886 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
888 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
889 "or{q}\t{$src, $dst|$dst, $src}",
890 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
893 let isTwoAddress = 1 in {
894 let isCommutable = 1 in
895 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
896 "xor{q}\t{$src2, $dst|$dst, $src2}",
897 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
899 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
900 "xor{q}\t{$src2, $dst|$dst, $src2}",
901 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
903 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
904 "xor{q}\t{$src2, $dst|$dst, $src2}",
905 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
907 def XOR64ri32 : RIi32<0x81, MRM6r,
908 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
909 "xor{q}\t{$src2, $dst|$dst, $src2}",
910 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
914 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
915 "xor{q}\t{$src, $dst|$dst, $src}",
916 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
918 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
919 "xor{q}\t{$src, $dst|$dst, $src}",
920 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
922 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
923 "xor{q}\t{$src, $dst|$dst, $src}",
924 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
928 //===----------------------------------------------------------------------===//
929 // Comparison Instructions...
932 // Integer comparison
933 let Defs = [EFLAGS] in {
934 let isCommutable = 1 in
935 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
936 "test{q}\t{$src2, $src1|$src1, $src2}",
937 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
939 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
940 "test{q}\t{$src2, $src1|$src1, $src2}",
941 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
943 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
944 (ins GR64:$src1, i64i32imm:$src2),
945 "test{q}\t{$src2, $src1|$src1, $src2}",
946 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
948 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
949 (ins i64mem:$src1, i64i32imm:$src2),
950 "test{q}\t{$src2, $src1|$src1, $src2}",
951 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
954 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
955 "cmp{q}\t{$src2, $src1|$src1, $src2}",
956 [(X86cmp GR64:$src1, GR64:$src2),
958 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
959 "cmp{q}\t{$src2, $src1|$src1, $src2}",
960 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
962 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
963 "cmp{q}\t{$src2, $src1|$src1, $src2}",
964 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
966 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
967 "cmp{q}\t{$src2, $src1|$src1, $src2}",
968 [(X86cmp GR64:$src1, i64immSExt8:$src2),
970 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
971 "cmp{q}\t{$src2, $src1|$src1, $src2}",
972 [(X86cmp GR64:$src1, i64immSExt32:$src2),
974 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
975 "cmp{q}\t{$src2, $src1|$src1, $src2}",
976 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
978 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
979 (ins i64mem:$src1, i64i32imm:$src2),
980 "cmp{q}\t{$src2, $src1|$src1, $src2}",
981 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
986 // TODO: BTC, BTR, and BTS
987 let Defs = [EFLAGS] in {
988 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
989 "bt{q}\t{$src2, $src1|$src1, $src2}",
990 [(X86bt GR64:$src1, GR64:$src2),
991 (implicit EFLAGS)]>, TB;
993 // Unlike with the register+register form, the memory+register form of the
994 // bt instruction does not ignore the high bits of the index. From ISel's
995 // perspective, this is pretty bizarre. Disable these instructions for now.
996 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
997 // "bt{q}\t{$src2, $src1|$src1, $src2}",
998 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
999 // (implicit EFLAGS)]>, TB;
1001 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1002 "bt{q}\t{$src2, $src1|$src1, $src2}",
1003 [(X86bt GR64:$src1, i64immSExt8:$src2),
1004 (implicit EFLAGS)]>, TB;
1005 // Note that these instructions don't need FastBTMem because that
1006 // only applies when the other operand is in a register. When it's
1007 // an immediate, bt is still fast.
1008 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1009 "bt{q}\t{$src2, $src1|$src1, $src2}",
1010 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1011 (implicit EFLAGS)]>, TB;
1012 } // Defs = [EFLAGS]
1014 // Conditional moves
1015 let Uses = [EFLAGS], isTwoAddress = 1 in {
1016 let isCommutable = 1 in {
1017 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1018 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1019 "cmovb\t{$src2, $dst|$dst, $src2}",
1020 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1021 X86_COND_B, EFLAGS))]>, TB;
1022 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1023 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1024 "cmovae\t{$src2, $dst|$dst, $src2}",
1025 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1026 X86_COND_AE, EFLAGS))]>, TB;
1027 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1028 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1029 "cmove\t{$src2, $dst|$dst, $src2}",
1030 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1031 X86_COND_E, EFLAGS))]>, TB;
1032 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1033 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1034 "cmovne\t{$src2, $dst|$dst, $src2}",
1035 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1036 X86_COND_NE, EFLAGS))]>, TB;
1037 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1038 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1039 "cmovbe\t{$src2, $dst|$dst, $src2}",
1040 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1041 X86_COND_BE, EFLAGS))]>, TB;
1042 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1043 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1044 "cmova\t{$src2, $dst|$dst, $src2}",
1045 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1046 X86_COND_A, EFLAGS))]>, TB;
1047 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1048 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1049 "cmovl\t{$src2, $dst|$dst, $src2}",
1050 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1051 X86_COND_L, EFLAGS))]>, TB;
1052 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1053 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1054 "cmovge\t{$src2, $dst|$dst, $src2}",
1055 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1056 X86_COND_GE, EFLAGS))]>, TB;
1057 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1058 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1059 "cmovle\t{$src2, $dst|$dst, $src2}",
1060 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1061 X86_COND_LE, EFLAGS))]>, TB;
1062 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1063 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1064 "cmovg\t{$src2, $dst|$dst, $src2}",
1065 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1066 X86_COND_G, EFLAGS))]>, TB;
1067 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1068 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1069 "cmovs\t{$src2, $dst|$dst, $src2}",
1070 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1071 X86_COND_S, EFLAGS))]>, TB;
1072 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1073 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1074 "cmovns\t{$src2, $dst|$dst, $src2}",
1075 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1076 X86_COND_NS, EFLAGS))]>, TB;
1077 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1078 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1079 "cmovp\t{$src2, $dst|$dst, $src2}",
1080 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1081 X86_COND_P, EFLAGS))]>, TB;
1082 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1083 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1084 "cmovnp\t{$src2, $dst|$dst, $src2}",
1085 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1086 X86_COND_NP, EFLAGS))]>, TB;
1087 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1088 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1089 "cmovo\t{$src2, $dst|$dst, $src2}",
1090 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1091 X86_COND_O, EFLAGS))]>, TB;
1092 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1093 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1094 "cmovno\t{$src2, $dst|$dst, $src2}",
1095 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1096 X86_COND_NO, EFLAGS))]>, TB;
1097 } // isCommutable = 1
1099 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1100 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1101 "cmovb\t{$src2, $dst|$dst, $src2}",
1102 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1103 X86_COND_B, EFLAGS))]>, TB;
1104 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1105 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1106 "cmovae\t{$src2, $dst|$dst, $src2}",
1107 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1108 X86_COND_AE, EFLAGS))]>, TB;
1109 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1110 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1111 "cmove\t{$src2, $dst|$dst, $src2}",
1112 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1113 X86_COND_E, EFLAGS))]>, TB;
1114 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1115 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1116 "cmovne\t{$src2, $dst|$dst, $src2}",
1117 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1118 X86_COND_NE, EFLAGS))]>, TB;
1119 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1120 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1121 "cmovbe\t{$src2, $dst|$dst, $src2}",
1122 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1123 X86_COND_BE, EFLAGS))]>, TB;
1124 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1125 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1126 "cmova\t{$src2, $dst|$dst, $src2}",
1127 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1128 X86_COND_A, EFLAGS))]>, TB;
1129 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1130 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1131 "cmovl\t{$src2, $dst|$dst, $src2}",
1132 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1133 X86_COND_L, EFLAGS))]>, TB;
1134 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1135 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1136 "cmovge\t{$src2, $dst|$dst, $src2}",
1137 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1138 X86_COND_GE, EFLAGS))]>, TB;
1139 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1140 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1141 "cmovle\t{$src2, $dst|$dst, $src2}",
1142 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1143 X86_COND_LE, EFLAGS))]>, TB;
1144 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1145 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1146 "cmovg\t{$src2, $dst|$dst, $src2}",
1147 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1148 X86_COND_G, EFLAGS))]>, TB;
1149 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1150 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1151 "cmovs\t{$src2, $dst|$dst, $src2}",
1152 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1153 X86_COND_S, EFLAGS))]>, TB;
1154 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1155 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1156 "cmovns\t{$src2, $dst|$dst, $src2}",
1157 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1158 X86_COND_NS, EFLAGS))]>, TB;
1159 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1160 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1161 "cmovp\t{$src2, $dst|$dst, $src2}",
1162 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1163 X86_COND_P, EFLAGS))]>, TB;
1164 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1165 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1166 "cmovnp\t{$src2, $dst|$dst, $src2}",
1167 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1168 X86_COND_NP, EFLAGS))]>, TB;
1169 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1170 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1171 "cmovo\t{$src2, $dst|$dst, $src2}",
1172 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1173 X86_COND_O, EFLAGS))]>, TB;
1174 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1175 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1176 "cmovno\t{$src2, $dst|$dst, $src2}",
1177 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1178 X86_COND_NO, EFLAGS))]>, TB;
1181 //===----------------------------------------------------------------------===//
1182 // Conversion Instructions...
1185 // f64 -> signed i64
1186 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1187 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1189 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1190 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1191 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1192 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1193 (load addr:$src)))]>;
1194 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1195 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1196 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1197 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1198 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1199 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1200 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1201 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1203 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1204 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1205 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1207 (int_x86_sse2_cvttsd2si64
1208 (load addr:$src)))]>;
1210 // Signed i64 -> f64
1211 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1212 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1213 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1214 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1215 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1216 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1218 let isTwoAddress = 1 in {
1219 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1220 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1221 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1223 (int_x86_sse2_cvtsi642sd VR128:$src1,
1225 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1226 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1227 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1229 (int_x86_sse2_cvtsi642sd VR128:$src1,
1230 (loadi64 addr:$src2)))]>;
1233 // Signed i64 -> f32
1234 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1235 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1236 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1237 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1238 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1239 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1241 let isTwoAddress = 1 in {
1242 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1243 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1244 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1246 (int_x86_sse_cvtsi642ss VR128:$src1,
1248 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1249 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1250 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1252 (int_x86_sse_cvtsi642ss VR128:$src1,
1253 (loadi64 addr:$src2)))]>;
1256 // f32 -> signed i64
1257 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1258 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1260 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1261 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1262 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1263 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1264 (load addr:$src)))]>;
1265 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1266 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1267 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1268 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1269 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1270 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1271 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1272 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1274 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1275 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1276 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1278 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1280 //===----------------------------------------------------------------------===//
1281 // Alias Instructions
1282 //===----------------------------------------------------------------------===//
1284 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1285 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1287 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1288 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1289 // when we have a better way to specify isel priority.
1290 let Defs = [EFLAGS], AddedComplexity = 1,
1291 isReMaterializable = 1, isAsCheapAsAMove = 1 in
1292 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1293 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1294 [(set GR64:$dst, 0)]>;
1296 // Materialize i64 constant where top 32-bits are zero.
1297 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1298 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1299 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1300 [(set GR64:$dst, i64immZExt32:$src)]>;
1302 //===----------------------------------------------------------------------===//
1303 // Thread Local Storage Instructions
1304 //===----------------------------------------------------------------------===//
1306 let hasSideEffects = 1, Defs = [RDI] in
1307 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64imm:$sym),
1308 ".byte\t0x66; leaq\t${sym:mem}(%rip), %rdi; .word\t0x6666; rex64",
1309 [(X86tlsaddr tglobaltlsaddr:$sym)]>,
1310 Requires<[In64BitMode]>;
1312 let AddedComplexity = 5 in
1313 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1314 "movq\t%gs:$src, $dst",
1315 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1317 //===----------------------------------------------------------------------===//
1318 // Atomic Instructions
1319 //===----------------------------------------------------------------------===//
1321 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1322 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1323 "lock\n\tcmpxchgq\t$swap,$ptr",
1324 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1327 let Constraints = "$val = $dst" in {
1328 let Defs = [EFLAGS] in
1329 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1330 "lock\n\txadd\t$val, $ptr",
1331 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1333 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1335 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1338 // Atomic exchange, and, or, xor
1339 let Constraints = "$val = $dst", Defs = [EFLAGS],
1340 usesCustomDAGSchedInserter = 1 in {
1341 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1342 "#ATOMAND64 PSEUDO!",
1343 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1344 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1345 "#ATOMOR64 PSEUDO!",
1346 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1347 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1348 "#ATOMXOR64 PSEUDO!",
1349 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1350 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1351 "#ATOMNAND64 PSEUDO!",
1352 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1353 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1354 "#ATOMMIN64 PSEUDO!",
1355 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1356 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1357 "#ATOMMAX64 PSEUDO!",
1358 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1359 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1360 "#ATOMUMIN64 PSEUDO!",
1361 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1362 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1363 "#ATOMUMAX64 PSEUDO!",
1364 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1367 //===----------------------------------------------------------------------===//
1368 // Non-Instruction Patterns
1369 //===----------------------------------------------------------------------===//
1371 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1372 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1373 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1374 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1375 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1376 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1377 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1378 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1379 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1381 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1382 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1383 Requires<[SmallCode, IsStatic]>;
1384 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1385 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1386 Requires<[SmallCode, IsStatic]>;
1387 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1388 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1389 Requires<[SmallCode, IsStatic]>;
1390 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1391 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1392 Requires<[SmallCode, IsStatic]>;
1395 // Direct PC relative function call for small code model. 32-bit displacement
1396 // sign extended to 64-bit.
1397 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1398 (CALL64pcrel32 tglobaladdr:$dst)>;
1399 def : Pat<(X86call (i64 texternalsym:$dst)),
1400 (CALL64pcrel32 texternalsym:$dst)>;
1402 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1403 (CALL64pcrel32 tglobaladdr:$dst)>;
1404 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1405 (CALL64pcrel32 texternalsym:$dst)>;
1407 def : Pat<(X86tailcall GR64:$dst),
1408 (CALL64r GR64:$dst)>;
1412 def : Pat<(X86tailcall GR32:$dst),
1414 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1416 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1419 def : Pat<(X86tcret GR64:$dst, imm:$off),
1420 (TCRETURNri64 GR64:$dst, imm:$off)>;
1422 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1423 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1425 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1426 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1430 // TEST R,R is smaller than CMP R,0
1431 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1432 (TEST64rr GR64:$src1, GR64:$src1)>;
1434 // Conditional moves with folded loads with operands swapped and conditions
1436 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1437 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1438 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1439 (CMOVB64rm GR64:$src2, addr:$src1)>;
1440 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1441 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1442 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1443 (CMOVE64rm GR64:$src2, addr:$src1)>;
1444 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1445 (CMOVA64rm GR64:$src2, addr:$src1)>;
1446 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1447 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1448 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1449 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1450 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1451 (CMOVL64rm GR64:$src2, addr:$src1)>;
1452 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1453 (CMOVG64rm GR64:$src2, addr:$src1)>;
1454 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1455 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1456 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1457 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1458 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1459 (CMOVP64rm GR64:$src2, addr:$src1)>;
1460 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1461 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1462 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1463 (CMOVS64rm GR64:$src2, addr:$src1)>;
1464 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1465 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1466 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1467 (CMOVO64rm GR64:$src2, addr:$src1)>;
1469 // zextload bool -> zextload byte
1470 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1473 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1474 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1475 // partial-register updates.
1476 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1477 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1478 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1479 // For other extloads, use subregs, since the high contents of the register are
1480 // defined after an extload.
1481 def : Pat<(extloadi64i32 addr:$src),
1482 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1484 def : Pat<(extloadi16i1 addr:$src),
1485 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1487 Requires<[In64BitMode]>;
1488 def : Pat<(extloadi16i8 addr:$src),
1489 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1491 Requires<[In64BitMode]>;
1494 def : Pat<(i64 (anyext GR8:$src)),
1495 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1496 def : Pat<(i64 (anyext GR16:$src)),
1497 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1498 def : Pat<(i64 (anyext GR32:$src)),
1499 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1500 def : Pat<(i16 (anyext GR8:$src)),
1501 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1502 Requires<[In64BitMode]>;
1503 def : Pat<(i32 (anyext GR8:$src)),
1504 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1505 Requires<[In64BitMode]>;
1507 //===----------------------------------------------------------------------===//
1509 //===----------------------------------------------------------------------===//
1511 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1512 // +128 doesn't, so in this special case use a sub instead of an add.
1513 def : Pat<(add GR64:$src1, 128),
1514 (SUB64ri8 GR64:$src1, -128)>;
1515 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1516 (SUB64mi8 addr:$dst, -128)>;
1518 // The same trick applies for 32-bit immediate fields in 64-bit
1520 def : Pat<(add GR64:$src1, 0x0000000080000000),
1521 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1522 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1523 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1525 // r & (2^32-1) ==> movz
1526 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1527 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1528 // r & (2^16-1) ==> movz
1529 def : Pat<(and GR64:$src, 0xffff),
1530 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1531 // r & (2^8-1) ==> movz
1532 def : Pat<(and GR64:$src, 0xff),
1533 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1534 // r & (2^8-1) ==> movz
1535 def : Pat<(and GR32:$src1, 0xff),
1536 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1537 Requires<[In64BitMode]>;
1538 // r & (2^8-1) ==> movz
1539 def : Pat<(and GR16:$src1, 0xff),
1540 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1541 Requires<[In64BitMode]>;
1543 // sext_inreg patterns
1544 def : Pat<(sext_inreg GR64:$src, i32),
1545 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1546 def : Pat<(sext_inreg GR64:$src, i16),
1547 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1548 def : Pat<(sext_inreg GR64:$src, i8),
1549 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1550 def : Pat<(sext_inreg GR32:$src, i8),
1551 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1552 Requires<[In64BitMode]>;
1553 def : Pat<(sext_inreg GR16:$src, i8),
1554 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1555 Requires<[In64BitMode]>;
1558 def : Pat<(i32 (trunc GR64:$src)),
1559 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1560 def : Pat<(i16 (trunc GR64:$src)),
1561 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1562 def : Pat<(i8 (trunc GR64:$src)),
1563 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1564 def : Pat<(i8 (trunc GR32:$src)),
1565 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1566 Requires<[In64BitMode]>;
1567 def : Pat<(i8 (trunc GR16:$src)),
1568 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1569 Requires<[In64BitMode]>;
1571 // h-register tricks.
1572 // For now, be conservative and only the extract if the value is immediately
1573 // zero-extended or stored, which are somewhat common cases. This uses a bunch
1574 // of code to prevent a register requiring a REX prefix from being allocated in
1575 // the same instruction as the h register, as there's currently no way to
1576 // describe this requirement to the register allocator.
1578 // h-register extract and zero-extend.
1579 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1583 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
1584 x86_subreg_8bit_hi)),
1586 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1588 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
1589 x86_subreg_8bit_hi))>,
1590 Requires<[In64BitMode]>;
1591 def : Pat<(srl_su GR16:$src, (i8 8)),
1594 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
1595 x86_subreg_8bit_hi)),
1597 Requires<[In64BitMode]>;
1599 // h-register extract and store.
1600 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1603 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
1604 x86_subreg_8bit_hi))>;
1605 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1608 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
1609 x86_subreg_8bit_hi))>,
1610 Requires<[In64BitMode]>;
1611 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1614 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
1615 x86_subreg_8bit_hi))>,
1616 Requires<[In64BitMode]>;
1618 // (shl x, 1) ==> (add x, x)
1619 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1621 // (shl x (and y, 63)) ==> (shl x, y)
1622 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1623 (SHL64rCL GR64:$src1)>;
1624 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1625 (SHL64mCL addr:$dst)>;
1627 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1628 (SHR64rCL GR64:$src1)>;
1629 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1630 (SHR64mCL addr:$dst)>;
1632 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1633 (SAR64rCL GR64:$src1)>;
1634 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1635 (SAR64mCL addr:$dst)>;
1637 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1638 def : Pat<(or (srl GR64:$src1, CL:$amt),
1639 (shl GR64:$src2, (sub 64, CL:$amt))),
1640 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1642 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1643 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1644 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1646 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1647 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1648 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1650 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1651 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1653 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1655 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1656 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1658 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1659 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1660 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1662 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1663 def : Pat<(or (shl GR64:$src1, CL:$amt),
1664 (srl GR64:$src2, (sub 64, CL:$amt))),
1665 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1667 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1668 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1669 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1671 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1672 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1673 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1675 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1676 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1678 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1680 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1681 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1683 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1684 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1685 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1687 // X86 specific add which produces a flag.
1688 def : Pat<(addc GR64:$src1, GR64:$src2),
1689 (ADD64rr GR64:$src1, GR64:$src2)>;
1690 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1691 (ADD64rm GR64:$src1, addr:$src2)>;
1692 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1693 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1694 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1695 (ADD64ri32 GR64:$src1, imm:$src2)>;
1697 def : Pat<(subc GR64:$src1, GR64:$src2),
1698 (SUB64rr GR64:$src1, GR64:$src2)>;
1699 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1700 (SUB64rm GR64:$src1, addr:$src2)>;
1701 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1702 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1703 def : Pat<(subc GR64:$src1, imm:$src2),
1704 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1706 //===----------------------------------------------------------------------===//
1707 // EFLAGS-defining Patterns
1708 //===----------------------------------------------------------------------===//
1710 // Register-Register Addition with EFLAGS result
1711 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1713 (ADD64rr GR64:$src1, GR64:$src2)>;
1715 // Register-Integer Addition with EFLAGS result
1716 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1718 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1719 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1721 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1723 // Register-Memory Addition with EFLAGS result
1724 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1726 (ADD64rm GR64:$src1, addr:$src2)>;
1728 // Memory-Register Addition with EFLAGS result
1729 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1732 (ADD64mr addr:$dst, GR64:$src2)>;
1733 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1736 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1737 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1740 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1742 // Register-Register Subtraction with EFLAGS result
1743 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1745 (SUB64rr GR64:$src1, GR64:$src2)>;
1747 // Register-Memory Subtraction with EFLAGS result
1748 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1750 (SUB64rm GR64:$src1, addr:$src2)>;
1752 // Register-Integer Subtraction with EFLAGS result
1753 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1755 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1756 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1758 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1760 // Memory-Register Subtraction with EFLAGS result
1761 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1764 (SUB64mr addr:$dst, GR64:$src2)>;
1766 // Memory-Integer Subtraction with EFLAGS result
1767 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1770 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1771 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1774 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1776 // Register-Register Signed Integer Multiplication with EFLAGS result
1777 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1779 (IMUL64rr GR64:$src1, GR64:$src2)>;
1781 // Register-Memory Signed Integer Multiplication with EFLAGS result
1782 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1784 (IMUL64rm GR64:$src1, addr:$src2)>;
1786 // Register-Integer Signed Integer Multiplication with EFLAGS result
1787 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1789 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1790 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1792 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1794 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1795 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1797 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1798 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1800 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1802 // INC and DEC with EFLAGS result. Note that these do not set CF.
1803 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1804 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1805 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1807 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1808 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1809 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1810 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1812 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1814 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1815 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1816 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1818 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1819 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1820 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1821 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1823 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1825 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1826 (INC64r GR64:$src)>;
1827 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1829 (INC64m addr:$dst)>;
1830 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1831 (DEC64r GR64:$src)>;
1832 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1834 (DEC64m addr:$dst)>;
1836 //===----------------------------------------------------------------------===//
1837 // X86-64 SSE Instructions
1838 //===----------------------------------------------------------------------===//
1840 // Move instructions...
1842 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1843 "mov{d|q}\t{$src, $dst|$dst, $src}",
1845 (v2i64 (scalar_to_vector GR64:$src)))]>;
1846 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1847 "mov{d|q}\t{$src, $dst|$dst, $src}",
1848 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1851 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1852 "mov{d|q}\t{$src, $dst|$dst, $src}",
1853 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1854 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1855 "movq\t{$src, $dst|$dst, $src}",
1856 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1858 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1859 "mov{d|q}\t{$src, $dst|$dst, $src}",
1860 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1861 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1862 "movq\t{$src, $dst|$dst, $src}",
1863 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1865 //===----------------------------------------------------------------------===//
1866 // X86-64 SSE4.1 Instructions
1867 //===----------------------------------------------------------------------===//
1869 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1870 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
1871 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
1872 (ins VR128:$src1, i32i8imm:$src2),
1873 !strconcat(OpcodeStr,
1874 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1876 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
1877 def mr : SS4AIi8<opc, MRMDestMem, (outs),
1878 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
1879 !strconcat(OpcodeStr,
1880 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1881 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
1882 addr:$dst)]>, OpSize, REX_W;
1885 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
1887 let isTwoAddress = 1 in {
1888 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
1889 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
1890 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
1891 !strconcat(OpcodeStr,
1892 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1894 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
1896 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
1897 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
1898 !strconcat(OpcodeStr,
1899 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1901 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
1902 imm:$src3)))]>, OpSize, REX_W;
1906 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;