1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64>;
33 def lea64mem : Operand<i64> {
34 let PrintMethod = "printlea64mem";
35 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
36 let ParserMatchClass = "Mem";
39 def lea64_32mem : Operand<i32> {
40 let PrintMethod = "printlea64_32mem";
41 let AsmOperandLowerMethod = "lower_lea64_32mem";
42 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
43 let ParserMatchClass = "Mem";
46 //===----------------------------------------------------------------------===//
47 // Complex Pattern Definitions.
49 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
50 [add, sub, mul, X86mul_imm, shl, or, frameindex,
53 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
54 [tglobaltlsaddr], []>;
56 //===----------------------------------------------------------------------===//
60 def i64immSExt8 : PatLeaf<(i64 imm), [{
61 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
62 // sign extended field.
63 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
66 def i64immSExt32 : PatLeaf<(i64 imm), [{
67 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
68 // sign extended field.
69 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
72 def i64immZExt32 : PatLeaf<(i64 imm), [{
73 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
74 // unsignedsign extended field.
75 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
78 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
79 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
80 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
82 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
83 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
84 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
85 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
87 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
88 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
89 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
90 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
92 //===----------------------------------------------------------------------===//
93 // Instruction list...
96 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
97 // a stack adjustment and the codegen must know that they may modify the stack
98 // pointer before prolog-epilog rewriting occurs.
99 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
100 // sub / add which can clobber EFLAGS.
101 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
102 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
104 [(X86callseq_start timm:$amt)]>,
105 Requires<[In64BitMode]>;
106 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
108 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
109 Requires<[In64BitMode]>;
112 //===----------------------------------------------------------------------===//
113 // Call Instructions...
116 // All calls clobber the non-callee saved registers. RSP is marked as
117 // a use to prevent stack-pointer assignments that appear immediately
118 // before calls from potentially appearing dead. Uses for argument
119 // registers are added manually.
120 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
121 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
122 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
123 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
124 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
127 // NOTE: this pattern doesn't match "X86call imm", because we do not know
128 // that the offset between an arbitrary immediate and the call will fit in
129 // the 32-bit pcrel field that we have.
130 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
131 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
133 Requires<[In64BitMode, NotWin64]>;
134 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
135 "call\t{*}$dst", [(X86call GR64:$dst)]>,
136 Requires<[NotWin64]>;
137 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
138 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
139 Requires<[NotWin64]>;
142 // FIXME: We need to teach codegen about single list of call-clobbered registers.
144 // All calls clobber the non-callee saved registers. RSP is marked as
145 // a use to prevent stack-pointer assignments that appear immediately
146 // before calls from potentially appearing dead. Uses for argument
147 // registers are added manually.
148 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
149 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
150 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
151 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
153 def WINCALL64pcrel32 : I<0xE8, RawFrm,
154 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
157 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
159 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
160 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
162 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
166 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
167 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
169 "#TC_RETURN $dst $offset",
172 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
173 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
175 "#TC_RETURN $dst $offset",
179 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
180 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
181 "jmp{q}\t{*}$dst # TAILCALL",
185 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
186 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
187 [(brind GR64:$dst)]>;
188 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
189 [(brind (loadi64 addr:$dst))]>;
192 //===----------------------------------------------------------------------===//
193 // EH Pseudo Instructions
195 let isTerminator = 1, isReturn = 1, isBarrier = 1,
197 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
198 "ret\t#eh_return, addr: $addr",
199 [(X86ehret GR64:$addr)]>;
203 //===----------------------------------------------------------------------===//
204 // Miscellaneous Instructions...
206 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
207 def LEAVE64 : I<0xC9, RawFrm,
208 (outs), (ins), "leave", []>;
209 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
211 def POP64r : I<0x58, AddRegFrm,
212 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
214 def PUSH64r : I<0x50, AddRegFrm,
215 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
218 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
219 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
220 "push{q}\t$imm", []>;
221 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
222 "push{q}\t$imm", []>;
223 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
224 "push{q}\t$imm", []>;
227 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
228 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
229 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
230 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
232 def LEA64_32r : I<0x8D, MRMSrcMem,
233 (outs GR32:$dst), (ins lea64_32mem:$src),
234 "lea{l}\t{$src|$dst}, {$dst|$src}",
235 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
237 let isReMaterializable = 1 in
238 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
239 "lea{q}\t{$src|$dst}, {$dst|$src}",
240 [(set GR64:$dst, lea64addr:$src)]>;
242 let isTwoAddress = 1 in
243 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
245 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
247 // Bit scan instructions.
248 let Defs = [EFLAGS] in {
249 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
250 "bsf{q}\t{$src, $dst|$dst, $src}",
251 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
252 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
253 "bsf{q}\t{$src, $dst|$dst, $src}",
254 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
255 (implicit EFLAGS)]>, TB;
257 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
258 "bsr{q}\t{$src, $dst|$dst, $src}",
259 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
260 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
261 "bsr{q}\t{$src, $dst|$dst, $src}",
262 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
263 (implicit EFLAGS)]>, TB;
267 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
268 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
269 [(X86rep_movs i64)]>, REP;
270 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
271 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
272 [(X86rep_stos i64)]>, REP;
274 // Fast system-call instructions
275 def SYSCALL : I<0x05, RawFrm,
276 (outs), (ins), "syscall", []>, TB;
277 def SYSENTER : I<0x34, RawFrm,
278 (outs), (ins), "sysenter", []>, TB;
279 def SYSEXIT : I<0x35, RawFrm,
280 (outs), (ins), "sysexit", []>, TB;
281 def SYSEXIT64 : RI<0x35, RawFrm,
282 (outs), (ins), "sysexit", []>, TB;
283 def SYSRET : I<0x07, RawFrm,
284 (outs), (ins), "sysret", []>, TB;
286 //===----------------------------------------------------------------------===//
287 // Move Instructions...
290 let neverHasSideEffects = 1 in
291 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
292 "mov{q}\t{$src, $dst|$dst, $src}", []>;
294 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
295 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
296 "movabs{q}\t{$src, $dst|$dst, $src}",
297 [(set GR64:$dst, imm:$src)]>;
298 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
299 "mov{q}\t{$src, $dst|$dst, $src}",
300 [(set GR64:$dst, i64immSExt32:$src)]>;
303 let canFoldAsLoad = 1 in
304 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
305 "mov{q}\t{$src, $dst|$dst, $src}",
306 [(set GR64:$dst, (load addr:$src))]>;
308 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
309 "mov{q}\t{$src, $dst|$dst, $src}",
310 [(store GR64:$src, addr:$dst)]>;
311 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
312 "mov{q}\t{$src, $dst|$dst, $src}",
313 [(store i64immSExt32:$src, addr:$dst)]>;
315 // Sign/Zero extenders
317 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
318 // operand, which makes it a rare instruction with an 8-bit register
319 // operand that can never access an h register. If support for h registers
320 // were generalized, this would require a special register class.
321 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
322 "movs{bq|x}\t{$src, $dst|$dst, $src}",
323 [(set GR64:$dst, (sext GR8:$src))]>, TB;
324 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
325 "movs{bq|x}\t{$src, $dst|$dst, $src}",
326 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
327 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
328 "movs{wq|x}\t{$src, $dst|$dst, $src}",
329 [(set GR64:$dst, (sext GR16:$src))]>, TB;
330 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
331 "movs{wq|x}\t{$src, $dst|$dst, $src}",
332 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
333 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
334 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
335 [(set GR64:$dst, (sext GR32:$src))]>;
336 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
337 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
338 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
340 // Use movzbl instead of movzbq when the destination is a register; it's
341 // equivalent due to implicit zero-extending, and it has a smaller encoding.
342 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
343 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
344 [(set GR64:$dst, (zext GR8:$src))]>, TB;
345 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
346 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
347 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
348 // Use movzwl instead of movzwq when the destination is a register; it's
349 // equivalent due to implicit zero-extending, and it has a smaller encoding.
350 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
351 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
352 [(set GR64:$dst, (zext GR16:$src))]>, TB;
353 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
354 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
355 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
357 // There's no movzlq instruction, but movl can be used for this purpose, using
358 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
359 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
360 // zero-extension, however this isn't possible when the 32-bit value is
361 // defined by a truncate or is copied from something where the high bits aren't
362 // necessarily all zero. In such cases, we fall back to these explicit zext
364 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
365 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
366 [(set GR64:$dst, (zext GR32:$src))]>;
367 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
368 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
369 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
371 // Any instruction that defines a 32-bit result leaves the high half of the
372 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
373 // be copying from a truncate, but any other 32-bit operation will zero-extend
375 def def32 : PatLeaf<(i32 GR32:$src), [{
376 return N->getOpcode() != ISD::TRUNCATE &&
377 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
378 N->getOpcode() != ISD::CopyFromReg;
381 // In the case of a 32-bit def that is known to implicitly zero-extend,
382 // we can use a SUBREG_TO_REG.
383 def : Pat<(i64 (zext def32:$src)),
384 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
386 let neverHasSideEffects = 1 in {
387 let Defs = [RAX], Uses = [EAX] in
388 def CDQE : RI<0x98, RawFrm, (outs), (ins),
389 "{cltq|cdqe}", []>; // RAX = signext(EAX)
391 let Defs = [RAX,RDX], Uses = [RAX] in
392 def CQO : RI<0x99, RawFrm, (outs), (ins),
393 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
396 //===----------------------------------------------------------------------===//
397 // Arithmetic Instructions...
400 let Defs = [EFLAGS] in {
401 let isTwoAddress = 1 in {
402 let isConvertibleToThreeAddress = 1 in {
403 let isCommutable = 1 in
404 // Register-Register Addition
405 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
406 "add{q}\t{$src2, $dst|$dst, $src2}",
407 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
410 // Register-Integer Addition
411 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
412 "add{q}\t{$src2, $dst|$dst, $src2}",
413 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
415 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
416 "add{q}\t{$src2, $dst|$dst, $src2}",
417 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
419 } // isConvertibleToThreeAddress
421 // Register-Memory Addition
422 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
423 "add{q}\t{$src2, $dst|$dst, $src2}",
424 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
428 // Memory-Register Addition
429 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
430 "add{q}\t{$src2, $dst|$dst, $src2}",
431 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
433 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
434 "add{q}\t{$src2, $dst|$dst, $src2}",
435 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
437 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
438 "add{q}\t{$src2, $dst|$dst, $src2}",
439 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
442 let Uses = [EFLAGS] in {
443 let isTwoAddress = 1 in {
444 let isCommutable = 1 in
445 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
446 "adc{q}\t{$src2, $dst|$dst, $src2}",
447 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
449 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
450 "adc{q}\t{$src2, $dst|$dst, $src2}",
451 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
453 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
454 "adc{q}\t{$src2, $dst|$dst, $src2}",
455 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
456 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
457 "adc{q}\t{$src2, $dst|$dst, $src2}",
458 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
461 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
462 "adc{q}\t{$src2, $dst|$dst, $src2}",
463 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
464 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
465 "adc{q}\t{$src2, $dst|$dst, $src2}",
466 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
467 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
468 "adc{q}\t{$src2, $dst|$dst, $src2}",
469 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
472 let isTwoAddress = 1 in {
473 // Register-Register Subtraction
474 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
475 "sub{q}\t{$src2, $dst|$dst, $src2}",
476 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
479 // Register-Memory Subtraction
480 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
481 "sub{q}\t{$src2, $dst|$dst, $src2}",
482 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
485 // Register-Integer Subtraction
486 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
487 (ins GR64:$src1, i64i8imm:$src2),
488 "sub{q}\t{$src2, $dst|$dst, $src2}",
489 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
491 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
492 (ins GR64:$src1, i64i32imm:$src2),
493 "sub{q}\t{$src2, $dst|$dst, $src2}",
494 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
498 // Memory-Register Subtraction
499 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
500 "sub{q}\t{$src2, $dst|$dst, $src2}",
501 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
504 // Memory-Integer Subtraction
505 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
506 "sub{q}\t{$src2, $dst|$dst, $src2}",
507 [(store (sub (load addr:$dst), i64immSExt8:$src2),
510 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
511 "sub{q}\t{$src2, $dst|$dst, $src2}",
512 [(store (sub (load addr:$dst), i64immSExt32:$src2),
516 let Uses = [EFLAGS] in {
517 let isTwoAddress = 1 in {
518 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
519 "sbb{q}\t{$src2, $dst|$dst, $src2}",
520 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
522 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
523 "sbb{q}\t{$src2, $dst|$dst, $src2}",
524 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
526 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
527 "sbb{q}\t{$src2, $dst|$dst, $src2}",
528 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
529 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
530 "sbb{q}\t{$src2, $dst|$dst, $src2}",
531 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
534 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
535 "sbb{q}\t{$src2, $dst|$dst, $src2}",
536 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
537 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
538 "sbb{q}\t{$src2, $dst|$dst, $src2}",
539 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
540 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
541 "sbb{q}\t{$src2, $dst|$dst, $src2}",
542 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
546 // Unsigned multiplication
547 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
548 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
549 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
551 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
552 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
554 // Signed multiplication
555 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
556 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
558 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
559 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
562 let Defs = [EFLAGS] in {
563 let isTwoAddress = 1 in {
564 let isCommutable = 1 in
565 // Register-Register Signed Integer Multiplication
566 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
567 (ins GR64:$src1, GR64:$src2),
568 "imul{q}\t{$src2, $dst|$dst, $src2}",
569 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
570 (implicit EFLAGS)]>, TB;
572 // Register-Memory Signed Integer Multiplication
573 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
574 (ins GR64:$src1, i64mem:$src2),
575 "imul{q}\t{$src2, $dst|$dst, $src2}",
576 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
577 (implicit EFLAGS)]>, TB;
580 // Suprisingly enough, these are not two address instructions!
582 // Register-Integer Signed Integer Multiplication
583 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
584 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
585 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
586 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
588 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
589 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
590 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
591 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
594 // Memory-Integer Signed Integer Multiplication
595 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
596 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
597 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
598 [(set GR64:$dst, (mul (load addr:$src1),
601 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
602 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
603 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
604 [(set GR64:$dst, (mul (load addr:$src1),
605 i64immSExt32:$src2)),
609 // Unsigned division / remainder
610 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
611 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
613 // Signed division / remainder
614 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
615 "idiv{q}\t$src", []>;
617 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
619 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
620 "idiv{q}\t$src", []>;
624 // Unary instructions
625 let Defs = [EFLAGS], CodeSize = 2 in {
626 let isTwoAddress = 1 in
627 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
628 [(set GR64:$dst, (ineg GR64:$src)),
630 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
631 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
634 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
635 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
636 [(set GR64:$dst, (add GR64:$src, 1)),
638 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
639 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
642 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
643 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
644 [(set GR64:$dst, (add GR64:$src, -1)),
646 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
647 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
650 // In 64-bit mode, single byte INC and DEC cannot be encoded.
651 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
652 // Can transform into LEA.
653 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
654 [(set GR16:$dst, (add GR16:$src, 1)),
656 OpSize, Requires<[In64BitMode]>;
657 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
658 [(set GR32:$dst, (add GR32:$src, 1)),
660 Requires<[In64BitMode]>;
661 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
662 [(set GR16:$dst, (add GR16:$src, -1)),
664 OpSize, Requires<[In64BitMode]>;
665 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
666 [(set GR32:$dst, (add GR32:$src, -1)),
668 Requires<[In64BitMode]>;
669 } // isConvertibleToThreeAddress
671 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
672 // how to unfold them.
673 let isTwoAddress = 0, CodeSize = 2 in {
674 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
675 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
677 OpSize, Requires<[In64BitMode]>;
678 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
679 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
681 Requires<[In64BitMode]>;
682 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
683 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
685 OpSize, Requires<[In64BitMode]>;
686 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
687 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
689 Requires<[In64BitMode]>;
691 } // Defs = [EFLAGS], CodeSize
694 let Defs = [EFLAGS] in {
695 // Shift instructions
696 let isTwoAddress = 1 in {
698 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
699 "shl{q}\t{%cl, $dst|$dst, %CL}",
700 [(set GR64:$dst, (shl GR64:$src, CL))]>;
701 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
702 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
703 "shl{q}\t{$src2, $dst|$dst, $src2}",
704 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
705 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
710 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
711 "shl{q}\t{%cl, $dst|$dst, %CL}",
712 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
713 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
714 "shl{q}\t{$src, $dst|$dst, $src}",
715 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
716 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
718 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
720 let isTwoAddress = 1 in {
722 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
723 "shr{q}\t{%cl, $dst|$dst, %CL}",
724 [(set GR64:$dst, (srl GR64:$src, CL))]>;
725 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
726 "shr{q}\t{$src2, $dst|$dst, $src2}",
727 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
728 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
730 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
734 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
735 "shr{q}\t{%cl, $dst|$dst, %CL}",
736 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
737 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
738 "shr{q}\t{$src, $dst|$dst, $src}",
739 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
740 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
742 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
744 let isTwoAddress = 1 in {
746 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
747 "sar{q}\t{%cl, $dst|$dst, %CL}",
748 [(set GR64:$dst, (sra GR64:$src, CL))]>;
749 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
750 "sar{q}\t{$src2, $dst|$dst, $src2}",
751 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
752 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
754 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
758 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
759 "sar{q}\t{%cl, $dst|$dst, %CL}",
760 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
761 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
762 "sar{q}\t{$src, $dst|$dst, $src}",
763 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
764 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
766 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
768 // Rotate instructions
769 let isTwoAddress = 1 in {
771 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
772 "rol{q}\t{%cl, $dst|$dst, %CL}",
773 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
774 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
775 "rol{q}\t{$src2, $dst|$dst, $src2}",
776 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
777 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
779 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
783 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
784 "rol{q}\t{%cl, $dst|$dst, %CL}",
785 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
786 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
787 "rol{q}\t{$src, $dst|$dst, $src}",
788 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
789 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
791 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
793 let isTwoAddress = 1 in {
795 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
796 "ror{q}\t{%cl, $dst|$dst, %CL}",
797 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
798 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
799 "ror{q}\t{$src2, $dst|$dst, $src2}",
800 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
801 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
803 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
807 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
808 "ror{q}\t{%cl, $dst|$dst, %CL}",
809 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
810 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
811 "ror{q}\t{$src, $dst|$dst, $src}",
812 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
813 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
815 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
817 // Double shift instructions (generalizations of rotate)
818 let isTwoAddress = 1 in {
820 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
821 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
822 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
823 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
824 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
825 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
828 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
829 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
830 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
831 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
832 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
835 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
836 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
837 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
838 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
845 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
846 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
847 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
849 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
850 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
851 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
854 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
855 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
856 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
857 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
858 (i8 imm:$src3)), addr:$dst)]>,
860 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
861 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
862 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
863 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
864 (i8 imm:$src3)), addr:$dst)]>,
868 //===----------------------------------------------------------------------===//
869 // Logical Instructions...
872 let isTwoAddress = 1 , AddedComplexity = 15 in
873 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
874 [(set GR64:$dst, (not GR64:$src))]>;
875 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
876 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
878 let Defs = [EFLAGS] in {
879 let isTwoAddress = 1 in {
880 let isCommutable = 1 in
881 def AND64rr : RI<0x21, MRMDestReg,
882 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
883 "and{q}\t{$src2, $dst|$dst, $src2}",
884 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
886 def AND64rm : RI<0x23, MRMSrcMem,
887 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
888 "and{q}\t{$src2, $dst|$dst, $src2}",
889 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
891 def AND64ri8 : RIi8<0x83, MRM4r,
892 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
893 "and{q}\t{$src2, $dst|$dst, $src2}",
894 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
896 def AND64ri32 : RIi32<0x81, MRM4r,
897 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
898 "and{q}\t{$src2, $dst|$dst, $src2}",
899 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
903 def AND64mr : RI<0x21, MRMDestMem,
904 (outs), (ins i64mem:$dst, GR64:$src),
905 "and{q}\t{$src, $dst|$dst, $src}",
906 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
908 def AND64mi8 : RIi8<0x83, MRM4m,
909 (outs), (ins i64mem:$dst, i64i8imm :$src),
910 "and{q}\t{$src, $dst|$dst, $src}",
911 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
913 def AND64mi32 : RIi32<0x81, MRM4m,
914 (outs), (ins i64mem:$dst, i64i32imm:$src),
915 "and{q}\t{$src, $dst|$dst, $src}",
916 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
919 let isTwoAddress = 1 in {
920 let isCommutable = 1 in
921 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
922 "or{q}\t{$src2, $dst|$dst, $src2}",
923 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
925 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
926 "or{q}\t{$src2, $dst|$dst, $src2}",
927 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
929 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
930 "or{q}\t{$src2, $dst|$dst, $src2}",
931 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
933 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
934 "or{q}\t{$src2, $dst|$dst, $src2}",
935 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
939 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
940 "or{q}\t{$src, $dst|$dst, $src}",
941 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
943 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
944 "or{q}\t{$src, $dst|$dst, $src}",
945 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
947 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
948 "or{q}\t{$src, $dst|$dst, $src}",
949 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
952 let isTwoAddress = 1 in {
953 let isCommutable = 1 in
954 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
955 "xor{q}\t{$src2, $dst|$dst, $src2}",
956 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
958 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
959 "xor{q}\t{$src2, $dst|$dst, $src2}",
960 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
962 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
963 "xor{q}\t{$src2, $dst|$dst, $src2}",
964 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
966 def XOR64ri32 : RIi32<0x81, MRM6r,
967 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
968 "xor{q}\t{$src2, $dst|$dst, $src2}",
969 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
973 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
974 "xor{q}\t{$src, $dst|$dst, $src}",
975 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
977 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
978 "xor{q}\t{$src, $dst|$dst, $src}",
979 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
981 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
982 "xor{q}\t{$src, $dst|$dst, $src}",
983 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
987 //===----------------------------------------------------------------------===//
988 // Comparison Instructions...
991 // Integer comparison
992 let Defs = [EFLAGS] in {
993 let isCommutable = 1 in
994 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
995 "test{q}\t{$src2, $src1|$src1, $src2}",
996 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
998 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
999 "test{q}\t{$src2, $src1|$src1, $src2}",
1000 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1001 (implicit EFLAGS)]>;
1002 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1003 (ins GR64:$src1, i64i32imm:$src2),
1004 "test{q}\t{$src2, $src1|$src1, $src2}",
1005 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1006 (implicit EFLAGS)]>;
1007 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1008 (ins i64mem:$src1, i64i32imm:$src2),
1009 "test{q}\t{$src2, $src1|$src1, $src2}",
1010 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1011 (implicit EFLAGS)]>;
1013 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1014 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1015 [(X86cmp GR64:$src1, GR64:$src2),
1016 (implicit EFLAGS)]>;
1017 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1018 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1019 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1020 (implicit EFLAGS)]>;
1021 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1022 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1023 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1024 (implicit EFLAGS)]>;
1025 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1026 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1027 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1028 (implicit EFLAGS)]>;
1029 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1030 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1031 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1032 (implicit EFLAGS)]>;
1033 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1034 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1035 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1036 (implicit EFLAGS)]>;
1037 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1038 (ins i64mem:$src1, i64i32imm:$src2),
1039 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1040 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1041 (implicit EFLAGS)]>;
1042 } // Defs = [EFLAGS]
1045 // TODO: BTC, BTR, and BTS
1046 let Defs = [EFLAGS] in {
1047 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1048 "bt{q}\t{$src2, $src1|$src1, $src2}",
1049 [(X86bt GR64:$src1, GR64:$src2),
1050 (implicit EFLAGS)]>, TB;
1052 // Unlike with the register+register form, the memory+register form of the
1053 // bt instruction does not ignore the high bits of the index. From ISel's
1054 // perspective, this is pretty bizarre. Disable these instructions for now.
1055 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1056 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1057 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1058 // (implicit EFLAGS)]>, TB;
1060 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1061 "bt{q}\t{$src2, $src1|$src1, $src2}",
1062 [(X86bt GR64:$src1, i64immSExt8:$src2),
1063 (implicit EFLAGS)]>, TB;
1064 // Note that these instructions don't need FastBTMem because that
1065 // only applies when the other operand is in a register. When it's
1066 // an immediate, bt is still fast.
1067 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1068 "bt{q}\t{$src2, $src1|$src1, $src2}",
1069 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1070 (implicit EFLAGS)]>, TB;
1071 } // Defs = [EFLAGS]
1073 // Conditional moves
1074 let Uses = [EFLAGS], isTwoAddress = 1 in {
1075 let isCommutable = 1 in {
1076 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1077 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1078 "cmovb\t{$src2, $dst|$dst, $src2}",
1079 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1080 X86_COND_B, EFLAGS))]>, TB;
1081 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1082 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1083 "cmovae\t{$src2, $dst|$dst, $src2}",
1084 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1085 X86_COND_AE, EFLAGS))]>, TB;
1086 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1087 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1088 "cmove\t{$src2, $dst|$dst, $src2}",
1089 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1090 X86_COND_E, EFLAGS))]>, TB;
1091 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1092 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1093 "cmovne\t{$src2, $dst|$dst, $src2}",
1094 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1095 X86_COND_NE, EFLAGS))]>, TB;
1096 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1097 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1098 "cmovbe\t{$src2, $dst|$dst, $src2}",
1099 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1100 X86_COND_BE, EFLAGS))]>, TB;
1101 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1102 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1103 "cmova\t{$src2, $dst|$dst, $src2}",
1104 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1105 X86_COND_A, EFLAGS))]>, TB;
1106 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1107 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1108 "cmovl\t{$src2, $dst|$dst, $src2}",
1109 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1110 X86_COND_L, EFLAGS))]>, TB;
1111 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1112 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1113 "cmovge\t{$src2, $dst|$dst, $src2}",
1114 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1115 X86_COND_GE, EFLAGS))]>, TB;
1116 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1117 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1118 "cmovle\t{$src2, $dst|$dst, $src2}",
1119 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1120 X86_COND_LE, EFLAGS))]>, TB;
1121 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1122 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1123 "cmovg\t{$src2, $dst|$dst, $src2}",
1124 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1125 X86_COND_G, EFLAGS))]>, TB;
1126 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1127 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1128 "cmovs\t{$src2, $dst|$dst, $src2}",
1129 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1130 X86_COND_S, EFLAGS))]>, TB;
1131 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1132 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1133 "cmovns\t{$src2, $dst|$dst, $src2}",
1134 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1135 X86_COND_NS, EFLAGS))]>, TB;
1136 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1137 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1138 "cmovp\t{$src2, $dst|$dst, $src2}",
1139 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1140 X86_COND_P, EFLAGS))]>, TB;
1141 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1142 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1143 "cmovnp\t{$src2, $dst|$dst, $src2}",
1144 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1145 X86_COND_NP, EFLAGS))]>, TB;
1146 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1147 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1148 "cmovo\t{$src2, $dst|$dst, $src2}",
1149 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1150 X86_COND_O, EFLAGS))]>, TB;
1151 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1152 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1153 "cmovno\t{$src2, $dst|$dst, $src2}",
1154 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1155 X86_COND_NO, EFLAGS))]>, TB;
1156 } // isCommutable = 1
1158 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1159 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1160 "cmovb\t{$src2, $dst|$dst, $src2}",
1161 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1162 X86_COND_B, EFLAGS))]>, TB;
1163 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1164 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1165 "cmovae\t{$src2, $dst|$dst, $src2}",
1166 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1167 X86_COND_AE, EFLAGS))]>, TB;
1168 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1169 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1170 "cmove\t{$src2, $dst|$dst, $src2}",
1171 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1172 X86_COND_E, EFLAGS))]>, TB;
1173 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1174 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1175 "cmovne\t{$src2, $dst|$dst, $src2}",
1176 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1177 X86_COND_NE, EFLAGS))]>, TB;
1178 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1179 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1180 "cmovbe\t{$src2, $dst|$dst, $src2}",
1181 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1182 X86_COND_BE, EFLAGS))]>, TB;
1183 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1184 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1185 "cmova\t{$src2, $dst|$dst, $src2}",
1186 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1187 X86_COND_A, EFLAGS))]>, TB;
1188 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1189 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1190 "cmovl\t{$src2, $dst|$dst, $src2}",
1191 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1192 X86_COND_L, EFLAGS))]>, TB;
1193 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1194 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1195 "cmovge\t{$src2, $dst|$dst, $src2}",
1196 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1197 X86_COND_GE, EFLAGS))]>, TB;
1198 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1199 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1200 "cmovle\t{$src2, $dst|$dst, $src2}",
1201 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1202 X86_COND_LE, EFLAGS))]>, TB;
1203 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1204 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1205 "cmovg\t{$src2, $dst|$dst, $src2}",
1206 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1207 X86_COND_G, EFLAGS))]>, TB;
1208 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1209 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1210 "cmovs\t{$src2, $dst|$dst, $src2}",
1211 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1212 X86_COND_S, EFLAGS))]>, TB;
1213 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1214 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1215 "cmovns\t{$src2, $dst|$dst, $src2}",
1216 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1217 X86_COND_NS, EFLAGS))]>, TB;
1218 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1219 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1220 "cmovp\t{$src2, $dst|$dst, $src2}",
1221 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1222 X86_COND_P, EFLAGS))]>, TB;
1223 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1224 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1225 "cmovnp\t{$src2, $dst|$dst, $src2}",
1226 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1227 X86_COND_NP, EFLAGS))]>, TB;
1228 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1229 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1230 "cmovo\t{$src2, $dst|$dst, $src2}",
1231 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1232 X86_COND_O, EFLAGS))]>, TB;
1233 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1234 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1235 "cmovno\t{$src2, $dst|$dst, $src2}",
1236 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1237 X86_COND_NO, EFLAGS))]>, TB;
1240 //===----------------------------------------------------------------------===//
1241 // Conversion Instructions...
1244 // f64 -> signed i64
1245 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1246 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1248 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1249 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1250 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1251 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1252 (load addr:$src)))]>;
1253 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1254 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1255 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1256 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1257 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1258 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1259 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1260 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1262 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1263 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1264 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1266 (int_x86_sse2_cvttsd2si64
1267 (load addr:$src)))]>;
1269 // Signed i64 -> f64
1270 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1271 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1272 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1273 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1274 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1275 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1277 let isTwoAddress = 1 in {
1278 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1279 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1280 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1282 (int_x86_sse2_cvtsi642sd VR128:$src1,
1284 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1285 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1286 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1288 (int_x86_sse2_cvtsi642sd VR128:$src1,
1289 (loadi64 addr:$src2)))]>;
1292 // Signed i64 -> f32
1293 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1294 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1295 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1296 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1297 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1298 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1300 let isTwoAddress = 1 in {
1301 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1302 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1303 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1305 (int_x86_sse_cvtsi642ss VR128:$src1,
1307 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1308 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1309 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1311 (int_x86_sse_cvtsi642ss VR128:$src1,
1312 (loadi64 addr:$src2)))]>;
1315 // f32 -> signed i64
1316 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1317 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1319 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1320 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1321 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1322 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1323 (load addr:$src)))]>;
1324 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1325 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1326 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1327 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1328 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1329 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1330 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1331 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1333 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1334 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1335 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1337 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1339 //===----------------------------------------------------------------------===//
1340 // Alias Instructions
1341 //===----------------------------------------------------------------------===//
1343 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1344 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1346 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1347 // when we have a better way to specify isel priority.
1348 let AddedComplexity = 1 in
1350 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1353 // Materialize i64 constant where top 32-bits are zero.
1354 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1355 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1356 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1357 [(set GR64:$dst, i64immZExt32:$src)]>;
1359 //===----------------------------------------------------------------------===//
1360 // Thread Local Storage Instructions
1361 //===----------------------------------------------------------------------===//
1363 // All calls clobber the non-callee saved registers. RSP is marked as
1364 // a use to prevent stack-pointer assignments that appear immediately
1365 // before calls from potentially appearing dead.
1366 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1367 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1368 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1369 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1370 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1372 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1374 "leaq\t$sym(%rip), %rdi; "
1377 "call\t__tls_get_addr@PLT",
1378 [(X86tlsaddr tls64addr:$sym)]>,
1379 Requires<[In64BitMode]>;
1381 let AddedComplexity = 5 in
1382 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1383 "movq\t%gs:$src, $dst",
1384 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1386 let AddedComplexity = 5 in
1387 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1388 "movq\t%fs:$src, $dst",
1389 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1391 //===----------------------------------------------------------------------===//
1392 // Atomic Instructions
1393 //===----------------------------------------------------------------------===//
1395 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1396 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1398 "cmpxchgq\t$swap,$ptr",
1399 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1402 let Constraints = "$val = $dst" in {
1403 let Defs = [EFLAGS] in
1404 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1407 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1410 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1412 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1415 // Optimized codegen when the non-memory output is not used.
1416 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1417 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1419 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1420 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1421 (ins i64mem:$dst, i64i8imm :$src2),
1423 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1424 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1425 (ins i64mem:$dst, i64i32imm :$src2),
1427 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1428 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1430 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1431 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1432 (ins i64mem:$dst, i64i8imm :$src2),
1434 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1435 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1436 (ins i64mem:$dst, i64i32imm:$src2),
1438 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1439 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1441 "inc{q}\t$dst", []>, LOCK;
1442 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1444 "dec{q}\t$dst", []>, LOCK;
1446 // Atomic exchange, and, or, xor
1447 let Constraints = "$val = $dst", Defs = [EFLAGS],
1448 usesCustomDAGSchedInserter = 1 in {
1449 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1450 "#ATOMAND64 PSEUDO!",
1451 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1452 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1453 "#ATOMOR64 PSEUDO!",
1454 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1455 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1456 "#ATOMXOR64 PSEUDO!",
1457 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1458 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1459 "#ATOMNAND64 PSEUDO!",
1460 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1461 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1462 "#ATOMMIN64 PSEUDO!",
1463 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1464 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1465 "#ATOMMAX64 PSEUDO!",
1466 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1467 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1468 "#ATOMUMIN64 PSEUDO!",
1469 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1470 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1471 "#ATOMUMAX64 PSEUDO!",
1472 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1475 //===----------------------------------------------------------------------===//
1476 // Non-Instruction Patterns
1477 //===----------------------------------------------------------------------===//
1479 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1480 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1481 // 'movabs' predicate should handle this sort of thing.
1482 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1483 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1484 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1485 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1486 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1487 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1488 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1489 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1491 // In static codegen with small code model, we can get the address of a label
1492 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1493 // the MOV64ri64i32 should accept these.
1494 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1495 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1496 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1497 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1498 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1499 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1500 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1501 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1503 // In kernel code model, we can get the address of a label
1504 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1505 // the MOV64ri32 should accept these.
1506 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1507 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1508 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1509 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1510 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1511 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1512 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1513 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1515 // If we have small model and -static mode, it is safe to store global addresses
1516 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1517 // for MOV64mi32 should handle this sort of thing.
1518 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1519 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1520 Requires<[NearData, IsStatic]>;
1521 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1522 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1523 Requires<[NearData, IsStatic]>;
1524 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1525 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1526 Requires<[NearData, IsStatic]>;
1527 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1528 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1529 Requires<[NearData, IsStatic]>;
1532 // Direct PC relative function call for small code model. 32-bit displacement
1533 // sign extended to 64-bit.
1534 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1535 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1536 def : Pat<(X86call (i64 texternalsym:$dst)),
1537 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1539 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1540 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1541 def : Pat<(X86call (i64 texternalsym:$dst)),
1542 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1545 def : Pat<(X86tcret GR64:$dst, imm:$off),
1546 (TCRETURNri64 GR64:$dst, imm:$off)>;
1548 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1549 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1551 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1552 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1556 // TEST R,R is smaller than CMP R,0
1557 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1558 (TEST64rr GR64:$src1, GR64:$src1)>;
1560 // Conditional moves with folded loads with operands swapped and conditions
1562 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1563 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1564 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1565 (CMOVB64rm GR64:$src2, addr:$src1)>;
1566 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1567 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1568 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1569 (CMOVE64rm GR64:$src2, addr:$src1)>;
1570 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1571 (CMOVA64rm GR64:$src2, addr:$src1)>;
1572 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1573 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1574 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1575 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1576 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1577 (CMOVL64rm GR64:$src2, addr:$src1)>;
1578 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1579 (CMOVG64rm GR64:$src2, addr:$src1)>;
1580 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1581 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1582 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1583 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1584 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1585 (CMOVP64rm GR64:$src2, addr:$src1)>;
1586 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1587 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1588 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1589 (CMOVS64rm GR64:$src2, addr:$src1)>;
1590 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1591 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1592 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1593 (CMOVO64rm GR64:$src2, addr:$src1)>;
1595 // zextload bool -> zextload byte
1596 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1599 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1600 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1601 // partial-register updates.
1602 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1603 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1604 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1605 // For other extloads, use subregs, since the high contents of the register are
1606 // defined after an extload.
1607 def : Pat<(extloadi64i32 addr:$src),
1608 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1610 def : Pat<(extloadi16i1 addr:$src),
1611 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1613 Requires<[In64BitMode]>;
1614 def : Pat<(extloadi16i8 addr:$src),
1615 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1617 Requires<[In64BitMode]>;
1620 def : Pat<(i64 (anyext GR8:$src)),
1621 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1622 def : Pat<(i64 (anyext GR16:$src)),
1623 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1624 def : Pat<(i64 (anyext GR32:$src)),
1625 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1626 def : Pat<(i16 (anyext GR8:$src)),
1627 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1628 Requires<[In64BitMode]>;
1629 def : Pat<(i32 (anyext GR8:$src)),
1630 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1631 Requires<[In64BitMode]>;
1633 //===----------------------------------------------------------------------===//
1635 //===----------------------------------------------------------------------===//
1637 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1638 // +128 doesn't, so in this special case use a sub instead of an add.
1639 def : Pat<(add GR64:$src1, 128),
1640 (SUB64ri8 GR64:$src1, -128)>;
1641 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1642 (SUB64mi8 addr:$dst, -128)>;
1644 // The same trick applies for 32-bit immediate fields in 64-bit
1646 def : Pat<(add GR64:$src1, 0x0000000080000000),
1647 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1648 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1649 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1651 // r & (2^32-1) ==> movz
1652 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1653 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1654 // r & (2^16-1) ==> movz
1655 def : Pat<(and GR64:$src, 0xffff),
1656 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1657 // r & (2^8-1) ==> movz
1658 def : Pat<(and GR64:$src, 0xff),
1659 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1660 // r & (2^8-1) ==> movz
1661 def : Pat<(and GR32:$src1, 0xff),
1662 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1663 Requires<[In64BitMode]>;
1664 // r & (2^8-1) ==> movz
1665 def : Pat<(and GR16:$src1, 0xff),
1666 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1667 Requires<[In64BitMode]>;
1669 // sext_inreg patterns
1670 def : Pat<(sext_inreg GR64:$src, i32),
1671 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1672 def : Pat<(sext_inreg GR64:$src, i16),
1673 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1674 def : Pat<(sext_inreg GR64:$src, i8),
1675 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1676 def : Pat<(sext_inreg GR32:$src, i8),
1677 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1678 Requires<[In64BitMode]>;
1679 def : Pat<(sext_inreg GR16:$src, i8),
1680 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1681 Requires<[In64BitMode]>;
1684 def : Pat<(i32 (trunc GR64:$src)),
1685 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1686 def : Pat<(i16 (trunc GR64:$src)),
1687 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1688 def : Pat<(i8 (trunc GR64:$src)),
1689 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1690 def : Pat<(i8 (trunc GR32:$src)),
1691 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1692 Requires<[In64BitMode]>;
1693 def : Pat<(i8 (trunc GR16:$src)),
1694 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1695 Requires<[In64BitMode]>;
1697 // h-register tricks.
1698 // For now, be conservative on x86-64 and use an h-register extract only if the
1699 // value is immediately zero-extended or stored, which are somewhat common
1700 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1701 // from being allocated in the same instruction as the h register, as there's
1702 // currently no way to describe this requirement to the register allocator.
1704 // h-register extract and zero-extend.
1705 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1709 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1710 x86_subreg_8bit_hi)),
1712 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1714 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1715 x86_subreg_8bit_hi))>,
1716 Requires<[In64BitMode]>;
1717 def : Pat<(srl_su GR16:$src, (i8 8)),
1720 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1721 x86_subreg_8bit_hi)),
1723 Requires<[In64BitMode]>;
1724 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1726 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1727 x86_subreg_8bit_hi))>,
1728 Requires<[In64BitMode]>;
1729 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1733 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1734 x86_subreg_8bit_hi)),
1737 // h-register extract and store.
1738 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1741 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1742 x86_subreg_8bit_hi))>;
1743 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1746 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1747 x86_subreg_8bit_hi))>,
1748 Requires<[In64BitMode]>;
1749 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1752 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1753 x86_subreg_8bit_hi))>,
1754 Requires<[In64BitMode]>;
1756 // (shl x, 1) ==> (add x, x)
1757 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1759 // (shl x (and y, 63)) ==> (shl x, y)
1760 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1761 (SHL64rCL GR64:$src1)>;
1762 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1763 (SHL64mCL addr:$dst)>;
1765 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1766 (SHR64rCL GR64:$src1)>;
1767 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1768 (SHR64mCL addr:$dst)>;
1770 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1771 (SAR64rCL GR64:$src1)>;
1772 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1773 (SAR64mCL addr:$dst)>;
1775 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1776 def : Pat<(or (srl GR64:$src1, CL:$amt),
1777 (shl GR64:$src2, (sub 64, CL:$amt))),
1778 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1780 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1781 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1782 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1784 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1785 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1786 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1788 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1789 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1791 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1793 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1794 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1796 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1797 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1798 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1800 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1801 def : Pat<(or (shl GR64:$src1, CL:$amt),
1802 (srl GR64:$src2, (sub 64, CL:$amt))),
1803 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1805 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1806 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1807 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1809 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1810 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1811 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1813 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1814 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1816 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1818 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1819 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1821 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1822 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1823 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1825 // X86 specific add which produces a flag.
1826 def : Pat<(addc GR64:$src1, GR64:$src2),
1827 (ADD64rr GR64:$src1, GR64:$src2)>;
1828 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1829 (ADD64rm GR64:$src1, addr:$src2)>;
1830 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1831 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1832 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1833 (ADD64ri32 GR64:$src1, imm:$src2)>;
1835 def : Pat<(subc GR64:$src1, GR64:$src2),
1836 (SUB64rr GR64:$src1, GR64:$src2)>;
1837 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1838 (SUB64rm GR64:$src1, addr:$src2)>;
1839 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1840 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1841 def : Pat<(subc GR64:$src1, imm:$src2),
1842 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1844 //===----------------------------------------------------------------------===//
1845 // EFLAGS-defining Patterns
1846 //===----------------------------------------------------------------------===//
1848 // Register-Register Addition with EFLAGS result
1849 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1851 (ADD64rr GR64:$src1, GR64:$src2)>;
1853 // Register-Integer Addition with EFLAGS result
1854 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1856 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1857 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1859 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1861 // Register-Memory Addition with EFLAGS result
1862 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1864 (ADD64rm GR64:$src1, addr:$src2)>;
1866 // Memory-Register Addition with EFLAGS result
1867 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1870 (ADD64mr addr:$dst, GR64:$src2)>;
1871 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1874 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1875 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1878 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1880 // Register-Register Subtraction with EFLAGS result
1881 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1883 (SUB64rr GR64:$src1, GR64:$src2)>;
1885 // Register-Memory Subtraction with EFLAGS result
1886 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1888 (SUB64rm GR64:$src1, addr:$src2)>;
1890 // Register-Integer Subtraction with EFLAGS result
1891 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1893 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1894 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1896 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1898 // Memory-Register Subtraction with EFLAGS result
1899 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1902 (SUB64mr addr:$dst, GR64:$src2)>;
1904 // Memory-Integer Subtraction with EFLAGS result
1905 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1908 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1909 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1912 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1914 // Register-Register Signed Integer Multiplication with EFLAGS result
1915 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1917 (IMUL64rr GR64:$src1, GR64:$src2)>;
1919 // Register-Memory Signed Integer Multiplication with EFLAGS result
1920 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1922 (IMUL64rm GR64:$src1, addr:$src2)>;
1924 // Register-Integer Signed Integer Multiplication with EFLAGS result
1925 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1927 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1928 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1930 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1932 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1933 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1935 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1936 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1938 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1940 // INC and DEC with EFLAGS result. Note that these do not set CF.
1941 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1942 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1943 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1945 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1946 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1947 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1948 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1950 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1952 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1953 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1954 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1956 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1957 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1958 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1959 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1961 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1963 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1964 (INC64r GR64:$src)>;
1965 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1967 (INC64m addr:$dst)>;
1968 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1969 (DEC64r GR64:$src)>;
1970 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1972 (DEC64m addr:$dst)>;
1974 //===----------------------------------------------------------------------===//
1975 // X86-64 SSE Instructions
1976 //===----------------------------------------------------------------------===//
1978 // Move instructions...
1980 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1981 "mov{d|q}\t{$src, $dst|$dst, $src}",
1983 (v2i64 (scalar_to_vector GR64:$src)))]>;
1984 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1985 "mov{d|q}\t{$src, $dst|$dst, $src}",
1986 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1989 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1990 "mov{d|q}\t{$src, $dst|$dst, $src}",
1991 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1992 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1993 "movq\t{$src, $dst|$dst, $src}",
1994 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1996 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1997 "mov{d|q}\t{$src, $dst|$dst, $src}",
1998 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1999 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2000 "movq\t{$src, $dst|$dst, $src}",
2001 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2003 //===----------------------------------------------------------------------===//
2004 // X86-64 SSE4.1 Instructions
2005 //===----------------------------------------------------------------------===//
2007 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2008 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2009 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2010 (ins VR128:$src1, i32i8imm:$src2),
2011 !strconcat(OpcodeStr,
2012 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2014 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2015 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2016 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2017 !strconcat(OpcodeStr,
2018 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2019 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2020 addr:$dst)]>, OpSize, REX_W;
2023 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2025 let isTwoAddress = 1 in {
2026 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2027 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2028 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2029 !strconcat(OpcodeStr,
2030 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2032 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2034 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2035 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2036 !strconcat(OpcodeStr,
2037 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2039 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2040 imm:$src3)))]>, OpSize, REX_W;
2044 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;