1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Support/InstVisitor.h"
24 #include "llvm/Target/MRegisterInfo.h"
27 using namespace MOTy; // Get Use, Def, UseAndDef
30 struct ISel : public FunctionPass, InstVisitor<ISel> {
32 MachineFunction *F; // The function we are compiling into
33 MachineBasicBlock *BB; // The current MBB we are compiling
36 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
38 ISel(TargetMachine &tm)
39 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
41 /// runOnFunction - Top level implementation of instruction selection for
42 /// the entire function.
44 bool runOnFunction(Function &Fn) {
45 F = &MachineFunction::construct(&Fn, TM);
48 CurReg = MRegisterInfo::FirstVirtualRegister;
50 return false; // We never modify the LLVM itself.
53 /// visitBasicBlock - This method is called when we are visiting a new basic
54 /// block. This simply creates a new MachineBasicBlock to emit code into
55 /// and adds it to the current MachineFunction. Subsequent visit* for
56 /// instructions will be invoked for all instructions in the basic block.
58 void visitBasicBlock(BasicBlock &LLVM_BB) {
59 BB = new MachineBasicBlock(&LLVM_BB);
60 // FIXME: Use the auto-insert form when it's available
61 F->getBasicBlockList().push_back(BB);
64 // Visitation methods for various instructions. These methods simply emit
65 // fixed X86 code for each instruction.
68 // Control flow operators
69 void visitReturnInst(ReturnInst &RI);
70 void visitBranchInst(BranchInst &BI);
71 void visitCallInst(CallInst &I);
73 // Arithmetic operators
74 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
75 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
76 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
77 void doMultiply(unsigned destReg, const Type *resultType,
78 unsigned op0Reg, unsigned op1Reg);
79 void visitMul(BinaryOperator &B);
81 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
82 void visitRem(BinaryOperator &B) { visitDivRem(B); }
83 void visitDivRem(BinaryOperator &B);
86 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
87 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
88 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
90 // Binary comparison operators
91 void visitSetCCInst(SetCondInst &I, unsigned OpNum);
92 void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
93 void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
94 void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
95 void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
96 void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
97 void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
99 // Memory Instructions
100 void visitLoadInst(LoadInst &I);
101 void visitStoreInst(StoreInst &I);
102 void visitGetElementPtrInst(GetElementPtrInst &I);
103 void visitMallocInst(MallocInst &I);
104 void visitFreeInst(FreeInst &I);
105 void visitAllocaInst(AllocaInst &I);
108 void visitShiftInst(ShiftInst &I);
109 void visitPHINode(PHINode &I);
110 void visitCastInst(CastInst &I);
112 void visitInstruction(Instruction &I) {
113 std::cerr << "Cannot instruction select: " << I;
117 void promote32(unsigned targetReg, Value *V);
119 // emitGEPOperation - Common code shared between visitGetElemenPtrInst and
120 // constant expression GEP support.
122 void emitGEPOperation(Value *Src, User::op_iterator IdxBegin,
123 User::op_iterator IdxEnd, unsigned TargetReg);
125 /// copyConstantToRegister - Output the instructions required to put the
126 /// specified constant into the specified register.
128 void copyConstantToRegister(Constant *C, unsigned Reg);
130 /// makeAnotherReg - This method returns the next register number
131 /// we haven't yet used.
132 unsigned makeAnotherReg(const Type *Ty) {
133 // Add the mapping of regnumber => reg class to MachineFunction
134 F->addRegMap(CurReg, TM.getRegisterInfo()->getRegClassForType(Ty));
138 /// getReg - This method turns an LLVM value into a register number. This
139 /// is guaranteed to produce the same register number for a particular value
140 /// every time it is queried.
142 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
143 unsigned getReg(Value *V) {
144 unsigned &Reg = RegMap[V];
146 Reg = makeAnotherReg(V->getType());
150 // If this operand is a constant, emit the code to copy the constant into
151 // the register here...
153 if (Constant *C = dyn_cast<Constant>(V)) {
154 copyConstantToRegister(C, Reg);
155 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
156 // Move the address of the global into the register
157 BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV);
158 } else if (Argument *A = dyn_cast<Argument>(V)) {
159 std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n";
167 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
171 cByte, cShort, cInt, cLong, cFloat, cDouble
174 /// getClass - Turn a primitive type into a "class" number which is based on the
175 /// size of the type, and whether or not it is floating point.
177 static inline TypeClass getClass(const Type *Ty) {
178 switch (Ty->getPrimitiveID()) {
179 case Type::SByteTyID:
180 case Type::UByteTyID: return cByte; // Byte operands are class #0
181 case Type::ShortTyID:
182 case Type::UShortTyID: return cShort; // Short operands are class #1
185 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
188 case Type::ULongTyID: //return cLong; // Longs are class #3
189 return cInt; // FIXME: LONGS ARE TREATED AS INTS!
191 case Type::FloatTyID: return cFloat; // Float is class #4
192 case Type::DoubleTyID: return cDouble; // Doubles are class #5
194 assert(0 && "Invalid type to getClass!");
195 return cByte; // not reached
200 /// copyConstantToRegister - Output the instructions required to put the
201 /// specified constant into the specified register.
203 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
204 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
205 if (CE->getOpcode() == Instruction::GetElementPtr) {
206 emitGEPOperation(CE->getOperand(0), CE->op_begin()+1, CE->op_end(), R);
210 std::cerr << "Offending expr: " << C << "\n";
211 assert (0 && "Constant expressions not yet handled!\n");
214 if (C->getType()->isIntegral()) {
215 unsigned Class = getClass(C->getType());
216 assert(Class != 3 && "Type not handled yet!");
218 static const unsigned IntegralOpcodeTab[] = {
219 X86::MOVir8, X86::MOVir16, X86::MOVir32
222 if (C->getType()->isSigned()) {
223 ConstantSInt *CSI = cast<ConstantSInt>(C);
224 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
226 ConstantUInt *CUI = cast<ConstantUInt>(C);
227 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
229 } else if (isa <ConstantPointerNull> (C)) {
230 // Copy zero (null pointer) to the register.
231 BuildMI (BB, X86::MOVir32, 1, R).addZImm(0);
232 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
233 unsigned SrcReg = getReg(CPR->getValue());
234 BuildMI (BB, X86::MOVrr32, 1, R).addReg(SrcReg);
236 std::cerr << "Offending constant: " << C << "\n";
237 assert(0 && "Type not handled yet!");
242 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
243 /// register, then move it to wherever the result should be.
244 /// We handle FP setcc instructions by pushing them, doing a
245 /// compare-and-pop-twice, and then copying the concodes to the main
246 /// processor's concodes (I didn't make this up, it's in the Intel manual)
248 void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
249 // The arguments are already supposed to be of the same type.
250 const Type *CompTy = I.getOperand(0)->getType();
251 unsigned reg1 = getReg(I.getOperand(0));
252 unsigned reg2 = getReg(I.getOperand(1));
254 unsigned Class = getClass(CompTy);
256 // Emit: cmp <var1>, <var2> (do the comparison). We can
257 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
260 BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
263 BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
266 BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
269 // Push the variables on the stack with fldl opcodes.
270 // FIXME: assuming var1, var2 are in memory, if not, spill to
272 case cFloat: // Floats
273 BuildMI (BB, X86::FLDr32, 1).addReg (reg1);
274 BuildMI (BB, X86::FLDr32, 1).addReg (reg2);
276 case cDouble: // Doubles
277 BuildMI (BB, X86::FLDr64, 1).addReg (reg1);
278 BuildMI (BB, X86::FLDr64, 1).addReg (reg2);
285 if (CompTy->isFloatingPoint()) {
286 // (Non-trapping) compare and pop twice.
287 BuildMI (BB, X86::FUCOMPP, 0);
288 // Move fp status word (concodes) to ax.
289 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
290 // Load real concodes from ax.
291 BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
294 // Emit setOp instruction (extract concode; clobbers ax),
295 // using the following mapping:
296 // LLVM -> X86 signed X86 unsigned
298 // seteq -> sete sete
299 // setne -> setne setne
300 // setlt -> setl setb
301 // setgt -> setg seta
302 // setle -> setle setbe
303 // setge -> setge setae
305 static const unsigned OpcodeTab[2][6] = {
306 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
307 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
310 BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
312 // Put it in the result using a move.
313 BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
316 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
317 /// operand, in the specified target register.
319 ISel::promote32 (unsigned targetReg, Value *v)
321 unsigned vReg = getReg (v);
322 unsigned Class = getClass (v->getType ());
323 bool isUnsigned = v->getType ()->isUnsigned ();
324 assert (((Class == cByte) || (Class == cShort) || (Class == cInt))
325 && "Unpromotable operand class in promote32");
329 // Extend value into target register (8->32)
331 BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg);
333 BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg);
336 // Extend value into target register (16->32)
338 BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg);
340 BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg);
343 // Move value into target register (32->32)
344 BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg);
349 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
350 /// we have the following possibilities:
352 /// ret void: No return value, simply emit a 'ret' instruction
353 /// ret sbyte, ubyte : Extend value into EAX and return
354 /// ret short, ushort: Extend value into EAX and return
355 /// ret int, uint : Move value into EAX and return
356 /// ret pointer : Move value into EAX and return
357 /// ret long, ulong : Move value into EAX/EDX and return
358 /// ret float/double : Top of FP stack
361 ISel::visitReturnInst (ReturnInst &I)
363 if (I.getNumOperands () == 0)
365 // Emit a 'ret' instruction
366 BuildMI (BB, X86::RET, 0);
369 Value *rv = I.getOperand (0);
370 unsigned Class = getClass (rv->getType ());
373 // integral return values: extend or move into EAX and return.
377 promote32 (X86::EAX, rv);
379 // ret float/double: top of FP stack
381 case cFloat: // Floats
382 BuildMI (BB, X86::FLDr32, 1).addReg (getReg (rv));
384 case cDouble: // Doubles
385 BuildMI (BB, X86::FLDr64, 1).addReg (getReg (rv));
388 // ret long: use EAX(least significant 32 bits)/EDX (most
389 // significant 32)...uh, I think so Brain, but how do i call
390 // up the two parts of the value from inside this mouse
393 visitInstruction (I);
395 // Emit a 'ret' instruction
396 BuildMI (BB, X86::RET, 0);
399 /// visitBranchInst - Handle conditional and unconditional branches here. Note
400 /// that since code layout is frozen at this point, that if we are trying to
401 /// jump to a block that is the immediate successor of the current block, we can
402 /// just make a fall-through. (but we don't currently).
405 ISel::visitBranchInst (BranchInst & BI)
407 if (BI.isConditional ())
409 BasicBlock *ifTrue = BI.getSuccessor (0);
410 BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
412 // simplest thing I can think of: compare condition with zero,
413 // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
415 unsigned int condReg = getReg (BI.getCondition ());
416 BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
417 BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
418 BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
420 else // unconditional branch
422 BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
426 /// visitCallInst - Push args on stack and do a procedure call instruction.
428 ISel::visitCallInst (CallInst & CI)
430 // keep a counter of how many bytes we pushed on the stack
431 unsigned bytesPushed = 0;
433 // Push the arguments on the stack in reverse order, as specified by
435 for (unsigned i = CI.getNumOperands()-1; i >= 1; --i)
437 Value *v = CI.getOperand (i);
438 switch (getClass (v->getType ()))
442 // Promote V to 32 bits wide, and move the result into EAX,
444 promote32 (X86::EAX, v);
445 BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
450 unsigned Reg = getReg(v);
451 BuildMI (BB, X86::PUSHr32, 1).addReg(Reg);
456 // FIXME: long/ulong/double args not handled.
457 visitInstruction (CI);
461 // Emit a CALL instruction with PC-relative displacement.
462 BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ());
464 // Adjust the stack by `bytesPushed' amount if non-zero
466 BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed);
468 // If there is a return value, scavenge the result from the location the call
471 if (CI.getType() != Type::VoidTy) {
472 unsigned resultTypeClass = getClass (CI.getType ());
473 switch (resultTypeClass) {
477 // Integral results are in %eax, or the appropriate portion
479 static const unsigned regRegMove[] = {
480 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
482 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
483 BuildMI (BB, regRegMove[resultTypeClass], 1,
484 getReg (CI)).addReg (AReg[resultTypeClass]);
488 // Floating-point return values live in %st(0) (i.e., the top of
489 // the FP stack.) The general way to approach this is to do a
490 // FSTP to save the top of the FP stack on the real stack, then
491 // do a MOV to load the top of the real stack into the target
493 visitInstruction (CI); // FIXME: add the right args for the calls below
494 // BuildMI (BB, X86::FSTPm32, 0);
495 // BuildMI (BB, X86::MOVmr32, 0);
498 std::cerr << "Cannot get return value for call of type '"
499 << *CI.getType() << "'\n";
500 visitInstruction(CI);
505 /// visitSimpleBinary - Implement simple binary operators for integral types...
506 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
509 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
510 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
513 unsigned Class = getClass(B.getType());
514 if (Class > 2) // FIXME: Handle longs
517 static const unsigned OpcodeTab[][4] = {
518 // Arithmetic operators
519 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
520 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
523 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
524 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
525 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
528 unsigned Opcode = OpcodeTab[OperatorClass][Class];
529 unsigned Op0r = getReg(B.getOperand(0));
530 unsigned Op1r = getReg(B.getOperand(1));
531 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
534 /// doMultiply - Emit appropriate instructions to multiply together
535 /// the registers op0Reg and op1Reg, and put the result in destReg.
536 /// The type of the result should be given as resultType.
538 ISel::doMultiply(unsigned destReg, const Type *resultType,
539 unsigned op0Reg, unsigned op1Reg)
541 unsigned Class = getClass (resultType);
544 assert (Class <= 2 && "Someday, we will learn how to multiply"
545 "longs and floating-point numbers. This is not that day.");
547 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
548 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
549 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
550 unsigned Reg = Regs[Class];
552 // Emit a MOV to put the first operand into the appropriately-sized
554 BuildMI (BB, MovOpcode[Class], 1, Reg).addReg (op0Reg);
556 // Emit the appropriate multiply instruction.
557 BuildMI (BB, MulOpcode[Class], 1).addReg (op1Reg);
559 // Emit another MOV to put the result into the destination register.
560 BuildMI (BB, MovOpcode[Class], 1, destReg).addReg (Reg);
563 /// visitMul - Multiplies are not simple binary operators because they must deal
564 /// with the EAX register explicitly.
566 void ISel::visitMul(BinaryOperator &I) {
567 doMultiply (getReg (I), I.getType (),
568 getReg (I.getOperand (0)), getReg (I.getOperand (1)));
572 /// visitDivRem - Handle division and remainder instructions... these
573 /// instruction both require the same instructions to be generated, they just
574 /// select the result from a different register. Note that both of these
575 /// instructions work differently for signed and unsigned operands.
577 void ISel::visitDivRem(BinaryOperator &I) {
578 unsigned Class = getClass(I.getType());
579 if (Class > 2) // FIXME: Handle longs
582 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
583 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
584 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
585 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
586 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
588 static const unsigned DivOpcode[][4] = {
589 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
590 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
593 bool isSigned = I.getType()->isSigned();
594 unsigned Reg = Regs[Class];
595 unsigned ExtReg = ExtRegs[Class];
596 unsigned Op0Reg = getReg(I.getOperand(0));
597 unsigned Op1Reg = getReg(I.getOperand(1));
599 // Put the first operand into one of the A registers...
600 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
603 // Emit a sign extension instruction...
604 BuildMI(BB, ExtOpcode[Class], 0);
606 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
607 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
610 // Emit the appropriate divide or remainder instruction...
611 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
613 // Figure out which register we want to pick the result out of...
614 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
616 // Put the result into the destination register...
617 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
621 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
622 /// for constant immediate shift values, and for constant immediate
623 /// shift values equal to 1. Even the general case is sort of special,
624 /// because the shift amount has to be in CL, not just any old register.
626 void ISel::visitShiftInst (ShiftInst &I) {
627 unsigned Op0r = getReg (I.getOperand(0));
628 unsigned DestReg = getReg(I);
629 bool isLeftShift = I.getOpcode() == Instruction::Shl;
630 bool isOperandSigned = I.getType()->isUnsigned();
631 unsigned OperandClass = getClass(I.getType());
633 if (OperandClass > 2)
634 visitInstruction(I); // Can't handle longs yet!
636 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
638 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
639 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
640 unsigned char shAmt = CUI->getValue();
642 static const unsigned ConstantOperand[][4] = {
643 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
644 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
645 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
646 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
649 const unsigned *OpTab = // Figure out the operand table to use
650 ConstantOperand[isLeftShift*2+isOperandSigned];
652 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
653 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
657 // The shift amount is non-constant.
659 // In fact, you can only shift with a variable shift amount if
660 // that amount is already in the CL register, so we have to put it
664 // Emit: move cl, shiftAmount (put the shift amount in CL.)
665 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
667 // This is a shift right (SHR).
668 static const unsigned NonConstantOperand[][4] = {
669 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
670 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
671 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
672 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
675 const unsigned *OpTab = // Figure out the operand table to use
676 NonConstantOperand[isLeftShift*2+isOperandSigned];
678 BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
683 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
686 void ISel::visitLoadInst(LoadInst &I) {
687 unsigned Class = getClass(I.getType());
688 if (Class > 2) // FIXME: Handle longs and others...
691 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
693 unsigned AddressReg = getReg(I.getOperand(0));
694 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
698 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
701 void ISel::visitStoreInst(StoreInst &I) {
702 unsigned Class = getClass(I.getOperand(0)->getType());
703 if (Class > 2) // FIXME: Handle longs and others...
706 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
708 unsigned ValReg = getReg(I.getOperand(0));
709 unsigned AddressReg = getReg(I.getOperand(1));
710 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
714 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
716 void ISel::visitPHINode(PHINode &PN) {
717 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
719 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
720 // FIXME: This will put constants after the PHI nodes in the block, which
721 // is invalid. They should be put inline into the PHI node eventually.
723 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
724 MI->addPCDispOperand(PN.getIncomingBlock(i));
728 /// visitCastInst - Here we have various kinds of copying with or without
729 /// sign extension going on.
731 ISel::visitCastInst (CastInst &CI)
733 const Type *targetType = CI.getType ();
734 Value *operand = CI.getOperand (0);
735 unsigned int operandReg = getReg (operand);
736 const Type *sourceType = operand->getType ();
737 unsigned int destReg = getReg (CI);
739 // Currently we handle:
743 // 2) cast {sbyte, ubyte} to {sbyte, ubyte}
744 // cast {short, ushort} to {ushort, short}
745 // cast {int, uint, ptr} to {int, uint, ptr}
747 // 3) cast {sbyte, ubyte} to {ushort, short}
748 // cast {sbyte, ubyte} to {int, uint, ptr}
749 // cast {short, ushort} to {int, uint, ptr}
751 // 4) cast {int, uint, ptr} to {short, ushort}
752 // cast {int, uint, ptr} to {sbyte, ubyte}
753 // cast {short, ushort} to {sbyte, ubyte}
755 // 1) Implement casts to bool by using compare on the operand followed
756 // by set if not zero on the result.
757 if (targetType == Type::BoolTy)
759 BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
760 BuildMI (BB, X86::SETNEr, 1, destReg);
763 // 2) Implement casts between values of the same type class (as determined
764 // by getClass) by using a register-to-register move.
765 unsigned int srcClass = getClass (sourceType);
766 unsigned int targClass = getClass (targetType);
767 static const unsigned regRegMove[] = {
768 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
770 if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass))
772 BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg);
775 // 3) Handle cast of SMALLER int to LARGER int using a move with sign
776 // extension or zero extension, depending on whether the source type
778 if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass))
780 static const unsigned ops[] = {
781 X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16,
782 X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16
784 unsigned srcSigned = sourceType->isSigned ();
785 BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1,
786 destReg).addReg (operandReg);
789 // 4) Handle cast of LARGER int to SMALLER int using a move to EAX
790 // followed by a move out of AX or AL.
791 if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass))
793 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
794 BuildMI (BB, regRegMove[srcClass], 1,
795 AReg[srcClass]).addReg (operandReg);
796 BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]);
799 // Anything we haven't handled already, we can't (yet) handle at all.
801 // FP to integral casts can be handled with FISTP to store onto the
802 // stack while converting to integer, followed by a MOV to load from
803 // the stack into the result register. Integral to FP casts can be
804 // handled with MOV to store onto the stack, followed by a FILD to
805 // load from the stack while converting to FP. For the moment, I
806 // can't quite get straight in my head how to borrow myself some
807 // stack space and write on it. Otherwise, this would be trivial.
808 visitInstruction (CI);
811 /// visitGetElementPtrInst - I don't know, most programs don't have
812 /// getelementptr instructions, right? That means we can put off
813 /// implementing this, right? Right. This method emits machine
814 /// instructions to perform type-safe pointer arithmetic. I am
815 /// guessing this could be cleaned up somewhat to use fewer temporary
818 ISel::visitGetElementPtrInst (GetElementPtrInst &I)
820 emitGEPOperation(I.getOperand(0), I.op_begin()+1, I.op_end(), getReg(I));
823 void ISel::emitGEPOperation(Value *Src, User::op_iterator IdxBegin,
824 User::op_iterator IdxEnd, unsigned TargetReg) {
825 const TargetData &TD = TM.getTargetData();
826 const Type *Ty = Src->getType();
827 unsigned basePtrReg = getReg(Src);
829 // GEPs have zero or more indices; we must perform a struct access
830 // or array access for each one.
831 for (GetElementPtrInst::op_iterator oi = IdxBegin,
832 oe = IdxEnd; oi != oe; ++oi) {
834 unsigned nextBasePtrReg = makeAnotherReg(Type::UIntTy);
835 if (const StructType *StTy = dyn_cast <StructType> (Ty)) {
836 // It's a struct access. idx is the index into the structure,
837 // which names the field. This index must have ubyte type.
838 const ConstantUInt *CUI = cast <ConstantUInt> (idx);
839 assert (CUI->getType () == Type::UByteTy
840 && "Funny-looking structure index in GEP");
841 // Use the TargetData structure to pick out what the layout of
842 // the structure is in memory. Since the structure index must
843 // be constant, we can get its value and use it to find the
844 // right byte offset from the StructLayout class's list of
845 // structure member offsets.
846 unsigned idxValue = CUI->getValue ();
847 unsigned memberOffset =
848 TD.getStructLayout (StTy)->MemberOffsets[idxValue];
849 // Emit an ADD to add memberOffset to the basePtr.
850 BuildMI (BB, X86::ADDri32, 2,
851 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
852 // The next type is the member of the structure selected by the
854 Ty = StTy->getElementTypes ()[idxValue];
855 } else if (const SequentialType *SqTy = cast <SequentialType> (Ty)) {
856 // It's an array or pointer access: [ArraySize x ElementType].
857 const Type *typeOfSequentialTypeIndex = SqTy->getIndexType ();
858 // idx is the index into the array. Unlike with structure
859 // indices, we may not know its actual value at code-generation
861 assert (idx->getType () == typeOfSequentialTypeIndex
862 && "Funny-looking array index in GEP");
863 // We want to add basePtrReg to (idxReg * sizeof
864 // ElementType). First, we must find the size of the pointed-to
865 // type. (Not coincidentally, the next type is the type of the
866 // elements in the array.)
867 Ty = SqTy->getElementType ();
868 unsigned elementSize = TD.getTypeSize (Ty);
869 unsigned elementSizeReg = makeAnotherReg(Type::UIntTy);
870 copyConstantToRegister (ConstantInt::get (typeOfSequentialTypeIndex,
873 unsigned idxReg = getReg (idx);
874 // Emit a MUL to multiply the register holding the index by
875 // elementSize, putting the result in memberOffsetReg.
876 unsigned memberOffsetReg = makeAnotherReg(Type::UIntTy);
877 doMultiply (memberOffsetReg, typeOfSequentialTypeIndex,
878 elementSizeReg, idxReg);
879 // Emit an ADD to add memberOffsetReg to the basePtr.
880 BuildMI (BB, X86::ADDrr32, 2,
881 nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg);
883 // Now that we are here, further indices refer to subtypes of this
884 // one, so we don't need to worry about basePtrReg itself, anymore.
885 basePtrReg = nextBasePtrReg;
887 // After we have processed all the indices, the result is left in
888 // basePtrReg. Move it to the register where we were expected to
889 // put the answer. A 32-bit move should do it, because we are in
891 BuildMI (BB, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg);
895 /// visitMallocInst - I know that personally, whenever I want to remember
896 /// something, I have to clear off some space in my brain.
898 ISel::visitMallocInst (MallocInst &I)
900 // We assume that by this point, malloc instructions have been
901 // lowered to calls, and dlsym will magically find malloc for us.
902 // So we do not want to see malloc instructions here.
903 visitInstruction (I);
907 /// visitFreeInst - same story as MallocInst
909 ISel::visitFreeInst (FreeInst &I)
911 // We assume that by this point, free instructions have been
912 // lowered to calls, and dlsym will magically find free for us.
913 // So we do not want to see free instructions here.
914 visitInstruction (I);
918 /// visitAllocaInst - I want some stack space. Come on, man, I said I
919 /// want some freakin' stack space.
921 ISel::visitAllocaInst (AllocaInst &I)
923 // Find the data size of the alloca inst's getAllocatedType.
924 const Type *allocatedType = I.getAllocatedType ();
925 const TargetData &TD = TM.DataLayout;
926 unsigned allocatedTypeSize = TD.getTypeSize (allocatedType);
927 // Keep stack 32-bit aligned.
928 unsigned int allocatedTypeWords = allocatedTypeSize / 4;
929 if (allocatedTypeSize % 4 != 0) { allocatedTypeWords++; }
930 // Subtract size from stack pointer, thereby allocating some space.
931 BuildMI (BB, X86::SUBri32, 1, X86::ESP).addZImm (allocatedTypeWords * 4);
932 // Put a pointer to the space into the result register, by copying
933 // the stack pointer.
934 BuildMI (BB, X86::MOVrr32, 1, getReg (I)).addReg (X86::ESP);
938 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
939 /// into a machine code representation is a very simple peep-hole fashion. The
940 /// generated code sucks but the implementation is nice and simple.
942 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {