1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
90 /// operand, usually produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
95 SETCC_CARRY, // R = carry_bit ? ~0 : 0
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
98 /// Operands are two FP values to compare; result is a mask of
99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
103 /// result in an integer GPR. Needs masking for scalar result.
106 /// X86 conditional moves. Operand 0 and operand 1 are the two values
107 /// to select from. Operand 2 is the condition code, and operand 3 is the
108 /// flag operand produced by a CMP or TEST instruction. It also writes a
112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
113 /// is the block to branch if condition is true, operand 2 is the
114 /// condition code, and operand 3 is the flag operand produced by a CMP
115 /// or TEST instruction.
118 /// Return with a flag operand. Operand 0 is the chain operand, operand
119 /// 1 is the number of bytes of stack to pop.
122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
129 /// at function entry, used for PIC code.
132 /// Wrapper - A wrapper node for TargetConstantPool,
133 /// TargetExternalSymbol, and TargetGlobalAddress.
136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
137 /// relative displacements.
140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
141 /// of an XMM vector, with the high word zero filled.
144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145 /// to an MMX vector. If you think this is too close to the previous
146 /// mnemonic, so do I; blame Intel.
149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
150 /// i32, corresponds to X86::PEXTRB.
153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
154 /// i32, corresponds to X86::PEXTRW.
157 /// INSERTPS - Insert any element of a 4 x float vector into any element
158 /// of a destination 4 x floatvector.
161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
162 /// corresponds to X86::PINSRB.
165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
166 /// corresponds to X86::PINSRW.
169 /// PSHUFB - Shuffle 16 8-bit values within a vector.
172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
175 /// PSIGN - Copy integer sign.
178 /// BLENDV - Blend where the selector is an XMM.
181 /// BLENDxx - Blend where the selector is an immediate.
186 /// HADD - Integer horizontal add.
189 /// HSUB - Integer horizontal sub.
192 /// FHADD - Floating point horizontal add.
195 /// FHSUB - Floating point horizontal sub.
198 /// FMAX, FMIN - Floating point max and min.
202 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
203 /// approximation. Note that these typically require refinement
204 /// in order to obtain suitable precision.
207 // TLSADDR - Thread Local Storage.
210 // TLSBASEADDR - Thread Local Storage. A call to get the start address
211 // of the TLS block for the current module.
214 // TLSCALL - Thread Local Storage. When calling to an OS provided
215 // thunk at the address from an earlier relocation.
218 // EH_RETURN - Exception Handling helpers.
221 /// TC_RETURN - Tail call return.
223 /// operand #1 callee (register or absolute)
224 /// operand #2 stack adjustment
225 /// operand #3 optional in flag
228 // VZEXT_MOVL - Vector move low and zero extend.
231 // VSEXT_MOVL - Vector move low and sign extend.
234 // VSHL, VSRL - 128-bit vector logical left / right shift
237 // VSHL, VSRL, VSRA - Vector shift elements
240 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
243 // CMPP - Vector packed double/float comparison.
246 // PCMP* - Vector integer comparisons.
249 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
250 ADD, SUB, ADC, SBB, SMUL,
251 INC, DEC, OR, XOR, AND,
253 ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
255 BLSI, // BLSI - Extract lowest set isolated bit
256 BLSMSK, // BLSMSK - Get mask up to lowest set bit
257 BLSR, // BLSR - Reset lowest set bit
259 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
261 // MUL_IMM - X86 specific multiply by immediate.
264 // PTEST - Vector bitwise comparisons
267 // TESTP - Vector packed fp sign bitwise comparisons
270 // Several flavors of instructions with vector shuffle behaviors.
294 // PMULUDQ - Vector multiply packed unsigned doubleword integers
305 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
306 // according to %al. An operator is needed so that this can be expanded
307 // with control flow.
308 VASTART_SAVE_XMM_REGS,
310 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
313 // SEG_ALLOCA - For allocating variable amounts of stack space when using
314 // segmented stacks. Check if the current stacklet has enough space, and
315 // falls back to heap allocation if not.
318 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
327 // FNSTSW16r - Store FP status word into i16 register.
330 // SAHF - Store contents of %ah into %eflags.
333 // RDRAND - Get a random integer and indicate whether it is valid in CF.
340 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
341 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
342 // Atomic 64-bit binary operations.
343 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
351 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
356 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
359 // FNSTCW16m - Store FP control world into i16 memory.
362 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
363 /// integer destination in memory and a FP reg source. This corresponds
364 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
365 /// has two inputs (token chain and address) and two outputs (int value
366 /// and token chain).
371 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
372 /// integer source in memory and FP reg result. This corresponds to the
373 /// X86::FILD*m instructions. It has three inputs (token chain, address,
374 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
375 /// also produces a flag).
379 /// FLD - This instruction implements an extending load to FP stack slots.
380 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
381 /// operand, ptr to load from, and a ValueType node indicating the type
385 /// FST - This instruction implements a truncating store to FP stack
386 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
387 /// chain operand, value to store, address, and a ValueType to store it
391 /// VAARG_64 - This instruction grabs the address of the next argument
392 /// from a va_list. (reads and modifies the va_list in memory)
395 // WARNING: Do not add anything in the end unless you want the node to
396 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
397 // thought as target memory ops!
401 /// Define some predicates that are used for node matching.
403 /// isVEXTRACTF128Index - Return true if the specified
404 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
405 /// suitable for input to VEXTRACTF128.
406 bool isVEXTRACTF128Index(SDNode *N);
408 /// isVINSERTF128Index - Return true if the specified
409 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
410 /// suitable for input to VINSERTF128.
411 bool isVINSERTF128Index(SDNode *N);
413 /// getExtractVEXTRACTF128Immediate - Return the appropriate
414 /// immediate to extract the specified EXTRACT_SUBVECTOR index
415 /// with VEXTRACTF128 instructions.
416 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
418 /// getInsertVINSERTF128Immediate - Return the appropriate
419 /// immediate to insert at the specified INSERT_SUBVECTOR index
420 /// with VINSERTF128 instructions.
421 unsigned getInsertVINSERTF128Immediate(SDNode *N);
423 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
425 bool isZeroNode(SDValue Elt);
427 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
428 /// fit into displacement field of the instruction.
429 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
430 bool hasSymbolicDisplacement = true);
433 /// isCalleePop - Determines whether the callee is required to pop its
434 /// own arguments. Callee pop is necessary to support tail calls.
435 bool isCalleePop(CallingConv::ID CallingConv,
436 bool is64Bit, bool IsVarArg, bool TailCallOpt);
439 //===--------------------------------------------------------------------===//
440 // X86TargetLowering - X86 Implementation of the TargetLowering interface
441 class X86TargetLowering : public TargetLowering {
443 explicit X86TargetLowering(X86TargetMachine &TM);
445 virtual unsigned getJumpTableEncoding() const;
447 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
449 virtual const MCExpr *
450 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
451 const MachineBasicBlock *MBB, unsigned uid,
452 MCContext &Ctx) const;
454 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
456 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
457 SelectionDAG &DAG) const;
458 virtual const MCExpr *
459 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
460 unsigned JTI, MCContext &Ctx) const;
462 /// getStackPtrReg - Return the stack pointer register we are using: either
464 unsigned getStackPtrReg() const { return X86StackPtr; }
466 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
467 /// function arguments in the caller parameter area. For X86, aggregates
468 /// that contains are placed at 16-byte boundaries while the rest are at
469 /// 4-byte boundaries.
470 virtual unsigned getByValTypeAlignment(Type *Ty) const;
472 /// getOptimalMemOpType - Returns the target specific optimal type for load
473 /// and store operations as a result of memset, memcpy, and memmove
474 /// lowering. If DstAlign is zero that means it's safe to destination
475 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
476 /// means there isn't a need to check it against alignment requirement,
477 /// probably because the source does not need to be loaded. If
478 /// 'IsZeroVal' is true, that means it's safe to return a
479 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
480 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
481 /// constant so it does not need to be loaded.
482 /// It returns EVT::Other if the type should be determined using generic
483 /// target-independent logic.
485 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
486 bool IsZeroVal, bool MemcpyStrSrc,
487 MachineFunction &MF) const;
489 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
490 /// unaligned memory accesses. of the specified type.
491 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
495 /// LowerOperation - Provide custom lowering hooks for some operations.
497 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
499 /// ReplaceNodeResults - Replace the results of node with an illegal result
500 /// type with new values built out of custom code.
502 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
503 SelectionDAG &DAG) const;
506 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
508 /// isTypeDesirableForOp - Return true if the target has native support for
509 /// the specified value type and it is 'desirable' to use the type for the
510 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
511 /// instruction encodings are longer and some i16 instructions are slow.
512 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
514 /// isTypeDesirable - Return true if the target has native support for the
515 /// specified value type and it is 'desirable' to use the type. e.g. On x86
516 /// i16 is legal, but undesirable since i16 instruction encodings are longer
517 /// and some i16 instructions are slow.
518 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
520 virtual MachineBasicBlock *
521 EmitInstrWithCustomInserter(MachineInstr *MI,
522 MachineBasicBlock *MBB) const;
525 /// getTargetNodeName - This method returns the name of a target specific
527 virtual const char *getTargetNodeName(unsigned Opcode) const;
529 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
530 virtual EVT getSetCCResultType(EVT VT) const;
532 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
533 /// in Mask are known to be either zero or one and return them in the
534 /// KnownZero/KnownOne bitsets.
535 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
538 const SelectionDAG &DAG,
539 unsigned Depth = 0) const;
541 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
542 // operation that are sign bits.
543 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
544 unsigned Depth) const;
547 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
549 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
551 virtual bool ExpandInlineAsm(CallInst *CI) const;
553 ConstraintType getConstraintType(const std::string &Constraint) const;
555 /// Examine constraint string and operand type and determine a weight value.
556 /// The operand object must already have been set up with the operand type.
557 virtual ConstraintWeight getSingleConstraintMatchWeight(
558 AsmOperandInfo &info, const char *constraint) const;
560 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
562 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
563 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
564 /// true it means one of the asm constraint of the inline asm instruction
565 /// being processed is 'm'.
566 virtual void LowerAsmOperandForConstraint(SDValue Op,
567 std::string &Constraint,
568 std::vector<SDValue> &Ops,
569 SelectionDAG &DAG) const;
571 /// getRegForInlineAsmConstraint - Given a physical register constraint
572 /// (e.g. {edx}), return the register number and the register class for the
573 /// register. This should only be used for C_Register constraints. On
574 /// error, this returns a register number of 0.
575 std::pair<unsigned, const TargetRegisterClass*>
576 getRegForInlineAsmConstraint(const std::string &Constraint,
579 /// isLegalAddressingMode - Return true if the addressing mode represented
580 /// by AM is legal for this target, for a load/store of the specified type.
581 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
583 /// isLegalICmpImmediate - Return true if the specified immediate is legal
584 /// icmp immediate, that is the target has icmp instructions which can
585 /// compare a register against the immediate without having to materialize
586 /// the immediate into a register.
587 virtual bool isLegalICmpImmediate(int64_t Imm) const;
589 /// isLegalAddImmediate - Return true if the specified immediate is legal
590 /// add immediate, that is the target has add instructions which can
591 /// add a register and the immediate without having to materialize
592 /// the immediate into a register.
593 virtual bool isLegalAddImmediate(int64_t Imm) const;
595 /// isTruncateFree - Return true if it's free to truncate a value of
596 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
597 /// register EAX to i16 by referencing its sub-register AX.
598 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
599 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
601 /// isZExtFree - Return true if any actual instruction that defines a
602 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
603 /// register. This does not necessarily include registers defined in
604 /// unknown ways, such as incoming arguments, or copies from unknown
605 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
606 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
607 /// all instructions that define 32-bit values implicit zero-extend the
608 /// result out to 64 bits.
609 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
610 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
612 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
613 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
614 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
615 /// is expanded to mul + add.
616 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
618 /// isNarrowingProfitable - Return true if it's profitable to narrow
619 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
620 /// from i32 to i8 but not from i32 to i16.
621 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
623 /// isFPImmLegal - Returns true if the target can instruction select the
624 /// specified FP immediate natively. If false, the legalizer will
625 /// materialize the FP immediate as a load from a constant pool.
626 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
628 /// isShuffleMaskLegal - Targets can use this to indicate that they only
629 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
630 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
631 /// values are assumed to be legal.
632 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
635 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
636 /// used by Targets can use this to indicate if there is a suitable
637 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
639 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
642 /// ShouldShrinkFPConstant - If true, then instruction selection should
643 /// seek to shrink the FP constant of the specified type to a smaller type
644 /// in order to save space and / or reduce runtime.
645 virtual bool ShouldShrinkFPConstant(EVT VT) const {
646 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
647 // expensive than a straight movsd. On the other hand, it's important to
648 // shrink long double fp constant since fldt is very slow.
649 return !X86ScalarSSEf64 || VT == MVT::f80;
652 const X86Subtarget* getSubtarget() const {
656 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
657 /// computed in an SSE register, not on the X87 floating point stack.
658 bool isScalarFPTypeInSSEReg(EVT VT) const {
659 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
660 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
663 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
665 bool isTargetFTOL() const {
666 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
669 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
670 /// used for fptoui to the given type.
671 bool isIntegerTypeFTOL(EVT VT) const {
672 return isTargetFTOL() && VT == MVT::i64;
675 /// createFastISel - This method returns a target specific FastISel object,
676 /// or null if the target does not support "fast" ISel.
677 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
678 const TargetLibraryInfo *libInfo) const;
680 /// getStackCookieLocation - Return true if the target stores stack
681 /// protector cookies at a fixed offset in some non-standard address
682 /// space, and populates the address space and offset as
684 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
686 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
687 SelectionDAG &DAG) const;
690 std::pair<const TargetRegisterClass*, uint8_t>
691 findRepresentativeClass(EVT VT) const;
694 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
695 /// make the right decision when generating code for different targets.
696 const X86Subtarget *Subtarget;
697 const X86RegisterInfo *RegInfo;
698 const TargetData *TD;
700 /// X86StackPtr - X86 physical register used as stack ptr.
701 unsigned X86StackPtr;
703 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
704 /// floating point ops.
705 /// When SSE is available, use it for f32 operations.
706 /// When SSE2 is available, use it for f64 operations.
707 bool X86ScalarSSEf32;
708 bool X86ScalarSSEf64;
710 /// LegalFPImmediates - A list of legal fp immediates.
711 std::vector<APFloat> LegalFPImmediates;
713 /// addLegalFPImmediate - Indicate that this x86 target can instruction
714 /// select the specified FP immediate natively.
715 void addLegalFPImmediate(const APFloat& Imm) {
716 LegalFPImmediates.push_back(Imm);
719 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
720 CallingConv::ID CallConv, bool isVarArg,
721 const SmallVectorImpl<ISD::InputArg> &Ins,
722 DebugLoc dl, SelectionDAG &DAG,
723 SmallVectorImpl<SDValue> &InVals) const;
724 SDValue LowerMemArgument(SDValue Chain,
725 CallingConv::ID CallConv,
726 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
727 DebugLoc dl, SelectionDAG &DAG,
728 const CCValAssign &VA, MachineFrameInfo *MFI,
730 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
731 DebugLoc dl, SelectionDAG &DAG,
732 const CCValAssign &VA,
733 ISD::ArgFlagsTy Flags) const;
735 // Call lowering helpers.
737 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
738 /// for tail call optimization. Targets which want to do tail call
739 /// optimization should implement this function.
740 bool IsEligibleForTailCallOptimization(SDValue Callee,
741 CallingConv::ID CalleeCC,
743 bool isCalleeStructRet,
744 bool isCallerStructRet,
745 const SmallVectorImpl<ISD::OutputArg> &Outs,
746 const SmallVectorImpl<SDValue> &OutVals,
747 const SmallVectorImpl<ISD::InputArg> &Ins,
748 SelectionDAG& DAG) const;
749 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
750 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
751 SDValue Chain, bool IsTailCall, bool Is64Bit,
752 int FPDiff, DebugLoc dl) const;
754 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
755 SelectionDAG &DAG) const;
757 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
759 bool isReplace) const;
761 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
762 SelectionDAG &DAG) const;
763 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
764 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
765 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
766 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
771 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
772 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
773 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
774 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
775 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
776 int64_t Offset, SelectionDAG &DAG) const;
777 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
782 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
785 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
790 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
791 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
792 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
793 DebugLoc dl, SelectionDAG &DAG) const;
794 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
804 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
805 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
807 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
810 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
814 SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
815 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
826 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
827 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
828 SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const;
830 // Utility functions to help LowerVECTOR_SHUFFLE
831 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const;
833 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
836 LowerFormalArguments(SDValue Chain,
837 CallingConv::ID CallConv, bool isVarArg,
838 const SmallVectorImpl<ISD::InputArg> &Ins,
839 DebugLoc dl, SelectionDAG &DAG,
840 SmallVectorImpl<SDValue> &InVals) const;
842 LowerCall(CallLoweringInfo &CLI,
843 SmallVectorImpl<SDValue> &InVals) const;
846 LowerReturn(SDValue Chain,
847 CallingConv::ID CallConv, bool isVarArg,
848 const SmallVectorImpl<ISD::OutputArg> &Outs,
849 const SmallVectorImpl<SDValue> &OutVals,
850 DebugLoc dl, SelectionDAG &DAG) const;
852 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
854 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
857 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
858 ISD::NodeType ExtendKind) const;
861 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
863 const SmallVectorImpl<ISD::OutputArg> &Outs,
864 LLVMContext &Context) const;
866 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
867 SelectionDAG &DAG, unsigned NewOp) const;
869 /// Utility function to emit string processing sse4.2 instructions
870 /// that return in xmm0.
871 /// This takes the instruction to expand, the associated machine basic
872 /// block, the number of args, and whether or not the second arg is
873 /// in memory or not.
874 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
875 unsigned argNum, bool inMem) const;
877 /// Utility functions to emit monitor and mwait instructions. These
878 /// need to make sure that the arguments to the intrinsic are in the
879 /// correct registers.
880 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
881 MachineBasicBlock *BB) const;
882 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
884 /// Utility function to emit atomic bitwise operations (and, or, xor).
885 /// It takes the bitwise instruction to expand, the associated machine basic
886 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
887 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
888 MachineInstr *BInstr,
889 MachineBasicBlock *BB,
896 const TargetRegisterClass *RC,
897 bool Invert = false) const;
899 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
900 MachineInstr *BInstr,
901 MachineBasicBlock *BB,
906 bool Invert = false) const;
908 /// Utility function to emit atomic min and max. It takes the min/max
909 /// instruction to expand, the associated basic block, and the associated
910 /// cmov opcode for moving the min or max value.
911 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
912 MachineBasicBlock *BB,
913 unsigned cmovOpc) const;
915 // Utility function to emit the low-level va_arg code for X86-64.
916 MachineBasicBlock *EmitVAARG64WithCustomInserter(
918 MachineBasicBlock *MBB) const;
920 /// Utility function to emit the xmm reg save portion of va_start.
921 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
922 MachineInstr *BInstr,
923 MachineBasicBlock *BB) const;
925 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
926 MachineBasicBlock *BB) const;
928 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
929 MachineBasicBlock *BB) const;
931 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
932 MachineBasicBlock *BB,
935 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
936 MachineBasicBlock *BB) const;
938 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
939 MachineBasicBlock *BB) const;
941 /// Emit nodes that will be selected as "test Op0,Op0", or something
942 /// equivalent, for use with the given x86 condition code.
943 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
945 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
946 /// equivalent, for use with the given x86 condition code.
947 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
948 SelectionDAG &DAG) const;
950 /// Convert a comparison if required by the subtarget.
951 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
955 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
956 const TargetLibraryInfo *libInfo);
960 #endif // X86ISELLOWERING_H