1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FSRL - Bitwise logical right shift of floating point values. These
56 /// corresponds to X86::PSRLDQ.
59 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
60 /// integer source in memory and FP reg result. This corresponds to the
61 /// X86::FILD*m instructions. It has three inputs (token chain, address,
62 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
63 /// also produces a flag).
67 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
68 /// integer destination in memory and a FP reg source. This corresponds
69 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
70 /// has two inputs (token chain and address) and two outputs (int value
76 /// FLD - This instruction implements an extending load to FP stack slots.
77 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
78 /// operand, ptr to load from, and a ValueType node indicating the type
82 /// FST - This instruction implements a truncating store to FP stack
83 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
84 /// chain operand, value to store, address, and a ValueType to store it
88 /// CALL - These operations represent an abstract X86 call
89 /// instruction, which includes a bunch of information. In particular the
90 /// operands of these node are:
92 /// #0 - The incoming token chain
94 /// #2 - The number of arg bytes the caller pushes on the stack.
95 /// #3 - The number of arg bytes the callee pops off the stack.
96 /// #4 - The value to pass in AL/AX/EAX (optional)
97 /// #5 - The value to pass in DL/DX/EDX (optional)
99 /// The result values of these nodes are:
101 /// #0 - The outgoing token chain
102 /// #1 - The first register result value (optional)
103 /// #2 - The second register result value (optional)
107 /// RDTSC_DAG - This operation implements the lowering for
111 /// X86 compare and logical compare instructions.
114 /// X86 bit-test instructions.
117 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
118 /// operand produced by a CMP instruction.
121 // Same as SETCC except it's materialized with a sbb and the value is all
122 // one's or all zero's.
125 /// X86 conditional moves. Operand 0 and operand 1 are the two values
126 /// to select from. Operand 2 is the condition code, and operand 3 is the
127 /// flag operand produced by a CMP or TEST instruction. It also writes a
131 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
132 /// is the block to branch if condition is true, operand 2 is the
133 /// condition code, and operand 3 is the flag operand produced by a CMP
134 /// or TEST instruction.
137 /// Return with a flag operand. Operand 0 is the chain operand, operand
138 /// 1 is the number of bytes of stack to pop.
141 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
144 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
147 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
148 /// at function entry, used for PIC code.
151 /// Wrapper - A wrapper node for TargetConstantPool,
152 /// TargetExternalSymbol, and TargetGlobalAddress.
155 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
156 /// relative displacements.
159 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
160 /// i32, corresponds to X86::PEXTRB.
163 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
164 /// i32, corresponds to X86::PEXTRW.
167 /// INSERTPS - Insert any element of a 4 x float vector into any element
168 /// of a destination 4 x floatvector.
171 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
172 /// corresponds to X86::PINSRB.
175 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
176 /// corresponds to X86::PINSRW.
179 /// PSHUFB - Shuffle 16 8-bit values within a vector.
182 /// FMAX, FMIN - Floating point max and min.
186 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
187 /// approximation. Note that these typically require refinement
188 /// in order to obtain suitable precision.
191 // TLSADDR - Thread Local Storage.
194 // SegmentBaseAddress - The address segment:0
197 // EH_RETURN - Exception Handling helpers.
200 /// TC_RETURN - Tail call return.
202 /// operand #1 callee (register or absolute)
203 /// operand #2 stack adjustment
204 /// operand #3 optional in flag
207 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
211 // FNSTCW16m - Store FP control world into i16 memory.
214 // VZEXT_MOVL - Vector move low and zero extend.
217 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
220 // VSHL, VSRL - Vector logical left / right shift.
223 // CMPPD, CMPPS - Vector double/float comparison.
224 // CMPPD, CMPPS - Vector double/float comparison.
227 // PCMP* - Vector integer comparisons.
228 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
229 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
231 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
232 ADD, SUB, SMUL, UMUL,
233 INC, DEC, OR, XOR, AND,
235 // MUL_IMM - X86 specific multiply by immediate.
238 // PTEST - Vector bitwise comparisons
241 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
242 // according to %al. An operator is needed so that this can be expanded
243 // with control flow.
244 VASTART_SAVE_XMM_REGS,
246 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
247 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
248 // Atomic 64-bit binary operations.
249 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
259 /// Define some predicates that are used for node matching.
261 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
262 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
263 bool isPSHUFDMask(ShuffleVectorSDNode *N);
265 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
266 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
267 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
269 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
270 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
271 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
273 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
274 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
275 bool isSHUFPMask(ShuffleVectorSDNode *N);
277 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
278 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
279 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
281 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
282 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
284 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
286 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
287 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
288 bool isMOVLPMask(ShuffleVectorSDNode *N);
290 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
291 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
292 /// as well as MOVLHPS.
293 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
295 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
296 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
297 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
301 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
303 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
304 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
306 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
308 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
309 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
311 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
313 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
314 /// specifies a shuffle of elements that is suitable for input to MOVSS,
315 /// MOVSD, and MOVD, i.e. setting the lowest element.
316 bool isMOVLMask(ShuffleVectorSDNode *N);
318 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
319 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
320 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
322 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
323 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
324 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
326 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
327 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
328 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
330 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
331 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
332 bool isPALIGNRMask(ShuffleVectorSDNode *N);
334 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
335 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
337 unsigned getShuffleSHUFImmediate(SDNode *N);
339 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
340 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
341 unsigned getShufflePSHUFHWImmediate(SDNode *N);
343 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
344 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
345 unsigned getShufflePSHUFLWImmediate(SDNode *N);
347 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
348 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
349 unsigned getShufflePALIGNRImmediate(SDNode *N);
351 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
353 bool isZeroNode(SDValue Elt);
355 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
356 /// fit into displacement field of the instruction.
357 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
358 bool hasSymbolicDisplacement = true);
361 //===--------------------------------------------------------------------===//
362 // X86TargetLowering - X86 Implementation of the TargetLowering interface
363 class X86TargetLowering : public TargetLowering {
364 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
365 int RegSaveFrameIndex; // X86-64 vararg func register save area.
366 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
367 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
368 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
369 int BytesCallerReserves; // Number of arg bytes caller makes.
372 explicit X86TargetLowering(X86TargetMachine &TM);
374 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
376 SDValue getPICJumpTableRelocBase(SDValue Table,
377 SelectionDAG &DAG) const;
379 // Return the number of bytes that a function should pop when it returns (in
380 // addition to the space used by the return address).
382 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
384 // Return the number of bytes that the caller reserves for arguments passed
386 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
388 /// getStackPtrReg - Return the stack pointer register we are using: either
390 unsigned getStackPtrReg() const { return X86StackPtr; }
392 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
393 /// function arguments in the caller parameter area. For X86, aggregates
394 /// that contains are placed at 16-byte boundaries while the rest are at
395 /// 4-byte boundaries.
396 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
398 /// getOptimalMemOpType - Returns the target specific optimal type for load
399 /// and store operations as a result of memset, memcpy, and memmove
400 /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
402 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
403 bool isSrcConst, bool isSrcStr,
404 SelectionDAG &DAG) const;
406 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
407 /// unaligned memory accesses. of the specified type.
408 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
412 /// LowerOperation - Provide custom lowering hooks for some operations.
414 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
416 /// ReplaceNodeResults - Replace the results of node with an illegal result
417 /// type with new values built out of custom code.
419 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
423 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
425 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
426 MachineBasicBlock *MBB,
427 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
430 /// getTargetNodeName - This method returns the name of a target specific
432 virtual const char *getTargetNodeName(unsigned Opcode) const;
434 /// getSetCCResultType - Return the ISD::SETCC ValueType
435 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
437 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
438 /// in Mask are known to be either zero or one and return them in the
439 /// KnownZero/KnownOne bitsets.
440 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
444 const SelectionDAG &DAG,
445 unsigned Depth = 0) const;
448 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
450 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
452 virtual bool ExpandInlineAsm(CallInst *CI) const;
454 ConstraintType getConstraintType(const std::string &Constraint) const;
456 std::vector<unsigned>
457 getRegClassForInlineAsmConstraint(const std::string &Constraint,
460 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
462 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
463 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
464 /// true it means one of the asm constraint of the inline asm instruction
465 /// being processed is 'm'.
466 virtual void LowerAsmOperandForConstraint(SDValue Op,
467 char ConstraintLetter,
469 std::vector<SDValue> &Ops,
470 SelectionDAG &DAG) const;
472 /// getRegForInlineAsmConstraint - Given a physical register constraint
473 /// (e.g. {edx}), return the register number and the register class for the
474 /// register. This should only be used for C_Register constraints. On
475 /// error, this returns a register number of 0.
476 std::pair<unsigned, const TargetRegisterClass*>
477 getRegForInlineAsmConstraint(const std::string &Constraint,
480 /// isLegalAddressingMode - Return true if the addressing mode represented
481 /// by AM is legal for this target, for a load/store of the specified type.
482 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
484 /// isTruncateFree - Return true if it's free to truncate a value of
485 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
486 /// register EAX to i16 by referencing its sub-register AX.
487 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
488 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
490 /// isZExtFree - Return true if any actual instruction that defines a
491 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
492 /// register. This does not necessarily include registers defined in
493 /// unknown ways, such as incoming arguments, or copies from unknown
494 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
495 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
496 /// all instructions that define 32-bit values implicit zero-extend the
497 /// result out to 64 bits.
498 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
499 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
501 /// isNarrowingProfitable - Return true if it's profitable to narrow
502 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
503 /// from i32 to i8 but not from i32 to i16.
504 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
506 /// isFPImmLegal - Returns true if the target can instruction select the
507 /// specified FP immediate natively. If false, the legalizer will
508 /// materialize the FP immediate as a load from a constant pool.
509 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
511 /// isShuffleMaskLegal - Targets can use this to indicate that they only
512 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
513 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
514 /// values are assumed to be legal.
515 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
518 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
519 /// used by Targets can use this to indicate if there is a suitable
520 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
522 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
525 /// ShouldShrinkFPConstant - If true, then instruction selection should
526 /// seek to shrink the FP constant of the specified type to a smaller type
527 /// in order to save space and / or reduce runtime.
528 virtual bool ShouldShrinkFPConstant(EVT VT) const {
529 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
530 // expensive than a straight movsd. On the other hand, it's important to
531 // shrink long double fp constant since fldt is very slow.
532 return !X86ScalarSSEf64 || VT == MVT::f80;
535 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
536 /// for tail call optimization. Targets which want to do tail call
537 /// optimization should implement this function.
539 IsEligibleForTailCallOptimization(SDValue Callee,
540 CallingConv::ID CalleeCC,
542 const SmallVectorImpl<ISD::InputArg> &Ins,
543 SelectionDAG& DAG) const;
545 virtual const X86Subtarget* getSubtarget() {
549 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
550 /// computed in an SSE register, not on the X87 floating point stack.
551 bool isScalarFPTypeInSSEReg(EVT VT) const {
552 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
553 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
556 /// getWidenVectorType: given a vector type, returns the type to widen
557 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
558 /// If there is no vector type that we want to widen to, returns EVT::Other
559 /// When and were to widen is target dependent based on the cost of
560 /// scalarizing vs using the wider vector type.
561 virtual EVT getWidenVectorType(EVT VT) const;
563 /// createFastISel - This method returns a target specific FastISel object,
564 /// or null if the target does not support "fast" ISel.
566 createFastISel(MachineFunction &mf,
567 MachineModuleInfo *mmi, DwarfWriter *dw,
568 DenseMap<const Value *, unsigned> &,
569 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
570 DenseMap<const AllocaInst *, int> &
572 , SmallSet<Instruction*, 8> &
576 /// getFunctionAlignment - Return the Log2 alignment of this function.
577 virtual unsigned getFunctionAlignment(const Function *F) const;
580 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
581 /// make the right decision when generating code for different targets.
582 const X86Subtarget *Subtarget;
583 const X86RegisterInfo *RegInfo;
584 const TargetData *TD;
586 /// X86StackPtr - X86 physical register used as stack ptr.
587 unsigned X86StackPtr;
589 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
590 /// floating point ops.
591 /// When SSE is available, use it for f32 operations.
592 /// When SSE2 is available, use it for f64 operations.
593 bool X86ScalarSSEf32;
594 bool X86ScalarSSEf64;
596 /// LegalFPImmediates - A list of legal fp immediates.
597 std::vector<APFloat> LegalFPImmediates;
599 /// addLegalFPImmediate - Indicate that this x86 target can instruction
600 /// select the specified FP immediate natively.
601 void addLegalFPImmediate(const APFloat& Imm) {
602 LegalFPImmediates.push_back(Imm);
605 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
606 CallingConv::ID CallConv, bool isVarArg,
607 const SmallVectorImpl<ISD::InputArg> &Ins,
608 DebugLoc dl, SelectionDAG &DAG,
609 SmallVectorImpl<SDValue> &InVals);
610 SDValue LowerMemArgument(SDValue Chain,
611 CallingConv::ID CallConv,
612 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
613 DebugLoc dl, SelectionDAG &DAG,
614 const CCValAssign &VA, MachineFrameInfo *MFI,
616 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
617 DebugLoc dl, SelectionDAG &DAG,
618 const CCValAssign &VA,
619 ISD::ArgFlagsTy Flags);
621 // Call lowering helpers.
622 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv);
623 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
624 SDValue Chain, bool IsTailCall, bool Is64Bit,
625 int FPDiff, DebugLoc dl);
627 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
628 NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv);
629 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
631 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
634 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
636 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
637 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
638 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
639 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
640 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
641 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
642 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
643 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
644 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
645 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
646 int64_t Offset, SelectionDAG &DAG) const;
647 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
648 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
649 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
650 SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
651 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
653 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
654 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG);
655 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG);
656 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG);
657 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
658 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG);
659 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
660 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
661 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
662 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
663 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
664 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
665 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
666 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
667 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
668 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
669 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
670 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
671 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
672 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
673 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
674 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
675 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
676 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
677 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
678 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
679 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
680 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
681 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG);
682 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG);
684 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
685 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
686 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG);
689 LowerFormalArguments(SDValue Chain,
690 CallingConv::ID CallConv, bool isVarArg,
691 const SmallVectorImpl<ISD::InputArg> &Ins,
692 DebugLoc dl, SelectionDAG &DAG,
693 SmallVectorImpl<SDValue> &InVals);
695 LowerCall(SDValue Chain, SDValue Callee,
696 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
697 const SmallVectorImpl<ISD::OutputArg> &Outs,
698 const SmallVectorImpl<ISD::InputArg> &Ins,
699 DebugLoc dl, SelectionDAG &DAG,
700 SmallVectorImpl<SDValue> &InVals);
703 LowerReturn(SDValue Chain,
704 CallingConv::ID CallConv, bool isVarArg,
705 const SmallVectorImpl<ISD::OutputArg> &Outs,
706 DebugLoc dl, SelectionDAG &DAG);
709 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
710 const SmallVectorImpl<EVT> &OutTys,
711 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
714 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
715 SelectionDAG &DAG, unsigned NewOp);
717 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
719 SDValue Dst, SDValue Src,
720 SDValue Size, unsigned Align,
721 const Value *DstSV, uint64_t DstSVOff);
722 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
724 SDValue Dst, SDValue Src,
725 SDValue Size, unsigned Align,
727 const Value *DstSV, uint64_t DstSVOff,
728 const Value *SrcSV, uint64_t SrcSVOff);
730 /// Utility function to emit string processing sse4.2 instructions
731 /// that return in xmm0.
732 /// This takes the instruction to expand, the associated machine basic
733 /// block, the number of args, and whether or not the second arg is
734 /// in memory or not.
735 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
736 unsigned argNum, bool inMem) const;
738 /// Utility function to emit atomic bitwise operations (and, or, xor).
739 /// It takes the bitwise instruction to expand, the associated machine basic
740 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
741 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
742 MachineInstr *BInstr,
743 MachineBasicBlock *BB,
751 TargetRegisterClass *RC,
752 bool invSrc = false) const;
754 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
755 MachineInstr *BInstr,
756 MachineBasicBlock *BB,
761 bool invSrc = false) const;
763 /// Utility function to emit atomic min and max. It takes the min/max
764 /// instruction to expand, the associated basic block, and the associated
765 /// cmov opcode for moving the min or max value.
766 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
767 MachineBasicBlock *BB,
768 unsigned cmovOpc) const;
770 /// Utility function to emit the xmm reg save portion of va_start.
771 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
772 MachineInstr *BInstr,
773 MachineBasicBlock *BB) const;
775 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
776 MachineBasicBlock *BB,
777 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
779 /// Emit nodes that will be selected as "test Op0,Op0", or something
780 /// equivalent, for use with the given x86 condition code.
781 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
783 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
784 /// equivalent, for use with the given x86 condition code.
785 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
790 FastISel *createFastISel(MachineFunction &mf,
791 MachineModuleInfo *mmi, DwarfWriter *dw,
792 DenseMap<const Value *, unsigned> &,
793 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
794 DenseMap<const AllocaInst *, int> &
796 , SmallSet<Instruction*, 8> &
802 #endif // X86ISELLOWERING_H