1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Target/TargetTransformImpl.h"
30 // X86 Specific DAG Nodes
32 // Start the numbering where the builtin ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 /// BSF - Bit scan forward.
36 /// BSR - Bit scan reverse.
40 /// SHLD, SHRD - Double shift instructions. These correspond to
41 /// X86::SHLDxx and X86::SHRDxx instructions.
45 /// FAND - Bitwise logical AND of floating point values. This corresponds
46 /// to X86::ANDPS or X86::ANDPD.
49 /// FOR - Bitwise logical OR of floating point values. This corresponds
50 /// to X86::ORPS or X86::ORPD.
53 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
54 /// to X86::XORPS or X86::XORPD.
57 /// FSRL - Bitwise logical right shift of floating point values. These
58 /// corresponds to X86::PSRLDQ.
61 /// CALL - These operations represent an abstract X86 call
62 /// instruction, which includes a bunch of information. In particular the
63 /// operands of these node are:
65 /// #0 - The incoming token chain
67 /// #2 - The number of arg bytes the caller pushes on the stack.
68 /// #3 - The number of arg bytes the callee pops off the stack.
69 /// #4 - The value to pass in AL/AX/EAX (optional)
70 /// #5 - The value to pass in DL/DX/EDX (optional)
72 /// The result values of these nodes are:
74 /// #0 - The outgoing token chain
75 /// #1 - The first register result value (optional)
76 /// #2 - The second register result value (optional)
80 /// RDTSC_DAG - This operation implements the lowering for
84 /// X86 compare and logical compare instructions.
87 /// X86 bit-test instructions.
90 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
91 /// operand, usually produced by a CMP instruction.
94 // Same as SETCC except it's materialized with a sbb and the value is all
95 // one's or all zero's.
96 SETCC_CARRY, // R = carry_bit ? ~0 : 0
98 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
99 /// Operands are two FP values to compare; result is a mask of
100 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
103 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
104 /// result in an integer GPR. Needs masking for scalar result.
107 /// X86 conditional moves. Operand 0 and operand 1 are the two values
108 /// to select from. Operand 2 is the condition code, and operand 3 is the
109 /// flag operand produced by a CMP or TEST instruction. It also writes a
113 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
114 /// is the block to branch if condition is true, operand 2 is the
115 /// condition code, and operand 3 is the flag operand produced by a CMP
116 /// or TEST instruction.
119 /// Return with a flag operand. Operand 0 is the chain operand, operand
120 /// 1 is the number of bytes of stack to pop.
123 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
126 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
129 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
130 /// at function entry, used for PIC code.
133 /// Wrapper - A wrapper node for TargetConstantPool,
134 /// TargetExternalSymbol, and TargetGlobalAddress.
137 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
138 /// relative displacements.
141 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
142 /// to an MMX vector. If you think this is too close to the previous
143 /// mnemonic, so do I; blame Intel.
146 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
150 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
151 /// i32, corresponds to X86::PEXTRB.
154 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
155 /// i32, corresponds to X86::PEXTRW.
158 /// INSERTPS - Insert any element of a 4 x float vector into any element
159 /// of a destination 4 x floatvector.
162 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
163 /// corresponds to X86::PINSRB.
166 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
167 /// corresponds to X86::PINSRW.
170 /// PSHUFB - Shuffle 16 8-bit values within a vector.
173 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
176 /// PSIGN - Copy integer sign.
179 /// BLENDV - Blend where the selector is a register.
182 /// BLENDI - Blend where the selector is an immediate.
185 // SUBUS - Integer sub with unsigned saturation.
188 /// HADD - Integer horizontal add.
191 /// HSUB - Integer horizontal sub.
194 /// FHADD - Floating point horizontal add.
197 /// FHSUB - Floating point horizontal sub.
200 /// UMAX, UMIN - Unsigned integer max and min.
203 /// SMAX, SMIN - Signed integer max and min.
206 /// FMAX, FMIN - Floating point max and min.
210 /// FMAXC, FMINC - Commutative FMIN and FMAX.
213 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
214 /// approximation. Note that these typically require refinement
215 /// in order to obtain suitable precision.
218 // TLSADDR - Thread Local Storage.
221 // TLSBASEADDR - Thread Local Storage. A call to get the start address
222 // of the TLS block for the current module.
225 // TLSCALL - Thread Local Storage. When calling to an OS provided
226 // thunk at the address from an earlier relocation.
229 // EH_RETURN - Exception Handling helpers.
232 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
235 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
238 /// TC_RETURN - Tail call return.
240 /// operand #1 callee (register or absolute)
241 /// operand #2 stack adjustment
242 /// operand #3 optional in flag
245 // VZEXT_MOVL - Vector move low and zero extend.
248 // VSEXT_MOVL - Vector move low and sign extend.
251 // VZEXT - Vector integer zero-extend.
254 // VSEXT - Vector integer signed-extend.
257 // VFPEXT - Vector FP extend.
260 // VFPROUND - Vector FP round.
263 // VSHL, VSRL - 128-bit vector logical left / right shift
266 // VSHL, VSRL, VSRA - Vector shift elements
269 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
272 // CMPP - Vector packed double/float comparison.
275 // PCMP* - Vector integer comparisons.
278 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
279 ADD, SUB, ADC, SBB, SMUL,
280 INC, DEC, OR, XOR, AND,
282 BLSI, // BLSI - Extract lowest set isolated bit
283 BLSMSK, // BLSMSK - Get mask up to lowest set bit
284 BLSR, // BLSR - Reset lowest set bit
286 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
288 // MUL_IMM - X86 specific multiply by immediate.
291 // PTEST - Vector bitwise comparisons
294 // TESTP - Vector packed fp sign bitwise comparisons
297 // Several flavors of instructions with vector shuffle behaviors.
321 // PMULUDQ - Vector multiply packed unsigned doubleword integers
332 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
333 // according to %al. An operator is needed so that this can be expanded
334 // with control flow.
335 VASTART_SAVE_XMM_REGS,
337 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
340 // SEG_ALLOCA - For allocating variable amounts of stack space when using
341 // segmented stacks. Check if the current stacklet has enough space, and
342 // falls back to heap allocation if not.
345 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
354 // FNSTSW16r - Store FP status word into i16 register.
357 // SAHF - Store contents of %ah into %eflags.
360 // RDRAND - Get a random integer and indicate whether it is valid in CF.
367 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
368 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
369 // Atomic 64-bit binary operations.
370 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
382 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
387 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
390 // FNSTCW16m - Store FP control world into i16 memory.
393 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
394 /// integer destination in memory and a FP reg source. This corresponds
395 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
396 /// has two inputs (token chain and address) and two outputs (int value
397 /// and token chain).
402 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
403 /// integer source in memory and FP reg result. This corresponds to the
404 /// X86::FILD*m instructions. It has three inputs (token chain, address,
405 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
406 /// also produces a flag).
410 /// FLD - This instruction implements an extending load to FP stack slots.
411 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
412 /// operand, ptr to load from, and a ValueType node indicating the type
416 /// FST - This instruction implements a truncating store to FP stack
417 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
418 /// chain operand, value to store, address, and a ValueType to store it
422 /// VAARG_64 - This instruction grabs the address of the next argument
423 /// from a va_list. (reads and modifies the va_list in memory)
426 // WARNING: Do not add anything in the end unless you want the node to
427 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
428 // thought as target memory ops!
432 /// Define some predicates that are used for node matching.
434 /// isVEXTRACTF128Index - Return true if the specified
435 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
436 /// suitable for input to VEXTRACTF128.
437 bool isVEXTRACTF128Index(SDNode *N);
439 /// isVINSERTF128Index - Return true if the specified
440 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
441 /// suitable for input to VINSERTF128.
442 bool isVINSERTF128Index(SDNode *N);
444 /// getExtractVEXTRACTF128Immediate - Return the appropriate
445 /// immediate to extract the specified EXTRACT_SUBVECTOR index
446 /// with VEXTRACTF128 instructions.
447 unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
449 /// getInsertVINSERTF128Immediate - Return the appropriate
450 /// immediate to insert at the specified INSERT_SUBVECTOR index
451 /// with VINSERTF128 instructions.
452 unsigned getInsertVINSERTF128Immediate(SDNode *N);
454 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
456 bool isZeroNode(SDValue Elt);
458 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
459 /// fit into displacement field of the instruction.
460 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
461 bool hasSymbolicDisplacement = true);
464 /// isCalleePop - Determines whether the callee is required to pop its
465 /// own arguments. Callee pop is necessary to support tail calls.
466 bool isCalleePop(CallingConv::ID CallingConv,
467 bool is64Bit, bool IsVarArg, bool TailCallOpt);
470 //===--------------------------------------------------------------------===//
471 // X86TargetLowering - X86 Implementation of the TargetLowering interface
472 class X86TargetLowering : public TargetLowering {
474 explicit X86TargetLowering(X86TargetMachine &TM);
476 virtual unsigned getJumpTableEncoding() const;
478 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
480 virtual const MCExpr *
481 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
482 const MachineBasicBlock *MBB, unsigned uid,
483 MCContext &Ctx) const;
485 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
487 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
488 SelectionDAG &DAG) const;
489 virtual const MCExpr *
490 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
491 unsigned JTI, MCContext &Ctx) const;
493 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
494 /// function arguments in the caller parameter area. For X86, aggregates
495 /// that contains are placed at 16-byte boundaries while the rest are at
496 /// 4-byte boundaries.
497 virtual unsigned getByValTypeAlignment(Type *Ty) const;
499 /// getOptimalMemOpType - Returns the target specific optimal type for load
500 /// and store operations as a result of memset, memcpy, and memmove
501 /// lowering. If DstAlign is zero that means it's safe to destination
502 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
503 /// means there isn't a need to check it against alignment requirement,
504 /// probably because the source does not need to be loaded. If 'IsMemset' is
505 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
506 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
507 /// source is constant so it does not need to be loaded.
508 /// It returns EVT::Other if the type should be determined using generic
509 /// target-independent logic.
511 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
512 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
513 MachineFunction &MF) const;
515 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
516 /// specified type to expand memcpy / memset inline. This is mostly true
517 /// for all types except for some special cases. For example, on X86
518 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
519 /// also does type conversion. Note the specified type doesn't have to be
520 /// legal as the hook is used before type legalization.
521 virtual bool isSafeMemOpType(MVT VT) const;
523 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
524 /// unaligned memory accesses. of the specified type. Returns whether it
525 /// is "fast" by reference in the second argument.
526 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
528 /// LowerOperation - Provide custom lowering hooks for some operations.
530 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
532 /// ReplaceNodeResults - Replace the results of node with an illegal result
533 /// type with new values built out of custom code.
535 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
536 SelectionDAG &DAG) const;
539 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
541 /// isTypeDesirableForOp - Return true if the target has native support for
542 /// the specified value type and it is 'desirable' to use the type for the
543 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
544 /// instruction encodings are longer and some i16 instructions are slow.
545 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
547 /// isTypeDesirable - Return true if the target has native support for the
548 /// specified value type and it is 'desirable' to use the type. e.g. On x86
549 /// i16 is legal, but undesirable since i16 instruction encodings are longer
550 /// and some i16 instructions are slow.
551 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
553 virtual MachineBasicBlock *
554 EmitInstrWithCustomInserter(MachineInstr *MI,
555 MachineBasicBlock *MBB) const;
558 /// getTargetNodeName - This method returns the name of a target specific
560 virtual const char *getTargetNodeName(unsigned Opcode) const;
562 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
563 virtual EVT getSetCCResultType(EVT VT) const;
565 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
566 /// in Mask are known to be either zero or one and return them in the
567 /// KnownZero/KnownOne bitsets.
568 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
571 const SelectionDAG &DAG,
572 unsigned Depth = 0) const;
574 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
575 // operation that are sign bits.
576 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
577 unsigned Depth) const;
580 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
582 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
584 virtual bool ExpandInlineAsm(CallInst *CI) const;
586 ConstraintType getConstraintType(const std::string &Constraint) const;
588 /// Examine constraint string and operand type and determine a weight value.
589 /// The operand object must already have been set up with the operand type.
590 virtual ConstraintWeight getSingleConstraintMatchWeight(
591 AsmOperandInfo &info, const char *constraint) const;
593 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
595 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
596 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
597 /// true it means one of the asm constraint of the inline asm instruction
598 /// being processed is 'm'.
599 virtual void LowerAsmOperandForConstraint(SDValue Op,
600 std::string &Constraint,
601 std::vector<SDValue> &Ops,
602 SelectionDAG &DAG) const;
604 /// getRegForInlineAsmConstraint - Given a physical register constraint
605 /// (e.g. {edx}), return the register number and the register class for the
606 /// register. This should only be used for C_Register constraints. On
607 /// error, this returns a register number of 0.
608 std::pair<unsigned, const TargetRegisterClass*>
609 getRegForInlineAsmConstraint(const std::string &Constraint,
612 /// isLegalAddressingMode - Return true if the addressing mode represented
613 /// by AM is legal for this target, for a load/store of the specified type.
614 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
616 /// isLegalICmpImmediate - Return true if the specified immediate is legal
617 /// icmp immediate, that is the target has icmp instructions which can
618 /// compare a register against the immediate without having to materialize
619 /// the immediate into a register.
620 virtual bool isLegalICmpImmediate(int64_t Imm) const;
622 /// isLegalAddImmediate - Return true if the specified immediate is legal
623 /// add immediate, that is the target has add instructions which can
624 /// add a register and the immediate without having to materialize
625 /// the immediate into a register.
626 virtual bool isLegalAddImmediate(int64_t Imm) const;
628 /// isTruncateFree - Return true if it's free to truncate a value of
629 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
630 /// register EAX to i16 by referencing its sub-register AX.
631 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
632 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
634 /// isZExtFree - Return true if any actual instruction that defines a
635 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
636 /// register. This does not necessarily include registers defined in
637 /// unknown ways, such as incoming arguments, or copies from unknown
638 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
639 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
640 /// all instructions that define 32-bit values implicit zero-extend the
641 /// result out to 64 bits.
642 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
643 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
644 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
646 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
647 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
648 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
649 /// is expanded to mul + add.
650 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
652 /// isNarrowingProfitable - Return true if it's profitable to narrow
653 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
654 /// from i32 to i8 but not from i32 to i16.
655 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
657 /// isFPImmLegal - Returns true if the target can instruction select the
658 /// specified FP immediate natively. If false, the legalizer will
659 /// materialize the FP immediate as a load from a constant pool.
660 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
662 /// isShuffleMaskLegal - Targets can use this to indicate that they only
663 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
664 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
665 /// values are assumed to be legal.
666 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
669 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
670 /// used by Targets can use this to indicate if there is a suitable
671 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
673 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
676 /// ShouldShrinkFPConstant - If true, then instruction selection should
677 /// seek to shrink the FP constant of the specified type to a smaller type
678 /// in order to save space and / or reduce runtime.
679 virtual bool ShouldShrinkFPConstant(EVT VT) const {
680 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
681 // expensive than a straight movsd. On the other hand, it's important to
682 // shrink long double fp constant since fldt is very slow.
683 return !X86ScalarSSEf64 || VT == MVT::f80;
686 const X86Subtarget* getSubtarget() const {
690 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
691 /// computed in an SSE register, not on the X87 floating point stack.
692 bool isScalarFPTypeInSSEReg(EVT VT) const {
693 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
694 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
697 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
699 bool isTargetFTOL() const {
700 return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
703 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
704 /// used for fptoui to the given type.
705 bool isIntegerTypeFTOL(EVT VT) const {
706 return isTargetFTOL() && VT == MVT::i64;
709 /// createFastISel - This method returns a target specific FastISel object,
710 /// or null if the target does not support "fast" ISel.
711 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
712 const TargetLibraryInfo *libInfo) const;
714 /// getStackCookieLocation - Return true if the target stores stack
715 /// protector cookies at a fixed offset in some non-standard address
716 /// space, and populates the address space and offset as
718 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
720 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
721 SelectionDAG &DAG) const;
724 std::pair<const TargetRegisterClass*, uint8_t>
725 findRepresentativeClass(MVT VT) const;
728 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
729 /// make the right decision when generating code for different targets.
730 const X86Subtarget *Subtarget;
731 const X86RegisterInfo *RegInfo;
732 const DataLayout *TD;
734 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
735 /// floating point ops.
736 /// When SSE is available, use it for f32 operations.
737 /// When SSE2 is available, use it for f64 operations.
738 bool X86ScalarSSEf32;
739 bool X86ScalarSSEf64;
741 /// LegalFPImmediates - A list of legal fp immediates.
742 std::vector<APFloat> LegalFPImmediates;
744 /// addLegalFPImmediate - Indicate that this x86 target can instruction
745 /// select the specified FP immediate natively.
746 void addLegalFPImmediate(const APFloat& Imm) {
747 LegalFPImmediates.push_back(Imm);
750 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
751 CallingConv::ID CallConv, bool isVarArg,
752 const SmallVectorImpl<ISD::InputArg> &Ins,
753 DebugLoc dl, SelectionDAG &DAG,
754 SmallVectorImpl<SDValue> &InVals) const;
755 SDValue LowerMemArgument(SDValue Chain,
756 CallingConv::ID CallConv,
757 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
758 DebugLoc dl, SelectionDAG &DAG,
759 const CCValAssign &VA, MachineFrameInfo *MFI,
761 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
762 DebugLoc dl, SelectionDAG &DAG,
763 const CCValAssign &VA,
764 ISD::ArgFlagsTy Flags) const;
766 // Call lowering helpers.
768 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
769 /// for tail call optimization. Targets which want to do tail call
770 /// optimization should implement this function.
771 bool IsEligibleForTailCallOptimization(SDValue Callee,
772 CallingConv::ID CalleeCC,
774 bool isCalleeStructRet,
775 bool isCallerStructRet,
777 const SmallVectorImpl<ISD::OutputArg> &Outs,
778 const SmallVectorImpl<SDValue> &OutVals,
779 const SmallVectorImpl<ISD::InputArg> &Ins,
780 SelectionDAG& DAG) const;
781 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
782 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
783 SDValue Chain, bool IsTailCall, bool Is64Bit,
784 int FPDiff, DebugLoc dl) const;
786 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
787 SelectionDAG &DAG) const;
789 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
791 bool isReplace) const;
793 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
794 SelectionDAG &DAG) const;
795 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
796 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
797 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
798 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
799 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
803 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
804 int64_t Offset, SelectionDAG &DAG) const;
805 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
806 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
807 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
808 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
809 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
810 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
812 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
813 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
814 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
815 SDValue lowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
816 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
817 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
818 SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
819 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
820 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
821 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
822 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
823 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
824 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
825 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
826 DebugLoc dl, SelectionDAG &DAG) const;
827 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
828 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
829 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
830 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
831 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
832 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
833 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
834 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
835 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
836 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
837 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
838 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
839 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
840 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
841 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
842 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
843 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
844 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
846 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
848 // Utility functions to help LowerVECTOR_SHUFFLE & LowerBUILD_VECTOR
849 SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
850 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
851 SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const;
853 SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
855 SDValue lowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const;
858 LowerFormalArguments(SDValue Chain,
859 CallingConv::ID CallConv, bool isVarArg,
860 const SmallVectorImpl<ISD::InputArg> &Ins,
861 DebugLoc dl, SelectionDAG &DAG,
862 SmallVectorImpl<SDValue> &InVals) const;
864 LowerCall(CallLoweringInfo &CLI,
865 SmallVectorImpl<SDValue> &InVals) const;
868 LowerReturn(SDValue Chain,
869 CallingConv::ID CallConv, bool isVarArg,
870 const SmallVectorImpl<ISD::OutputArg> &Outs,
871 const SmallVectorImpl<SDValue> &OutVals,
872 DebugLoc dl, SelectionDAG &DAG) const;
874 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
876 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
879 getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
882 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
884 const SmallVectorImpl<ISD::OutputArg> &Outs,
885 LLVMContext &Context) const;
887 /// Utility function to emit atomic-load-arith operations (and, or, xor,
888 /// nand, max, min, umax, umin). It takes the corresponding instruction to
889 /// expand, the associated machine basic block, and the associated X86
890 /// opcodes for reg/reg.
891 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
892 MachineBasicBlock *MBB) const;
894 /// Utility function to emit atomic-load-arith operations (and, or, xor,
895 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
896 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
897 MachineBasicBlock *MBB) const;
899 // Utility function to emit the low-level va_arg code for X86-64.
900 MachineBasicBlock *EmitVAARG64WithCustomInserter(
902 MachineBasicBlock *MBB) const;
904 /// Utility function to emit the xmm reg save portion of va_start.
905 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
906 MachineInstr *BInstr,
907 MachineBasicBlock *BB) const;
909 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
910 MachineBasicBlock *BB) const;
912 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
913 MachineBasicBlock *BB) const;
915 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
916 MachineBasicBlock *BB,
919 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
920 MachineBasicBlock *BB) const;
922 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
923 MachineBasicBlock *BB) const;
925 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
926 MachineBasicBlock *MBB) const;
928 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
929 MachineBasicBlock *MBB) const;
931 /// Emit nodes that will be selected as "test Op0,Op0", or something
932 /// equivalent, for use with the given x86 condition code.
933 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
935 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
936 /// equivalent, for use with the given x86 condition code.
937 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
938 SelectionDAG &DAG) const;
940 /// Convert a comparison if required by the subtarget.
941 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
945 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
946 const TargetLibraryInfo *libInfo);
949 class X86ScalarTargetTransformImpl : public ScalarTargetTransformImpl {
951 explicit X86ScalarTargetTransformImpl(const TargetLowering *TL) :
952 ScalarTargetTransformImpl(TL) {};
954 virtual PopcntHwSupport getPopcntHwSupport(unsigned TyWidth) const;
957 class X86VectorTargetTransformInfo : public VectorTargetTransformImpl {
959 explicit X86VectorTargetTransformInfo(const TargetLowering *TL) :
960 VectorTargetTransformImpl(TL) {}
962 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
964 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
966 unsigned AddressSpace) const;
968 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
969 unsigned Index) const;
971 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
974 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
977 unsigned getShuffleCost(ShuffleKind Kind,
978 Type *Tp, int Index, Type *SubTp) const;
982 #endif // X86ISELLOWERING_H