1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FSRL - Bitwise logical right shift of floating point values. These
56 /// corresponds to X86::PSRLDQ.
59 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
60 /// integer source in memory and FP reg result. This corresponds to the
61 /// X86::FILD*m instructions. It has three inputs (token chain, address,
62 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
63 /// also produces a flag).
67 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
68 /// integer destination in memory and a FP reg source. This corresponds
69 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
70 /// has two inputs (token chain and address) and two outputs (int value
76 /// FLD - This instruction implements an extending load to FP stack slots.
77 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
78 /// operand, ptr to load from, and a ValueType node indicating the type
82 /// FST - This instruction implements a truncating store to FP stack
83 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
84 /// chain operand, value to store, address, and a ValueType to store it
88 /// CALL - These operations represent an abstract X86 call
89 /// instruction, which includes a bunch of information. In particular the
90 /// operands of these node are:
92 /// #0 - The incoming token chain
94 /// #2 - The number of arg bytes the caller pushes on the stack.
95 /// #3 - The number of arg bytes the callee pops off the stack.
96 /// #4 - The value to pass in AL/AX/EAX (optional)
97 /// #5 - The value to pass in DL/DX/EDX (optional)
99 /// The result values of these nodes are:
101 /// #0 - The outgoing token chain
102 /// #1 - The first register result value (optional)
103 /// #2 - The second register result value (optional)
107 /// RDTSC_DAG - This operation implements the lowering for
111 /// X86 compare and logical compare instructions.
114 /// X86 bit-test instructions.
117 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
118 /// operand produced by a CMP instruction.
121 // Same as SETCC except it's materialized with a sbb and the value is all
122 // one's or all zero's.
125 /// X86 conditional moves. Operand 0 and operand 1 are the two values
126 /// to select from. Operand 2 is the condition code, and operand 3 is the
127 /// flag operand produced by a CMP or TEST instruction. It also writes a
131 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
132 /// is the block to branch if condition is true, operand 2 is the
133 /// condition code, and operand 3 is the flag operand produced by a CMP
134 /// or TEST instruction.
137 /// Return with a flag operand. Operand 0 is the chain operand, operand
138 /// 1 is the number of bytes of stack to pop.
141 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
144 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
147 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
148 /// at function entry, used for PIC code.
151 /// Wrapper - A wrapper node for TargetConstantPool,
152 /// TargetExternalSymbol, and TargetGlobalAddress.
155 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
156 /// relative displacements.
159 /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector.
160 /// Can be used to move a vector value from a MMX register to a XMM
164 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRB.
168 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
169 /// i32, corresponds to X86::PEXTRW.
172 /// INSERTPS - Insert any element of a 4 x float vector into any element
173 /// of a destination 4 x floatvector.
176 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRB.
180 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
181 /// corresponds to X86::PINSRW.
184 /// PSHUFB - Shuffle 16 8-bit values within a vector.
187 /// FMAX, FMIN - Floating point max and min.
191 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
192 /// approximation. Note that these typically require refinement
193 /// in order to obtain suitable precision.
196 // TLSADDR - Thread Local Storage.
199 // SegmentBaseAddress - The address segment:0
202 // EH_RETURN - Exception Handling helpers.
205 /// TC_RETURN - Tail call return.
207 /// operand #1 callee (register or absolute)
208 /// operand #2 stack adjustment
209 /// operand #3 optional in flag
212 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
216 // FNSTCW16m - Store FP control world into i16 memory.
219 // VZEXT_MOVL - Vector move low and zero extend.
222 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
225 // VSHL, VSRL - Vector logical left / right shift.
228 // CMPPD, CMPPS - Vector double/float comparison.
229 // CMPPD, CMPPS - Vector double/float comparison.
232 // PCMP* - Vector integer comparisons.
233 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
234 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
236 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
237 ADD, SUB, SMUL, UMUL,
238 INC, DEC, OR, XOR, AND,
240 // MUL_IMM - X86 specific multiply by immediate.
243 // PTEST - Vector bitwise comparisons
246 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
247 // according to %al. An operator is needed so that this can be expanded
248 // with control flow.
249 VASTART_SAVE_XMM_REGS,
251 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
252 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
253 // Atomic 64-bit binary operations.
254 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
264 /// Define some predicates that are used for node matching.
266 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
267 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
268 bool isPSHUFDMask(ShuffleVectorSDNode *N);
270 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
271 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
272 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
274 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
275 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
276 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
278 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
279 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
280 bool isSHUFPMask(ShuffleVectorSDNode *N);
282 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
283 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
284 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
286 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
287 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
289 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
291 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
292 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
293 bool isMOVLPMask(ShuffleVectorSDNode *N);
295 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
296 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
297 /// as well as MOVLHPS.
298 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
300 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
301 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
302 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
304 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
305 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
306 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
308 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
309 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
311 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
313 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
314 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
316 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
318 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
319 /// specifies a shuffle of elements that is suitable for input to MOVSS,
320 /// MOVSD, and MOVD, i.e. setting the lowest element.
321 bool isMOVLMask(ShuffleVectorSDNode *N);
323 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
324 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
325 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
327 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
328 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
329 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
331 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
332 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
333 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
335 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
336 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
337 bool isPALIGNRMask(ShuffleVectorSDNode *N);
339 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
340 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
342 unsigned getShuffleSHUFImmediate(SDNode *N);
344 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
345 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
346 unsigned getShufflePSHUFHWImmediate(SDNode *N);
348 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
349 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
350 unsigned getShufflePSHUFLWImmediate(SDNode *N);
352 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
353 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
354 unsigned getShufflePALIGNRImmediate(SDNode *N);
356 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
358 bool isZeroNode(SDValue Elt);
360 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
361 /// fit into displacement field of the instruction.
362 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
363 bool hasSymbolicDisplacement = true);
366 //===--------------------------------------------------------------------===//
367 // X86TargetLowering - X86 Implementation of the TargetLowering interface
368 class X86TargetLowering : public TargetLowering {
369 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
370 int RegSaveFrameIndex; // X86-64 vararg func register save area.
371 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
372 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
373 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
374 int BytesCallerReserves; // Number of arg bytes caller makes.
377 explicit X86TargetLowering(X86TargetMachine &TM);
379 /// getPICBaseSymbol - Return the X86-32 PIC base.
380 MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const;
382 virtual unsigned getJumpTableEncoding() const;
384 virtual const MCExpr *
385 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
386 const MachineBasicBlock *MBB, unsigned uid,
387 MCContext &Ctx) const;
389 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
391 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
392 SelectionDAG &DAG) const;
393 virtual const MCExpr *
394 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
395 unsigned JTI, MCContext &Ctx) const;
397 // Return the number of bytes that a function should pop when it returns (in
398 // addition to the space used by the return address).
400 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
402 // Return the number of bytes that the caller reserves for arguments passed
404 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
406 /// getStackPtrReg - Return the stack pointer register we are using: either
408 unsigned getStackPtrReg() const { return X86StackPtr; }
410 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
411 /// function arguments in the caller parameter area. For X86, aggregates
412 /// that contains are placed at 16-byte boundaries while the rest are at
413 /// 4-byte boundaries.
414 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
416 /// getOptimalMemOpType - Returns the target specific optimal type for load
417 /// and store operations as a result of memset, memcpy, and memmove
418 /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for
420 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
421 bool isSrcConst, bool isSrcStr,
422 SelectionDAG &DAG) const;
424 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
425 /// unaligned memory accesses. of the specified type.
426 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
430 /// LowerOperation - Provide custom lowering hooks for some operations.
432 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
434 /// ReplaceNodeResults - Replace the results of node with an illegal result
435 /// type with new values built out of custom code.
437 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
441 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
443 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
444 MachineBasicBlock *MBB,
445 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
448 /// getTargetNodeName - This method returns the name of a target specific
450 virtual const char *getTargetNodeName(unsigned Opcode) const;
452 /// getSetCCResultType - Return the ISD::SETCC ValueType
453 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
455 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
456 /// in Mask are known to be either zero or one and return them in the
457 /// KnownZero/KnownOne bitsets.
458 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
462 const SelectionDAG &DAG,
463 unsigned Depth = 0) const;
466 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
468 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
470 virtual bool ExpandInlineAsm(CallInst *CI) const;
472 ConstraintType getConstraintType(const std::string &Constraint) const;
474 std::vector<unsigned>
475 getRegClassForInlineAsmConstraint(const std::string &Constraint,
478 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
480 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
481 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
482 /// true it means one of the asm constraint of the inline asm instruction
483 /// being processed is 'm'.
484 virtual void LowerAsmOperandForConstraint(SDValue Op,
485 char ConstraintLetter,
487 std::vector<SDValue> &Ops,
488 SelectionDAG &DAG) const;
490 /// getRegForInlineAsmConstraint - Given a physical register constraint
491 /// (e.g. {edx}), return the register number and the register class for the
492 /// register. This should only be used for C_Register constraints. On
493 /// error, this returns a register number of 0.
494 std::pair<unsigned, const TargetRegisterClass*>
495 getRegForInlineAsmConstraint(const std::string &Constraint,
498 /// isLegalAddressingMode - Return true if the addressing mode represented
499 /// by AM is legal for this target, for a load/store of the specified type.
500 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
502 /// isTruncateFree - Return true if it's free to truncate a value of
503 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
504 /// register EAX to i16 by referencing its sub-register AX.
505 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
506 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
508 /// isZExtFree - Return true if any actual instruction that defines a
509 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
510 /// register. This does not necessarily include registers defined in
511 /// unknown ways, such as incoming arguments, or copies from unknown
512 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
513 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
514 /// all instructions that define 32-bit values implicit zero-extend the
515 /// result out to 64 bits.
516 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
517 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
519 /// isNarrowingProfitable - Return true if it's profitable to narrow
520 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
521 /// from i32 to i8 but not from i32 to i16.
522 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
524 /// isFPImmLegal - Returns true if the target can instruction select the
525 /// specified FP immediate natively. If false, the legalizer will
526 /// materialize the FP immediate as a load from a constant pool.
527 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
529 /// isShuffleMaskLegal - Targets can use this to indicate that they only
530 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
531 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
532 /// values are assumed to be legal.
533 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
536 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
537 /// used by Targets can use this to indicate if there is a suitable
538 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
540 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
543 /// ShouldShrinkFPConstant - If true, then instruction selection should
544 /// seek to shrink the FP constant of the specified type to a smaller type
545 /// in order to save space and / or reduce runtime.
546 virtual bool ShouldShrinkFPConstant(EVT VT) const {
547 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
548 // expensive than a straight movsd. On the other hand, it's important to
549 // shrink long double fp constant since fldt is very slow.
550 return !X86ScalarSSEf64 || VT == MVT::f80;
553 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
554 /// for tail call optimization. Targets which want to do tail call
555 /// optimization should implement this function.
557 IsEligibleForTailCallOptimization(SDValue Callee,
558 CallingConv::ID CalleeCC,
560 const SmallVectorImpl<ISD::InputArg> &Ins,
561 SelectionDAG& DAG) const;
563 virtual const X86Subtarget* getSubtarget() {
567 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
568 /// computed in an SSE register, not on the X87 floating point stack.
569 bool isScalarFPTypeInSSEReg(EVT VT) const {
570 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
571 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
574 /// getWidenVectorType: given a vector type, returns the type to widen
575 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
576 /// If there is no vector type that we want to widen to, returns EVT::Other
577 /// When and were to widen is target dependent based on the cost of
578 /// scalarizing vs using the wider vector type.
579 virtual EVT getWidenVectorType(EVT VT) const;
581 /// createFastISel - This method returns a target specific FastISel object,
582 /// or null if the target does not support "fast" ISel.
584 createFastISel(MachineFunction &mf,
585 MachineModuleInfo *mmi, DwarfWriter *dw,
586 DenseMap<const Value *, unsigned> &,
587 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
588 DenseMap<const AllocaInst *, int> &
590 , SmallSet<Instruction*, 8> &
594 /// getFunctionAlignment - Return the Log2 alignment of this function.
595 virtual unsigned getFunctionAlignment(const Function *F) const;
598 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
599 /// make the right decision when generating code for different targets.
600 const X86Subtarget *Subtarget;
601 const X86RegisterInfo *RegInfo;
602 const TargetData *TD;
604 /// X86StackPtr - X86 physical register used as stack ptr.
605 unsigned X86StackPtr;
607 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
608 /// floating point ops.
609 /// When SSE is available, use it for f32 operations.
610 /// When SSE2 is available, use it for f64 operations.
611 bool X86ScalarSSEf32;
612 bool X86ScalarSSEf64;
614 /// LegalFPImmediates - A list of legal fp immediates.
615 std::vector<APFloat> LegalFPImmediates;
617 /// addLegalFPImmediate - Indicate that this x86 target can instruction
618 /// select the specified FP immediate natively.
619 void addLegalFPImmediate(const APFloat& Imm) {
620 LegalFPImmediates.push_back(Imm);
623 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
624 CallingConv::ID CallConv, bool isVarArg,
625 const SmallVectorImpl<ISD::InputArg> &Ins,
626 DebugLoc dl, SelectionDAG &DAG,
627 SmallVectorImpl<SDValue> &InVals);
628 SDValue LowerMemArgument(SDValue Chain,
629 CallingConv::ID CallConv,
630 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
631 DebugLoc dl, SelectionDAG &DAG,
632 const CCValAssign &VA, MachineFrameInfo *MFI,
634 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
635 DebugLoc dl, SelectionDAG &DAG,
636 const CCValAssign &VA,
637 ISD::ArgFlagsTy Flags);
639 // Call lowering helpers.
640 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv);
641 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
642 SDValue Chain, bool IsTailCall, bool Is64Bit,
643 int FPDiff, DebugLoc dl);
645 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
646 NameDecorationStyle NameDecorationForCallConv(CallingConv::ID CallConv);
647 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG);
649 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
652 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
654 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
655 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG);
656 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
657 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
658 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
659 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG);
660 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
661 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
662 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
663 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
664 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
665 int64_t Offset, SelectionDAG &DAG) const;
666 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
667 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
668 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
669 SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
670 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
672 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
673 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG);
674 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG);
675 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG);
676 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
677 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG);
678 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG);
679 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG);
680 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG);
681 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
682 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG);
683 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
684 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
685 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG);
686 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
687 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
688 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
689 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
690 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG);
691 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
692 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
693 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
694 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG);
695 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG);
696 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
697 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
698 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
699 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
700 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG);
701 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG);
703 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
704 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
705 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG);
708 LowerFormalArguments(SDValue Chain,
709 CallingConv::ID CallConv, bool isVarArg,
710 const SmallVectorImpl<ISD::InputArg> &Ins,
711 DebugLoc dl, SelectionDAG &DAG,
712 SmallVectorImpl<SDValue> &InVals);
714 LowerCall(SDValue Chain, SDValue Callee,
715 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
716 const SmallVectorImpl<ISD::OutputArg> &Outs,
717 const SmallVectorImpl<ISD::InputArg> &Ins,
718 DebugLoc dl, SelectionDAG &DAG,
719 SmallVectorImpl<SDValue> &InVals);
722 LowerReturn(SDValue Chain,
723 CallingConv::ID CallConv, bool isVarArg,
724 const SmallVectorImpl<ISD::OutputArg> &Outs,
725 DebugLoc dl, SelectionDAG &DAG);
728 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
729 const SmallVectorImpl<EVT> &OutTys,
730 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
733 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
734 SelectionDAG &DAG, unsigned NewOp);
736 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
738 SDValue Dst, SDValue Src,
739 SDValue Size, unsigned Align,
740 const Value *DstSV, uint64_t DstSVOff);
741 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
743 SDValue Dst, SDValue Src,
744 SDValue Size, unsigned Align,
746 const Value *DstSV, uint64_t DstSVOff,
747 const Value *SrcSV, uint64_t SrcSVOff);
749 /// Utility function to emit string processing sse4.2 instructions
750 /// that return in xmm0.
751 /// This takes the instruction to expand, the associated machine basic
752 /// block, the number of args, and whether or not the second arg is
753 /// in memory or not.
754 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
755 unsigned argNum, bool inMem) const;
757 /// Utility function to emit atomic bitwise operations (and, or, xor).
758 /// It takes the bitwise instruction to expand, the associated machine basic
759 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
760 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
761 MachineInstr *BInstr,
762 MachineBasicBlock *BB,
770 TargetRegisterClass *RC,
771 bool invSrc = false) const;
773 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
774 MachineInstr *BInstr,
775 MachineBasicBlock *BB,
780 bool invSrc = false) const;
782 /// Utility function to emit atomic min and max. It takes the min/max
783 /// instruction to expand, the associated basic block, and the associated
784 /// cmov opcode for moving the min or max value.
785 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
786 MachineBasicBlock *BB,
787 unsigned cmovOpc) const;
789 /// Utility function to emit the xmm reg save portion of va_start.
790 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
791 MachineInstr *BInstr,
792 MachineBasicBlock *BB) const;
794 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
795 MachineBasicBlock *BB,
796 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
798 /// Emit nodes that will be selected as "test Op0,Op0", or something
799 /// equivalent, for use with the given x86 condition code.
800 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG);
802 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
803 /// equivalent, for use with the given x86 condition code.
804 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
809 FastISel *createFastISel(MachineFunction &mf,
810 MachineModuleInfo *mmi, DwarfWriter *dw,
811 DenseMap<const Value *, unsigned> &,
812 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
813 DenseMap<const AllocaInst *, int> &
815 , SmallSet<Instruction*, 8> &
821 #endif // X86ISELLOWERING_H