1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "X86IntrinsicsInfo.h"
58 #define DEBUG_TYPE "x86-isel"
60 STATISTIC(NumTailCalls, "Number of tail calls");
62 static cl::opt<bool> ExperimentalVectorWideningLegalization(
63 "x86-experimental-vector-widening-legalization", cl::init(false),
64 cl::desc("Enable an experimental vector type legalization through widening "
65 "rather than promotion."),
68 static cl::opt<bool> ExperimentalVectorShuffleLowering(
69 "x86-experimental-vector-shuffle-lowering", cl::init(false),
70 cl::desc("Enable an experimental vector shuffle lowering code path."),
73 // Forward declarations.
74 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
77 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
78 SelectionDAG &DAG, SDLoc dl,
79 unsigned vectorWidth) {
80 assert((vectorWidth == 128 || vectorWidth == 256) &&
81 "Unsupported vector width");
82 EVT VT = Vec.getValueType();
83 EVT ElVT = VT.getVectorElementType();
84 unsigned Factor = VT.getSizeInBits()/vectorWidth;
85 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
86 VT.getVectorNumElements()/Factor);
88 // Extract from UNDEF is UNDEF.
89 if (Vec.getOpcode() == ISD::UNDEF)
90 return DAG.getUNDEF(ResultVT);
92 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
93 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
95 // This is the index of the first element of the vectorWidth-bit chunk
97 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
100 // If the input is a buildvector just emit a smaller one.
101 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
102 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
103 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
106 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
113 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
114 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
115 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
116 /// instructions or a simple subregister reference. Idx is an index in the
117 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
118 /// lowering EXTRACT_VECTOR_ELT operations easier.
119 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
120 SelectionDAG &DAG, SDLoc dl) {
121 assert((Vec.getValueType().is256BitVector() ||
122 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
123 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
126 /// Generate a DAG to grab 256-bits from a 512-bit vector.
127 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
128 SelectionDAG &DAG, SDLoc dl) {
129 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
133 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
134 unsigned IdxVal, SelectionDAG &DAG,
135 SDLoc dl, unsigned vectorWidth) {
136 assert((vectorWidth == 128 || vectorWidth == 256) &&
137 "Unsupported vector width");
138 // Inserting UNDEF is Result
139 if (Vec.getOpcode() == ISD::UNDEF)
141 EVT VT = Vec.getValueType();
142 EVT ElVT = VT.getVectorElementType();
143 EVT ResultVT = Result.getValueType();
145 // Insert the relevant vectorWidth bits.
146 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
148 // This is the index of the first element of the vectorWidth-bit chunk
150 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
153 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
154 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
157 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
158 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
159 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
160 /// simple superregister reference. Idx is an index in the 128 bits
161 /// we want. It need not be aligned to a 128-bit bounday. That makes
162 /// lowering INSERT_VECTOR_ELT operations easier.
163 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
164 unsigned IdxVal, SelectionDAG &DAG,
166 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
167 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
170 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
177 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
178 /// instructions. This is used because creating CONCAT_VECTOR nodes of
179 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
180 /// large BUILD_VECTORS.
181 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
182 unsigned NumElems, SelectionDAG &DAG,
184 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
185 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
188 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
195 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
196 if (TT.isOSBinFormatMachO()) {
197 if (TT.getArch() == Triple::x86_64)
198 return new X86_64MachoTargetObjectFile();
199 return new TargetLoweringObjectFileMachO();
203 return new X86LinuxTargetObjectFile();
204 if (TT.isOSBinFormatELF())
205 return new TargetLoweringObjectFileELF();
206 if (TT.isKnownWindowsMSVCEnvironment())
207 return new X86WindowsTargetObjectFile();
208 if (TT.isOSBinFormatCOFF())
209 return new TargetLoweringObjectFileCOFF();
210 llvm_unreachable("unknown subtarget type");
213 // FIXME: This should stop caching the target machine as soon as
214 // we can remove resetOperationActions et al.
215 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
216 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
217 Subtarget = &TM.getSubtarget<X86Subtarget>();
218 X86ScalarSSEf64 = Subtarget->hasSSE2();
219 X86ScalarSSEf32 = Subtarget->hasSSE1();
220 TD = getDataLayout();
222 resetOperationActions();
225 void X86TargetLowering::resetOperationActions() {
226 const TargetMachine &TM = getTargetMachine();
227 static bool FirstTimeThrough = true;
229 // If none of the target options have changed, then we don't need to reset the
230 // operation actions.
231 if (!FirstTimeThrough && TO == TM.Options) return;
233 if (!FirstTimeThrough) {
234 // Reinitialize the actions.
236 FirstTimeThrough = false;
241 // Set up the TargetLowering object.
242 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
244 // X86 is weird, it always uses i8 for shift amounts and setcc results.
245 setBooleanContents(ZeroOrOneBooleanContent);
246 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
247 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
249 // For 64-bit since we have so many registers use the ILP scheduler, for
250 // 32-bit code use the register pressure specific scheduling.
251 // For Atom, always use ILP scheduling.
252 if (Subtarget->isAtom())
253 setSchedulingPreference(Sched::ILP);
254 else if (Subtarget->is64Bit())
255 setSchedulingPreference(Sched::ILP);
257 setSchedulingPreference(Sched::RegPressure);
258 const X86RegisterInfo *RegInfo =
259 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
260 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
262 // Bypass expensive divides on Atom when compiling with O2
263 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
264 addBypassSlowDiv(32, 8);
265 if (Subtarget->is64Bit())
266 addBypassSlowDiv(64, 16);
269 if (Subtarget->isTargetKnownWindowsMSVC()) {
270 // Setup Windows compiler runtime calls.
271 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
272 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
273 setLibcallName(RTLIB::SREM_I64, "_allrem");
274 setLibcallName(RTLIB::UREM_I64, "_aullrem");
275 setLibcallName(RTLIB::MUL_I64, "_allmul");
276 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
282 // The _ftol2 runtime function has an unusual calling conv, which
283 // is modeled by a special pseudo-instruction.
284 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
290 if (Subtarget->isTargetDarwin()) {
291 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
292 setUseUnderscoreSetJmp(false);
293 setUseUnderscoreLongJmp(false);
294 } else if (Subtarget->isTargetWindowsGNU()) {
295 // MS runtime is weird: it exports _setjmp, but longjmp!
296 setUseUnderscoreSetJmp(true);
297 setUseUnderscoreLongJmp(false);
299 setUseUnderscoreSetJmp(true);
300 setUseUnderscoreLongJmp(true);
303 // Set up the register classes.
304 addRegisterClass(MVT::i8, &X86::GR8RegClass);
305 addRegisterClass(MVT::i16, &X86::GR16RegClass);
306 addRegisterClass(MVT::i32, &X86::GR32RegClass);
307 if (Subtarget->is64Bit())
308 addRegisterClass(MVT::i64, &X86::GR64RegClass);
310 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
312 // We don't accept any truncstore of integer registers.
313 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
316 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
317 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
318 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
320 // SETOEQ and SETUNE require checking two conditions.
321 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
323 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
328 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
330 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
332 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
334 if (Subtarget->is64Bit()) {
335 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
336 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
337 } else if (!TM.Options.UseSoftFloat) {
338 // We have an algorithm for SSE2->double, and we turn this into a
339 // 64-bit FILD followed by conditional FADD for other targets.
340 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
341 // We have an algorithm for SSE2, and we turn this into a 64-bit
342 // FILD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
346 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
348 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
351 if (!TM.Options.UseSoftFloat) {
352 // SSE has no i16 to fp conversion, only i32
353 if (X86ScalarSSEf32) {
354 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 // f32 and f64 cases are Legal, f80 case is not
356 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
363 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
366 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
367 // are Legal, f80 is custom lowered.
368 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
369 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
371 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
373 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
374 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
376 if (X86ScalarSSEf32) {
377 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
378 // f32 and f64 cases are Legal, f80 case is not
379 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
385 // Handle FP_TO_UINT by promoting the destination to a larger signed
387 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
389 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
391 if (Subtarget->is64Bit()) {
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
393 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
394 } else if (!TM.Options.UseSoftFloat) {
395 // Since AVX is a superset of SSE3, only check for SSE here.
396 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
397 // Expand FP_TO_UINT into a select.
398 // FIXME: We would like to use a Custom expander here eventually to do
399 // the optimal thing for SSE vs. the default expansion in the legalizer.
400 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
402 // With SSE3 we can use fisttpll to convert to a signed i64; without
403 // SSE, we're stuck with a fistpll.
404 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
407 if (isTargetFTOL()) {
408 // Use the _ftol2 runtime function, which has a pseudo-instruction
409 // to handle its weird calling convention.
410 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
413 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
414 if (!X86ScalarSSEf64) {
415 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
416 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
419 // Without SSE, i64->f64 goes through memory.
420 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
424 // Scalar integer divide and remainder are lowered to use operations that
425 // produce two results, to match the available instructions. This exposes
426 // the two-result form to trivial CSE, which is able to combine x/y and x%y
427 // into a single instruction.
429 // Scalar integer multiply-high is also lowered to use two-result
430 // operations, to match the available instructions. However, plain multiply
431 // (low) operations are left as Legal, as there are single-result
432 // instructions for this in x86. Using the two-result multiply instructions
433 // when both high and low results are needed must be arranged by dagcombine.
434 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
436 setOperationAction(ISD::MULHS, VT, Expand);
437 setOperationAction(ISD::MULHU, VT, Expand);
438 setOperationAction(ISD::SDIV, VT, Expand);
439 setOperationAction(ISD::UDIV, VT, Expand);
440 setOperationAction(ISD::SREM, VT, Expand);
441 setOperationAction(ISD::UREM, VT, Expand);
443 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
444 setOperationAction(ISD::ADDC, VT, Custom);
445 setOperationAction(ISD::ADDE, VT, Custom);
446 setOperationAction(ISD::SUBC, VT, Custom);
447 setOperationAction(ISD::SUBE, VT, Custom);
450 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
451 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
452 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
454 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
466 if (Subtarget->is64Bit())
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
471 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f32 , Expand);
473 setOperationAction(ISD::FREM , MVT::f64 , Expand);
474 setOperationAction(ISD::FREM , MVT::f80 , Expand);
475 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
477 // Promote the i8 variants and force them on up to i32 which has a shorter
479 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
480 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
481 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
482 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
483 if (Subtarget->hasBMI()) {
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
485 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
486 if (Subtarget->is64Bit())
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
489 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
490 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
495 if (Subtarget->hasLZCNT()) {
496 // When promoting the i8 variants, force them to i32 for a shorter
498 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
499 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
501 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
504 if (Subtarget->is64Bit())
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
507 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
509 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
513 if (Subtarget->is64Bit()) {
514 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
519 // Special handling for half-precision floating point conversions.
520 // If we don't have F16C support, then lower half float conversions
521 // into library calls.
522 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
523 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
524 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
527 // There's never any support for operations beyond MVT::f32.
528 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
529 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
531 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
533 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
536 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
538 if (Subtarget->hasPOPCNT()) {
539 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
541 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
543 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
544 if (Subtarget->is64Bit())
545 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
548 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
550 if (!Subtarget->hasMOVBE())
551 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
553 // These should be promoted to a larger select which is supported.
554 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
555 // X86 wants to expand cmov itself.
556 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
558 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
561 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
564 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
567 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
568 if (Subtarget->is64Bit()) {
569 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
572 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
573 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
574 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
575 // support continuation, user-level threading, and etc.. As a result, no
576 // other SjLj exception interfaces are implemented and please don't build
577 // your own exception handling based on them.
578 // LLVM/Clang supports zero-cost DWARF exception handling.
579 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
580 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
583 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
584 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
586 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
587 if (Subtarget->is64Bit())
588 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
589 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
590 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
591 if (Subtarget->is64Bit()) {
592 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
593 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
594 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
595 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
596 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
598 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
599 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
601 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
602 if (Subtarget->is64Bit()) {
603 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
605 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
608 if (Subtarget->hasSSE1())
609 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
611 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
613 // Expand certain atomics
614 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
616 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
617 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
618 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
621 if (Subtarget->hasCmpxchg16b()) {
622 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
625 // FIXME - use subtarget debug flags
626 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
627 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
628 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
631 if (Subtarget->is64Bit()) {
632 setExceptionPointerRegister(X86::RAX);
633 setExceptionSelectorRegister(X86::RDX);
635 setExceptionPointerRegister(X86::EAX);
636 setExceptionSelectorRegister(X86::EDX);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
639 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
641 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
642 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
644 setOperationAction(ISD::TRAP, MVT::Other, Legal);
645 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
647 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
648 setOperationAction(ISD::VASTART , MVT::Other, Custom);
649 setOperationAction(ISD::VAEND , MVT::Other, Expand);
650 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
651 // TargetInfo::X86_64ABIBuiltinVaList
652 setOperationAction(ISD::VAARG , MVT::Other, Custom);
653 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
655 // TargetInfo::CharPtrBuiltinVaList
656 setOperationAction(ISD::VAARG , MVT::Other, Expand);
657 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
660 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
661 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
663 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
665 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
666 // f32 and f64 use SSE.
667 // Set up the FP register classes.
668 addRegisterClass(MVT::f32, &X86::FR32RegClass);
669 addRegisterClass(MVT::f64, &X86::FR64RegClass);
671 // Use ANDPD to simulate FABS.
672 setOperationAction(ISD::FABS , MVT::f64, Custom);
673 setOperationAction(ISD::FABS , MVT::f32, Custom);
675 // Use XORP to simulate FNEG.
676 setOperationAction(ISD::FNEG , MVT::f64, Custom);
677 setOperationAction(ISD::FNEG , MVT::f32, Custom);
679 // Use ANDPD and ORPD to simulate FCOPYSIGN.
680 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
681 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
683 // Lower this to FGETSIGNx86 plus an AND.
684 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
685 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
687 // We don't support sin/cos/fmod
688 setOperationAction(ISD::FSIN , MVT::f64, Expand);
689 setOperationAction(ISD::FCOS , MVT::f64, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f32, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
695 // Expand FP immediates into loads from the stack, except for the special
697 addLegalFPImmediate(APFloat(+0.0)); // xorpd
698 addLegalFPImmediate(APFloat(+0.0f)); // xorps
699 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
700 // Use SSE for f32, x87 for f64.
701 // Set up the FP register classes.
702 addRegisterClass(MVT::f32, &X86::FR32RegClass);
703 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
705 // Use ANDPS to simulate FABS.
706 setOperationAction(ISD::FABS , MVT::f32, Custom);
708 // Use XORP to simulate FNEG.
709 setOperationAction(ISD::FNEG , MVT::f32, Custom);
711 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
713 // Use ANDPS and ORPS to simulate FCOPYSIGN.
714 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
717 // We don't support sin/cos/fmod
718 setOperationAction(ISD::FSIN , MVT::f32, Expand);
719 setOperationAction(ISD::FCOS , MVT::f32, Expand);
720 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
722 // Special cases we handle for FP constants.
723 addLegalFPImmediate(APFloat(+0.0f)); // xorps
724 addLegalFPImmediate(APFloat(+0.0)); // FLD0
725 addLegalFPImmediate(APFloat(+1.0)); // FLD1
726 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
727 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
729 if (!TM.Options.UnsafeFPMath) {
730 setOperationAction(ISD::FSIN , MVT::f64, Expand);
731 setOperationAction(ISD::FCOS , MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
734 } else if (!TM.Options.UseSoftFloat) {
735 // f32 and f64 in x87.
736 // Set up the FP register classes.
737 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
738 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
740 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
741 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
743 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
745 if (!TM.Options.UnsafeFPMath) {
746 setOperationAction(ISD::FSIN , MVT::f64, Expand);
747 setOperationAction(ISD::FSIN , MVT::f32, Expand);
748 setOperationAction(ISD::FCOS , MVT::f64, Expand);
749 setOperationAction(ISD::FCOS , MVT::f32, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
751 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
753 addLegalFPImmediate(APFloat(+0.0)); // FLD0
754 addLegalFPImmediate(APFloat(+1.0)); // FLD1
755 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
756 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
757 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
758 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
759 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
760 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
763 // We don't support FMA.
764 setOperationAction(ISD::FMA, MVT::f64, Expand);
765 setOperationAction(ISD::FMA, MVT::f32, Expand);
767 // Long double always uses X87.
768 if (!TM.Options.UseSoftFloat) {
769 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
771 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
773 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
774 addLegalFPImmediate(TmpFlt); // FLD0
776 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
779 APFloat TmpFlt2(+1.0);
780 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
782 addLegalFPImmediate(TmpFlt2); // FLD1
783 TmpFlt2.changeSign();
784 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
787 if (!TM.Options.UnsafeFPMath) {
788 setOperationAction(ISD::FSIN , MVT::f80, Expand);
789 setOperationAction(ISD::FCOS , MVT::f80, Expand);
790 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
793 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
794 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
795 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
796 setOperationAction(ISD::FRINT, MVT::f80, Expand);
797 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
798 setOperationAction(ISD::FMA, MVT::f80, Expand);
801 // Always use a library call for pow.
802 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
804 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
806 setOperationAction(ISD::FLOG, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
808 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP, MVT::f80, Expand);
810 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
812 // First set operation action for all vector types to either promote
813 // (for widening) or expand (for scalarization). Then we will selectively
814 // turn on ones that can be effectively codegen'd.
815 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
816 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
817 MVT VT = (MVT::SimpleValueType)i;
818 setOperationAction(ISD::ADD , VT, Expand);
819 setOperationAction(ISD::SUB , VT, Expand);
820 setOperationAction(ISD::FADD, VT, Expand);
821 setOperationAction(ISD::FNEG, VT, Expand);
822 setOperationAction(ISD::FSUB, VT, Expand);
823 setOperationAction(ISD::MUL , VT, Expand);
824 setOperationAction(ISD::FMUL, VT, Expand);
825 setOperationAction(ISD::SDIV, VT, Expand);
826 setOperationAction(ISD::UDIV, VT, Expand);
827 setOperationAction(ISD::FDIV, VT, Expand);
828 setOperationAction(ISD::SREM, VT, Expand);
829 setOperationAction(ISD::UREM, VT, Expand);
830 setOperationAction(ISD::LOAD, VT, Expand);
831 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
834 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
836 setOperationAction(ISD::FABS, VT, Expand);
837 setOperationAction(ISD::FSIN, VT, Expand);
838 setOperationAction(ISD::FSINCOS, VT, Expand);
839 setOperationAction(ISD::FCOS, VT, Expand);
840 setOperationAction(ISD::FSINCOS, VT, Expand);
841 setOperationAction(ISD::FREM, VT, Expand);
842 setOperationAction(ISD::FMA, VT, Expand);
843 setOperationAction(ISD::FPOWI, VT, Expand);
844 setOperationAction(ISD::FSQRT, VT, Expand);
845 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
846 setOperationAction(ISD::FFLOOR, VT, Expand);
847 setOperationAction(ISD::FCEIL, VT, Expand);
848 setOperationAction(ISD::FTRUNC, VT, Expand);
849 setOperationAction(ISD::FRINT, VT, Expand);
850 setOperationAction(ISD::FNEARBYINT, VT, Expand);
851 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
852 setOperationAction(ISD::MULHS, VT, Expand);
853 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
854 setOperationAction(ISD::MULHU, VT, Expand);
855 setOperationAction(ISD::SDIVREM, VT, Expand);
856 setOperationAction(ISD::UDIVREM, VT, Expand);
857 setOperationAction(ISD::FPOW, VT, Expand);
858 setOperationAction(ISD::CTPOP, VT, Expand);
859 setOperationAction(ISD::CTTZ, VT, Expand);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
861 setOperationAction(ISD::CTLZ, VT, Expand);
862 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
863 setOperationAction(ISD::SHL, VT, Expand);
864 setOperationAction(ISD::SRA, VT, Expand);
865 setOperationAction(ISD::SRL, VT, Expand);
866 setOperationAction(ISD::ROTL, VT, Expand);
867 setOperationAction(ISD::ROTR, VT, Expand);
868 setOperationAction(ISD::BSWAP, VT, Expand);
869 setOperationAction(ISD::SETCC, VT, Expand);
870 setOperationAction(ISD::FLOG, VT, Expand);
871 setOperationAction(ISD::FLOG2, VT, Expand);
872 setOperationAction(ISD::FLOG10, VT, Expand);
873 setOperationAction(ISD::FEXP, VT, Expand);
874 setOperationAction(ISD::FEXP2, VT, Expand);
875 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
876 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
877 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
879 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
880 setOperationAction(ISD::TRUNCATE, VT, Expand);
881 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
882 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
883 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
884 setOperationAction(ISD::VSELECT, VT, Expand);
885 setOperationAction(ISD::SELECT_CC, VT, Expand);
886 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
887 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
888 setTruncStoreAction(VT,
889 (MVT::SimpleValueType)InnerVT, Expand);
890 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
891 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
893 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
894 // we have to deal with them whether we ask for Expansion or not. Setting
895 // Expand causes its own optimisation problems though, so leave them legal.
896 if (VT.getVectorElementType() == MVT::i1)
897 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
900 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
901 // with -msoft-float, disable use of MMX as well.
902 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
903 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
904 // No operations on x86mmx supported, everything uses intrinsics.
907 // MMX-sized vectors (other than x86mmx) are expected to be expanded
908 // into smaller operations.
909 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
910 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
911 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
912 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
913 setOperationAction(ISD::AND, MVT::v8i8, Expand);
914 setOperationAction(ISD::AND, MVT::v4i16, Expand);
915 setOperationAction(ISD::AND, MVT::v2i32, Expand);
916 setOperationAction(ISD::AND, MVT::v1i64, Expand);
917 setOperationAction(ISD::OR, MVT::v8i8, Expand);
918 setOperationAction(ISD::OR, MVT::v4i16, Expand);
919 setOperationAction(ISD::OR, MVT::v2i32, Expand);
920 setOperationAction(ISD::OR, MVT::v1i64, Expand);
921 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
922 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
923 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
924 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
930 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
931 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
932 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
933 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
939 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
940 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
942 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
943 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
944 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
945 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
947 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
948 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
949 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
950 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
951 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
952 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
953 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
956 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
957 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
959 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
960 // registers cannot be used even for integer operations.
961 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
962 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
963 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
964 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
966 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
967 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
968 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
969 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
971 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
972 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
974 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
975 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
976 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
977 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
978 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
979 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
980 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
981 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
982 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
983 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
984 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
986 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
987 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
990 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
991 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
992 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
995 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1001 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1002 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to custom lower non-power-of-2 vectors
1004 if (!isPowerOf2_32(VT.getVectorNumElements()))
1006 // Do not attempt to custom lower non-128-bit vectors
1007 if (!VT.is128BitVector())
1009 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1010 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1014 // We support custom legalizing of sext and anyext loads for specific
1015 // memory vector types which we can load as a scalar (or sequence of
1016 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1017 // loads these must work with a single scalar load.
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1028 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1030 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1032 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1033 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1035 if (Subtarget->is64Bit()) {
1036 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1037 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1040 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1041 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1042 MVT VT = (MVT::SimpleValueType)i;
1044 // Do not attempt to promote non-128-bit vectors
1045 if (!VT.is128BitVector())
1048 setOperationAction(ISD::AND, VT, Promote);
1049 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1050 setOperationAction(ISD::OR, VT, Promote);
1051 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1052 setOperationAction(ISD::XOR, VT, Promote);
1053 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1054 setOperationAction(ISD::LOAD, VT, Promote);
1055 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1056 setOperationAction(ISD::SELECT, VT, Promote);
1057 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1060 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1062 // Custom lower v2i64 and v2f64 selects.
1063 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1064 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1065 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1068 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1069 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1071 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1073 // As there is no 64-bit GPR available, we need build a special custom
1074 // sequence to convert from v2i32 to v2f32.
1075 if (!Subtarget->is64Bit())
1076 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1078 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1081 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1083 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1084 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1088 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1089 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1090 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1091 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1092 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1093 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1097 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1100 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1106 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1111 // FIXME: Do we need to handle scalar-to-vector here?
1112 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1114 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1115 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1119 // There is no BLENDI for byte vectors. We don't need to custom lower
1120 // some vselects for now.
1121 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1123 // SSE41 brings specific instructions for doing vector sign extend even in
1124 // cases where we don't have SRA.
1125 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1129 // i8 and i16 vectors are custom because the source register and source
1130 // source memory operand types are not the same width. f32 vectors are
1131 // custom since the immediate controlling the insert encodes additional
1133 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1143 // FIXME: these should be Legal, but that's only for the case where
1144 // the index is constant. For now custom expand to deal with that.
1145 if (Subtarget->is64Bit()) {
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1147 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1151 if (Subtarget->hasSSE2()) {
1152 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1153 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1155 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1156 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1158 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1159 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1161 // In the customized shift lowering, the legal cases in AVX2 will be
1163 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1164 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1166 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1167 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1169 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1172 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1173 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1174 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1180 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1181 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1184 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1195 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1197 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1208 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1210 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1211 // even though v8i16 is a legal type.
1212 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1213 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1216 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1218 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1220 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1223 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1225 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1234 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1243 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1248 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1251 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1254 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1257 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1261 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1262 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1263 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1265 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1266 setOperationAction(ISD::FMA, MVT::f32, Legal);
1267 setOperationAction(ISD::FMA, MVT::f64, Legal);
1270 if (Subtarget->hasInt256()) {
1271 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1272 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1273 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1274 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1276 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1277 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1278 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1279 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1281 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1282 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1283 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1284 // Don't lower v32i8 because there is no 128-bit byte mul
1286 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1287 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1289 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1291 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1292 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1295 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1296 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1297 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1299 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1300 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1301 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1302 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1304 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1305 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1306 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1307 // Don't lower v32i8 because there is no 128-bit byte mul
1310 // In the customized shift lowering, the legal cases in AVX2 will be
1312 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1316 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1318 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1320 // Custom lower several nodes for 256-bit types.
1321 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1322 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1323 MVT VT = (MVT::SimpleValueType)i;
1325 // Extract subvector is special because the value type
1326 // (result) is 128-bit but the source is 256-bit wide.
1327 if (VT.is128BitVector())
1328 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1330 // Do not attempt to custom lower other non-256-bit vectors
1331 if (!VT.is256BitVector())
1334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1335 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1336 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1337 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1339 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1340 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1343 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1344 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1345 MVT VT = (MVT::SimpleValueType)i;
1347 // Do not attempt to promote non-256-bit vectors
1348 if (!VT.is256BitVector())
1351 setOperationAction(ISD::AND, VT, Promote);
1352 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1353 setOperationAction(ISD::OR, VT, Promote);
1354 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1355 setOperationAction(ISD::XOR, VT, Promote);
1356 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1357 setOperationAction(ISD::LOAD, VT, Promote);
1358 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1359 setOperationAction(ISD::SELECT, VT, Promote);
1360 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1364 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1365 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1366 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1371 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1372 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1374 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1375 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1376 setOperationAction(ISD::XOR, MVT::i1, Legal);
1377 setOperationAction(ISD::OR, MVT::i1, Legal);
1378 setOperationAction(ISD::AND, MVT::i1, Legal);
1379 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1386 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1393 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1399 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1406 if (Subtarget->is64Bit()) {
1407 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1413 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector())
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1516 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1517 MVT VT = (MVT::SimpleValueType)i;
1519 // Do not attempt to promote non-256-bit vectors
1520 if (!VT.is512BitVector())
1523 setOperationAction(ISD::SELECT, VT, Promote);
1524 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1528 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1529 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1533 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1536 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1537 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1540 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1541 const MVT VT = (MVT::SimpleValueType)i;
1543 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1545 // Do not attempt to promote non-256-bit vectors
1546 if (!VT.is512BitVector())
1549 if ( EltSize < 32) {
1550 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1551 setOperationAction(ISD::VSELECT, VT, Legal);
1556 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1557 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1558 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1560 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1564 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1565 // of this type with custom code.
1566 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1567 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1568 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1572 // We want to custom lower some of our intrinsics.
1573 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1574 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1576 if (!Subtarget->is64Bit())
1577 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1579 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1580 // handle type legalization for these operations here.
1582 // FIXME: We really should do custom legalization for addition and
1583 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1584 // than generic legalization for 64-bit multiplication-with-overflow, though.
1585 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1586 // Add/Sub/Mul with overflow operations are custom lowered.
1588 setOperationAction(ISD::SADDO, VT, Custom);
1589 setOperationAction(ISD::UADDO, VT, Custom);
1590 setOperationAction(ISD::SSUBO, VT, Custom);
1591 setOperationAction(ISD::USUBO, VT, Custom);
1592 setOperationAction(ISD::SMULO, VT, Custom);
1593 setOperationAction(ISD::UMULO, VT, Custom);
1596 // There are no 8-bit 3-address imul/mul instructions
1597 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1598 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1600 if (!Subtarget->is64Bit()) {
1601 // These libcalls are not available in 32-bit.
1602 setLibcallName(RTLIB::SHL_I128, nullptr);
1603 setLibcallName(RTLIB::SRL_I128, nullptr);
1604 setLibcallName(RTLIB::SRA_I128, nullptr);
1607 // Combine sin / cos into one node or libcall if possible.
1608 if (Subtarget->hasSinCos()) {
1609 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1610 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1611 if (Subtarget->isTargetDarwin()) {
1612 // For MacOSX, we don't want to the normal expansion of a libcall to
1613 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1615 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1616 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1620 if (Subtarget->isTargetWin64()) {
1621 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1622 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::SREM, MVT::i128, Custom);
1624 setOperationAction(ISD::UREM, MVT::i128, Custom);
1625 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1629 // We have target-specific dag combine patterns for the following nodes:
1630 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1631 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1632 setTargetDAGCombine(ISD::VSELECT);
1633 setTargetDAGCombine(ISD::SELECT);
1634 setTargetDAGCombine(ISD::SHL);
1635 setTargetDAGCombine(ISD::SRA);
1636 setTargetDAGCombine(ISD::SRL);
1637 setTargetDAGCombine(ISD::OR);
1638 setTargetDAGCombine(ISD::AND);
1639 setTargetDAGCombine(ISD::ADD);
1640 setTargetDAGCombine(ISD::FADD);
1641 setTargetDAGCombine(ISD::FSUB);
1642 setTargetDAGCombine(ISD::FMA);
1643 setTargetDAGCombine(ISD::SUB);
1644 setTargetDAGCombine(ISD::LOAD);
1645 setTargetDAGCombine(ISD::STORE);
1646 setTargetDAGCombine(ISD::ZERO_EXTEND);
1647 setTargetDAGCombine(ISD::ANY_EXTEND);
1648 setTargetDAGCombine(ISD::SIGN_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1650 setTargetDAGCombine(ISD::TRUNCATE);
1651 setTargetDAGCombine(ISD::SINT_TO_FP);
1652 setTargetDAGCombine(ISD::SETCC);
1653 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1654 setTargetDAGCombine(ISD::BUILD_VECTOR);
1655 if (Subtarget->is64Bit())
1656 setTargetDAGCombine(ISD::MUL);
1657 setTargetDAGCombine(ISD::XOR);
1659 computeRegisterProperties();
1661 // On Darwin, -Os means optimize for size without hurting performance,
1662 // do not reduce the limit.
1663 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1664 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1665 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1666 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1667 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1668 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 setPrefLoopAlignment(4); // 2^4 bytes.
1671 // Predictable cmov don't hurt on atom because it's in-order.
1672 PredictableSelectIsExpensive = !Subtarget->isAtom();
1674 setPrefFunctionAlignment(4); // 2^4 bytes.
1676 verifyIntrinsicTables();
1679 // This has so far only been implemented for 64-bit MachO.
1680 bool X86TargetLowering::useLoadStackGuardNode() const {
1681 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1682 Subtarget->is64Bit();
1685 TargetLoweringBase::LegalizeTypeAction
1686 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1687 if (ExperimentalVectorWideningLegalization &&
1688 VT.getVectorNumElements() != 1 &&
1689 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1690 return TypeWidenVector;
1692 return TargetLoweringBase::getPreferredVectorAction(VT);
1695 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1697 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1699 const unsigned NumElts = VT.getVectorNumElements();
1700 const EVT EltVT = VT.getVectorElementType();
1701 if (VT.is512BitVector()) {
1702 if (Subtarget->hasAVX512())
1703 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1704 EltVT == MVT::f32 || EltVT == MVT::f64)
1706 case 8: return MVT::v8i1;
1707 case 16: return MVT::v16i1;
1709 if (Subtarget->hasBWI())
1710 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1712 case 32: return MVT::v32i1;
1713 case 64: return MVT::v64i1;
1717 if (VT.is256BitVector() || VT.is128BitVector()) {
1718 if (Subtarget->hasVLX())
1719 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1720 EltVT == MVT::f32 || EltVT == MVT::f64)
1722 case 2: return MVT::v2i1;
1723 case 4: return MVT::v4i1;
1724 case 8: return MVT::v8i1;
1726 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1727 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1729 case 8: return MVT::v8i1;
1730 case 16: return MVT::v16i1;
1731 case 32: return MVT::v32i1;
1735 return VT.changeVectorElementTypeToInteger();
1738 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1739 /// the desired ByVal argument alignment.
1740 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1743 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1744 if (VTy->getBitWidth() == 128)
1746 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1747 unsigned EltAlign = 0;
1748 getMaxByValAlign(ATy->getElementType(), EltAlign);
1749 if (EltAlign > MaxAlign)
1750 MaxAlign = EltAlign;
1751 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1752 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1753 unsigned EltAlign = 0;
1754 getMaxByValAlign(STy->getElementType(i), EltAlign);
1755 if (EltAlign > MaxAlign)
1756 MaxAlign = EltAlign;
1763 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1764 /// function arguments in the caller parameter area. For X86, aggregates
1765 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1766 /// are at 4-byte boundaries.
1767 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1768 if (Subtarget->is64Bit()) {
1769 // Max of 8 and alignment of type.
1770 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1777 if (Subtarget->hasSSE1())
1778 getMaxByValAlign(Ty, Align);
1782 /// getOptimalMemOpType - Returns the target specific optimal type for load
1783 /// and store operations as a result of memset, memcpy, and memmove
1784 /// lowering. If DstAlign is zero that means it's safe to destination
1785 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1786 /// means there isn't a need to check it against alignment requirement,
1787 /// probably because the source does not need to be loaded. If 'IsMemset' is
1788 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1789 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1790 /// source is constant so it does not need to be loaded.
1791 /// It returns EVT::Other if the type should be determined using generic
1792 /// target-independent logic.
1794 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1795 unsigned DstAlign, unsigned SrcAlign,
1796 bool IsMemset, bool ZeroMemset,
1798 MachineFunction &MF) const {
1799 const Function *F = MF.getFunction();
1800 if ((!IsMemset || ZeroMemset) &&
1801 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1802 Attribute::NoImplicitFloat)) {
1804 (Subtarget->isUnalignedMemAccessFast() ||
1805 ((DstAlign == 0 || DstAlign >= 16) &&
1806 (SrcAlign == 0 || SrcAlign >= 16)))) {
1808 if (Subtarget->hasInt256())
1810 if (Subtarget->hasFp256())
1813 if (Subtarget->hasSSE2())
1815 if (Subtarget->hasSSE1())
1817 } else if (!MemcpyStrSrc && Size >= 8 &&
1818 !Subtarget->is64Bit() &&
1819 Subtarget->hasSSE2()) {
1820 // Do not use f64 to lower memcpy if source is string constant. It's
1821 // better to use i32 to avoid the loads.
1825 if (Subtarget->is64Bit() && Size >= 8)
1830 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1832 return X86ScalarSSEf32;
1833 else if (VT == MVT::f64)
1834 return X86ScalarSSEf64;
1839 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1844 *Fast = Subtarget->isUnalignedMemAccessFast();
1848 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1849 /// current function. The returned value is a member of the
1850 /// MachineJumpTableInfo::JTEntryKind enum.
1851 unsigned X86TargetLowering::getJumpTableEncoding() const {
1852 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1854 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1855 Subtarget->isPICStyleGOT())
1856 return MachineJumpTableInfo::EK_Custom32;
1858 // Otherwise, use the normal jump table encoding heuristics.
1859 return TargetLowering::getJumpTableEncoding();
1863 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1864 const MachineBasicBlock *MBB,
1865 unsigned uid,MCContext &Ctx) const{
1866 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1867 Subtarget->isPICStyleGOT());
1868 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1870 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1871 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1874 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1876 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1877 SelectionDAG &DAG) const {
1878 if (!Subtarget->is64Bit())
1879 // This doesn't have SDLoc associated with it, but is not really the
1880 // same as a Register.
1881 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1885 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1886 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1888 const MCExpr *X86TargetLowering::
1889 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1890 MCContext &Ctx) const {
1891 // X86-64 uses RIP relative addressing based on the jump table label.
1892 if (Subtarget->isPICStyleRIPRel())
1893 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1895 // Otherwise, the reference is relative to the PIC base.
1896 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1899 // FIXME: Why this routine is here? Move to RegInfo!
1900 std::pair<const TargetRegisterClass*, uint8_t>
1901 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1902 const TargetRegisterClass *RRC = nullptr;
1904 switch (VT.SimpleTy) {
1906 return TargetLowering::findRepresentativeClass(VT);
1907 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1908 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1911 RRC = &X86::VR64RegClass;
1913 case MVT::f32: case MVT::f64:
1914 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1915 case MVT::v4f32: case MVT::v2f64:
1916 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1918 RRC = &X86::VR128RegClass;
1921 return std::make_pair(RRC, Cost);
1924 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1925 unsigned &Offset) const {
1926 if (!Subtarget->isTargetLinux())
1929 if (Subtarget->is64Bit()) {
1930 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1932 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1944 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1945 unsigned DestAS) const {
1946 assert(SrcAS != DestAS && "Expected different address spaces!");
1948 return SrcAS < 256 && DestAS < 256;
1951 //===----------------------------------------------------------------------===//
1952 // Return Value Calling Convention Implementation
1953 //===----------------------------------------------------------------------===//
1955 #include "X86GenCallingConv.inc"
1958 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1959 MachineFunction &MF, bool isVarArg,
1960 const SmallVectorImpl<ISD::OutputArg> &Outs,
1961 LLVMContext &Context) const {
1962 SmallVector<CCValAssign, 16> RVLocs;
1963 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1964 return CCInfo.CheckReturn(Outs, RetCC_X86);
1967 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1968 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1973 X86TargetLowering::LowerReturn(SDValue Chain,
1974 CallingConv::ID CallConv, bool isVarArg,
1975 const SmallVectorImpl<ISD::OutputArg> &Outs,
1976 const SmallVectorImpl<SDValue> &OutVals,
1977 SDLoc dl, SelectionDAG &DAG) const {
1978 MachineFunction &MF = DAG.getMachineFunction();
1979 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1981 SmallVector<CCValAssign, 16> RVLocs;
1982 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1983 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1986 SmallVector<SDValue, 6> RetOps;
1987 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1988 // Operand #1 = Bytes To Pop
1989 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1992 // Copy the result values into the output registers.
1993 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1994 CCValAssign &VA = RVLocs[i];
1995 assert(VA.isRegLoc() && "Can only return in registers!");
1996 SDValue ValToCopy = OutVals[i];
1997 EVT ValVT = ValToCopy.getValueType();
1999 // Promote values to the appropriate types
2000 if (VA.getLocInfo() == CCValAssign::SExt)
2001 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::ZExt)
2003 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::AExt)
2005 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::BCvt)
2007 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2009 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2010 "Unexpected FP-extend for return value.");
2012 // If this is x86-64, and we disabled SSE, we can't return FP values,
2013 // or SSE or MMX vectors.
2014 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2015 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2016 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2017 report_fatal_error("SSE register return with SSE disabled");
2019 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2020 // llvm-gcc has never done it right and no one has noticed, so this
2021 // should be OK for now.
2022 if (ValVT == MVT::f64 &&
2023 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2024 report_fatal_error("SSE2 register return with SSE2 disabled");
2026 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2027 // the RET instruction and handled by the FP Stackifier.
2028 if (VA.getLocReg() == X86::FP0 ||
2029 VA.getLocReg() == X86::FP1) {
2030 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2031 // change the value to the FP stack register class.
2032 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2033 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2034 RetOps.push_back(ValToCopy);
2035 // Don't emit a copytoreg.
2039 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2040 // which is returned in RAX / RDX.
2041 if (Subtarget->is64Bit()) {
2042 if (ValVT == MVT::x86mmx) {
2043 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2044 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2045 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2047 // If we don't have SSE2 available, convert to v4f32 so the generated
2048 // register is legal.
2049 if (!Subtarget->hasSSE2())
2050 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2055 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2056 Flag = Chain.getValue(1);
2057 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2060 // The x86-64 ABIs require that for returning structs by value we copy
2061 // the sret argument into %rax/%eax (depending on ABI) for the return.
2062 // Win32 requires us to put the sret argument to %eax as well.
2063 // We saved the argument into a virtual register in the entry block,
2064 // so now we copy the value out and into %rax/%eax.
2065 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2066 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2067 MachineFunction &MF = DAG.getMachineFunction();
2068 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2069 unsigned Reg = FuncInfo->getSRetReturnReg();
2071 "SRetReturnReg should have been set in LowerFormalArguments().");
2072 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2075 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2076 X86::RAX : X86::EAX;
2077 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2078 Flag = Chain.getValue(1);
2080 // RAX/EAX now acts like a return value.
2081 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2084 RetOps[0] = Chain; // Update chain.
2086 // Add the flag if we have it.
2088 RetOps.push_back(Flag);
2090 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2093 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2094 if (N->getNumValues() != 1)
2096 if (!N->hasNUsesOfValue(1, 0))
2099 SDValue TCChain = Chain;
2100 SDNode *Copy = *N->use_begin();
2101 if (Copy->getOpcode() == ISD::CopyToReg) {
2102 // If the copy has a glue operand, we conservatively assume it isn't safe to
2103 // perform a tail call.
2104 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2106 TCChain = Copy->getOperand(0);
2107 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2110 bool HasRet = false;
2111 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2113 if (UI->getOpcode() != X86ISD::RET_FLAG)
2115 // If we are returning more than one value, we can definitely
2116 // not make a tail call see PR19530
2117 if (UI->getNumOperands() > 4)
2119 if (UI->getNumOperands() == 4 &&
2120 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2133 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2134 ISD::NodeType ExtendKind) const {
2136 // TODO: Is this also valid on 32-bit?
2137 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2138 ReturnMVT = MVT::i8;
2140 ReturnMVT = MVT::i32;
2142 EVT MinVT = getRegisterType(Context, ReturnMVT);
2143 return VT.bitsLT(MinVT) ? MinVT : VT;
2146 /// LowerCallResult - Lower the result values of a call into the
2147 /// appropriate copies out of appropriate physical registers.
2150 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2151 CallingConv::ID CallConv, bool isVarArg,
2152 const SmallVectorImpl<ISD::InputArg> &Ins,
2153 SDLoc dl, SelectionDAG &DAG,
2154 SmallVectorImpl<SDValue> &InVals) const {
2156 // Assign locations to each value returned by this call.
2157 SmallVector<CCValAssign, 16> RVLocs;
2158 bool Is64Bit = Subtarget->is64Bit();
2159 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2161 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2163 // Copy all of the result registers out of their specified physreg.
2164 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2165 CCValAssign &VA = RVLocs[i];
2166 EVT CopyVT = VA.getValVT();
2168 // If this is x86-64, and we disabled SSE, we can't return FP values
2169 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2170 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2171 report_fatal_error("SSE register return with SSE disabled");
2174 // If we prefer to use the value in xmm registers, copy it out as f80 and
2175 // use a truncate to move it from fp stack reg to xmm reg.
2176 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2177 isScalarFPTypeInSSEReg(VA.getValVT()))
2180 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2181 CopyVT, InFlag).getValue(1);
2182 SDValue Val = Chain.getValue(0);
2184 if (CopyVT != VA.getValVT())
2185 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2186 // This truncation won't change the value.
2187 DAG.getIntPtrConstant(1));
2189 InFlag = Chain.getValue(2);
2190 InVals.push_back(Val);
2196 //===----------------------------------------------------------------------===//
2197 // C & StdCall & Fast Calling Convention implementation
2198 //===----------------------------------------------------------------------===//
2199 // StdCall calling convention seems to be standard for many Windows' API
2200 // routines and around. It differs from C calling convention just a little:
2201 // callee should clean up the stack, not caller. Symbols should be also
2202 // decorated in some fancy way :) It doesn't support any vector arguments.
2203 // For info on fast calling convention see Fast Calling Convention (tail call)
2204 // implementation LowerX86_32FastCCCallTo.
2206 /// CallIsStructReturn - Determines whether a call uses struct return
2208 enum StructReturnType {
2213 static StructReturnType
2214 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2216 return NotStructReturn;
2218 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2219 if (!Flags.isSRet())
2220 return NotStructReturn;
2221 if (Flags.isInReg())
2222 return RegStructReturn;
2223 return StackStructReturn;
2226 /// ArgsAreStructReturn - Determines whether a function uses struct
2227 /// return semantics.
2228 static StructReturnType
2229 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2231 return NotStructReturn;
2233 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2234 if (!Flags.isSRet())
2235 return NotStructReturn;
2236 if (Flags.isInReg())
2237 return RegStructReturn;
2238 return StackStructReturn;
2241 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2242 /// by "Src" to address "Dst" with size and alignment information specified by
2243 /// the specific parameter attribute. The copy will be passed as a byval
2244 /// function parameter.
2246 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2247 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2249 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2251 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2252 /*isVolatile*/false, /*AlwaysInline=*/true,
2253 MachinePointerInfo(), MachinePointerInfo());
2256 /// IsTailCallConvention - Return true if the calling convention is one that
2257 /// supports tail call optimization.
2258 static bool IsTailCallConvention(CallingConv::ID CC) {
2259 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2260 CC == CallingConv::HiPE);
2263 /// \brief Return true if the calling convention is a C calling convention.
2264 static bool IsCCallConvention(CallingConv::ID CC) {
2265 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2266 CC == CallingConv::X86_64_SysV);
2269 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2270 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2274 CallingConv::ID CalleeCC = CS.getCallingConv();
2275 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2281 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2282 /// a tailcall target by changing its ABI.
2283 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2284 bool GuaranteedTailCallOpt) {
2285 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2289 X86TargetLowering::LowerMemArgument(SDValue Chain,
2290 CallingConv::ID CallConv,
2291 const SmallVectorImpl<ISD::InputArg> &Ins,
2292 SDLoc dl, SelectionDAG &DAG,
2293 const CCValAssign &VA,
2294 MachineFrameInfo *MFI,
2296 // Create the nodes corresponding to a load from this parameter slot.
2297 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2298 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2299 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2300 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2303 // If value is passed by pointer we have address passed instead of the value
2305 if (VA.getLocInfo() == CCValAssign::Indirect)
2306 ValVT = VA.getLocVT();
2308 ValVT = VA.getValVT();
2310 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2311 // changed with more analysis.
2312 // In case of tail call optimization mark all arguments mutable. Since they
2313 // could be overwritten by lowering of arguments in case of a tail call.
2314 if (Flags.isByVal()) {
2315 unsigned Bytes = Flags.getByValSize();
2316 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2317 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2318 return DAG.getFrameIndex(FI, getPointerTy());
2320 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2321 VA.getLocMemOffset(), isImmutable);
2322 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2323 return DAG.getLoad(ValVT, dl, Chain, FIN,
2324 MachinePointerInfo::getFixedStack(FI),
2325 false, false, false, 0);
2329 // FIXME: Get this from tablegen.
2330 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2331 const X86Subtarget *Subtarget) {
2332 assert(Subtarget->is64Bit());
2334 if (Subtarget->isCallingConvWin64(CallConv)) {
2335 static const MCPhysReg GPR64ArgRegsWin64[] = {
2336 X86::RCX, X86::RDX, X86::R8, X86::R9
2338 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2341 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2342 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2344 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2347 // FIXME: Get this from tablegen.
2348 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2349 CallingConv::ID CallConv,
2350 const X86Subtarget *Subtarget) {
2351 assert(Subtarget->is64Bit());
2352 if (Subtarget->isCallingConvWin64(CallConv)) {
2353 // The XMM registers which might contain var arg parameters are shadowed
2354 // in their paired GPR. So we only need to save the GPR to their home
2356 // TODO: __vectorcall will change this.
2360 const Function *Fn = MF.getFunction();
2361 bool NoImplicitFloatOps = Fn->getAttributes().
2362 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2363 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2364 "SSE register cannot be used when SSE is disabled!");
2365 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2366 !Subtarget->hasSSE1())
2367 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2371 static const MCPhysReg XMMArgRegs64Bit[] = {
2372 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2373 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2375 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2379 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2380 CallingConv::ID CallConv,
2382 const SmallVectorImpl<ISD::InputArg> &Ins,
2385 SmallVectorImpl<SDValue> &InVals)
2387 MachineFunction &MF = DAG.getMachineFunction();
2388 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2390 const Function* Fn = MF.getFunction();
2391 if (Fn->hasExternalLinkage() &&
2392 Subtarget->isTargetCygMing() &&
2393 Fn->getName() == "main")
2394 FuncInfo->setForceFramePointer(true);
2396 MachineFrameInfo *MFI = MF.getFrameInfo();
2397 bool Is64Bit = Subtarget->is64Bit();
2398 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2400 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2401 "Var args not supported with calling convention fastcc, ghc or hipe");
2403 // Assign locations to all of the incoming arguments.
2404 SmallVector<CCValAssign, 16> ArgLocs;
2405 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2407 // Allocate shadow area for Win64
2409 CCInfo.AllocateStack(32, 8);
2411 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2413 unsigned LastVal = ~0U;
2415 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2416 CCValAssign &VA = ArgLocs[i];
2417 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2419 assert(VA.getValNo() != LastVal &&
2420 "Don't support value assigned to multiple locs yet");
2422 LastVal = VA.getValNo();
2424 if (VA.isRegLoc()) {
2425 EVT RegVT = VA.getLocVT();
2426 const TargetRegisterClass *RC;
2427 if (RegVT == MVT::i32)
2428 RC = &X86::GR32RegClass;
2429 else if (Is64Bit && RegVT == MVT::i64)
2430 RC = &X86::GR64RegClass;
2431 else if (RegVT == MVT::f32)
2432 RC = &X86::FR32RegClass;
2433 else if (RegVT == MVT::f64)
2434 RC = &X86::FR64RegClass;
2435 else if (RegVT.is512BitVector())
2436 RC = &X86::VR512RegClass;
2437 else if (RegVT.is256BitVector())
2438 RC = &X86::VR256RegClass;
2439 else if (RegVT.is128BitVector())
2440 RC = &X86::VR128RegClass;
2441 else if (RegVT == MVT::x86mmx)
2442 RC = &X86::VR64RegClass;
2443 else if (RegVT == MVT::i1)
2444 RC = &X86::VK1RegClass;
2445 else if (RegVT == MVT::v8i1)
2446 RC = &X86::VK8RegClass;
2447 else if (RegVT == MVT::v16i1)
2448 RC = &X86::VK16RegClass;
2449 else if (RegVT == MVT::v32i1)
2450 RC = &X86::VK32RegClass;
2451 else if (RegVT == MVT::v64i1)
2452 RC = &X86::VK64RegClass;
2454 llvm_unreachable("Unknown argument type!");
2456 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2457 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2459 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2460 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2462 if (VA.getLocInfo() == CCValAssign::SExt)
2463 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2464 DAG.getValueType(VA.getValVT()));
2465 else if (VA.getLocInfo() == CCValAssign::ZExt)
2466 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2467 DAG.getValueType(VA.getValVT()));
2468 else if (VA.getLocInfo() == CCValAssign::BCvt)
2469 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2471 if (VA.isExtInLoc()) {
2472 // Handle MMX values passed in XMM regs.
2473 if (RegVT.isVector())
2474 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2476 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2479 assert(VA.isMemLoc());
2480 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2483 // If value is passed via pointer - do a load.
2484 if (VA.getLocInfo() == CCValAssign::Indirect)
2485 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2486 MachinePointerInfo(), false, false, false, 0);
2488 InVals.push_back(ArgValue);
2491 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2492 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2493 // The x86-64 ABIs require that for returning structs by value we copy
2494 // the sret argument into %rax/%eax (depending on ABI) for the return.
2495 // Win32 requires us to put the sret argument to %eax as well.
2496 // Save the argument into a virtual register so that we can access it
2497 // from the return points.
2498 if (Ins[i].Flags.isSRet()) {
2499 unsigned Reg = FuncInfo->getSRetReturnReg();
2501 MVT PtrTy = getPointerTy();
2502 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2503 FuncInfo->setSRetReturnReg(Reg);
2505 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2506 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2512 unsigned StackSize = CCInfo.getNextStackOffset();
2513 // Align stack specially for tail calls.
2514 if (FuncIsMadeTailCallSafe(CallConv,
2515 MF.getTarget().Options.GuaranteedTailCallOpt))
2516 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2518 // If the function takes variable number of arguments, make a frame index for
2519 // the start of the first vararg value... for expansion of llvm.va_start. We
2520 // can skip this if there are no va_start calls.
2521 if (MFI->hasVAStart() &&
2522 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2523 CallConv != CallingConv::X86_ThisCall))) {
2524 FuncInfo->setVarArgsFrameIndex(
2525 MFI->CreateFixedObject(1, StackSize, true));
2528 // 64-bit calling conventions support varargs and register parameters, so we
2529 // have to do extra work to spill them in the prologue or forward them to
2531 if (Is64Bit && isVarArg &&
2532 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2533 // Find the first unallocated argument registers.
2534 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2535 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2536 unsigned NumIntRegs =
2537 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2538 unsigned NumXMMRegs =
2539 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2540 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2541 "SSE register cannot be used when SSE is disabled!");
2543 // Gather all the live in physical registers.
2544 SmallVector<SDValue, 6> LiveGPRs;
2545 SmallVector<SDValue, 8> LiveXMMRegs;
2547 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2548 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2550 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2552 if (!ArgXMMs.empty()) {
2553 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2554 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2555 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2556 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2557 LiveXMMRegs.push_back(
2558 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2562 // Store them to the va_list returned by va_start.
2563 if (MFI->hasVAStart()) {
2565 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2566 // Get to the caller-allocated home save location. Add 8 to account
2567 // for the return address.
2568 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2569 FuncInfo->setRegSaveFrameIndex(
2570 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2571 // Fixup to set vararg frame on shadow area (4 x i64).
2573 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2575 // For X86-64, if there are vararg parameters that are passed via
2576 // registers, then we must store them to their spots on the stack so
2577 // they may be loaded by deferencing the result of va_next.
2578 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2579 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2580 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2581 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2584 // Store the integer parameter registers.
2585 SmallVector<SDValue, 8> MemOps;
2586 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2588 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2589 for (SDValue Val : LiveGPRs) {
2590 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2591 DAG.getIntPtrConstant(Offset));
2593 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2594 MachinePointerInfo::getFixedStack(
2595 FuncInfo->getRegSaveFrameIndex(), Offset),
2597 MemOps.push_back(Store);
2601 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2602 // Now store the XMM (fp + vector) parameter registers.
2603 SmallVector<SDValue, 12> SaveXMMOps;
2604 SaveXMMOps.push_back(Chain);
2605 SaveXMMOps.push_back(ALVal);
2606 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2607 FuncInfo->getRegSaveFrameIndex()));
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getVarArgsFPOffset()));
2610 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2612 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2613 MVT::Other, SaveXMMOps));
2616 if (!MemOps.empty())
2617 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2619 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2620 // to the liveout set on a musttail call.
2621 assert(MFI->hasMustTailInVarArgFunc());
2622 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2623 typedef X86MachineFunctionInfo::Forward Forward;
2625 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2627 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2628 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2629 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2632 if (!ArgXMMs.empty()) {
2634 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2635 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2636 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2638 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2640 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2641 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2643 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2649 // Some CCs need callee pop.
2650 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2651 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2652 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2654 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2655 // If this is an sret function, the return should pop the hidden pointer.
2656 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2657 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2658 argsAreStructReturn(Ins) == StackStructReturn)
2659 FuncInfo->setBytesToPopOnReturn(4);
2663 // RegSaveFrameIndex is X86-64 only.
2664 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2665 if (CallConv == CallingConv::X86_FastCall ||
2666 CallConv == CallingConv::X86_ThisCall)
2667 // fastcc functions can't have varargs.
2668 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2671 FuncInfo->setArgumentStackSize(StackSize);
2677 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2678 SDValue StackPtr, SDValue Arg,
2679 SDLoc dl, SelectionDAG &DAG,
2680 const CCValAssign &VA,
2681 ISD::ArgFlagsTy Flags) const {
2682 unsigned LocMemOffset = VA.getLocMemOffset();
2683 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2684 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2685 if (Flags.isByVal())
2686 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2688 return DAG.getStore(Chain, dl, Arg, PtrOff,
2689 MachinePointerInfo::getStack(LocMemOffset),
2693 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2694 /// optimization is performed and it is required.
2696 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2697 SDValue &OutRetAddr, SDValue Chain,
2698 bool IsTailCall, bool Is64Bit,
2699 int FPDiff, SDLoc dl) const {
2700 // Adjust the Return address stack slot.
2701 EVT VT = getPointerTy();
2702 OutRetAddr = getReturnAddressFrameIndex(DAG);
2704 // Load the "old" Return address.
2705 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2706 false, false, false, 0);
2707 return SDValue(OutRetAddr.getNode(), 1);
2710 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2711 /// optimization is performed and it is required (FPDiff!=0).
2712 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2713 SDValue Chain, SDValue RetAddrFrIdx,
2714 EVT PtrVT, unsigned SlotSize,
2715 int FPDiff, SDLoc dl) {
2716 // Store the return address to the appropriate stack slot.
2717 if (!FPDiff) return Chain;
2718 // Calculate the new stack slot for the return address.
2719 int NewReturnAddrFI =
2720 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2722 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2723 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2724 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2730 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2731 SmallVectorImpl<SDValue> &InVals) const {
2732 SelectionDAG &DAG = CLI.DAG;
2734 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2735 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2736 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2737 SDValue Chain = CLI.Chain;
2738 SDValue Callee = CLI.Callee;
2739 CallingConv::ID CallConv = CLI.CallConv;
2740 bool &isTailCall = CLI.IsTailCall;
2741 bool isVarArg = CLI.IsVarArg;
2743 MachineFunction &MF = DAG.getMachineFunction();
2744 bool Is64Bit = Subtarget->is64Bit();
2745 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2746 StructReturnType SR = callIsStructReturn(Outs);
2747 bool IsSibcall = false;
2748 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2750 if (MF.getTarget().Options.DisableTailCalls)
2753 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2755 // Force this to be a tail call. The verifier rules are enough to ensure
2756 // that we can lower this successfully without moving the return address
2759 } else if (isTailCall) {
2760 // Check if it's really possible to do a tail call.
2761 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2762 isVarArg, SR != NotStructReturn,
2763 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2764 Outs, OutVals, Ins, DAG);
2766 // Sibcalls are automatically detected tailcalls which do not require
2768 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2775 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2776 "Var args not supported with calling convention fastcc, ghc or hipe");
2778 // Analyze operands of the call, assigning locations to each operand.
2779 SmallVector<CCValAssign, 16> ArgLocs;
2780 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2782 // Allocate shadow area for Win64
2784 CCInfo.AllocateStack(32, 8);
2786 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2788 // Get a count of how many bytes are to be pushed on the stack.
2789 unsigned NumBytes = CCInfo.getNextStackOffset();
2791 // This is a sibcall. The memory operands are available in caller's
2792 // own caller's stack.
2794 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2795 IsTailCallConvention(CallConv))
2796 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2799 if (isTailCall && !IsSibcall && !IsMustTail) {
2800 // Lower arguments at fp - stackoffset + fpdiff.
2801 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2803 FPDiff = NumBytesCallerPushed - NumBytes;
2805 // Set the delta of movement of the returnaddr stackslot.
2806 // But only set if delta is greater than previous delta.
2807 if (FPDiff < X86Info->getTCReturnAddrDelta())
2808 X86Info->setTCReturnAddrDelta(FPDiff);
2811 unsigned NumBytesToPush = NumBytes;
2812 unsigned NumBytesToPop = NumBytes;
2814 // If we have an inalloca argument, all stack space has already been allocated
2815 // for us and be right at the top of the stack. We don't support multiple
2816 // arguments passed in memory when using inalloca.
2817 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2819 if (!ArgLocs.back().isMemLoc())
2820 report_fatal_error("cannot use inalloca attribute on a register "
2822 if (ArgLocs.back().getLocMemOffset() != 0)
2823 report_fatal_error("any parameter with the inalloca attribute must be "
2824 "the only memory argument");
2828 Chain = DAG.getCALLSEQ_START(
2829 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2831 SDValue RetAddrFrIdx;
2832 // Load return address for tail calls.
2833 if (isTailCall && FPDiff)
2834 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2835 Is64Bit, FPDiff, dl);
2837 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2838 SmallVector<SDValue, 8> MemOpChains;
2841 // Walk the register/memloc assignments, inserting copies/loads. In the case
2842 // of tail call optimization arguments are handle later.
2843 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2844 DAG.getSubtarget().getRegisterInfo());
2845 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2846 // Skip inalloca arguments, they have already been written.
2847 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2848 if (Flags.isInAlloca())
2851 CCValAssign &VA = ArgLocs[i];
2852 EVT RegVT = VA.getLocVT();
2853 SDValue Arg = OutVals[i];
2854 bool isByVal = Flags.isByVal();
2856 // Promote the value if needed.
2857 switch (VA.getLocInfo()) {
2858 default: llvm_unreachable("Unknown loc info!");
2859 case CCValAssign::Full: break;
2860 case CCValAssign::SExt:
2861 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2863 case CCValAssign::ZExt:
2864 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2866 case CCValAssign::AExt:
2867 if (RegVT.is128BitVector()) {
2868 // Special case: passing MMX values in XMM registers.
2869 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2870 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2871 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2873 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2875 case CCValAssign::BCvt:
2876 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2878 case CCValAssign::Indirect: {
2879 // Store the argument.
2880 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2881 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2882 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2883 MachinePointerInfo::getFixedStack(FI),
2890 if (VA.isRegLoc()) {
2891 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2892 if (isVarArg && IsWin64) {
2893 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2894 // shadow reg if callee is a varargs function.
2895 unsigned ShadowReg = 0;
2896 switch (VA.getLocReg()) {
2897 case X86::XMM0: ShadowReg = X86::RCX; break;
2898 case X86::XMM1: ShadowReg = X86::RDX; break;
2899 case X86::XMM2: ShadowReg = X86::R8; break;
2900 case X86::XMM3: ShadowReg = X86::R9; break;
2903 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2905 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2906 assert(VA.isMemLoc());
2907 if (!StackPtr.getNode())
2908 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2910 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2911 dl, DAG, VA, Flags));
2915 if (!MemOpChains.empty())
2916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2918 if (Subtarget->isPICStyleGOT()) {
2919 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2922 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2923 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2925 // If we are tail calling and generating PIC/GOT style code load the
2926 // address of the callee into ECX. The value in ecx is used as target of
2927 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2928 // for tail calls on PIC/GOT architectures. Normally we would just put the
2929 // address of GOT into ebx and then call target@PLT. But for tail calls
2930 // ebx would be restored (since ebx is callee saved) before jumping to the
2933 // Note: The actual moving to ECX is done further down.
2934 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2935 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2936 !G->getGlobal()->hasProtectedVisibility())
2937 Callee = LowerGlobalAddress(Callee, DAG);
2938 else if (isa<ExternalSymbolSDNode>(Callee))
2939 Callee = LowerExternalSymbol(Callee, DAG);
2943 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2944 // From AMD64 ABI document:
2945 // For calls that may call functions that use varargs or stdargs
2946 // (prototype-less calls or calls to functions containing ellipsis (...) in
2947 // the declaration) %al is used as hidden argument to specify the number
2948 // of SSE registers used. The contents of %al do not need to match exactly
2949 // the number of registers, but must be an ubound on the number of SSE
2950 // registers used and is in the range 0 - 8 inclusive.
2952 // Count the number of XMM registers allocated.
2953 static const MCPhysReg XMMArgRegs[] = {
2954 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2955 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2957 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2958 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2959 && "SSE registers cannot be used when SSE is disabled");
2961 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2962 DAG.getConstant(NumXMMRegs, MVT::i8)));
2965 if (Is64Bit && isVarArg && IsMustTail) {
2966 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2967 for (const auto &F : Forwards) {
2968 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2969 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2973 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2974 // don't need this because the eligibility check rejects calls that require
2975 // shuffling arguments passed in memory.
2976 if (!IsSibcall && isTailCall) {
2977 // Force all the incoming stack arguments to be loaded from the stack
2978 // before any new outgoing arguments are stored to the stack, because the
2979 // outgoing stack slots may alias the incoming argument stack slots, and
2980 // the alias isn't otherwise explicit. This is slightly more conservative
2981 // than necessary, because it means that each store effectively depends
2982 // on every argument instead of just those arguments it would clobber.
2983 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2985 SmallVector<SDValue, 8> MemOpChains2;
2988 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2989 CCValAssign &VA = ArgLocs[i];
2992 assert(VA.isMemLoc());
2993 SDValue Arg = OutVals[i];
2994 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2995 // Skip inalloca arguments. They don't require any work.
2996 if (Flags.isInAlloca())
2998 // Create frame index.
2999 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3000 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3001 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3002 FIN = DAG.getFrameIndex(FI, getPointerTy());
3004 if (Flags.isByVal()) {
3005 // Copy relative to framepointer.
3006 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3007 if (!StackPtr.getNode())
3008 StackPtr = DAG.getCopyFromReg(Chain, dl,
3009 RegInfo->getStackRegister(),
3011 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3013 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3017 // Store relative to framepointer.
3018 MemOpChains2.push_back(
3019 DAG.getStore(ArgChain, dl, Arg, FIN,
3020 MachinePointerInfo::getFixedStack(FI),
3025 if (!MemOpChains2.empty())
3026 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3028 // Store the return address to the appropriate stack slot.
3029 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3030 getPointerTy(), RegInfo->getSlotSize(),
3034 // Build a sequence of copy-to-reg nodes chained together with token chain
3035 // and flag operands which copy the outgoing args into registers.
3037 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3038 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3039 RegsToPass[i].second, InFlag);
3040 InFlag = Chain.getValue(1);
3043 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3044 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3045 // In the 64-bit large code model, we have to make all calls
3046 // through a register, since the call instruction's 32-bit
3047 // pc-relative offset may not be large enough to hold the whole
3049 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3050 // If the callee is a GlobalAddress node (quite common, every direct call
3051 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3054 // We should use extra load for direct calls to dllimported functions in
3056 const GlobalValue *GV = G->getGlobal();
3057 if (!GV->hasDLLImportStorageClass()) {
3058 unsigned char OpFlags = 0;
3059 bool ExtraLoad = false;
3060 unsigned WrapperKind = ISD::DELETED_NODE;
3062 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3063 // external symbols most go through the PLT in PIC mode. If the symbol
3064 // has hidden or protected visibility, or if it is static or local, then
3065 // we don't need to use the PLT - we can directly call it.
3066 if (Subtarget->isTargetELF() &&
3067 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3068 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3069 OpFlags = X86II::MO_PLT;
3070 } else if (Subtarget->isPICStyleStubAny() &&
3071 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3072 (!Subtarget->getTargetTriple().isMacOSX() ||
3073 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3074 // PC-relative references to external symbols should go through $stub,
3075 // unless we're building with the leopard linker or later, which
3076 // automatically synthesizes these stubs.
3077 OpFlags = X86II::MO_DARWIN_STUB;
3078 } else if (Subtarget->isPICStyleRIPRel() &&
3079 isa<Function>(GV) &&
3080 cast<Function>(GV)->getAttributes().
3081 hasAttribute(AttributeSet::FunctionIndex,
3082 Attribute::NonLazyBind)) {
3083 // If the function is marked as non-lazy, generate an indirect call
3084 // which loads from the GOT directly. This avoids runtime overhead
3085 // at the cost of eager binding (and one extra byte of encoding).
3086 OpFlags = X86II::MO_GOTPCREL;
3087 WrapperKind = X86ISD::WrapperRIP;
3091 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3092 G->getOffset(), OpFlags);
3094 // Add a wrapper if needed.
3095 if (WrapperKind != ISD::DELETED_NODE)
3096 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3097 // Add extra indirection if needed.
3099 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3100 MachinePointerInfo::getGOT(),
3101 false, false, false, 0);
3103 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3104 unsigned char OpFlags = 0;
3106 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3107 // external symbols should go through the PLT.
3108 if (Subtarget->isTargetELF() &&
3109 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3110 OpFlags = X86II::MO_PLT;
3111 } else if (Subtarget->isPICStyleStubAny() &&
3112 (!Subtarget->getTargetTriple().isMacOSX() ||
3113 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3114 // PC-relative references to external symbols should go through $stub,
3115 // unless we're building with the leopard linker or later, which
3116 // automatically synthesizes these stubs.
3117 OpFlags = X86II::MO_DARWIN_STUB;
3120 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 // Returns a chain & a flag for retval copy to use.
3125 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3126 SmallVector<SDValue, 8> Ops;
3128 if (!IsSibcall && isTailCall) {
3129 Chain = DAG.getCALLSEQ_END(Chain,
3130 DAG.getIntPtrConstant(NumBytesToPop, true),
3131 DAG.getIntPtrConstant(0, true), InFlag, dl);
3132 InFlag = Chain.getValue(1);
3135 Ops.push_back(Chain);
3136 Ops.push_back(Callee);
3139 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3141 // Add argument registers to the end of the list so that they are known live
3143 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3144 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3145 RegsToPass[i].second.getValueType()));
3147 // Add a register mask operand representing the call-preserved registers.
3148 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3149 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3150 assert(Mask && "Missing call preserved mask for calling convention");
3151 Ops.push_back(DAG.getRegisterMask(Mask));
3153 if (InFlag.getNode())
3154 Ops.push_back(InFlag);
3158 //// If this is the first return lowered for this function, add the regs
3159 //// to the liveout set for the function.
3160 // This isn't right, although it's probably harmless on x86; liveouts
3161 // should be computed from returns not tail calls. Consider a void
3162 // function making a tail call to a function returning int.
3163 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3166 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3167 InFlag = Chain.getValue(1);
3169 // Create the CALLSEQ_END node.
3170 unsigned NumBytesForCalleeToPop;
3171 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3172 DAG.getTarget().Options.GuaranteedTailCallOpt))
3173 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3174 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3175 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3176 SR == StackStructReturn)
3177 // If this is a call to a struct-return function, the callee
3178 // pops the hidden struct pointer, so we have to push it back.
3179 // This is common for Darwin/X86, Linux & Mingw32 targets.
3180 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3181 NumBytesForCalleeToPop = 4;
3183 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3185 // Returns a flag for retval copy to use.
3187 Chain = DAG.getCALLSEQ_END(Chain,
3188 DAG.getIntPtrConstant(NumBytesToPop, true),
3189 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3192 InFlag = Chain.getValue(1);
3195 // Handle result values, copying them out of physregs into vregs that we
3197 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3198 Ins, dl, DAG, InVals);
3201 //===----------------------------------------------------------------------===//
3202 // Fast Calling Convention (tail call) implementation
3203 //===----------------------------------------------------------------------===//
3205 // Like std call, callee cleans arguments, convention except that ECX is
3206 // reserved for storing the tail called function address. Only 2 registers are
3207 // free for argument passing (inreg). Tail call optimization is performed
3209 // * tailcallopt is enabled
3210 // * caller/callee are fastcc
3211 // On X86_64 architecture with GOT-style position independent code only local
3212 // (within module) calls are supported at the moment.
3213 // To keep the stack aligned according to platform abi the function
3214 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3215 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3216 // If a tail called function callee has more arguments than the caller the
3217 // caller needs to make sure that there is room to move the RETADDR to. This is
3218 // achieved by reserving an area the size of the argument delta right after the
3219 // original RETADDR, but before the saved framepointer or the spilled registers
3220 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3232 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3233 /// for a 16 byte align requirement.
3235 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3236 SelectionDAG& DAG) const {
3237 MachineFunction &MF = DAG.getMachineFunction();
3238 const TargetMachine &TM = MF.getTarget();
3239 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3240 TM.getSubtargetImpl()->getRegisterInfo());
3241 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3242 unsigned StackAlignment = TFI.getStackAlignment();
3243 uint64_t AlignMask = StackAlignment - 1;
3244 int64_t Offset = StackSize;
3245 unsigned SlotSize = RegInfo->getSlotSize();
3246 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3247 // Number smaller than 12 so just add the difference.
3248 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3250 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3251 Offset = ((~AlignMask) & Offset) + StackAlignment +
3252 (StackAlignment-SlotSize);
3257 /// MatchingStackOffset - Return true if the given stack call argument is
3258 /// already available in the same position (relatively) of the caller's
3259 /// incoming argument stack.
3261 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3262 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3263 const X86InstrInfo *TII) {
3264 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3266 if (Arg.getOpcode() == ISD::CopyFromReg) {
3267 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3268 if (!TargetRegisterInfo::isVirtualRegister(VR))
3270 MachineInstr *Def = MRI->getVRegDef(VR);
3273 if (!Flags.isByVal()) {
3274 if (!TII->isLoadFromStackSlot(Def, FI))
3277 unsigned Opcode = Def->getOpcode();
3278 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3279 Def->getOperand(1).isFI()) {
3280 FI = Def->getOperand(1).getIndex();
3281 Bytes = Flags.getByValSize();
3285 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3286 if (Flags.isByVal())
3287 // ByVal argument is passed in as a pointer but it's now being
3288 // dereferenced. e.g.
3289 // define @foo(%struct.X* %A) {
3290 // tail call @bar(%struct.X* byval %A)
3293 SDValue Ptr = Ld->getBasePtr();
3294 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3297 FI = FINode->getIndex();
3298 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3299 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3300 FI = FINode->getIndex();
3301 Bytes = Flags.getByValSize();
3305 assert(FI != INT_MAX);
3306 if (!MFI->isFixedObjectIndex(FI))
3308 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3311 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3312 /// for tail call optimization. Targets which want to do tail call
3313 /// optimization should implement this function.
3315 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3316 CallingConv::ID CalleeCC,
3318 bool isCalleeStructRet,
3319 bool isCallerStructRet,
3321 const SmallVectorImpl<ISD::OutputArg> &Outs,
3322 const SmallVectorImpl<SDValue> &OutVals,
3323 const SmallVectorImpl<ISD::InputArg> &Ins,
3324 SelectionDAG &DAG) const {
3325 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3328 // If -tailcallopt is specified, make fastcc functions tail-callable.
3329 const MachineFunction &MF = DAG.getMachineFunction();
3330 const Function *CallerF = MF.getFunction();
3332 // If the function return type is x86_fp80 and the callee return type is not,
3333 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3334 // perform a tailcall optimization here.
3335 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3338 CallingConv::ID CallerCC = CallerF->getCallingConv();
3339 bool CCMatch = CallerCC == CalleeCC;
3340 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3341 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3343 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3344 if (IsTailCallConvention(CalleeCC) && CCMatch)
3349 // Look for obvious safe cases to perform tail call optimization that do not
3350 // require ABI changes. This is what gcc calls sibcall.
3352 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3353 // emit a special epilogue.
3354 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3355 DAG.getSubtarget().getRegisterInfo());
3356 if (RegInfo->needsStackRealignment(MF))
3359 // Also avoid sibcall optimization if either caller or callee uses struct
3360 // return semantics.
3361 if (isCalleeStructRet || isCallerStructRet)
3364 // An stdcall/thiscall caller is expected to clean up its arguments; the
3365 // callee isn't going to do that.
3366 // FIXME: this is more restrictive than needed. We could produce a tailcall
3367 // when the stack adjustment matches. For example, with a thiscall that takes
3368 // only one argument.
3369 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3370 CallerCC == CallingConv::X86_ThisCall))
3373 // Do not sibcall optimize vararg calls unless all arguments are passed via
3375 if (isVarArg && !Outs.empty()) {
3377 // Optimizing for varargs on Win64 is unlikely to be safe without
3378 // additional testing.
3379 if (IsCalleeWin64 || IsCallerWin64)
3382 SmallVector<CCValAssign, 16> ArgLocs;
3383 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3386 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3387 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3388 if (!ArgLocs[i].isRegLoc())
3392 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3393 // stack. Therefore, if it's not used by the call it is not safe to optimize
3394 // this into a sibcall.
3395 bool Unused = false;
3396 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3403 SmallVector<CCValAssign, 16> RVLocs;
3404 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3406 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3407 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3408 CCValAssign &VA = RVLocs[i];
3409 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3414 // If the calling conventions do not match, then we'd better make sure the
3415 // results are returned in the same way as what the caller expects.
3417 SmallVector<CCValAssign, 16> RVLocs1;
3418 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3420 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3422 SmallVector<CCValAssign, 16> RVLocs2;
3423 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3425 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3427 if (RVLocs1.size() != RVLocs2.size())
3429 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3430 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3432 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3434 if (RVLocs1[i].isRegLoc()) {
3435 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3438 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3444 // If the callee takes no arguments then go on to check the results of the
3446 if (!Outs.empty()) {
3447 // Check if stack adjustment is needed. For now, do not do this if any
3448 // argument is passed on the stack.
3449 SmallVector<CCValAssign, 16> ArgLocs;
3450 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3453 // Allocate shadow area for Win64
3455 CCInfo.AllocateStack(32, 8);
3457 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3458 if (CCInfo.getNextStackOffset()) {
3459 MachineFunction &MF = DAG.getMachineFunction();
3460 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3463 // Check if the arguments are already laid out in the right way as
3464 // the caller's fixed stack objects.
3465 MachineFrameInfo *MFI = MF.getFrameInfo();
3466 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3467 const X86InstrInfo *TII =
3468 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3469 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3470 CCValAssign &VA = ArgLocs[i];
3471 SDValue Arg = OutVals[i];
3472 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3473 if (VA.getLocInfo() == CCValAssign::Indirect)
3475 if (!VA.isRegLoc()) {
3476 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3483 // If the tailcall address may be in a register, then make sure it's
3484 // possible to register allocate for it. In 32-bit, the call address can
3485 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3486 // callee-saved registers are restored. These happen to be the same
3487 // registers used to pass 'inreg' arguments so watch out for those.
3488 if (!Subtarget->is64Bit() &&
3489 ((!isa<GlobalAddressSDNode>(Callee) &&
3490 !isa<ExternalSymbolSDNode>(Callee)) ||
3491 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3492 unsigned NumInRegs = 0;
3493 // In PIC we need an extra register to formulate the address computation
3495 unsigned MaxInRegs =
3496 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3498 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3499 CCValAssign &VA = ArgLocs[i];
3502 unsigned Reg = VA.getLocReg();
3505 case X86::EAX: case X86::EDX: case X86::ECX:
3506 if (++NumInRegs == MaxInRegs)
3518 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3519 const TargetLibraryInfo *libInfo) const {
3520 return X86::createFastISel(funcInfo, libInfo);
3523 //===----------------------------------------------------------------------===//
3524 // Other Lowering Hooks
3525 //===----------------------------------------------------------------------===//
3527 static bool MayFoldLoad(SDValue Op) {
3528 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3531 static bool MayFoldIntoStore(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3535 static bool isTargetShuffle(unsigned Opcode) {
3537 default: return false;
3538 case X86ISD::PSHUFB:
3539 case X86ISD::PSHUFD:
3540 case X86ISD::PSHUFHW:
3541 case X86ISD::PSHUFLW:
3543 case X86ISD::PALIGNR:
3544 case X86ISD::MOVLHPS:
3545 case X86ISD::MOVLHPD:
3546 case X86ISD::MOVHLPS:
3547 case X86ISD::MOVLPS:
3548 case X86ISD::MOVLPD:
3549 case X86ISD::MOVSHDUP:
3550 case X86ISD::MOVSLDUP:
3551 case X86ISD::MOVDDUP:
3554 case X86ISD::UNPCKL:
3555 case X86ISD::UNPCKH:
3556 case X86ISD::VPERMILP:
3557 case X86ISD::VPERM2X128:
3558 case X86ISD::VPERMI:
3563 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3564 SDValue V1, SelectionDAG &DAG) {
3566 default: llvm_unreachable("Unknown x86 shuffle node");
3567 case X86ISD::MOVSHDUP:
3568 case X86ISD::MOVSLDUP:
3569 case X86ISD::MOVDDUP:
3570 return DAG.getNode(Opc, dl, VT, V1);
3574 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3575 SDValue V1, unsigned TargetMask,
3576 SelectionDAG &DAG) {
3578 default: llvm_unreachable("Unknown x86 shuffle node");
3579 case X86ISD::PSHUFD:
3580 case X86ISD::PSHUFHW:
3581 case X86ISD::PSHUFLW:
3582 case X86ISD::VPERMILP:
3583 case X86ISD::VPERMI:
3584 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3588 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3589 SDValue V1, SDValue V2, unsigned TargetMask,
3590 SelectionDAG &DAG) {
3592 default: llvm_unreachable("Unknown x86 shuffle node");
3593 case X86ISD::PALIGNR:
3594 case X86ISD::VALIGN:
3596 case X86ISD::VPERM2X128:
3597 return DAG.getNode(Opc, dl, VT, V1, V2,
3598 DAG.getConstant(TargetMask, MVT::i8));
3602 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3603 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3605 default: llvm_unreachable("Unknown x86 shuffle node");
3606 case X86ISD::MOVLHPS:
3607 case X86ISD::MOVLHPD:
3608 case X86ISD::MOVHLPS:
3609 case X86ISD::MOVLPS:
3610 case X86ISD::MOVLPD:
3613 case X86ISD::UNPCKL:
3614 case X86ISD::UNPCKH:
3615 return DAG.getNode(Opc, dl, VT, V1, V2);
3619 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3620 MachineFunction &MF = DAG.getMachineFunction();
3621 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3622 DAG.getSubtarget().getRegisterInfo());
3623 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3624 int ReturnAddrIndex = FuncInfo->getRAIndex();
3626 if (ReturnAddrIndex == 0) {
3627 // Set up a frame object for the return address.
3628 unsigned SlotSize = RegInfo->getSlotSize();
3629 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3632 FuncInfo->setRAIndex(ReturnAddrIndex);
3635 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3638 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3639 bool hasSymbolicDisplacement) {
3640 // Offset should fit into 32 bit immediate field.
3641 if (!isInt<32>(Offset))
3644 // If we don't have a symbolic displacement - we don't have any extra
3646 if (!hasSymbolicDisplacement)
3649 // FIXME: Some tweaks might be needed for medium code model.
3650 if (M != CodeModel::Small && M != CodeModel::Kernel)
3653 // For small code model we assume that latest object is 16MB before end of 31
3654 // bits boundary. We may also accept pretty large negative constants knowing
3655 // that all objects are in the positive half of address space.
3656 if (M == CodeModel::Small && Offset < 16*1024*1024)
3659 // For kernel code model we know that all object resist in the negative half
3660 // of 32bits address space. We may not accept negative offsets, since they may
3661 // be just off and we may accept pretty large positive ones.
3662 if (M == CodeModel::Kernel && Offset > 0)
3668 /// isCalleePop - Determines whether the callee is required to pop its
3669 /// own arguments. Callee pop is necessary to support tail calls.
3670 bool X86::isCalleePop(CallingConv::ID CallingConv,
3671 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3672 switch (CallingConv) {
3675 case CallingConv::X86_StdCall:
3676 case CallingConv::X86_FastCall:
3677 case CallingConv::X86_ThisCall:
3679 case CallingConv::Fast:
3680 case CallingConv::GHC:
3681 case CallingConv::HiPE:
3688 /// \brief Return true if the condition is an unsigned comparison operation.
3689 static bool isX86CCUnsigned(unsigned X86CC) {
3691 default: llvm_unreachable("Invalid integer condition!");
3692 case X86::COND_E: return true;
3693 case X86::COND_G: return false;
3694 case X86::COND_GE: return false;
3695 case X86::COND_L: return false;
3696 case X86::COND_LE: return false;
3697 case X86::COND_NE: return true;
3698 case X86::COND_B: return true;
3699 case X86::COND_A: return true;
3700 case X86::COND_BE: return true;
3701 case X86::COND_AE: return true;
3703 llvm_unreachable("covered switch fell through?!");
3706 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3707 /// specific condition code, returning the condition code and the LHS/RHS of the
3708 /// comparison to make.
3709 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3710 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3712 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3713 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3714 // X > -1 -> X == 0, jump !sign.
3715 RHS = DAG.getConstant(0, RHS.getValueType());
3716 return X86::COND_NS;
3718 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3719 // X < 0 -> X == 0, jump on sign.
3722 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3724 RHS = DAG.getConstant(0, RHS.getValueType());
3725 return X86::COND_LE;
3729 switch (SetCCOpcode) {
3730 default: llvm_unreachable("Invalid integer condition!");
3731 case ISD::SETEQ: return X86::COND_E;
3732 case ISD::SETGT: return X86::COND_G;
3733 case ISD::SETGE: return X86::COND_GE;
3734 case ISD::SETLT: return X86::COND_L;
3735 case ISD::SETLE: return X86::COND_LE;
3736 case ISD::SETNE: return X86::COND_NE;
3737 case ISD::SETULT: return X86::COND_B;
3738 case ISD::SETUGT: return X86::COND_A;
3739 case ISD::SETULE: return X86::COND_BE;
3740 case ISD::SETUGE: return X86::COND_AE;
3744 // First determine if it is required or is profitable to flip the operands.
3746 // If LHS is a foldable load, but RHS is not, flip the condition.
3747 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3748 !ISD::isNON_EXTLoad(RHS.getNode())) {
3749 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3750 std::swap(LHS, RHS);
3753 switch (SetCCOpcode) {
3759 std::swap(LHS, RHS);
3763 // On a floating point condition, the flags are set as follows:
3765 // 0 | 0 | 0 | X > Y
3766 // 0 | 0 | 1 | X < Y
3767 // 1 | 0 | 0 | X == Y
3768 // 1 | 1 | 1 | unordered
3769 switch (SetCCOpcode) {
3770 default: llvm_unreachable("Condcode should be pre-legalized away");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETOLT: // flipped
3775 case ISD::SETGT: return X86::COND_A;
3776 case ISD::SETOLE: // flipped
3778 case ISD::SETGE: return X86::COND_AE;
3779 case ISD::SETUGT: // flipped
3781 case ISD::SETLT: return X86::COND_B;
3782 case ISD::SETUGE: // flipped
3784 case ISD::SETLE: return X86::COND_BE;
3786 case ISD::SETNE: return X86::COND_NE;
3787 case ISD::SETUO: return X86::COND_P;
3788 case ISD::SETO: return X86::COND_NP;
3790 case ISD::SETUNE: return X86::COND_INVALID;
3794 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3795 /// code. Current x86 isa includes the following FP cmov instructions:
3796 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3797 static bool hasFPCMov(unsigned X86CC) {
3813 /// isFPImmLegal - Returns true if the target can instruction select the
3814 /// specified FP immediate natively. If false, the legalizer will
3815 /// materialize the FP immediate as a load from a constant pool.
3816 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3817 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3818 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3824 /// \brief Returns true if it is beneficial to convert a load of a constant
3825 /// to just the constant itself.
3826 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3828 assert(Ty->isIntegerTy());
3830 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3831 if (BitSize == 0 || BitSize > 64)
3836 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3837 /// the specified range (L, H].
3838 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3839 return (Val < 0) || (Val >= Low && Val < Hi);
3842 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3843 /// specified value.
3844 static bool isUndefOrEqual(int Val, int CmpVal) {
3845 return (Val < 0 || Val == CmpVal);
3848 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3849 /// from position Pos and ending in Pos+Size, falls within the specified
3850 /// sequential range (L, L+Pos]. or is undef.
3851 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3852 unsigned Pos, unsigned Size, int Low) {
3853 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3854 if (!isUndefOrEqual(Mask[i], Low))
3859 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3860 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3861 /// the second operand.
3862 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3863 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3864 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3865 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3866 return (Mask[0] < 2 && Mask[1] < 2);
3870 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3871 /// is suitable for input to PSHUFHW.
3872 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3873 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3876 // Lower quadword copied in order or undef.
3877 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3880 // Upper quadword shuffled.
3881 for (unsigned i = 4; i != 8; ++i)
3882 if (!isUndefOrInRange(Mask[i], 4, 8))
3885 if (VT == MVT::v16i16) {
3886 // Lower quadword copied in order or undef.
3887 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3890 // Upper quadword shuffled.
3891 for (unsigned i = 12; i != 16; ++i)
3892 if (!isUndefOrInRange(Mask[i], 12, 16))
3899 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3900 /// is suitable for input to PSHUFLW.
3901 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3902 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3905 // Upper quadword copied in order.
3906 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3909 // Lower quadword shuffled.
3910 for (unsigned i = 0; i != 4; ++i)
3911 if (!isUndefOrInRange(Mask[i], 0, 4))
3914 if (VT == MVT::v16i16) {
3915 // Upper quadword copied in order.
3916 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3919 // Lower quadword shuffled.
3920 for (unsigned i = 8; i != 12; ++i)
3921 if (!isUndefOrInRange(Mask[i], 8, 12))
3928 /// \brief Return true if the mask specifies a shuffle of elements that is
3929 /// suitable for input to intralane (palignr) or interlane (valign) vector
3931 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3932 unsigned NumElts = VT.getVectorNumElements();
3933 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3934 unsigned NumLaneElts = NumElts/NumLanes;
3936 // Do not handle 64-bit element shuffles with palignr.
3937 if (NumLaneElts == 2)
3940 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3942 for (i = 0; i != NumLaneElts; ++i) {
3947 // Lane is all undef, go to next lane
3948 if (i == NumLaneElts)
3951 int Start = Mask[i+l];
3953 // Make sure its in this lane in one of the sources
3954 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3955 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3958 // If not lane 0, then we must match lane 0
3959 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3962 // Correct second source to be contiguous with first source
3963 if (Start >= (int)NumElts)
3964 Start -= NumElts - NumLaneElts;
3966 // Make sure we're shifting in the right direction.
3967 if (Start <= (int)(i+l))
3972 // Check the rest of the elements to see if they are consecutive.
3973 for (++i; i != NumLaneElts; ++i) {
3974 int Idx = Mask[i+l];
3976 // Make sure its in this lane
3977 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3978 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3981 // If not lane 0, then we must match lane 0
3982 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3985 if (Idx >= (int)NumElts)
3986 Idx -= NumElts - NumLaneElts;
3988 if (!isUndefOrEqual(Idx, Start+i))
3997 /// \brief Return true if the node specifies a shuffle of elements that is
3998 /// suitable for input to PALIGNR.
3999 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4000 const X86Subtarget *Subtarget) {
4001 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4002 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4003 VT.is512BitVector())
4004 // FIXME: Add AVX512BW.
4007 return isAlignrMask(Mask, VT, false);
4010 /// \brief Return true if the node specifies a shuffle of elements that is
4011 /// suitable for input to VALIGN.
4012 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4013 const X86Subtarget *Subtarget) {
4014 // FIXME: Add AVX512VL.
4015 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4017 return isAlignrMask(Mask, VT, true);
4020 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4021 /// the two vector operands have swapped position.
4022 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4023 unsigned NumElems) {
4024 for (unsigned i = 0; i != NumElems; ++i) {
4028 else if (idx < (int)NumElems)
4029 Mask[i] = idx + NumElems;
4031 Mask[i] = idx - NumElems;
4035 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4036 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4037 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4038 /// reverse of what x86 shuffles want.
4039 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4041 unsigned NumElems = VT.getVectorNumElements();
4042 unsigned NumLanes = VT.getSizeInBits()/128;
4043 unsigned NumLaneElems = NumElems/NumLanes;
4045 if (NumLaneElems != 2 && NumLaneElems != 4)
4048 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4049 bool symetricMaskRequired =
4050 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4052 // VSHUFPSY divides the resulting vector into 4 chunks.
4053 // The sources are also splitted into 4 chunks, and each destination
4054 // chunk must come from a different source chunk.
4056 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4057 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4059 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4060 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4062 // VSHUFPDY divides the resulting vector into 4 chunks.
4063 // The sources are also splitted into 4 chunks, and each destination
4064 // chunk must come from a different source chunk.
4066 // SRC1 => X3 X2 X1 X0
4067 // SRC2 => Y3 Y2 Y1 Y0
4069 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4071 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4072 unsigned HalfLaneElems = NumLaneElems/2;
4073 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4074 for (unsigned i = 0; i != NumLaneElems; ++i) {
4075 int Idx = Mask[i+l];
4076 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4077 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4079 // For VSHUFPSY, the mask of the second half must be the same as the
4080 // first but with the appropriate offsets. This works in the same way as
4081 // VPERMILPS works with masks.
4082 if (!symetricMaskRequired || Idx < 0)
4084 if (MaskVal[i] < 0) {
4085 MaskVal[i] = Idx - l;
4088 if ((signed)(Idx - l) != MaskVal[i])
4096 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4097 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4098 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4099 if (!VT.is128BitVector())
4102 unsigned NumElems = VT.getVectorNumElements();
4107 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4108 return isUndefOrEqual(Mask[0], 6) &&
4109 isUndefOrEqual(Mask[1], 7) &&
4110 isUndefOrEqual(Mask[2], 2) &&
4111 isUndefOrEqual(Mask[3], 3);
4114 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4115 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4117 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4118 if (!VT.is128BitVector())
4121 unsigned NumElems = VT.getVectorNumElements();
4126 return isUndefOrEqual(Mask[0], 2) &&
4127 isUndefOrEqual(Mask[1], 3) &&
4128 isUndefOrEqual(Mask[2], 2) &&
4129 isUndefOrEqual(Mask[3], 3);
4132 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4133 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4134 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4135 if (!VT.is128BitVector())
4138 unsigned NumElems = VT.getVectorNumElements();
4140 if (NumElems != 2 && NumElems != 4)
4143 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4144 if (!isUndefOrEqual(Mask[i], i + NumElems))
4147 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i))
4154 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4155 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4156 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4157 if (!VT.is128BitVector())
4160 unsigned NumElems = VT.getVectorNumElements();
4162 if (NumElems != 2 && NumElems != 4)
4165 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4166 if (!isUndefOrEqual(Mask[i], i))
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4176 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4177 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4178 /// i. e: If all but one element come from the same vector.
4179 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4180 // TODO: Deal with AVX's VINSERTPS
4181 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4184 unsigned CorrectPosV1 = 0;
4185 unsigned CorrectPosV2 = 0;
4186 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4187 if (Mask[i] == -1) {
4195 else if (Mask[i] == i + 4)
4199 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4200 // We have 3 elements (undefs count as elements from any vector) from one
4201 // vector, and one from another.
4208 // Some special combinations that can be optimized.
4211 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4212 SelectionDAG &DAG) {
4213 MVT VT = SVOp->getSimpleValueType(0);
4216 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4219 ArrayRef<int> Mask = SVOp->getMask();
4221 // These are the special masks that may be optimized.
4222 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4223 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4224 bool MatchEvenMask = true;
4225 bool MatchOddMask = true;
4226 for (int i=0; i<8; ++i) {
4227 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4228 MatchEvenMask = false;
4229 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4230 MatchOddMask = false;
4233 if (!MatchEvenMask && !MatchOddMask)
4236 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4238 SDValue Op0 = SVOp->getOperand(0);
4239 SDValue Op1 = SVOp->getOperand(1);
4241 if (MatchEvenMask) {
4242 // Shift the second operand right to 32 bits.
4243 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4244 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4246 // Shift the first operand left to 32 bits.
4247 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4248 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4250 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4251 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4254 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4255 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4256 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4257 bool HasInt256, bool V2IsSplat = false) {
4259 assert(VT.getSizeInBits() >= 128 &&
4260 "Unsupported vector type for unpckl");
4262 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4264 unsigned NumOf256BitLanes;
4265 unsigned NumElts = VT.getVectorNumElements();
4266 if (VT.is256BitVector()) {
4267 if (NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 NumOf256BitLanes = 1;
4272 } else if (VT.is512BitVector()) {
4273 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4274 "Unsupported vector type for unpckh");
4276 NumOf256BitLanes = 2;
4279 NumOf256BitLanes = 1;
4282 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4283 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4285 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4286 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l256*NumEltsInStride+l+i];
4289 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4290 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4292 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4294 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4302 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4303 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4304 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4305 bool HasInt256, bool V2IsSplat = false) {
4306 assert(VT.getSizeInBits() >= 128 &&
4307 "Unsupported vector type for unpckh");
4309 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4311 unsigned NumOf256BitLanes;
4312 unsigned NumElts = VT.getVectorNumElements();
4313 if (VT.is256BitVector()) {
4314 if (NumElts != 4 && NumElts != 8 &&
4315 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4318 NumOf256BitLanes = 1;
4319 } else if (VT.is512BitVector()) {
4320 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4321 "Unsupported vector type for unpckh");
4323 NumOf256BitLanes = 2;
4326 NumOf256BitLanes = 1;
4329 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4330 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4332 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4333 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4334 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4335 int BitI = Mask[l256*NumEltsInStride+l+i];
4336 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4337 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4339 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4341 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4349 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4350 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4352 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4353 unsigned NumElts = VT.getVectorNumElements();
4354 bool Is256BitVec = VT.is256BitVector();
4356 if (VT.is512BitVector())
4358 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4359 "Unsupported vector type for unpckh");
4361 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4362 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4365 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4366 // FIXME: Need a better way to get rid of this, there's no latency difference
4367 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4368 // the former later. We should also remove the "_undef" special mask.
4369 if (NumElts == 4 && Is256BitVec)
4372 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4373 // independently on 128-bit lanes.
4374 unsigned NumLanes = VT.getSizeInBits()/128;
4375 unsigned NumLaneElts = NumElts/NumLanes;
4377 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4378 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4379 int BitI = Mask[l+i];
4380 int BitI1 = Mask[l+i+1];
4382 if (!isUndefOrEqual(BitI, j))
4384 if (!isUndefOrEqual(BitI1, j))
4392 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4393 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4395 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4396 unsigned NumElts = VT.getVectorNumElements();
4398 if (VT.is512BitVector())
4401 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4402 "Unsupported vector type for unpckh");
4404 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4405 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4408 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4409 // independently on 128-bit lanes.
4410 unsigned NumLanes = VT.getSizeInBits()/128;
4411 unsigned NumLaneElts = NumElts/NumLanes;
4413 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4414 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4415 int BitI = Mask[l+i];
4416 int BitI1 = Mask[l+i+1];
4417 if (!isUndefOrEqual(BitI, j))
4419 if (!isUndefOrEqual(BitI1, j))
4426 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4427 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4428 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4429 if (!VT.is512BitVector())
4432 unsigned NumElts = VT.getVectorNumElements();
4433 unsigned HalfSize = NumElts/2;
4434 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4435 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4440 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4441 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4449 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4450 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4451 /// MOVSD, and MOVD, i.e. setting the lowest element.
4452 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4453 if (VT.getVectorElementType().getSizeInBits() < 32)
4455 if (!VT.is128BitVector())
4458 unsigned NumElts = VT.getVectorNumElements();
4460 if (!isUndefOrEqual(Mask[0], NumElts))
4463 for (unsigned i = 1; i != NumElts; ++i)
4464 if (!isUndefOrEqual(Mask[i], i))
4470 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4471 /// as permutations between 128-bit chunks or halves. As an example: this
4473 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4474 /// The first half comes from the second half of V1 and the second half from the
4475 /// the second half of V2.
4476 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4477 if (!HasFp256 || !VT.is256BitVector())
4480 // The shuffle result is divided into half A and half B. In total the two
4481 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4482 // B must come from C, D, E or F.
4483 unsigned HalfSize = VT.getVectorNumElements()/2;
4484 bool MatchA = false, MatchB = false;
4486 // Check if A comes from one of C, D, E, F.
4487 for (unsigned Half = 0; Half != 4; ++Half) {
4488 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4494 // Check if B comes from one of C, D, E, F.
4495 for (unsigned Half = 0; Half != 4; ++Half) {
4496 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4502 return MatchA && MatchB;
4505 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4506 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4507 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4508 MVT VT = SVOp->getSimpleValueType(0);
4510 unsigned HalfSize = VT.getVectorNumElements()/2;
4512 unsigned FstHalf = 0, SndHalf = 0;
4513 for (unsigned i = 0; i < HalfSize; ++i) {
4514 if (SVOp->getMaskElt(i) > 0) {
4515 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4519 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4520 if (SVOp->getMaskElt(i) > 0) {
4521 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4526 return (FstHalf | (SndHalf << 4));
4529 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4530 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4531 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4535 unsigned NumElts = VT.getVectorNumElements();
4537 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4538 for (unsigned i = 0; i != NumElts; ++i) {
4541 Imm8 |= Mask[i] << (i*2);
4546 unsigned LaneSize = 4;
4547 SmallVector<int, 4> MaskVal(LaneSize, -1);
4549 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4550 for (unsigned i = 0; i != LaneSize; ++i) {
4551 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4555 if (MaskVal[i] < 0) {
4556 MaskVal[i] = Mask[i+l] - l;
4557 Imm8 |= MaskVal[i] << (i*2);
4560 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4567 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4568 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4569 /// Note that VPERMIL mask matching is different depending whether theunderlying
4570 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4571 /// to the same elements of the low, but to the higher half of the source.
4572 /// In VPERMILPD the two lanes could be shuffled independently of each other
4573 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4574 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4575 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4576 if (VT.getSizeInBits() < 256 || EltSize < 32)
4578 bool symetricMaskRequired = (EltSize == 32);
4579 unsigned NumElts = VT.getVectorNumElements();
4581 unsigned NumLanes = VT.getSizeInBits()/128;
4582 unsigned LaneSize = NumElts/NumLanes;
4583 // 2 or 4 elements in one lane
4585 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4586 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4587 for (unsigned i = 0; i != LaneSize; ++i) {
4588 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4590 if (symetricMaskRequired) {
4591 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4592 ExpectedMaskVal[i] = Mask[i+l] - l;
4595 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4603 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4604 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4605 /// element of vector 2 and the other elements to come from vector 1 in order.
4606 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4607 bool V2IsSplat = false, bool V2IsUndef = false) {
4608 if (!VT.is128BitVector())
4611 unsigned NumOps = VT.getVectorNumElements();
4612 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4615 if (!isUndefOrEqual(Mask[0], 0))
4618 for (unsigned i = 1; i != NumOps; ++i)
4619 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4620 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4621 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4627 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4628 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4629 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4630 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4631 const X86Subtarget *Subtarget) {
4632 if (!Subtarget->hasSSE3())
4635 unsigned NumElems = VT.getVectorNumElements();
4637 if ((VT.is128BitVector() && NumElems != 4) ||
4638 (VT.is256BitVector() && NumElems != 8) ||
4639 (VT.is512BitVector() && NumElems != 16))
4642 // "i+1" is the value the indexed mask element must have
4643 for (unsigned i = 0; i != NumElems; i += 2)
4644 if (!isUndefOrEqual(Mask[i], i+1) ||
4645 !isUndefOrEqual(Mask[i+1], i+1))
4651 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4652 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4653 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4654 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4655 const X86Subtarget *Subtarget) {
4656 if (!Subtarget->hasSSE3())
4659 unsigned NumElems = VT.getVectorNumElements();
4661 if ((VT.is128BitVector() && NumElems != 4) ||
4662 (VT.is256BitVector() && NumElems != 8) ||
4663 (VT.is512BitVector() && NumElems != 16))
4666 // "i" is the value the indexed mask element must have
4667 for (unsigned i = 0; i != NumElems; i += 2)
4668 if (!isUndefOrEqual(Mask[i], i) ||
4669 !isUndefOrEqual(Mask[i+1], i))
4675 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4676 /// specifies a shuffle of elements that is suitable for input to 256-bit
4677 /// version of MOVDDUP.
4678 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4679 if (!HasFp256 || !VT.is256BitVector())
4682 unsigned NumElts = VT.getVectorNumElements();
4686 for (unsigned i = 0; i != NumElts/2; ++i)
4687 if (!isUndefOrEqual(Mask[i], 0))
4689 for (unsigned i = NumElts/2; i != NumElts; ++i)
4690 if (!isUndefOrEqual(Mask[i], NumElts/2))
4695 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4696 /// specifies a shuffle of elements that is suitable for input to 128-bit
4697 /// version of MOVDDUP.
4698 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4699 if (!VT.is128BitVector())
4702 unsigned e = VT.getVectorNumElements() / 2;
4703 for (unsigned i = 0; i != e; ++i)
4704 if (!isUndefOrEqual(Mask[i], i))
4706 for (unsigned i = 0; i != e; ++i)
4707 if (!isUndefOrEqual(Mask[e+i], i))
4712 /// isVEXTRACTIndex - Return true if the specified
4713 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4714 /// suitable for instruction that extract 128 or 256 bit vectors
4715 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4716 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4717 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4720 // The index should be aligned on a vecWidth-bit boundary.
4722 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4724 MVT VT = N->getSimpleValueType(0);
4725 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4726 bool Result = (Index * ElSize) % vecWidth == 0;
4731 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4732 /// operand specifies a subvector insert that is suitable for input to
4733 /// insertion of 128 or 256-bit subvectors
4734 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4735 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4736 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4738 // The index should be aligned on a vecWidth-bit boundary.
4740 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4742 MVT VT = N->getSimpleValueType(0);
4743 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4744 bool Result = (Index * ElSize) % vecWidth == 0;
4749 bool X86::isVINSERT128Index(SDNode *N) {
4750 return isVINSERTIndex(N, 128);
4753 bool X86::isVINSERT256Index(SDNode *N) {
4754 return isVINSERTIndex(N, 256);
4757 bool X86::isVEXTRACT128Index(SDNode *N) {
4758 return isVEXTRACTIndex(N, 128);
4761 bool X86::isVEXTRACT256Index(SDNode *N) {
4762 return isVEXTRACTIndex(N, 256);
4765 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4766 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4767 /// Handles 128-bit and 256-bit.
4768 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4769 MVT VT = N->getSimpleValueType(0);
4771 assert((VT.getSizeInBits() >= 128) &&
4772 "Unsupported vector type for PSHUF/SHUFP");
4774 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4775 // independently on 128-bit lanes.
4776 unsigned NumElts = VT.getVectorNumElements();
4777 unsigned NumLanes = VT.getSizeInBits()/128;
4778 unsigned NumLaneElts = NumElts/NumLanes;
4780 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4781 "Only supports 2, 4 or 8 elements per lane");
4783 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4785 for (unsigned i = 0; i != NumElts; ++i) {
4786 int Elt = N->getMaskElt(i);
4787 if (Elt < 0) continue;
4788 Elt &= NumLaneElts - 1;
4789 unsigned ShAmt = (i << Shift) % 8;
4790 Mask |= Elt << ShAmt;
4796 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4797 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4798 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4799 MVT VT = N->getSimpleValueType(0);
4801 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4802 "Unsupported vector type for PSHUFHW");
4804 unsigned NumElts = VT.getVectorNumElements();
4807 for (unsigned l = 0; l != NumElts; l += 8) {
4808 // 8 nodes per lane, but we only care about the last 4.
4809 for (unsigned i = 0; i < 4; ++i) {
4810 int Elt = N->getMaskElt(l+i+4);
4811 if (Elt < 0) continue;
4812 Elt &= 0x3; // only 2-bits.
4813 Mask |= Elt << (i * 2);
4820 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4821 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4822 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4823 MVT VT = N->getSimpleValueType(0);
4825 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4826 "Unsupported vector type for PSHUFHW");
4828 unsigned NumElts = VT.getVectorNumElements();
4831 for (unsigned l = 0; l != NumElts; l += 8) {
4832 // 8 nodes per lane, but we only care about the first 4.
4833 for (unsigned i = 0; i < 4; ++i) {
4834 int Elt = N->getMaskElt(l+i);
4835 if (Elt < 0) continue;
4836 Elt &= 0x3; // only 2-bits
4837 Mask |= Elt << (i * 2);
4844 /// \brief Return the appropriate immediate to shuffle the specified
4845 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4846 /// VALIGN (if Interlane is true) instructions.
4847 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4849 MVT VT = SVOp->getSimpleValueType(0);
4850 unsigned EltSize = InterLane ? 1 :
4851 VT.getVectorElementType().getSizeInBits() >> 3;
4853 unsigned NumElts = VT.getVectorNumElements();
4854 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4855 unsigned NumLaneElts = NumElts/NumLanes;
4859 for (i = 0; i != NumElts; ++i) {
4860 Val = SVOp->getMaskElt(i);
4864 if (Val >= (int)NumElts)
4865 Val -= NumElts - NumLaneElts;
4867 assert(Val - i > 0 && "PALIGNR imm should be positive");
4868 return (Val - i) * EltSize;
4871 /// \brief Return the appropriate immediate to shuffle the specified
4872 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4873 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4874 return getShuffleAlignrImmediate(SVOp, false);
4877 /// \brief Return the appropriate immediate to shuffle the specified
4878 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4879 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4880 return getShuffleAlignrImmediate(SVOp, true);
4884 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4887 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4890 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4892 MVT VecVT = N->getOperand(0).getSimpleValueType();
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4900 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4901 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4902 llvm_unreachable("Illegal insert subvector for VINSERT");
4905 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4907 MVT VecVT = N->getSimpleValueType(0);
4908 MVT ElVT = VecVT.getVectorElementType();
4910 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4911 return Index / NumElemsPerChunk;
4914 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4915 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4918 return getExtractVEXTRACTImmediate(N, 128);
4921 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4922 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4925 return getExtractVEXTRACTImmediate(N, 256);
4928 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4929 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4930 /// and VINSERTI128 instructions.
4931 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4932 return getInsertVINSERTImmediate(N, 128);
4935 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4936 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4937 /// and VINSERTI64x4 instructions.
4938 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4939 return getInsertVINSERTImmediate(N, 256);
4942 /// isZero - Returns true if Elt is a constant integer zero
4943 static bool isZero(SDValue V) {
4944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4945 return C && C->isNullValue();
4948 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4950 bool X86::isZeroNode(SDValue Elt) {
4953 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4954 return CFP->getValueAPF().isPosZero();
4958 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4959 /// match movhlps. The lower half elements should come from upper half of
4960 /// V1 (and in order), and the upper half elements should come from the upper
4961 /// half of V2 (and in order).
4962 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4963 if (!VT.is128BitVector())
4965 if (VT.getVectorNumElements() != 4)
4967 for (unsigned i = 0, e = 2; i != e; ++i)
4968 if (!isUndefOrEqual(Mask[i], i+2))
4970 for (unsigned i = 2; i != 4; ++i)
4971 if (!isUndefOrEqual(Mask[i], i+4))
4976 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4977 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4979 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4980 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4982 N = N->getOperand(0).getNode();
4983 if (!ISD::isNON_EXTLoad(N))
4986 *LD = cast<LoadSDNode>(N);
4990 // Test whether the given value is a vector value which will be legalized
4992 static bool WillBeConstantPoolLoad(SDNode *N) {
4993 if (N->getOpcode() != ISD::BUILD_VECTOR)
4996 // Check for any non-constant elements.
4997 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4998 switch (N->getOperand(i).getNode()->getOpcode()) {
5000 case ISD::ConstantFP:
5007 // Vectors of all-zeros and all-ones are materialized with special
5008 // instructions rather than being loaded.
5009 return !ISD::isBuildVectorAllZeros(N) &&
5010 !ISD::isBuildVectorAllOnes(N);
5013 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5014 /// match movlp{s|d}. The lower half elements should come from lower half of
5015 /// V1 (and in order), and the upper half elements should come from the upper
5016 /// half of V2 (and in order). And since V1 will become the source of the
5017 /// MOVLP, it must be either a vector load or a scalar load to vector.
5018 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5019 ArrayRef<int> Mask, MVT VT) {
5020 if (!VT.is128BitVector())
5023 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5025 // Is V2 is a vector load, don't do this transformation. We will try to use
5026 // load folding shufps op.
5027 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5030 unsigned NumElems = VT.getVectorNumElements();
5032 if (NumElems != 2 && NumElems != 4)
5034 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5035 if (!isUndefOrEqual(Mask[i], i))
5037 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i+NumElems))
5043 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5044 /// to an zero vector.
5045 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5046 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5047 SDValue V1 = N->getOperand(0);
5048 SDValue V2 = N->getOperand(1);
5049 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5050 for (unsigned i = 0; i != NumElems; ++i) {
5051 int Idx = N->getMaskElt(i);
5052 if (Idx >= (int)NumElems) {
5053 unsigned Opc = V2.getOpcode();
5054 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5056 if (Opc != ISD::BUILD_VECTOR ||
5057 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5059 } else if (Idx >= 0) {
5060 unsigned Opc = V1.getOpcode();
5061 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5063 if (Opc != ISD::BUILD_VECTOR ||
5064 !X86::isZeroNode(V1.getOperand(Idx)))
5071 /// getZeroVector - Returns a vector of specified type with all zero elements.
5073 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5074 SelectionDAG &DAG, SDLoc dl) {
5075 assert(VT.isVector() && "Expected a vector type");
5077 // Always build SSE zero vectors as <4 x i32> bitcasted
5078 // to their dest type. This ensures they get CSE'd.
5080 if (VT.is128BitVector()) { // SSE
5081 if (Subtarget->hasSSE2()) { // SSE2
5082 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5085 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5086 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5088 } else if (VT.is256BitVector()) { // AVX
5089 if (Subtarget->hasInt256()) { // AVX2
5090 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5091 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5092 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5094 // 256-bit logic and arithmetic instructions in AVX are all
5095 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5096 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5097 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5098 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5100 } else if (VT.is512BitVector()) { // AVX-512
5101 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5102 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5103 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5104 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5105 } else if (VT.getScalarType() == MVT::i1) {
5106 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5107 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5108 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5109 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5111 llvm_unreachable("Unexpected vector type");
5113 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5116 /// getOnesVector - Returns a vector of specified type with all bits set.
5117 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5118 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5119 /// Then bitcast to their original type, ensuring they get CSE'd.
5120 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5122 assert(VT.isVector() && "Expected a vector type");
5124 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5126 if (VT.is256BitVector()) {
5127 if (HasInt256) { // AVX2
5128 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5131 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5132 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5134 } else if (VT.is128BitVector()) {
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5137 llvm_unreachable("Unexpected vector type");
5139 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5142 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5143 /// that point to V2 points to its first element.
5144 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5145 for (unsigned i = 0; i != NumElems; ++i) {
5146 if (Mask[i] > (int)NumElems) {
5152 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5153 /// operation of specified width.
5154 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5156 unsigned NumElems = VT.getVectorNumElements();
5157 SmallVector<int, 8> Mask;
5158 Mask.push_back(NumElems);
5159 for (unsigned i = 1; i != NumElems; ++i)
5161 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5164 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5165 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5167 unsigned NumElems = VT.getVectorNumElements();
5168 SmallVector<int, 8> Mask;
5169 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5171 Mask.push_back(i + NumElems);
5173 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5176 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5177 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5179 unsigned NumElems = VT.getVectorNumElements();
5180 SmallVector<int, 8> Mask;
5181 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5182 Mask.push_back(i + Half);
5183 Mask.push_back(i + NumElems + Half);
5185 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5188 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5189 // a generic shuffle instruction because the target has no such instructions.
5190 // Generate shuffles which repeat i16 and i8 several times until they can be
5191 // represented by v4f32 and then be manipulated by target suported shuffles.
5192 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5193 MVT VT = V.getSimpleValueType();
5194 int NumElems = VT.getVectorNumElements();
5197 while (NumElems > 4) {
5198 if (EltNo < NumElems/2) {
5199 V = getUnpackl(DAG, dl, VT, V, V);
5201 V = getUnpackh(DAG, dl, VT, V, V);
5202 EltNo -= NumElems/2;
5209 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5210 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5211 MVT VT = V.getSimpleValueType();
5214 if (VT.is128BitVector()) {
5215 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5216 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5217 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5219 } else if (VT.is256BitVector()) {
5220 // To use VPERMILPS to splat scalars, the second half of indicies must
5221 // refer to the higher part, which is a duplication of the lower one,
5222 // because VPERMILPS can only handle in-lane permutations.
5223 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5224 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5226 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5227 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5230 llvm_unreachable("Vector size not supported");
5232 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5235 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5236 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5237 MVT SrcVT = SV->getSimpleValueType(0);
5238 SDValue V1 = SV->getOperand(0);
5241 int EltNo = SV->getSplatIndex();
5242 int NumElems = SrcVT.getVectorNumElements();
5243 bool Is256BitVec = SrcVT.is256BitVector();
5245 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5246 "Unknown how to promote splat for type");
5248 // Extract the 128-bit part containing the splat element and update
5249 // the splat element index when it refers to the higher register.
5251 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5252 if (EltNo >= NumElems/2)
5253 EltNo -= NumElems/2;
5256 // All i16 and i8 vector types can't be used directly by a generic shuffle
5257 // instruction because the target has no such instruction. Generate shuffles
5258 // which repeat i16 and i8 several times until they fit in i32, and then can
5259 // be manipulated by target suported shuffles.
5260 MVT EltVT = SrcVT.getVectorElementType();
5261 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5262 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5264 // Recreate the 256-bit vector and place the same 128-bit vector
5265 // into the low and high part. This is necessary because we want
5266 // to use VPERM* to shuffle the vectors
5268 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5271 return getLegalSplat(DAG, V1, EltNo);
5274 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5275 /// vector of zero or undef vector. This produces a shuffle where the low
5276 /// element of V2 is swizzled into the zero/undef vector, landing at element
5277 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5278 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5280 const X86Subtarget *Subtarget,
5281 SelectionDAG &DAG) {
5282 MVT VT = V2.getSimpleValueType();
5284 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5285 unsigned NumElems = VT.getVectorNumElements();
5286 SmallVector<int, 16> MaskVec;
5287 for (unsigned i = 0; i != NumElems; ++i)
5288 // If this is the insertion idx, put the low elt of V2 here.
5289 MaskVec.push_back(i == Idx ? NumElems : i);
5290 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5293 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5294 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5295 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5296 /// shuffles which use a single input multiple times, and in those cases it will
5297 /// adjust the mask to only have indices within that single input.
5298 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5299 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5300 unsigned NumElems = VT.getVectorNumElements();
5304 bool IsFakeUnary = false;
5305 switch(N->getOpcode()) {
5307 ImmN = N->getOperand(N->getNumOperands()-1);
5308 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5311 case X86ISD::UNPCKH:
5312 DecodeUNPCKHMask(VT, Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::UNPCKL:
5316 DecodeUNPCKLMask(VT, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::MOVHLPS:
5320 DecodeMOVHLPSMask(NumElems, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::MOVLHPS:
5324 DecodeMOVLHPSMask(NumElems, Mask);
5325 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5327 case X86ISD::PALIGNR:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5331 case X86ISD::PSHUFD:
5332 case X86ISD::VPERMILP:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFHW:
5338 ImmN = N->getOperand(N->getNumOperands()-1);
5339 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5342 case X86ISD::PSHUFLW:
5343 ImmN = N->getOperand(N->getNumOperands()-1);
5344 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5347 case X86ISD::PSHUFB: {
5349 SDValue MaskNode = N->getOperand(1);
5350 while (MaskNode->getOpcode() == ISD::BITCAST)
5351 MaskNode = MaskNode->getOperand(0);
5353 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5354 // If we have a build-vector, then things are easy.
5355 EVT VT = MaskNode.getValueType();
5356 assert(VT.isVector() &&
5357 "Can't produce a non-vector with a build_vector!");
5358 if (!VT.isInteger())
5361 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5363 SmallVector<uint64_t, 32> RawMask;
5364 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5365 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5368 APInt MaskElement = CN->getAPIntValue();
5370 // We now have to decode the element which could be any integer size and
5371 // extract each byte of it.
5372 for (int j = 0; j < NumBytesPerElement; ++j) {
5373 // Note that this is x86 and so always little endian: the low byte is
5374 // the first byte of the mask.
5375 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5376 MaskElement = MaskElement.lshr(8);
5379 DecodePSHUFBMask(RawMask, Mask);
5383 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5387 SDValue Ptr = MaskLoad->getBasePtr();
5388 if (Ptr->getOpcode() == X86ISD::Wrapper)
5389 Ptr = Ptr->getOperand(0);
5391 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5392 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5395 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5396 // FIXME: Support AVX-512 here.
5397 if (!C->getType()->isVectorTy() ||
5398 (C->getNumElements() != 16 && C->getNumElements() != 32))
5401 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5402 DecodePSHUFBMask(C, Mask);
5408 case X86ISD::VPERMI:
5409 ImmN = N->getOperand(N->getNumOperands()-1);
5410 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5414 case X86ISD::MOVSD: {
5415 // The index 0 always comes from the first element of the second source,
5416 // this is why MOVSS and MOVSD are used in the first place. The other
5417 // elements come from the other positions of the first source vector
5418 Mask.push_back(NumElems);
5419 for (unsigned i = 1; i != NumElems; ++i) {
5424 case X86ISD::VPERM2X128:
5425 ImmN = N->getOperand(N->getNumOperands()-1);
5426 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5427 if (Mask.empty()) return false;
5429 case X86ISD::MOVDDUP:
5430 case X86ISD::MOVLHPD:
5431 case X86ISD::MOVLPD:
5432 case X86ISD::MOVLPS:
5433 case X86ISD::MOVSHDUP:
5434 case X86ISD::MOVSLDUP:
5435 // Not yet implemented
5437 default: llvm_unreachable("unknown target shuffle node");
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5445 if (M >= (int)Mask.size())
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5485 int Elt = ShuffleMask[Index];
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5530 if (X86::isZeroNode(Elt))
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5557 if (Idx < (int)NumElems)
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5567 OpNum = SeenV1 ? 0 : 1;
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5588 // V1 = {X, A, B, C} 0
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5602 ShVal = SVOp->getOperand(OpSrc);
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5623 // 0 { A, B, X, X } = V2
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5637 ShVal = SVOp->getOperand(OpSrc);
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5676 V = DAG.getUNDEF(MVT::v8i16);
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5725 V = DAG.getUNDEF(MVT::v8i16);
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5784 else if (IncorrectIdx == -1U) {
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5810 /// getVShift - Return a vector logical shift node.
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5874 if ((Offset % RequiredAlign) & 3)
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5933 if (Elt.getOpcode() == ISD::UNDEF)
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 if (!Subtarget->hasFp256())
6013 MVT VT = Op.getSimpleValueType();
6016 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6017 "Unsupported vector type for broadcast.");
6022 switch (Op.getOpcode()) {
6024 // Unknown pattern found.
6027 case ISD::BUILD_VECTOR: {
6028 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6029 BitVector UndefElements;
6030 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6032 // We need a splat of a single value to use broadcast, and it doesn't
6033 // make any sense if the value is only in one element of the vector.
6034 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6038 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6039 Ld.getOpcode() == ISD::ConstantFP);
6041 // Make sure that all of the users of a non-constant load are from the
6042 // BUILD_VECTOR node.
6043 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6048 case ISD::VECTOR_SHUFFLE: {
6049 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6051 // Shuffles must have a splat mask where the first element is
6053 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6056 SDValue Sc = Op.getOperand(0);
6057 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6058 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6060 if (!Subtarget->hasInt256())
6063 // Use the register form of the broadcast instruction available on AVX2.
6064 if (VT.getSizeInBits() >= 256)
6065 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6066 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6069 Ld = Sc.getOperand(0);
6070 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6071 Ld.getOpcode() == ISD::ConstantFP);
6073 // The scalar_to_vector node and the suspected
6074 // load node must have exactly one user.
6075 // Constants may have multiple users.
6077 // AVX-512 has register version of the broadcast
6078 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6079 Ld.getValueType().getSizeInBits() >= 32;
6080 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6087 bool IsGE256 = (VT.getSizeInBits() >= 256);
6089 // Handle the broadcasting a single constant scalar from the constant pool
6090 // into a vector. On Sandybridge it is still better to load a constant vector
6091 // from the constant pool and not to broadcast it from a scalar.
6092 if (ConstSplatVal && Subtarget->hasInt256()) {
6093 EVT CVT = Ld.getValueType();
6094 assert(!CVT.isVector() && "Must not broadcast a vector type");
6095 unsigned ScalarSize = CVT.getSizeInBits();
6097 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
6098 const Constant *C = nullptr;
6099 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6100 C = CI->getConstantIntValue();
6101 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6102 C = CF->getConstantFPValue();
6104 assert(C && "Invalid constant type");
6106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6107 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6108 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6109 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6110 MachinePointerInfo::getConstantPool(),
6111 false, false, false, Alignment);
6113 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6117 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6118 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6120 // Handle AVX2 in-register broadcasts.
6121 if (!IsLoad && Subtarget->hasInt256() &&
6122 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6123 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6125 // The scalar source must be a normal load.
6129 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6130 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6132 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6133 // double since there is no vbroadcastsd xmm
6134 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6135 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6136 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6139 // Unsupported broadcast.
6143 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6144 /// underlying vector and index.
6146 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6148 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6150 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6151 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6154 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6156 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6158 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6159 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6162 // In this case the vector is the extract_subvector expression and the index
6163 // is 2, as specified by the shuffle.
6164 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6165 SDValue ShuffleVec = SVOp->getOperand(0);
6166 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6167 assert(ShuffleVecVT.getVectorElementType() ==
6168 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6170 int ShuffleIdx = SVOp->getMaskElt(Idx);
6171 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6172 ExtractedFromVec = ShuffleVec;
6178 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6179 MVT VT = Op.getSimpleValueType();
6181 // Skip if insert_vec_elt is not supported.
6182 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6183 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6187 unsigned NumElems = Op.getNumOperands();
6191 SmallVector<unsigned, 4> InsertIndices;
6192 SmallVector<int, 8> Mask(NumElems, -1);
6194 for (unsigned i = 0; i != NumElems; ++i) {
6195 unsigned Opc = Op.getOperand(i).getOpcode();
6197 if (Opc == ISD::UNDEF)
6200 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6201 // Quit if more than 1 elements need inserting.
6202 if (InsertIndices.size() > 1)
6205 InsertIndices.push_back(i);
6209 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6210 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6211 // Quit if non-constant index.
6212 if (!isa<ConstantSDNode>(ExtIdx))
6214 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6216 // Quit if extracted from vector of different type.
6217 if (ExtractedFromVec.getValueType() != VT)
6220 if (!VecIn1.getNode())
6221 VecIn1 = ExtractedFromVec;
6222 else if (VecIn1 != ExtractedFromVec) {
6223 if (!VecIn2.getNode())
6224 VecIn2 = ExtractedFromVec;
6225 else if (VecIn2 != ExtractedFromVec)
6226 // Quit if more than 2 vectors to shuffle
6230 if (ExtractedFromVec == VecIn1)
6232 else if (ExtractedFromVec == VecIn2)
6233 Mask[i] = Idx + NumElems;
6236 if (!VecIn1.getNode())
6239 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6240 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6241 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6242 unsigned Idx = InsertIndices[i];
6243 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6244 DAG.getIntPtrConstant(Idx));
6250 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6252 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6254 MVT VT = Op.getSimpleValueType();
6255 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6256 "Unexpected type in LowerBUILD_VECTORvXi1!");
6259 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6260 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6261 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6262 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6265 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6266 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6267 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6268 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6271 bool AllContants = true;
6272 uint64_t Immediate = 0;
6273 int NonConstIdx = -1;
6274 bool IsSplat = true;
6275 unsigned NumNonConsts = 0;
6276 unsigned NumConsts = 0;
6277 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6278 SDValue In = Op.getOperand(idx);
6279 if (In.getOpcode() == ISD::UNDEF)
6281 if (!isa<ConstantSDNode>(In)) {
6282 AllContants = false;
6288 if (cast<ConstantSDNode>(In)->getZExtValue())
6289 Immediate |= (1ULL << idx);
6291 if (In != Op.getOperand(0))
6296 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6297 DAG.getConstant(Immediate, MVT::i16));
6298 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6299 DAG.getIntPtrConstant(0));
6302 if (NumNonConsts == 1 && NonConstIdx != 0) {
6305 SDValue VecAsImm = DAG.getConstant(Immediate,
6306 MVT::getIntegerVT(VT.getSizeInBits()));
6307 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6310 DstVec = DAG.getUNDEF(VT);
6311 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6312 Op.getOperand(NonConstIdx),
6313 DAG.getIntPtrConstant(NonConstIdx));
6315 if (!IsSplat && (NonConstIdx != 0))
6316 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6317 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6320 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6321 DAG.getConstant(-1, SelectVT),
6322 DAG.getConstant(0, SelectVT));
6324 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6325 DAG.getConstant((Immediate | 1), SelectVT),
6326 DAG.getConstant(Immediate, SelectVT));
6327 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6330 /// \brief Return true if \p N implements a horizontal binop and return the
6331 /// operands for the horizontal binop into V0 and V1.
6333 /// This is a helper function of PerformBUILD_VECTORCombine.
6334 /// This function checks that the build_vector \p N in input implements a
6335 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6336 /// operation to match.
6337 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6338 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6339 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6342 /// This function only analyzes elements of \p N whose indices are
6343 /// in range [BaseIdx, LastIdx).
6344 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6346 unsigned BaseIdx, unsigned LastIdx,
6347 SDValue &V0, SDValue &V1) {
6348 EVT VT = N->getValueType(0);
6350 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6351 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6352 "Invalid Vector in input!");
6354 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6355 bool CanFold = true;
6356 unsigned ExpectedVExtractIdx = BaseIdx;
6357 unsigned NumElts = LastIdx - BaseIdx;
6358 V0 = DAG.getUNDEF(VT);
6359 V1 = DAG.getUNDEF(VT);
6361 // Check if N implements a horizontal binop.
6362 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6363 SDValue Op = N->getOperand(i + BaseIdx);
6366 if (Op->getOpcode() == ISD::UNDEF) {
6367 // Update the expected vector extract index.
6368 if (i * 2 == NumElts)
6369 ExpectedVExtractIdx = BaseIdx;
6370 ExpectedVExtractIdx += 2;
6374 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6379 SDValue Op0 = Op.getOperand(0);
6380 SDValue Op1 = Op.getOperand(1);
6382 // Try to match the following pattern:
6383 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6384 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6385 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6386 Op0.getOperand(0) == Op1.getOperand(0) &&
6387 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6388 isa<ConstantSDNode>(Op1.getOperand(1)));
6392 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6393 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6395 if (i * 2 < NumElts) {
6396 if (V0.getOpcode() == ISD::UNDEF)
6397 V0 = Op0.getOperand(0);
6399 if (V1.getOpcode() == ISD::UNDEF)
6400 V1 = Op0.getOperand(0);
6401 if (i * 2 == NumElts)
6402 ExpectedVExtractIdx = BaseIdx;
6405 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6406 if (I0 == ExpectedVExtractIdx)
6407 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6408 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6409 // Try to match the following dag sequence:
6410 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6411 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6415 ExpectedVExtractIdx += 2;
6421 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6422 /// a concat_vector.
6424 /// This is a helper function of PerformBUILD_VECTORCombine.
6425 /// This function expects two 256-bit vectors called V0 and V1.
6426 /// At first, each vector is split into two separate 128-bit vectors.
6427 /// Then, the resulting 128-bit vectors are used to implement two
6428 /// horizontal binary operations.
6430 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6432 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6433 /// the two new horizontal binop.
6434 /// When Mode is set, the first horizontal binop dag node would take as input
6435 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6436 /// horizontal binop dag node would take as input the lower 128-bit of V1
6437 /// and the upper 128-bit of V1.
6439 /// HADD V0_LO, V0_HI
6440 /// HADD V1_LO, V1_HI
6442 /// Otherwise, the first horizontal binop dag node takes as input the lower
6443 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6444 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6446 /// HADD V0_LO, V1_LO
6447 /// HADD V0_HI, V1_HI
6449 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6450 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6451 /// the upper 128-bits of the result.
6452 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6453 SDLoc DL, SelectionDAG &DAG,
6454 unsigned X86Opcode, bool Mode,
6455 bool isUndefLO, bool isUndefHI) {
6456 EVT VT = V0.getValueType();
6457 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6458 "Invalid nodes in input!");
6460 unsigned NumElts = VT.getVectorNumElements();
6461 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6462 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6463 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6464 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6465 EVT NewVT = V0_LO.getValueType();
6467 SDValue LO = DAG.getUNDEF(NewVT);
6468 SDValue HI = DAG.getUNDEF(NewVT);
6471 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6472 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6473 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6474 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6475 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6477 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6478 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6479 V1_LO->getOpcode() != ISD::UNDEF))
6480 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6482 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6483 V1_HI->getOpcode() != ISD::UNDEF))
6484 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6487 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6490 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6491 /// sequence of 'vadd + vsub + blendi'.
6492 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6493 const X86Subtarget *Subtarget) {
6495 EVT VT = BV->getValueType(0);
6496 unsigned NumElts = VT.getVectorNumElements();
6497 SDValue InVec0 = DAG.getUNDEF(VT);
6498 SDValue InVec1 = DAG.getUNDEF(VT);
6500 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6501 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6503 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6504 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6505 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6508 // Odd-numbered elements in the input build vector are obtained from
6509 // adding two integer/float elements.
6510 // Even-numbered elements in the input build vector are obtained from
6511 // subtracting two integer/float elements.
6512 unsigned ExpectedOpcode = ISD::FSUB;
6513 unsigned NextExpectedOpcode = ISD::FADD;
6514 bool AddFound = false;
6515 bool SubFound = false;
6517 for (unsigned i = 0, e = NumElts; i != e; i++) {
6518 SDValue Op = BV->getOperand(i);
6520 // Skip 'undef' values.
6521 unsigned Opcode = Op.getOpcode();
6522 if (Opcode == ISD::UNDEF) {
6523 std::swap(ExpectedOpcode, NextExpectedOpcode);
6527 // Early exit if we found an unexpected opcode.
6528 if (Opcode != ExpectedOpcode)
6531 SDValue Op0 = Op.getOperand(0);
6532 SDValue Op1 = Op.getOperand(1);
6534 // Try to match the following pattern:
6535 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6536 // Early exit if we cannot match that sequence.
6537 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6538 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6539 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6540 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6541 Op0.getOperand(1) != Op1.getOperand(1))
6544 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6548 // We found a valid add/sub node. Update the information accordingly.
6554 // Update InVec0 and InVec1.
6555 if (InVec0.getOpcode() == ISD::UNDEF)
6556 InVec0 = Op0.getOperand(0);
6557 if (InVec1.getOpcode() == ISD::UNDEF)
6558 InVec1 = Op1.getOperand(0);
6560 // Make sure that operands in input to each add/sub node always
6561 // come from a same pair of vectors.
6562 if (InVec0 != Op0.getOperand(0)) {
6563 if (ExpectedOpcode == ISD::FSUB)
6566 // FADD is commutable. Try to commute the operands
6567 // and then test again.
6568 std::swap(Op0, Op1);
6569 if (InVec0 != Op0.getOperand(0))
6573 if (InVec1 != Op1.getOperand(0))
6576 // Update the pair of expected opcodes.
6577 std::swap(ExpectedOpcode, NextExpectedOpcode);
6580 // Don't try to fold this build_vector into a VSELECT if it has
6581 // too many UNDEF operands.
6582 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6583 InVec1.getOpcode() != ISD::UNDEF) {
6584 // Emit a sequence of vector add and sub followed by a VSELECT.
6585 // The new VSELECT will be lowered into a BLENDI.
6586 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6587 // and emit a single ADDSUB instruction.
6588 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6589 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6591 // Construct the VSELECT mask.
6592 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6593 EVT SVT = MaskVT.getVectorElementType();
6594 unsigned SVTBits = SVT.getSizeInBits();
6595 SmallVector<SDValue, 8> Ops;
6597 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6598 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6599 APInt::getAllOnesValue(SVTBits);
6600 SDValue Constant = DAG.getConstant(Value, SVT);
6601 Ops.push_back(Constant);
6604 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6605 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6611 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6612 const X86Subtarget *Subtarget) {
6614 EVT VT = N->getValueType(0);
6615 unsigned NumElts = VT.getVectorNumElements();
6616 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6617 SDValue InVec0, InVec1;
6619 // Try to match an ADDSUB.
6620 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6621 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6622 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6623 if (Value.getNode())
6627 // Try to match horizontal ADD/SUB.
6628 unsigned NumUndefsLO = 0;
6629 unsigned NumUndefsHI = 0;
6630 unsigned Half = NumElts/2;
6632 // Count the number of UNDEF operands in the build_vector in input.
6633 for (unsigned i = 0, e = Half; i != e; ++i)
6634 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6637 for (unsigned i = Half, e = NumElts; i != e; ++i)
6638 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6641 // Early exit if this is either a build_vector of all UNDEFs or all the
6642 // operands but one are UNDEF.
6643 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6646 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6647 // Try to match an SSE3 float HADD/HSUB.
6648 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6651 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6652 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6653 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6654 // Try to match an SSSE3 integer HADD/HSUB.
6655 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6656 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6658 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6659 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6662 if (!Subtarget->hasAVX())
6665 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6666 // Try to match an AVX horizontal add/sub of packed single/double
6667 // precision floating point values from 256-bit vectors.
6668 SDValue InVec2, InVec3;
6669 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6670 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6671 ((InVec0.getOpcode() == ISD::UNDEF ||
6672 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6673 ((InVec1.getOpcode() == ISD::UNDEF ||
6674 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6675 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6677 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6678 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6679 ((InVec0.getOpcode() == ISD::UNDEF ||
6680 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6681 ((InVec1.getOpcode() == ISD::UNDEF ||
6682 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6683 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6684 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6685 // Try to match an AVX2 horizontal add/sub of signed integers.
6686 SDValue InVec2, InVec3;
6688 bool CanFold = true;
6690 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6691 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6692 ((InVec0.getOpcode() == ISD::UNDEF ||
6693 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6694 ((InVec1.getOpcode() == ISD::UNDEF ||
6695 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6696 X86Opcode = X86ISD::HADD;
6697 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6698 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6699 ((InVec0.getOpcode() == ISD::UNDEF ||
6700 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6701 ((InVec1.getOpcode() == ISD::UNDEF ||
6702 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6703 X86Opcode = X86ISD::HSUB;
6708 // Fold this build_vector into a single horizontal add/sub.
6709 // Do this only if the target has AVX2.
6710 if (Subtarget->hasAVX2())
6711 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6713 // Do not try to expand this build_vector into a pair of horizontal
6714 // add/sub if we can emit a pair of scalar add/sub.
6715 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6718 // Convert this build_vector into a pair of horizontal binop followed by
6720 bool isUndefLO = NumUndefsLO == Half;
6721 bool isUndefHI = NumUndefsHI == Half;
6722 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6723 isUndefLO, isUndefHI);
6727 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6728 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6730 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6731 X86Opcode = X86ISD::HADD;
6732 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6733 X86Opcode = X86ISD::HSUB;
6734 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6735 X86Opcode = X86ISD::FHADD;
6736 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6737 X86Opcode = X86ISD::FHSUB;
6741 // Don't try to expand this build_vector into a pair of horizontal add/sub
6742 // if we can simply emit a pair of scalar add/sub.
6743 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6746 // Convert this build_vector into two horizontal add/sub followed by
6748 bool isUndefLO = NumUndefsLO == Half;
6749 bool isUndefHI = NumUndefsHI == Half;
6750 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6751 isUndefLO, isUndefHI);
6758 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6761 MVT VT = Op.getSimpleValueType();
6762 MVT ExtVT = VT.getVectorElementType();
6763 unsigned NumElems = Op.getNumOperands();
6765 // Generate vectors for predicate vectors.
6766 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6767 return LowerBUILD_VECTORvXi1(Op, DAG);
6769 // Vectors containing all zeros can be matched by pxor and xorps later
6770 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6771 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6772 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6773 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6776 return getZeroVector(VT, Subtarget, DAG, dl);
6779 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6780 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6781 // vpcmpeqd on 256-bit vectors.
6782 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6783 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6786 if (!VT.is512BitVector())
6787 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6790 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6791 if (Broadcast.getNode())
6794 unsigned EVTBits = ExtVT.getSizeInBits();
6796 unsigned NumZero = 0;
6797 unsigned NumNonZero = 0;
6798 unsigned NonZeros = 0;
6799 bool IsAllConstants = true;
6800 SmallSet<SDValue, 8> Values;
6801 for (unsigned i = 0; i < NumElems; ++i) {
6802 SDValue Elt = Op.getOperand(i);
6803 if (Elt.getOpcode() == ISD::UNDEF)
6806 if (Elt.getOpcode() != ISD::Constant &&
6807 Elt.getOpcode() != ISD::ConstantFP)
6808 IsAllConstants = false;
6809 if (X86::isZeroNode(Elt))
6812 NonZeros |= (1 << i);
6817 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6818 if (NumNonZero == 0)
6819 return DAG.getUNDEF(VT);
6821 // Special case for single non-zero, non-undef, element.
6822 if (NumNonZero == 1) {
6823 unsigned Idx = countTrailingZeros(NonZeros);
6824 SDValue Item = Op.getOperand(Idx);
6826 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6827 // the value are obviously zero, truncate the value to i32 and do the
6828 // insertion that way. Only do this if the value is non-constant or if the
6829 // value is a constant being inserted into element 0. It is cheaper to do
6830 // a constant pool load than it is to do a movd + shuffle.
6831 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6832 (!IsAllConstants || Idx == 0)) {
6833 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6835 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6836 EVT VecVT = MVT::v4i32;
6837 unsigned VecElts = 4;
6839 // Truncate the value (which may itself be a constant) to i32, and
6840 // convert it to a vector with movd (S2V+shuffle to zero extend).
6841 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6842 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6844 // If using the new shuffle lowering, just directly insert this.
6845 if (ExperimentalVectorShuffleLowering)
6847 ISD::BITCAST, dl, VT,
6848 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6850 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6852 // Now we have our 32-bit value zero extended in the low element of
6853 // a vector. If Idx != 0, swizzle it into place.
6855 SmallVector<int, 4> Mask;
6856 Mask.push_back(Idx);
6857 for (unsigned i = 1; i != VecElts; ++i)
6859 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6862 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6866 // If we have a constant or non-constant insertion into the low element of
6867 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6868 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6869 // depending on what the source datatype is.
6872 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6875 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6876 if (VT.is256BitVector() || VT.is512BitVector()) {
6877 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6878 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6879 Item, DAG.getIntPtrConstant(0));
6881 assert(VT.is128BitVector() && "Expected an SSE value type!");
6882 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6883 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6884 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6888 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6889 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6890 if (VT.is256BitVector()) {
6891 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6892 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6894 assert(VT.is128BitVector() && "Expected an SSE value type!");
6895 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6897 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6901 // Is it a vector logical left shift?
6902 if (NumElems == 2 && Idx == 1 &&
6903 X86::isZeroNode(Op.getOperand(0)) &&
6904 !X86::isZeroNode(Op.getOperand(1))) {
6905 unsigned NumBits = VT.getSizeInBits();
6906 return getVShift(true, VT,
6907 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6908 VT, Op.getOperand(1)),
6909 NumBits/2, DAG, *this, dl);
6912 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6915 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6916 // is a non-constant being inserted into an element other than the low one,
6917 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6918 // movd/movss) to move this into the low element, then shuffle it into
6920 if (EVTBits == 32) {
6921 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6923 // If using the new shuffle lowering, just directly insert this.
6924 if (ExperimentalVectorShuffleLowering)
6925 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6927 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6928 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6929 SmallVector<int, 8> MaskVec;
6930 for (unsigned i = 0; i != NumElems; ++i)
6931 MaskVec.push_back(i == Idx ? 0 : 1);
6932 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6936 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6937 if (Values.size() == 1) {
6938 if (EVTBits == 32) {
6939 // Instead of a shuffle like this:
6940 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6941 // Check if it's possible to issue this instead.
6942 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6943 unsigned Idx = countTrailingZeros(NonZeros);
6944 SDValue Item = Op.getOperand(Idx);
6945 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6946 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6951 // A vector full of immediates; various special cases are already
6952 // handled, so this is best done with a single constant-pool load.
6956 // For AVX-length vectors, build the individual 128-bit pieces and use
6957 // shuffles to put them in place.
6958 if (VT.is256BitVector() || VT.is512BitVector()) {
6959 SmallVector<SDValue, 64> V;
6960 for (unsigned i = 0; i != NumElems; ++i)
6961 V.push_back(Op.getOperand(i));
6963 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6965 // Build both the lower and upper subvector.
6966 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6967 makeArrayRef(&V[0], NumElems/2));
6968 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6969 makeArrayRef(&V[NumElems / 2], NumElems/2));
6971 // Recreate the wider vector with the lower and upper part.
6972 if (VT.is256BitVector())
6973 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6974 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6977 // Let legalizer expand 2-wide build_vectors.
6978 if (EVTBits == 64) {
6979 if (NumNonZero == 1) {
6980 // One half is zero or undef.
6981 unsigned Idx = countTrailingZeros(NonZeros);
6982 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6983 Op.getOperand(Idx));
6984 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6989 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6990 if (EVTBits == 8 && NumElems == 16) {
6991 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6993 if (V.getNode()) return V;
6996 if (EVTBits == 16 && NumElems == 8) {
6997 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6999 if (V.getNode()) return V;
7002 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7003 if (EVTBits == 32 && NumElems == 4) {
7004 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
7005 NumZero, DAG, Subtarget, *this);
7010 // If element VT is == 32 bits, turn it into a number of shuffles.
7011 SmallVector<SDValue, 8> V(NumElems);
7012 if (NumElems == 4 && NumZero > 0) {
7013 for (unsigned i = 0; i < 4; ++i) {
7014 bool isZero = !(NonZeros & (1 << i));
7016 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7018 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7021 for (unsigned i = 0; i < 2; ++i) {
7022 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7025 V[i] = V[i*2]; // Must be a zero vector.
7028 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7031 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7034 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7039 bool Reverse1 = (NonZeros & 0x3) == 2;
7040 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7044 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7045 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7047 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7050 if (Values.size() > 1 && VT.is128BitVector()) {
7051 // Check for a build vector of consecutive loads.
7052 for (unsigned i = 0; i < NumElems; ++i)
7053 V[i] = Op.getOperand(i);
7055 // Check for elements which are consecutive loads.
7056 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7060 // Check for a build vector from mostly shuffle plus few inserting.
7061 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7065 // For SSE 4.1, use insertps to put the high elements into the low element.
7066 if (getSubtarget()->hasSSE41()) {
7068 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7069 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7071 Result = DAG.getUNDEF(VT);
7073 for (unsigned i = 1; i < NumElems; ++i) {
7074 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7075 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7076 Op.getOperand(i), DAG.getIntPtrConstant(i));
7081 // Otherwise, expand into a number of unpckl*, start by extending each of
7082 // our (non-undef) elements to the full vector width with the element in the
7083 // bottom slot of the vector (which generates no code for SSE).
7084 for (unsigned i = 0; i < NumElems; ++i) {
7085 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7086 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7088 V[i] = DAG.getUNDEF(VT);
7091 // Next, we iteratively mix elements, e.g. for v4f32:
7092 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7093 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7094 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7095 unsigned EltStride = NumElems >> 1;
7096 while (EltStride != 0) {
7097 for (unsigned i = 0; i < EltStride; ++i) {
7098 // If V[i+EltStride] is undef and this is the first round of mixing,
7099 // then it is safe to just drop this shuffle: V[i] is already in the
7100 // right place, the one element (since it's the first round) being
7101 // inserted as undef can be dropped. This isn't safe for successive
7102 // rounds because they will permute elements within both vectors.
7103 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7104 EltStride == NumElems/2)
7107 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7116 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7117 // to create 256-bit vectors from two other 128-bit ones.
7118 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7120 MVT ResVT = Op.getSimpleValueType();
7122 assert((ResVT.is256BitVector() ||
7123 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7125 SDValue V1 = Op.getOperand(0);
7126 SDValue V2 = Op.getOperand(1);
7127 unsigned NumElems = ResVT.getVectorNumElements();
7128 if(ResVT.is256BitVector())
7129 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7131 if (Op.getNumOperands() == 4) {
7132 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7133 ResVT.getVectorNumElements()/2);
7134 SDValue V3 = Op.getOperand(2);
7135 SDValue V4 = Op.getOperand(3);
7136 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7137 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7139 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7142 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7143 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7144 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7145 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7146 Op.getNumOperands() == 4)));
7148 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7149 // from two other 128-bit ones.
7151 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7152 return LowerAVXCONCAT_VECTORS(Op, DAG);
7156 //===----------------------------------------------------------------------===//
7157 // Vector shuffle lowering
7159 // This is an experimental code path for lowering vector shuffles on x86. It is
7160 // designed to handle arbitrary vector shuffles and blends, gracefully
7161 // degrading performance as necessary. It works hard to recognize idiomatic
7162 // shuffles and lower them to optimal instruction patterns without leaving
7163 // a framework that allows reasonably efficient handling of all vector shuffle
7165 //===----------------------------------------------------------------------===//
7167 /// \brief Tiny helper function to identify a no-op mask.
7169 /// This is a somewhat boring predicate function. It checks whether the mask
7170 /// array input, which is assumed to be a single-input shuffle mask of the kind
7171 /// used by the X86 shuffle instructions (not a fully general
7172 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7173 /// in-place shuffle are 'no-op's.
7174 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7175 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7176 if (Mask[i] != -1 && Mask[i] != i)
7181 /// \brief Helper function to classify a mask as a single-input mask.
7183 /// This isn't a generic single-input test because in the vector shuffle
7184 /// lowering we canonicalize single inputs to be the first input operand. This
7185 /// means we can more quickly test for a single input by only checking whether
7186 /// an input from the second operand exists. We also assume that the size of
7187 /// mask corresponds to the size of the input vectors which isn't true in the
7188 /// fully general case.
7189 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7191 if (M >= (int)Mask.size())
7196 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7197 // 2013 will allow us to use it as a non-type template parameter.
7200 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7202 /// See its documentation for details.
7203 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7204 if (Mask.size() != Args.size())
7206 for (int i = 0, e = Mask.size(); i < e; ++i) {
7207 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7208 assert(*Args[i] < (int)Args.size() * 2 &&
7209 "Argument outside the range of possible shuffle inputs!");
7210 if (Mask[i] != -1 && Mask[i] != *Args[i])
7218 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7221 /// This is a fast way to test a shuffle mask against a fixed pattern:
7223 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7225 /// It returns true if the mask is exactly as wide as the argument list, and
7226 /// each element of the mask is either -1 (signifying undef) or the value given
7227 /// in the argument.
7228 static const VariadicFunction1<
7229 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7231 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7233 /// This helper function produces an 8-bit shuffle immediate corresponding to
7234 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7235 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7238 /// NB: We rely heavily on "undef" masks preserving the input lane.
7239 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7240 SelectionDAG &DAG) {
7241 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7242 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7243 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7244 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7245 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7248 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7249 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7250 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7251 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7252 return DAG.getConstant(Imm, MVT::i8);
7255 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7257 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7258 /// support for floating point shuffles but not integer shuffles. These
7259 /// instructions will incur a domain crossing penalty on some chips though so
7260 /// it is better to avoid lowering through this for integer vectors where
7262 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7263 const X86Subtarget *Subtarget,
7264 SelectionDAG &DAG) {
7266 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7267 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7268 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7269 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7270 ArrayRef<int> Mask = SVOp->getMask();
7271 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7273 if (isSingleInputShuffleMask(Mask)) {
7274 // Straight shuffle of a single input vector. Simulate this by using the
7275 // single input as both of the "inputs" to this instruction..
7276 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7277 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7278 DAG.getConstant(SHUFPDMask, MVT::i8));
7280 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7281 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7283 // Use dedicated unpack instructions for masks that match their pattern.
7284 if (isShuffleEquivalent(Mask, 0, 2))
7285 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7286 if (isShuffleEquivalent(Mask, 1, 3))
7287 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7289 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7290 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7291 DAG.getConstant(SHUFPDMask, MVT::i8));
7294 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7296 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7297 /// the integer unit to minimize domain crossing penalties. However, for blends
7298 /// it falls back to the floating point shuffle operation with appropriate bit
7300 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7305 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7306 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7307 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7308 ArrayRef<int> Mask = SVOp->getMask();
7309 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7311 if (isSingleInputShuffleMask(Mask)) {
7312 // Straight shuffle of a single input vector. For everything from SSE2
7313 // onward this has a single fast instruction with no scary immediates.
7314 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7315 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7316 int WidenedMask[4] = {
7317 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7318 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7320 ISD::BITCAST, DL, MVT::v2i64,
7321 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7322 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7325 // Use dedicated unpack instructions for masks that match their pattern.
7326 if (isShuffleEquivalent(Mask, 0, 2))
7327 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7328 if (isShuffleEquivalent(Mask, 1, 3))
7329 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7331 // We implement this with SHUFPD which is pretty lame because it will likely
7332 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7333 // However, all the alternatives are still more cycles and newer chips don't
7334 // have this problem. It would be really nice if x86 had better shuffles here.
7335 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7336 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7337 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7338 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7341 /// \brief Lower 4-lane 32-bit floating point shuffles.
7343 /// Uses instructions exclusively from the floating point unit to minimize
7344 /// domain crossing penalties, as these are sufficient to implement all v4f32
7346 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7347 const X86Subtarget *Subtarget,
7348 SelectionDAG &DAG) {
7350 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7351 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7352 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7354 ArrayRef<int> Mask = SVOp->getMask();
7355 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7357 SDValue LowV = V1, HighV = V2;
7358 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7361 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7363 if (NumV2Elements == 0)
7364 // Straight shuffle of a single input vector. We pass the input vector to
7365 // both operands to simulate this with a SHUFPS.
7366 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7367 getV4X86ShuffleImm8ForMask(Mask, DAG));
7369 // Use dedicated unpack instructions for masks that match their pattern.
7370 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7371 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7372 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7373 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7375 if (NumV2Elements == 1) {
7377 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7380 // Check for whether we can use INSERTPS to perform the blend. We only use
7381 // INSERTPS when the V1 elements are already in the correct locations
7382 // because otherwise we can just always use two SHUFPS instructions which
7383 // are much smaller to encode than a SHUFPS and an INSERTPS.
7384 if (Subtarget->hasSSE41()) {
7385 // When using INSERTPS we can zero any lane of the destination. Collect
7386 // the zero inputs into a mask and drop them from the lanes of V1 which
7387 // actually need to be present as inputs to the INSERTPS.
7389 if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7390 ZMask = 0xF ^ (1 << V2Index);
7391 } else if (V1.getOpcode() == ISD::BUILD_VECTOR) {
7392 for (int i = 0; i < 4; ++i) {
7397 SDValue Input = V1.getOperand(M);
7398 if (Input.getOpcode() != ISD::UNDEF &&
7399 !X86::isZeroNode(Input)) {
7400 // A non-zero input!
7409 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7410 int InsertShuffleMask[4] = {-1, -1, -1, -1};
7411 for (int i = 0; i < 4; ++i)
7412 if (i != V2Index && (ZMask & (1 << i)) == 0)
7413 InsertShuffleMask[i] = Mask[i];
7415 if (isNoopShuffleMask(InsertShuffleMask)) {
7416 // Replace V1 with undef if nothing from V1 survives the INSERTPS.
7417 if ((ZMask | 1 << V2Index) == 0xF)
7418 V1 = DAG.getUNDEF(MVT::v4f32);
7420 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7421 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7423 // Insert the V2 element into the desired position.
7424 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7425 DAG.getConstant(InsertPSMask, MVT::i8));
7429 // Compute the index adjacent to V2Index and in the same half by toggling
7431 int V2AdjIndex = V2Index ^ 1;
7433 if (Mask[V2AdjIndex] == -1) {
7434 // Handles all the cases where we have a single V2 element and an undef.
7435 // This will only ever happen in the high lanes because we commute the
7436 // vector otherwise.
7438 std::swap(LowV, HighV);
7439 NewMask[V2Index] -= 4;
7441 // Handle the case where the V2 element ends up adjacent to a V1 element.
7442 // To make this work, blend them together as the first step.
7443 int V1Index = V2AdjIndex;
7444 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7445 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7446 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7448 // Now proceed to reconstruct the final blend as we have the necessary
7449 // high or low half formed.
7456 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7457 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7459 } else if (NumV2Elements == 2) {
7460 if (Mask[0] < 4 && Mask[1] < 4) {
7461 // Handle the easy case where we have V1 in the low lanes and V2 in the
7462 // high lanes. We never see this reversed because we sort the shuffle.
7466 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7467 // trying to place elements directly, just blend them and set up the final
7468 // shuffle to place them.
7470 // The first two blend mask elements are for V1, the second two are for
7472 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7473 Mask[2] < 4 ? Mask[2] : Mask[3],
7474 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7475 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7476 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7477 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7479 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7482 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7483 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7484 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7485 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7488 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7489 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7492 static SDValue lowerIntegerElementInsertionVectorShuffle(
7493 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7494 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7495 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7496 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7499 // Check for a single input from a SCALAR_TO_VECTOR node.
7500 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7501 // all the smarts here sunk into that routine. However, the current
7502 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7503 // vector shuffle lowering is dead.
7504 if ((Mask[V2Index] == (int)Mask.size() &&
7505 V2.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
7506 V2.getOpcode() == ISD::BUILD_VECTOR) {
7507 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7509 bool V1IsAllZero = false;
7510 if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7512 } else if (V1.getOpcode() == ISD::BUILD_VECTOR) {
7514 for (int M : Mask) {
7515 if (M < 0 || M >= (int)Mask.size())
7517 SDValue Input = V1.getOperand(M);
7518 if (Input.getOpcode() != ISD::UNDEF && !X86::isZeroNode(Input)) {
7519 // A non-zero input!
7520 V1IsAllZero = false;
7526 // First, we need to zext the scalar if it is smaller than an i32.
7527 MVT EltVT = VT.getVectorElementType();
7528 assert(EltVT == V2S.getSimpleValueType() &&
7529 "Different scalar and element types!");
7531 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7532 // Zero-extend directly to i32.
7534 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7537 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7538 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7540 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7543 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7544 // the desired position. Otherwise it is more efficient to do a vector
7545 // shift left. We know that we can do a vector shift left because all
7546 // the inputs are zero.
7547 if (VT.getVectorNumElements() <= 4) {
7548 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7549 V2Shuffle[V2Index] = 0;
7550 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7552 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7554 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7556 V2Index * EltVT.getSizeInBits(),
7557 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7558 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7567 /// \brief Lower 4-lane i32 vector shuffles.
7569 /// We try to handle these with integer-domain shuffles where we can, but for
7570 /// blends we use the floating point domain blend instructions.
7571 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7572 const X86Subtarget *Subtarget,
7573 SelectionDAG &DAG) {
7575 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7576 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7577 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7578 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7579 ArrayRef<int> Mask = SVOp->getMask();
7580 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7583 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7585 if (NumV2Elements == 0)
7586 // Straight shuffle of a single input vector. For everything from SSE2
7587 // onward this has a single fast instruction with no scary immediates.
7588 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7589 getV4X86ShuffleImm8ForMask(Mask, DAG));
7591 // Use dedicated unpack instructions for masks that match their pattern.
7592 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7593 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7594 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7595 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7597 // There are special ways we can lower some single-element blends.
7598 if (NumV2Elements == 1)
7599 if (SDValue V = lowerIntegerElementInsertionVectorShuffle(
7600 MVT::v4i32, DL, V1, V2, Mask, Subtarget, DAG))
7603 // We implement this with SHUFPS because it can blend from two vectors.
7604 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7605 // up the inputs, bypassing domain shift penalties that we would encur if we
7606 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7608 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7609 DAG.getVectorShuffle(
7611 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7612 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7615 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7616 /// shuffle lowering, and the most complex part.
7618 /// The lowering strategy is to try to form pairs of input lanes which are
7619 /// targeted at the same half of the final vector, and then use a dword shuffle
7620 /// to place them onto the right half, and finally unpack the paired lanes into
7621 /// their final position.
7623 /// The exact breakdown of how to form these dword pairs and align them on the
7624 /// correct sides is really tricky. See the comments within the function for
7625 /// more of the details.
7626 static SDValue lowerV8I16SingleInputVectorShuffle(
7627 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7628 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7629 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7630 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7631 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7633 SmallVector<int, 4> LoInputs;
7634 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7635 [](int M) { return M >= 0; });
7636 std::sort(LoInputs.begin(), LoInputs.end());
7637 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7638 SmallVector<int, 4> HiInputs;
7639 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7640 [](int M) { return M >= 0; });
7641 std::sort(HiInputs.begin(), HiInputs.end());
7642 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7644 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7645 int NumHToL = LoInputs.size() - NumLToL;
7647 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7648 int NumHToH = HiInputs.size() - NumLToH;
7649 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7650 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7651 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7652 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7654 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7655 // such inputs we can swap two of the dwords across the half mark and end up
7656 // with <=2 inputs to each half in each half. Once there, we can fall through
7657 // to the generic code below. For example:
7659 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7660 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7662 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7663 // and an existing 2-into-2 on the other half. In this case we may have to
7664 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7665 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7666 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7667 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7668 // half than the one we target for fixing) will be fixed when we re-enter this
7669 // path. We will also combine away any sequence of PSHUFD instructions that
7670 // result into a single instruction. Here is an example of the tricky case:
7672 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7673 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7675 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7677 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7678 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7680 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7681 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7683 // The result is fine to be handled by the generic logic.
7684 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7685 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7686 int AOffset, int BOffset) {
7687 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7688 "Must call this with A having 3 or 1 inputs from the A half.");
7689 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7690 "Must call this with B having 1 or 3 inputs from the B half.");
7691 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7692 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7694 // Compute the index of dword with only one word among the three inputs in
7695 // a half by taking the sum of the half with three inputs and subtracting
7696 // the sum of the actual three inputs. The difference is the remaining
7699 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7700 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7701 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7702 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7703 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7704 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7705 int TripleNonInputIdx =
7706 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7707 TripleDWord = TripleNonInputIdx / 2;
7709 // We use xor with one to compute the adjacent DWord to whichever one the
7711 OneInputDWord = (OneInput / 2) ^ 1;
7713 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7714 // and BToA inputs. If there is also such a problem with the BToB and AToB
7715 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7716 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7717 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7718 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7719 // Compute how many inputs will be flipped by swapping these DWords. We
7721 // to balance this to ensure we don't form a 3-1 shuffle in the other
7723 int NumFlippedAToBInputs =
7724 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7725 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7726 int NumFlippedBToBInputs =
7727 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7728 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7729 if ((NumFlippedAToBInputs == 1 &&
7730 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7731 (NumFlippedBToBInputs == 1 &&
7732 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7733 // We choose whether to fix the A half or B half based on whether that
7734 // half has zero flipped inputs. At zero, we may not be able to fix it
7735 // with that half. We also bias towards fixing the B half because that
7736 // will more commonly be the high half, and we have to bias one way.
7737 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7738 ArrayRef<int> Inputs) {
7739 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7740 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7741 PinnedIdx ^ 1) != Inputs.end();
7742 // Determine whether the free index is in the flipped dword or the
7743 // unflipped dword based on where the pinned index is. We use this bit
7744 // in an xor to conditionally select the adjacent dword.
7745 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7746 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7747 FixFreeIdx) != Inputs.end();
7748 if (IsFixIdxInput == IsFixFreeIdxInput)
7750 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7751 FixFreeIdx) != Inputs.end();
7752 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7753 "We need to be changing the number of flipped inputs!");
7754 int PSHUFHalfMask[] = {0, 1, 2, 3};
7755 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7756 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7758 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7761 if (M != -1 && M == FixIdx)
7763 else if (M != -1 && M == FixFreeIdx)
7766 if (NumFlippedBToBInputs != 0) {
7768 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7769 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7771 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7773 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7774 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7779 int PSHUFDMask[] = {0, 1, 2, 3};
7780 PSHUFDMask[ADWord] = BDWord;
7781 PSHUFDMask[BDWord] = ADWord;
7782 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7783 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7784 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7785 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7787 // Adjust the mask to match the new locations of A and B.
7789 if (M != -1 && M/2 == ADWord)
7790 M = 2 * BDWord + M % 2;
7791 else if (M != -1 && M/2 == BDWord)
7792 M = 2 * ADWord + M % 2;
7794 // Recurse back into this routine to re-compute state now that this isn't
7795 // a 3 and 1 problem.
7796 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7799 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7800 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7801 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7802 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7804 // At this point there are at most two inputs to the low and high halves from
7805 // each half. That means the inputs can always be grouped into dwords and
7806 // those dwords can then be moved to the correct half with a dword shuffle.
7807 // We use at most one low and one high word shuffle to collect these paired
7808 // inputs into dwords, and finally a dword shuffle to place them.
7809 int PSHUFLMask[4] = {-1, -1, -1, -1};
7810 int PSHUFHMask[4] = {-1, -1, -1, -1};
7811 int PSHUFDMask[4] = {-1, -1, -1, -1};
7813 // First fix the masks for all the inputs that are staying in their
7814 // original halves. This will then dictate the targets of the cross-half
7816 auto fixInPlaceInputs =
7817 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7818 MutableArrayRef<int> SourceHalfMask,
7819 MutableArrayRef<int> HalfMask, int HalfOffset) {
7820 if (InPlaceInputs.empty())
7822 if (InPlaceInputs.size() == 1) {
7823 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7824 InPlaceInputs[0] - HalfOffset;
7825 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7828 if (IncomingInputs.empty()) {
7829 // Just fix all of the in place inputs.
7830 for (int Input : InPlaceInputs) {
7831 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7832 PSHUFDMask[Input / 2] = Input / 2;
7837 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7838 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7839 InPlaceInputs[0] - HalfOffset;
7840 // Put the second input next to the first so that they are packed into
7841 // a dword. We find the adjacent index by toggling the low bit.
7842 int AdjIndex = InPlaceInputs[0] ^ 1;
7843 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7844 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7845 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7847 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7848 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7850 // Now gather the cross-half inputs and place them into a free dword of
7851 // their target half.
7852 // FIXME: This operation could almost certainly be simplified dramatically to
7853 // look more like the 3-1 fixing operation.
7854 auto moveInputsToRightHalf = [&PSHUFDMask](
7855 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7856 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7857 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7859 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7860 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7862 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7864 int LowWord = Word & ~1;
7865 int HighWord = Word | 1;
7866 return isWordClobbered(SourceHalfMask, LowWord) ||
7867 isWordClobbered(SourceHalfMask, HighWord);
7870 if (IncomingInputs.empty())
7873 if (ExistingInputs.empty()) {
7874 // Map any dwords with inputs from them into the right half.
7875 for (int Input : IncomingInputs) {
7876 // If the source half mask maps over the inputs, turn those into
7877 // swaps and use the swapped lane.
7878 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7879 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7880 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7881 Input - SourceOffset;
7882 // We have to swap the uses in our half mask in one sweep.
7883 for (int &M : HalfMask)
7884 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7886 else if (M == Input)
7887 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7889 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7890 Input - SourceOffset &&
7891 "Previous placement doesn't match!");
7893 // Note that this correctly re-maps both when we do a swap and when
7894 // we observe the other side of the swap above. We rely on that to
7895 // avoid swapping the members of the input list directly.
7896 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7899 // Map the input's dword into the correct half.
7900 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7901 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7903 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7905 "Previous placement doesn't match!");
7908 // And just directly shift any other-half mask elements to be same-half
7909 // as we will have mirrored the dword containing the element into the
7910 // same position within that half.
7911 for (int &M : HalfMask)
7912 if (M >= SourceOffset && M < SourceOffset + 4) {
7913 M = M - SourceOffset + DestOffset;
7914 assert(M >= 0 && "This should never wrap below zero!");
7919 // Ensure we have the input in a viable dword of its current half. This
7920 // is particularly tricky because the original position may be clobbered
7921 // by inputs being moved and *staying* in that half.
7922 if (IncomingInputs.size() == 1) {
7923 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7924 int InputFixed = std::find(std::begin(SourceHalfMask),
7925 std::end(SourceHalfMask), -1) -
7926 std::begin(SourceHalfMask) + SourceOffset;
7927 SourceHalfMask[InputFixed - SourceOffset] =
7928 IncomingInputs[0] - SourceOffset;
7929 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7931 IncomingInputs[0] = InputFixed;
7933 } else if (IncomingInputs.size() == 2) {
7934 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7935 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7936 // We have two non-adjacent or clobbered inputs we need to extract from
7937 // the source half. To do this, we need to map them into some adjacent
7938 // dword slot in the source mask.
7939 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
7940 IncomingInputs[1] - SourceOffset};
7942 // If there is a free slot in the source half mask adjacent to one of
7943 // the inputs, place the other input in it. We use (Index XOR 1) to
7944 // compute an adjacent index.
7945 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
7946 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
7947 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
7948 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7949 InputsFixed[1] = InputsFixed[0] ^ 1;
7950 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
7951 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
7952 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
7953 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
7954 InputsFixed[0] = InputsFixed[1] ^ 1;
7955 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
7956 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
7957 // The two inputs are in the same DWord but it is clobbered and the
7958 // adjacent DWord isn't used at all. Move both inputs to the free
7960 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
7961 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
7962 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
7963 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
7965 // The only way we hit this point is if there is no clobbering
7966 // (because there are no off-half inputs to this half) and there is no
7967 // free slot adjacent to one of the inputs. In this case, we have to
7968 // swap an input with a non-input.
7969 for (int i = 0; i < 4; ++i)
7970 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
7971 "We can't handle any clobbers here!");
7972 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
7973 "Cannot have adjacent inputs here!");
7975 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7976 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
7978 // We also have to update the final source mask in this case because
7979 // it may need to undo the above swap.
7980 for (int &M : FinalSourceHalfMask)
7981 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
7982 M = InputsFixed[1] + SourceOffset;
7983 else if (M == InputsFixed[1] + SourceOffset)
7984 M = (InputsFixed[0] ^ 1) + SourceOffset;
7986 InputsFixed[1] = InputsFixed[0] ^ 1;
7989 // Point everything at the fixed inputs.
7990 for (int &M : HalfMask)
7991 if (M == IncomingInputs[0])
7992 M = InputsFixed[0] + SourceOffset;
7993 else if (M == IncomingInputs[1])
7994 M = InputsFixed[1] + SourceOffset;
7996 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
7997 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8000 llvm_unreachable("Unhandled input size!");
8003 // Now hoist the DWord down to the right half.
8004 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8005 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8006 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8007 for (int &M : HalfMask)
8008 for (int Input : IncomingInputs)
8010 M = FreeDWord * 2 + Input % 2;
8012 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8013 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8014 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8015 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8017 // Now enact all the shuffles we've computed to move the inputs into their
8019 if (!isNoopShuffleMask(PSHUFLMask))
8020 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8021 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8022 if (!isNoopShuffleMask(PSHUFHMask))
8023 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8024 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8025 if (!isNoopShuffleMask(PSHUFDMask))
8026 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8027 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8028 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8029 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8031 // At this point, each half should contain all its inputs, and we can then
8032 // just shuffle them into their final position.
8033 assert(std::count_if(LoMask.begin(), LoMask.end(),
8034 [](int M) { return M >= 4; }) == 0 &&
8035 "Failed to lift all the high half inputs to the low mask!");
8036 assert(std::count_if(HiMask.begin(), HiMask.end(),
8037 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8038 "Failed to lift all the low half inputs to the high mask!");
8040 // Do a half shuffle for the low mask.
8041 if (!isNoopShuffleMask(LoMask))
8042 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8043 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8045 // Do a half shuffle with the high mask after shifting its values down.
8046 for (int &M : HiMask)
8049 if (!isNoopShuffleMask(HiMask))
8050 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8051 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8056 /// \brief Detect whether the mask pattern should be lowered through
8059 /// This essentially tests whether viewing the mask as an interleaving of two
8060 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8061 /// lowering it through interleaving is a significantly better strategy.
8062 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8063 int NumEvenInputs[2] = {0, 0};
8064 int NumOddInputs[2] = {0, 0};
8065 int NumLoInputs[2] = {0, 0};
8066 int NumHiInputs[2] = {0, 0};
8067 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8071 int InputIdx = Mask[i] >= Size;
8074 ++NumLoInputs[InputIdx];
8076 ++NumHiInputs[InputIdx];
8079 ++NumEvenInputs[InputIdx];
8081 ++NumOddInputs[InputIdx];
8084 // The minimum number of cross-input results for both the interleaved and
8085 // split cases. If interleaving results in fewer cross-input results, return
8087 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8088 NumEvenInputs[0] + NumOddInputs[1]);
8089 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8090 NumLoInputs[0] + NumHiInputs[1]);
8091 return InterleavedCrosses < SplitCrosses;
8094 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8096 /// This strategy only works when the inputs from each vector fit into a single
8097 /// half of that vector, and generally there are not so many inputs as to leave
8098 /// the in-place shuffles required highly constrained (and thus expensive). It
8099 /// shifts all the inputs into a single side of both input vectors and then
8100 /// uses an unpack to interleave these inputs in a single vector. At that
8101 /// point, we will fall back on the generic single input shuffle lowering.
8102 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8104 MutableArrayRef<int> Mask,
8105 const X86Subtarget *Subtarget,
8106 SelectionDAG &DAG) {
8107 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8108 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8109 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8110 for (int i = 0; i < 8; ++i)
8111 if (Mask[i] >= 0 && Mask[i] < 4)
8112 LoV1Inputs.push_back(i);
8113 else if (Mask[i] >= 4 && Mask[i] < 8)
8114 HiV1Inputs.push_back(i);
8115 else if (Mask[i] >= 8 && Mask[i] < 12)
8116 LoV2Inputs.push_back(i);
8117 else if (Mask[i] >= 12)
8118 HiV2Inputs.push_back(i);
8120 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8121 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8124 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8125 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8126 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8128 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8129 HiV1Inputs.size() + HiV2Inputs.size();
8131 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8132 ArrayRef<int> HiInputs, bool MoveToLo,
8134 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8135 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8136 if (BadInputs.empty())
8139 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8140 int MoveOffset = MoveToLo ? 0 : 4;
8142 if (GoodInputs.empty()) {
8143 for (int BadInput : BadInputs) {
8144 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8145 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8148 if (GoodInputs.size() == 2) {
8149 // If the low inputs are spread across two dwords, pack them into
8151 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8152 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8153 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8154 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8156 // Otherwise pin the good inputs.
8157 for (int GoodInput : GoodInputs)
8158 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8161 if (BadInputs.size() == 2) {
8162 // If we have two bad inputs then there may be either one or two good
8163 // inputs fixed in place. Find a fixed input, and then find the *other*
8164 // two adjacent indices by using modular arithmetic.
8166 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8167 [](int M) { return M >= 0; }) -
8168 std::begin(MoveMask);
8170 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8171 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8172 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8173 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8174 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8175 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8176 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8178 assert(BadInputs.size() == 1 && "All sizes handled");
8179 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8180 std::end(MoveMask), -1) -
8181 std::begin(MoveMask);
8182 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8183 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8187 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8190 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8192 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8195 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8196 // cross-half traffic in the final shuffle.
8198 // Munge the mask to be a single-input mask after the unpack merges the
8202 M = 2 * (M % 4) + (M / 8);
8204 return DAG.getVectorShuffle(
8205 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8206 DL, MVT::v8i16, V1, V2),
8207 DAG.getUNDEF(MVT::v8i16), Mask);
8210 /// \brief Generic lowering of 8-lane i16 shuffles.
8212 /// This handles both single-input shuffles and combined shuffle/blends with
8213 /// two inputs. The single input shuffles are immediately delegated to
8214 /// a dedicated lowering routine.
8216 /// The blends are lowered in one of three fundamental ways. If there are few
8217 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8218 /// of the input is significantly cheaper when lowered as an interleaving of
8219 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8220 /// halves of the inputs separately (making them have relatively few inputs)
8221 /// and then concatenate them.
8222 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8223 const X86Subtarget *Subtarget,
8224 SelectionDAG &DAG) {
8226 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8227 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8228 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8229 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8230 ArrayRef<int> OrigMask = SVOp->getMask();
8231 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8232 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8233 MutableArrayRef<int> Mask(MaskStorage);
8235 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8237 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8238 auto isV2 = [](int M) { return M >= 8; };
8240 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8241 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8243 if (NumV2Inputs == 0)
8244 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8246 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8247 "to be V1-input shuffles.");
8249 // There are special ways we can lower some single-element blends.
8250 if (NumV2Inputs == 1)
8251 if (SDValue V = lowerIntegerElementInsertionVectorShuffle(
8252 MVT::v8i16, DL, V1, V2, Mask, Subtarget, DAG))
8255 if (NumV1Inputs + NumV2Inputs <= 4)
8256 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8258 // Check whether an interleaving lowering is likely to be more efficient.
8259 // This isn't perfect but it is a strong heuristic that tends to work well on
8260 // the kinds of shuffles that show up in practice.
8262 // FIXME: Handle 1x, 2x, and 4x interleaving.
8263 if (shouldLowerAsInterleaving(Mask)) {
8264 // FIXME: Figure out whether we should pack these into the low or high
8267 int EMask[8], OMask[8];
8268 for (int i = 0; i < 4; ++i) {
8269 EMask[i] = Mask[2*i];
8270 OMask[i] = Mask[2*i + 1];
8275 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8276 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8278 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8281 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8282 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8284 for (int i = 0; i < 4; ++i) {
8285 LoBlendMask[i] = Mask[i];
8286 HiBlendMask[i] = Mask[i + 4];
8289 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8290 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8291 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8292 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8294 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8295 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8298 /// \brief Check whether a compaction lowering can be done by dropping even
8299 /// elements and compute how many times even elements must be dropped.
8301 /// This handles shuffles which take every Nth element where N is a power of
8302 /// two. Example shuffle masks:
8304 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8305 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8306 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8307 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8308 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8309 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8311 /// Any of these lanes can of course be undef.
8313 /// This routine only supports N <= 3.
8314 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8317 /// \returns N above, or the number of times even elements must be dropped if
8318 /// there is such a number. Otherwise returns zero.
8319 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8320 // Figure out whether we're looping over two inputs or just one.
8321 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8323 // The modulus for the shuffle vector entries is based on whether this is
8324 // a single input or not.
8325 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8326 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8327 "We should only be called with masks with a power-of-2 size!");
8329 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8331 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8332 // and 2^3 simultaneously. This is because we may have ambiguity with
8333 // partially undef inputs.
8334 bool ViableForN[3] = {true, true, true};
8336 for (int i = 0, e = Mask.size(); i < e; ++i) {
8337 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8342 bool IsAnyViable = false;
8343 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8344 if (ViableForN[j]) {
8347 // The shuffle mask must be equal to (i * 2^N) % M.
8348 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8351 ViableForN[j] = false;
8353 // Early exit if we exhaust the possible powers of two.
8358 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8362 // Return 0 as there is no viable power of two.
8366 /// \brief Generic lowering of v16i8 shuffles.
8368 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8369 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8370 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8371 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8373 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8374 const X86Subtarget *Subtarget,
8375 SelectionDAG &DAG) {
8377 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8378 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8379 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8380 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8381 ArrayRef<int> OrigMask = SVOp->getMask();
8382 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8383 int MaskStorage[16] = {
8384 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8385 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8386 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8387 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8388 MutableArrayRef<int> Mask(MaskStorage);
8389 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8390 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8393 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8395 // For single-input shuffles, there are some nicer lowering tricks we can use.
8396 if (NumV2Elements == 0) {
8397 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8398 // Notably, this handles splat and partial-splat shuffles more efficiently.
8399 // However, it only makes sense if the pre-duplication shuffle simplifies
8400 // things significantly. Currently, this means we need to be able to
8401 // express the pre-duplication shuffle as an i16 shuffle.
8403 // FIXME: We should check for other patterns which can be widened into an
8404 // i16 shuffle as well.
8405 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8406 for (int i = 0; i < 16; i += 2) {
8407 if (Mask[i] != Mask[i + 1])
8412 auto tryToWidenViaDuplication = [&]() -> SDValue {
8413 if (!canWidenViaDuplication(Mask))
8415 SmallVector<int, 4> LoInputs;
8416 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8417 [](int M) { return M >= 0 && M < 8; });
8418 std::sort(LoInputs.begin(), LoInputs.end());
8419 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8421 SmallVector<int, 4> HiInputs;
8422 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8423 [](int M) { return M >= 8; });
8424 std::sort(HiInputs.begin(), HiInputs.end());
8425 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8428 bool TargetLo = LoInputs.size() >= HiInputs.size();
8429 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8430 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8432 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8433 SmallDenseMap<int, int, 8> LaneMap;
8434 for (int I : InPlaceInputs) {
8435 PreDupI16Shuffle[I/2] = I/2;
8438 int j = TargetLo ? 0 : 4, je = j + 4;
8439 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8440 // Check if j is already a shuffle of this input. This happens when
8441 // there are two adjacent bytes after we move the low one.
8442 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8443 // If we haven't yet mapped the input, search for a slot into which
8445 while (j < je && PreDupI16Shuffle[j] != -1)
8449 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8452 // Map this input with the i16 shuffle.
8453 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8456 // Update the lane map based on the mapping we ended up with.
8457 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8460 ISD::BITCAST, DL, MVT::v16i8,
8461 DAG.getVectorShuffle(MVT::v8i16, DL,
8462 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8463 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8465 // Unpack the bytes to form the i16s that will be shuffled into place.
8466 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8467 MVT::v16i8, V1, V1);
8469 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8470 for (int i = 0; i < 16; i += 2) {
8472 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8473 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8476 ISD::BITCAST, DL, MVT::v16i8,
8477 DAG.getVectorShuffle(MVT::v8i16, DL,
8478 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8479 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8481 if (SDValue V = tryToWidenViaDuplication())
8485 // Check whether an interleaving lowering is likely to be more efficient.
8486 // This isn't perfect but it is a strong heuristic that tends to work well on
8487 // the kinds of shuffles that show up in practice.
8489 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8490 if (shouldLowerAsInterleaving(Mask)) {
8491 // FIXME: Figure out whether we should pack these into the low or high
8494 int EMask[16], OMask[16];
8495 for (int i = 0; i < 8; ++i) {
8496 EMask[i] = Mask[2*i];
8497 OMask[i] = Mask[2*i + 1];
8502 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8503 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8505 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8508 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8509 // with PSHUFB. It is important to do this before we attempt to generate any
8510 // blends but after all of the single-input lowerings. If the single input
8511 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8512 // want to preserve that and we can DAG combine any longer sequences into
8513 // a PSHUFB in the end. But once we start blending from multiple inputs,
8514 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8515 // and there are *very* few patterns that would actually be faster than the
8516 // PSHUFB approach because of its ability to zero lanes.
8518 // FIXME: The only exceptions to the above are blends which are exact
8519 // interleavings with direct instructions supporting them. We currently don't
8520 // handle those well here.
8521 if (Subtarget->hasSSSE3()) {
8524 for (int i = 0; i < 16; ++i)
8525 if (Mask[i] == -1) {
8526 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8528 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8530 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8532 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8533 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8534 if (isSingleInputShuffleMask(Mask))
8535 return V1; // Single inputs are easy.
8537 // Otherwise, blend the two.
8538 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8539 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8540 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8543 // There are special ways we can lower some single-element blends.
8544 if (NumV2Elements == 1)
8545 if (SDValue V = lowerIntegerElementInsertionVectorShuffle(
8546 MVT::v16i8, DL, V1, V2, Mask, Subtarget, DAG))
8549 // Check whether a compaction lowering can be done. This handles shuffles
8550 // which take every Nth element for some even N. See the helper function for
8553 // We special case these as they can be particularly efficiently handled with
8554 // the PACKUSB instruction on x86 and they show up in common patterns of
8555 // rearranging bytes to truncate wide elements.
8556 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8557 // NumEvenDrops is the power of two stride of the elements. Another way of
8558 // thinking about it is that we need to drop the even elements this many
8559 // times to get the original input.
8560 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8562 // First we need to zero all the dropped bytes.
8563 assert(NumEvenDrops <= 3 &&
8564 "No support for dropping even elements more than 3 times.");
8565 // We use the mask type to pick which bytes are preserved based on how many
8566 // elements are dropped.
8567 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8568 SDValue ByteClearMask =
8569 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8570 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8571 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8573 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8575 // Now pack things back together.
8576 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8577 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8578 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8579 for (int i = 1; i < NumEvenDrops; ++i) {
8580 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8581 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8587 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8588 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8589 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8590 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8592 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8593 MutableArrayRef<int> V1HalfBlendMask,
8594 MutableArrayRef<int> V2HalfBlendMask) {
8595 for (int i = 0; i < 8; ++i)
8596 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8597 V1HalfBlendMask[i] = HalfMask[i];
8599 } else if (HalfMask[i] >= 16) {
8600 V2HalfBlendMask[i] = HalfMask[i] - 16;
8601 HalfMask[i] = i + 8;
8604 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8605 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8607 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8609 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8610 MutableArrayRef<int> HiBlendMask) {
8612 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8613 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8615 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8616 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8617 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8618 [](int M) { return M >= 0 && M % 2 == 1; })) {
8619 // Use a mask to drop the high bytes.
8620 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8621 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8622 DAG.getConstant(0x00FF, MVT::v8i16));
8624 // This will be a single vector shuffle instead of a blend so nuke V2.
8625 V2 = DAG.getUNDEF(MVT::v8i16);
8627 // Squash the masks to point directly into V1.
8628 for (int &M : LoBlendMask)
8631 for (int &M : HiBlendMask)
8635 // Otherwise just unpack the low half of V into V1 and the high half into
8636 // V2 so that we can blend them as i16s.
8637 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8638 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8639 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8640 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8643 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8644 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8645 return std::make_pair(BlendedLo, BlendedHi);
8647 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8648 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8649 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8651 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8652 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8654 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8657 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8659 /// This routine breaks down the specific type of 128-bit shuffle and
8660 /// dispatches to the lowering routines accordingly.
8661 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8662 MVT VT, const X86Subtarget *Subtarget,
8663 SelectionDAG &DAG) {
8664 switch (VT.SimpleTy) {
8666 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8668 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8670 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8672 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8674 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8676 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8679 llvm_unreachable("Unimplemented!");
8683 static bool isHalfCrossingShuffleMask(ArrayRef<int> Mask) {
8684 int Size = Mask.size();
8685 for (int M : Mask.slice(0, Size / 2))
8686 if (M >= 0 && (M % Size) >= Size / 2)
8688 for (int M : Mask.slice(Size / 2, Size / 2))
8689 if (M >= 0 && (M % Size) < Size / 2)
8694 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
8697 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
8698 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
8699 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
8700 /// we encode the logic here for specific shuffle lowering routines to bail to
8701 /// when they exhaust the features avaible to more directly handle the shuffle.
8702 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
8704 const X86Subtarget *Subtarget,
8705 SelectionDAG &DAG) {
8707 MVT VT = Op.getSimpleValueType();
8708 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8709 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8710 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8712 ArrayRef<int> Mask = SVOp->getMask();
8714 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
8715 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
8717 int NumElements = VT.getVectorNumElements();
8718 int SplitNumElements = NumElements / 2;
8719 MVT ScalarVT = VT.getScalarType();
8720 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8722 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8723 DAG.getIntPtrConstant(0));
8724 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8725 DAG.getIntPtrConstant(SplitNumElements));
8726 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8727 DAG.getIntPtrConstant(0));
8728 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8729 DAG.getIntPtrConstant(SplitNumElements));
8731 // Now create two 4-way blends of these half-width vectors.
8732 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8733 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
8734 for (int i = 0; i < SplitNumElements; ++i) {
8735 int M = HalfMask[i];
8736 if (M >= NumElements) {
8737 V2BlendMask.push_back(M - NumElements);
8738 V1BlendMask.push_back(-1);
8739 BlendMask.push_back(SplitNumElements + i);
8740 } else if (M >= 0) {
8741 V2BlendMask.push_back(-1);
8742 V1BlendMask.push_back(M);
8743 BlendMask.push_back(i);
8745 V2BlendMask.push_back(-1);
8746 V1BlendMask.push_back(-1);
8747 BlendMask.push_back(-1);
8750 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8751 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8752 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8754 SDValue Lo = HalfBlend(LoMask);
8755 SDValue Hi = HalfBlend(HiMask);
8756 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8759 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
8761 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
8762 /// isn't available.
8763 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8764 const X86Subtarget *Subtarget,
8765 SelectionDAG &DAG) {
8767 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8768 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8770 ArrayRef<int> Mask = SVOp->getMask();
8771 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8773 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8774 // shuffles aren't a problem and FP and int have the same patterns.
8776 // FIXME: We can handle these more cleverly than splitting for v4f64.
8777 if (isHalfCrossingShuffleMask(Mask))
8778 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8780 if (isSingleInputShuffleMask(Mask)) {
8781 // Non-half-crossing single input shuffles can be lowerid with an
8782 // interleaved permutation.
8783 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
8784 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
8785 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
8786 DAG.getConstant(VPERMILPMask, MVT::i8));
8789 // X86 has dedicated unpack instructions that can handle specific blend
8790 // operations: UNPCKH and UNPCKL.
8791 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
8792 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
8793 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
8794 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
8795 // FIXME: It would be nice to find a way to get canonicalization to commute
8797 if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
8798 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
8799 if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
8800 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
8802 // Check if the blend happens to exactly fit that of SHUFPD.
8803 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
8804 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
8805 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
8806 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
8807 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
8808 DAG.getConstant(SHUFPDMask, MVT::i8));
8810 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
8811 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
8812 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
8813 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
8814 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
8815 DAG.getConstant(SHUFPDMask, MVT::i8));
8818 // Shuffle the input elements into the desired positions in V1 and V2 and
8819 // blend them together.
8820 int V1Mask[] = {-1, -1, -1, -1};
8821 int V2Mask[] = {-1, -1, -1, -1};
8822 for (int i = 0; i < 4; ++i)
8823 if (Mask[i] >= 0 && Mask[i] < 4)
8824 V1Mask[i] = Mask[i];
8825 else if (Mask[i] >= 4)
8826 V2Mask[i] = Mask[i] - 4;
8828 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
8829 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
8831 unsigned BlendMask = 0;
8832 for (int i = 0; i < 4; ++i)
8834 BlendMask |= 1 << i;
8836 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
8837 DAG.getConstant(BlendMask, MVT::i8));
8840 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
8842 /// Largely delegates to common code when we have AVX2 and to the floating-point
8843 /// code when we only have AVX.
8844 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8845 const X86Subtarget *Subtarget,
8846 SelectionDAG &DAG) {
8848 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
8849 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8850 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8852 ArrayRef<int> Mask = SVOp->getMask();
8853 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8855 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8856 // shuffles aren't a problem and FP and int have the same patterns.
8858 if (isHalfCrossingShuffleMask(Mask))
8859 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8861 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
8862 // delegate to floating point code.
8863 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
8864 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
8865 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
8866 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
8869 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
8871 /// This routine either breaks down the specific type of a 256-bit x86 vector
8872 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
8873 /// together based on the available instructions.
8874 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8875 MVT VT, const X86Subtarget *Subtarget,
8876 SelectionDAG &DAG) {
8877 switch (VT.SimpleTy) {
8879 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8881 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8886 // Fall back to the basic pattern of extracting the high half and forming
8888 // FIXME: Add targeted lowering for each type that can document rationale
8889 // for delegating to this when necessary.
8890 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8893 llvm_unreachable("Not a valid 256-bit x86 vector type!");
8897 /// \brief Tiny helper function to test whether a shuffle mask could be
8898 /// simplified by widening the elements being shuffled.
8899 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
8900 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8901 if (Mask[i] % 2 != 0 || Mask[i] + 1 != Mask[i+1])
8907 /// \brief Top-level lowering for x86 vector shuffles.
8909 /// This handles decomposition, canonicalization, and lowering of all x86
8910 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8911 /// above in helper routines. The canonicalization attempts to widen shuffles
8912 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8913 /// s.t. only one of the two inputs needs to be tested, etc.
8914 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8915 SelectionDAG &DAG) {
8916 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8917 ArrayRef<int> Mask = SVOp->getMask();
8918 SDValue V1 = Op.getOperand(0);
8919 SDValue V2 = Op.getOperand(1);
8920 MVT VT = Op.getSimpleValueType();
8921 int NumElements = VT.getVectorNumElements();
8924 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8926 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8927 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8928 if (V1IsUndef && V2IsUndef)
8929 return DAG.getUNDEF(VT);
8931 // When we create a shuffle node we put the UNDEF node to second operand,
8932 // but in some cases the first operand may be transformed to UNDEF.
8933 // In this case we should just commute the node.
8935 return DAG.getCommutedVectorShuffle(*SVOp);
8937 // Check for non-undef masks pointing at an undef vector and make the masks
8938 // undef as well. This makes it easier to match the shuffle based solely on
8942 if (M >= NumElements) {
8943 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8944 for (int &M : NewMask)
8945 if (M >= NumElements)
8947 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8950 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8951 // lanes but wider integers. We cap this to not form integers larger than i64
8952 // but it might be interesting to form i128 integers to handle flipping the
8953 // low and high halves of AVX 256-bit vectors.
8954 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8955 canWidenShuffleElements(Mask)) {
8956 SmallVector<int, 8> NewMask;
8957 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8958 NewMask.push_back(Mask[i] / 2);
8960 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8961 VT.getVectorNumElements() / 2);
8962 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8963 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8964 return DAG.getNode(ISD::BITCAST, dl, VT,
8965 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8968 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8969 for (int M : SVOp->getMask())
8972 else if (M < NumElements)
8977 // Commute the shuffle as needed such that more elements come from V1 than
8978 // V2. This allows us to match the shuffle pattern strictly on how many
8979 // elements come from V1 without handling the symmetric cases.
8980 if (NumV2Elements > NumV1Elements)
8981 return DAG.getCommutedVectorShuffle(*SVOp);
8983 // When the number of V1 and V2 elements are the same, try to minimize the
8984 // number of uses of V2 in the low half of the vector.
8985 if (NumV1Elements == NumV2Elements) {
8986 int LowV1Elements = 0, LowV2Elements = 0;
8987 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8988 if (M >= NumElements)
8992 if (LowV2Elements > LowV1Elements)
8993 return DAG.getCommutedVectorShuffle(*SVOp);
8996 // For each vector width, delegate to a specialized lowering routine.
8997 if (VT.getSizeInBits() == 128)
8998 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9000 if (VT.getSizeInBits() == 256)
9001 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9003 llvm_unreachable("Unimplemented!");
9007 //===----------------------------------------------------------------------===//
9008 // Legacy vector shuffle lowering
9010 // This code is the legacy code handling vector shuffles until the above
9011 // replaces its functionality and performance.
9012 //===----------------------------------------------------------------------===//
9014 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9015 bool hasInt256, unsigned *MaskOut = nullptr) {
9016 MVT EltVT = VT.getVectorElementType();
9018 // There is no blend with immediate in AVX-512.
9019 if (VT.is512BitVector())
9022 if (!hasSSE41 || EltVT == MVT::i8)
9024 if (!hasInt256 && VT == MVT::v16i16)
9027 unsigned MaskValue = 0;
9028 unsigned NumElems = VT.getVectorNumElements();
9029 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9030 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9031 unsigned NumElemsInLane = NumElems / NumLanes;
9033 // Blend for v16i16 should be symetric for the both lanes.
9034 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9036 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9037 int EltIdx = MaskVals[i];
9039 if ((EltIdx < 0 || EltIdx == (int)i) &&
9040 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9043 if (((unsigned)EltIdx == (i + NumElems)) &&
9044 (SndLaneEltIdx < 0 ||
9045 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9046 MaskValue |= (1 << i);
9052 *MaskOut = MaskValue;
9056 // Try to lower a shuffle node into a simple blend instruction.
9057 // This function assumes isBlendMask returns true for this
9058 // SuffleVectorSDNode
9059 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9061 const X86Subtarget *Subtarget,
9062 SelectionDAG &DAG) {
9063 MVT VT = SVOp->getSimpleValueType(0);
9064 MVT EltVT = VT.getVectorElementType();
9065 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9066 Subtarget->hasInt256() && "Trying to lower a "
9067 "VECTOR_SHUFFLE to a Blend but "
9068 "with the wrong mask"));
9069 SDValue V1 = SVOp->getOperand(0);
9070 SDValue V2 = SVOp->getOperand(1);
9072 unsigned NumElems = VT.getVectorNumElements();
9074 // Convert i32 vectors to floating point if it is not AVX2.
9075 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9077 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9078 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9080 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9081 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9084 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9085 DAG.getConstant(MaskValue, MVT::i32));
9086 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9089 /// In vector type \p VT, return true if the element at index \p InputIdx
9090 /// falls on a different 128-bit lane than \p OutputIdx.
9091 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9092 unsigned OutputIdx) {
9093 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9094 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9097 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9098 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9099 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9100 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9102 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9103 SelectionDAG &DAG) {
9104 MVT VT = V1.getSimpleValueType();
9105 assert(VT.is128BitVector() || VT.is256BitVector());
9107 MVT EltVT = VT.getVectorElementType();
9108 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9109 unsigned NumElts = VT.getVectorNumElements();
9111 SmallVector<SDValue, 32> PshufbMask;
9112 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9113 int InputIdx = MaskVals[OutputIdx];
9114 unsigned InputByteIdx;
9116 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9117 InputByteIdx = 0x80;
9119 // Cross lane is not allowed.
9120 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9122 InputByteIdx = InputIdx * EltSizeInBytes;
9123 // Index is an byte offset within the 128-bit lane.
9124 InputByteIdx &= 0xf;
9127 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9128 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9129 if (InputByteIdx != 0x80)
9134 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9136 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9137 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9138 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9141 // v8i16 shuffles - Prefer shuffles in the following order:
9142 // 1. [all] pshuflw, pshufhw, optional move
9143 // 2. [ssse3] 1 x pshufb
9144 // 3. [ssse3] 2 x pshufb + 1 x por
9145 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9147 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9148 SelectionDAG &DAG) {
9149 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9150 SDValue V1 = SVOp->getOperand(0);
9151 SDValue V2 = SVOp->getOperand(1);
9153 SmallVector<int, 8> MaskVals;
9155 // Determine if more than 1 of the words in each of the low and high quadwords
9156 // of the result come from the same quadword of one of the two inputs. Undef
9157 // mask values count as coming from any quadword, for better codegen.
9159 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9160 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9161 unsigned LoQuad[] = { 0, 0, 0, 0 };
9162 unsigned HiQuad[] = { 0, 0, 0, 0 };
9163 // Indices of quads used.
9164 std::bitset<4> InputQuads;
9165 for (unsigned i = 0; i < 8; ++i) {
9166 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9167 int EltIdx = SVOp->getMaskElt(i);
9168 MaskVals.push_back(EltIdx);
9177 InputQuads.set(EltIdx / 4);
9180 int BestLoQuad = -1;
9181 unsigned MaxQuad = 1;
9182 for (unsigned i = 0; i < 4; ++i) {
9183 if (LoQuad[i] > MaxQuad) {
9185 MaxQuad = LoQuad[i];
9189 int BestHiQuad = -1;
9191 for (unsigned i = 0; i < 4; ++i) {
9192 if (HiQuad[i] > MaxQuad) {
9194 MaxQuad = HiQuad[i];
9198 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9199 // of the two input vectors, shuffle them into one input vector so only a
9200 // single pshufb instruction is necessary. If there are more than 2 input
9201 // quads, disable the next transformation since it does not help SSSE3.
9202 bool V1Used = InputQuads[0] || InputQuads[1];
9203 bool V2Used = InputQuads[2] || InputQuads[3];
9204 if (Subtarget->hasSSSE3()) {
9205 if (InputQuads.count() == 2 && V1Used && V2Used) {
9206 BestLoQuad = InputQuads[0] ? 0 : 1;
9207 BestHiQuad = InputQuads[2] ? 2 : 3;
9209 if (InputQuads.count() > 2) {
9215 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9216 // the shuffle mask. If a quad is scored as -1, that means that it contains
9217 // words from all 4 input quadwords.
9219 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9221 BestLoQuad < 0 ? 0 : BestLoQuad,
9222 BestHiQuad < 0 ? 1 : BestHiQuad
9224 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9225 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9226 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9227 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9229 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9230 // source words for the shuffle, to aid later transformations.
9231 bool AllWordsInNewV = true;
9232 bool InOrder[2] = { true, true };
9233 for (unsigned i = 0; i != 8; ++i) {
9234 int idx = MaskVals[i];
9236 InOrder[i/4] = false;
9237 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9239 AllWordsInNewV = false;
9243 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9244 if (AllWordsInNewV) {
9245 for (int i = 0; i != 8; ++i) {
9246 int idx = MaskVals[i];
9249 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9250 if ((idx != i) && idx < 4)
9252 if ((idx != i) && idx > 3)
9261 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9262 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9263 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9264 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9265 unsigned TargetMask = 0;
9266 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9267 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9268 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9269 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9270 getShufflePSHUFLWImmediate(SVOp);
9271 V1 = NewV.getOperand(0);
9272 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9276 // Promote splats to a larger type which usually leads to more efficient code.
9277 // FIXME: Is this true if pshufb is available?
9278 if (SVOp->isSplat())
9279 return PromoteSplat(SVOp, DAG);
9281 // If we have SSSE3, and all words of the result are from 1 input vector,
9282 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9283 // is present, fall back to case 4.
9284 if (Subtarget->hasSSSE3()) {
9285 SmallVector<SDValue,16> pshufbMask;
9287 // If we have elements from both input vectors, set the high bit of the
9288 // shuffle mask element to zero out elements that come from V2 in the V1
9289 // mask, and elements that come from V1 in the V2 mask, so that the two
9290 // results can be OR'd together.
9291 bool TwoInputs = V1Used && V2Used;
9292 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9294 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9296 // Calculate the shuffle mask for the second input, shuffle it, and
9297 // OR it with the first shuffled input.
9298 CommuteVectorShuffleMask(MaskVals, 8);
9299 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9300 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9301 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9304 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9305 // and update MaskVals with new element order.
9306 std::bitset<8> InOrder;
9307 if (BestLoQuad >= 0) {
9308 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9309 for (int i = 0; i != 4; ++i) {
9310 int idx = MaskVals[i];
9313 } else if ((idx / 4) == BestLoQuad) {
9318 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9321 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9323 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9325 getShufflePSHUFLWImmediate(SVOp), DAG);
9329 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9330 // and update MaskVals with the new element order.
9331 if (BestHiQuad >= 0) {
9332 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9333 for (unsigned i = 4; i != 8; ++i) {
9334 int idx = MaskVals[i];
9337 } else if ((idx / 4) == BestHiQuad) {
9338 MaskV[i] = (idx & 3) + 4;
9342 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9345 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9346 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9347 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
9349 getShufflePSHUFHWImmediate(SVOp), DAG);
9353 // In case BestHi & BestLo were both -1, which means each quadword has a word
9354 // from each of the four input quadwords, calculate the InOrder bitvector now
9355 // before falling through to the insert/extract cleanup.
9356 if (BestLoQuad == -1 && BestHiQuad == -1) {
9358 for (int i = 0; i != 8; ++i)
9359 if (MaskVals[i] < 0 || MaskVals[i] == i)
9363 // The other elements are put in the right place using pextrw and pinsrw.
9364 for (unsigned i = 0; i != 8; ++i) {
9367 int EltIdx = MaskVals[i];
9370 SDValue ExtOp = (EltIdx < 8) ?
9371 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9372 DAG.getIntPtrConstant(EltIdx)) :
9373 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9374 DAG.getIntPtrConstant(EltIdx - 8));
9375 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9376 DAG.getIntPtrConstant(i));
9381 /// \brief v16i16 shuffles
9383 /// FIXME: We only support generation of a single pshufb currently. We can
9384 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9385 /// well (e.g 2 x pshufb + 1 x por).
9387 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9388 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9389 SDValue V1 = SVOp->getOperand(0);
9390 SDValue V2 = SVOp->getOperand(1);
9393 if (V2.getOpcode() != ISD::UNDEF)
9396 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9397 return getPSHUFB(MaskVals, V1, dl, DAG);
9400 // v16i8 shuffles - Prefer shuffles in the following order:
9401 // 1. [ssse3] 1 x pshufb
9402 // 2. [ssse3] 2 x pshufb + 1 x por
9403 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9404 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9405 const X86Subtarget* Subtarget,
9406 SelectionDAG &DAG) {
9407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9408 SDValue V1 = SVOp->getOperand(0);
9409 SDValue V2 = SVOp->getOperand(1);
9411 ArrayRef<int> MaskVals = SVOp->getMask();
9413 // Promote splats to a larger type which usually leads to more efficient code.
9414 // FIXME: Is this true if pshufb is available?
9415 if (SVOp->isSplat())
9416 return PromoteSplat(SVOp, DAG);
9418 // If we have SSSE3, case 1 is generated when all result bytes come from
9419 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9420 // present, fall back to case 3.
9422 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9423 if (Subtarget->hasSSSE3()) {
9424 SmallVector<SDValue,16> pshufbMask;
9426 // If all result elements are from one input vector, then only translate
9427 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9429 // Otherwise, we have elements from both input vectors, and must zero out
9430 // elements that come from V2 in the first mask, and V1 in the second mask
9431 // so that we can OR them together.
9432 for (unsigned i = 0; i != 16; ++i) {
9433 int EltIdx = MaskVals[i];
9434 if (EltIdx < 0 || EltIdx >= 16)
9436 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9438 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9439 DAG.getNode(ISD::BUILD_VECTOR, dl,
9440 MVT::v16i8, pshufbMask));
9442 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9443 // the 2nd operand if it's undefined or zero.
9444 if (V2.getOpcode() == ISD::UNDEF ||
9445 ISD::isBuildVectorAllZeros(V2.getNode()))
9448 // Calculate the shuffle mask for the second input, shuffle it, and
9449 // OR it with the first shuffled input.
9451 for (unsigned i = 0; i != 16; ++i) {
9452 int EltIdx = MaskVals[i];
9453 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9454 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9456 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9457 DAG.getNode(ISD::BUILD_VECTOR, dl,
9458 MVT::v16i8, pshufbMask));
9459 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9462 // No SSSE3 - Calculate in place words and then fix all out of place words
9463 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9464 // the 16 different words that comprise the two doublequadword input vectors.
9465 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9466 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9468 for (int i = 0; i != 8; ++i) {
9469 int Elt0 = MaskVals[i*2];
9470 int Elt1 = MaskVals[i*2+1];
9472 // This word of the result is all undef, skip it.
9473 if (Elt0 < 0 && Elt1 < 0)
9476 // This word of the result is already in the correct place, skip it.
9477 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9480 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9481 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9484 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9485 // using a single extract together, load it and store it.
9486 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9487 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9488 DAG.getIntPtrConstant(Elt1 / 2));
9489 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9490 DAG.getIntPtrConstant(i));
9494 // If Elt1 is defined, extract it from the appropriate source. If the
9495 // source byte is not also odd, shift the extracted word left 8 bits
9496 // otherwise clear the bottom 8 bits if we need to do an or.
9498 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9499 DAG.getIntPtrConstant(Elt1 / 2));
9500 if ((Elt1 & 1) == 0)
9501 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9503 TLI.getShiftAmountTy(InsElt.getValueType())));
9505 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9506 DAG.getConstant(0xFF00, MVT::i16));
9508 // If Elt0 is defined, extract it from the appropriate source. If the
9509 // source byte is not also even, shift the extracted word right 8 bits. If
9510 // Elt1 was also defined, OR the extracted values together before
9511 // inserting them in the result.
9513 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9514 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9515 if ((Elt0 & 1) != 0)
9516 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9518 TLI.getShiftAmountTy(InsElt0.getValueType())));
9520 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9521 DAG.getConstant(0x00FF, MVT::i16));
9522 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9525 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9526 DAG.getIntPtrConstant(i));
9528 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9531 // v32i8 shuffles - Translate to VPSHUFB if possible.
9533 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9534 const X86Subtarget *Subtarget,
9535 SelectionDAG &DAG) {
9536 MVT VT = SVOp->getSimpleValueType(0);
9537 SDValue V1 = SVOp->getOperand(0);
9538 SDValue V2 = SVOp->getOperand(1);
9540 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9542 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9543 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9544 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9546 // VPSHUFB may be generated if
9547 // (1) one of input vector is undefined or zeroinitializer.
9548 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9549 // And (2) the mask indexes don't cross the 128-bit lane.
9550 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9551 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9554 if (V1IsAllZero && !V2IsAllZero) {
9555 CommuteVectorShuffleMask(MaskVals, 32);
9558 return getPSHUFB(MaskVals, V1, dl, DAG);
9561 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9562 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9563 /// done when every pair / quad of shuffle mask elements point to elements in
9564 /// the right sequence. e.g.
9565 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9567 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9568 SelectionDAG &DAG) {
9569 MVT VT = SVOp->getSimpleValueType(0);
9571 unsigned NumElems = VT.getVectorNumElements();
9574 switch (VT.SimpleTy) {
9575 default: llvm_unreachable("Unexpected!");
9578 return SDValue(SVOp, 0);
9579 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
9580 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
9581 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
9582 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9583 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9584 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9587 SmallVector<int, 8> MaskVec;
9588 for (unsigned i = 0; i != NumElems; i += Scale) {
9590 for (unsigned j = 0; j != Scale; ++j) {
9591 int EltIdx = SVOp->getMaskElt(i+j);
9595 StartIdx = (EltIdx / Scale);
9596 if (EltIdx != (int)(StartIdx*Scale + j))
9599 MaskVec.push_back(StartIdx);
9602 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
9603 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
9604 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
9607 /// getVZextMovL - Return a zero-extending vector move low node.
9609 static SDValue getVZextMovL(MVT VT, MVT OpVT,
9610 SDValue SrcOp, SelectionDAG &DAG,
9611 const X86Subtarget *Subtarget, SDLoc dl) {
9612 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
9613 LoadSDNode *LD = nullptr;
9614 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
9615 LD = dyn_cast<LoadSDNode>(SrcOp);
9617 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
9619 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
9620 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
9621 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9622 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
9623 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
9625 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
9626 return DAG.getNode(ISD::BITCAST, dl, VT,
9627 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9628 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9636 return DAG.getNode(ISD::BITCAST, dl, VT,
9637 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9638 DAG.getNode(ISD::BITCAST, dl,
9642 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
9643 /// which could not be matched by any known target speficic shuffle
9645 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9647 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
9648 if (NewOp.getNode())
9651 MVT VT = SVOp->getSimpleValueType(0);
9653 unsigned NumElems = VT.getVectorNumElements();
9654 unsigned NumLaneElems = NumElems / 2;
9657 MVT EltVT = VT.getVectorElementType();
9658 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
9661 SmallVector<int, 16> Mask;
9662 for (unsigned l = 0; l < 2; ++l) {
9663 // Build a shuffle mask for the output, discovering on the fly which
9664 // input vectors to use as shuffle operands (recorded in InputUsed).
9665 // If building a suitable shuffle vector proves too hard, then bail
9666 // out with UseBuildVector set.
9667 bool UseBuildVector = false;
9668 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
9669 unsigned LaneStart = l * NumLaneElems;
9670 for (unsigned i = 0; i != NumLaneElems; ++i) {
9671 // The mask element. This indexes into the input.
9672 int Idx = SVOp->getMaskElt(i+LaneStart);
9674 // the mask element does not index into any input vector.
9679 // The input vector this mask element indexes into.
9680 int Input = Idx / NumLaneElems;
9682 // Turn the index into an offset from the start of the input vector.
9683 Idx -= Input * NumLaneElems;
9685 // Find or create a shuffle vector operand to hold this input.
9687 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
9688 if (InputUsed[OpNo] == Input)
9689 // This input vector is already an operand.
9691 if (InputUsed[OpNo] < 0) {
9692 // Create a new operand for this input vector.
9693 InputUsed[OpNo] = Input;
9698 if (OpNo >= array_lengthof(InputUsed)) {
9699 // More than two input vectors used! Give up on trying to create a
9700 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
9701 UseBuildVector = true;
9705 // Add the mask index for the new shuffle vector.
9706 Mask.push_back(Idx + OpNo * NumLaneElems);
9709 if (UseBuildVector) {
9710 SmallVector<SDValue, 16> SVOps;
9711 for (unsigned i = 0; i != NumLaneElems; ++i) {
9712 // The mask element. This indexes into the input.
9713 int Idx = SVOp->getMaskElt(i+LaneStart);
9715 SVOps.push_back(DAG.getUNDEF(EltVT));
9719 // The input vector this mask element indexes into.
9720 int Input = Idx / NumElems;
9722 // Turn the index into an offset from the start of the input vector.
9723 Idx -= Input * NumElems;
9725 // Extract the vector element by hand.
9726 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9727 SVOp->getOperand(Input),
9728 DAG.getIntPtrConstant(Idx)));
9731 // Construct the output using a BUILD_VECTOR.
9732 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9733 } else if (InputUsed[0] < 0) {
9734 // No input vectors were used! The result is undefined.
9735 Output[l] = DAG.getUNDEF(NVT);
9737 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9738 (InputUsed[0] % 2) * NumLaneElems,
9740 // If only one input was used, use an undefined vector for the other.
9741 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9742 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9743 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9744 // At least one input vector was used. Create a new shuffle vector.
9745 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9751 // Concatenate the result back
9752 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9755 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9756 /// 4 elements, and match them with several different shuffle types.
9758 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9759 SDValue V1 = SVOp->getOperand(0);
9760 SDValue V2 = SVOp->getOperand(1);
9762 MVT VT = SVOp->getSimpleValueType(0);
9764 assert(VT.is128BitVector() && "Unsupported vector size");
9766 std::pair<int, int> Locs[4];
9767 int Mask1[] = { -1, -1, -1, -1 };
9768 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9772 for (unsigned i = 0; i != 4; ++i) {
9773 int Idx = PermMask[i];
9775 Locs[i] = std::make_pair(-1, -1);
9777 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9779 Locs[i] = std::make_pair(0, NumLo);
9783 Locs[i] = std::make_pair(1, NumHi);
9785 Mask1[2+NumHi] = Idx;
9791 if (NumLo <= 2 && NumHi <= 2) {
9792 // If no more than two elements come from either vector. This can be
9793 // implemented with two shuffles. First shuffle gather the elements.
9794 // The second shuffle, which takes the first shuffle as both of its
9795 // vector operands, put the elements into the right order.
9796 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9798 int Mask2[] = { -1, -1, -1, -1 };
9800 for (unsigned i = 0; i != 4; ++i)
9801 if (Locs[i].first != -1) {
9802 unsigned Idx = (i < 2) ? 0 : 4;
9803 Idx += Locs[i].first * 2 + Locs[i].second;
9807 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9810 if (NumLo == 3 || NumHi == 3) {
9811 // Otherwise, we must have three elements from one vector, call it X, and
9812 // one element from the other, call it Y. First, use a shufps to build an
9813 // intermediate vector with the one element from Y and the element from X
9814 // that will be in the same half in the final destination (the indexes don't
9815 // matter). Then, use a shufps to build the final vector, taking the half
9816 // containing the element from Y from the intermediate, and the other half
9819 // Normalize it so the 3 elements come from V1.
9820 CommuteVectorShuffleMask(PermMask, 4);
9824 // Find the element from V2.
9826 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9827 int Val = PermMask[HiIndex];
9834 Mask1[0] = PermMask[HiIndex];
9836 Mask1[2] = PermMask[HiIndex^1];
9838 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9841 Mask1[0] = PermMask[0];
9842 Mask1[1] = PermMask[1];
9843 Mask1[2] = HiIndex & 1 ? 6 : 4;
9844 Mask1[3] = HiIndex & 1 ? 4 : 6;
9845 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9848 Mask1[0] = HiIndex & 1 ? 2 : 0;
9849 Mask1[1] = HiIndex & 1 ? 0 : 2;
9850 Mask1[2] = PermMask[2];
9851 Mask1[3] = PermMask[3];
9856 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9859 // Break it into (shuffle shuffle_hi, shuffle_lo).
9860 int LoMask[] = { -1, -1, -1, -1 };
9861 int HiMask[] = { -1, -1, -1, -1 };
9863 int *MaskPtr = LoMask;
9864 unsigned MaskIdx = 0;
9867 for (unsigned i = 0; i != 4; ++i) {
9874 int Idx = PermMask[i];
9876 Locs[i] = std::make_pair(-1, -1);
9877 } else if (Idx < 4) {
9878 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9879 MaskPtr[LoIdx] = Idx;
9882 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9883 MaskPtr[HiIdx] = Idx;
9888 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9889 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9890 int MaskOps[] = { -1, -1, -1, -1 };
9891 for (unsigned i = 0; i != 4; ++i)
9892 if (Locs[i].first != -1)
9893 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9894 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9897 static bool MayFoldVectorLoad(SDValue V) {
9898 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9899 V = V.getOperand(0);
9901 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9902 V = V.getOperand(0);
9903 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9904 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9905 // BUILD_VECTOR (load), undef
9906 V = V.getOperand(0);
9908 return MayFoldLoad(V);
9912 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9913 MVT VT = Op.getSimpleValueType();
9915 // Canonizalize to v2f64.
9916 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9917 return DAG.getNode(ISD::BITCAST, dl, VT,
9918 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9923 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9925 SDValue V1 = Op.getOperand(0);
9926 SDValue V2 = Op.getOperand(1);
9927 MVT VT = Op.getSimpleValueType();
9929 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9931 if (HasSSE2 && VT == MVT::v2f64)
9932 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9934 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9935 return DAG.getNode(ISD::BITCAST, dl, VT,
9936 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9937 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9938 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9942 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9943 SDValue V1 = Op.getOperand(0);
9944 SDValue V2 = Op.getOperand(1);
9945 MVT VT = Op.getSimpleValueType();
9947 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9948 "unsupported shuffle type");
9950 if (V2.getOpcode() == ISD::UNDEF)
9954 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9958 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9959 SDValue V1 = Op.getOperand(0);
9960 SDValue V2 = Op.getOperand(1);
9961 MVT VT = Op.getSimpleValueType();
9962 unsigned NumElems = VT.getVectorNumElements();
9964 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9965 // operand of these instructions is only memory, so check if there's a
9966 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9968 bool CanFoldLoad = false;
9970 // Trivial case, when V2 comes from a load.
9971 if (MayFoldVectorLoad(V2))
9974 // When V1 is a load, it can be folded later into a store in isel, example:
9975 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9977 // (MOVLPSmr addr:$src1, VR128:$src2)
9978 // So, recognize this potential and also use MOVLPS or MOVLPD
9979 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9982 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9984 if (HasSSE2 && NumElems == 2)
9985 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9988 // If we don't care about the second element, proceed to use movss.
9989 if (SVOp->getMaskElt(1) != -1)
9990 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9993 // movl and movlp will both match v2i64, but v2i64 is never matched by
9994 // movl earlier because we make it strict to avoid messing with the movlp load
9995 // folding logic (see the code above getMOVLP call). Match it here then,
9996 // this is horrible, but will stay like this until we move all shuffle
9997 // matching to x86 specific nodes. Note that for the 1st condition all
9998 // types are matched with movsd.
10000 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10001 // as to remove this logic from here, as much as possible
10002 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10003 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10004 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10007 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10009 // Invert the operand order and use SHUFPS to match it.
10010 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10011 getShuffleSHUFImmediate(SVOp), DAG);
10014 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10015 SelectionDAG &DAG) {
10017 MVT VT = Load->getSimpleValueType(0);
10018 MVT EVT = VT.getVectorElementType();
10019 SDValue Addr = Load->getOperand(1);
10020 SDValue NewAddr = DAG.getNode(
10021 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10022 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10025 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10026 DAG.getMachineFunction().getMachineMemOperand(
10027 Load->getMemOperand(), 0, EVT.getStoreSize()));
10031 // It is only safe to call this function if isINSERTPSMask is true for
10032 // this shufflevector mask.
10033 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10034 SelectionDAG &DAG) {
10035 // Generate an insertps instruction when inserting an f32 from memory onto a
10036 // v4f32 or when copying a member from one v4f32 to another.
10037 // We also use it for transferring i32 from one register to another,
10038 // since it simply copies the same bits.
10039 // If we're transferring an i32 from memory to a specific element in a
10040 // register, we output a generic DAG that will match the PINSRD
10042 MVT VT = SVOp->getSimpleValueType(0);
10043 MVT EVT = VT.getVectorElementType();
10044 SDValue V1 = SVOp->getOperand(0);
10045 SDValue V2 = SVOp->getOperand(1);
10046 auto Mask = SVOp->getMask();
10047 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10048 "unsupported vector type for insertps/pinsrd");
10050 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10051 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10052 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10056 unsigned DestIndex;
10060 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10063 // If we have 1 element from each vector, we have to check if we're
10064 // changing V1's element's place. If so, we're done. Otherwise, we
10065 // should assume we're changing V2's element's place and behave
10067 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10068 assert(DestIndex <= INT32_MAX && "truncated destination index");
10069 if (FromV1 == FromV2 &&
10070 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10074 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10077 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10078 "More than one element from V1 and from V2, or no elements from one "
10079 "of the vectors. This case should not have returned true from "
10084 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10087 // Get an index into the source vector in the range [0,4) (the mask is
10088 // in the range [0,8) because it can address V1 and V2)
10089 unsigned SrcIndex = Mask[DestIndex] % 4;
10090 if (MayFoldLoad(From)) {
10091 // Trivial case, when From comes from a load and is only used by the
10092 // shuffle. Make it use insertps from the vector that we need from that
10095 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10096 if (!NewLoad.getNode())
10099 if (EVT == MVT::f32) {
10100 // Create this as a scalar to vector to match the instruction pattern.
10101 SDValue LoadScalarToVector =
10102 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10103 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10104 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10106 } else { // EVT == MVT::i32
10107 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10108 // instruction, to match the PINSRD instruction, which loads an i32 to a
10109 // certain vector element.
10110 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10111 DAG.getConstant(DestIndex, MVT::i32));
10115 // Vector-element-to-vector
10116 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10117 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10120 // Reduce a vector shuffle to zext.
10121 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10122 SelectionDAG &DAG) {
10123 // PMOVZX is only available from SSE41.
10124 if (!Subtarget->hasSSE41())
10127 MVT VT = Op.getSimpleValueType();
10129 // Only AVX2 support 256-bit vector integer extending.
10130 if (!Subtarget->hasInt256() && VT.is256BitVector())
10133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10135 SDValue V1 = Op.getOperand(0);
10136 SDValue V2 = Op.getOperand(1);
10137 unsigned NumElems = VT.getVectorNumElements();
10139 // Extending is an unary operation and the element type of the source vector
10140 // won't be equal to or larger than i64.
10141 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10142 VT.getVectorElementType() == MVT::i64)
10145 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10146 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10147 while ((1U << Shift) < NumElems) {
10148 if (SVOp->getMaskElt(1U << Shift) == 1)
10151 // The maximal ratio is 8, i.e. from i8 to i64.
10156 // Check the shuffle mask.
10157 unsigned Mask = (1U << Shift) - 1;
10158 for (unsigned i = 0; i != NumElems; ++i) {
10159 int EltIdx = SVOp->getMaskElt(i);
10160 if ((i & Mask) != 0 && EltIdx != -1)
10162 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10166 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10167 MVT NeVT = MVT::getIntegerVT(NBits);
10168 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10170 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10173 // Simplify the operand as it's prepared to be fed into shuffle.
10174 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10175 if (V1.getOpcode() == ISD::BITCAST &&
10176 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10177 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10178 V1.getOperand(0).getOperand(0)
10179 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10180 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10181 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10182 ConstantSDNode *CIdx =
10183 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10184 // If it's foldable, i.e. normal load with single use, we will let code
10185 // selection to fold it. Otherwise, we will short the conversion sequence.
10186 if (CIdx && CIdx->getZExtValue() == 0 &&
10187 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10188 MVT FullVT = V.getSimpleValueType();
10189 MVT V1VT = V1.getSimpleValueType();
10190 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10191 // The "ext_vec_elt" node is wider than the result node.
10192 // In this case we should extract subvector from V.
10193 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10194 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10195 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10196 FullVT.getVectorNumElements()/Ratio);
10197 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10198 DAG.getIntPtrConstant(0));
10200 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10204 return DAG.getNode(ISD::BITCAST, DL, VT,
10205 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10208 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10209 SelectionDAG &DAG) {
10210 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10211 MVT VT = Op.getSimpleValueType();
10213 SDValue V1 = Op.getOperand(0);
10214 SDValue V2 = Op.getOperand(1);
10216 if (isZeroShuffle(SVOp))
10217 return getZeroVector(VT, Subtarget, DAG, dl);
10219 // Handle splat operations
10220 if (SVOp->isSplat()) {
10221 // Use vbroadcast whenever the splat comes from a foldable load
10222 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10223 if (Broadcast.getNode())
10227 // Check integer expanding shuffles.
10228 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10229 if (NewOp.getNode())
10232 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10234 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10235 VT == MVT::v32i8) {
10236 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10237 if (NewOp.getNode())
10238 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10239 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10240 // FIXME: Figure out a cleaner way to do this.
10241 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10242 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10243 if (NewOp.getNode()) {
10244 MVT NewVT = NewOp.getSimpleValueType();
10245 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10246 NewVT, true, false))
10247 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10250 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10251 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10252 if (NewOp.getNode()) {
10253 MVT NewVT = NewOp.getSimpleValueType();
10254 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10255 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10264 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10265 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10266 SDValue V1 = Op.getOperand(0);
10267 SDValue V2 = Op.getOperand(1);
10268 MVT VT = Op.getSimpleValueType();
10270 unsigned NumElems = VT.getVectorNumElements();
10271 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10272 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10273 bool V1IsSplat = false;
10274 bool V2IsSplat = false;
10275 bool HasSSE2 = Subtarget->hasSSE2();
10276 bool HasFp256 = Subtarget->hasFp256();
10277 bool HasInt256 = Subtarget->hasInt256();
10278 MachineFunction &MF = DAG.getMachineFunction();
10279 bool OptForSize = MF.getFunction()->getAttributes().
10280 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10282 // Check if we should use the experimental vector shuffle lowering. If so,
10283 // delegate completely to that code path.
10284 if (ExperimentalVectorShuffleLowering)
10285 return lowerVectorShuffle(Op, Subtarget, DAG);
10287 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10289 if (V1IsUndef && V2IsUndef)
10290 return DAG.getUNDEF(VT);
10292 // When we create a shuffle node we put the UNDEF node to second operand,
10293 // but in some cases the first operand may be transformed to UNDEF.
10294 // In this case we should just commute the node.
10296 return DAG.getCommutedVectorShuffle(*SVOp);
10298 // Vector shuffle lowering takes 3 steps:
10300 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10301 // narrowing and commutation of operands should be handled.
10302 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10304 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10305 // so the shuffle can be broken into other shuffles and the legalizer can
10306 // try the lowering again.
10308 // The general idea is that no vector_shuffle operation should be left to
10309 // be matched during isel, all of them must be converted to a target specific
10312 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10313 // narrowing and commutation of operands should be handled. The actual code
10314 // doesn't include all of those, work in progress...
10315 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10316 if (NewOp.getNode())
10319 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10321 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10322 // unpckh_undef). Only use pshufd if speed is more important than size.
10323 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10324 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10325 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10326 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10328 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10329 V2IsUndef && MayFoldVectorLoad(V1))
10330 return getMOVDDup(Op, dl, V1, DAG);
10332 if (isMOVHLPS_v_undef_Mask(M, VT))
10333 return getMOVHighToLow(Op, dl, DAG);
10335 // Use to match splats
10336 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10337 (VT == MVT::v2f64 || VT == MVT::v2i64))
10338 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10340 if (isPSHUFDMask(M, VT)) {
10341 // The actual implementation will match the mask in the if above and then
10342 // during isel it can match several different instructions, not only pshufd
10343 // as its name says, sad but true, emulate the behavior for now...
10344 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
10345 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
10347 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
10349 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
10350 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
10352 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
10353 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
10356 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10360 if (isPALIGNRMask(M, VT, Subtarget))
10361 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10362 getShufflePALIGNRImmediate(SVOp),
10365 if (isVALIGNMask(M, VT, Subtarget))
10366 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10367 getShuffleVALIGNImmediate(SVOp),
10370 // Check if this can be converted into a logical shift.
10371 bool isLeft = false;
10372 unsigned ShAmt = 0;
10374 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10375 if (isShift && ShVal.hasOneUse()) {
10376 // If the shifted value has multiple uses, it may be cheaper to use
10377 // v_set0 + movlhps or movhlps, etc.
10378 MVT EltVT = VT.getVectorElementType();
10379 ShAmt *= EltVT.getSizeInBits();
10380 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10383 if (isMOVLMask(M, VT)) {
10384 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10385 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10386 if (!isMOVLPMask(M, VT)) {
10387 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10388 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10390 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10391 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10395 // FIXME: fold these into legal mask.
10396 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10397 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10399 if (isMOVHLPSMask(M, VT))
10400 return getMOVHighToLow(Op, dl, DAG);
10402 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10403 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10405 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10406 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10408 if (isMOVLPMask(M, VT))
10409 return getMOVLP(Op, dl, DAG, HasSSE2);
10411 if (ShouldXformToMOVHLPS(M, VT) ||
10412 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10413 return DAG.getCommutedVectorShuffle(*SVOp);
10416 // No better options. Use a vshldq / vsrldq.
10417 MVT EltVT = VT.getVectorElementType();
10418 ShAmt *= EltVT.getSizeInBits();
10419 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10422 bool Commuted = false;
10423 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10424 // 1,1,1,1 -> v8i16 though.
10425 BitVector UndefElements;
10426 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10427 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10429 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10430 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10433 // Canonicalize the splat or undef, if present, to be on the RHS.
10434 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10435 CommuteVectorShuffleMask(M, NumElems);
10437 std::swap(V1IsSplat, V2IsSplat);
10441 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10442 // Shuffling low element of v1 into undef, just return v1.
10445 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10446 // the instruction selector will not match, so get a canonical MOVL with
10447 // swapped operands to undo the commute.
10448 return getMOVL(DAG, dl, VT, V2, V1);
10451 if (isUNPCKLMask(M, VT, HasInt256))
10452 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10454 if (isUNPCKHMask(M, VT, HasInt256))
10455 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10458 // Normalize mask so all entries that point to V2 points to its first
10459 // element then try to match unpck{h|l} again. If match, return a
10460 // new vector_shuffle with the corrected mask.p
10461 SmallVector<int, 8> NewMask(M.begin(), M.end());
10462 NormalizeMask(NewMask, NumElems);
10463 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10464 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10465 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10466 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10470 // Commute is back and try unpck* again.
10471 // FIXME: this seems wrong.
10472 CommuteVectorShuffleMask(M, NumElems);
10474 std::swap(V1IsSplat, V2IsSplat);
10476 if (isUNPCKLMask(M, VT, HasInt256))
10477 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10479 if (isUNPCKHMask(M, VT, HasInt256))
10480 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10483 // Normalize the node to match x86 shuffle ops if needed
10484 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10485 return DAG.getCommutedVectorShuffle(*SVOp);
10487 // The checks below are all present in isShuffleMaskLegal, but they are
10488 // inlined here right now to enable us to directly emit target specific
10489 // nodes, and remove one by one until they don't return Op anymore.
10491 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10492 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10493 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10494 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10497 if (isPSHUFHWMask(M, VT, HasInt256))
10498 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10499 getShufflePSHUFHWImmediate(SVOp),
10502 if (isPSHUFLWMask(M, VT, HasInt256))
10503 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10504 getShufflePSHUFLWImmediate(SVOp),
10507 unsigned MaskValue;
10508 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10510 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10512 if (isSHUFPMask(M, VT))
10513 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10514 getShuffleSHUFImmediate(SVOp), DAG);
10516 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10517 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10518 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10519 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10521 //===--------------------------------------------------------------------===//
10522 // Generate target specific nodes for 128 or 256-bit shuffles only
10523 // supported in the AVX instruction set.
10526 // Handle VMOVDDUPY permutations
10527 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10528 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10530 // Handle VPERMILPS/D* permutations
10531 if (isVPERMILPMask(M, VT)) {
10532 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10533 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10534 getShuffleSHUFImmediate(SVOp), DAG);
10535 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10536 getShuffleSHUFImmediate(SVOp), DAG);
10540 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10541 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10542 Idx*(NumElems/2), DAG, dl);
10544 // Handle VPERM2F128/VPERM2I128 permutations
10545 if (isVPERM2X128Mask(M, VT, HasFp256))
10546 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10547 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10549 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10550 return getINSERTPS(SVOp, dl, DAG);
10553 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10554 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10556 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10557 VT.is512BitVector()) {
10558 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10559 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10560 SmallVector<SDValue, 16> permclMask;
10561 for (unsigned i = 0; i != NumElems; ++i) {
10562 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10565 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10567 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10568 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10569 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
10570 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
10571 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
10574 //===--------------------------------------------------------------------===//
10575 // Since no target specific shuffle was selected for this generic one,
10576 // lower it into other known shuffles. FIXME: this isn't true yet, but
10577 // this is the plan.
10580 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
10581 if (VT == MVT::v8i16) {
10582 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
10583 if (NewOp.getNode())
10587 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
10588 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
10589 if (NewOp.getNode())
10593 if (VT == MVT::v16i8) {
10594 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
10595 if (NewOp.getNode())
10599 if (VT == MVT::v32i8) {
10600 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
10601 if (NewOp.getNode())
10605 // Handle all 128-bit wide vectors with 4 elements, and match them with
10606 // several different shuffle types.
10607 if (NumElems == 4 && VT.is128BitVector())
10608 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
10610 // Handle general 256-bit shuffles
10611 if (VT.is256BitVector())
10612 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
10617 // This function assumes its argument is a BUILD_VECTOR of constants or
10618 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10620 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10621 unsigned &MaskValue) {
10623 unsigned NumElems = BuildVector->getNumOperands();
10624 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10625 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10626 unsigned NumElemsInLane = NumElems / NumLanes;
10628 // Blend for v16i16 should be symetric for the both lanes.
10629 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10630 SDValue EltCond = BuildVector->getOperand(i);
10631 SDValue SndLaneEltCond =
10632 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10634 int Lane1Cond = -1, Lane2Cond = -1;
10635 if (isa<ConstantSDNode>(EltCond))
10636 Lane1Cond = !isZero(EltCond);
10637 if (isa<ConstantSDNode>(SndLaneEltCond))
10638 Lane2Cond = !isZero(SndLaneEltCond);
10640 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10641 // Lane1Cond != 0, means we want the first argument.
10642 // Lane1Cond == 0, means we want the second argument.
10643 // The encoding of this argument is 0 for the first argument, 1
10644 // for the second. Therefore, invert the condition.
10645 MaskValue |= !Lane1Cond << i;
10646 else if (Lane1Cond < 0)
10647 MaskValue |= !Lane2Cond << i;
10654 // Try to lower a vselect node into a simple blend instruction.
10655 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
10656 SelectionDAG &DAG) {
10657 SDValue Cond = Op.getOperand(0);
10658 SDValue LHS = Op.getOperand(1);
10659 SDValue RHS = Op.getOperand(2);
10661 MVT VT = Op.getSimpleValueType();
10662 MVT EltVT = VT.getVectorElementType();
10663 unsigned NumElems = VT.getVectorNumElements();
10665 // There is no blend with immediate in AVX-512.
10666 if (VT.is512BitVector())
10669 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
10671 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
10674 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10677 // Check the mask for BLEND and build the value.
10678 unsigned MaskValue = 0;
10679 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
10682 // Convert i32 vectors to floating point if it is not AVX2.
10683 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10685 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10686 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10688 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
10689 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
10692 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
10693 DAG.getConstant(MaskValue, MVT::i32));
10694 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10697 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10698 // A vselect where all conditions and data are constants can be optimized into
10699 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10700 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10701 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10702 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10705 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
10706 if (BlendOp.getNode())
10709 // Some types for vselect were previously set to Expand, not Legal or
10710 // Custom. Return an empty SDValue so we fall-through to Expand, after
10711 // the Custom lowering phase.
10712 MVT VT = Op.getSimpleValueType();
10713 switch (VT.SimpleTy) {
10718 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10723 // We couldn't create a "Blend with immediate" node.
10724 // This node should still be legal, but we'll have to emit a blendv*
10729 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10730 MVT VT = Op.getSimpleValueType();
10733 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10736 if (VT.getSizeInBits() == 8) {
10737 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10738 Op.getOperand(0), Op.getOperand(1));
10739 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10740 DAG.getValueType(VT));
10741 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10744 if (VT.getSizeInBits() == 16) {
10745 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10746 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10748 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10749 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10750 DAG.getNode(ISD::BITCAST, dl,
10753 Op.getOperand(1)));
10754 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10755 Op.getOperand(0), Op.getOperand(1));
10756 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10757 DAG.getValueType(VT));
10758 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10761 if (VT == MVT::f32) {
10762 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10763 // the result back to FR32 register. It's only worth matching if the
10764 // result has a single use which is a store or a bitcast to i32. And in
10765 // the case of a store, it's not worth it if the index is a constant 0,
10766 // because a MOVSSmr can be used instead, which is smaller and faster.
10767 if (!Op.hasOneUse())
10769 SDNode *User = *Op.getNode()->use_begin();
10770 if ((User->getOpcode() != ISD::STORE ||
10771 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10772 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10773 (User->getOpcode() != ISD::BITCAST ||
10774 User->getValueType(0) != MVT::i32))
10776 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10777 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10780 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10783 if (VT == MVT::i32 || VT == MVT::i64) {
10784 // ExtractPS/pextrq works with constant index.
10785 if (isa<ConstantSDNode>(Op.getOperand(1)))
10791 /// Extract one bit from mask vector, like v16i1 or v8i1.
10792 /// AVX-512 feature.
10794 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10795 SDValue Vec = Op.getOperand(0);
10797 MVT VecVT = Vec.getSimpleValueType();
10798 SDValue Idx = Op.getOperand(1);
10799 MVT EltVT = Op.getSimpleValueType();
10801 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10803 // variable index can't be handled in mask registers,
10804 // extend vector to VR512
10805 if (!isa<ConstantSDNode>(Idx)) {
10806 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10807 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10808 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10809 ExtVT.getVectorElementType(), Ext, Idx);
10810 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10813 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10814 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10815 unsigned MaxSift = rc->getSize()*8 - 1;
10816 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10817 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10818 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10819 DAG.getConstant(MaxSift, MVT::i8));
10820 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10821 DAG.getIntPtrConstant(0));
10825 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10826 SelectionDAG &DAG) const {
10828 SDValue Vec = Op.getOperand(0);
10829 MVT VecVT = Vec.getSimpleValueType();
10830 SDValue Idx = Op.getOperand(1);
10832 if (Op.getSimpleValueType() == MVT::i1)
10833 return ExtractBitFromMaskVector(Op, DAG);
10835 if (!isa<ConstantSDNode>(Idx)) {
10836 if (VecVT.is512BitVector() ||
10837 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10838 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10841 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10842 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10843 MaskEltVT.getSizeInBits());
10845 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10846 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10847 getZeroVector(MaskVT, Subtarget, DAG, dl),
10848 Idx, DAG.getConstant(0, getPointerTy()));
10849 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10850 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10851 Perm, DAG.getConstant(0, getPointerTy()));
10856 // If this is a 256-bit vector result, first extract the 128-bit vector and
10857 // then extract the element from the 128-bit vector.
10858 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10860 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10861 // Get the 128-bit vector.
10862 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10863 MVT EltVT = VecVT.getVectorElementType();
10865 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10867 //if (IdxVal >= NumElems/2)
10868 // IdxVal -= NumElems/2;
10869 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10870 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10871 DAG.getConstant(IdxVal, MVT::i32));
10874 assert(VecVT.is128BitVector() && "Unexpected vector length");
10876 if (Subtarget->hasSSE41()) {
10877 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10882 MVT VT = Op.getSimpleValueType();
10883 // TODO: handle v16i8.
10884 if (VT.getSizeInBits() == 16) {
10885 SDValue Vec = Op.getOperand(0);
10886 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10888 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10889 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10890 DAG.getNode(ISD::BITCAST, dl,
10892 Op.getOperand(1)));
10893 // Transform it so it match pextrw which produces a 32-bit result.
10894 MVT EltVT = MVT::i32;
10895 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10896 Op.getOperand(0), Op.getOperand(1));
10897 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10898 DAG.getValueType(VT));
10899 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10902 if (VT.getSizeInBits() == 32) {
10903 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10907 // SHUFPS the element to the lowest double word, then movss.
10908 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10909 MVT VVT = Op.getOperand(0).getSimpleValueType();
10910 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10911 DAG.getUNDEF(VVT), Mask);
10912 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10913 DAG.getIntPtrConstant(0));
10916 if (VT.getSizeInBits() == 64) {
10917 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10918 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10919 // to match extract_elt for f64.
10920 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10924 // UNPCKHPD the element to the lowest double word, then movsd.
10925 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10926 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10927 int Mask[2] = { 1, -1 };
10928 MVT VVT = Op.getOperand(0).getSimpleValueType();
10929 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10930 DAG.getUNDEF(VVT), Mask);
10931 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10932 DAG.getIntPtrConstant(0));
10938 /// Insert one bit to mask vector, like v16i1 or v8i1.
10939 /// AVX-512 feature.
10941 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10943 SDValue Vec = Op.getOperand(0);
10944 SDValue Elt = Op.getOperand(1);
10945 SDValue Idx = Op.getOperand(2);
10946 MVT VecVT = Vec.getSimpleValueType();
10948 if (!isa<ConstantSDNode>(Idx)) {
10949 // Non constant index. Extend source and destination,
10950 // insert element and then truncate the result.
10951 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10952 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10953 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10954 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10955 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10956 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10959 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10960 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10961 if (Vec.getOpcode() == ISD::UNDEF)
10962 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10963 DAG.getConstant(IdxVal, MVT::i8));
10964 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10965 unsigned MaxSift = rc->getSize()*8 - 1;
10966 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10967 DAG.getConstant(MaxSift, MVT::i8));
10968 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10969 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10970 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10973 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10974 SelectionDAG &DAG) const {
10975 MVT VT = Op.getSimpleValueType();
10976 MVT EltVT = VT.getVectorElementType();
10978 if (EltVT == MVT::i1)
10979 return InsertBitToMaskVector(Op, DAG);
10982 SDValue N0 = Op.getOperand(0);
10983 SDValue N1 = Op.getOperand(1);
10984 SDValue N2 = Op.getOperand(2);
10985 if (!isa<ConstantSDNode>(N2))
10987 auto *N2C = cast<ConstantSDNode>(N2);
10988 unsigned IdxVal = N2C->getZExtValue();
10990 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10991 // into that, and then insert the subvector back into the result.
10992 if (VT.is256BitVector() || VT.is512BitVector()) {
10993 // Get the desired 128-bit vector half.
10994 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10996 // Insert the element into the desired half.
10997 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10998 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11000 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11001 DAG.getConstant(IdxIn128, MVT::i32));
11003 // Insert the changed part back to the 256-bit vector
11004 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11006 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11008 if (Subtarget->hasSSE41()) {
11009 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11011 if (VT == MVT::v8i16) {
11012 Opc = X86ISD::PINSRW;
11014 assert(VT == MVT::v16i8);
11015 Opc = X86ISD::PINSRB;
11018 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11020 if (N1.getValueType() != MVT::i32)
11021 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11022 if (N2.getValueType() != MVT::i32)
11023 N2 = DAG.getIntPtrConstant(IdxVal);
11024 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11027 if (EltVT == MVT::f32) {
11028 // Bits [7:6] of the constant are the source select. This will always be
11029 // zero here. The DAG Combiner may combine an extract_elt index into
11031 // bits. For example (insert (extract, 3), 2) could be matched by
11033 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11034 // Bits [5:4] of the constant are the destination select. This is the
11035 // value of the incoming immediate.
11036 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11037 // combine either bitwise AND or insert of float 0.0 to set these bits.
11038 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11039 // Create this as a scalar to vector..
11040 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11041 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11044 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11045 // PINSR* works with constant index.
11050 if (EltVT == MVT::i8)
11053 if (EltVT.getSizeInBits() == 16) {
11054 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11055 // as its second argument.
11056 if (N1.getValueType() != MVT::i32)
11057 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11058 if (N2.getValueType() != MVT::i32)
11059 N2 = DAG.getIntPtrConstant(IdxVal);
11060 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11065 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11067 MVT OpVT = Op.getSimpleValueType();
11069 // If this is a 256-bit vector result, first insert into a 128-bit
11070 // vector and then insert into the 256-bit vector.
11071 if (!OpVT.is128BitVector()) {
11072 // Insert into a 128-bit vector.
11073 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11074 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11075 OpVT.getVectorNumElements() / SizeFactor);
11077 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11079 // Insert the 128-bit vector.
11080 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11083 if (OpVT == MVT::v1i64 &&
11084 Op.getOperand(0).getValueType() == MVT::i64)
11085 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11087 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11088 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11089 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11090 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11093 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11094 // a simple subregister reference or explicit instructions to grab
11095 // upper bits of a vector.
11096 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11097 SelectionDAG &DAG) {
11099 SDValue In = Op.getOperand(0);
11100 SDValue Idx = Op.getOperand(1);
11101 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11102 MVT ResVT = Op.getSimpleValueType();
11103 MVT InVT = In.getSimpleValueType();
11105 if (Subtarget->hasFp256()) {
11106 if (ResVT.is128BitVector() &&
11107 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11108 isa<ConstantSDNode>(Idx)) {
11109 return Extract128BitVector(In, IdxVal, DAG, dl);
11111 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11112 isa<ConstantSDNode>(Idx)) {
11113 return Extract256BitVector(In, IdxVal, DAG, dl);
11119 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11120 // simple superregister reference or explicit instructions to insert
11121 // the upper bits of a vector.
11122 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11123 SelectionDAG &DAG) {
11124 if (Subtarget->hasFp256()) {
11125 SDLoc dl(Op.getNode());
11126 SDValue Vec = Op.getNode()->getOperand(0);
11127 SDValue SubVec = Op.getNode()->getOperand(1);
11128 SDValue Idx = Op.getNode()->getOperand(2);
11130 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11131 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11132 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11133 isa<ConstantSDNode>(Idx)) {
11134 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11135 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11138 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11139 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11140 isa<ConstantSDNode>(Idx)) {
11141 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11142 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11148 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11149 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11150 // one of the above mentioned nodes. It has to be wrapped because otherwise
11151 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11152 // be used to form addressing mode. These wrapped nodes will be selected
11155 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11156 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11158 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11159 // global base reg.
11160 unsigned char OpFlag = 0;
11161 unsigned WrapperKind = X86ISD::Wrapper;
11162 CodeModel::Model M = DAG.getTarget().getCodeModel();
11164 if (Subtarget->isPICStyleRIPRel() &&
11165 (M == CodeModel::Small || M == CodeModel::Kernel))
11166 WrapperKind = X86ISD::WrapperRIP;
11167 else if (Subtarget->isPICStyleGOT())
11168 OpFlag = X86II::MO_GOTOFF;
11169 else if (Subtarget->isPICStyleStubPIC())
11170 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11172 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11173 CP->getAlignment(),
11174 CP->getOffset(), OpFlag);
11176 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11177 // With PIC, the address is actually $g + Offset.
11179 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11180 DAG.getNode(X86ISD::GlobalBaseReg,
11181 SDLoc(), getPointerTy()),
11188 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11189 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11191 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11192 // global base reg.
11193 unsigned char OpFlag = 0;
11194 unsigned WrapperKind = X86ISD::Wrapper;
11195 CodeModel::Model M = DAG.getTarget().getCodeModel();
11197 if (Subtarget->isPICStyleRIPRel() &&
11198 (M == CodeModel::Small || M == CodeModel::Kernel))
11199 WrapperKind = X86ISD::WrapperRIP;
11200 else if (Subtarget->isPICStyleGOT())
11201 OpFlag = X86II::MO_GOTOFF;
11202 else if (Subtarget->isPICStyleStubPIC())
11203 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11205 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11208 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11210 // With PIC, the address is actually $g + Offset.
11212 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11213 DAG.getNode(X86ISD::GlobalBaseReg,
11214 SDLoc(), getPointerTy()),
11221 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11222 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11224 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11225 // global base reg.
11226 unsigned char OpFlag = 0;
11227 unsigned WrapperKind = X86ISD::Wrapper;
11228 CodeModel::Model M = DAG.getTarget().getCodeModel();
11230 if (Subtarget->isPICStyleRIPRel() &&
11231 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11232 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11233 OpFlag = X86II::MO_GOTPCREL;
11234 WrapperKind = X86ISD::WrapperRIP;
11235 } else if (Subtarget->isPICStyleGOT()) {
11236 OpFlag = X86II::MO_GOT;
11237 } else if (Subtarget->isPICStyleStubPIC()) {
11238 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11239 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11240 OpFlag = X86II::MO_DARWIN_NONLAZY;
11243 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11246 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11248 // With PIC, the address is actually $g + Offset.
11249 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11250 !Subtarget->is64Bit()) {
11251 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11252 DAG.getNode(X86ISD::GlobalBaseReg,
11253 SDLoc(), getPointerTy()),
11257 // For symbols that require a load from a stub to get the address, emit the
11259 if (isGlobalStubReference(OpFlag))
11260 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11261 MachinePointerInfo::getGOT(), false, false, false, 0);
11267 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11268 // Create the TargetBlockAddressAddress node.
11269 unsigned char OpFlags =
11270 Subtarget->ClassifyBlockAddressReference();
11271 CodeModel::Model M = DAG.getTarget().getCodeModel();
11272 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11273 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11275 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11278 if (Subtarget->isPICStyleRIPRel() &&
11279 (M == CodeModel::Small || M == CodeModel::Kernel))
11280 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11282 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11284 // With PIC, the address is actually $g + Offset.
11285 if (isGlobalRelativeToPICBase(OpFlags)) {
11286 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11287 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11295 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11296 int64_t Offset, SelectionDAG &DAG) const {
11297 // Create the TargetGlobalAddress node, folding in the constant
11298 // offset if it is legal.
11299 unsigned char OpFlags =
11300 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11301 CodeModel::Model M = DAG.getTarget().getCodeModel();
11303 if (OpFlags == X86II::MO_NO_FLAG &&
11304 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11305 // A direct static reference to a global.
11306 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11309 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11312 if (Subtarget->isPICStyleRIPRel() &&
11313 (M == CodeModel::Small || M == CodeModel::Kernel))
11314 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11316 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11318 // With PIC, the address is actually $g + Offset.
11319 if (isGlobalRelativeToPICBase(OpFlags)) {
11320 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11321 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11325 // For globals that require a load from a stub to get the address, emit the
11327 if (isGlobalStubReference(OpFlags))
11328 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11329 MachinePointerInfo::getGOT(), false, false, false, 0);
11331 // If there was a non-zero offset that we didn't fold, create an explicit
11332 // addition for it.
11334 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11335 DAG.getConstant(Offset, getPointerTy()));
11341 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11342 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11343 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11344 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11348 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11349 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11350 unsigned char OperandFlags, bool LocalDynamic = false) {
11351 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11352 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11354 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11355 GA->getValueType(0),
11359 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11363 SDValue Ops[] = { Chain, TGA, *InFlag };
11364 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11366 SDValue Ops[] = { Chain, TGA };
11367 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11370 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11371 MFI->setAdjustsStack(true);
11373 SDValue Flag = Chain.getValue(1);
11374 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11377 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11379 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11382 SDLoc dl(GA); // ? function entry point might be better
11383 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11384 DAG.getNode(X86ISD::GlobalBaseReg,
11385 SDLoc(), PtrVT), InFlag);
11386 InFlag = Chain.getValue(1);
11388 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11391 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11393 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11395 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11396 X86::RAX, X86II::MO_TLSGD);
11399 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11405 // Get the start address of the TLS block for this module.
11406 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11407 .getInfo<X86MachineFunctionInfo>();
11408 MFI->incNumLocalDynamicTLSAccesses();
11412 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11413 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11416 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11417 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11418 InFlag = Chain.getValue(1);
11419 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11420 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11423 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11427 unsigned char OperandFlags = X86II::MO_DTPOFF;
11428 unsigned WrapperKind = X86ISD::Wrapper;
11429 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11430 GA->getValueType(0),
11431 GA->getOffset(), OperandFlags);
11432 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11434 // Add x@dtpoff with the base.
11435 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11438 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11439 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11440 const EVT PtrVT, TLSModel::Model model,
11441 bool is64Bit, bool isPIC) {
11444 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11445 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11446 is64Bit ? 257 : 256));
11448 SDValue ThreadPointer =
11449 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11450 MachinePointerInfo(Ptr), false, false, false, 0);
11452 unsigned char OperandFlags = 0;
11453 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11455 unsigned WrapperKind = X86ISD::Wrapper;
11456 if (model == TLSModel::LocalExec) {
11457 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11458 } else if (model == TLSModel::InitialExec) {
11460 OperandFlags = X86II::MO_GOTTPOFF;
11461 WrapperKind = X86ISD::WrapperRIP;
11463 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11466 llvm_unreachable("Unexpected model");
11469 // emit "addl x@ntpoff,%eax" (local exec)
11470 // or "addl x@indntpoff,%eax" (initial exec)
11471 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11473 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11474 GA->getOffset(), OperandFlags);
11475 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11477 if (model == TLSModel::InitialExec) {
11478 if (isPIC && !is64Bit) {
11479 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11480 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11484 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11485 MachinePointerInfo::getGOT(), false, false, false, 0);
11488 // The address of the thread local variable is the add of the thread
11489 // pointer with the offset of the variable.
11490 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11494 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11496 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11497 const GlobalValue *GV = GA->getGlobal();
11499 if (Subtarget->isTargetELF()) {
11500 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11503 case TLSModel::GeneralDynamic:
11504 if (Subtarget->is64Bit())
11505 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11506 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11507 case TLSModel::LocalDynamic:
11508 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11509 Subtarget->is64Bit());
11510 case TLSModel::InitialExec:
11511 case TLSModel::LocalExec:
11512 return LowerToTLSExecModel(
11513 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11514 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11516 llvm_unreachable("Unknown TLS model.");
11519 if (Subtarget->isTargetDarwin()) {
11520 // Darwin only has one model of TLS. Lower to that.
11521 unsigned char OpFlag = 0;
11522 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11523 X86ISD::WrapperRIP : X86ISD::Wrapper;
11525 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11526 // global base reg.
11527 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11528 !Subtarget->is64Bit();
11530 OpFlag = X86II::MO_TLVP_PIC_BASE;
11532 OpFlag = X86II::MO_TLVP;
11534 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11535 GA->getValueType(0),
11536 GA->getOffset(), OpFlag);
11537 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11539 // With PIC32, the address is actually $g + Offset.
11541 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11542 DAG.getNode(X86ISD::GlobalBaseReg,
11543 SDLoc(), getPointerTy()),
11546 // Lowering the machine isd will make sure everything is in the right
11548 SDValue Chain = DAG.getEntryNode();
11549 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11550 SDValue Args[] = { Chain, Offset };
11551 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11553 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11554 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11555 MFI->setAdjustsStack(true);
11557 // And our return value (tls address) is in the standard call return value
11559 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11560 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11561 Chain.getValue(1));
11564 if (Subtarget->isTargetKnownWindowsMSVC() ||
11565 Subtarget->isTargetWindowsGNU()) {
11566 // Just use the implicit TLS architecture
11567 // Need to generate someting similar to:
11568 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11570 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11571 // mov rcx, qword [rdx+rcx*8]
11572 // mov eax, .tls$:tlsvar
11573 // [rax+rcx] contains the address
11574 // Windows 64bit: gs:0x58
11575 // Windows 32bit: fs:__tls_array
11578 SDValue Chain = DAG.getEntryNode();
11580 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11581 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11582 // use its literal value of 0x2C.
11583 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11584 ? Type::getInt8PtrTy(*DAG.getContext(),
11586 : Type::getInt32PtrTy(*DAG.getContext(),
11590 Subtarget->is64Bit()
11591 ? DAG.getIntPtrConstant(0x58)
11592 : (Subtarget->isTargetWindowsGNU()
11593 ? DAG.getIntPtrConstant(0x2C)
11594 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11596 SDValue ThreadPointer =
11597 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11598 MachinePointerInfo(Ptr), false, false, false, 0);
11600 // Load the _tls_index variable
11601 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11602 if (Subtarget->is64Bit())
11603 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11604 IDX, MachinePointerInfo(), MVT::i32,
11605 false, false, false, 0);
11607 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11608 false, false, false, 0);
11610 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11612 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11614 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11615 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11616 false, false, false, 0);
11618 // Get the offset of start of .tls section
11619 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11620 GA->getValueType(0),
11621 GA->getOffset(), X86II::MO_SECREL);
11622 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11624 // The address of the thread local variable is the add of the thread
11625 // pointer with the offset of the variable.
11626 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11629 llvm_unreachable("TLS not implemented for this target.");
11632 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11633 /// and take a 2 x i32 value to shift plus a shift amount.
11634 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11635 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11636 MVT VT = Op.getSimpleValueType();
11637 unsigned VTBits = VT.getSizeInBits();
11639 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11640 SDValue ShOpLo = Op.getOperand(0);
11641 SDValue ShOpHi = Op.getOperand(1);
11642 SDValue ShAmt = Op.getOperand(2);
11643 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11644 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11646 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11647 DAG.getConstant(VTBits - 1, MVT::i8));
11648 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11649 DAG.getConstant(VTBits - 1, MVT::i8))
11650 : DAG.getConstant(0, VT);
11652 SDValue Tmp2, Tmp3;
11653 if (Op.getOpcode() == ISD::SHL_PARTS) {
11654 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11655 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11657 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11658 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11661 // If the shift amount is larger or equal than the width of a part we can't
11662 // rely on the results of shld/shrd. Insert a test and select the appropriate
11663 // values for large shift amounts.
11664 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11665 DAG.getConstant(VTBits, MVT::i8));
11666 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11667 AndNode, DAG.getConstant(0, MVT::i8));
11670 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11671 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11672 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11674 if (Op.getOpcode() == ISD::SHL_PARTS) {
11675 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11676 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11678 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11679 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11682 SDValue Ops[2] = { Lo, Hi };
11683 return DAG.getMergeValues(Ops, dl);
11686 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11687 SelectionDAG &DAG) const {
11688 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11690 if (SrcVT.isVector())
11693 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11694 "Unknown SINT_TO_FP to lower!");
11696 // These are really Legal; return the operand so the caller accepts it as
11698 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11700 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11701 Subtarget->is64Bit()) {
11706 unsigned Size = SrcVT.getSizeInBits()/8;
11707 MachineFunction &MF = DAG.getMachineFunction();
11708 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11709 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11710 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11712 MachinePointerInfo::getFixedStack(SSFI),
11714 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11717 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11719 SelectionDAG &DAG) const {
11723 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11725 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11727 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11729 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11731 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11732 MachineMemOperand *MMO;
11734 int SSFI = FI->getIndex();
11736 DAG.getMachineFunction()
11737 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11738 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11740 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11741 StackSlot = StackSlot.getOperand(1);
11743 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11744 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11746 Tys, Ops, SrcVT, MMO);
11749 Chain = Result.getValue(1);
11750 SDValue InFlag = Result.getValue(2);
11752 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11753 // shouldn't be necessary except that RFP cannot be live across
11754 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11755 MachineFunction &MF = DAG.getMachineFunction();
11756 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11757 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11758 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11759 Tys = DAG.getVTList(MVT::Other);
11761 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11763 MachineMemOperand *MMO =
11764 DAG.getMachineFunction()
11765 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11766 MachineMemOperand::MOStore, SSFISize, SSFISize);
11768 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11769 Ops, Op.getValueType(), MMO);
11770 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11771 MachinePointerInfo::getFixedStack(SSFI),
11772 false, false, false, 0);
11778 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11779 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11780 SelectionDAG &DAG) const {
11781 // This algorithm is not obvious. Here it is what we're trying to output:
11784 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11785 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11787 haddpd %xmm0, %xmm0
11789 pshufd $0x4e, %xmm0, %xmm1
11795 LLVMContext *Context = DAG.getContext();
11797 // Build some magic constants.
11798 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11799 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11800 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11802 SmallVector<Constant*,2> CV1;
11804 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11805 APInt(64, 0x4330000000000000ULL))));
11807 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11808 APInt(64, 0x4530000000000000ULL))));
11809 Constant *C1 = ConstantVector::get(CV1);
11810 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11812 // Load the 64-bit value into an XMM register.
11813 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11815 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11816 MachinePointerInfo::getConstantPool(),
11817 false, false, false, 16);
11818 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11819 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11822 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11823 MachinePointerInfo::getConstantPool(),
11824 false, false, false, 16);
11825 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11826 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11829 if (Subtarget->hasSSE3()) {
11830 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11831 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11833 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11834 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11836 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11837 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11841 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11842 DAG.getIntPtrConstant(0));
11845 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11846 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11847 SelectionDAG &DAG) const {
11849 // FP constant to bias correct the final result.
11850 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11853 // Load the 32-bit value into an XMM register.
11854 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11857 // Zero out the upper parts of the register.
11858 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11860 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11861 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11862 DAG.getIntPtrConstant(0));
11864 // Or the load with the bias.
11865 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11866 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11867 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11868 MVT::v2f64, Load)),
11869 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11870 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11871 MVT::v2f64, Bias)));
11872 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11873 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11874 DAG.getIntPtrConstant(0));
11876 // Subtract the bias.
11877 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11879 // Handle final rounding.
11880 EVT DestVT = Op.getValueType();
11882 if (DestVT.bitsLT(MVT::f64))
11883 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11884 DAG.getIntPtrConstant(0));
11885 if (DestVT.bitsGT(MVT::f64))
11886 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11888 // Handle final rounding.
11892 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11893 SelectionDAG &DAG) const {
11894 SDValue N0 = Op.getOperand(0);
11895 MVT SVT = N0.getSimpleValueType();
11898 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11899 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11900 "Custom UINT_TO_FP is not supported!");
11902 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11903 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11904 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11907 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11908 SelectionDAG &DAG) const {
11909 SDValue N0 = Op.getOperand(0);
11912 if (Op.getValueType().isVector())
11913 return lowerUINT_TO_FP_vec(Op, DAG);
11915 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11916 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11917 // the optimization here.
11918 if (DAG.SignBitIsZero(N0))
11919 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11921 MVT SrcVT = N0.getSimpleValueType();
11922 MVT DstVT = Op.getSimpleValueType();
11923 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11924 return LowerUINT_TO_FP_i64(Op, DAG);
11925 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11926 return LowerUINT_TO_FP_i32(Op, DAG);
11927 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11930 // Make a 64-bit buffer, and use it to build an FILD.
11931 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11932 if (SrcVT == MVT::i32) {
11933 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11934 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11935 getPointerTy(), StackSlot, WordOff);
11936 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11937 StackSlot, MachinePointerInfo(),
11939 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11940 OffsetSlot, MachinePointerInfo(),
11942 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11946 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11947 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11948 StackSlot, MachinePointerInfo(),
11950 // For i64 source, we need to add the appropriate power of 2 if the input
11951 // was negative. This is the same as the optimization in
11952 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11953 // we must be careful to do the computation in x87 extended precision, not
11954 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11955 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11956 MachineMemOperand *MMO =
11957 DAG.getMachineFunction()
11958 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11959 MachineMemOperand::MOLoad, 8, 8);
11961 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11962 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11963 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11966 APInt FF(32, 0x5F800000ULL);
11968 // Check whether the sign bit is set.
11969 SDValue SignSet = DAG.getSetCC(dl,
11970 getSetCCResultType(*DAG.getContext(), MVT::i64),
11971 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11974 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11975 SDValue FudgePtr = DAG.getConstantPool(
11976 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11979 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11980 SDValue Zero = DAG.getIntPtrConstant(0);
11981 SDValue Four = DAG.getIntPtrConstant(4);
11982 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11984 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11986 // Load the value out, extending it from f32 to f80.
11987 // FIXME: Avoid the extend by constructing the right constant pool?
11988 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11989 FudgePtr, MachinePointerInfo::getConstantPool(),
11990 MVT::f32, false, false, false, 4);
11991 // Extend everything to 80 bits to force it to be done on x87.
11992 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11993 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11996 std::pair<SDValue,SDValue>
11997 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11998 bool IsSigned, bool IsReplace) const {
12001 EVT DstTy = Op.getValueType();
12003 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12004 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12008 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12009 DstTy.getSimpleVT() >= MVT::i16 &&
12010 "Unknown FP_TO_INT to lower!");
12012 // These are really Legal.
12013 if (DstTy == MVT::i32 &&
12014 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12015 return std::make_pair(SDValue(), SDValue());
12016 if (Subtarget->is64Bit() &&
12017 DstTy == MVT::i64 &&
12018 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12019 return std::make_pair(SDValue(), SDValue());
12021 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12022 // stack slot, or into the FTOL runtime function.
12023 MachineFunction &MF = DAG.getMachineFunction();
12024 unsigned MemSize = DstTy.getSizeInBits()/8;
12025 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12026 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12029 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12030 Opc = X86ISD::WIN_FTOL;
12032 switch (DstTy.getSimpleVT().SimpleTy) {
12033 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12034 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12035 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12036 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12039 SDValue Chain = DAG.getEntryNode();
12040 SDValue Value = Op.getOperand(0);
12041 EVT TheVT = Op.getOperand(0).getValueType();
12042 // FIXME This causes a redundant load/store if the SSE-class value is already
12043 // in memory, such as if it is on the callstack.
12044 if (isScalarFPTypeInSSEReg(TheVT)) {
12045 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12046 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12047 MachinePointerInfo::getFixedStack(SSFI),
12049 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12051 Chain, StackSlot, DAG.getValueType(TheVT)
12054 MachineMemOperand *MMO =
12055 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12056 MachineMemOperand::MOLoad, MemSize, MemSize);
12057 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12058 Chain = Value.getValue(1);
12059 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12060 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12063 MachineMemOperand *MMO =
12064 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12065 MachineMemOperand::MOStore, MemSize, MemSize);
12067 if (Opc != X86ISD::WIN_FTOL) {
12068 // Build the FP_TO_INT*_IN_MEM
12069 SDValue Ops[] = { Chain, Value, StackSlot };
12070 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12072 return std::make_pair(FIST, StackSlot);
12074 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12075 DAG.getVTList(MVT::Other, MVT::Glue),
12077 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12078 MVT::i32, ftol.getValue(1));
12079 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12080 MVT::i32, eax.getValue(2));
12081 SDValue Ops[] = { eax, edx };
12082 SDValue pair = IsReplace
12083 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12084 : DAG.getMergeValues(Ops, DL);
12085 return std::make_pair(pair, SDValue());
12089 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12090 const X86Subtarget *Subtarget) {
12091 MVT VT = Op->getSimpleValueType(0);
12092 SDValue In = Op->getOperand(0);
12093 MVT InVT = In.getSimpleValueType();
12096 // Optimize vectors in AVX mode:
12099 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12100 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12101 // Concat upper and lower parts.
12104 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12105 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12106 // Concat upper and lower parts.
12109 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12110 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12111 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12114 if (Subtarget->hasInt256())
12115 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12117 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12118 SDValue Undef = DAG.getUNDEF(InVT);
12119 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12120 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12121 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12123 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12124 VT.getVectorNumElements()/2);
12126 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12127 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12129 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12132 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12133 SelectionDAG &DAG) {
12134 MVT VT = Op->getSimpleValueType(0);
12135 SDValue In = Op->getOperand(0);
12136 MVT InVT = In.getSimpleValueType();
12138 unsigned int NumElts = VT.getVectorNumElements();
12139 if (NumElts != 8 && NumElts != 16)
12142 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12143 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12145 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12146 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12147 // Now we have only mask extension
12148 assert(InVT.getVectorElementType() == MVT::i1);
12149 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12150 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12151 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12152 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12153 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12154 MachinePointerInfo::getConstantPool(),
12155 false, false, false, Alignment);
12157 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12158 if (VT.is512BitVector())
12160 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12163 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12164 SelectionDAG &DAG) {
12165 if (Subtarget->hasFp256()) {
12166 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12174 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12175 SelectionDAG &DAG) {
12177 MVT VT = Op.getSimpleValueType();
12178 SDValue In = Op.getOperand(0);
12179 MVT SVT = In.getSimpleValueType();
12181 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12182 return LowerZERO_EXTEND_AVX512(Op, DAG);
12184 if (Subtarget->hasFp256()) {
12185 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12190 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12191 VT.getVectorNumElements() != SVT.getVectorNumElements());
12195 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12197 MVT VT = Op.getSimpleValueType();
12198 SDValue In = Op.getOperand(0);
12199 MVT InVT = In.getSimpleValueType();
12201 if (VT == MVT::i1) {
12202 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12203 "Invalid scalar TRUNCATE operation");
12204 if (InVT.getSizeInBits() >= 32)
12206 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12207 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12209 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12210 "Invalid TRUNCATE operation");
12212 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12213 if (VT.getVectorElementType().getSizeInBits() >=8)
12214 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12216 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12217 unsigned NumElts = InVT.getVectorNumElements();
12218 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12219 if (InVT.getSizeInBits() < 512) {
12220 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12221 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12225 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12226 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12227 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12228 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12229 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12230 MachinePointerInfo::getConstantPool(),
12231 false, false, false, Alignment);
12232 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12233 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12234 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12237 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12238 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12239 if (Subtarget->hasInt256()) {
12240 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12241 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12242 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12244 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12245 DAG.getIntPtrConstant(0));
12248 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12249 DAG.getIntPtrConstant(0));
12250 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12251 DAG.getIntPtrConstant(2));
12252 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12253 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12254 static const int ShufMask[] = {0, 2, 4, 6};
12255 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12258 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12259 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12260 if (Subtarget->hasInt256()) {
12261 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12263 SmallVector<SDValue,32> pshufbMask;
12264 for (unsigned i = 0; i < 2; ++i) {
12265 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12266 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12267 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12268 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12269 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12270 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12271 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12272 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12273 for (unsigned j = 0; j < 8; ++j)
12274 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12276 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12277 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12278 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12280 static const int ShufMask[] = {0, 2, -1, -1};
12281 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12283 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12284 DAG.getIntPtrConstant(0));
12285 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12288 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12289 DAG.getIntPtrConstant(0));
12291 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12292 DAG.getIntPtrConstant(4));
12294 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12295 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12297 // The PSHUFB mask:
12298 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12299 -1, -1, -1, -1, -1, -1, -1, -1};
12301 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12302 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12303 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12305 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12306 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12308 // The MOVLHPS Mask:
12309 static const int ShufMask2[] = {0, 1, 4, 5};
12310 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12311 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12314 // Handle truncation of V256 to V128 using shuffles.
12315 if (!VT.is128BitVector() || !InVT.is256BitVector())
12318 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12320 unsigned NumElems = VT.getVectorNumElements();
12321 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12323 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12324 // Prepare truncation shuffle mask
12325 for (unsigned i = 0; i != NumElems; ++i)
12326 MaskVec[i] = i * 2;
12327 SDValue V = DAG.getVectorShuffle(NVT, DL,
12328 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12329 DAG.getUNDEF(NVT), &MaskVec[0]);
12330 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12331 DAG.getIntPtrConstant(0));
12334 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12335 SelectionDAG &DAG) const {
12336 assert(!Op.getSimpleValueType().isVector());
12338 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12339 /*IsSigned=*/ true, /*IsReplace=*/ false);
12340 SDValue FIST = Vals.first, StackSlot = Vals.second;
12341 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12342 if (!FIST.getNode()) return Op;
12344 if (StackSlot.getNode())
12345 // Load the result.
12346 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12347 FIST, StackSlot, MachinePointerInfo(),
12348 false, false, false, 0);
12350 // The node is the result.
12354 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12355 SelectionDAG &DAG) const {
12356 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12357 /*IsSigned=*/ false, /*IsReplace=*/ false);
12358 SDValue FIST = Vals.first, StackSlot = Vals.second;
12359 assert(FIST.getNode() && "Unexpected failure");
12361 if (StackSlot.getNode())
12362 // Load the result.
12363 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12364 FIST, StackSlot, MachinePointerInfo(),
12365 false, false, false, 0);
12367 // The node is the result.
12371 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12373 MVT VT = Op.getSimpleValueType();
12374 SDValue In = Op.getOperand(0);
12375 MVT SVT = In.getSimpleValueType();
12377 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12379 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12380 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12381 In, DAG.getUNDEF(SVT)));
12384 // The only differences between FABS and FNEG are the mask and the logic op.
12385 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12386 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12387 "Wrong opcode for lowering FABS or FNEG.");
12389 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12391 MVT VT = Op.getSimpleValueType();
12392 // Assume scalar op for initialization; update for vector if needed.
12393 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12394 // generate a 16-byte vector constant and logic op even for the scalar case.
12395 // Using a 16-byte mask allows folding the load of the mask with
12396 // the logic op, so it can save (~4 bytes) on code size.
12398 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12399 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12400 // decide if we should generate a 16-byte constant mask when we only need 4 or
12401 // 8 bytes for the scalar case.
12402 if (VT.isVector()) {
12403 EltVT = VT.getVectorElementType();
12404 NumElts = VT.getVectorNumElements();
12407 unsigned EltBits = EltVT.getSizeInBits();
12408 LLVMContext *Context = DAG.getContext();
12409 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12411 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12412 Constant *C = ConstantInt::get(*Context, MaskElt);
12413 C = ConstantVector::getSplat(NumElts, C);
12414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12415 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12416 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12417 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12418 MachinePointerInfo::getConstantPool(),
12419 false, false, false, Alignment);
12421 if (VT.isVector()) {
12422 // For a vector, cast operands to a vector type, perform the logic op,
12423 // and cast the result back to the original value type.
12424 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12425 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
12426 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12427 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
12428 return DAG.getNode(ISD::BITCAST, dl, VT,
12429 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
12431 // If not vector, then scalar.
12432 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
12433 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
12436 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12438 LLVMContext *Context = DAG.getContext();
12439 SDValue Op0 = Op.getOperand(0);
12440 SDValue Op1 = Op.getOperand(1);
12442 MVT VT = Op.getSimpleValueType();
12443 MVT SrcVT = Op1.getSimpleValueType();
12445 // If second operand is smaller, extend it first.
12446 if (SrcVT.bitsLT(VT)) {
12447 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12450 // And if it is bigger, shrink it first.
12451 if (SrcVT.bitsGT(VT)) {
12452 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12456 // At this point the operands and the result should have the same
12457 // type, and that won't be f80 since that is not custom lowered.
12459 // First get the sign bit of second operand.
12460 SmallVector<Constant*,4> CV;
12461 if (SrcVT == MVT::f64) {
12462 const fltSemantics &Sem = APFloat::IEEEdouble;
12463 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12464 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12466 const fltSemantics &Sem = APFloat::IEEEsingle;
12467 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12468 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12470 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12472 Constant *C = ConstantVector::get(CV);
12473 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12474 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12475 MachinePointerInfo::getConstantPool(),
12476 false, false, false, 16);
12477 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12479 // Shift sign bit right or left if the two operands have different types.
12480 if (SrcVT.bitsGT(VT)) {
12481 // Op0 is MVT::f32, Op1 is MVT::f64.
12482 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12483 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12484 DAG.getConstant(32, MVT::i32));
12485 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12486 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12487 DAG.getIntPtrConstant(0));
12490 // Clear first operand sign bit.
12492 if (VT == MVT::f64) {
12493 const fltSemantics &Sem = APFloat::IEEEdouble;
12494 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12495 APInt(64, ~(1ULL << 63)))));
12496 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12498 const fltSemantics &Sem = APFloat::IEEEsingle;
12499 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12500 APInt(32, ~(1U << 31)))));
12501 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12502 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12503 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12505 C = ConstantVector::get(CV);
12506 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12507 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12508 MachinePointerInfo::getConstantPool(),
12509 false, false, false, 16);
12510 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12512 // Or the value with the sign bit.
12513 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12516 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12517 SDValue N0 = Op.getOperand(0);
12519 MVT VT = Op.getSimpleValueType();
12521 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12522 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12523 DAG.getConstant(1, VT));
12524 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12527 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12529 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12530 SelectionDAG &DAG) {
12531 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12533 if (!Subtarget->hasSSE41())
12536 if (!Op->hasOneUse())
12539 SDNode *N = Op.getNode();
12542 SmallVector<SDValue, 8> Opnds;
12543 DenseMap<SDValue, unsigned> VecInMap;
12544 SmallVector<SDValue, 8> VecIns;
12545 EVT VT = MVT::Other;
12547 // Recognize a special case where a vector is casted into wide integer to
12549 Opnds.push_back(N->getOperand(0));
12550 Opnds.push_back(N->getOperand(1));
12552 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12553 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12554 // BFS traverse all OR'd operands.
12555 if (I->getOpcode() == ISD::OR) {
12556 Opnds.push_back(I->getOperand(0));
12557 Opnds.push_back(I->getOperand(1));
12558 // Re-evaluate the number of nodes to be traversed.
12559 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12563 // Quit if a non-EXTRACT_VECTOR_ELT
12564 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12567 // Quit if without a constant index.
12568 SDValue Idx = I->getOperand(1);
12569 if (!isa<ConstantSDNode>(Idx))
12572 SDValue ExtractedFromVec = I->getOperand(0);
12573 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12574 if (M == VecInMap.end()) {
12575 VT = ExtractedFromVec.getValueType();
12576 // Quit if not 128/256-bit vector.
12577 if (!VT.is128BitVector() && !VT.is256BitVector())
12579 // Quit if not the same type.
12580 if (VecInMap.begin() != VecInMap.end() &&
12581 VT != VecInMap.begin()->first.getValueType())
12583 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12584 VecIns.push_back(ExtractedFromVec);
12586 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12589 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12590 "Not extracted from 128-/256-bit vector.");
12592 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12594 for (DenseMap<SDValue, unsigned>::const_iterator
12595 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12596 // Quit if not all elements are used.
12597 if (I->second != FullMask)
12601 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12603 // Cast all vectors into TestVT for PTEST.
12604 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12605 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12607 // If more than one full vectors are evaluated, OR them first before PTEST.
12608 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12609 // Each iteration will OR 2 nodes and append the result until there is only
12610 // 1 node left, i.e. the final OR'd value of all vectors.
12611 SDValue LHS = VecIns[Slot];
12612 SDValue RHS = VecIns[Slot + 1];
12613 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12616 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12617 VecIns.back(), VecIns.back());
12620 /// \brief return true if \c Op has a use that doesn't just read flags.
12621 static bool hasNonFlagsUse(SDValue Op) {
12622 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12624 SDNode *User = *UI;
12625 unsigned UOpNo = UI.getOperandNo();
12626 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12627 // Look pass truncate.
12628 UOpNo = User->use_begin().getOperandNo();
12629 User = *User->use_begin();
12632 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12633 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12639 /// Emit nodes that will be selected as "test Op0,Op0", or something
12641 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12642 SelectionDAG &DAG) const {
12643 if (Op.getValueType() == MVT::i1)
12644 // KORTEST instruction should be selected
12645 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12646 DAG.getConstant(0, Op.getValueType()));
12648 // CF and OF aren't always set the way we want. Determine which
12649 // of these we need.
12650 bool NeedCF = false;
12651 bool NeedOF = false;
12654 case X86::COND_A: case X86::COND_AE:
12655 case X86::COND_B: case X86::COND_BE:
12658 case X86::COND_G: case X86::COND_GE:
12659 case X86::COND_L: case X86::COND_LE:
12660 case X86::COND_O: case X86::COND_NO: {
12661 // Check if we really need to set the
12662 // Overflow flag. If NoSignedWrap is present
12663 // that is not actually needed.
12664 switch (Op->getOpcode()) {
12669 const BinaryWithFlagsSDNode *BinNode =
12670 cast<BinaryWithFlagsSDNode>(Op.getNode());
12671 if (BinNode->hasNoSignedWrap())
12681 // See if we can use the EFLAGS value from the operand instead of
12682 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12683 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12684 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12685 // Emit a CMP with 0, which is the TEST pattern.
12686 //if (Op.getValueType() == MVT::i1)
12687 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12688 // DAG.getConstant(0, MVT::i1));
12689 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12690 DAG.getConstant(0, Op.getValueType()));
12692 unsigned Opcode = 0;
12693 unsigned NumOperands = 0;
12695 // Truncate operations may prevent the merge of the SETCC instruction
12696 // and the arithmetic instruction before it. Attempt to truncate the operands
12697 // of the arithmetic instruction and use a reduced bit-width instruction.
12698 bool NeedTruncation = false;
12699 SDValue ArithOp = Op;
12700 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12701 SDValue Arith = Op->getOperand(0);
12702 // Both the trunc and the arithmetic op need to have one user each.
12703 if (Arith->hasOneUse())
12704 switch (Arith.getOpcode()) {
12711 NeedTruncation = true;
12717 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12718 // which may be the result of a CAST. We use the variable 'Op', which is the
12719 // non-casted variable when we check for possible users.
12720 switch (ArithOp.getOpcode()) {
12722 // Due to an isel shortcoming, be conservative if this add is likely to be
12723 // selected as part of a load-modify-store instruction. When the root node
12724 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12725 // uses of other nodes in the match, such as the ADD in this case. This
12726 // leads to the ADD being left around and reselected, with the result being
12727 // two adds in the output. Alas, even if none our users are stores, that
12728 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12729 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12730 // climbing the DAG back to the root, and it doesn't seem to be worth the
12732 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12733 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12734 if (UI->getOpcode() != ISD::CopyToReg &&
12735 UI->getOpcode() != ISD::SETCC &&
12736 UI->getOpcode() != ISD::STORE)
12739 if (ConstantSDNode *C =
12740 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12741 // An add of one will be selected as an INC.
12742 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12743 Opcode = X86ISD::INC;
12748 // An add of negative one (subtract of one) will be selected as a DEC.
12749 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12750 Opcode = X86ISD::DEC;
12756 // Otherwise use a regular EFLAGS-setting add.
12757 Opcode = X86ISD::ADD;
12762 // If we have a constant logical shift that's only used in a comparison
12763 // against zero turn it into an equivalent AND. This allows turning it into
12764 // a TEST instruction later.
12765 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12766 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12767 EVT VT = Op.getValueType();
12768 unsigned BitWidth = VT.getSizeInBits();
12769 unsigned ShAmt = Op->getConstantOperandVal(1);
12770 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12772 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12773 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12774 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12775 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12777 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12778 DAG.getConstant(Mask, VT));
12779 DAG.ReplaceAllUsesWith(Op, New);
12785 // If the primary and result isn't used, don't bother using X86ISD::AND,
12786 // because a TEST instruction will be better.
12787 if (!hasNonFlagsUse(Op))
12793 // Due to the ISEL shortcoming noted above, be conservative if this op is
12794 // likely to be selected as part of a load-modify-store instruction.
12795 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12796 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12797 if (UI->getOpcode() == ISD::STORE)
12800 // Otherwise use a regular EFLAGS-setting instruction.
12801 switch (ArithOp.getOpcode()) {
12802 default: llvm_unreachable("unexpected operator!");
12803 case ISD::SUB: Opcode = X86ISD::SUB; break;
12804 case ISD::XOR: Opcode = X86ISD::XOR; break;
12805 case ISD::AND: Opcode = X86ISD::AND; break;
12807 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12808 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12809 if (EFLAGS.getNode())
12812 Opcode = X86ISD::OR;
12826 return SDValue(Op.getNode(), 1);
12832 // If we found that truncation is beneficial, perform the truncation and
12834 if (NeedTruncation) {
12835 EVT VT = Op.getValueType();
12836 SDValue WideVal = Op->getOperand(0);
12837 EVT WideVT = WideVal.getValueType();
12838 unsigned ConvertedOp = 0;
12839 // Use a target machine opcode to prevent further DAGCombine
12840 // optimizations that may separate the arithmetic operations
12841 // from the setcc node.
12842 switch (WideVal.getOpcode()) {
12844 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12845 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12846 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12847 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12848 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12853 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12854 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12855 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12856 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12862 // Emit a CMP with 0, which is the TEST pattern.
12863 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12864 DAG.getConstant(0, Op.getValueType()));
12866 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12867 SmallVector<SDValue, 4> Ops;
12868 for (unsigned i = 0; i != NumOperands; ++i)
12869 Ops.push_back(Op.getOperand(i));
12871 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12872 DAG.ReplaceAllUsesWith(Op, New);
12873 return SDValue(New.getNode(), 1);
12876 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12878 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12879 SDLoc dl, SelectionDAG &DAG) const {
12880 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12881 if (C->getAPIntValue() == 0)
12882 return EmitTest(Op0, X86CC, dl, DAG);
12884 if (Op0.getValueType() == MVT::i1)
12885 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12888 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12889 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12890 // Do the comparison at i32 if it's smaller, besides the Atom case.
12891 // This avoids subregister aliasing issues. Keep the smaller reference
12892 // if we're optimizing for size, however, as that'll allow better folding
12893 // of memory operations.
12894 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12895 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12896 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12897 !Subtarget->isAtom()) {
12898 unsigned ExtendOp =
12899 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12900 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12901 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12903 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12904 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12905 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12907 return SDValue(Sub.getNode(), 1);
12909 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12912 /// Convert a comparison if required by the subtarget.
12913 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12914 SelectionDAG &DAG) const {
12915 // If the subtarget does not support the FUCOMI instruction, floating-point
12916 // comparisons have to be converted.
12917 if (Subtarget->hasCMov() ||
12918 Cmp.getOpcode() != X86ISD::CMP ||
12919 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12920 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12923 // The instruction selector will select an FUCOM instruction instead of
12924 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12925 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12926 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12928 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12929 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12930 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12931 DAG.getConstant(8, MVT::i8));
12932 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12933 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12936 static bool isAllOnes(SDValue V) {
12937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12938 return C && C->isAllOnesValue();
12941 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12942 /// if it's possible.
12943 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12944 SDLoc dl, SelectionDAG &DAG) const {
12945 SDValue Op0 = And.getOperand(0);
12946 SDValue Op1 = And.getOperand(1);
12947 if (Op0.getOpcode() == ISD::TRUNCATE)
12948 Op0 = Op0.getOperand(0);
12949 if (Op1.getOpcode() == ISD::TRUNCATE)
12950 Op1 = Op1.getOperand(0);
12953 if (Op1.getOpcode() == ISD::SHL)
12954 std::swap(Op0, Op1);
12955 if (Op0.getOpcode() == ISD::SHL) {
12956 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12957 if (And00C->getZExtValue() == 1) {
12958 // If we looked past a truncate, check that it's only truncating away
12960 unsigned BitWidth = Op0.getValueSizeInBits();
12961 unsigned AndBitWidth = And.getValueSizeInBits();
12962 if (BitWidth > AndBitWidth) {
12964 DAG.computeKnownBits(Op0, Zeros, Ones);
12965 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12969 RHS = Op0.getOperand(1);
12971 } else if (Op1.getOpcode() == ISD::Constant) {
12972 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12973 uint64_t AndRHSVal = AndRHS->getZExtValue();
12974 SDValue AndLHS = Op0;
12976 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12977 LHS = AndLHS.getOperand(0);
12978 RHS = AndLHS.getOperand(1);
12981 // Use BT if the immediate can't be encoded in a TEST instruction.
12982 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12984 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12988 if (LHS.getNode()) {
12989 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12990 // instruction. Since the shift amount is in-range-or-undefined, we know
12991 // that doing a bittest on the i32 value is ok. We extend to i32 because
12992 // the encoding for the i16 version is larger than the i32 version.
12993 // Also promote i16 to i32 for performance / code size reason.
12994 if (LHS.getValueType() == MVT::i8 ||
12995 LHS.getValueType() == MVT::i16)
12996 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12998 // If the operand types disagree, extend the shift amount to match. Since
12999 // BT ignores high bits (like shifts) we can use anyextend.
13000 if (LHS.getValueType() != RHS.getValueType())
13001 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13003 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13004 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13005 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13006 DAG.getConstant(Cond, MVT::i8), BT);
13012 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13014 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13019 // SSE Condition code mapping:
13028 switch (SetCCOpcode) {
13029 default: llvm_unreachable("Unexpected SETCC condition");
13031 case ISD::SETEQ: SSECC = 0; break;
13033 case ISD::SETGT: Swap = true; // Fallthrough
13035 case ISD::SETOLT: SSECC = 1; break;
13037 case ISD::SETGE: Swap = true; // Fallthrough
13039 case ISD::SETOLE: SSECC = 2; break;
13040 case ISD::SETUO: SSECC = 3; break;
13042 case ISD::SETNE: SSECC = 4; break;
13043 case ISD::SETULE: Swap = true; // Fallthrough
13044 case ISD::SETUGE: SSECC = 5; break;
13045 case ISD::SETULT: Swap = true; // Fallthrough
13046 case ISD::SETUGT: SSECC = 6; break;
13047 case ISD::SETO: SSECC = 7; break;
13049 case ISD::SETONE: SSECC = 8; break;
13052 std::swap(Op0, Op1);
13057 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13058 // ones, and then concatenate the result back.
13059 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13060 MVT VT = Op.getSimpleValueType();
13062 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13063 "Unsupported value type for operation");
13065 unsigned NumElems = VT.getVectorNumElements();
13067 SDValue CC = Op.getOperand(2);
13069 // Extract the LHS vectors
13070 SDValue LHS = Op.getOperand(0);
13071 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13072 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13074 // Extract the RHS vectors
13075 SDValue RHS = Op.getOperand(1);
13076 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13077 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13079 // Issue the operation on the smaller types and concatenate the result back
13080 MVT EltVT = VT.getVectorElementType();
13081 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13082 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13083 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13084 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13087 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13088 const X86Subtarget *Subtarget) {
13089 SDValue Op0 = Op.getOperand(0);
13090 SDValue Op1 = Op.getOperand(1);
13091 SDValue CC = Op.getOperand(2);
13092 MVT VT = Op.getSimpleValueType();
13095 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13096 Op.getValueType().getScalarType() == MVT::i1 &&
13097 "Cannot set masked compare for this operation");
13099 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13101 bool Unsigned = false;
13104 switch (SetCCOpcode) {
13105 default: llvm_unreachable("Unexpected SETCC condition");
13106 case ISD::SETNE: SSECC = 4; break;
13107 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13108 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13109 case ISD::SETLT: Swap = true; //fall-through
13110 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13111 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13112 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13113 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13114 case ISD::SETULE: Unsigned = true; //fall-through
13115 case ISD::SETLE: SSECC = 2; break;
13119 std::swap(Op0, Op1);
13121 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13122 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13123 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13124 DAG.getConstant(SSECC, MVT::i8));
13127 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13128 /// operand \p Op1. If non-trivial (for example because it's not constant)
13129 /// return an empty value.
13130 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13132 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13136 MVT VT = Op1.getSimpleValueType();
13137 MVT EVT = VT.getVectorElementType();
13138 unsigned n = VT.getVectorNumElements();
13139 SmallVector<SDValue, 8> ULTOp1;
13141 for (unsigned i = 0; i < n; ++i) {
13142 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13143 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13146 // Avoid underflow.
13147 APInt Val = Elt->getAPIntValue();
13151 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13154 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13157 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13158 SelectionDAG &DAG) {
13159 SDValue Op0 = Op.getOperand(0);
13160 SDValue Op1 = Op.getOperand(1);
13161 SDValue CC = Op.getOperand(2);
13162 MVT VT = Op.getSimpleValueType();
13163 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13164 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13169 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13170 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13173 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13174 unsigned Opc = X86ISD::CMPP;
13175 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13176 assert(VT.getVectorNumElements() <= 16);
13177 Opc = X86ISD::CMPM;
13179 // In the two special cases we can't handle, emit two comparisons.
13182 unsigned CombineOpc;
13183 if (SetCCOpcode == ISD::SETUEQ) {
13184 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13186 assert(SetCCOpcode == ISD::SETONE);
13187 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13190 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13191 DAG.getConstant(CC0, MVT::i8));
13192 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13193 DAG.getConstant(CC1, MVT::i8));
13194 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13196 // Handle all other FP comparisons here.
13197 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13198 DAG.getConstant(SSECC, MVT::i8));
13201 // Break 256-bit integer vector compare into smaller ones.
13202 if (VT.is256BitVector() && !Subtarget->hasInt256())
13203 return Lower256IntVSETCC(Op, DAG);
13205 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13206 EVT OpVT = Op1.getValueType();
13207 if (Subtarget->hasAVX512()) {
13208 if (Op1.getValueType().is512BitVector() ||
13209 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13210 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13211 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13213 // In AVX-512 architecture setcc returns mask with i1 elements,
13214 // But there is no compare instruction for i8 and i16 elements in KNL.
13215 // We are not talking about 512-bit operands in this case, these
13216 // types are illegal.
13218 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13219 OpVT.getVectorElementType().getSizeInBits() >= 8))
13220 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13221 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13224 // We are handling one of the integer comparisons here. Since SSE only has
13225 // GT and EQ comparisons for integer, swapping operands and multiple
13226 // operations may be required for some comparisons.
13228 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13229 bool Subus = false;
13231 switch (SetCCOpcode) {
13232 default: llvm_unreachable("Unexpected SETCC condition");
13233 case ISD::SETNE: Invert = true;
13234 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13235 case ISD::SETLT: Swap = true;
13236 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13237 case ISD::SETGE: Swap = true;
13238 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13239 Invert = true; break;
13240 case ISD::SETULT: Swap = true;
13241 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13242 FlipSigns = true; break;
13243 case ISD::SETUGE: Swap = true;
13244 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13245 FlipSigns = true; Invert = true; break;
13248 // Special case: Use min/max operations for SETULE/SETUGE
13249 MVT VET = VT.getVectorElementType();
13251 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13252 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13255 switch (SetCCOpcode) {
13257 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13258 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13261 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13264 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13265 if (!MinMax && hasSubus) {
13266 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13268 // t = psubus Op0, Op1
13269 // pcmpeq t, <0..0>
13270 switch (SetCCOpcode) {
13272 case ISD::SETULT: {
13273 // If the comparison is against a constant we can turn this into a
13274 // setule. With psubus, setule does not require a swap. This is
13275 // beneficial because the constant in the register is no longer
13276 // destructed as the destination so it can be hoisted out of a loop.
13277 // Only do this pre-AVX since vpcmp* is no longer destructive.
13278 if (Subtarget->hasAVX())
13280 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13281 if (ULEOp1.getNode()) {
13283 Subus = true; Invert = false; Swap = false;
13287 // Psubus is better than flip-sign because it requires no inversion.
13288 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13289 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13293 Opc = X86ISD::SUBUS;
13299 std::swap(Op0, Op1);
13301 // Check that the operation in question is available (most are plain SSE2,
13302 // but PCMPGTQ and PCMPEQQ have different requirements).
13303 if (VT == MVT::v2i64) {
13304 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13305 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13307 // First cast everything to the right type.
13308 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13309 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13311 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13312 // bits of the inputs before performing those operations. The lower
13313 // compare is always unsigned.
13316 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13318 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13319 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13320 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13321 Sign, Zero, Sign, Zero);
13323 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13324 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13326 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13327 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13328 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13330 // Create masks for only the low parts/high parts of the 64 bit integers.
13331 static const int MaskHi[] = { 1, 1, 3, 3 };
13332 static const int MaskLo[] = { 0, 0, 2, 2 };
13333 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13334 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13335 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13337 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13338 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13341 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13343 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13346 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13347 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13348 // pcmpeqd + pshufd + pand.
13349 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13351 // First cast everything to the right type.
13352 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13353 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13356 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13358 // Make sure the lower and upper halves are both all-ones.
13359 static const int Mask[] = { 1, 0, 3, 2 };
13360 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13361 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13364 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13366 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13370 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13371 // bits of the inputs before performing those operations.
13373 EVT EltVT = VT.getVectorElementType();
13374 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13375 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13376 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13379 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13381 // If the logical-not of the result is required, perform that now.
13383 Result = DAG.getNOT(dl, Result, VT);
13386 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13389 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13390 getZeroVector(VT, Subtarget, DAG, dl));
13395 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13397 MVT VT = Op.getSimpleValueType();
13399 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13401 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13402 && "SetCC type must be 8-bit or 1-bit integer");
13403 SDValue Op0 = Op.getOperand(0);
13404 SDValue Op1 = Op.getOperand(1);
13406 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13408 // Optimize to BT if possible.
13409 // Lower (X & (1 << N)) == 0 to BT(X, N).
13410 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13411 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13412 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13413 Op1.getOpcode() == ISD::Constant &&
13414 cast<ConstantSDNode>(Op1)->isNullValue() &&
13415 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13416 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13417 if (NewSetCC.getNode())
13421 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13423 if (Op1.getOpcode() == ISD::Constant &&
13424 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13425 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13426 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13428 // If the input is a setcc, then reuse the input setcc or use a new one with
13429 // the inverted condition.
13430 if (Op0.getOpcode() == X86ISD::SETCC) {
13431 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13432 bool Invert = (CC == ISD::SETNE) ^
13433 cast<ConstantSDNode>(Op1)->isNullValue();
13437 CCode = X86::GetOppositeBranchCondition(CCode);
13438 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13439 DAG.getConstant(CCode, MVT::i8),
13440 Op0.getOperand(1));
13442 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13446 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13447 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13448 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13450 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13451 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13454 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13455 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13456 if (X86CC == X86::COND_INVALID)
13459 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13460 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13461 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13462 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13464 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13468 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13469 static bool isX86LogicalCmp(SDValue Op) {
13470 unsigned Opc = Op.getNode()->getOpcode();
13471 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13472 Opc == X86ISD::SAHF)
13474 if (Op.getResNo() == 1 &&
13475 (Opc == X86ISD::ADD ||
13476 Opc == X86ISD::SUB ||
13477 Opc == X86ISD::ADC ||
13478 Opc == X86ISD::SBB ||
13479 Opc == X86ISD::SMUL ||
13480 Opc == X86ISD::UMUL ||
13481 Opc == X86ISD::INC ||
13482 Opc == X86ISD::DEC ||
13483 Opc == X86ISD::OR ||
13484 Opc == X86ISD::XOR ||
13485 Opc == X86ISD::AND))
13488 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13494 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13495 if (V.getOpcode() != ISD::TRUNCATE)
13498 SDValue VOp0 = V.getOperand(0);
13499 unsigned InBits = VOp0.getValueSizeInBits();
13500 unsigned Bits = V.getValueSizeInBits();
13501 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13504 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13505 bool addTest = true;
13506 SDValue Cond = Op.getOperand(0);
13507 SDValue Op1 = Op.getOperand(1);
13508 SDValue Op2 = Op.getOperand(2);
13510 EVT VT = Op1.getValueType();
13513 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13514 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13515 // sequence later on.
13516 if (Cond.getOpcode() == ISD::SETCC &&
13517 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13518 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13519 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13520 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13521 int SSECC = translateX86FSETCC(
13522 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13525 if (Subtarget->hasAVX512()) {
13526 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13527 DAG.getConstant(SSECC, MVT::i8));
13528 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13530 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13531 DAG.getConstant(SSECC, MVT::i8));
13532 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13533 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13534 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13538 if (Cond.getOpcode() == ISD::SETCC) {
13539 SDValue NewCond = LowerSETCC(Cond, DAG);
13540 if (NewCond.getNode())
13544 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13545 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13546 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13547 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13548 if (Cond.getOpcode() == X86ISD::SETCC &&
13549 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13550 isZero(Cond.getOperand(1).getOperand(1))) {
13551 SDValue Cmp = Cond.getOperand(1);
13553 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13555 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13556 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13557 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13559 SDValue CmpOp0 = Cmp.getOperand(0);
13560 // Apply further optimizations for special cases
13561 // (select (x != 0), -1, 0) -> neg & sbb
13562 // (select (x == 0), 0, -1) -> neg & sbb
13563 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13564 if (YC->isNullValue() &&
13565 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13566 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13567 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13568 DAG.getConstant(0, CmpOp0.getValueType()),
13570 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13571 DAG.getConstant(X86::COND_B, MVT::i8),
13572 SDValue(Neg.getNode(), 1));
13576 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13577 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13578 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13580 SDValue Res = // Res = 0 or -1.
13581 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13582 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13584 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13585 Res = DAG.getNOT(DL, Res, Res.getValueType());
13587 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13588 if (!N2C || !N2C->isNullValue())
13589 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13594 // Look past (and (setcc_carry (cmp ...)), 1).
13595 if (Cond.getOpcode() == ISD::AND &&
13596 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13597 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13598 if (C && C->getAPIntValue() == 1)
13599 Cond = Cond.getOperand(0);
13602 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13603 // setting operand in place of the X86ISD::SETCC.
13604 unsigned CondOpcode = Cond.getOpcode();
13605 if (CondOpcode == X86ISD::SETCC ||
13606 CondOpcode == X86ISD::SETCC_CARRY) {
13607 CC = Cond.getOperand(0);
13609 SDValue Cmp = Cond.getOperand(1);
13610 unsigned Opc = Cmp.getOpcode();
13611 MVT VT = Op.getSimpleValueType();
13613 bool IllegalFPCMov = false;
13614 if (VT.isFloatingPoint() && !VT.isVector() &&
13615 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13616 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13618 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13619 Opc == X86ISD::BT) { // FIXME
13623 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13624 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13625 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13626 Cond.getOperand(0).getValueType() != MVT::i8)) {
13627 SDValue LHS = Cond.getOperand(0);
13628 SDValue RHS = Cond.getOperand(1);
13629 unsigned X86Opcode;
13632 switch (CondOpcode) {
13633 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13634 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13635 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13636 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13637 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13638 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13639 default: llvm_unreachable("unexpected overflowing operator");
13641 if (CondOpcode == ISD::UMULO)
13642 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13645 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13647 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13649 if (CondOpcode == ISD::UMULO)
13650 Cond = X86Op.getValue(2);
13652 Cond = X86Op.getValue(1);
13654 CC = DAG.getConstant(X86Cond, MVT::i8);
13659 // Look pass the truncate if the high bits are known zero.
13660 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13661 Cond = Cond.getOperand(0);
13663 // We know the result of AND is compared against zero. Try to match
13665 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13666 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13667 if (NewSetCC.getNode()) {
13668 CC = NewSetCC.getOperand(0);
13669 Cond = NewSetCC.getOperand(1);
13676 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13677 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13680 // a < b ? -1 : 0 -> RES = ~setcc_carry
13681 // a < b ? 0 : -1 -> RES = setcc_carry
13682 // a >= b ? -1 : 0 -> RES = setcc_carry
13683 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13684 if (Cond.getOpcode() == X86ISD::SUB) {
13685 Cond = ConvertCmpIfNecessary(Cond, DAG);
13686 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13688 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13689 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13690 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13691 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13692 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13693 return DAG.getNOT(DL, Res, Res.getValueType());
13698 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13699 // widen the cmov and push the truncate through. This avoids introducing a new
13700 // branch during isel and doesn't add any extensions.
13701 if (Op.getValueType() == MVT::i8 &&
13702 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13703 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13704 if (T1.getValueType() == T2.getValueType() &&
13705 // Blacklist CopyFromReg to avoid partial register stalls.
13706 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13707 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13708 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13709 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13713 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13714 // condition is true.
13715 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13716 SDValue Ops[] = { Op2, Op1, CC, Cond };
13717 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13720 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13721 MVT VT = Op->getSimpleValueType(0);
13722 SDValue In = Op->getOperand(0);
13723 MVT InVT = In.getSimpleValueType();
13726 unsigned int NumElts = VT.getVectorNumElements();
13727 if (NumElts != 8 && NumElts != 16)
13730 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13731 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13734 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13736 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13737 Constant *C = ConstantInt::get(*DAG.getContext(),
13738 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13740 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13741 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13742 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13743 MachinePointerInfo::getConstantPool(),
13744 false, false, false, Alignment);
13745 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13746 if (VT.is512BitVector())
13748 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13751 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13752 SelectionDAG &DAG) {
13753 MVT VT = Op->getSimpleValueType(0);
13754 SDValue In = Op->getOperand(0);
13755 MVT InVT = In.getSimpleValueType();
13758 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13759 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13761 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13762 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13763 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13766 if (Subtarget->hasInt256())
13767 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13769 // Optimize vectors in AVX mode
13770 // Sign extend v8i16 to v8i32 and
13773 // Divide input vector into two parts
13774 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13775 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13776 // concat the vectors to original VT
13778 unsigned NumElems = InVT.getVectorNumElements();
13779 SDValue Undef = DAG.getUNDEF(InVT);
13781 SmallVector<int,8> ShufMask1(NumElems, -1);
13782 for (unsigned i = 0; i != NumElems/2; ++i)
13785 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13787 SmallVector<int,8> ShufMask2(NumElems, -1);
13788 for (unsigned i = 0; i != NumElems/2; ++i)
13789 ShufMask2[i] = i + NumElems/2;
13791 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13793 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13794 VT.getVectorNumElements()/2);
13796 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13797 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13799 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13802 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13803 // may emit an illegal shuffle but the expansion is still better than scalar
13804 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13805 // we'll emit a shuffle and a arithmetic shift.
13806 // TODO: It is possible to support ZExt by zeroing the undef values during
13807 // the shuffle phase or after the shuffle.
13808 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13809 SelectionDAG &DAG) {
13810 MVT RegVT = Op.getSimpleValueType();
13811 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13812 assert(RegVT.isInteger() &&
13813 "We only custom lower integer vector sext loads.");
13815 // Nothing useful we can do without SSE2 shuffles.
13816 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13818 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13820 EVT MemVT = Ld->getMemoryVT();
13821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13822 unsigned RegSz = RegVT.getSizeInBits();
13824 ISD::LoadExtType Ext = Ld->getExtensionType();
13826 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13827 && "Only anyext and sext are currently implemented.");
13828 assert(MemVT != RegVT && "Cannot extend to the same type");
13829 assert(MemVT.isVector() && "Must load a vector from memory");
13831 unsigned NumElems = RegVT.getVectorNumElements();
13832 unsigned MemSz = MemVT.getSizeInBits();
13833 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13835 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13836 // The only way in which we have a legal 256-bit vector result but not the
13837 // integer 256-bit operations needed to directly lower a sextload is if we
13838 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13839 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13840 // correctly legalized. We do this late to allow the canonical form of
13841 // sextload to persist throughout the rest of the DAG combiner -- it wants
13842 // to fold together any extensions it can, and so will fuse a sign_extend
13843 // of an sextload into a sextload targeting a wider value.
13845 if (MemSz == 128) {
13846 // Just switch this to a normal load.
13847 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13848 "it must be a legal 128-bit vector "
13850 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13851 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13852 Ld->isInvariant(), Ld->getAlignment());
13854 assert(MemSz < 128 &&
13855 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13856 // Do an sext load to a 128-bit vector type. We want to use the same
13857 // number of elements, but elements half as wide. This will end up being
13858 // recursively lowered by this routine, but will succeed as we definitely
13859 // have all the necessary features if we're using AVX1.
13861 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13862 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13864 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13865 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13866 Ld->isNonTemporal(), Ld->isInvariant(),
13867 Ld->getAlignment());
13870 // Replace chain users with the new chain.
13871 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13872 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13874 // Finally, do a normal sign-extend to the desired register.
13875 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13878 // All sizes must be a power of two.
13879 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13880 "Non-power-of-two elements are not custom lowered!");
13882 // Attempt to load the original value using scalar loads.
13883 // Find the largest scalar type that divides the total loaded size.
13884 MVT SclrLoadTy = MVT::i8;
13885 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13886 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13887 MVT Tp = (MVT::SimpleValueType)tp;
13888 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13893 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13894 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13896 SclrLoadTy = MVT::f64;
13898 // Calculate the number of scalar loads that we need to perform
13899 // in order to load our vector from memory.
13900 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13902 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13903 "Can only lower sext loads with a single scalar load!");
13905 unsigned loadRegZize = RegSz;
13906 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13909 // Represent our vector as a sequence of elements which are the
13910 // largest scalar that we can load.
13911 EVT LoadUnitVecVT = EVT::getVectorVT(
13912 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13914 // Represent the data using the same element type that is stored in
13915 // memory. In practice, we ''widen'' MemVT.
13917 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13918 loadRegZize / MemVT.getScalarType().getSizeInBits());
13920 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13921 "Invalid vector type");
13923 // We can't shuffle using an illegal type.
13924 assert(TLI.isTypeLegal(WideVecVT) &&
13925 "We only lower types that form legal widened vector types");
13927 SmallVector<SDValue, 8> Chains;
13928 SDValue Ptr = Ld->getBasePtr();
13929 SDValue Increment =
13930 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13931 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13933 for (unsigned i = 0; i < NumLoads; ++i) {
13934 // Perform a single load.
13935 SDValue ScalarLoad =
13936 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13937 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13938 Ld->getAlignment());
13939 Chains.push_back(ScalarLoad.getValue(1));
13940 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13941 // another round of DAGCombining.
13943 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13945 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13946 ScalarLoad, DAG.getIntPtrConstant(i));
13948 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13951 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13953 // Bitcast the loaded value to a vector of the original element type, in
13954 // the size of the target vector type.
13955 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13956 unsigned SizeRatio = RegSz / MemSz;
13958 if (Ext == ISD::SEXTLOAD) {
13959 // If we have SSE4.1, we can directly emit a VSEXT node.
13960 if (Subtarget->hasSSE41()) {
13961 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13962 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13966 // Otherwise we'll shuffle the small elements in the high bits of the
13967 // larger type and perform an arithmetic shift. If the shift is not legal
13968 // it's better to scalarize.
13969 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13970 "We can't implement a sext load without an arithmetic right shift!");
13972 // Redistribute the loaded elements into the different locations.
13973 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13974 for (unsigned i = 0; i != NumElems; ++i)
13975 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13977 SDValue Shuff = DAG.getVectorShuffle(
13978 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13980 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13982 // Build the arithmetic shift.
13983 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13984 MemVT.getVectorElementType().getSizeInBits();
13986 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13988 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13992 // Redistribute the loaded elements into the different locations.
13993 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13994 for (unsigned i = 0; i != NumElems; ++i)
13995 ShuffleVec[i * SizeRatio] = i;
13997 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13998 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14000 // Bitcast to the requested type.
14001 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14002 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14006 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14007 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14008 // from the AND / OR.
14009 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14010 Opc = Op.getOpcode();
14011 if (Opc != ISD::OR && Opc != ISD::AND)
14013 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14014 Op.getOperand(0).hasOneUse() &&
14015 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14016 Op.getOperand(1).hasOneUse());
14019 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14020 // 1 and that the SETCC node has a single use.
14021 static bool isXor1OfSetCC(SDValue Op) {
14022 if (Op.getOpcode() != ISD::XOR)
14024 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14025 if (N1C && N1C->getAPIntValue() == 1) {
14026 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14027 Op.getOperand(0).hasOneUse();
14032 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14033 bool addTest = true;
14034 SDValue Chain = Op.getOperand(0);
14035 SDValue Cond = Op.getOperand(1);
14036 SDValue Dest = Op.getOperand(2);
14039 bool Inverted = false;
14041 if (Cond.getOpcode() == ISD::SETCC) {
14042 // Check for setcc([su]{add,sub,mul}o == 0).
14043 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14044 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14045 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14046 Cond.getOperand(0).getResNo() == 1 &&
14047 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14048 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14049 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14050 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14051 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14052 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14054 Cond = Cond.getOperand(0);
14056 SDValue NewCond = LowerSETCC(Cond, DAG);
14057 if (NewCond.getNode())
14062 // FIXME: LowerXALUO doesn't handle these!!
14063 else if (Cond.getOpcode() == X86ISD::ADD ||
14064 Cond.getOpcode() == X86ISD::SUB ||
14065 Cond.getOpcode() == X86ISD::SMUL ||
14066 Cond.getOpcode() == X86ISD::UMUL)
14067 Cond = LowerXALUO(Cond, DAG);
14070 // Look pass (and (setcc_carry (cmp ...)), 1).
14071 if (Cond.getOpcode() == ISD::AND &&
14072 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14073 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14074 if (C && C->getAPIntValue() == 1)
14075 Cond = Cond.getOperand(0);
14078 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14079 // setting operand in place of the X86ISD::SETCC.
14080 unsigned CondOpcode = Cond.getOpcode();
14081 if (CondOpcode == X86ISD::SETCC ||
14082 CondOpcode == X86ISD::SETCC_CARRY) {
14083 CC = Cond.getOperand(0);
14085 SDValue Cmp = Cond.getOperand(1);
14086 unsigned Opc = Cmp.getOpcode();
14087 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14088 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14092 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14096 // These can only come from an arithmetic instruction with overflow,
14097 // e.g. SADDO, UADDO.
14098 Cond = Cond.getNode()->getOperand(1);
14104 CondOpcode = Cond.getOpcode();
14105 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14106 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14107 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14108 Cond.getOperand(0).getValueType() != MVT::i8)) {
14109 SDValue LHS = Cond.getOperand(0);
14110 SDValue RHS = Cond.getOperand(1);
14111 unsigned X86Opcode;
14114 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14115 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14117 switch (CondOpcode) {
14118 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14122 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14125 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14126 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14130 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14133 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14134 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14135 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14136 default: llvm_unreachable("unexpected overflowing operator");
14139 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14140 if (CondOpcode == ISD::UMULO)
14141 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14144 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14146 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14148 if (CondOpcode == ISD::UMULO)
14149 Cond = X86Op.getValue(2);
14151 Cond = X86Op.getValue(1);
14153 CC = DAG.getConstant(X86Cond, MVT::i8);
14157 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14158 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14159 if (CondOpc == ISD::OR) {
14160 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14161 // two branches instead of an explicit OR instruction with a
14163 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14164 isX86LogicalCmp(Cmp)) {
14165 CC = Cond.getOperand(0).getOperand(0);
14166 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14167 Chain, Dest, CC, Cmp);
14168 CC = Cond.getOperand(1).getOperand(0);
14172 } else { // ISD::AND
14173 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14174 // two branches instead of an explicit AND instruction with a
14175 // separate test. However, we only do this if this block doesn't
14176 // have a fall-through edge, because this requires an explicit
14177 // jmp when the condition is false.
14178 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14179 isX86LogicalCmp(Cmp) &&
14180 Op.getNode()->hasOneUse()) {
14181 X86::CondCode CCode =
14182 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14183 CCode = X86::GetOppositeBranchCondition(CCode);
14184 CC = DAG.getConstant(CCode, MVT::i8);
14185 SDNode *User = *Op.getNode()->use_begin();
14186 // Look for an unconditional branch following this conditional branch.
14187 // We need this because we need to reverse the successors in order
14188 // to implement FCMP_OEQ.
14189 if (User->getOpcode() == ISD::BR) {
14190 SDValue FalseBB = User->getOperand(1);
14192 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14193 assert(NewBR == User);
14197 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14198 Chain, Dest, CC, Cmp);
14199 X86::CondCode CCode =
14200 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14201 CCode = X86::GetOppositeBranchCondition(CCode);
14202 CC = DAG.getConstant(CCode, MVT::i8);
14208 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14209 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14210 // It should be transformed during dag combiner except when the condition
14211 // is set by a arithmetics with overflow node.
14212 X86::CondCode CCode =
14213 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14214 CCode = X86::GetOppositeBranchCondition(CCode);
14215 CC = DAG.getConstant(CCode, MVT::i8);
14216 Cond = Cond.getOperand(0).getOperand(1);
14218 } else if (Cond.getOpcode() == ISD::SETCC &&
14219 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14220 // For FCMP_OEQ, we can emit
14221 // two branches instead of an explicit AND instruction with a
14222 // separate test. However, we only do this if this block doesn't
14223 // have a fall-through edge, because this requires an explicit
14224 // jmp when the condition is false.
14225 if (Op.getNode()->hasOneUse()) {
14226 SDNode *User = *Op.getNode()->use_begin();
14227 // Look for an unconditional branch following this conditional branch.
14228 // We need this because we need to reverse the successors in order
14229 // to implement FCMP_OEQ.
14230 if (User->getOpcode() == ISD::BR) {
14231 SDValue FalseBB = User->getOperand(1);
14233 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14234 assert(NewBR == User);
14238 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14239 Cond.getOperand(0), Cond.getOperand(1));
14240 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14241 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14242 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14243 Chain, Dest, CC, Cmp);
14244 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14249 } else if (Cond.getOpcode() == ISD::SETCC &&
14250 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14251 // For FCMP_UNE, we can emit
14252 // two branches instead of an explicit AND instruction with a
14253 // separate test. However, we only do this if this block doesn't
14254 // have a fall-through edge, because this requires an explicit
14255 // jmp when the condition is false.
14256 if (Op.getNode()->hasOneUse()) {
14257 SDNode *User = *Op.getNode()->use_begin();
14258 // Look for an unconditional branch following this conditional branch.
14259 // We need this because we need to reverse the successors in order
14260 // to implement FCMP_UNE.
14261 if (User->getOpcode() == ISD::BR) {
14262 SDValue FalseBB = User->getOperand(1);
14264 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14265 assert(NewBR == User);
14268 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14269 Cond.getOperand(0), Cond.getOperand(1));
14270 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14271 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14272 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14273 Chain, Dest, CC, Cmp);
14274 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14284 // Look pass the truncate if the high bits are known zero.
14285 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14286 Cond = Cond.getOperand(0);
14288 // We know the result of AND is compared against zero. Try to match
14290 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14291 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14292 if (NewSetCC.getNode()) {
14293 CC = NewSetCC.getOperand(0);
14294 Cond = NewSetCC.getOperand(1);
14301 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14302 CC = DAG.getConstant(X86Cond, MVT::i8);
14303 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14305 Cond = ConvertCmpIfNecessary(Cond, DAG);
14306 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14307 Chain, Dest, CC, Cond);
14310 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14311 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14312 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14313 // that the guard pages used by the OS virtual memory manager are allocated in
14314 // correct sequence.
14316 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14317 SelectionDAG &DAG) const {
14318 MachineFunction &MF = DAG.getMachineFunction();
14319 bool SplitStack = MF.shouldSplitStack();
14320 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14325 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14326 SDNode* Node = Op.getNode();
14328 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14329 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14330 " not tell us which reg is the stack pointer!");
14331 EVT VT = Node->getValueType(0);
14332 SDValue Tmp1 = SDValue(Node, 0);
14333 SDValue Tmp2 = SDValue(Node, 1);
14334 SDValue Tmp3 = Node->getOperand(2);
14335 SDValue Chain = Tmp1.getOperand(0);
14337 // Chain the dynamic stack allocation so that it doesn't modify the stack
14338 // pointer when other instructions are using the stack.
14339 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14342 SDValue Size = Tmp2.getOperand(1);
14343 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14344 Chain = SP.getValue(1);
14345 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14346 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14347 unsigned StackAlign = TFI.getStackAlignment();
14348 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14349 if (Align > StackAlign)
14350 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14351 DAG.getConstant(-(uint64_t)Align, VT));
14352 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14354 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14355 DAG.getIntPtrConstant(0, true), SDValue(),
14358 SDValue Ops[2] = { Tmp1, Tmp2 };
14359 return DAG.getMergeValues(Ops, dl);
14363 SDValue Chain = Op.getOperand(0);
14364 SDValue Size = Op.getOperand(1);
14365 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14366 EVT VT = Op.getNode()->getValueType(0);
14368 bool Is64Bit = Subtarget->is64Bit();
14369 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14372 MachineRegisterInfo &MRI = MF.getRegInfo();
14375 // The 64 bit implementation of segmented stacks needs to clobber both r10
14376 // r11. This makes it impossible to use it along with nested parameters.
14377 const Function *F = MF.getFunction();
14379 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14381 if (I->hasNestAttr())
14382 report_fatal_error("Cannot use segmented stacks with functions that "
14383 "have nested arguments.");
14386 const TargetRegisterClass *AddrRegClass =
14387 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14388 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14389 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14390 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14391 DAG.getRegister(Vreg, SPTy));
14392 SDValue Ops1[2] = { Value, Chain };
14393 return DAG.getMergeValues(Ops1, dl);
14396 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14398 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14399 Flag = Chain.getValue(1);
14400 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14402 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14404 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14405 DAG.getSubtarget().getRegisterInfo());
14406 unsigned SPReg = RegInfo->getStackRegister();
14407 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14408 Chain = SP.getValue(1);
14411 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14412 DAG.getConstant(-(uint64_t)Align, VT));
14413 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14416 SDValue Ops1[2] = { SP, Chain };
14417 return DAG.getMergeValues(Ops1, dl);
14421 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14422 MachineFunction &MF = DAG.getMachineFunction();
14423 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14425 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14428 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14429 // vastart just stores the address of the VarArgsFrameIndex slot into the
14430 // memory location argument.
14431 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14433 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14434 MachinePointerInfo(SV), false, false, 0);
14438 // gp_offset (0 - 6 * 8)
14439 // fp_offset (48 - 48 + 8 * 16)
14440 // overflow_arg_area (point to parameters coming in memory).
14442 SmallVector<SDValue, 8> MemOps;
14443 SDValue FIN = Op.getOperand(1);
14445 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14446 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14448 FIN, MachinePointerInfo(SV), false, false, 0);
14449 MemOps.push_back(Store);
14452 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14453 FIN, DAG.getIntPtrConstant(4));
14454 Store = DAG.getStore(Op.getOperand(0), DL,
14455 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14457 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14458 MemOps.push_back(Store);
14460 // Store ptr to overflow_arg_area
14461 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14462 FIN, DAG.getIntPtrConstant(4));
14463 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14465 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14466 MachinePointerInfo(SV, 8),
14468 MemOps.push_back(Store);
14470 // Store ptr to reg_save_area.
14471 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14472 FIN, DAG.getIntPtrConstant(8));
14473 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14475 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14476 MachinePointerInfo(SV, 16), false, false, 0);
14477 MemOps.push_back(Store);
14478 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14481 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14482 assert(Subtarget->is64Bit() &&
14483 "LowerVAARG only handles 64-bit va_arg!");
14484 assert((Subtarget->isTargetLinux() ||
14485 Subtarget->isTargetDarwin()) &&
14486 "Unhandled target in LowerVAARG");
14487 assert(Op.getNode()->getNumOperands() == 4);
14488 SDValue Chain = Op.getOperand(0);
14489 SDValue SrcPtr = Op.getOperand(1);
14490 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14491 unsigned Align = Op.getConstantOperandVal(3);
14494 EVT ArgVT = Op.getNode()->getValueType(0);
14495 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14496 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14499 // Decide which area this value should be read from.
14500 // TODO: Implement the AMD64 ABI in its entirety. This simple
14501 // selection mechanism works only for the basic types.
14502 if (ArgVT == MVT::f80) {
14503 llvm_unreachable("va_arg for f80 not yet implemented");
14504 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14505 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14506 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14507 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14509 llvm_unreachable("Unhandled argument type in LowerVAARG");
14512 if (ArgMode == 2) {
14513 // Sanity Check: Make sure using fp_offset makes sense.
14514 assert(!DAG.getTarget().Options.UseSoftFloat &&
14515 !(DAG.getMachineFunction()
14516 .getFunction()->getAttributes()
14517 .hasAttribute(AttributeSet::FunctionIndex,
14518 Attribute::NoImplicitFloat)) &&
14519 Subtarget->hasSSE1());
14522 // Insert VAARG_64 node into the DAG
14523 // VAARG_64 returns two values: Variable Argument Address, Chain
14524 SmallVector<SDValue, 11> InstOps;
14525 InstOps.push_back(Chain);
14526 InstOps.push_back(SrcPtr);
14527 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14528 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14529 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14530 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14531 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14532 VTs, InstOps, MVT::i64,
14533 MachinePointerInfo(SV),
14535 /*Volatile=*/false,
14537 /*WriteMem=*/true);
14538 Chain = VAARG.getValue(1);
14540 // Load the next argument and return it
14541 return DAG.getLoad(ArgVT, dl,
14544 MachinePointerInfo(),
14545 false, false, false, 0);
14548 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14549 SelectionDAG &DAG) {
14550 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14551 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14552 SDValue Chain = Op.getOperand(0);
14553 SDValue DstPtr = Op.getOperand(1);
14554 SDValue SrcPtr = Op.getOperand(2);
14555 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14556 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14559 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14560 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14562 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14565 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14566 // amount is a constant. Takes immediate version of shift as input.
14567 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14568 SDValue SrcOp, uint64_t ShiftAmt,
14569 SelectionDAG &DAG) {
14570 MVT ElementType = VT.getVectorElementType();
14572 // Fold this packed shift into its first operand if ShiftAmt is 0.
14576 // Check for ShiftAmt >= element width
14577 if (ShiftAmt >= ElementType.getSizeInBits()) {
14578 if (Opc == X86ISD::VSRAI)
14579 ShiftAmt = ElementType.getSizeInBits() - 1;
14581 return DAG.getConstant(0, VT);
14584 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14585 && "Unknown target vector shift-by-constant node");
14587 // Fold this packed vector shift into a build vector if SrcOp is a
14588 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14589 if (VT == SrcOp.getSimpleValueType() &&
14590 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14591 SmallVector<SDValue, 8> Elts;
14592 unsigned NumElts = SrcOp->getNumOperands();
14593 ConstantSDNode *ND;
14596 default: llvm_unreachable(nullptr);
14597 case X86ISD::VSHLI:
14598 for (unsigned i=0; i!=NumElts; ++i) {
14599 SDValue CurrentOp = SrcOp->getOperand(i);
14600 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14601 Elts.push_back(CurrentOp);
14604 ND = cast<ConstantSDNode>(CurrentOp);
14605 const APInt &C = ND->getAPIntValue();
14606 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14609 case X86ISD::VSRLI:
14610 for (unsigned i=0; i!=NumElts; ++i) {
14611 SDValue CurrentOp = SrcOp->getOperand(i);
14612 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14613 Elts.push_back(CurrentOp);
14616 ND = cast<ConstantSDNode>(CurrentOp);
14617 const APInt &C = ND->getAPIntValue();
14618 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14621 case X86ISD::VSRAI:
14622 for (unsigned i=0; i!=NumElts; ++i) {
14623 SDValue CurrentOp = SrcOp->getOperand(i);
14624 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14625 Elts.push_back(CurrentOp);
14628 ND = cast<ConstantSDNode>(CurrentOp);
14629 const APInt &C = ND->getAPIntValue();
14630 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14635 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14638 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14641 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14642 // may or may not be a constant. Takes immediate version of shift as input.
14643 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14644 SDValue SrcOp, SDValue ShAmt,
14645 SelectionDAG &DAG) {
14646 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
14648 // Catch shift-by-constant.
14649 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14650 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14651 CShAmt->getZExtValue(), DAG);
14653 // Change opcode to non-immediate version
14655 default: llvm_unreachable("Unknown target vector shift node");
14656 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14657 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14658 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14661 // Need to build a vector containing shift amount
14662 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
14665 ShOps[1] = DAG.getConstant(0, MVT::i32);
14666 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
14667 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
14669 // The return type has to be a 128-bit type with the same element
14670 // type as the input type.
14671 MVT EltVT = VT.getVectorElementType();
14672 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14674 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14675 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14678 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
14679 /// necessary casting for \p Mask when lowering masking intrinsics.
14680 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14681 SDValue PreservedSrc, SelectionDAG &DAG) {
14682 EVT VT = Op.getValueType();
14683 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14684 MVT::i1, VT.getVectorNumElements());
14687 assert(MaskVT.isSimple() && "invalid mask type");
14688 return DAG.getNode(ISD::VSELECT, dl, VT,
14689 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
14693 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
14695 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14696 case Intrinsic::x86_fma_vfmadd_ps:
14697 case Intrinsic::x86_fma_vfmadd_pd:
14698 case Intrinsic::x86_fma_vfmadd_ps_256:
14699 case Intrinsic::x86_fma_vfmadd_pd_256:
14700 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14701 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14702 return X86ISD::FMADD;
14703 case Intrinsic::x86_fma_vfmsub_ps:
14704 case Intrinsic::x86_fma_vfmsub_pd:
14705 case Intrinsic::x86_fma_vfmsub_ps_256:
14706 case Intrinsic::x86_fma_vfmsub_pd_256:
14707 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14708 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14709 return X86ISD::FMSUB;
14710 case Intrinsic::x86_fma_vfnmadd_ps:
14711 case Intrinsic::x86_fma_vfnmadd_pd:
14712 case Intrinsic::x86_fma_vfnmadd_ps_256:
14713 case Intrinsic::x86_fma_vfnmadd_pd_256:
14714 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14715 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14716 return X86ISD::FNMADD;
14717 case Intrinsic::x86_fma_vfnmsub_ps:
14718 case Intrinsic::x86_fma_vfnmsub_pd:
14719 case Intrinsic::x86_fma_vfnmsub_ps_256:
14720 case Intrinsic::x86_fma_vfnmsub_pd_256:
14721 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14722 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14723 return X86ISD::FNMSUB;
14724 case Intrinsic::x86_fma_vfmaddsub_ps:
14725 case Intrinsic::x86_fma_vfmaddsub_pd:
14726 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14727 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14728 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14729 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14730 return X86ISD::FMADDSUB;
14731 case Intrinsic::x86_fma_vfmsubadd_ps:
14732 case Intrinsic::x86_fma_vfmsubadd_pd:
14733 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14734 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14735 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14736 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
14737 return X86ISD::FMSUBADD;
14741 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
14743 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14745 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14747 switch(IntrData->Type) {
14748 case INTR_TYPE_1OP:
14749 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14750 case INTR_TYPE_2OP:
14751 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14753 case INTR_TYPE_3OP:
14754 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14755 Op.getOperand(2), Op.getOperand(3));
14756 case COMI: { // Comparison intrinsics
14757 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14758 SDValue LHS = Op.getOperand(1);
14759 SDValue RHS = Op.getOperand(2);
14760 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14761 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14762 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14763 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14764 DAG.getConstant(X86CC, MVT::i8), Cond);
14765 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14768 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14769 Op.getOperand(1), Op.getOperand(2), DAG);
14776 default: return SDValue(); // Don't custom lower most intrinsics.
14778 // Arithmetic intrinsics.
14779 case Intrinsic::x86_sse2_pmulu_dq:
14780 case Intrinsic::x86_avx2_pmulu_dq:
14781 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14782 Op.getOperand(1), Op.getOperand(2));
14784 case Intrinsic::x86_sse41_pmuldq:
14785 case Intrinsic::x86_avx2_pmul_dq:
14786 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14787 Op.getOperand(1), Op.getOperand(2));
14789 case Intrinsic::x86_sse2_pmulhu_w:
14790 case Intrinsic::x86_avx2_pmulhu_w:
14791 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14792 Op.getOperand(1), Op.getOperand(2));
14794 case Intrinsic::x86_sse2_pmulh_w:
14795 case Intrinsic::x86_avx2_pmulh_w:
14796 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14797 Op.getOperand(1), Op.getOperand(2));
14799 // SSE/SSE2/AVX floating point max/min intrinsics.
14800 case Intrinsic::x86_sse_max_ps:
14801 case Intrinsic::x86_sse2_max_pd:
14802 case Intrinsic::x86_avx_max_ps_256:
14803 case Intrinsic::x86_avx_max_pd_256:
14804 case Intrinsic::x86_sse_min_ps:
14805 case Intrinsic::x86_sse2_min_pd:
14806 case Intrinsic::x86_avx_min_ps_256:
14807 case Intrinsic::x86_avx_min_pd_256: {
14810 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14811 case Intrinsic::x86_sse_max_ps:
14812 case Intrinsic::x86_sse2_max_pd:
14813 case Intrinsic::x86_avx_max_ps_256:
14814 case Intrinsic::x86_avx_max_pd_256:
14815 Opcode = X86ISD::FMAX;
14817 case Intrinsic::x86_sse_min_ps:
14818 case Intrinsic::x86_sse2_min_pd:
14819 case Intrinsic::x86_avx_min_ps_256:
14820 case Intrinsic::x86_avx_min_pd_256:
14821 Opcode = X86ISD::FMIN;
14824 return DAG.getNode(Opcode, dl, Op.getValueType(),
14825 Op.getOperand(1), Op.getOperand(2));
14828 // AVX2 variable shift intrinsics
14829 case Intrinsic::x86_avx2_psllv_d:
14830 case Intrinsic::x86_avx2_psllv_q:
14831 case Intrinsic::x86_avx2_psllv_d_256:
14832 case Intrinsic::x86_avx2_psllv_q_256:
14833 case Intrinsic::x86_avx2_psrlv_d:
14834 case Intrinsic::x86_avx2_psrlv_q:
14835 case Intrinsic::x86_avx2_psrlv_d_256:
14836 case Intrinsic::x86_avx2_psrlv_q_256:
14837 case Intrinsic::x86_avx2_psrav_d:
14838 case Intrinsic::x86_avx2_psrav_d_256: {
14841 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14842 case Intrinsic::x86_avx2_psllv_d:
14843 case Intrinsic::x86_avx2_psllv_q:
14844 case Intrinsic::x86_avx2_psllv_d_256:
14845 case Intrinsic::x86_avx2_psllv_q_256:
14848 case Intrinsic::x86_avx2_psrlv_d:
14849 case Intrinsic::x86_avx2_psrlv_q:
14850 case Intrinsic::x86_avx2_psrlv_d_256:
14851 case Intrinsic::x86_avx2_psrlv_q_256:
14854 case Intrinsic::x86_avx2_psrav_d:
14855 case Intrinsic::x86_avx2_psrav_d_256:
14859 return DAG.getNode(Opcode, dl, Op.getValueType(),
14860 Op.getOperand(1), Op.getOperand(2));
14863 case Intrinsic::x86_sse2_packssdw_128:
14864 case Intrinsic::x86_sse2_packsswb_128:
14865 case Intrinsic::x86_avx2_packssdw:
14866 case Intrinsic::x86_avx2_packsswb:
14867 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14868 Op.getOperand(1), Op.getOperand(2));
14870 case Intrinsic::x86_sse2_packuswb_128:
14871 case Intrinsic::x86_sse41_packusdw:
14872 case Intrinsic::x86_avx2_packuswb:
14873 case Intrinsic::x86_avx2_packusdw:
14874 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14875 Op.getOperand(1), Op.getOperand(2));
14877 case Intrinsic::x86_ssse3_pshuf_b_128:
14878 case Intrinsic::x86_avx2_pshuf_b:
14879 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14880 Op.getOperand(1), Op.getOperand(2));
14882 case Intrinsic::x86_sse2_pshuf_d:
14883 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14884 Op.getOperand(1), Op.getOperand(2));
14886 case Intrinsic::x86_sse2_pshufl_w:
14887 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14888 Op.getOperand(1), Op.getOperand(2));
14890 case Intrinsic::x86_sse2_pshufh_w:
14891 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14892 Op.getOperand(1), Op.getOperand(2));
14894 case Intrinsic::x86_ssse3_psign_b_128:
14895 case Intrinsic::x86_ssse3_psign_w_128:
14896 case Intrinsic::x86_ssse3_psign_d_128:
14897 case Intrinsic::x86_avx2_psign_b:
14898 case Intrinsic::x86_avx2_psign_w:
14899 case Intrinsic::x86_avx2_psign_d:
14900 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14901 Op.getOperand(1), Op.getOperand(2));
14903 case Intrinsic::x86_avx2_permd:
14904 case Intrinsic::x86_avx2_permps:
14905 // Operands intentionally swapped. Mask is last operand to intrinsic,
14906 // but second operand for node/instruction.
14907 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14908 Op.getOperand(2), Op.getOperand(1));
14910 case Intrinsic::x86_avx512_mask_valign_q_512:
14911 case Intrinsic::x86_avx512_mask_valign_d_512:
14912 // Vector source operands are swapped.
14913 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14914 Op.getValueType(), Op.getOperand(2),
14917 Op.getOperand(5), Op.getOperand(4), DAG);
14919 // ptest and testp intrinsics. The intrinsic these come from are designed to
14920 // return an integer value, not just an instruction so lower it to the ptest
14921 // or testp pattern and a setcc for the result.
14922 case Intrinsic::x86_sse41_ptestz:
14923 case Intrinsic::x86_sse41_ptestc:
14924 case Intrinsic::x86_sse41_ptestnzc:
14925 case Intrinsic::x86_avx_ptestz_256:
14926 case Intrinsic::x86_avx_ptestc_256:
14927 case Intrinsic::x86_avx_ptestnzc_256:
14928 case Intrinsic::x86_avx_vtestz_ps:
14929 case Intrinsic::x86_avx_vtestc_ps:
14930 case Intrinsic::x86_avx_vtestnzc_ps:
14931 case Intrinsic::x86_avx_vtestz_pd:
14932 case Intrinsic::x86_avx_vtestc_pd:
14933 case Intrinsic::x86_avx_vtestnzc_pd:
14934 case Intrinsic::x86_avx_vtestz_ps_256:
14935 case Intrinsic::x86_avx_vtestc_ps_256:
14936 case Intrinsic::x86_avx_vtestnzc_ps_256:
14937 case Intrinsic::x86_avx_vtestz_pd_256:
14938 case Intrinsic::x86_avx_vtestc_pd_256:
14939 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14940 bool IsTestPacked = false;
14943 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14944 case Intrinsic::x86_avx_vtestz_ps:
14945 case Intrinsic::x86_avx_vtestz_pd:
14946 case Intrinsic::x86_avx_vtestz_ps_256:
14947 case Intrinsic::x86_avx_vtestz_pd_256:
14948 IsTestPacked = true; // Fallthrough
14949 case Intrinsic::x86_sse41_ptestz:
14950 case Intrinsic::x86_avx_ptestz_256:
14952 X86CC = X86::COND_E;
14954 case Intrinsic::x86_avx_vtestc_ps:
14955 case Intrinsic::x86_avx_vtestc_pd:
14956 case Intrinsic::x86_avx_vtestc_ps_256:
14957 case Intrinsic::x86_avx_vtestc_pd_256:
14958 IsTestPacked = true; // Fallthrough
14959 case Intrinsic::x86_sse41_ptestc:
14960 case Intrinsic::x86_avx_ptestc_256:
14962 X86CC = X86::COND_B;
14964 case Intrinsic::x86_avx_vtestnzc_ps:
14965 case Intrinsic::x86_avx_vtestnzc_pd:
14966 case Intrinsic::x86_avx_vtestnzc_ps_256:
14967 case Intrinsic::x86_avx_vtestnzc_pd_256:
14968 IsTestPacked = true; // Fallthrough
14969 case Intrinsic::x86_sse41_ptestnzc:
14970 case Intrinsic::x86_avx_ptestnzc_256:
14972 X86CC = X86::COND_A;
14976 SDValue LHS = Op.getOperand(1);
14977 SDValue RHS = Op.getOperand(2);
14978 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14979 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14980 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14981 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14982 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14984 case Intrinsic::x86_avx512_kortestz_w:
14985 case Intrinsic::x86_avx512_kortestc_w: {
14986 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14987 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14988 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14989 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14990 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14991 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14992 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14995 case Intrinsic::x86_sse42_pcmpistria128:
14996 case Intrinsic::x86_sse42_pcmpestria128:
14997 case Intrinsic::x86_sse42_pcmpistric128:
14998 case Intrinsic::x86_sse42_pcmpestric128:
14999 case Intrinsic::x86_sse42_pcmpistrio128:
15000 case Intrinsic::x86_sse42_pcmpestrio128:
15001 case Intrinsic::x86_sse42_pcmpistris128:
15002 case Intrinsic::x86_sse42_pcmpestris128:
15003 case Intrinsic::x86_sse42_pcmpistriz128:
15004 case Intrinsic::x86_sse42_pcmpestriz128: {
15008 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15009 case Intrinsic::x86_sse42_pcmpistria128:
15010 Opcode = X86ISD::PCMPISTRI;
15011 X86CC = X86::COND_A;
15013 case Intrinsic::x86_sse42_pcmpestria128:
15014 Opcode = X86ISD::PCMPESTRI;
15015 X86CC = X86::COND_A;
15017 case Intrinsic::x86_sse42_pcmpistric128:
15018 Opcode = X86ISD::PCMPISTRI;
15019 X86CC = X86::COND_B;
15021 case Intrinsic::x86_sse42_pcmpestric128:
15022 Opcode = X86ISD::PCMPESTRI;
15023 X86CC = X86::COND_B;
15025 case Intrinsic::x86_sse42_pcmpistrio128:
15026 Opcode = X86ISD::PCMPISTRI;
15027 X86CC = X86::COND_O;
15029 case Intrinsic::x86_sse42_pcmpestrio128:
15030 Opcode = X86ISD::PCMPESTRI;
15031 X86CC = X86::COND_O;
15033 case Intrinsic::x86_sse42_pcmpistris128:
15034 Opcode = X86ISD::PCMPISTRI;
15035 X86CC = X86::COND_S;
15037 case Intrinsic::x86_sse42_pcmpestris128:
15038 Opcode = X86ISD::PCMPESTRI;
15039 X86CC = X86::COND_S;
15041 case Intrinsic::x86_sse42_pcmpistriz128:
15042 Opcode = X86ISD::PCMPISTRI;
15043 X86CC = X86::COND_E;
15045 case Intrinsic::x86_sse42_pcmpestriz128:
15046 Opcode = X86ISD::PCMPESTRI;
15047 X86CC = X86::COND_E;
15050 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15051 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15052 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15053 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15054 DAG.getConstant(X86CC, MVT::i8),
15055 SDValue(PCMP.getNode(), 1));
15056 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15059 case Intrinsic::x86_sse42_pcmpistri128:
15060 case Intrinsic::x86_sse42_pcmpestri128: {
15062 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15063 Opcode = X86ISD::PCMPISTRI;
15065 Opcode = X86ISD::PCMPESTRI;
15067 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15068 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15069 return DAG.getNode(Opcode, dl, VTs, NewOps);
15072 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15073 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15074 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15075 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15076 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15077 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15078 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15079 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15080 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15081 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15082 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15083 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15084 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15085 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15086 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15087 dl, Op.getValueType(),
15091 Op.getOperand(4), Op.getOperand(1), DAG);
15096 case Intrinsic::x86_fma_vfmadd_ps:
15097 case Intrinsic::x86_fma_vfmadd_pd:
15098 case Intrinsic::x86_fma_vfmsub_ps:
15099 case Intrinsic::x86_fma_vfmsub_pd:
15100 case Intrinsic::x86_fma_vfnmadd_ps:
15101 case Intrinsic::x86_fma_vfnmadd_pd:
15102 case Intrinsic::x86_fma_vfnmsub_ps:
15103 case Intrinsic::x86_fma_vfnmsub_pd:
15104 case Intrinsic::x86_fma_vfmaddsub_ps:
15105 case Intrinsic::x86_fma_vfmaddsub_pd:
15106 case Intrinsic::x86_fma_vfmsubadd_ps:
15107 case Intrinsic::x86_fma_vfmsubadd_pd:
15108 case Intrinsic::x86_fma_vfmadd_ps_256:
15109 case Intrinsic::x86_fma_vfmadd_pd_256:
15110 case Intrinsic::x86_fma_vfmsub_ps_256:
15111 case Intrinsic::x86_fma_vfmsub_pd_256:
15112 case Intrinsic::x86_fma_vfnmadd_ps_256:
15113 case Intrinsic::x86_fma_vfnmadd_pd_256:
15114 case Intrinsic::x86_fma_vfnmsub_ps_256:
15115 case Intrinsic::x86_fma_vfnmsub_pd_256:
15116 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15117 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15118 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15119 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15120 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15121 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15125 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15126 SDValue Src, SDValue Mask, SDValue Base,
15127 SDValue Index, SDValue ScaleOp, SDValue Chain,
15128 const X86Subtarget * Subtarget) {
15130 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15131 assert(C && "Invalid scale type");
15132 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15133 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15134 Index.getSimpleValueType().getVectorNumElements());
15136 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15138 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15140 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15141 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15142 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15143 SDValue Segment = DAG.getRegister(0, MVT::i32);
15144 if (Src.getOpcode() == ISD::UNDEF)
15145 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15146 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15147 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15148 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15149 return DAG.getMergeValues(RetOps, dl);
15152 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15153 SDValue Src, SDValue Mask, SDValue Base,
15154 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15156 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15157 assert(C && "Invalid scale type");
15158 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15159 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15160 SDValue Segment = DAG.getRegister(0, MVT::i32);
15161 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15162 Index.getSimpleValueType().getVectorNumElements());
15164 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15166 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15168 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15169 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15170 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15171 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15172 return SDValue(Res, 1);
15175 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15176 SDValue Mask, SDValue Base, SDValue Index,
15177 SDValue ScaleOp, SDValue Chain) {
15179 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15180 assert(C && "Invalid scale type");
15181 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15182 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15183 SDValue Segment = DAG.getRegister(0, MVT::i32);
15185 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15187 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15189 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15191 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15192 //SDVTList VTs = DAG.getVTList(MVT::Other);
15193 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15194 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15195 return SDValue(Res, 0);
15198 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15199 // read performance monitor counters (x86_rdpmc).
15200 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15201 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15202 SmallVectorImpl<SDValue> &Results) {
15203 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15204 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15207 // The ECX register is used to select the index of the performance counter
15209 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15211 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15213 // Reads the content of a 64-bit performance counter and returns it in the
15214 // registers EDX:EAX.
15215 if (Subtarget->is64Bit()) {
15216 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15217 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15220 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15221 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15224 Chain = HI.getValue(1);
15226 if (Subtarget->is64Bit()) {
15227 // The EAX register is loaded with the low-order 32 bits. The EDX register
15228 // is loaded with the supported high-order bits of the counter.
15229 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15230 DAG.getConstant(32, MVT::i8));
15231 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15232 Results.push_back(Chain);
15236 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15237 SDValue Ops[] = { LO, HI };
15238 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15239 Results.push_back(Pair);
15240 Results.push_back(Chain);
15243 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15244 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15245 // also used to custom lower READCYCLECOUNTER nodes.
15246 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15247 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15248 SmallVectorImpl<SDValue> &Results) {
15249 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15250 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15253 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15254 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15255 // and the EAX register is loaded with the low-order 32 bits.
15256 if (Subtarget->is64Bit()) {
15257 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15258 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15261 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15262 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15265 SDValue Chain = HI.getValue(1);
15267 if (Opcode == X86ISD::RDTSCP_DAG) {
15268 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15270 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15271 // the ECX register. Add 'ecx' explicitly to the chain.
15272 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15274 // Explicitly store the content of ECX at the location passed in input
15275 // to the 'rdtscp' intrinsic.
15276 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15277 MachinePointerInfo(), false, false, 0);
15280 if (Subtarget->is64Bit()) {
15281 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15282 // the EAX register is loaded with the low-order 32 bits.
15283 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15284 DAG.getConstant(32, MVT::i8));
15285 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15286 Results.push_back(Chain);
15290 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15291 SDValue Ops[] = { LO, HI };
15292 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15293 Results.push_back(Pair);
15294 Results.push_back(Chain);
15297 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15298 SelectionDAG &DAG) {
15299 SmallVector<SDValue, 2> Results;
15301 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15303 return DAG.getMergeValues(Results, DL);
15307 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15308 SelectionDAG &DAG) {
15309 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15311 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15316 switch(IntrData->Type) {
15318 llvm_unreachable("Unknown Intrinsic Type");
15322 // Emit the node with the right value type.
15323 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15324 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15326 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15327 // Otherwise return the value from Rand, which is always 0, casted to i32.
15328 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15329 DAG.getConstant(1, Op->getValueType(1)),
15330 DAG.getConstant(X86::COND_B, MVT::i32),
15331 SDValue(Result.getNode(), 1) };
15332 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15333 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15336 // Return { result, isValid, chain }.
15337 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15338 SDValue(Result.getNode(), 2));
15341 //gather(v1, mask, index, base, scale);
15342 SDValue Chain = Op.getOperand(0);
15343 SDValue Src = Op.getOperand(2);
15344 SDValue Base = Op.getOperand(3);
15345 SDValue Index = Op.getOperand(4);
15346 SDValue Mask = Op.getOperand(5);
15347 SDValue Scale = Op.getOperand(6);
15348 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15352 //scatter(base, mask, index, v1, scale);
15353 SDValue Chain = Op.getOperand(0);
15354 SDValue Base = Op.getOperand(2);
15355 SDValue Mask = Op.getOperand(3);
15356 SDValue Index = Op.getOperand(4);
15357 SDValue Src = Op.getOperand(5);
15358 SDValue Scale = Op.getOperand(6);
15359 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15362 SDValue Hint = Op.getOperand(6);
15364 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15365 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15366 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15367 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15368 SDValue Chain = Op.getOperand(0);
15369 SDValue Mask = Op.getOperand(2);
15370 SDValue Index = Op.getOperand(3);
15371 SDValue Base = Op.getOperand(4);
15372 SDValue Scale = Op.getOperand(5);
15373 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15375 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15377 SmallVector<SDValue, 2> Results;
15378 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15379 return DAG.getMergeValues(Results, dl);
15381 // Read Performance Monitoring Counters.
15383 SmallVector<SDValue, 2> Results;
15384 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15385 return DAG.getMergeValues(Results, dl);
15387 // XTEST intrinsics.
15389 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15390 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15391 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15392 DAG.getConstant(X86::COND_NE, MVT::i8),
15394 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15395 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15396 Ret, SDValue(InTrans.getNode(), 1));
15400 SmallVector<SDValue, 2> Results;
15401 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15402 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15403 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15404 DAG.getConstant(-1, MVT::i8));
15405 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15406 Op.getOperand(4), GenCF.getValue(1));
15407 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15408 Op.getOperand(5), MachinePointerInfo(),
15410 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15411 DAG.getConstant(X86::COND_B, MVT::i8),
15413 Results.push_back(SetCC);
15414 Results.push_back(Store);
15415 return DAG.getMergeValues(Results, dl);
15420 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15421 SelectionDAG &DAG) const {
15422 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15423 MFI->setReturnAddressIsTaken(true);
15425 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15428 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15430 EVT PtrVT = getPointerTy();
15433 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15434 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15435 DAG.getSubtarget().getRegisterInfo());
15436 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15437 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15438 DAG.getNode(ISD::ADD, dl, PtrVT,
15439 FrameAddr, Offset),
15440 MachinePointerInfo(), false, false, false, 0);
15443 // Just load the return address.
15444 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15445 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15446 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15449 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15450 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15451 MFI->setFrameAddressIsTaken(true);
15453 EVT VT = Op.getValueType();
15454 SDLoc dl(Op); // FIXME probably not meaningful
15455 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15456 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15457 DAG.getSubtarget().getRegisterInfo());
15458 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15459 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15460 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15461 "Invalid Frame Register!");
15462 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15464 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15465 MachinePointerInfo(),
15466 false, false, false, 0);
15470 // FIXME? Maybe this could be a TableGen attribute on some registers and
15471 // this table could be generated automatically from RegInfo.
15472 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15474 unsigned Reg = StringSwitch<unsigned>(RegName)
15475 .Case("esp", X86::ESP)
15476 .Case("rsp", X86::RSP)
15480 report_fatal_error("Invalid register name global variable");
15483 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15484 SelectionDAG &DAG) const {
15485 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15486 DAG.getSubtarget().getRegisterInfo());
15487 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15490 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15491 SDValue Chain = Op.getOperand(0);
15492 SDValue Offset = Op.getOperand(1);
15493 SDValue Handler = Op.getOperand(2);
15496 EVT PtrVT = getPointerTy();
15497 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15498 DAG.getSubtarget().getRegisterInfo());
15499 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15500 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15501 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15502 "Invalid Frame Register!");
15503 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15504 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15506 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15507 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15508 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15509 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15511 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15513 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15514 DAG.getRegister(StoreAddrReg, PtrVT));
15517 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15518 SelectionDAG &DAG) const {
15520 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15521 DAG.getVTList(MVT::i32, MVT::Other),
15522 Op.getOperand(0), Op.getOperand(1));
15525 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15526 SelectionDAG &DAG) const {
15528 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15529 Op.getOperand(0), Op.getOperand(1));
15532 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15533 return Op.getOperand(0);
15536 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15537 SelectionDAG &DAG) const {
15538 SDValue Root = Op.getOperand(0);
15539 SDValue Trmp = Op.getOperand(1); // trampoline
15540 SDValue FPtr = Op.getOperand(2); // nested function
15541 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15544 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15545 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15547 if (Subtarget->is64Bit()) {
15548 SDValue OutChains[6];
15550 // Large code-model.
15551 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15552 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15554 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15555 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15557 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15559 // Load the pointer to the nested function into R11.
15560 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15561 SDValue Addr = Trmp;
15562 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15563 Addr, MachinePointerInfo(TrmpAddr),
15566 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15567 DAG.getConstant(2, MVT::i64));
15568 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15569 MachinePointerInfo(TrmpAddr, 2),
15572 // Load the 'nest' parameter value into R10.
15573 // R10 is specified in X86CallingConv.td
15574 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15575 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15576 DAG.getConstant(10, MVT::i64));
15577 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15578 Addr, MachinePointerInfo(TrmpAddr, 10),
15581 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15582 DAG.getConstant(12, MVT::i64));
15583 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15584 MachinePointerInfo(TrmpAddr, 12),
15587 // Jump to the nested function.
15588 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15589 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15590 DAG.getConstant(20, MVT::i64));
15591 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15592 Addr, MachinePointerInfo(TrmpAddr, 20),
15595 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15596 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15597 DAG.getConstant(22, MVT::i64));
15598 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15599 MachinePointerInfo(TrmpAddr, 22),
15602 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15604 const Function *Func =
15605 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15606 CallingConv::ID CC = Func->getCallingConv();
15611 llvm_unreachable("Unsupported calling convention");
15612 case CallingConv::C:
15613 case CallingConv::X86_StdCall: {
15614 // Pass 'nest' parameter in ECX.
15615 // Must be kept in sync with X86CallingConv.td
15616 NestReg = X86::ECX;
15618 // Check that ECX wasn't needed by an 'inreg' parameter.
15619 FunctionType *FTy = Func->getFunctionType();
15620 const AttributeSet &Attrs = Func->getAttributes();
15622 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15623 unsigned InRegCount = 0;
15626 for (FunctionType::param_iterator I = FTy->param_begin(),
15627 E = FTy->param_end(); I != E; ++I, ++Idx)
15628 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15629 // FIXME: should only count parameters that are lowered to integers.
15630 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15632 if (InRegCount > 2) {
15633 report_fatal_error("Nest register in use - reduce number of inreg"
15639 case CallingConv::X86_FastCall:
15640 case CallingConv::X86_ThisCall:
15641 case CallingConv::Fast:
15642 // Pass 'nest' parameter in EAX.
15643 // Must be kept in sync with X86CallingConv.td
15644 NestReg = X86::EAX;
15648 SDValue OutChains[4];
15649 SDValue Addr, Disp;
15651 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15652 DAG.getConstant(10, MVT::i32));
15653 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15655 // This is storing the opcode for MOV32ri.
15656 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15657 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15658 OutChains[0] = DAG.getStore(Root, dl,
15659 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15660 Trmp, MachinePointerInfo(TrmpAddr),
15663 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15664 DAG.getConstant(1, MVT::i32));
15665 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15666 MachinePointerInfo(TrmpAddr, 1),
15669 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15670 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15671 DAG.getConstant(5, MVT::i32));
15672 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15673 MachinePointerInfo(TrmpAddr, 5),
15676 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15677 DAG.getConstant(6, MVT::i32));
15678 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15679 MachinePointerInfo(TrmpAddr, 6),
15682 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15686 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15687 SelectionDAG &DAG) const {
15689 The rounding mode is in bits 11:10 of FPSR, and has the following
15691 00 Round to nearest
15696 FLT_ROUNDS, on the other hand, expects the following:
15703 To perform the conversion, we do:
15704 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15707 MachineFunction &MF = DAG.getMachineFunction();
15708 const TargetMachine &TM = MF.getTarget();
15709 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15710 unsigned StackAlignment = TFI.getStackAlignment();
15711 MVT VT = Op.getSimpleValueType();
15714 // Save FP Control Word to stack slot
15715 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15716 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15718 MachineMemOperand *MMO =
15719 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15720 MachineMemOperand::MOStore, 2, 2);
15722 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15723 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15724 DAG.getVTList(MVT::Other),
15725 Ops, MVT::i16, MMO);
15727 // Load FP Control Word from stack slot
15728 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15729 MachinePointerInfo(), false, false, false, 0);
15731 // Transform as necessary
15733 DAG.getNode(ISD::SRL, DL, MVT::i16,
15734 DAG.getNode(ISD::AND, DL, MVT::i16,
15735 CWD, DAG.getConstant(0x800, MVT::i16)),
15736 DAG.getConstant(11, MVT::i8));
15738 DAG.getNode(ISD::SRL, DL, MVT::i16,
15739 DAG.getNode(ISD::AND, DL, MVT::i16,
15740 CWD, DAG.getConstant(0x400, MVT::i16)),
15741 DAG.getConstant(9, MVT::i8));
15744 DAG.getNode(ISD::AND, DL, MVT::i16,
15745 DAG.getNode(ISD::ADD, DL, MVT::i16,
15746 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15747 DAG.getConstant(1, MVT::i16)),
15748 DAG.getConstant(3, MVT::i16));
15750 return DAG.getNode((VT.getSizeInBits() < 16 ?
15751 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15754 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15755 MVT VT = Op.getSimpleValueType();
15757 unsigned NumBits = VT.getSizeInBits();
15760 Op = Op.getOperand(0);
15761 if (VT == MVT::i8) {
15762 // Zero extend to i32 since there is not an i8 bsr.
15764 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15767 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15768 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15769 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15771 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15774 DAG.getConstant(NumBits+NumBits-1, OpVT),
15775 DAG.getConstant(X86::COND_E, MVT::i8),
15778 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15780 // Finally xor with NumBits-1.
15781 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15784 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15788 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15789 MVT VT = Op.getSimpleValueType();
15791 unsigned NumBits = VT.getSizeInBits();
15794 Op = Op.getOperand(0);
15795 if (VT == MVT::i8) {
15796 // Zero extend to i32 since there is not an i8 bsr.
15798 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15801 // Issue a bsr (scan bits in reverse).
15802 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15803 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15805 // And xor with NumBits-1.
15806 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15809 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15813 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15814 MVT VT = Op.getSimpleValueType();
15815 unsigned NumBits = VT.getSizeInBits();
15817 Op = Op.getOperand(0);
15819 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15820 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15821 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15823 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15826 DAG.getConstant(NumBits, VT),
15827 DAG.getConstant(X86::COND_E, MVT::i8),
15830 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15833 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15834 // ones, and then concatenate the result back.
15835 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15836 MVT VT = Op.getSimpleValueType();
15838 assert(VT.is256BitVector() && VT.isInteger() &&
15839 "Unsupported value type for operation");
15841 unsigned NumElems = VT.getVectorNumElements();
15844 // Extract the LHS vectors
15845 SDValue LHS = Op.getOperand(0);
15846 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15847 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15849 // Extract the RHS vectors
15850 SDValue RHS = Op.getOperand(1);
15851 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15852 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15854 MVT EltVT = VT.getVectorElementType();
15855 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15857 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15858 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15859 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15862 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15863 assert(Op.getSimpleValueType().is256BitVector() &&
15864 Op.getSimpleValueType().isInteger() &&
15865 "Only handle AVX 256-bit vector integer operation");
15866 return Lower256IntArith(Op, DAG);
15869 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15870 assert(Op.getSimpleValueType().is256BitVector() &&
15871 Op.getSimpleValueType().isInteger() &&
15872 "Only handle AVX 256-bit vector integer operation");
15873 return Lower256IntArith(Op, DAG);
15876 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15877 SelectionDAG &DAG) {
15879 MVT VT = Op.getSimpleValueType();
15881 // Decompose 256-bit ops into smaller 128-bit ops.
15882 if (VT.is256BitVector() && !Subtarget->hasInt256())
15883 return Lower256IntArith(Op, DAG);
15885 SDValue A = Op.getOperand(0);
15886 SDValue B = Op.getOperand(1);
15888 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15889 if (VT == MVT::v4i32) {
15890 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15891 "Should not custom lower when pmuldq is available!");
15893 // Extract the odd parts.
15894 static const int UnpackMask[] = { 1, -1, 3, -1 };
15895 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15896 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15898 // Multiply the even parts.
15899 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15900 // Now multiply odd parts.
15901 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15903 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15904 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15906 // Merge the two vectors back together with a shuffle. This expands into 2
15908 static const int ShufMask[] = { 0, 4, 2, 6 };
15909 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15912 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15913 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15915 // Ahi = psrlqi(a, 32);
15916 // Bhi = psrlqi(b, 32);
15918 // AloBlo = pmuludq(a, b);
15919 // AloBhi = pmuludq(a, Bhi);
15920 // AhiBlo = pmuludq(Ahi, b);
15922 // AloBhi = psllqi(AloBhi, 32);
15923 // AhiBlo = psllqi(AhiBlo, 32);
15924 // return AloBlo + AloBhi + AhiBlo;
15926 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15927 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15929 // Bit cast to 32-bit vectors for MULUDQ
15930 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15931 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15932 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15933 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15934 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15935 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15937 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15938 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15939 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15941 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15942 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15944 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15945 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15948 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15949 assert(Subtarget->isTargetWin64() && "Unexpected target");
15950 EVT VT = Op.getValueType();
15951 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15952 "Unexpected return type for lowering");
15956 switch (Op->getOpcode()) {
15957 default: llvm_unreachable("Unexpected request for libcall!");
15958 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15959 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15960 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15961 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15962 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15963 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15967 SDValue InChain = DAG.getEntryNode();
15969 TargetLowering::ArgListTy Args;
15970 TargetLowering::ArgListEntry Entry;
15971 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15972 EVT ArgVT = Op->getOperand(i).getValueType();
15973 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15974 "Unexpected argument type for lowering");
15975 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15976 Entry.Node = StackPtr;
15977 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15979 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15980 Entry.Ty = PointerType::get(ArgTy,0);
15981 Entry.isSExt = false;
15982 Entry.isZExt = false;
15983 Args.push_back(Entry);
15986 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15989 TargetLowering::CallLoweringInfo CLI(DAG);
15990 CLI.setDebugLoc(dl).setChain(InChain)
15991 .setCallee(getLibcallCallingConv(LC),
15992 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15993 Callee, std::move(Args), 0)
15994 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15996 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15997 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16000 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16001 SelectionDAG &DAG) {
16002 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16003 EVT VT = Op0.getValueType();
16006 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16007 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16009 // PMULxD operations multiply each even value (starting at 0) of LHS with
16010 // the related value of RHS and produce a widen result.
16011 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16012 // => <2 x i64> <ae|cg>
16014 // In other word, to have all the results, we need to perform two PMULxD:
16015 // 1. one with the even values.
16016 // 2. one with the odd values.
16017 // To achieve #2, with need to place the odd values at an even position.
16019 // Place the odd value at an even position (basically, shift all values 1
16020 // step to the left):
16021 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16022 // <a|b|c|d> => <b|undef|d|undef>
16023 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16024 // <e|f|g|h> => <f|undef|h|undef>
16025 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16027 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16029 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16030 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16032 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16033 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16034 // => <2 x i64> <ae|cg>
16035 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16036 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16037 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16038 // => <2 x i64> <bf|dh>
16039 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16040 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16042 // Shuffle it back into the right order.
16043 SDValue Highs, Lows;
16044 if (VT == MVT::v8i32) {
16045 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16046 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16047 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16048 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16050 const int HighMask[] = {1, 5, 3, 7};
16051 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16052 const int LowMask[] = {0, 4, 2, 6};
16053 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16056 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16057 // unsigned multiply.
16058 if (IsSigned && !Subtarget->hasSSE41()) {
16060 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16061 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16062 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16063 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16064 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16066 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16067 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16070 // The first result of MUL_LOHI is actually the low value, followed by the
16072 SDValue Ops[] = {Lows, Highs};
16073 return DAG.getMergeValues(Ops, dl);
16076 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16077 const X86Subtarget *Subtarget) {
16078 MVT VT = Op.getSimpleValueType();
16080 SDValue R = Op.getOperand(0);
16081 SDValue Amt = Op.getOperand(1);
16083 // Optimize shl/srl/sra with constant shift amount.
16084 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16085 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16086 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16088 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16089 (Subtarget->hasInt256() &&
16090 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16091 (Subtarget->hasAVX512() &&
16092 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16093 if (Op.getOpcode() == ISD::SHL)
16094 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16096 if (Op.getOpcode() == ISD::SRL)
16097 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16099 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16100 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16104 if (VT == MVT::v16i8) {
16105 if (Op.getOpcode() == ISD::SHL) {
16106 // Make a large shift.
16107 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16108 MVT::v8i16, R, ShiftAmt,
16110 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16111 // Zero out the rightmost bits.
16112 SmallVector<SDValue, 16> V(16,
16113 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16115 return DAG.getNode(ISD::AND, dl, VT, SHL,
16116 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16118 if (Op.getOpcode() == ISD::SRL) {
16119 // Make a large shift.
16120 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16121 MVT::v8i16, R, ShiftAmt,
16123 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16124 // Zero out the leftmost bits.
16125 SmallVector<SDValue, 16> V(16,
16126 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16128 return DAG.getNode(ISD::AND, dl, VT, SRL,
16129 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16131 if (Op.getOpcode() == ISD::SRA) {
16132 if (ShiftAmt == 7) {
16133 // R s>> 7 === R s< 0
16134 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16135 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16138 // R s>> a === ((R u>> a) ^ m) - m
16139 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16140 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16142 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16143 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16144 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16147 llvm_unreachable("Unknown shift opcode.");
16150 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16151 if (Op.getOpcode() == ISD::SHL) {
16152 // Make a large shift.
16153 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16154 MVT::v16i16, R, ShiftAmt,
16156 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16157 // Zero out the rightmost bits.
16158 SmallVector<SDValue, 32> V(32,
16159 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16161 return DAG.getNode(ISD::AND, dl, VT, SHL,
16162 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16164 if (Op.getOpcode() == ISD::SRL) {
16165 // Make a large shift.
16166 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16167 MVT::v16i16, R, ShiftAmt,
16169 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16170 // Zero out the leftmost bits.
16171 SmallVector<SDValue, 32> V(32,
16172 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16174 return DAG.getNode(ISD::AND, dl, VT, SRL,
16175 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16177 if (Op.getOpcode() == ISD::SRA) {
16178 if (ShiftAmt == 7) {
16179 // R s>> 7 === R s< 0
16180 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16181 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16184 // R s>> a === ((R u>> a) ^ m) - m
16185 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16186 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16188 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16189 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16190 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16193 llvm_unreachable("Unknown shift opcode.");
16198 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16199 if (!Subtarget->is64Bit() &&
16200 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16201 Amt.getOpcode() == ISD::BITCAST &&
16202 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16203 Amt = Amt.getOperand(0);
16204 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16205 VT.getVectorNumElements();
16206 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16207 uint64_t ShiftAmt = 0;
16208 for (unsigned i = 0; i != Ratio; ++i) {
16209 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16213 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16215 // Check remaining shift amounts.
16216 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16217 uint64_t ShAmt = 0;
16218 for (unsigned j = 0; j != Ratio; ++j) {
16219 ConstantSDNode *C =
16220 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16224 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16226 if (ShAmt != ShiftAmt)
16229 switch (Op.getOpcode()) {
16231 llvm_unreachable("Unknown shift opcode!");
16233 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16236 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16239 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16247 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16248 const X86Subtarget* Subtarget) {
16249 MVT VT = Op.getSimpleValueType();
16251 SDValue R = Op.getOperand(0);
16252 SDValue Amt = Op.getOperand(1);
16254 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16255 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16256 (Subtarget->hasInt256() &&
16257 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16258 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16259 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16261 EVT EltVT = VT.getVectorElementType();
16263 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16264 unsigned NumElts = VT.getVectorNumElements();
16266 for (i = 0; i != NumElts; ++i) {
16267 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16271 for (j = i; j != NumElts; ++j) {
16272 SDValue Arg = Amt.getOperand(j);
16273 if (Arg.getOpcode() == ISD::UNDEF) continue;
16274 if (Arg != Amt.getOperand(i))
16277 if (i != NumElts && j == NumElts)
16278 BaseShAmt = Amt.getOperand(i);
16280 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16281 Amt = Amt.getOperand(0);
16282 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16283 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16284 SDValue InVec = Amt.getOperand(0);
16285 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16286 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16288 for (; i != NumElts; ++i) {
16289 SDValue Arg = InVec.getOperand(i);
16290 if (Arg.getOpcode() == ISD::UNDEF) continue;
16294 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16295 if (ConstantSDNode *C =
16296 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16297 unsigned SplatIdx =
16298 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16299 if (C->getZExtValue() == SplatIdx)
16300 BaseShAmt = InVec.getOperand(1);
16303 if (!BaseShAmt.getNode())
16304 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16305 DAG.getIntPtrConstant(0));
16309 if (BaseShAmt.getNode()) {
16310 if (EltVT.bitsGT(MVT::i32))
16311 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16312 else if (EltVT.bitsLT(MVT::i32))
16313 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16315 switch (Op.getOpcode()) {
16317 llvm_unreachable("Unknown shift opcode!");
16319 switch (VT.SimpleTy) {
16320 default: return SDValue();
16329 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16332 switch (VT.SimpleTy) {
16333 default: return SDValue();
16340 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16343 switch (VT.SimpleTy) {
16344 default: return SDValue();
16353 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16359 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16360 if (!Subtarget->is64Bit() &&
16361 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16362 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16363 Amt.getOpcode() == ISD::BITCAST &&
16364 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16365 Amt = Amt.getOperand(0);
16366 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16367 VT.getVectorNumElements();
16368 std::vector<SDValue> Vals(Ratio);
16369 for (unsigned i = 0; i != Ratio; ++i)
16370 Vals[i] = Amt.getOperand(i);
16371 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16372 for (unsigned j = 0; j != Ratio; ++j)
16373 if (Vals[j] != Amt.getOperand(i + j))
16376 switch (Op.getOpcode()) {
16378 llvm_unreachable("Unknown shift opcode!");
16380 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16382 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16384 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16391 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16392 SelectionDAG &DAG) {
16393 MVT VT = Op.getSimpleValueType();
16395 SDValue R = Op.getOperand(0);
16396 SDValue Amt = Op.getOperand(1);
16399 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16400 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16402 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16406 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16410 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16412 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16413 if (Subtarget->hasInt256()) {
16414 if (Op.getOpcode() == ISD::SRL &&
16415 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16416 VT == MVT::v4i64 || VT == MVT::v8i32))
16418 if (Op.getOpcode() == ISD::SHL &&
16419 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16420 VT == MVT::v4i64 || VT == MVT::v8i32))
16422 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16426 // If possible, lower this packed shift into a vector multiply instead of
16427 // expanding it into a sequence of scalar shifts.
16428 // Do this only if the vector shift count is a constant build_vector.
16429 if (Op.getOpcode() == ISD::SHL &&
16430 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16431 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16432 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16433 SmallVector<SDValue, 8> Elts;
16434 EVT SVT = VT.getScalarType();
16435 unsigned SVTBits = SVT.getSizeInBits();
16436 const APInt &One = APInt(SVTBits, 1);
16437 unsigned NumElems = VT.getVectorNumElements();
16439 for (unsigned i=0; i !=NumElems; ++i) {
16440 SDValue Op = Amt->getOperand(i);
16441 if (Op->getOpcode() == ISD::UNDEF) {
16442 Elts.push_back(Op);
16446 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16447 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16448 uint64_t ShAmt = C.getZExtValue();
16449 if (ShAmt >= SVTBits) {
16450 Elts.push_back(DAG.getUNDEF(SVT));
16453 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16455 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16456 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16459 // Lower SHL with variable shift amount.
16460 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16461 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16463 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16464 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16465 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16466 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16469 // If possible, lower this shift as a sequence of two shifts by
16470 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16472 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16474 // Could be rewritten as:
16475 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16477 // The advantage is that the two shifts from the example would be
16478 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16479 // the vector shift into four scalar shifts plus four pairs of vector
16481 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16482 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16483 unsigned TargetOpcode = X86ISD::MOVSS;
16484 bool CanBeSimplified;
16485 // The splat value for the first packed shift (the 'X' from the example).
16486 SDValue Amt1 = Amt->getOperand(0);
16487 // The splat value for the second packed shift (the 'Y' from the example).
16488 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16489 Amt->getOperand(2);
16491 // See if it is possible to replace this node with a sequence of
16492 // two shifts followed by a MOVSS/MOVSD
16493 if (VT == MVT::v4i32) {
16494 // Check if it is legal to use a MOVSS.
16495 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16496 Amt2 == Amt->getOperand(3);
16497 if (!CanBeSimplified) {
16498 // Otherwise, check if we can still simplify this node using a MOVSD.
16499 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16500 Amt->getOperand(2) == Amt->getOperand(3);
16501 TargetOpcode = X86ISD::MOVSD;
16502 Amt2 = Amt->getOperand(2);
16505 // Do similar checks for the case where the machine value type
16507 CanBeSimplified = Amt1 == Amt->getOperand(1);
16508 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16509 CanBeSimplified = Amt2 == Amt->getOperand(i);
16511 if (!CanBeSimplified) {
16512 TargetOpcode = X86ISD::MOVSD;
16513 CanBeSimplified = true;
16514 Amt2 = Amt->getOperand(4);
16515 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16516 CanBeSimplified = Amt1 == Amt->getOperand(i);
16517 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16518 CanBeSimplified = Amt2 == Amt->getOperand(j);
16522 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16523 isa<ConstantSDNode>(Amt2)) {
16524 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16525 EVT CastVT = MVT::v4i32;
16527 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16528 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16530 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16531 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16532 if (TargetOpcode == X86ISD::MOVSD)
16533 CastVT = MVT::v2i64;
16534 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16535 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16536 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16538 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16542 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16543 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16546 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16547 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16549 // Turn 'a' into a mask suitable for VSELECT
16550 SDValue VSelM = DAG.getConstant(0x80, VT);
16551 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16552 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16554 SDValue CM1 = DAG.getConstant(0x0f, VT);
16555 SDValue CM2 = DAG.getConstant(0x3f, VT);
16557 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16558 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16559 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16560 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16561 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16564 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16565 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16566 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16568 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16569 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16570 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16571 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16572 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16575 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16576 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16577 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16579 // return VSELECT(r, r+r, a);
16580 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16581 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16585 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16586 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16587 // solution better.
16588 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16589 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16591 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16592 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16593 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16594 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16595 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16598 // Decompose 256-bit shifts into smaller 128-bit shifts.
16599 if (VT.is256BitVector()) {
16600 unsigned NumElems = VT.getVectorNumElements();
16601 MVT EltVT = VT.getVectorElementType();
16602 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16604 // Extract the two vectors
16605 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16606 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16608 // Recreate the shift amount vectors
16609 SDValue Amt1, Amt2;
16610 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16611 // Constant shift amount
16612 SmallVector<SDValue, 4> Amt1Csts;
16613 SmallVector<SDValue, 4> Amt2Csts;
16614 for (unsigned i = 0; i != NumElems/2; ++i)
16615 Amt1Csts.push_back(Amt->getOperand(i));
16616 for (unsigned i = NumElems/2; i != NumElems; ++i)
16617 Amt2Csts.push_back(Amt->getOperand(i));
16619 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16620 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16622 // Variable shift amount
16623 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16624 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16627 // Issue new vector shifts for the smaller types
16628 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16629 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16631 // Concatenate the result back
16632 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16638 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16639 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16640 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16641 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16642 // has only one use.
16643 SDNode *N = Op.getNode();
16644 SDValue LHS = N->getOperand(0);
16645 SDValue RHS = N->getOperand(1);
16646 unsigned BaseOp = 0;
16649 switch (Op.getOpcode()) {
16650 default: llvm_unreachable("Unknown ovf instruction!");
16652 // A subtract of one will be selected as a INC. Note that INC doesn't
16653 // set CF, so we can't do this for UADDO.
16654 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16656 BaseOp = X86ISD::INC;
16657 Cond = X86::COND_O;
16660 BaseOp = X86ISD::ADD;
16661 Cond = X86::COND_O;
16664 BaseOp = X86ISD::ADD;
16665 Cond = X86::COND_B;
16668 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16669 // set CF, so we can't do this for USUBO.
16670 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16672 BaseOp = X86ISD::DEC;
16673 Cond = X86::COND_O;
16676 BaseOp = X86ISD::SUB;
16677 Cond = X86::COND_O;
16680 BaseOp = X86ISD::SUB;
16681 Cond = X86::COND_B;
16684 BaseOp = X86ISD::SMUL;
16685 Cond = X86::COND_O;
16687 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16688 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16690 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16693 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16694 DAG.getConstant(X86::COND_O, MVT::i32),
16695 SDValue(Sum.getNode(), 2));
16697 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16701 // Also sets EFLAGS.
16702 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16703 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16706 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16707 DAG.getConstant(Cond, MVT::i32),
16708 SDValue(Sum.getNode(), 1));
16710 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16713 // Sign extension of the low part of vector elements. This may be used either
16714 // when sign extend instructions are not available or if the vector element
16715 // sizes already match the sign-extended size. If the vector elements are in
16716 // their pre-extended size and sign extend instructions are available, that will
16717 // be handled by LowerSIGN_EXTEND.
16718 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16719 SelectionDAG &DAG) const {
16721 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16722 MVT VT = Op.getSimpleValueType();
16724 if (!Subtarget->hasSSE2() || !VT.isVector())
16727 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16728 ExtraVT.getScalarType().getSizeInBits();
16730 switch (VT.SimpleTy) {
16731 default: return SDValue();
16734 if (!Subtarget->hasFp256())
16736 if (!Subtarget->hasInt256()) {
16737 // needs to be split
16738 unsigned NumElems = VT.getVectorNumElements();
16740 // Extract the LHS vectors
16741 SDValue LHS = Op.getOperand(0);
16742 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16743 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16745 MVT EltVT = VT.getVectorElementType();
16746 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16748 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16749 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16750 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16752 SDValue Extra = DAG.getValueType(ExtraVT);
16754 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16755 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16757 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16762 SDValue Op0 = Op.getOperand(0);
16764 // This is a sign extension of some low part of vector elements without
16765 // changing the size of the vector elements themselves:
16766 // Shift-Left + Shift-Right-Algebraic.
16767 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
16769 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
16775 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16776 SelectionDAG &DAG) {
16778 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16779 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16780 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16781 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16783 // The only fence that needs an instruction is a sequentially-consistent
16784 // cross-thread fence.
16785 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16786 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16787 // no-sse2). There isn't any reason to disable it if the target processor
16789 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16790 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16792 SDValue Chain = Op.getOperand(0);
16793 SDValue Zero = DAG.getConstant(0, MVT::i32);
16795 DAG.getRegister(X86::ESP, MVT::i32), // Base
16796 DAG.getTargetConstant(1, MVT::i8), // Scale
16797 DAG.getRegister(0, MVT::i32), // Index
16798 DAG.getTargetConstant(0, MVT::i32), // Disp
16799 DAG.getRegister(0, MVT::i32), // Segment.
16803 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16804 return SDValue(Res, 0);
16807 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16808 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16811 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16812 SelectionDAG &DAG) {
16813 MVT T = Op.getSimpleValueType();
16817 switch(T.SimpleTy) {
16818 default: llvm_unreachable("Invalid value type!");
16819 case MVT::i8: Reg = X86::AL; size = 1; break;
16820 case MVT::i16: Reg = X86::AX; size = 2; break;
16821 case MVT::i32: Reg = X86::EAX; size = 4; break;
16823 assert(Subtarget->is64Bit() && "Node not type legal!");
16824 Reg = X86::RAX; size = 8;
16827 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16828 Op.getOperand(2), SDValue());
16829 SDValue Ops[] = { cpIn.getValue(0),
16832 DAG.getTargetConstant(size, MVT::i8),
16833 cpIn.getValue(1) };
16834 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16835 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16836 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16840 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16841 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16842 MVT::i32, cpOut.getValue(2));
16843 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16844 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16846 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16847 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16848 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16852 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16853 SelectionDAG &DAG) {
16854 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16855 MVT DstVT = Op.getSimpleValueType();
16857 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16858 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16859 if (DstVT != MVT::f64)
16860 // This conversion needs to be expanded.
16863 SDValue InVec = Op->getOperand(0);
16865 unsigned NumElts = SrcVT.getVectorNumElements();
16866 EVT SVT = SrcVT.getVectorElementType();
16868 // Widen the vector in input in the case of MVT::v2i32.
16869 // Example: from MVT::v2i32 to MVT::v4i32.
16870 SmallVector<SDValue, 16> Elts;
16871 for (unsigned i = 0, e = NumElts; i != e; ++i)
16872 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16873 DAG.getIntPtrConstant(i)));
16875 // Explicitly mark the extra elements as Undef.
16876 SDValue Undef = DAG.getUNDEF(SVT);
16877 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16878 Elts.push_back(Undef);
16880 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16881 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16882 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16883 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16884 DAG.getIntPtrConstant(0));
16887 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16888 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16889 assert((DstVT == MVT::i64 ||
16890 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16891 "Unexpected custom BITCAST");
16892 // i64 <=> MMX conversions are Legal.
16893 if (SrcVT==MVT::i64 && DstVT.isVector())
16895 if (DstVT==MVT::i64 && SrcVT.isVector())
16897 // MMX <=> MMX conversions are Legal.
16898 if (SrcVT.isVector() && DstVT.isVector())
16900 // All other conversions need to be expanded.
16904 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16905 SDNode *Node = Op.getNode();
16907 EVT T = Node->getValueType(0);
16908 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16909 DAG.getConstant(0, T), Node->getOperand(2));
16910 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16911 cast<AtomicSDNode>(Node)->getMemoryVT(),
16912 Node->getOperand(0),
16913 Node->getOperand(1), negOp,
16914 cast<AtomicSDNode>(Node)->getMemOperand(),
16915 cast<AtomicSDNode>(Node)->getOrdering(),
16916 cast<AtomicSDNode>(Node)->getSynchScope());
16919 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16920 SDNode *Node = Op.getNode();
16922 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16924 // Convert seq_cst store -> xchg
16925 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16926 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16927 // (The only way to get a 16-byte store is cmpxchg16b)
16928 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16929 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16930 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16931 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16932 cast<AtomicSDNode>(Node)->getMemoryVT(),
16933 Node->getOperand(0),
16934 Node->getOperand(1), Node->getOperand(2),
16935 cast<AtomicSDNode>(Node)->getMemOperand(),
16936 cast<AtomicSDNode>(Node)->getOrdering(),
16937 cast<AtomicSDNode>(Node)->getSynchScope());
16938 return Swap.getValue(1);
16940 // Other atomic stores have a simple pattern.
16944 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16945 EVT VT = Op.getNode()->getSimpleValueType(0);
16947 // Let legalize expand this if it isn't a legal type yet.
16948 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16951 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16954 bool ExtraOp = false;
16955 switch (Op.getOpcode()) {
16956 default: llvm_unreachable("Invalid code");
16957 case ISD::ADDC: Opc = X86ISD::ADD; break;
16958 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16959 case ISD::SUBC: Opc = X86ISD::SUB; break;
16960 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16964 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16966 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16967 Op.getOperand(1), Op.getOperand(2));
16970 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16971 SelectionDAG &DAG) {
16972 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16974 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16975 // which returns the values as { float, float } (in XMM0) or
16976 // { double, double } (which is returned in XMM0, XMM1).
16978 SDValue Arg = Op.getOperand(0);
16979 EVT ArgVT = Arg.getValueType();
16980 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16982 TargetLowering::ArgListTy Args;
16983 TargetLowering::ArgListEntry Entry;
16987 Entry.isSExt = false;
16988 Entry.isZExt = false;
16989 Args.push_back(Entry);
16991 bool isF64 = ArgVT == MVT::f64;
16992 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16993 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16994 // the results are returned via SRet in memory.
16995 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16997 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16999 Type *RetTy = isF64
17000 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17001 : (Type*)VectorType::get(ArgTy, 4);
17003 TargetLowering::CallLoweringInfo CLI(DAG);
17004 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17005 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17007 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17010 // Returned in xmm0 and xmm1.
17011 return CallResult.first;
17013 // Returned in bits 0:31 and 32:64 xmm0.
17014 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17015 CallResult.first, DAG.getIntPtrConstant(0));
17016 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17017 CallResult.first, DAG.getIntPtrConstant(1));
17018 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17019 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17022 /// LowerOperation - Provide custom lowering hooks for some operations.
17024 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17025 switch (Op.getOpcode()) {
17026 default: llvm_unreachable("Should not custom lower this!");
17027 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17028 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17029 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17030 return LowerCMP_SWAP(Op, Subtarget, DAG);
17031 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17032 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17033 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17034 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17035 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17036 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17037 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17038 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17039 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17040 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17041 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17042 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17043 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17044 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17045 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17046 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17047 case ISD::SHL_PARTS:
17048 case ISD::SRA_PARTS:
17049 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17050 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17051 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17052 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17053 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17054 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17055 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17056 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17057 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17058 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17059 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17061 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17062 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17063 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17064 case ISD::SETCC: return LowerSETCC(Op, DAG);
17065 case ISD::SELECT: return LowerSELECT(Op, DAG);
17066 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17067 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17068 case ISD::VASTART: return LowerVASTART(Op, DAG);
17069 case ISD::VAARG: return LowerVAARG(Op, DAG);
17070 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17071 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17072 case ISD::INTRINSIC_VOID:
17073 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17074 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17075 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17076 case ISD::FRAME_TO_ARGS_OFFSET:
17077 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17078 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17079 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17080 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17081 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17082 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17083 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17084 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17085 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17086 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17087 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17088 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17089 case ISD::UMUL_LOHI:
17090 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17093 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17099 case ISD::UMULO: return LowerXALUO(Op, DAG);
17100 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17101 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17105 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17106 case ISD::ADD: return LowerADD(Op, DAG);
17107 case ISD::SUB: return LowerSUB(Op, DAG);
17108 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17112 static void ReplaceATOMIC_LOAD(SDNode *Node,
17113 SmallVectorImpl<SDValue> &Results,
17114 SelectionDAG &DAG) {
17116 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17118 // Convert wide load -> cmpxchg8b/cmpxchg16b
17119 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17120 // (The only way to get a 16-byte load is cmpxchg16b)
17121 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17122 SDValue Zero = DAG.getConstant(0, VT);
17123 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17125 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17126 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17127 cast<AtomicSDNode>(Node)->getMemOperand(),
17128 cast<AtomicSDNode>(Node)->getOrdering(),
17129 cast<AtomicSDNode>(Node)->getOrdering(),
17130 cast<AtomicSDNode>(Node)->getSynchScope());
17131 Results.push_back(Swap.getValue(0));
17132 Results.push_back(Swap.getValue(2));
17135 /// ReplaceNodeResults - Replace a node with an illegal result type
17136 /// with a new node built out of custom code.
17137 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17138 SmallVectorImpl<SDValue>&Results,
17139 SelectionDAG &DAG) const {
17141 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17142 switch (N->getOpcode()) {
17144 llvm_unreachable("Do not know how to custom type legalize this operation!");
17145 case ISD::SIGN_EXTEND_INREG:
17150 // We don't want to expand or promote these.
17157 case ISD::UDIVREM: {
17158 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17159 Results.push_back(V);
17162 case ISD::FP_TO_SINT:
17163 case ISD::FP_TO_UINT: {
17164 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17166 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17169 std::pair<SDValue,SDValue> Vals =
17170 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17171 SDValue FIST = Vals.first, StackSlot = Vals.second;
17172 if (FIST.getNode()) {
17173 EVT VT = N->getValueType(0);
17174 // Return a load from the stack slot.
17175 if (StackSlot.getNode())
17176 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17177 MachinePointerInfo(),
17178 false, false, false, 0));
17180 Results.push_back(FIST);
17184 case ISD::UINT_TO_FP: {
17185 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17186 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17187 N->getValueType(0) != MVT::v2f32)
17189 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17191 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17193 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17194 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17195 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17196 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17197 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17198 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17201 case ISD::FP_ROUND: {
17202 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17204 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17205 Results.push_back(V);
17208 case ISD::INTRINSIC_W_CHAIN: {
17209 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17211 default : llvm_unreachable("Do not know how to custom type "
17212 "legalize this intrinsic operation!");
17213 case Intrinsic::x86_rdtsc:
17214 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17216 case Intrinsic::x86_rdtscp:
17217 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17219 case Intrinsic::x86_rdpmc:
17220 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17223 case ISD::READCYCLECOUNTER: {
17224 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17227 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17228 EVT T = N->getValueType(0);
17229 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17230 bool Regs64bit = T == MVT::i128;
17231 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17232 SDValue cpInL, cpInH;
17233 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17234 DAG.getConstant(0, HalfT));
17235 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17236 DAG.getConstant(1, HalfT));
17237 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17238 Regs64bit ? X86::RAX : X86::EAX,
17240 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17241 Regs64bit ? X86::RDX : X86::EDX,
17242 cpInH, cpInL.getValue(1));
17243 SDValue swapInL, swapInH;
17244 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17245 DAG.getConstant(0, HalfT));
17246 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17247 DAG.getConstant(1, HalfT));
17248 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17249 Regs64bit ? X86::RBX : X86::EBX,
17250 swapInL, cpInH.getValue(1));
17251 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17252 Regs64bit ? X86::RCX : X86::ECX,
17253 swapInH, swapInL.getValue(1));
17254 SDValue Ops[] = { swapInH.getValue(0),
17256 swapInH.getValue(1) };
17257 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17258 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17259 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17260 X86ISD::LCMPXCHG8_DAG;
17261 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17262 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17263 Regs64bit ? X86::RAX : X86::EAX,
17264 HalfT, Result.getValue(1));
17265 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17266 Regs64bit ? X86::RDX : X86::EDX,
17267 HalfT, cpOutL.getValue(2));
17268 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17270 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17271 MVT::i32, cpOutH.getValue(2));
17273 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17274 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17275 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17277 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17278 Results.push_back(Success);
17279 Results.push_back(EFLAGS.getValue(1));
17282 case ISD::ATOMIC_SWAP:
17283 case ISD::ATOMIC_LOAD_ADD:
17284 case ISD::ATOMIC_LOAD_SUB:
17285 case ISD::ATOMIC_LOAD_AND:
17286 case ISD::ATOMIC_LOAD_OR:
17287 case ISD::ATOMIC_LOAD_XOR:
17288 case ISD::ATOMIC_LOAD_NAND:
17289 case ISD::ATOMIC_LOAD_MIN:
17290 case ISD::ATOMIC_LOAD_MAX:
17291 case ISD::ATOMIC_LOAD_UMIN:
17292 case ISD::ATOMIC_LOAD_UMAX:
17293 // Delegate to generic TypeLegalization. Situations we can really handle
17294 // should have already been dealt with by X86AtomicExpandPass.cpp.
17296 case ISD::ATOMIC_LOAD: {
17297 ReplaceATOMIC_LOAD(N, Results, DAG);
17300 case ISD::BITCAST: {
17301 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17302 EVT DstVT = N->getValueType(0);
17303 EVT SrcVT = N->getOperand(0)->getValueType(0);
17305 if (SrcVT != MVT::f64 ||
17306 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17309 unsigned NumElts = DstVT.getVectorNumElements();
17310 EVT SVT = DstVT.getVectorElementType();
17311 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17312 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17313 MVT::v2f64, N->getOperand(0));
17314 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17316 if (ExperimentalVectorWideningLegalization) {
17317 // If we are legalizing vectors by widening, we already have the desired
17318 // legal vector type, just return it.
17319 Results.push_back(ToVecInt);
17323 SmallVector<SDValue, 8> Elts;
17324 for (unsigned i = 0, e = NumElts; i != e; ++i)
17325 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17326 ToVecInt, DAG.getIntPtrConstant(i)));
17328 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17333 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17335 default: return nullptr;
17336 case X86ISD::BSF: return "X86ISD::BSF";
17337 case X86ISD::BSR: return "X86ISD::BSR";
17338 case X86ISD::SHLD: return "X86ISD::SHLD";
17339 case X86ISD::SHRD: return "X86ISD::SHRD";
17340 case X86ISD::FAND: return "X86ISD::FAND";
17341 case X86ISD::FANDN: return "X86ISD::FANDN";
17342 case X86ISD::FOR: return "X86ISD::FOR";
17343 case X86ISD::FXOR: return "X86ISD::FXOR";
17344 case X86ISD::FSRL: return "X86ISD::FSRL";
17345 case X86ISD::FILD: return "X86ISD::FILD";
17346 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17347 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17348 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17349 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17350 case X86ISD::FLD: return "X86ISD::FLD";
17351 case X86ISD::FST: return "X86ISD::FST";
17352 case X86ISD::CALL: return "X86ISD::CALL";
17353 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17354 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17355 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17356 case X86ISD::BT: return "X86ISD::BT";
17357 case X86ISD::CMP: return "X86ISD::CMP";
17358 case X86ISD::COMI: return "X86ISD::COMI";
17359 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17360 case X86ISD::CMPM: return "X86ISD::CMPM";
17361 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17362 case X86ISD::SETCC: return "X86ISD::SETCC";
17363 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17364 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17365 case X86ISD::CMOV: return "X86ISD::CMOV";
17366 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17367 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17368 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17369 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17370 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17371 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17372 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17373 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17374 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17375 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17376 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17377 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17378 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17379 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17380 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17381 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17382 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17383 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17384 case X86ISD::HADD: return "X86ISD::HADD";
17385 case X86ISD::HSUB: return "X86ISD::HSUB";
17386 case X86ISD::FHADD: return "X86ISD::FHADD";
17387 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17388 case X86ISD::UMAX: return "X86ISD::UMAX";
17389 case X86ISD::UMIN: return "X86ISD::UMIN";
17390 case X86ISD::SMAX: return "X86ISD::SMAX";
17391 case X86ISD::SMIN: return "X86ISD::SMIN";
17392 case X86ISD::FMAX: return "X86ISD::FMAX";
17393 case X86ISD::FMIN: return "X86ISD::FMIN";
17394 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17395 case X86ISD::FMINC: return "X86ISD::FMINC";
17396 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17397 case X86ISD::FRCP: return "X86ISD::FRCP";
17398 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17399 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17400 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17401 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17402 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17403 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17404 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17405 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17406 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17407 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17408 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17409 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17410 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17411 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17412 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17413 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17414 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17415 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17416 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17417 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17418 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17419 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17420 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17421 case X86ISD::VSHL: return "X86ISD::VSHL";
17422 case X86ISD::VSRL: return "X86ISD::VSRL";
17423 case X86ISD::VSRA: return "X86ISD::VSRA";
17424 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17425 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17426 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17427 case X86ISD::CMPP: return "X86ISD::CMPP";
17428 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17429 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17430 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17431 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17432 case X86ISD::ADD: return "X86ISD::ADD";
17433 case X86ISD::SUB: return "X86ISD::SUB";
17434 case X86ISD::ADC: return "X86ISD::ADC";
17435 case X86ISD::SBB: return "X86ISD::SBB";
17436 case X86ISD::SMUL: return "X86ISD::SMUL";
17437 case X86ISD::UMUL: return "X86ISD::UMUL";
17438 case X86ISD::INC: return "X86ISD::INC";
17439 case X86ISD::DEC: return "X86ISD::DEC";
17440 case X86ISD::OR: return "X86ISD::OR";
17441 case X86ISD::XOR: return "X86ISD::XOR";
17442 case X86ISD::AND: return "X86ISD::AND";
17443 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17444 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17445 case X86ISD::PTEST: return "X86ISD::PTEST";
17446 case X86ISD::TESTP: return "X86ISD::TESTP";
17447 case X86ISD::TESTM: return "X86ISD::TESTM";
17448 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17449 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17450 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17451 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17452 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17453 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17454 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17455 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17456 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17457 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17458 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17459 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17460 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17461 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17462 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17463 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17464 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17465 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17466 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17467 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17468 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17469 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17470 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17471 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17472 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17473 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17474 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17475 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17476 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17477 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17478 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17479 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17480 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17481 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17482 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17483 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17484 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17485 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17486 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17487 case X86ISD::SAHF: return "X86ISD::SAHF";
17488 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17489 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17490 case X86ISD::FMADD: return "X86ISD::FMADD";
17491 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17492 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17493 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17494 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17495 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17496 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17497 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17498 case X86ISD::XTEST: return "X86ISD::XTEST";
17502 // isLegalAddressingMode - Return true if the addressing mode represented
17503 // by AM is legal for this target, for a load/store of the specified type.
17504 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17506 // X86 supports extremely general addressing modes.
17507 CodeModel::Model M = getTargetMachine().getCodeModel();
17508 Reloc::Model R = getTargetMachine().getRelocationModel();
17510 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17511 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17516 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17518 // If a reference to this global requires an extra load, we can't fold it.
17519 if (isGlobalStubReference(GVFlags))
17522 // If BaseGV requires a register for the PIC base, we cannot also have a
17523 // BaseReg specified.
17524 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17527 // If lower 4G is not available, then we must use rip-relative addressing.
17528 if ((M != CodeModel::Small || R != Reloc::Static) &&
17529 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17533 switch (AM.Scale) {
17539 // These scales always work.
17544 // These scales are formed with basereg+scalereg. Only accept if there is
17549 default: // Other stuff never works.
17556 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17557 unsigned Bits = Ty->getScalarSizeInBits();
17559 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17560 // particularly cheaper than those without.
17564 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17565 // variable shifts just as cheap as scalar ones.
17566 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17569 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17570 // fully general vector.
17574 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17575 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17577 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17578 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17579 return NumBits1 > NumBits2;
17582 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17583 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17586 if (!isTypeLegal(EVT::getEVT(Ty1)))
17589 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17591 // Assuming the caller doesn't have a zeroext or signext return parameter,
17592 // truncation all the way down to i1 is valid.
17596 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17597 return isInt<32>(Imm);
17600 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17601 // Can also use sub to handle negated immediates.
17602 return isInt<32>(Imm);
17605 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17606 if (!VT1.isInteger() || !VT2.isInteger())
17608 unsigned NumBits1 = VT1.getSizeInBits();
17609 unsigned NumBits2 = VT2.getSizeInBits();
17610 return NumBits1 > NumBits2;
17613 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17614 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17615 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17618 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17619 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17620 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17623 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17624 EVT VT1 = Val.getValueType();
17625 if (isZExtFree(VT1, VT2))
17628 if (Val.getOpcode() != ISD::LOAD)
17631 if (!VT1.isSimple() || !VT1.isInteger() ||
17632 !VT2.isSimple() || !VT2.isInteger())
17635 switch (VT1.getSimpleVT().SimpleTy) {
17640 // X86 has 8, 16, and 32-bit zero-extending loads.
17648 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17649 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17652 VT = VT.getScalarType();
17654 if (!VT.isSimple())
17657 switch (VT.getSimpleVT().SimpleTy) {
17668 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17669 // i16 instructions are longer (0x66 prefix) and potentially slower.
17670 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17673 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17674 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17675 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17676 /// are assumed to be legal.
17678 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17680 if (!VT.isSimple())
17683 MVT SVT = VT.getSimpleVT();
17685 // Very little shuffling can be done for 64-bit vectors right now.
17686 if (VT.getSizeInBits() == 64)
17689 // If this is a single-input shuffle with no 128 bit lane crossings we can
17690 // lower it into pshufb.
17691 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17692 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17693 bool isLegal = true;
17694 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17695 if (M[I] >= (int)SVT.getVectorNumElements() ||
17696 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17705 // FIXME: blends, shifts.
17706 return (SVT.getVectorNumElements() == 2 ||
17707 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17708 isMOVLMask(M, SVT) ||
17709 isMOVHLPSMask(M, SVT) ||
17710 isSHUFPMask(M, SVT) ||
17711 isPSHUFDMask(M, SVT) ||
17712 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17713 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17714 isPALIGNRMask(M, SVT, Subtarget) ||
17715 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17716 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17717 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17718 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17719 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17723 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17725 if (!VT.isSimple())
17728 MVT SVT = VT.getSimpleVT();
17729 unsigned NumElts = SVT.getVectorNumElements();
17730 // FIXME: This collection of masks seems suspect.
17733 if (NumElts == 4 && SVT.is128BitVector()) {
17734 return (isMOVLMask(Mask, SVT) ||
17735 isCommutedMOVLMask(Mask, SVT, true) ||
17736 isSHUFPMask(Mask, SVT) ||
17737 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17742 //===----------------------------------------------------------------------===//
17743 // X86 Scheduler Hooks
17744 //===----------------------------------------------------------------------===//
17746 /// Utility function to emit xbegin specifying the start of an RTM region.
17747 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17748 const TargetInstrInfo *TII) {
17749 DebugLoc DL = MI->getDebugLoc();
17751 const BasicBlock *BB = MBB->getBasicBlock();
17752 MachineFunction::iterator I = MBB;
17755 // For the v = xbegin(), we generate
17766 MachineBasicBlock *thisMBB = MBB;
17767 MachineFunction *MF = MBB->getParent();
17768 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17769 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17770 MF->insert(I, mainMBB);
17771 MF->insert(I, sinkMBB);
17773 // Transfer the remainder of BB and its successor edges to sinkMBB.
17774 sinkMBB->splice(sinkMBB->begin(), MBB,
17775 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17776 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17780 // # fallthrough to mainMBB
17781 // # abortion to sinkMBB
17782 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17783 thisMBB->addSuccessor(mainMBB);
17784 thisMBB->addSuccessor(sinkMBB);
17788 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17789 mainMBB->addSuccessor(sinkMBB);
17792 // EAX is live into the sinkMBB
17793 sinkMBB->addLiveIn(X86::EAX);
17794 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17795 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17798 MI->eraseFromParent();
17802 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17803 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17804 // in the .td file.
17805 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17806 const TargetInstrInfo *TII) {
17808 switch (MI->getOpcode()) {
17809 default: llvm_unreachable("illegal opcode!");
17810 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17811 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17812 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17813 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17814 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17815 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17816 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17817 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17820 DebugLoc dl = MI->getDebugLoc();
17821 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17823 unsigned NumArgs = MI->getNumOperands();
17824 for (unsigned i = 1; i < NumArgs; ++i) {
17825 MachineOperand &Op = MI->getOperand(i);
17826 if (!(Op.isReg() && Op.isImplicit()))
17827 MIB.addOperand(Op);
17829 if (MI->hasOneMemOperand())
17830 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17832 BuildMI(*BB, MI, dl,
17833 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17834 .addReg(X86::XMM0);
17836 MI->eraseFromParent();
17840 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17841 // defs in an instruction pattern
17842 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17843 const TargetInstrInfo *TII) {
17845 switch (MI->getOpcode()) {
17846 default: llvm_unreachable("illegal opcode!");
17847 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17848 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17849 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17850 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17851 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17852 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17853 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17854 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17857 DebugLoc dl = MI->getDebugLoc();
17858 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17860 unsigned NumArgs = MI->getNumOperands(); // remove the results
17861 for (unsigned i = 1; i < NumArgs; ++i) {
17862 MachineOperand &Op = MI->getOperand(i);
17863 if (!(Op.isReg() && Op.isImplicit()))
17864 MIB.addOperand(Op);
17866 if (MI->hasOneMemOperand())
17867 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17869 BuildMI(*BB, MI, dl,
17870 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17873 MI->eraseFromParent();
17877 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17878 const TargetInstrInfo *TII,
17879 const X86Subtarget* Subtarget) {
17880 DebugLoc dl = MI->getDebugLoc();
17882 // Address into RAX/EAX, other two args into ECX, EDX.
17883 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17884 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17885 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17886 for (int i = 0; i < X86::AddrNumOperands; ++i)
17887 MIB.addOperand(MI->getOperand(i));
17889 unsigned ValOps = X86::AddrNumOperands;
17890 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17891 .addReg(MI->getOperand(ValOps).getReg());
17892 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17893 .addReg(MI->getOperand(ValOps+1).getReg());
17895 // The instruction doesn't actually take any operands though.
17896 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17898 MI->eraseFromParent(); // The pseudo is gone now.
17902 MachineBasicBlock *
17903 X86TargetLowering::EmitVAARG64WithCustomInserter(
17905 MachineBasicBlock *MBB) const {
17906 // Emit va_arg instruction on X86-64.
17908 // Operands to this pseudo-instruction:
17909 // 0 ) Output : destination address (reg)
17910 // 1-5) Input : va_list address (addr, i64mem)
17911 // 6 ) ArgSize : Size (in bytes) of vararg type
17912 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17913 // 8 ) Align : Alignment of type
17914 // 9 ) EFLAGS (implicit-def)
17916 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17917 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17919 unsigned DestReg = MI->getOperand(0).getReg();
17920 MachineOperand &Base = MI->getOperand(1);
17921 MachineOperand &Scale = MI->getOperand(2);
17922 MachineOperand &Index = MI->getOperand(3);
17923 MachineOperand &Disp = MI->getOperand(4);
17924 MachineOperand &Segment = MI->getOperand(5);
17925 unsigned ArgSize = MI->getOperand(6).getImm();
17926 unsigned ArgMode = MI->getOperand(7).getImm();
17927 unsigned Align = MI->getOperand(8).getImm();
17929 // Memory Reference
17930 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17931 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17932 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17934 // Machine Information
17935 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17936 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17937 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17938 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17939 DebugLoc DL = MI->getDebugLoc();
17941 // struct va_list {
17944 // i64 overflow_area (address)
17945 // i64 reg_save_area (address)
17947 // sizeof(va_list) = 24
17948 // alignment(va_list) = 8
17950 unsigned TotalNumIntRegs = 6;
17951 unsigned TotalNumXMMRegs = 8;
17952 bool UseGPOffset = (ArgMode == 1);
17953 bool UseFPOffset = (ArgMode == 2);
17954 unsigned MaxOffset = TotalNumIntRegs * 8 +
17955 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17957 /* Align ArgSize to a multiple of 8 */
17958 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17959 bool NeedsAlign = (Align > 8);
17961 MachineBasicBlock *thisMBB = MBB;
17962 MachineBasicBlock *overflowMBB;
17963 MachineBasicBlock *offsetMBB;
17964 MachineBasicBlock *endMBB;
17966 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17967 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17968 unsigned OffsetReg = 0;
17970 if (!UseGPOffset && !UseFPOffset) {
17971 // If we only pull from the overflow region, we don't create a branch.
17972 // We don't need to alter control flow.
17973 OffsetDestReg = 0; // unused
17974 OverflowDestReg = DestReg;
17976 offsetMBB = nullptr;
17977 overflowMBB = thisMBB;
17980 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17981 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17982 // If not, pull from overflow_area. (branch to overflowMBB)
17987 // offsetMBB overflowMBB
17992 // Registers for the PHI in endMBB
17993 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17994 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17996 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17997 MachineFunction *MF = MBB->getParent();
17998 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17999 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18000 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18002 MachineFunction::iterator MBBIter = MBB;
18005 // Insert the new basic blocks
18006 MF->insert(MBBIter, offsetMBB);
18007 MF->insert(MBBIter, overflowMBB);
18008 MF->insert(MBBIter, endMBB);
18010 // Transfer the remainder of MBB and its successor edges to endMBB.
18011 endMBB->splice(endMBB->begin(), thisMBB,
18012 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18013 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18015 // Make offsetMBB and overflowMBB successors of thisMBB
18016 thisMBB->addSuccessor(offsetMBB);
18017 thisMBB->addSuccessor(overflowMBB);
18019 // endMBB is a successor of both offsetMBB and overflowMBB
18020 offsetMBB->addSuccessor(endMBB);
18021 overflowMBB->addSuccessor(endMBB);
18023 // Load the offset value into a register
18024 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18025 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18029 .addDisp(Disp, UseFPOffset ? 4 : 0)
18030 .addOperand(Segment)
18031 .setMemRefs(MMOBegin, MMOEnd);
18033 // Check if there is enough room left to pull this argument.
18034 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18036 .addImm(MaxOffset + 8 - ArgSizeA8);
18038 // Branch to "overflowMBB" if offset >= max
18039 // Fall through to "offsetMBB" otherwise
18040 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18041 .addMBB(overflowMBB);
18044 // In offsetMBB, emit code to use the reg_save_area.
18046 assert(OffsetReg != 0);
18048 // Read the reg_save_area address.
18049 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18050 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18055 .addOperand(Segment)
18056 .setMemRefs(MMOBegin, MMOEnd);
18058 // Zero-extend the offset
18059 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18060 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18063 .addImm(X86::sub_32bit);
18065 // Add the offset to the reg_save_area to get the final address.
18066 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18067 .addReg(OffsetReg64)
18068 .addReg(RegSaveReg);
18070 // Compute the offset for the next argument
18071 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18072 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18074 .addImm(UseFPOffset ? 16 : 8);
18076 // Store it back into the va_list.
18077 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18081 .addDisp(Disp, UseFPOffset ? 4 : 0)
18082 .addOperand(Segment)
18083 .addReg(NextOffsetReg)
18084 .setMemRefs(MMOBegin, MMOEnd);
18087 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18092 // Emit code to use overflow area
18095 // Load the overflow_area address into a register.
18096 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18097 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18102 .addOperand(Segment)
18103 .setMemRefs(MMOBegin, MMOEnd);
18105 // If we need to align it, do so. Otherwise, just copy the address
18106 // to OverflowDestReg.
18108 // Align the overflow address
18109 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18110 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18112 // aligned_addr = (addr + (align-1)) & ~(align-1)
18113 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18114 .addReg(OverflowAddrReg)
18117 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18119 .addImm(~(uint64_t)(Align-1));
18121 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18122 .addReg(OverflowAddrReg);
18125 // Compute the next overflow address after this argument.
18126 // (the overflow address should be kept 8-byte aligned)
18127 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18128 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18129 .addReg(OverflowDestReg)
18130 .addImm(ArgSizeA8);
18132 // Store the new overflow address.
18133 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18138 .addOperand(Segment)
18139 .addReg(NextAddrReg)
18140 .setMemRefs(MMOBegin, MMOEnd);
18142 // If we branched, emit the PHI to the front of endMBB.
18144 BuildMI(*endMBB, endMBB->begin(), DL,
18145 TII->get(X86::PHI), DestReg)
18146 .addReg(OffsetDestReg).addMBB(offsetMBB)
18147 .addReg(OverflowDestReg).addMBB(overflowMBB);
18150 // Erase the pseudo instruction
18151 MI->eraseFromParent();
18156 MachineBasicBlock *
18157 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18159 MachineBasicBlock *MBB) const {
18160 // Emit code to save XMM registers to the stack. The ABI says that the
18161 // number of registers to save is given in %al, so it's theoretically
18162 // possible to do an indirect jump trick to avoid saving all of them,
18163 // however this code takes a simpler approach and just executes all
18164 // of the stores if %al is non-zero. It's less code, and it's probably
18165 // easier on the hardware branch predictor, and stores aren't all that
18166 // expensive anyway.
18168 // Create the new basic blocks. One block contains all the XMM stores,
18169 // and one block is the final destination regardless of whether any
18170 // stores were performed.
18171 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18172 MachineFunction *F = MBB->getParent();
18173 MachineFunction::iterator MBBIter = MBB;
18175 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18176 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18177 F->insert(MBBIter, XMMSaveMBB);
18178 F->insert(MBBIter, EndMBB);
18180 // Transfer the remainder of MBB and its successor edges to EndMBB.
18181 EndMBB->splice(EndMBB->begin(), MBB,
18182 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18183 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18185 // The original block will now fall through to the XMM save block.
18186 MBB->addSuccessor(XMMSaveMBB);
18187 // The XMMSaveMBB will fall through to the end block.
18188 XMMSaveMBB->addSuccessor(EndMBB);
18190 // Now add the instructions.
18191 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18192 DebugLoc DL = MI->getDebugLoc();
18194 unsigned CountReg = MI->getOperand(0).getReg();
18195 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18196 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18198 if (!Subtarget->isTargetWin64()) {
18199 // If %al is 0, branch around the XMM save block.
18200 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18201 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18202 MBB->addSuccessor(EndMBB);
18205 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18206 // that was just emitted, but clearly shouldn't be "saved".
18207 assert((MI->getNumOperands() <= 3 ||
18208 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18209 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18210 && "Expected last argument to be EFLAGS");
18211 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18212 // In the XMM save block, save all the XMM argument registers.
18213 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18214 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18215 MachineMemOperand *MMO =
18216 F->getMachineMemOperand(
18217 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18218 MachineMemOperand::MOStore,
18219 /*Size=*/16, /*Align=*/16);
18220 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18221 .addFrameIndex(RegSaveFrameIndex)
18222 .addImm(/*Scale=*/1)
18223 .addReg(/*IndexReg=*/0)
18224 .addImm(/*Disp=*/Offset)
18225 .addReg(/*Segment=*/0)
18226 .addReg(MI->getOperand(i).getReg())
18227 .addMemOperand(MMO);
18230 MI->eraseFromParent(); // The pseudo instruction is gone now.
18235 // The EFLAGS operand of SelectItr might be missing a kill marker
18236 // because there were multiple uses of EFLAGS, and ISel didn't know
18237 // which to mark. Figure out whether SelectItr should have had a
18238 // kill marker, and set it if it should. Returns the correct kill
18240 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18241 MachineBasicBlock* BB,
18242 const TargetRegisterInfo* TRI) {
18243 // Scan forward through BB for a use/def of EFLAGS.
18244 MachineBasicBlock::iterator miI(std::next(SelectItr));
18245 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18246 const MachineInstr& mi = *miI;
18247 if (mi.readsRegister(X86::EFLAGS))
18249 if (mi.definesRegister(X86::EFLAGS))
18250 break; // Should have kill-flag - update below.
18253 // If we hit the end of the block, check whether EFLAGS is live into a
18255 if (miI == BB->end()) {
18256 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18257 sEnd = BB->succ_end();
18258 sItr != sEnd; ++sItr) {
18259 MachineBasicBlock* succ = *sItr;
18260 if (succ->isLiveIn(X86::EFLAGS))
18265 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18266 // out. SelectMI should have a kill flag on EFLAGS.
18267 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18271 MachineBasicBlock *
18272 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18273 MachineBasicBlock *BB) const {
18274 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18275 DebugLoc DL = MI->getDebugLoc();
18277 // To "insert" a SELECT_CC instruction, we actually have to insert the
18278 // diamond control-flow pattern. The incoming instruction knows the
18279 // destination vreg to set, the condition code register to branch on, the
18280 // true/false values to select between, and a branch opcode to use.
18281 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18282 MachineFunction::iterator It = BB;
18288 // cmpTY ccX, r1, r2
18290 // fallthrough --> copy0MBB
18291 MachineBasicBlock *thisMBB = BB;
18292 MachineFunction *F = BB->getParent();
18293 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18294 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18295 F->insert(It, copy0MBB);
18296 F->insert(It, sinkMBB);
18298 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18299 // live into the sink and copy blocks.
18300 const TargetRegisterInfo *TRI =
18301 BB->getParent()->getSubtarget().getRegisterInfo();
18302 if (!MI->killsRegister(X86::EFLAGS) &&
18303 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18304 copy0MBB->addLiveIn(X86::EFLAGS);
18305 sinkMBB->addLiveIn(X86::EFLAGS);
18308 // Transfer the remainder of BB and its successor edges to sinkMBB.
18309 sinkMBB->splice(sinkMBB->begin(), BB,
18310 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18311 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18313 // Add the true and fallthrough blocks as its successors.
18314 BB->addSuccessor(copy0MBB);
18315 BB->addSuccessor(sinkMBB);
18317 // Create the conditional branch instruction.
18319 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18320 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18323 // %FalseValue = ...
18324 // # fallthrough to sinkMBB
18325 copy0MBB->addSuccessor(sinkMBB);
18328 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18330 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18331 TII->get(X86::PHI), MI->getOperand(0).getReg())
18332 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18333 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18335 MI->eraseFromParent(); // The pseudo instruction is gone now.
18339 MachineBasicBlock *
18340 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18341 bool Is64Bit) const {
18342 MachineFunction *MF = BB->getParent();
18343 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18344 DebugLoc DL = MI->getDebugLoc();
18345 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18347 assert(MF->shouldSplitStack());
18349 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18350 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18353 // ... [Till the alloca]
18354 // If stacklet is not large enough, jump to mallocMBB
18357 // Allocate by subtracting from RSP
18358 // Jump to continueMBB
18361 // Allocate by call to runtime
18365 // [rest of original BB]
18368 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18369 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18370 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18372 MachineRegisterInfo &MRI = MF->getRegInfo();
18373 const TargetRegisterClass *AddrRegClass =
18374 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18376 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18377 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18378 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18379 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18380 sizeVReg = MI->getOperand(1).getReg(),
18381 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18383 MachineFunction::iterator MBBIter = BB;
18386 MF->insert(MBBIter, bumpMBB);
18387 MF->insert(MBBIter, mallocMBB);
18388 MF->insert(MBBIter, continueMBB);
18390 continueMBB->splice(continueMBB->begin(), BB,
18391 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18392 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18394 // Add code to the main basic block to check if the stack limit has been hit,
18395 // and if so, jump to mallocMBB otherwise to bumpMBB.
18396 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18397 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18398 .addReg(tmpSPVReg).addReg(sizeVReg);
18399 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18400 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18401 .addReg(SPLimitVReg);
18402 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18404 // bumpMBB simply decreases the stack pointer, since we know the current
18405 // stacklet has enough space.
18406 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18407 .addReg(SPLimitVReg);
18408 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18409 .addReg(SPLimitVReg);
18410 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18412 // Calls into a routine in libgcc to allocate more space from the heap.
18413 const uint32_t *RegMask = MF->getTarget()
18414 .getSubtargetImpl()
18415 ->getRegisterInfo()
18416 ->getCallPreservedMask(CallingConv::C);
18418 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18420 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18421 .addExternalSymbol("__morestack_allocate_stack_space")
18422 .addRegMask(RegMask)
18423 .addReg(X86::RDI, RegState::Implicit)
18424 .addReg(X86::RAX, RegState::ImplicitDefine);
18426 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18428 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18429 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18430 .addExternalSymbol("__morestack_allocate_stack_space")
18431 .addRegMask(RegMask)
18432 .addReg(X86::EAX, RegState::ImplicitDefine);
18436 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18439 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18440 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18441 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18443 // Set up the CFG correctly.
18444 BB->addSuccessor(bumpMBB);
18445 BB->addSuccessor(mallocMBB);
18446 mallocMBB->addSuccessor(continueMBB);
18447 bumpMBB->addSuccessor(continueMBB);
18449 // Take care of the PHI nodes.
18450 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18451 MI->getOperand(0).getReg())
18452 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18453 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18455 // Delete the original pseudo instruction.
18456 MI->eraseFromParent();
18459 return continueMBB;
18462 MachineBasicBlock *
18463 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18464 MachineBasicBlock *BB) const {
18465 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18466 DebugLoc DL = MI->getDebugLoc();
18468 assert(!Subtarget->isTargetMacho());
18470 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18471 // non-trivial part is impdef of ESP.
18473 if (Subtarget->isTargetWin64()) {
18474 if (Subtarget->isTargetCygMing()) {
18475 // ___chkstk(Mingw64):
18476 // Clobbers R10, R11, RAX and EFLAGS.
18478 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18479 .addExternalSymbol("___chkstk")
18480 .addReg(X86::RAX, RegState::Implicit)
18481 .addReg(X86::RSP, RegState::Implicit)
18482 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18483 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18484 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18486 // __chkstk(MSVCRT): does not update stack pointer.
18487 // Clobbers R10, R11 and EFLAGS.
18488 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18489 .addExternalSymbol("__chkstk")
18490 .addReg(X86::RAX, RegState::Implicit)
18491 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18492 // RAX has the offset to be subtracted from RSP.
18493 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18498 const char *StackProbeSymbol =
18499 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18501 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18502 .addExternalSymbol(StackProbeSymbol)
18503 .addReg(X86::EAX, RegState::Implicit)
18504 .addReg(X86::ESP, RegState::Implicit)
18505 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18506 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18507 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18510 MI->eraseFromParent(); // The pseudo instruction is gone now.
18514 MachineBasicBlock *
18515 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18516 MachineBasicBlock *BB) const {
18517 // This is pretty easy. We're taking the value that we received from
18518 // our load from the relocation, sticking it in either RDI (x86-64)
18519 // or EAX and doing an indirect call. The return value will then
18520 // be in the normal return register.
18521 MachineFunction *F = BB->getParent();
18522 const X86InstrInfo *TII =
18523 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18524 DebugLoc DL = MI->getDebugLoc();
18526 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18527 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18529 // Get a register mask for the lowered call.
18530 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18531 // proper register mask.
18532 const uint32_t *RegMask = F->getTarget()
18533 .getSubtargetImpl()
18534 ->getRegisterInfo()
18535 ->getCallPreservedMask(CallingConv::C);
18536 if (Subtarget->is64Bit()) {
18537 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18538 TII->get(X86::MOV64rm), X86::RDI)
18540 .addImm(0).addReg(0)
18541 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18542 MI->getOperand(3).getTargetFlags())
18544 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18545 addDirectMem(MIB, X86::RDI);
18546 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18547 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18548 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18549 TII->get(X86::MOV32rm), X86::EAX)
18551 .addImm(0).addReg(0)
18552 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18553 MI->getOperand(3).getTargetFlags())
18555 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18556 addDirectMem(MIB, X86::EAX);
18557 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18559 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18560 TII->get(X86::MOV32rm), X86::EAX)
18561 .addReg(TII->getGlobalBaseReg(F))
18562 .addImm(0).addReg(0)
18563 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18564 MI->getOperand(3).getTargetFlags())
18566 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18567 addDirectMem(MIB, X86::EAX);
18568 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18571 MI->eraseFromParent(); // The pseudo instruction is gone now.
18575 MachineBasicBlock *
18576 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18577 MachineBasicBlock *MBB) const {
18578 DebugLoc DL = MI->getDebugLoc();
18579 MachineFunction *MF = MBB->getParent();
18580 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18581 MachineRegisterInfo &MRI = MF->getRegInfo();
18583 const BasicBlock *BB = MBB->getBasicBlock();
18584 MachineFunction::iterator I = MBB;
18587 // Memory Reference
18588 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18589 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18592 unsigned MemOpndSlot = 0;
18594 unsigned CurOp = 0;
18596 DstReg = MI->getOperand(CurOp++).getReg();
18597 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18598 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18599 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18600 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18602 MemOpndSlot = CurOp;
18604 MVT PVT = getPointerTy();
18605 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18606 "Invalid Pointer Size!");
18608 // For v = setjmp(buf), we generate
18611 // buf[LabelOffset] = restoreMBB
18612 // SjLjSetup restoreMBB
18618 // v = phi(main, restore)
18623 MachineBasicBlock *thisMBB = MBB;
18624 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18625 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18626 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18627 MF->insert(I, mainMBB);
18628 MF->insert(I, sinkMBB);
18629 MF->push_back(restoreMBB);
18631 MachineInstrBuilder MIB;
18633 // Transfer the remainder of BB and its successor edges to sinkMBB.
18634 sinkMBB->splice(sinkMBB->begin(), MBB,
18635 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18636 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18639 unsigned PtrStoreOpc = 0;
18640 unsigned LabelReg = 0;
18641 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18642 Reloc::Model RM = MF->getTarget().getRelocationModel();
18643 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18644 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18646 // Prepare IP either in reg or imm.
18647 if (!UseImmLabel) {
18648 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18649 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18650 LabelReg = MRI.createVirtualRegister(PtrRC);
18651 if (Subtarget->is64Bit()) {
18652 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18656 .addMBB(restoreMBB)
18659 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18660 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18661 .addReg(XII->getGlobalBaseReg(MF))
18664 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18668 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18670 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18671 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18672 if (i == X86::AddrDisp)
18673 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18675 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18678 MIB.addReg(LabelReg);
18680 MIB.addMBB(restoreMBB);
18681 MIB.setMemRefs(MMOBegin, MMOEnd);
18683 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18684 .addMBB(restoreMBB);
18686 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18687 MF->getSubtarget().getRegisterInfo());
18688 MIB.addRegMask(RegInfo->getNoPreservedMask());
18689 thisMBB->addSuccessor(mainMBB);
18690 thisMBB->addSuccessor(restoreMBB);
18694 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18695 mainMBB->addSuccessor(sinkMBB);
18698 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18699 TII->get(X86::PHI), DstReg)
18700 .addReg(mainDstReg).addMBB(mainMBB)
18701 .addReg(restoreDstReg).addMBB(restoreMBB);
18704 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18705 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18706 restoreMBB->addSuccessor(sinkMBB);
18708 MI->eraseFromParent();
18712 MachineBasicBlock *
18713 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18714 MachineBasicBlock *MBB) const {
18715 DebugLoc DL = MI->getDebugLoc();
18716 MachineFunction *MF = MBB->getParent();
18717 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18718 MachineRegisterInfo &MRI = MF->getRegInfo();
18720 // Memory Reference
18721 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18722 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18724 MVT PVT = getPointerTy();
18725 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18726 "Invalid Pointer Size!");
18728 const TargetRegisterClass *RC =
18729 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18730 unsigned Tmp = MRI.createVirtualRegister(RC);
18731 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18732 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18733 MF->getSubtarget().getRegisterInfo());
18734 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18735 unsigned SP = RegInfo->getStackRegister();
18737 MachineInstrBuilder MIB;
18739 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18740 const int64_t SPOffset = 2 * PVT.getStoreSize();
18742 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18743 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18746 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18747 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18748 MIB.addOperand(MI->getOperand(i));
18749 MIB.setMemRefs(MMOBegin, MMOEnd);
18751 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18752 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18753 if (i == X86::AddrDisp)
18754 MIB.addDisp(MI->getOperand(i), LabelOffset);
18756 MIB.addOperand(MI->getOperand(i));
18758 MIB.setMemRefs(MMOBegin, MMOEnd);
18760 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18761 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18762 if (i == X86::AddrDisp)
18763 MIB.addDisp(MI->getOperand(i), SPOffset);
18765 MIB.addOperand(MI->getOperand(i));
18767 MIB.setMemRefs(MMOBegin, MMOEnd);
18769 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18771 MI->eraseFromParent();
18775 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18776 // accumulator loops. Writing back to the accumulator allows the coalescer
18777 // to remove extra copies in the loop.
18778 MachineBasicBlock *
18779 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18780 MachineBasicBlock *MBB) const {
18781 MachineOperand &AddendOp = MI->getOperand(3);
18783 // Bail out early if the addend isn't a register - we can't switch these.
18784 if (!AddendOp.isReg())
18787 MachineFunction &MF = *MBB->getParent();
18788 MachineRegisterInfo &MRI = MF.getRegInfo();
18790 // Check whether the addend is defined by a PHI:
18791 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18792 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18793 if (!AddendDef.isPHI())
18796 // Look for the following pattern:
18798 // %addend = phi [%entry, 0], [%loop, %result]
18800 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18804 // %addend = phi [%entry, 0], [%loop, %result]
18806 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18808 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18809 assert(AddendDef.getOperand(i).isReg());
18810 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18811 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18812 if (&PHISrcInst == MI) {
18813 // Found a matching instruction.
18814 unsigned NewFMAOpc = 0;
18815 switch (MI->getOpcode()) {
18816 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18817 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18818 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18819 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18820 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18821 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18822 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18823 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18824 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18825 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18826 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18827 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18828 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18829 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18830 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18831 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18832 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18833 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18834 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18835 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18836 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18837 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18838 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18839 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18840 default: llvm_unreachable("Unrecognized FMA variant.");
18843 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18844 MachineInstrBuilder MIB =
18845 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18846 .addOperand(MI->getOperand(0))
18847 .addOperand(MI->getOperand(3))
18848 .addOperand(MI->getOperand(2))
18849 .addOperand(MI->getOperand(1));
18850 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18851 MI->eraseFromParent();
18858 MachineBasicBlock *
18859 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18860 MachineBasicBlock *BB) const {
18861 switch (MI->getOpcode()) {
18862 default: llvm_unreachable("Unexpected instr type to insert");
18863 case X86::TAILJMPd64:
18864 case X86::TAILJMPr64:
18865 case X86::TAILJMPm64:
18866 llvm_unreachable("TAILJMP64 would not be touched here.");
18867 case X86::TCRETURNdi64:
18868 case X86::TCRETURNri64:
18869 case X86::TCRETURNmi64:
18871 case X86::WIN_ALLOCA:
18872 return EmitLoweredWinAlloca(MI, BB);
18873 case X86::SEG_ALLOCA_32:
18874 return EmitLoweredSegAlloca(MI, BB, false);
18875 case X86::SEG_ALLOCA_64:
18876 return EmitLoweredSegAlloca(MI, BB, true);
18877 case X86::TLSCall_32:
18878 case X86::TLSCall_64:
18879 return EmitLoweredTLSCall(MI, BB);
18880 case X86::CMOV_GR8:
18881 case X86::CMOV_FR32:
18882 case X86::CMOV_FR64:
18883 case X86::CMOV_V4F32:
18884 case X86::CMOV_V2F64:
18885 case X86::CMOV_V2I64:
18886 case X86::CMOV_V8F32:
18887 case X86::CMOV_V4F64:
18888 case X86::CMOV_V4I64:
18889 case X86::CMOV_V16F32:
18890 case X86::CMOV_V8F64:
18891 case X86::CMOV_V8I64:
18892 case X86::CMOV_GR16:
18893 case X86::CMOV_GR32:
18894 case X86::CMOV_RFP32:
18895 case X86::CMOV_RFP64:
18896 case X86::CMOV_RFP80:
18897 return EmitLoweredSelect(MI, BB);
18899 case X86::FP32_TO_INT16_IN_MEM:
18900 case X86::FP32_TO_INT32_IN_MEM:
18901 case X86::FP32_TO_INT64_IN_MEM:
18902 case X86::FP64_TO_INT16_IN_MEM:
18903 case X86::FP64_TO_INT32_IN_MEM:
18904 case X86::FP64_TO_INT64_IN_MEM:
18905 case X86::FP80_TO_INT16_IN_MEM:
18906 case X86::FP80_TO_INT32_IN_MEM:
18907 case X86::FP80_TO_INT64_IN_MEM: {
18908 MachineFunction *F = BB->getParent();
18909 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
18910 DebugLoc DL = MI->getDebugLoc();
18912 // Change the floating point control register to use "round towards zero"
18913 // mode when truncating to an integer value.
18914 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18915 addFrameReference(BuildMI(*BB, MI, DL,
18916 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18918 // Load the old value of the high byte of the control word...
18920 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18921 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18924 // Set the high part to be round to zero...
18925 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18928 // Reload the modified control word now...
18929 addFrameReference(BuildMI(*BB, MI, DL,
18930 TII->get(X86::FLDCW16m)), CWFrameIdx);
18932 // Restore the memory image of control word to original value
18933 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18936 // Get the X86 opcode to use.
18938 switch (MI->getOpcode()) {
18939 default: llvm_unreachable("illegal opcode!");
18940 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18941 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18942 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18943 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18944 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18945 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18946 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18947 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18948 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18952 MachineOperand &Op = MI->getOperand(0);
18954 AM.BaseType = X86AddressMode::RegBase;
18955 AM.Base.Reg = Op.getReg();
18957 AM.BaseType = X86AddressMode::FrameIndexBase;
18958 AM.Base.FrameIndex = Op.getIndex();
18960 Op = MI->getOperand(1);
18962 AM.Scale = Op.getImm();
18963 Op = MI->getOperand(2);
18965 AM.IndexReg = Op.getImm();
18966 Op = MI->getOperand(3);
18967 if (Op.isGlobal()) {
18968 AM.GV = Op.getGlobal();
18970 AM.Disp = Op.getImm();
18972 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18973 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18975 // Reload the original control word now.
18976 addFrameReference(BuildMI(*BB, MI, DL,
18977 TII->get(X86::FLDCW16m)), CWFrameIdx);
18979 MI->eraseFromParent(); // The pseudo instruction is gone now.
18982 // String/text processing lowering.
18983 case X86::PCMPISTRM128REG:
18984 case X86::VPCMPISTRM128REG:
18985 case X86::PCMPISTRM128MEM:
18986 case X86::VPCMPISTRM128MEM:
18987 case X86::PCMPESTRM128REG:
18988 case X86::VPCMPESTRM128REG:
18989 case X86::PCMPESTRM128MEM:
18990 case X86::VPCMPESTRM128MEM:
18991 assert(Subtarget->hasSSE42() &&
18992 "Target must have SSE4.2 or AVX features enabled");
18993 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18995 // String/text processing lowering.
18996 case X86::PCMPISTRIREG:
18997 case X86::VPCMPISTRIREG:
18998 case X86::PCMPISTRIMEM:
18999 case X86::VPCMPISTRIMEM:
19000 case X86::PCMPESTRIREG:
19001 case X86::VPCMPESTRIREG:
19002 case X86::PCMPESTRIMEM:
19003 case X86::VPCMPESTRIMEM:
19004 assert(Subtarget->hasSSE42() &&
19005 "Target must have SSE4.2 or AVX features enabled");
19006 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19008 // Thread synchronization.
19010 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19015 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19017 case X86::VASTART_SAVE_XMM_REGS:
19018 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19020 case X86::VAARG_64:
19021 return EmitVAARG64WithCustomInserter(MI, BB);
19023 case X86::EH_SjLj_SetJmp32:
19024 case X86::EH_SjLj_SetJmp64:
19025 return emitEHSjLjSetJmp(MI, BB);
19027 case X86::EH_SjLj_LongJmp32:
19028 case X86::EH_SjLj_LongJmp64:
19029 return emitEHSjLjLongJmp(MI, BB);
19031 case TargetOpcode::STACKMAP:
19032 case TargetOpcode::PATCHPOINT:
19033 return emitPatchPoint(MI, BB);
19035 case X86::VFMADDPDr213r:
19036 case X86::VFMADDPSr213r:
19037 case X86::VFMADDSDr213r:
19038 case X86::VFMADDSSr213r:
19039 case X86::VFMSUBPDr213r:
19040 case X86::VFMSUBPSr213r:
19041 case X86::VFMSUBSDr213r:
19042 case X86::VFMSUBSSr213r:
19043 case X86::VFNMADDPDr213r:
19044 case X86::VFNMADDPSr213r:
19045 case X86::VFNMADDSDr213r:
19046 case X86::VFNMADDSSr213r:
19047 case X86::VFNMSUBPDr213r:
19048 case X86::VFNMSUBPSr213r:
19049 case X86::VFNMSUBSDr213r:
19050 case X86::VFNMSUBSSr213r:
19051 case X86::VFMADDPDr213rY:
19052 case X86::VFMADDPSr213rY:
19053 case X86::VFMSUBPDr213rY:
19054 case X86::VFMSUBPSr213rY:
19055 case X86::VFNMADDPDr213rY:
19056 case X86::VFNMADDPSr213rY:
19057 case X86::VFNMSUBPDr213rY:
19058 case X86::VFNMSUBPSr213rY:
19059 return emitFMA3Instr(MI, BB);
19063 //===----------------------------------------------------------------------===//
19064 // X86 Optimization Hooks
19065 //===----------------------------------------------------------------------===//
19067 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19070 const SelectionDAG &DAG,
19071 unsigned Depth) const {
19072 unsigned BitWidth = KnownZero.getBitWidth();
19073 unsigned Opc = Op.getOpcode();
19074 assert((Opc >= ISD::BUILTIN_OP_END ||
19075 Opc == ISD::INTRINSIC_WO_CHAIN ||
19076 Opc == ISD::INTRINSIC_W_CHAIN ||
19077 Opc == ISD::INTRINSIC_VOID) &&
19078 "Should use MaskedValueIsZero if you don't know whether Op"
19079 " is a target node!");
19081 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19095 // These nodes' second result is a boolean.
19096 if (Op.getResNo() == 0)
19099 case X86ISD::SETCC:
19100 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19102 case ISD::INTRINSIC_WO_CHAIN: {
19103 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19104 unsigned NumLoBits = 0;
19107 case Intrinsic::x86_sse_movmsk_ps:
19108 case Intrinsic::x86_avx_movmsk_ps_256:
19109 case Intrinsic::x86_sse2_movmsk_pd:
19110 case Intrinsic::x86_avx_movmsk_pd_256:
19111 case Intrinsic::x86_mmx_pmovmskb:
19112 case Intrinsic::x86_sse2_pmovmskb_128:
19113 case Intrinsic::x86_avx2_pmovmskb: {
19114 // High bits of movmskp{s|d}, pmovmskb are known zero.
19116 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19117 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19118 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19119 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19120 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19121 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19122 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19123 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19125 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19134 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19136 const SelectionDAG &,
19137 unsigned Depth) const {
19138 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19139 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19140 return Op.getValueType().getScalarType().getSizeInBits();
19146 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19147 /// node is a GlobalAddress + offset.
19148 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19149 const GlobalValue* &GA,
19150 int64_t &Offset) const {
19151 if (N->getOpcode() == X86ISD::Wrapper) {
19152 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19153 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19154 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19158 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19161 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19162 /// same as extracting the high 128-bit part of 256-bit vector and then
19163 /// inserting the result into the low part of a new 256-bit vector
19164 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19165 EVT VT = SVOp->getValueType(0);
19166 unsigned NumElems = VT.getVectorNumElements();
19168 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19169 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19170 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19171 SVOp->getMaskElt(j) >= 0)
19177 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19178 /// same as extracting the low 128-bit part of 256-bit vector and then
19179 /// inserting the result into the high part of a new 256-bit vector
19180 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19181 EVT VT = SVOp->getValueType(0);
19182 unsigned NumElems = VT.getVectorNumElements();
19184 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19185 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19186 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19187 SVOp->getMaskElt(j) >= 0)
19193 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19194 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19195 TargetLowering::DAGCombinerInfo &DCI,
19196 const X86Subtarget* Subtarget) {
19198 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19199 SDValue V1 = SVOp->getOperand(0);
19200 SDValue V2 = SVOp->getOperand(1);
19201 EVT VT = SVOp->getValueType(0);
19202 unsigned NumElems = VT.getVectorNumElements();
19204 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19205 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19209 // V UNDEF BUILD_VECTOR UNDEF
19211 // CONCAT_VECTOR CONCAT_VECTOR
19214 // RESULT: V + zero extended
19216 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19217 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19218 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19221 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19224 // To match the shuffle mask, the first half of the mask should
19225 // be exactly the first vector, and all the rest a splat with the
19226 // first element of the second one.
19227 for (unsigned i = 0; i != NumElems/2; ++i)
19228 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19229 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19232 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19233 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19234 if (Ld->hasNUsesOfValue(1, 0)) {
19235 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19236 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19238 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19240 Ld->getPointerInfo(),
19241 Ld->getAlignment(),
19242 false/*isVolatile*/, true/*ReadMem*/,
19243 false/*WriteMem*/);
19245 // Make sure the newly-created LOAD is in the same position as Ld in
19246 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19247 // and update uses of Ld's output chain to use the TokenFactor.
19248 if (Ld->hasAnyUseOfValue(1)) {
19249 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19250 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19251 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19252 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19253 SDValue(ResNode.getNode(), 1));
19256 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19260 // Emit a zeroed vector and insert the desired subvector on its
19262 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19263 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19264 return DCI.CombineTo(N, InsV);
19267 //===--------------------------------------------------------------------===//
19268 // Combine some shuffles into subvector extracts and inserts:
19271 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19272 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19273 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19274 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19275 return DCI.CombineTo(N, InsV);
19278 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19279 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19280 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19281 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19282 return DCI.CombineTo(N, InsV);
19288 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19291 /// This is the leaf of the recursive combinine below. When we have found some
19292 /// chain of single-use x86 shuffle instructions and accumulated the combined
19293 /// shuffle mask represented by them, this will try to pattern match that mask
19294 /// into either a single instruction if there is a special purpose instruction
19295 /// for this operation, or into a PSHUFB instruction which is a fully general
19296 /// instruction but should only be used to replace chains over a certain depth.
19297 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19298 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19299 TargetLowering::DAGCombinerInfo &DCI,
19300 const X86Subtarget *Subtarget) {
19301 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19303 // Find the operand that enters the chain. Note that multiple uses are OK
19304 // here, we're not going to remove the operand we find.
19305 SDValue Input = Op.getOperand(0);
19306 while (Input.getOpcode() == ISD::BITCAST)
19307 Input = Input.getOperand(0);
19309 MVT VT = Input.getSimpleValueType();
19310 MVT RootVT = Root.getSimpleValueType();
19313 // Just remove no-op shuffle masks.
19314 if (Mask.size() == 1) {
19315 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19320 // Use the float domain if the operand type is a floating point type.
19321 bool FloatDomain = VT.isFloatingPoint();
19323 // If we don't have access to VEX encodings, the generic PSHUF instructions
19324 // are preferable to some of the specialized forms despite requiring one more
19325 // byte to encode because they can implicitly copy.
19327 // IF we *do* have VEX encodings, than we can use shorter, more specific
19328 // shuffle instructions freely as they can copy due to the extra register
19330 if (Subtarget->hasAVX()) {
19331 // We have both floating point and integer variants of shuffles that dup
19332 // either the low or high half of the vector.
19333 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19334 bool Lo = Mask.equals(0, 0);
19335 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19336 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19337 if (Depth == 1 && Root->getOpcode() == Shuffle)
19338 return false; // Nothing to do!
19339 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19340 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19341 DCI.AddToWorklist(Op.getNode());
19342 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19343 DCI.AddToWorklist(Op.getNode());
19344 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19349 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19351 // For the integer domain we have specialized instructions for duplicating
19352 // any element size from the low or high half.
19353 if (!FloatDomain &&
19354 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19355 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19356 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19357 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19358 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19360 bool Lo = Mask[0] == 0;
19361 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19362 if (Depth == 1 && Root->getOpcode() == Shuffle)
19363 return false; // Nothing to do!
19365 switch (Mask.size()) {
19366 case 4: ShuffleVT = MVT::v4i32; break;
19367 case 8: ShuffleVT = MVT::v8i16; break;
19368 case 16: ShuffleVT = MVT::v16i8; break;
19370 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19371 DCI.AddToWorklist(Op.getNode());
19372 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19373 DCI.AddToWorklist(Op.getNode());
19374 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19380 // Don't try to re-form single instruction chains under any circumstances now
19381 // that we've done encoding canonicalization for them.
19385 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19386 // can replace them with a single PSHUFB instruction profitably. Intel's
19387 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19388 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19389 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19390 SmallVector<SDValue, 16> PSHUFBMask;
19391 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19392 int Ratio = 16 / Mask.size();
19393 for (unsigned i = 0; i < 16; ++i) {
19394 int M = Mask[i / Ratio] != SM_SentinelZero
19395 ? Ratio * Mask[i / Ratio] + i % Ratio
19397 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19399 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19400 DCI.AddToWorklist(Op.getNode());
19401 SDValue PSHUFBMaskOp =
19402 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19403 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19404 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19405 DCI.AddToWorklist(Op.getNode());
19406 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19411 // Failed to find any combines.
19415 /// \brief Fully generic combining of x86 shuffle instructions.
19417 /// This should be the last combine run over the x86 shuffle instructions. Once
19418 /// they have been fully optimized, this will recursively consider all chains
19419 /// of single-use shuffle instructions, build a generic model of the cumulative
19420 /// shuffle operation, and check for simpler instructions which implement this
19421 /// operation. We use this primarily for two purposes:
19423 /// 1) Collapse generic shuffles to specialized single instructions when
19424 /// equivalent. In most cases, this is just an encoding size win, but
19425 /// sometimes we will collapse multiple generic shuffles into a single
19426 /// special-purpose shuffle.
19427 /// 2) Look for sequences of shuffle instructions with 3 or more total
19428 /// instructions, and replace them with the slightly more expensive SSSE3
19429 /// PSHUFB instruction if available. We do this as the last combining step
19430 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19431 /// a suitable short sequence of other instructions. The PHUFB will either
19432 /// use a register or have to read from memory and so is slightly (but only
19433 /// slightly) more expensive than the other shuffle instructions.
19435 /// Because this is inherently a quadratic operation (for each shuffle in
19436 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19437 /// This should never be an issue in practice as the shuffle lowering doesn't
19438 /// produce sequences of more than 8 instructions.
19440 /// FIXME: We will currently miss some cases where the redundant shuffling
19441 /// would simplify under the threshold for PSHUFB formation because of
19442 /// combine-ordering. To fix this, we should do the redundant instruction
19443 /// combining in this recursive walk.
19444 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19445 ArrayRef<int> RootMask,
19446 int Depth, bool HasPSHUFB,
19448 TargetLowering::DAGCombinerInfo &DCI,
19449 const X86Subtarget *Subtarget) {
19450 // Bound the depth of our recursive combine because this is ultimately
19451 // quadratic in nature.
19455 // Directly rip through bitcasts to find the underlying operand.
19456 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19457 Op = Op.getOperand(0);
19459 MVT VT = Op.getSimpleValueType();
19460 if (!VT.isVector())
19461 return false; // Bail if we hit a non-vector.
19462 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19463 // version should be added.
19464 if (VT.getSizeInBits() != 128)
19467 assert(Root.getSimpleValueType().isVector() &&
19468 "Shuffles operate on vector types!");
19469 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19470 "Can only combine shuffles of the same vector register size.");
19472 if (!isTargetShuffle(Op.getOpcode()))
19474 SmallVector<int, 16> OpMask;
19476 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19477 // We only can combine unary shuffles which we can decode the mask for.
19478 if (!HaveMask || !IsUnary)
19481 assert(VT.getVectorNumElements() == OpMask.size() &&
19482 "Different mask size from vector size!");
19483 assert(((RootMask.size() > OpMask.size() &&
19484 RootMask.size() % OpMask.size() == 0) ||
19485 (OpMask.size() > RootMask.size() &&
19486 OpMask.size() % RootMask.size() == 0) ||
19487 OpMask.size() == RootMask.size()) &&
19488 "The smaller number of elements must divide the larger.");
19489 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19490 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19491 assert(((RootRatio == 1 && OpRatio == 1) ||
19492 (RootRatio == 1) != (OpRatio == 1)) &&
19493 "Must not have a ratio for both incoming and op masks!");
19495 SmallVector<int, 16> Mask;
19496 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19498 // Merge this shuffle operation's mask into our accumulated mask. Note that
19499 // this shuffle's mask will be the first applied to the input, followed by the
19500 // root mask to get us all the way to the root value arrangement. The reason
19501 // for this order is that we are recursing up the operation chain.
19502 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19503 int RootIdx = i / RootRatio;
19504 if (RootMask[RootIdx] == SM_SentinelZero) {
19505 // This is a zero-ed lane, we're done.
19506 Mask.push_back(SM_SentinelZero);
19510 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19511 int OpIdx = RootMaskedIdx / OpRatio;
19512 if (OpMask[OpIdx] == SM_SentinelZero) {
19513 // The incoming lanes are zero, it doesn't matter which ones we are using.
19514 Mask.push_back(SM_SentinelZero);
19518 // Ok, we have non-zero lanes, map them through.
19519 Mask.push_back(OpMask[OpIdx] * OpRatio +
19520 RootMaskedIdx % OpRatio);
19523 // See if we can recurse into the operand to combine more things.
19524 switch (Op.getOpcode()) {
19525 case X86ISD::PSHUFB:
19527 case X86ISD::PSHUFD:
19528 case X86ISD::PSHUFHW:
19529 case X86ISD::PSHUFLW:
19530 if (Op.getOperand(0).hasOneUse() &&
19531 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19532 HasPSHUFB, DAG, DCI, Subtarget))
19536 case X86ISD::UNPCKL:
19537 case X86ISD::UNPCKH:
19538 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19539 // We can't check for single use, we have to check that this shuffle is the only user.
19540 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19541 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19542 HasPSHUFB, DAG, DCI, Subtarget))
19547 // Minor canonicalization of the accumulated shuffle mask to make it easier
19548 // to match below. All this does is detect masks with squential pairs of
19549 // elements, and shrink them to the half-width mask. It does this in a loop
19550 // so it will reduce the size of the mask to the minimal width mask which
19551 // performs an equivalent shuffle.
19552 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
19553 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
19554 Mask[i] = Mask[2 * i] / 2;
19555 Mask.resize(Mask.size() / 2);
19558 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19562 /// \brief Get the PSHUF-style mask from PSHUF node.
19564 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19565 /// PSHUF-style masks that can be reused with such instructions.
19566 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19567 SmallVector<int, 4> Mask;
19569 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19573 switch (N.getOpcode()) {
19574 case X86ISD::PSHUFD:
19576 case X86ISD::PSHUFLW:
19579 case X86ISD::PSHUFHW:
19580 Mask.erase(Mask.begin(), Mask.begin() + 4);
19581 for (int &M : Mask)
19585 llvm_unreachable("No valid shuffle instruction found!");
19589 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19591 /// We walk up the chain and look for a combinable shuffle, skipping over
19592 /// shuffles that we could hoist this shuffle's transformation past without
19593 /// altering anything.
19595 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19597 TargetLowering::DAGCombinerInfo &DCI) {
19598 assert(N.getOpcode() == X86ISD::PSHUFD &&
19599 "Called with something other than an x86 128-bit half shuffle!");
19602 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
19603 // of the shuffles in the chain so that we can form a fresh chain to replace
19605 SmallVector<SDValue, 8> Chain;
19606 SDValue V = N.getOperand(0);
19607 for (; V.hasOneUse(); V = V.getOperand(0)) {
19608 switch (V.getOpcode()) {
19610 return SDValue(); // Nothing combined!
19613 // Skip bitcasts as we always know the type for the target specific
19617 case X86ISD::PSHUFD:
19618 // Found another dword shuffle.
19621 case X86ISD::PSHUFLW:
19622 // Check that the low words (being shuffled) are the identity in the
19623 // dword shuffle, and the high words are self-contained.
19624 if (Mask[0] != 0 || Mask[1] != 1 ||
19625 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19628 Chain.push_back(V);
19631 case X86ISD::PSHUFHW:
19632 // Check that the high words (being shuffled) are the identity in the
19633 // dword shuffle, and the low words are self-contained.
19634 if (Mask[2] != 2 || Mask[3] != 3 ||
19635 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19638 Chain.push_back(V);
19641 case X86ISD::UNPCKL:
19642 case X86ISD::UNPCKH:
19643 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19644 // shuffle into a preceding word shuffle.
19645 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19648 // Search for a half-shuffle which we can combine with.
19649 unsigned CombineOp =
19650 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19651 if (V.getOperand(0) != V.getOperand(1) ||
19652 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19654 Chain.push_back(V);
19655 V = V.getOperand(0);
19657 switch (V.getOpcode()) {
19659 return SDValue(); // Nothing to combine.
19661 case X86ISD::PSHUFLW:
19662 case X86ISD::PSHUFHW:
19663 if (V.getOpcode() == CombineOp)
19666 Chain.push_back(V);
19670 V = V.getOperand(0);
19674 } while (V.hasOneUse());
19677 // Break out of the loop if we break out of the switch.
19681 if (!V.hasOneUse())
19682 // We fell out of the loop without finding a viable combining instruction.
19685 // Merge this node's mask and our incoming mask.
19686 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19687 for (int &M : Mask)
19689 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19690 getV4X86ShuffleImm8ForMask(Mask, DAG));
19692 // Rebuild the chain around this new shuffle.
19693 while (!Chain.empty()) {
19694 SDValue W = Chain.pop_back_val();
19696 if (V.getValueType() != W.getOperand(0).getValueType())
19697 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
19699 switch (W.getOpcode()) {
19701 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
19703 case X86ISD::UNPCKL:
19704 case X86ISD::UNPCKH:
19705 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
19708 case X86ISD::PSHUFD:
19709 case X86ISD::PSHUFLW:
19710 case X86ISD::PSHUFHW:
19711 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
19715 if (V.getValueType() != N.getValueType())
19716 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
19718 // Return the new chain to replace N.
19722 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19724 /// We walk up the chain, skipping shuffles of the other half and looking
19725 /// through shuffles which switch halves trying to find a shuffle of the same
19726 /// pair of dwords.
19727 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19729 TargetLowering::DAGCombinerInfo &DCI) {
19731 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19732 "Called with something other than an x86 128-bit half shuffle!");
19734 unsigned CombineOpcode = N.getOpcode();
19736 // Walk up a single-use chain looking for a combinable shuffle.
19737 SDValue V = N.getOperand(0);
19738 for (; V.hasOneUse(); V = V.getOperand(0)) {
19739 switch (V.getOpcode()) {
19741 return false; // Nothing combined!
19744 // Skip bitcasts as we always know the type for the target specific
19748 case X86ISD::PSHUFLW:
19749 case X86ISD::PSHUFHW:
19750 if (V.getOpcode() == CombineOpcode)
19753 // Other-half shuffles are no-ops.
19756 // Break out of the loop if we break out of the switch.
19760 if (!V.hasOneUse())
19761 // We fell out of the loop without finding a viable combining instruction.
19764 // Combine away the bottom node as its shuffle will be accumulated into
19765 // a preceding shuffle.
19766 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19768 // Record the old value.
19771 // Merge this node's mask and our incoming mask (adjusted to account for all
19772 // the pshufd instructions encountered).
19773 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19774 for (int &M : Mask)
19776 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19777 getV4X86ShuffleImm8ForMask(Mask, DAG));
19779 // Check that the shuffles didn't cancel each other out. If not, we need to
19780 // combine to the new one.
19782 // Replace the combinable shuffle with the combined one, updating all users
19783 // so that we re-evaluate the chain here.
19784 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19789 /// \brief Try to combine x86 target specific shuffles.
19790 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19791 TargetLowering::DAGCombinerInfo &DCI,
19792 const X86Subtarget *Subtarget) {
19794 MVT VT = N.getSimpleValueType();
19795 SmallVector<int, 4> Mask;
19797 switch (N.getOpcode()) {
19798 case X86ISD::PSHUFD:
19799 case X86ISD::PSHUFLW:
19800 case X86ISD::PSHUFHW:
19801 Mask = getPSHUFShuffleMask(N);
19802 assert(Mask.size() == 4);
19808 // Nuke no-op shuffles that show up after combining.
19809 if (isNoopShuffleMask(Mask))
19810 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19812 // Look for simplifications involving one or two shuffle instructions.
19813 SDValue V = N.getOperand(0);
19814 switch (N.getOpcode()) {
19817 case X86ISD::PSHUFLW:
19818 case X86ISD::PSHUFHW:
19819 assert(VT == MVT::v8i16);
19822 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19823 return SDValue(); // We combined away this shuffle, so we're done.
19825 // See if this reduces to a PSHUFD which is no more expensive and can
19826 // combine with more operations.
19827 if (canWidenShuffleElements(Mask)) {
19828 int DMask[] = {-1, -1, -1, -1};
19829 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19830 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19831 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19832 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19833 DCI.AddToWorklist(V.getNode());
19834 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19835 getV4X86ShuffleImm8ForMask(DMask, DAG));
19836 DCI.AddToWorklist(V.getNode());
19837 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19840 // Look for shuffle patterns which can be implemented as a single unpack.
19841 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19842 // only works when we have a PSHUFD followed by two half-shuffles.
19843 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19844 (V.getOpcode() == X86ISD::PSHUFLW ||
19845 V.getOpcode() == X86ISD::PSHUFHW) &&
19846 V.getOpcode() != N.getOpcode() &&
19848 SDValue D = V.getOperand(0);
19849 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19850 D = D.getOperand(0);
19851 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19852 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19853 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19854 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19855 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19857 for (int i = 0; i < 4; ++i) {
19858 WordMask[i + NOffset] = Mask[i] + NOffset;
19859 WordMask[i + VOffset] = VMask[i] + VOffset;
19861 // Map the word mask through the DWord mask.
19863 for (int i = 0; i < 8; ++i)
19864 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19865 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19866 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19867 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19868 std::begin(UnpackLoMask)) ||
19869 std::equal(std::begin(MappedMask), std::end(MappedMask),
19870 std::begin(UnpackHiMask))) {
19871 // We can replace all three shuffles with an unpack.
19872 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19873 DCI.AddToWorklist(V.getNode());
19874 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19876 DL, MVT::v8i16, V, V);
19883 case X86ISD::PSHUFD:
19884 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19893 /// PerformShuffleCombine - Performs several different shuffle combines.
19894 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19895 TargetLowering::DAGCombinerInfo &DCI,
19896 const X86Subtarget *Subtarget) {
19898 SDValue N0 = N->getOperand(0);
19899 SDValue N1 = N->getOperand(1);
19900 EVT VT = N->getValueType(0);
19902 // Don't create instructions with illegal types after legalize types has run.
19903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19904 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19907 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19908 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19909 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19910 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19912 // During Type Legalization, when promoting illegal vector types,
19913 // the backend might introduce new shuffle dag nodes and bitcasts.
19915 // This code performs the following transformation:
19916 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19917 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19919 // We do this only if both the bitcast and the BINOP dag nodes have
19920 // one use. Also, perform this transformation only if the new binary
19921 // operation is legal. This is to avoid introducing dag nodes that
19922 // potentially need to be further expanded (or custom lowered) into a
19923 // less optimal sequence of dag nodes.
19924 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19925 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19926 N0.getOpcode() == ISD::BITCAST) {
19927 SDValue BC0 = N0.getOperand(0);
19928 EVT SVT = BC0.getValueType();
19929 unsigned Opcode = BC0.getOpcode();
19930 unsigned NumElts = VT.getVectorNumElements();
19932 if (BC0.hasOneUse() && SVT.isVector() &&
19933 SVT.getVectorNumElements() * 2 == NumElts &&
19934 TLI.isOperationLegal(Opcode, VT)) {
19935 bool CanFold = false;
19947 unsigned SVTNumElts = SVT.getVectorNumElements();
19948 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19949 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19950 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19951 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19952 CanFold = SVOp->getMaskElt(i) < 0;
19955 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19956 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19957 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19958 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19963 // Only handle 128 wide vector from here on.
19964 if (!VT.is128BitVector())
19967 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19968 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19969 // consecutive, non-overlapping, and in the right order.
19970 SmallVector<SDValue, 16> Elts;
19971 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19972 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19974 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19978 if (isTargetShuffle(N->getOpcode())) {
19980 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19981 if (Shuffle.getNode())
19984 // Try recursively combining arbitrary sequences of x86 shuffle
19985 // instructions into higher-order shuffles. We do this after combining
19986 // specific PSHUF instruction sequences into their minimal form so that we
19987 // can evaluate how many specialized shuffle instructions are involved in
19988 // a particular chain.
19989 SmallVector<int, 1> NonceMask; // Just a placeholder.
19990 NonceMask.push_back(0);
19991 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19992 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19994 return SDValue(); // This routine will use CombineTo to replace N.
20000 /// PerformTruncateCombine - Converts truncate operation to
20001 /// a sequence of vector shuffle operations.
20002 /// It is possible when we truncate 256-bit vector to 128-bit vector
20003 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20004 TargetLowering::DAGCombinerInfo &DCI,
20005 const X86Subtarget *Subtarget) {
20009 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20010 /// specific shuffle of a load can be folded into a single element load.
20011 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20012 /// shuffles have been customed lowered so we need to handle those here.
20013 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20014 TargetLowering::DAGCombinerInfo &DCI) {
20015 if (DCI.isBeforeLegalizeOps())
20018 SDValue InVec = N->getOperand(0);
20019 SDValue EltNo = N->getOperand(1);
20021 if (!isa<ConstantSDNode>(EltNo))
20024 EVT VT = InVec.getValueType();
20026 if (InVec.getOpcode() == ISD::BITCAST) {
20027 // Don't duplicate a load with other uses.
20028 if (!InVec.hasOneUse())
20030 EVT BCVT = InVec.getOperand(0).getValueType();
20031 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20033 InVec = InVec.getOperand(0);
20036 if (!isTargetShuffle(InVec.getOpcode()))
20039 // Don't duplicate a load with other uses.
20040 if (!InVec.hasOneUse())
20043 SmallVector<int, 16> ShuffleMask;
20045 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20049 // Select the input vector, guarding against out of range extract vector.
20050 unsigned NumElems = VT.getVectorNumElements();
20051 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20052 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20053 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20054 : InVec.getOperand(1);
20056 // If inputs to shuffle are the same for both ops, then allow 2 uses
20057 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20059 if (LdNode.getOpcode() == ISD::BITCAST) {
20060 // Don't duplicate a load with other uses.
20061 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20064 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20065 LdNode = LdNode.getOperand(0);
20068 if (!ISD::isNormalLoad(LdNode.getNode()))
20071 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20073 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20076 EVT EltVT = N->getValueType(0);
20077 // If there's a bitcast before the shuffle, check if the load type and
20078 // alignment is valid.
20079 unsigned Align = LN0->getAlignment();
20080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20081 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20082 EltVT.getTypeForEVT(*DAG.getContext()));
20084 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20087 // All checks match so transform back to vector_shuffle so that DAG combiner
20088 // can finish the job
20091 // Create shuffle node taking into account the case that its a unary shuffle
20092 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20093 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20094 InVec.getOperand(0), Shuffle,
20096 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20097 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20101 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20102 /// generation and convert it from being a bunch of shuffles and extracts
20103 /// to a simple store and scalar loads to extract the elements.
20104 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20105 TargetLowering::DAGCombinerInfo &DCI) {
20106 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20107 if (NewOp.getNode())
20110 SDValue InputVector = N->getOperand(0);
20112 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20113 // from mmx to v2i32 has a single usage.
20114 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20115 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20116 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20117 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20118 N->getValueType(0),
20119 InputVector.getNode()->getOperand(0));
20121 // Only operate on vectors of 4 elements, where the alternative shuffling
20122 // gets to be more expensive.
20123 if (InputVector.getValueType() != MVT::v4i32)
20126 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20127 // single use which is a sign-extend or zero-extend, and all elements are
20129 SmallVector<SDNode *, 4> Uses;
20130 unsigned ExtractedElements = 0;
20131 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20132 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20133 if (UI.getUse().getResNo() != InputVector.getResNo())
20136 SDNode *Extract = *UI;
20137 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20140 if (Extract->getValueType(0) != MVT::i32)
20142 if (!Extract->hasOneUse())
20144 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20145 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20147 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20150 // Record which element was extracted.
20151 ExtractedElements |=
20152 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20154 Uses.push_back(Extract);
20157 // If not all the elements were used, this may not be worthwhile.
20158 if (ExtractedElements != 15)
20161 // Ok, we've now decided to do the transformation.
20162 SDLoc dl(InputVector);
20164 // Store the value to a temporary stack slot.
20165 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20166 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20167 MachinePointerInfo(), false, false, 0);
20169 // Replace each use (extract) with a load of the appropriate element.
20170 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20171 UE = Uses.end(); UI != UE; ++UI) {
20172 SDNode *Extract = *UI;
20174 // cOMpute the element's address.
20175 SDValue Idx = Extract->getOperand(1);
20177 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20178 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20180 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20182 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20183 StackPtr, OffsetVal);
20185 // Load the scalar.
20186 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20187 ScalarAddr, MachinePointerInfo(),
20188 false, false, false, 0);
20190 // Replace the exact with the load.
20191 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20194 // The replacement was made in place; don't return anything.
20198 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20199 static std::pair<unsigned, bool>
20200 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20201 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20202 if (!VT.isVector())
20203 return std::make_pair(0, false);
20205 bool NeedSplit = false;
20206 switch (VT.getSimpleVT().SimpleTy) {
20207 default: return std::make_pair(0, false);
20211 if (!Subtarget->hasAVX2())
20213 if (!Subtarget->hasAVX())
20214 return std::make_pair(0, false);
20219 if (!Subtarget->hasSSE2())
20220 return std::make_pair(0, false);
20223 // SSE2 has only a small subset of the operations.
20224 bool hasUnsigned = Subtarget->hasSSE41() ||
20225 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20226 bool hasSigned = Subtarget->hasSSE41() ||
20227 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20229 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20232 // Check for x CC y ? x : y.
20233 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20234 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20239 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20242 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20245 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20248 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20250 // Check for x CC y ? y : x -- a min/max with reversed arms.
20251 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20252 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20257 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20260 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20263 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20266 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20270 return std::make_pair(Opc, NeedSplit);
20274 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20275 const X86Subtarget *Subtarget) {
20277 SDValue Cond = N->getOperand(0);
20278 SDValue LHS = N->getOperand(1);
20279 SDValue RHS = N->getOperand(2);
20281 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20282 SDValue CondSrc = Cond->getOperand(0);
20283 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20284 Cond = CondSrc->getOperand(0);
20287 MVT VT = N->getSimpleValueType(0);
20288 MVT EltVT = VT.getVectorElementType();
20289 unsigned NumElems = VT.getVectorNumElements();
20290 // There is no blend with immediate in AVX-512.
20291 if (VT.is512BitVector())
20294 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20296 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20299 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20302 // A vselect where all conditions and data are constants can be optimized into
20303 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20304 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20305 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20308 unsigned MaskValue = 0;
20309 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20312 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20313 for (unsigned i = 0; i < NumElems; ++i) {
20314 // Be sure we emit undef where we can.
20315 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20316 ShuffleMask[i] = -1;
20318 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20321 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20324 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20326 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20327 TargetLowering::DAGCombinerInfo &DCI,
20328 const X86Subtarget *Subtarget) {
20330 SDValue Cond = N->getOperand(0);
20331 // Get the LHS/RHS of the select.
20332 SDValue LHS = N->getOperand(1);
20333 SDValue RHS = N->getOperand(2);
20334 EVT VT = LHS.getValueType();
20335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20337 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20338 // instructions match the semantics of the common C idiom x<y?x:y but not
20339 // x<=y?x:y, because of how they handle negative zero (which can be
20340 // ignored in unsafe-math mode).
20341 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20342 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20343 (Subtarget->hasSSE2() ||
20344 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20345 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20347 unsigned Opcode = 0;
20348 // Check for x CC y ? x : y.
20349 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20350 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20354 // Converting this to a min would handle NaNs incorrectly, and swapping
20355 // the operands would cause it to handle comparisons between positive
20356 // and negative zero incorrectly.
20357 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20358 if (!DAG.getTarget().Options.UnsafeFPMath &&
20359 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20361 std::swap(LHS, RHS);
20363 Opcode = X86ISD::FMIN;
20366 // Converting this to a min would handle comparisons between positive
20367 // and negative zero incorrectly.
20368 if (!DAG.getTarget().Options.UnsafeFPMath &&
20369 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20371 Opcode = X86ISD::FMIN;
20374 // Converting this to a min would handle both negative zeros and NaNs
20375 // incorrectly, but we can swap the operands to fix both.
20376 std::swap(LHS, RHS);
20380 Opcode = X86ISD::FMIN;
20384 // Converting this to a max would handle comparisons between positive
20385 // and negative zero incorrectly.
20386 if (!DAG.getTarget().Options.UnsafeFPMath &&
20387 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20389 Opcode = X86ISD::FMAX;
20392 // Converting this to a max would handle NaNs incorrectly, and swapping
20393 // the operands would cause it to handle comparisons between positive
20394 // and negative zero incorrectly.
20395 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20396 if (!DAG.getTarget().Options.UnsafeFPMath &&
20397 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20399 std::swap(LHS, RHS);
20401 Opcode = X86ISD::FMAX;
20404 // Converting this to a max would handle both negative zeros and NaNs
20405 // incorrectly, but we can swap the operands to fix both.
20406 std::swap(LHS, RHS);
20410 Opcode = X86ISD::FMAX;
20413 // Check for x CC y ? y : x -- a min/max with reversed arms.
20414 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20415 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20419 // Converting this to a min would handle comparisons between positive
20420 // and negative zero incorrectly, and swapping the operands would
20421 // cause it to handle NaNs incorrectly.
20422 if (!DAG.getTarget().Options.UnsafeFPMath &&
20423 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20424 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20426 std::swap(LHS, RHS);
20428 Opcode = X86ISD::FMIN;
20431 // Converting this to a min would handle NaNs incorrectly.
20432 if (!DAG.getTarget().Options.UnsafeFPMath &&
20433 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20435 Opcode = X86ISD::FMIN;
20438 // Converting this to a min would handle both negative zeros and NaNs
20439 // incorrectly, but we can swap the operands to fix both.
20440 std::swap(LHS, RHS);
20444 Opcode = X86ISD::FMIN;
20448 // Converting this to a max would handle NaNs incorrectly.
20449 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20451 Opcode = X86ISD::FMAX;
20454 // Converting this to a max would handle comparisons between positive
20455 // and negative zero incorrectly, and swapping the operands would
20456 // cause it to handle NaNs incorrectly.
20457 if (!DAG.getTarget().Options.UnsafeFPMath &&
20458 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20459 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20461 std::swap(LHS, RHS);
20463 Opcode = X86ISD::FMAX;
20466 // Converting this to a max would handle both negative zeros and NaNs
20467 // incorrectly, but we can swap the operands to fix both.
20468 std::swap(LHS, RHS);
20472 Opcode = X86ISD::FMAX;
20478 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20481 EVT CondVT = Cond.getValueType();
20482 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20483 CondVT.getVectorElementType() == MVT::i1) {
20484 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20485 // lowering on KNL. In this case we convert it to
20486 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20487 // The same situation for all 128 and 256-bit vectors of i8 and i16.
20488 // Since SKX these selects have a proper lowering.
20489 EVT OpVT = LHS.getValueType();
20490 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20491 (OpVT.getVectorElementType() == MVT::i8 ||
20492 OpVT.getVectorElementType() == MVT::i16) &&
20493 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
20494 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20495 DCI.AddToWorklist(Cond.getNode());
20496 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20499 // If this is a select between two integer constants, try to do some
20501 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20502 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20503 // Don't do this for crazy integer types.
20504 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20505 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20506 // so that TrueC (the true value) is larger than FalseC.
20507 bool NeedsCondInvert = false;
20509 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20510 // Efficiently invertible.
20511 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20512 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20513 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20514 NeedsCondInvert = true;
20515 std::swap(TrueC, FalseC);
20518 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20519 if (FalseC->getAPIntValue() == 0 &&
20520 TrueC->getAPIntValue().isPowerOf2()) {
20521 if (NeedsCondInvert) // Invert the condition if needed.
20522 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20523 DAG.getConstant(1, Cond.getValueType()));
20525 // Zero extend the condition if needed.
20526 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20528 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20529 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20530 DAG.getConstant(ShAmt, MVT::i8));
20533 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20534 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20535 if (NeedsCondInvert) // Invert the condition if needed.
20536 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20537 DAG.getConstant(1, Cond.getValueType()));
20539 // Zero extend the condition if needed.
20540 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20541 FalseC->getValueType(0), Cond);
20542 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20543 SDValue(FalseC, 0));
20546 // Optimize cases that will turn into an LEA instruction. This requires
20547 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20548 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20549 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20550 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20552 bool isFastMultiplier = false;
20554 switch ((unsigned char)Diff) {
20556 case 1: // result = add base, cond
20557 case 2: // result = lea base( , cond*2)
20558 case 3: // result = lea base(cond, cond*2)
20559 case 4: // result = lea base( , cond*4)
20560 case 5: // result = lea base(cond, cond*4)
20561 case 8: // result = lea base( , cond*8)
20562 case 9: // result = lea base(cond, cond*8)
20563 isFastMultiplier = true;
20568 if (isFastMultiplier) {
20569 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20570 if (NeedsCondInvert) // Invert the condition if needed.
20571 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20572 DAG.getConstant(1, Cond.getValueType()));
20574 // Zero extend the condition if needed.
20575 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20577 // Scale the condition by the difference.
20579 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20580 DAG.getConstant(Diff, Cond.getValueType()));
20582 // Add the base if non-zero.
20583 if (FalseC->getAPIntValue() != 0)
20584 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20585 SDValue(FalseC, 0));
20592 // Canonicalize max and min:
20593 // (x > y) ? x : y -> (x >= y) ? x : y
20594 // (x < y) ? x : y -> (x <= y) ? x : y
20595 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20596 // the need for an extra compare
20597 // against zero. e.g.
20598 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20600 // testl %edi, %edi
20602 // cmovgl %edi, %eax
20606 // cmovsl %eax, %edi
20607 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20608 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20609 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20610 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20615 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20616 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20617 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20618 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20623 // Early exit check
20624 if (!TLI.isTypeLegal(VT))
20627 // Match VSELECTs into subs with unsigned saturation.
20628 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20629 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20630 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20631 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20632 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20634 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20635 // left side invert the predicate to simplify logic below.
20637 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20639 CC = ISD::getSetCCInverse(CC, true);
20640 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20644 if (Other.getNode() && Other->getNumOperands() == 2 &&
20645 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20646 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20647 SDValue CondRHS = Cond->getOperand(1);
20649 // Look for a general sub with unsigned saturation first.
20650 // x >= y ? x-y : 0 --> subus x, y
20651 // x > y ? x-y : 0 --> subus x, y
20652 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20653 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20654 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20656 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20657 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20658 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20659 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20660 // If the RHS is a constant we have to reverse the const
20661 // canonicalization.
20662 // x > C-1 ? x+-C : 0 --> subus x, C
20663 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20664 CondRHSConst->getAPIntValue() ==
20665 (-OpRHSConst->getAPIntValue() - 1))
20666 return DAG.getNode(
20667 X86ISD::SUBUS, DL, VT, OpLHS,
20668 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20670 // Another special case: If C was a sign bit, the sub has been
20671 // canonicalized into a xor.
20672 // FIXME: Would it be better to use computeKnownBits to determine
20673 // whether it's safe to decanonicalize the xor?
20674 // x s< 0 ? x^C : 0 --> subus x, C
20675 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20676 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20677 OpRHSConst->getAPIntValue().isSignBit())
20678 // Note that we have to rebuild the RHS constant here to ensure we
20679 // don't rely on particular values of undef lanes.
20680 return DAG.getNode(
20681 X86ISD::SUBUS, DL, VT, OpLHS,
20682 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20687 // Try to match a min/max vector operation.
20688 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20689 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20690 unsigned Opc = ret.first;
20691 bool NeedSplit = ret.second;
20693 if (Opc && NeedSplit) {
20694 unsigned NumElems = VT.getVectorNumElements();
20695 // Extract the LHS vectors
20696 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20697 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20699 // Extract the RHS vectors
20700 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20701 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20703 // Create min/max for each subvector
20704 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20705 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20707 // Merge the result
20708 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20710 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20713 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20714 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20715 // Check if SETCC has already been promoted
20716 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20717 // Check that condition value type matches vselect operand type
20720 assert(Cond.getValueType().isVector() &&
20721 "vector select expects a vector selector!");
20723 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20724 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20726 if (!TValIsAllOnes && !FValIsAllZeros) {
20727 // Try invert the condition if true value is not all 1s and false value
20729 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20730 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20732 if (TValIsAllZeros || FValIsAllOnes) {
20733 SDValue CC = Cond.getOperand(2);
20734 ISD::CondCode NewCC =
20735 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20736 Cond.getOperand(0).getValueType().isInteger());
20737 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20738 std::swap(LHS, RHS);
20739 TValIsAllOnes = FValIsAllOnes;
20740 FValIsAllZeros = TValIsAllZeros;
20744 if (TValIsAllOnes || FValIsAllZeros) {
20747 if (TValIsAllOnes && FValIsAllZeros)
20749 else if (TValIsAllOnes)
20750 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20751 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20752 else if (FValIsAllZeros)
20753 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20754 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20756 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20760 // Try to fold this VSELECT into a MOVSS/MOVSD
20761 if (N->getOpcode() == ISD::VSELECT &&
20762 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20763 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20764 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20765 bool CanFold = false;
20766 unsigned NumElems = Cond.getNumOperands();
20770 if (isZero(Cond.getOperand(0))) {
20773 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20774 // fold (vselect <0,-1> -> (movsd A, B)
20775 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20776 CanFold = isAllOnes(Cond.getOperand(i));
20777 } else if (isAllOnes(Cond.getOperand(0))) {
20781 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20782 // fold (vselect <-1,0> -> (movsd B, A)
20783 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20784 CanFold = isZero(Cond.getOperand(i));
20788 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20789 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20790 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20793 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20794 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20795 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20796 // (v2i64 (bitcast B)))))
20798 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20799 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20800 // (v2f64 (bitcast B)))))
20802 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20803 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20804 // (v2i64 (bitcast A)))))
20806 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20807 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20808 // (v2f64 (bitcast A)))))
20810 CanFold = (isZero(Cond.getOperand(0)) &&
20811 isZero(Cond.getOperand(1)) &&
20812 isAllOnes(Cond.getOperand(2)) &&
20813 isAllOnes(Cond.getOperand(3)));
20815 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20816 isAllOnes(Cond.getOperand(1)) &&
20817 isZero(Cond.getOperand(2)) &&
20818 isZero(Cond.getOperand(3))) {
20820 std::swap(LHS, RHS);
20824 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20825 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20826 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20827 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20829 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20835 // If we know that this node is legal then we know that it is going to be
20836 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20837 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20838 // to simplify previous instructions.
20839 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20840 !DCI.isBeforeLegalize() &&
20841 // We explicitly check against v8i16 and v16i16 because, although
20842 // they're marked as Custom, they might only be legal when Cond is a
20843 // build_vector of constants. This will be taken care in a later
20845 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20846 VT != MVT::v8i16)) {
20847 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20849 // Don't optimize vector selects that map to mask-registers.
20853 // Check all uses of that condition operand to check whether it will be
20854 // consumed by non-BLEND instructions, which may depend on all bits are set
20856 for (SDNode::use_iterator I = Cond->use_begin(),
20857 E = Cond->use_end(); I != E; ++I)
20858 if (I->getOpcode() != ISD::VSELECT)
20859 // TODO: Add other opcodes eventually lowered into BLEND.
20862 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20863 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20865 APInt KnownZero, KnownOne;
20866 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20867 DCI.isBeforeLegalizeOps());
20868 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20869 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20870 DCI.CommitTargetLoweringOpt(TLO);
20873 // We should generate an X86ISD::BLENDI from a vselect if its argument
20874 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20875 // constants. This specific pattern gets generated when we split a
20876 // selector for a 512 bit vector in a machine without AVX512 (but with
20877 // 256-bit vectors), during legalization:
20879 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20881 // Iff we find this pattern and the build_vectors are built from
20882 // constants, we translate the vselect into a shuffle_vector that we
20883 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20884 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20885 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20886 if (Shuffle.getNode())
20893 // Check whether a boolean test is testing a boolean value generated by
20894 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20897 // Simplify the following patterns:
20898 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20899 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20900 // to (Op EFLAGS Cond)
20902 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20903 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20904 // to (Op EFLAGS !Cond)
20906 // where Op could be BRCOND or CMOV.
20908 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20909 // Quit if not CMP and SUB with its value result used.
20910 if (Cmp.getOpcode() != X86ISD::CMP &&
20911 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20914 // Quit if not used as a boolean value.
20915 if (CC != X86::COND_E && CC != X86::COND_NE)
20918 // Check CMP operands. One of them should be 0 or 1 and the other should be
20919 // an SetCC or extended from it.
20920 SDValue Op1 = Cmp.getOperand(0);
20921 SDValue Op2 = Cmp.getOperand(1);
20924 const ConstantSDNode* C = nullptr;
20925 bool needOppositeCond = (CC == X86::COND_E);
20926 bool checkAgainstTrue = false; // Is it a comparison against 1?
20928 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20930 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20932 else // Quit if all operands are not constants.
20935 if (C->getZExtValue() == 1) {
20936 needOppositeCond = !needOppositeCond;
20937 checkAgainstTrue = true;
20938 } else if (C->getZExtValue() != 0)
20939 // Quit if the constant is neither 0 or 1.
20942 bool truncatedToBoolWithAnd = false;
20943 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20944 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20945 SetCC.getOpcode() == ISD::TRUNCATE ||
20946 SetCC.getOpcode() == ISD::AND) {
20947 if (SetCC.getOpcode() == ISD::AND) {
20949 ConstantSDNode *CS;
20950 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20951 CS->getZExtValue() == 1)
20953 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20954 CS->getZExtValue() == 1)
20958 SetCC = SetCC.getOperand(OpIdx);
20959 truncatedToBoolWithAnd = true;
20961 SetCC = SetCC.getOperand(0);
20964 switch (SetCC.getOpcode()) {
20965 case X86ISD::SETCC_CARRY:
20966 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20967 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20968 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20969 // truncated to i1 using 'and'.
20970 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20972 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20973 "Invalid use of SETCC_CARRY!");
20975 case X86ISD::SETCC:
20976 // Set the condition code or opposite one if necessary.
20977 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20978 if (needOppositeCond)
20979 CC = X86::GetOppositeBranchCondition(CC);
20980 return SetCC.getOperand(1);
20981 case X86ISD::CMOV: {
20982 // Check whether false/true value has canonical one, i.e. 0 or 1.
20983 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20984 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20985 // Quit if true value is not a constant.
20988 // Quit if false value is not a constant.
20990 SDValue Op = SetCC.getOperand(0);
20991 // Skip 'zext' or 'trunc' node.
20992 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20993 Op.getOpcode() == ISD::TRUNCATE)
20994 Op = Op.getOperand(0);
20995 // A special case for rdrand/rdseed, where 0 is set if false cond is
20997 if ((Op.getOpcode() != X86ISD::RDRAND &&
20998 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21001 // Quit if false value is not the constant 0 or 1.
21002 bool FValIsFalse = true;
21003 if (FVal && FVal->getZExtValue() != 0) {
21004 if (FVal->getZExtValue() != 1)
21006 // If FVal is 1, opposite cond is needed.
21007 needOppositeCond = !needOppositeCond;
21008 FValIsFalse = false;
21010 // Quit if TVal is not the constant opposite of FVal.
21011 if (FValIsFalse && TVal->getZExtValue() != 1)
21013 if (!FValIsFalse && TVal->getZExtValue() != 0)
21015 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21016 if (needOppositeCond)
21017 CC = X86::GetOppositeBranchCondition(CC);
21018 return SetCC.getOperand(3);
21025 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21026 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21027 TargetLowering::DAGCombinerInfo &DCI,
21028 const X86Subtarget *Subtarget) {
21031 // If the flag operand isn't dead, don't touch this CMOV.
21032 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21035 SDValue FalseOp = N->getOperand(0);
21036 SDValue TrueOp = N->getOperand(1);
21037 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21038 SDValue Cond = N->getOperand(3);
21040 if (CC == X86::COND_E || CC == X86::COND_NE) {
21041 switch (Cond.getOpcode()) {
21045 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21046 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21047 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21053 Flags = checkBoolTestSetCCCombine(Cond, CC);
21054 if (Flags.getNode() &&
21055 // Extra check as FCMOV only supports a subset of X86 cond.
21056 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21057 SDValue Ops[] = { FalseOp, TrueOp,
21058 DAG.getConstant(CC, MVT::i8), Flags };
21059 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21062 // If this is a select between two integer constants, try to do some
21063 // optimizations. Note that the operands are ordered the opposite of SELECT
21065 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21066 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21067 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21068 // larger than FalseC (the false value).
21069 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21070 CC = X86::GetOppositeBranchCondition(CC);
21071 std::swap(TrueC, FalseC);
21072 std::swap(TrueOp, FalseOp);
21075 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21076 // This is efficient for any integer data type (including i8/i16) and
21078 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21079 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21080 DAG.getConstant(CC, MVT::i8), Cond);
21082 // Zero extend the condition if needed.
21083 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21085 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21086 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21087 DAG.getConstant(ShAmt, MVT::i8));
21088 if (N->getNumValues() == 2) // Dead flag value?
21089 return DCI.CombineTo(N, Cond, SDValue());
21093 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21094 // for any integer data type, including i8/i16.
21095 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21096 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21097 DAG.getConstant(CC, MVT::i8), Cond);
21099 // Zero extend the condition if needed.
21100 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21101 FalseC->getValueType(0), Cond);
21102 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21103 SDValue(FalseC, 0));
21105 if (N->getNumValues() == 2) // Dead flag value?
21106 return DCI.CombineTo(N, Cond, SDValue());
21110 // Optimize cases that will turn into an LEA instruction. This requires
21111 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21112 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21113 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21114 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21116 bool isFastMultiplier = false;
21118 switch ((unsigned char)Diff) {
21120 case 1: // result = add base, cond
21121 case 2: // result = lea base( , cond*2)
21122 case 3: // result = lea base(cond, cond*2)
21123 case 4: // result = lea base( , cond*4)
21124 case 5: // result = lea base(cond, cond*4)
21125 case 8: // result = lea base( , cond*8)
21126 case 9: // result = lea base(cond, cond*8)
21127 isFastMultiplier = true;
21132 if (isFastMultiplier) {
21133 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21134 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21135 DAG.getConstant(CC, MVT::i8), Cond);
21136 // Zero extend the condition if needed.
21137 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21139 // Scale the condition by the difference.
21141 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21142 DAG.getConstant(Diff, Cond.getValueType()));
21144 // Add the base if non-zero.
21145 if (FalseC->getAPIntValue() != 0)
21146 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21147 SDValue(FalseC, 0));
21148 if (N->getNumValues() == 2) // Dead flag value?
21149 return DCI.CombineTo(N, Cond, SDValue());
21156 // Handle these cases:
21157 // (select (x != c), e, c) -> select (x != c), e, x),
21158 // (select (x == c), c, e) -> select (x == c), x, e)
21159 // where the c is an integer constant, and the "select" is the combination
21160 // of CMOV and CMP.
21162 // The rationale for this change is that the conditional-move from a constant
21163 // needs two instructions, however, conditional-move from a register needs
21164 // only one instruction.
21166 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21167 // some instruction-combining opportunities. This opt needs to be
21168 // postponed as late as possible.
21170 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21171 // the DCI.xxxx conditions are provided to postpone the optimization as
21172 // late as possible.
21174 ConstantSDNode *CmpAgainst = nullptr;
21175 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21176 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21177 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21179 if (CC == X86::COND_NE &&
21180 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21181 CC = X86::GetOppositeBranchCondition(CC);
21182 std::swap(TrueOp, FalseOp);
21185 if (CC == X86::COND_E &&
21186 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21187 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21188 DAG.getConstant(CC, MVT::i8), Cond };
21189 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21197 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21198 const X86Subtarget *Subtarget) {
21199 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21201 default: return SDValue();
21202 // SSE/AVX/AVX2 blend intrinsics.
21203 case Intrinsic::x86_avx2_pblendvb:
21204 case Intrinsic::x86_avx2_pblendw:
21205 case Intrinsic::x86_avx2_pblendd_128:
21206 case Intrinsic::x86_avx2_pblendd_256:
21207 // Don't try to simplify this intrinsic if we don't have AVX2.
21208 if (!Subtarget->hasAVX2())
21211 case Intrinsic::x86_avx_blend_pd_256:
21212 case Intrinsic::x86_avx_blend_ps_256:
21213 case Intrinsic::x86_avx_blendv_pd_256:
21214 case Intrinsic::x86_avx_blendv_ps_256:
21215 // Don't try to simplify this intrinsic if we don't have AVX.
21216 if (!Subtarget->hasAVX())
21219 case Intrinsic::x86_sse41_pblendw:
21220 case Intrinsic::x86_sse41_blendpd:
21221 case Intrinsic::x86_sse41_blendps:
21222 case Intrinsic::x86_sse41_blendvps:
21223 case Intrinsic::x86_sse41_blendvpd:
21224 case Intrinsic::x86_sse41_pblendvb: {
21225 SDValue Op0 = N->getOperand(1);
21226 SDValue Op1 = N->getOperand(2);
21227 SDValue Mask = N->getOperand(3);
21229 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21230 if (!Subtarget->hasSSE41())
21233 // fold (blend A, A, Mask) -> A
21236 // fold (blend A, B, allZeros) -> A
21237 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21239 // fold (blend A, B, allOnes) -> B
21240 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21243 // Simplify the case where the mask is a constant i32 value.
21244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21245 if (C->isNullValue())
21247 if (C->isAllOnesValue())
21254 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21255 case Intrinsic::x86_sse2_psrai_w:
21256 case Intrinsic::x86_sse2_psrai_d:
21257 case Intrinsic::x86_avx2_psrai_w:
21258 case Intrinsic::x86_avx2_psrai_d:
21259 case Intrinsic::x86_sse2_psra_w:
21260 case Intrinsic::x86_sse2_psra_d:
21261 case Intrinsic::x86_avx2_psra_w:
21262 case Intrinsic::x86_avx2_psra_d: {
21263 SDValue Op0 = N->getOperand(1);
21264 SDValue Op1 = N->getOperand(2);
21265 EVT VT = Op0.getValueType();
21266 assert(VT.isVector() && "Expected a vector type!");
21268 if (isa<BuildVectorSDNode>(Op1))
21269 Op1 = Op1.getOperand(0);
21271 if (!isa<ConstantSDNode>(Op1))
21274 EVT SVT = VT.getVectorElementType();
21275 unsigned SVTBits = SVT.getSizeInBits();
21277 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21278 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21279 uint64_t ShAmt = C.getZExtValue();
21281 // Don't try to convert this shift into a ISD::SRA if the shift
21282 // count is bigger than or equal to the element size.
21283 if (ShAmt >= SVTBits)
21286 // Trivial case: if the shift count is zero, then fold this
21287 // into the first operand.
21291 // Replace this packed shift intrinsic with a target independent
21293 SDValue Splat = DAG.getConstant(C, VT);
21294 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21299 /// PerformMulCombine - Optimize a single multiply with constant into two
21300 /// in order to implement it with two cheaper instructions, e.g.
21301 /// LEA + SHL, LEA + LEA.
21302 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21303 TargetLowering::DAGCombinerInfo &DCI) {
21304 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21307 EVT VT = N->getValueType(0);
21308 if (VT != MVT::i64)
21311 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21314 uint64_t MulAmt = C->getZExtValue();
21315 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21318 uint64_t MulAmt1 = 0;
21319 uint64_t MulAmt2 = 0;
21320 if ((MulAmt % 9) == 0) {
21322 MulAmt2 = MulAmt / 9;
21323 } else if ((MulAmt % 5) == 0) {
21325 MulAmt2 = MulAmt / 5;
21326 } else if ((MulAmt % 3) == 0) {
21328 MulAmt2 = MulAmt / 3;
21331 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21334 if (isPowerOf2_64(MulAmt2) &&
21335 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21336 // If second multiplifer is pow2, issue it first. We want the multiply by
21337 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21339 std::swap(MulAmt1, MulAmt2);
21342 if (isPowerOf2_64(MulAmt1))
21343 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21344 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21346 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21347 DAG.getConstant(MulAmt1, VT));
21349 if (isPowerOf2_64(MulAmt2))
21350 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21351 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21353 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21354 DAG.getConstant(MulAmt2, VT));
21356 // Do not add new nodes to DAG combiner worklist.
21357 DCI.CombineTo(N, NewMul, false);
21362 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21363 SDValue N0 = N->getOperand(0);
21364 SDValue N1 = N->getOperand(1);
21365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21366 EVT VT = N0.getValueType();
21368 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21369 // since the result of setcc_c is all zero's or all ones.
21370 if (VT.isInteger() && !VT.isVector() &&
21371 N1C && N0.getOpcode() == ISD::AND &&
21372 N0.getOperand(1).getOpcode() == ISD::Constant) {
21373 SDValue N00 = N0.getOperand(0);
21374 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21375 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21376 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21377 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21378 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21379 APInt ShAmt = N1C->getAPIntValue();
21380 Mask = Mask.shl(ShAmt);
21382 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21383 N00, DAG.getConstant(Mask, VT));
21387 // Hardware support for vector shifts is sparse which makes us scalarize the
21388 // vector operations in many cases. Also, on sandybridge ADD is faster than
21390 // (shl V, 1) -> add V,V
21391 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21392 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21393 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21394 // We shift all of the values by one. In many cases we do not have
21395 // hardware support for this operation. This is better expressed as an ADD
21397 if (N1SplatC->getZExtValue() == 1)
21398 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21404 /// \brief Returns a vector of 0s if the node in input is a vector logical
21405 /// shift by a constant amount which is known to be bigger than or equal
21406 /// to the vector element size in bits.
21407 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21408 const X86Subtarget *Subtarget) {
21409 EVT VT = N->getValueType(0);
21411 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21412 (!Subtarget->hasInt256() ||
21413 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21416 SDValue Amt = N->getOperand(1);
21418 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21419 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21420 APInt ShiftAmt = AmtSplat->getAPIntValue();
21421 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21423 // SSE2/AVX2 logical shifts always return a vector of 0s
21424 // if the shift amount is bigger than or equal to
21425 // the element size. The constant shift amount will be
21426 // encoded as a 8-bit immediate.
21427 if (ShiftAmt.trunc(8).uge(MaxAmount))
21428 return getZeroVector(VT, Subtarget, DAG, DL);
21434 /// PerformShiftCombine - Combine shifts.
21435 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21436 TargetLowering::DAGCombinerInfo &DCI,
21437 const X86Subtarget *Subtarget) {
21438 if (N->getOpcode() == ISD::SHL) {
21439 SDValue V = PerformSHLCombine(N, DAG);
21440 if (V.getNode()) return V;
21443 if (N->getOpcode() != ISD::SRA) {
21444 // Try to fold this logical shift into a zero vector.
21445 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21446 if (V.getNode()) return V;
21452 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21453 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21454 // and friends. Likewise for OR -> CMPNEQSS.
21455 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21456 TargetLowering::DAGCombinerInfo &DCI,
21457 const X86Subtarget *Subtarget) {
21460 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21461 // we're requiring SSE2 for both.
21462 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21463 SDValue N0 = N->getOperand(0);
21464 SDValue N1 = N->getOperand(1);
21465 SDValue CMP0 = N0->getOperand(1);
21466 SDValue CMP1 = N1->getOperand(1);
21469 // The SETCCs should both refer to the same CMP.
21470 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21473 SDValue CMP00 = CMP0->getOperand(0);
21474 SDValue CMP01 = CMP0->getOperand(1);
21475 EVT VT = CMP00.getValueType();
21477 if (VT == MVT::f32 || VT == MVT::f64) {
21478 bool ExpectingFlags = false;
21479 // Check for any users that want flags:
21480 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21481 !ExpectingFlags && UI != UE; ++UI)
21482 switch (UI->getOpcode()) {
21487 ExpectingFlags = true;
21489 case ISD::CopyToReg:
21490 case ISD::SIGN_EXTEND:
21491 case ISD::ZERO_EXTEND:
21492 case ISD::ANY_EXTEND:
21496 if (!ExpectingFlags) {
21497 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21498 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21500 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21501 X86::CondCode tmp = cc0;
21506 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21507 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21508 // FIXME: need symbolic constants for these magic numbers.
21509 // See X86ATTInstPrinter.cpp:printSSECC().
21510 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21511 if (Subtarget->hasAVX512()) {
21512 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21513 CMP01, DAG.getConstant(x86cc, MVT::i8));
21514 if (N->getValueType(0) != MVT::i1)
21515 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21519 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21520 CMP00.getValueType(), CMP00, CMP01,
21521 DAG.getConstant(x86cc, MVT::i8));
21523 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21524 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21526 if (is64BitFP && !Subtarget->is64Bit()) {
21527 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21528 // 64-bit integer, since that's not a legal type. Since
21529 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21530 // bits, but can do this little dance to extract the lowest 32 bits
21531 // and work with those going forward.
21532 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21534 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21536 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21537 Vector32, DAG.getIntPtrConstant(0));
21541 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21542 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21543 DAG.getConstant(1, IntVT));
21544 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21545 return OneBitOfTruth;
21553 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21554 /// so it can be folded inside ANDNP.
21555 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21556 EVT VT = N->getValueType(0);
21558 // Match direct AllOnes for 128 and 256-bit vectors
21559 if (ISD::isBuildVectorAllOnes(N))
21562 // Look through a bit convert.
21563 if (N->getOpcode() == ISD::BITCAST)
21564 N = N->getOperand(0).getNode();
21566 // Sometimes the operand may come from a insert_subvector building a 256-bit
21568 if (VT.is256BitVector() &&
21569 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21570 SDValue V1 = N->getOperand(0);
21571 SDValue V2 = N->getOperand(1);
21573 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21574 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21575 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21576 ISD::isBuildVectorAllOnes(V2.getNode()))
21583 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21584 // register. In most cases we actually compare or select YMM-sized registers
21585 // and mixing the two types creates horrible code. This method optimizes
21586 // some of the transition sequences.
21587 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21588 TargetLowering::DAGCombinerInfo &DCI,
21589 const X86Subtarget *Subtarget) {
21590 EVT VT = N->getValueType(0);
21591 if (!VT.is256BitVector())
21594 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21595 N->getOpcode() == ISD::ZERO_EXTEND ||
21596 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21598 SDValue Narrow = N->getOperand(0);
21599 EVT NarrowVT = Narrow->getValueType(0);
21600 if (!NarrowVT.is128BitVector())
21603 if (Narrow->getOpcode() != ISD::XOR &&
21604 Narrow->getOpcode() != ISD::AND &&
21605 Narrow->getOpcode() != ISD::OR)
21608 SDValue N0 = Narrow->getOperand(0);
21609 SDValue N1 = Narrow->getOperand(1);
21612 // The Left side has to be a trunc.
21613 if (N0.getOpcode() != ISD::TRUNCATE)
21616 // The type of the truncated inputs.
21617 EVT WideVT = N0->getOperand(0)->getValueType(0);
21621 // The right side has to be a 'trunc' or a constant vector.
21622 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21623 ConstantSDNode *RHSConstSplat = nullptr;
21624 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21625 RHSConstSplat = RHSBV->getConstantSplatNode();
21626 if (!RHSTrunc && !RHSConstSplat)
21629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21631 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21634 // Set N0 and N1 to hold the inputs to the new wide operation.
21635 N0 = N0->getOperand(0);
21636 if (RHSConstSplat) {
21637 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21638 SDValue(RHSConstSplat, 0));
21639 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21640 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21641 } else if (RHSTrunc) {
21642 N1 = N1->getOperand(0);
21645 // Generate the wide operation.
21646 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21647 unsigned Opcode = N->getOpcode();
21649 case ISD::ANY_EXTEND:
21651 case ISD::ZERO_EXTEND: {
21652 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21653 APInt Mask = APInt::getAllOnesValue(InBits);
21654 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21655 return DAG.getNode(ISD::AND, DL, VT,
21656 Op, DAG.getConstant(Mask, VT));
21658 case ISD::SIGN_EXTEND:
21659 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21660 Op, DAG.getValueType(NarrowVT));
21662 llvm_unreachable("Unexpected opcode");
21666 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21667 TargetLowering::DAGCombinerInfo &DCI,
21668 const X86Subtarget *Subtarget) {
21669 EVT VT = N->getValueType(0);
21670 if (DCI.isBeforeLegalizeOps())
21673 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21677 // Create BEXTR instructions
21678 // BEXTR is ((X >> imm) & (2**size-1))
21679 if (VT == MVT::i32 || VT == MVT::i64) {
21680 SDValue N0 = N->getOperand(0);
21681 SDValue N1 = N->getOperand(1);
21684 // Check for BEXTR.
21685 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21686 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21687 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21688 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21689 if (MaskNode && ShiftNode) {
21690 uint64_t Mask = MaskNode->getZExtValue();
21691 uint64_t Shift = ShiftNode->getZExtValue();
21692 if (isMask_64(Mask)) {
21693 uint64_t MaskSize = CountPopulation_64(Mask);
21694 if (Shift + MaskSize <= VT.getSizeInBits())
21695 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21696 DAG.getConstant(Shift | (MaskSize << 8), VT));
21704 // Want to form ANDNP nodes:
21705 // 1) In the hopes of then easily combining them with OR and AND nodes
21706 // to form PBLEND/PSIGN.
21707 // 2) To match ANDN packed intrinsics
21708 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21711 SDValue N0 = N->getOperand(0);
21712 SDValue N1 = N->getOperand(1);
21715 // Check LHS for vnot
21716 if (N0.getOpcode() == ISD::XOR &&
21717 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21718 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21719 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21721 // Check RHS for vnot
21722 if (N1.getOpcode() == ISD::XOR &&
21723 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21724 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21725 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21730 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21731 TargetLowering::DAGCombinerInfo &DCI,
21732 const X86Subtarget *Subtarget) {
21733 if (DCI.isBeforeLegalizeOps())
21736 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21740 SDValue N0 = N->getOperand(0);
21741 SDValue N1 = N->getOperand(1);
21742 EVT VT = N->getValueType(0);
21744 // look for psign/blend
21745 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21746 if (!Subtarget->hasSSSE3() ||
21747 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21750 // Canonicalize pandn to RHS
21751 if (N0.getOpcode() == X86ISD::ANDNP)
21753 // or (and (m, y), (pandn m, x))
21754 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21755 SDValue Mask = N1.getOperand(0);
21756 SDValue X = N1.getOperand(1);
21758 if (N0.getOperand(0) == Mask)
21759 Y = N0.getOperand(1);
21760 if (N0.getOperand(1) == Mask)
21761 Y = N0.getOperand(0);
21763 // Check to see if the mask appeared in both the AND and ANDNP and
21767 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21768 // Look through mask bitcast.
21769 if (Mask.getOpcode() == ISD::BITCAST)
21770 Mask = Mask.getOperand(0);
21771 if (X.getOpcode() == ISD::BITCAST)
21772 X = X.getOperand(0);
21773 if (Y.getOpcode() == ISD::BITCAST)
21774 Y = Y.getOperand(0);
21776 EVT MaskVT = Mask.getValueType();
21778 // Validate that the Mask operand is a vector sra node.
21779 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21780 // there is no psrai.b
21781 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21782 unsigned SraAmt = ~0;
21783 if (Mask.getOpcode() == ISD::SRA) {
21784 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21785 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21786 SraAmt = AmtConst->getZExtValue();
21787 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21788 SDValue SraC = Mask.getOperand(1);
21789 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21791 if ((SraAmt + 1) != EltBits)
21796 // Now we know we at least have a plendvb with the mask val. See if
21797 // we can form a psignb/w/d.
21798 // psign = x.type == y.type == mask.type && y = sub(0, x);
21799 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21800 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21801 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21802 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21803 "Unsupported VT for PSIGN");
21804 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21805 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21807 // PBLENDVB only available on SSE 4.1
21808 if (!Subtarget->hasSSE41())
21811 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21813 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21814 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21815 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21816 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21817 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21821 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21824 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21825 MachineFunction &MF = DAG.getMachineFunction();
21826 bool OptForSize = MF.getFunction()->getAttributes().
21827 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21829 // SHLD/SHRD instructions have lower register pressure, but on some
21830 // platforms they have higher latency than the equivalent
21831 // series of shifts/or that would otherwise be generated.
21832 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21833 // have higher latencies and we are not optimizing for size.
21834 if (!OptForSize && Subtarget->isSHLDSlow())
21837 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21839 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21841 if (!N0.hasOneUse() || !N1.hasOneUse())
21844 SDValue ShAmt0 = N0.getOperand(1);
21845 if (ShAmt0.getValueType() != MVT::i8)
21847 SDValue ShAmt1 = N1.getOperand(1);
21848 if (ShAmt1.getValueType() != MVT::i8)
21850 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21851 ShAmt0 = ShAmt0.getOperand(0);
21852 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21853 ShAmt1 = ShAmt1.getOperand(0);
21856 unsigned Opc = X86ISD::SHLD;
21857 SDValue Op0 = N0.getOperand(0);
21858 SDValue Op1 = N1.getOperand(0);
21859 if (ShAmt0.getOpcode() == ISD::SUB) {
21860 Opc = X86ISD::SHRD;
21861 std::swap(Op0, Op1);
21862 std::swap(ShAmt0, ShAmt1);
21865 unsigned Bits = VT.getSizeInBits();
21866 if (ShAmt1.getOpcode() == ISD::SUB) {
21867 SDValue Sum = ShAmt1.getOperand(0);
21868 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21869 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21870 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21871 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21872 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21873 return DAG.getNode(Opc, DL, VT,
21875 DAG.getNode(ISD::TRUNCATE, DL,
21878 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21879 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21881 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21882 return DAG.getNode(Opc, DL, VT,
21883 N0.getOperand(0), N1.getOperand(0),
21884 DAG.getNode(ISD::TRUNCATE, DL,
21891 // Generate NEG and CMOV for integer abs.
21892 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21893 EVT VT = N->getValueType(0);
21895 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21896 // 8-bit integer abs to NEG and CMOV.
21897 if (VT.isInteger() && VT.getSizeInBits() == 8)
21900 SDValue N0 = N->getOperand(0);
21901 SDValue N1 = N->getOperand(1);
21904 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21905 // and change it to SUB and CMOV.
21906 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21907 N0.getOpcode() == ISD::ADD &&
21908 N0.getOperand(1) == N1 &&
21909 N1.getOpcode() == ISD::SRA &&
21910 N1.getOperand(0) == N0.getOperand(0))
21911 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21912 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21913 // Generate SUB & CMOV.
21914 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21915 DAG.getConstant(0, VT), N0.getOperand(0));
21917 SDValue Ops[] = { N0.getOperand(0), Neg,
21918 DAG.getConstant(X86::COND_GE, MVT::i8),
21919 SDValue(Neg.getNode(), 1) };
21920 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21925 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21926 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21927 TargetLowering::DAGCombinerInfo &DCI,
21928 const X86Subtarget *Subtarget) {
21929 if (DCI.isBeforeLegalizeOps())
21932 if (Subtarget->hasCMov()) {
21933 SDValue RV = performIntegerAbsCombine(N, DAG);
21941 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21942 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21943 TargetLowering::DAGCombinerInfo &DCI,
21944 const X86Subtarget *Subtarget) {
21945 LoadSDNode *Ld = cast<LoadSDNode>(N);
21946 EVT RegVT = Ld->getValueType(0);
21947 EVT MemVT = Ld->getMemoryVT();
21949 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21951 // On Sandybridge unaligned 256bit loads are inefficient.
21952 ISD::LoadExtType Ext = Ld->getExtensionType();
21953 unsigned Alignment = Ld->getAlignment();
21954 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21955 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
21956 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21957 unsigned NumElems = RegVT.getVectorNumElements();
21961 SDValue Ptr = Ld->getBasePtr();
21962 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21964 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
21966 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21967 Ld->getPointerInfo(), Ld->isVolatile(),
21968 Ld->isNonTemporal(), Ld->isInvariant(),
21970 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21971 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21972 Ld->getPointerInfo(), Ld->isVolatile(),
21973 Ld->isNonTemporal(), Ld->isInvariant(),
21974 std::min(16U, Alignment));
21975 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21977 Load2.getValue(1));
21979 SDValue NewVec = DAG.getUNDEF(RegVT);
21980 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
21981 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
21982 return DCI.CombineTo(N, NewVec, TF, true);
21988 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21989 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21990 const X86Subtarget *Subtarget) {
21991 StoreSDNode *St = cast<StoreSDNode>(N);
21992 EVT VT = St->getValue().getValueType();
21993 EVT StVT = St->getMemoryVT();
21995 SDValue StoredVal = St->getOperand(1);
21996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21998 // If we are saving a concatenation of two XMM registers, perform two stores.
21999 // On Sandy Bridge, 256-bit memory operations are executed by two
22000 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22001 // memory operation.
22002 unsigned Alignment = St->getAlignment();
22003 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22004 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22005 StVT == VT && !IsAligned) {
22006 unsigned NumElems = VT.getVectorNumElements();
22010 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22011 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22013 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22014 SDValue Ptr0 = St->getBasePtr();
22015 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22017 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22018 St->getPointerInfo(), St->isVolatile(),
22019 St->isNonTemporal(), Alignment);
22020 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22021 St->getPointerInfo(), St->isVolatile(),
22022 St->isNonTemporal(),
22023 std::min(16U, Alignment));
22024 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22027 // Optimize trunc store (of multiple scalars) to shuffle and store.
22028 // First, pack all of the elements in one place. Next, store to memory
22029 // in fewer chunks.
22030 if (St->isTruncatingStore() && VT.isVector()) {
22031 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22032 unsigned NumElems = VT.getVectorNumElements();
22033 assert(StVT != VT && "Cannot truncate to the same type");
22034 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22035 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22037 // From, To sizes and ElemCount must be pow of two
22038 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22039 // We are going to use the original vector elt for storing.
22040 // Accumulated smaller vector elements must be a multiple of the store size.
22041 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22043 unsigned SizeRatio = FromSz / ToSz;
22045 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22047 // Create a type on which we perform the shuffle
22048 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22049 StVT.getScalarType(), NumElems*SizeRatio);
22051 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22053 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22054 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22055 for (unsigned i = 0; i != NumElems; ++i)
22056 ShuffleVec[i] = i * SizeRatio;
22058 // Can't shuffle using an illegal type.
22059 if (!TLI.isTypeLegal(WideVecVT))
22062 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22063 DAG.getUNDEF(WideVecVT),
22065 // At this point all of the data is stored at the bottom of the
22066 // register. We now need to save it to mem.
22068 // Find the largest store unit
22069 MVT StoreType = MVT::i8;
22070 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22071 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22072 MVT Tp = (MVT::SimpleValueType)tp;
22073 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22077 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22078 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22079 (64 <= NumElems * ToSz))
22080 StoreType = MVT::f64;
22082 // Bitcast the original vector into a vector of store-size units
22083 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22084 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22085 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22086 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22087 SmallVector<SDValue, 8> Chains;
22088 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22089 TLI.getPointerTy());
22090 SDValue Ptr = St->getBasePtr();
22092 // Perform one or more big stores into memory.
22093 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22094 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22095 StoreType, ShuffWide,
22096 DAG.getIntPtrConstant(i));
22097 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22098 St->getPointerInfo(), St->isVolatile(),
22099 St->isNonTemporal(), St->getAlignment());
22100 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22101 Chains.push_back(Ch);
22104 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22107 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22108 // the FP state in cases where an emms may be missing.
22109 // A preferable solution to the general problem is to figure out the right
22110 // places to insert EMMS. This qualifies as a quick hack.
22112 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22113 if (VT.getSizeInBits() != 64)
22116 const Function *F = DAG.getMachineFunction().getFunction();
22117 bool NoImplicitFloatOps = F->getAttributes().
22118 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22119 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22120 && Subtarget->hasSSE2();
22121 if ((VT.isVector() ||
22122 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22123 isa<LoadSDNode>(St->getValue()) &&
22124 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22125 St->getChain().hasOneUse() && !St->isVolatile()) {
22126 SDNode* LdVal = St->getValue().getNode();
22127 LoadSDNode *Ld = nullptr;
22128 int TokenFactorIndex = -1;
22129 SmallVector<SDValue, 8> Ops;
22130 SDNode* ChainVal = St->getChain().getNode();
22131 // Must be a store of a load. We currently handle two cases: the load
22132 // is a direct child, and it's under an intervening TokenFactor. It is
22133 // possible to dig deeper under nested TokenFactors.
22134 if (ChainVal == LdVal)
22135 Ld = cast<LoadSDNode>(St->getChain());
22136 else if (St->getValue().hasOneUse() &&
22137 ChainVal->getOpcode() == ISD::TokenFactor) {
22138 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22139 if (ChainVal->getOperand(i).getNode() == LdVal) {
22140 TokenFactorIndex = i;
22141 Ld = cast<LoadSDNode>(St->getValue());
22143 Ops.push_back(ChainVal->getOperand(i));
22147 if (!Ld || !ISD::isNormalLoad(Ld))
22150 // If this is not the MMX case, i.e. we are just turning i64 load/store
22151 // into f64 load/store, avoid the transformation if there are multiple
22152 // uses of the loaded value.
22153 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22158 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22159 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22161 if (Subtarget->is64Bit() || F64IsLegal) {
22162 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22163 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22164 Ld->getPointerInfo(), Ld->isVolatile(),
22165 Ld->isNonTemporal(), Ld->isInvariant(),
22166 Ld->getAlignment());
22167 SDValue NewChain = NewLd.getValue(1);
22168 if (TokenFactorIndex != -1) {
22169 Ops.push_back(NewChain);
22170 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22172 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22173 St->getPointerInfo(),
22174 St->isVolatile(), St->isNonTemporal(),
22175 St->getAlignment());
22178 // Otherwise, lower to two pairs of 32-bit loads / stores.
22179 SDValue LoAddr = Ld->getBasePtr();
22180 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22181 DAG.getConstant(4, MVT::i32));
22183 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22184 Ld->getPointerInfo(),
22185 Ld->isVolatile(), Ld->isNonTemporal(),
22186 Ld->isInvariant(), Ld->getAlignment());
22187 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22188 Ld->getPointerInfo().getWithOffset(4),
22189 Ld->isVolatile(), Ld->isNonTemporal(),
22191 MinAlign(Ld->getAlignment(), 4));
22193 SDValue NewChain = LoLd.getValue(1);
22194 if (TokenFactorIndex != -1) {
22195 Ops.push_back(LoLd);
22196 Ops.push_back(HiLd);
22197 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22200 LoAddr = St->getBasePtr();
22201 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22202 DAG.getConstant(4, MVT::i32));
22204 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22205 St->getPointerInfo(),
22206 St->isVolatile(), St->isNonTemporal(),
22207 St->getAlignment());
22208 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22209 St->getPointerInfo().getWithOffset(4),
22211 St->isNonTemporal(),
22212 MinAlign(St->getAlignment(), 4));
22213 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22218 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22219 /// and return the operands for the horizontal operation in LHS and RHS. A
22220 /// horizontal operation performs the binary operation on successive elements
22221 /// of its first operand, then on successive elements of its second operand,
22222 /// returning the resulting values in a vector. For example, if
22223 /// A = < float a0, float a1, float a2, float a3 >
22225 /// B = < float b0, float b1, float b2, float b3 >
22226 /// then the result of doing a horizontal operation on A and B is
22227 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22228 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22229 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22230 /// set to A, RHS to B, and the routine returns 'true'.
22231 /// Note that the binary operation should have the property that if one of the
22232 /// operands is UNDEF then the result is UNDEF.
22233 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22234 // Look for the following pattern: if
22235 // A = < float a0, float a1, float a2, float a3 >
22236 // B = < float b0, float b1, float b2, float b3 >
22238 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22239 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22240 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22241 // which is A horizontal-op B.
22243 // At least one of the operands should be a vector shuffle.
22244 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22245 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22248 MVT VT = LHS.getSimpleValueType();
22250 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22251 "Unsupported vector type for horizontal add/sub");
22253 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22254 // operate independently on 128-bit lanes.
22255 unsigned NumElts = VT.getVectorNumElements();
22256 unsigned NumLanes = VT.getSizeInBits()/128;
22257 unsigned NumLaneElts = NumElts / NumLanes;
22258 assert((NumLaneElts % 2 == 0) &&
22259 "Vector type should have an even number of elements in each lane");
22260 unsigned HalfLaneElts = NumLaneElts/2;
22262 // View LHS in the form
22263 // LHS = VECTOR_SHUFFLE A, B, LMask
22264 // If LHS is not a shuffle then pretend it is the shuffle
22265 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22266 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22269 SmallVector<int, 16> LMask(NumElts);
22270 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22271 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22272 A = LHS.getOperand(0);
22273 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22274 B = LHS.getOperand(1);
22275 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22276 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22278 if (LHS.getOpcode() != ISD::UNDEF)
22280 for (unsigned i = 0; i != NumElts; ++i)
22284 // Likewise, view RHS in the form
22285 // RHS = VECTOR_SHUFFLE C, D, RMask
22287 SmallVector<int, 16> RMask(NumElts);
22288 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22289 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22290 C = RHS.getOperand(0);
22291 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22292 D = RHS.getOperand(1);
22293 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22294 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22296 if (RHS.getOpcode() != ISD::UNDEF)
22298 for (unsigned i = 0; i != NumElts; ++i)
22302 // Check that the shuffles are both shuffling the same vectors.
22303 if (!(A == C && B == D) && !(A == D && B == C))
22306 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22307 if (!A.getNode() && !B.getNode())
22310 // If A and B occur in reverse order in RHS, then "swap" them (which means
22311 // rewriting the mask).
22313 CommuteVectorShuffleMask(RMask, NumElts);
22315 // At this point LHS and RHS are equivalent to
22316 // LHS = VECTOR_SHUFFLE A, B, LMask
22317 // RHS = VECTOR_SHUFFLE A, B, RMask
22318 // Check that the masks correspond to performing a horizontal operation.
22319 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22320 for (unsigned i = 0; i != NumLaneElts; ++i) {
22321 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22323 // Ignore any UNDEF components.
22324 if (LIdx < 0 || RIdx < 0 ||
22325 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22326 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22329 // Check that successive elements are being operated on. If not, this is
22330 // not a horizontal operation.
22331 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22332 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22333 if (!(LIdx == Index && RIdx == Index + 1) &&
22334 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22339 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22340 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22344 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22345 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22346 const X86Subtarget *Subtarget) {
22347 EVT VT = N->getValueType(0);
22348 SDValue LHS = N->getOperand(0);
22349 SDValue RHS = N->getOperand(1);
22351 // Try to synthesize horizontal adds from adds of shuffles.
22352 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22353 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22354 isHorizontalBinOp(LHS, RHS, true))
22355 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22359 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22360 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22361 const X86Subtarget *Subtarget) {
22362 EVT VT = N->getValueType(0);
22363 SDValue LHS = N->getOperand(0);
22364 SDValue RHS = N->getOperand(1);
22366 // Try to synthesize horizontal subs from subs of shuffles.
22367 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22368 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22369 isHorizontalBinOp(LHS, RHS, false))
22370 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22374 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22375 /// X86ISD::FXOR nodes.
22376 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22377 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22378 // F[X]OR(0.0, x) -> x
22379 // F[X]OR(x, 0.0) -> x
22380 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22381 if (C->getValueAPF().isPosZero())
22382 return N->getOperand(1);
22383 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22384 if (C->getValueAPF().isPosZero())
22385 return N->getOperand(0);
22389 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22390 /// X86ISD::FMAX nodes.
22391 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22392 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22394 // Only perform optimizations if UnsafeMath is used.
22395 if (!DAG.getTarget().Options.UnsafeFPMath)
22398 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22399 // into FMINC and FMAXC, which are Commutative operations.
22400 unsigned NewOp = 0;
22401 switch (N->getOpcode()) {
22402 default: llvm_unreachable("unknown opcode");
22403 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22404 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22407 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22408 N->getOperand(0), N->getOperand(1));
22411 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22412 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22413 // FAND(0.0, x) -> 0.0
22414 // FAND(x, 0.0) -> 0.0
22415 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22416 if (C->getValueAPF().isPosZero())
22417 return N->getOperand(0);
22418 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22419 if (C->getValueAPF().isPosZero())
22420 return N->getOperand(1);
22424 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22425 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22426 // FANDN(x, 0.0) -> 0.0
22427 // FANDN(0.0, x) -> x
22428 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22429 if (C->getValueAPF().isPosZero())
22430 return N->getOperand(1);
22431 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22432 if (C->getValueAPF().isPosZero())
22433 return N->getOperand(1);
22437 static SDValue PerformBTCombine(SDNode *N,
22439 TargetLowering::DAGCombinerInfo &DCI) {
22440 // BT ignores high bits in the bit index operand.
22441 SDValue Op1 = N->getOperand(1);
22442 if (Op1.hasOneUse()) {
22443 unsigned BitWidth = Op1.getValueSizeInBits();
22444 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22445 APInt KnownZero, KnownOne;
22446 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22447 !DCI.isBeforeLegalizeOps());
22448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22449 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22450 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22451 DCI.CommitTargetLoweringOpt(TLO);
22456 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22457 SDValue Op = N->getOperand(0);
22458 if (Op.getOpcode() == ISD::BITCAST)
22459 Op = Op.getOperand(0);
22460 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22461 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22462 VT.getVectorElementType().getSizeInBits() ==
22463 OpVT.getVectorElementType().getSizeInBits()) {
22464 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22469 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22470 const X86Subtarget *Subtarget) {
22471 EVT VT = N->getValueType(0);
22472 if (!VT.isVector())
22475 SDValue N0 = N->getOperand(0);
22476 SDValue N1 = N->getOperand(1);
22477 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22480 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22481 // both SSE and AVX2 since there is no sign-extended shift right
22482 // operation on a vector with 64-bit elements.
22483 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22484 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22485 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22486 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22487 SDValue N00 = N0.getOperand(0);
22489 // EXTLOAD has a better solution on AVX2,
22490 // it may be replaced with X86ISD::VSEXT node.
22491 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22492 if (!ISD::isNormalLoad(N00.getNode()))
22495 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22496 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22498 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22504 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22505 TargetLowering::DAGCombinerInfo &DCI,
22506 const X86Subtarget *Subtarget) {
22507 if (!DCI.isBeforeLegalizeOps())
22510 if (!Subtarget->hasFp256())
22513 EVT VT = N->getValueType(0);
22514 if (VT.isVector() && VT.getSizeInBits() == 256) {
22515 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22523 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22524 const X86Subtarget* Subtarget) {
22526 EVT VT = N->getValueType(0);
22528 // Let legalize expand this if it isn't a legal type yet.
22529 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22532 EVT ScalarVT = VT.getScalarType();
22533 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22534 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22537 SDValue A = N->getOperand(0);
22538 SDValue B = N->getOperand(1);
22539 SDValue C = N->getOperand(2);
22541 bool NegA = (A.getOpcode() == ISD::FNEG);
22542 bool NegB = (B.getOpcode() == ISD::FNEG);
22543 bool NegC = (C.getOpcode() == ISD::FNEG);
22545 // Negative multiplication when NegA xor NegB
22546 bool NegMul = (NegA != NegB);
22548 A = A.getOperand(0);
22550 B = B.getOperand(0);
22552 C = C.getOperand(0);
22556 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22558 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22560 return DAG.getNode(Opcode, dl, VT, A, B, C);
22563 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22564 TargetLowering::DAGCombinerInfo &DCI,
22565 const X86Subtarget *Subtarget) {
22566 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22567 // (and (i32 x86isd::setcc_carry), 1)
22568 // This eliminates the zext. This transformation is necessary because
22569 // ISD::SETCC is always legalized to i8.
22571 SDValue N0 = N->getOperand(0);
22572 EVT VT = N->getValueType(0);
22574 if (N0.getOpcode() == ISD::AND &&
22576 N0.getOperand(0).hasOneUse()) {
22577 SDValue N00 = N0.getOperand(0);
22578 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22579 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22580 if (!C || C->getZExtValue() != 1)
22582 return DAG.getNode(ISD::AND, dl, VT,
22583 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22584 N00.getOperand(0), N00.getOperand(1)),
22585 DAG.getConstant(1, VT));
22589 if (N0.getOpcode() == ISD::TRUNCATE &&
22591 N0.getOperand(0).hasOneUse()) {
22592 SDValue N00 = N0.getOperand(0);
22593 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22594 return DAG.getNode(ISD::AND, dl, VT,
22595 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22596 N00.getOperand(0), N00.getOperand(1)),
22597 DAG.getConstant(1, VT));
22600 if (VT.is256BitVector()) {
22601 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22609 // Optimize x == -y --> x+y == 0
22610 // x != -y --> x+y != 0
22611 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22612 const X86Subtarget* Subtarget) {
22613 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22614 SDValue LHS = N->getOperand(0);
22615 SDValue RHS = N->getOperand(1);
22616 EVT VT = N->getValueType(0);
22619 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22621 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22622 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22623 LHS.getValueType(), RHS, LHS.getOperand(1));
22624 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22625 addV, DAG.getConstant(0, addV.getValueType()), CC);
22627 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22628 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22629 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22630 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22631 RHS.getValueType(), LHS, RHS.getOperand(1));
22632 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22633 addV, DAG.getConstant(0, addV.getValueType()), CC);
22636 if (VT.getScalarType() == MVT::i1) {
22637 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22638 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22639 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22640 if (!IsSEXT0 && !IsVZero0)
22642 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22643 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22644 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22646 if (!IsSEXT1 && !IsVZero1)
22649 if (IsSEXT0 && IsVZero1) {
22650 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22651 if (CC == ISD::SETEQ)
22652 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22653 return LHS.getOperand(0);
22655 if (IsSEXT1 && IsVZero0) {
22656 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22657 if (CC == ISD::SETEQ)
22658 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22659 return RHS.getOperand(0);
22666 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22667 const X86Subtarget *Subtarget) {
22669 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22670 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22671 "X86insertps is only defined for v4x32");
22673 SDValue Ld = N->getOperand(1);
22674 if (MayFoldLoad(Ld)) {
22675 // Extract the countS bits from the immediate so we can get the proper
22676 // address when narrowing the vector load to a specific element.
22677 // When the second source op is a memory address, interps doesn't use
22678 // countS and just gets an f32 from that address.
22679 unsigned DestIndex =
22680 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22681 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22685 // Create this as a scalar to vector to match the instruction pattern.
22686 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22687 // countS bits are ignored when loading from memory on insertps, which
22688 // means we don't need to explicitly set them to 0.
22689 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22690 LoadScalarToVector, N->getOperand(2));
22693 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22694 // as "sbb reg,reg", since it can be extended without zext and produces
22695 // an all-ones bit which is more useful than 0/1 in some cases.
22696 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22699 return DAG.getNode(ISD::AND, DL, VT,
22700 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22701 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22702 DAG.getConstant(1, VT));
22703 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22704 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22705 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22706 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22709 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22710 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22711 TargetLowering::DAGCombinerInfo &DCI,
22712 const X86Subtarget *Subtarget) {
22714 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22715 SDValue EFLAGS = N->getOperand(1);
22717 if (CC == X86::COND_A) {
22718 // Try to convert COND_A into COND_B in an attempt to facilitate
22719 // materializing "setb reg".
22721 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22722 // cannot take an immediate as its first operand.
22724 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22725 EFLAGS.getValueType().isInteger() &&
22726 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22727 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22728 EFLAGS.getNode()->getVTList(),
22729 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22730 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22731 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22735 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22736 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22738 if (CC == X86::COND_B)
22739 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22743 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22744 if (Flags.getNode()) {
22745 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22746 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22752 // Optimize branch condition evaluation.
22754 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22755 TargetLowering::DAGCombinerInfo &DCI,
22756 const X86Subtarget *Subtarget) {
22758 SDValue Chain = N->getOperand(0);
22759 SDValue Dest = N->getOperand(1);
22760 SDValue EFLAGS = N->getOperand(3);
22761 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22765 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22766 if (Flags.getNode()) {
22767 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22768 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22775 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22776 SelectionDAG &DAG) {
22777 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22778 // optimize away operation when it's from a constant.
22780 // The general transformation is:
22781 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22782 // AND(VECTOR_CMP(x,y), constant2)
22783 // constant2 = UNARYOP(constant)
22785 // Early exit if this isn't a vector operation, the operand of the
22786 // unary operation isn't a bitwise AND, or if the sizes of the operations
22787 // aren't the same.
22788 EVT VT = N->getValueType(0);
22789 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22790 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22791 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22794 // Now check that the other operand of the AND is a constant. We could
22795 // make the transformation for non-constant splats as well, but it's unclear
22796 // that would be a benefit as it would not eliminate any operations, just
22797 // perform one more step in scalar code before moving to the vector unit.
22798 if (BuildVectorSDNode *BV =
22799 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22800 // Bail out if the vector isn't a constant.
22801 if (!BV->isConstant())
22804 // Everything checks out. Build up the new and improved node.
22806 EVT IntVT = BV->getValueType(0);
22807 // Create a new constant of the appropriate type for the transformed
22809 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22810 // The AND node needs bitcasts to/from an integer vector type around it.
22811 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22812 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22813 N->getOperand(0)->getOperand(0), MaskConst);
22814 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22821 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22822 const X86TargetLowering *XTLI) {
22823 // First try to optimize away the conversion entirely when it's
22824 // conditionally from a constant. Vectors only.
22825 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22826 if (Res != SDValue())
22829 // Now move on to more general possibilities.
22830 SDValue Op0 = N->getOperand(0);
22831 EVT InVT = Op0->getValueType(0);
22833 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22834 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22836 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22837 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22838 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22841 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22842 // a 32-bit target where SSE doesn't support i64->FP operations.
22843 if (Op0.getOpcode() == ISD::LOAD) {
22844 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22845 EVT VT = Ld->getValueType(0);
22846 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22847 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22848 !XTLI->getSubtarget()->is64Bit() &&
22850 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22851 Ld->getChain(), Op0, DAG);
22852 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22859 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22860 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22861 X86TargetLowering::DAGCombinerInfo &DCI) {
22862 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22863 // the result is either zero or one (depending on the input carry bit).
22864 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22865 if (X86::isZeroNode(N->getOperand(0)) &&
22866 X86::isZeroNode(N->getOperand(1)) &&
22867 // We don't have a good way to replace an EFLAGS use, so only do this when
22869 SDValue(N, 1).use_empty()) {
22871 EVT VT = N->getValueType(0);
22872 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22873 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22874 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22875 DAG.getConstant(X86::COND_B,MVT::i8),
22877 DAG.getConstant(1, VT));
22878 return DCI.CombineTo(N, Res1, CarryOut);
22884 // fold (add Y, (sete X, 0)) -> adc 0, Y
22885 // (add Y, (setne X, 0)) -> sbb -1, Y
22886 // (sub (sete X, 0), Y) -> sbb 0, Y
22887 // (sub (setne X, 0), Y) -> adc -1, Y
22888 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22891 // Look through ZExts.
22892 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22893 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22896 SDValue SetCC = Ext.getOperand(0);
22897 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22900 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22901 if (CC != X86::COND_E && CC != X86::COND_NE)
22904 SDValue Cmp = SetCC.getOperand(1);
22905 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22906 !X86::isZeroNode(Cmp.getOperand(1)) ||
22907 !Cmp.getOperand(0).getValueType().isInteger())
22910 SDValue CmpOp0 = Cmp.getOperand(0);
22911 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22912 DAG.getConstant(1, CmpOp0.getValueType()));
22914 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22915 if (CC == X86::COND_NE)
22916 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
22917 DL, OtherVal.getValueType(), OtherVal,
22918 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
22919 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
22920 DL, OtherVal.getValueType(), OtherVal,
22921 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
22924 /// PerformADDCombine - Do target-specific dag combines on integer adds.
22925 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
22926 const X86Subtarget *Subtarget) {
22927 EVT VT = N->getValueType(0);
22928 SDValue Op0 = N->getOperand(0);
22929 SDValue Op1 = N->getOperand(1);
22931 // Try to synthesize horizontal adds from adds of shuffles.
22932 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22933 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22934 isHorizontalBinOp(Op0, Op1, true))
22935 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
22937 return OptimizeConditionalInDecrement(N, DAG);
22940 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
22941 const X86Subtarget *Subtarget) {
22942 SDValue Op0 = N->getOperand(0);
22943 SDValue Op1 = N->getOperand(1);
22945 // X86 can't encode an immediate LHS of a sub. See if we can push the
22946 // negation into a preceding instruction.
22947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
22948 // If the RHS of the sub is a XOR with one use and a constant, invert the
22949 // immediate. Then add one to the LHS of the sub so we can turn
22950 // X-Y -> X+~Y+1, saving one register.
22951 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
22952 isa<ConstantSDNode>(Op1.getOperand(1))) {
22953 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
22954 EVT VT = Op0.getValueType();
22955 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
22957 DAG.getConstant(~XorC, VT));
22958 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
22959 DAG.getConstant(C->getAPIntValue()+1, VT));
22963 // Try to synthesize horizontal adds from adds of shuffles.
22964 EVT VT = N->getValueType(0);
22965 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22966 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22967 isHorizontalBinOp(Op0, Op1, true))
22968 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
22970 return OptimizeConditionalInDecrement(N, DAG);
22973 /// performVZEXTCombine - Performs build vector combines
22974 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
22975 TargetLowering::DAGCombinerInfo &DCI,
22976 const X86Subtarget *Subtarget) {
22977 // (vzext (bitcast (vzext (x)) -> (vzext x)
22978 SDValue In = N->getOperand(0);
22979 while (In.getOpcode() == ISD::BITCAST)
22980 In = In.getOperand(0);
22982 if (In.getOpcode() != X86ISD::VZEXT)
22985 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
22989 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22990 DAGCombinerInfo &DCI) const {
22991 SelectionDAG &DAG = DCI.DAG;
22992 switch (N->getOpcode()) {
22994 case ISD::EXTRACT_VECTOR_ELT:
22995 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22997 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22998 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22999 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23000 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23001 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23002 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23005 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23006 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23007 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23008 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23009 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23010 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23011 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23012 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23013 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23015 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23017 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23018 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23019 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23020 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23021 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23022 case ISD::ANY_EXTEND:
23023 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23024 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23025 case ISD::SIGN_EXTEND_INREG:
23026 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23027 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23028 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23029 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23030 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23031 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23032 case X86ISD::SHUFP: // Handle all target specific shuffles
23033 case X86ISD::PALIGNR:
23034 case X86ISD::UNPCKH:
23035 case X86ISD::UNPCKL:
23036 case X86ISD::MOVHLPS:
23037 case X86ISD::MOVLHPS:
23038 case X86ISD::PSHUFB:
23039 case X86ISD::PSHUFD:
23040 case X86ISD::PSHUFHW:
23041 case X86ISD::PSHUFLW:
23042 case X86ISD::MOVSS:
23043 case X86ISD::MOVSD:
23044 case X86ISD::VPERMILP:
23045 case X86ISD::VPERM2X128:
23046 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23047 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23048 case ISD::INTRINSIC_WO_CHAIN:
23049 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23050 case X86ISD::INSERTPS:
23051 return PerformINSERTPSCombine(N, DAG, Subtarget);
23052 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23058 /// isTypeDesirableForOp - Return true if the target has native support for
23059 /// the specified value type and it is 'desirable' to use the type for the
23060 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23061 /// instruction encodings are longer and some i16 instructions are slow.
23062 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23063 if (!isTypeLegal(VT))
23065 if (VT != MVT::i16)
23072 case ISD::SIGN_EXTEND:
23073 case ISD::ZERO_EXTEND:
23074 case ISD::ANY_EXTEND:
23087 /// IsDesirableToPromoteOp - This method query the target whether it is
23088 /// beneficial for dag combiner to promote the specified node. If true, it
23089 /// should return the desired promotion type by reference.
23090 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23091 EVT VT = Op.getValueType();
23092 if (VT != MVT::i16)
23095 bool Promote = false;
23096 bool Commute = false;
23097 switch (Op.getOpcode()) {
23100 LoadSDNode *LD = cast<LoadSDNode>(Op);
23101 // If the non-extending load has a single use and it's not live out, then it
23102 // might be folded.
23103 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23104 Op.hasOneUse()*/) {
23105 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23106 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23107 // The only case where we'd want to promote LOAD (rather then it being
23108 // promoted as an operand is when it's only use is liveout.
23109 if (UI->getOpcode() != ISD::CopyToReg)
23116 case ISD::SIGN_EXTEND:
23117 case ISD::ZERO_EXTEND:
23118 case ISD::ANY_EXTEND:
23123 SDValue N0 = Op.getOperand(0);
23124 // Look out for (store (shl (load), x)).
23125 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23138 SDValue N0 = Op.getOperand(0);
23139 SDValue N1 = Op.getOperand(1);
23140 if (!Commute && MayFoldLoad(N1))
23142 // Avoid disabling potential load folding opportunities.
23143 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23145 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23155 //===----------------------------------------------------------------------===//
23156 // X86 Inline Assembly Support
23157 //===----------------------------------------------------------------------===//
23160 // Helper to match a string separated by whitespace.
23161 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23162 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23164 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23165 StringRef piece(*args[i]);
23166 if (!s.startswith(piece)) // Check if the piece matches.
23169 s = s.substr(piece.size());
23170 StringRef::size_type pos = s.find_first_not_of(" \t");
23171 if (pos == 0) // We matched a prefix.
23179 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23182 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23184 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23185 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23186 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23187 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23189 if (AsmPieces.size() == 3)
23191 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23198 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23199 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23201 std::string AsmStr = IA->getAsmString();
23203 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23204 if (!Ty || Ty->getBitWidth() % 16 != 0)
23207 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23208 SmallVector<StringRef, 4> AsmPieces;
23209 SplitString(AsmStr, AsmPieces, ";\n");
23211 switch (AsmPieces.size()) {
23212 default: return false;
23214 // FIXME: this should verify that we are targeting a 486 or better. If not,
23215 // we will turn this bswap into something that will be lowered to logical
23216 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23217 // lower so don't worry about this.
23219 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23220 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23221 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23222 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23223 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23224 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23225 // No need to check constraints, nothing other than the equivalent of
23226 // "=r,0" would be valid here.
23227 return IntrinsicLowering::LowerToByteSwap(CI);
23230 // rorw $$8, ${0:w} --> llvm.bswap.i16
23231 if (CI->getType()->isIntegerTy(16) &&
23232 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23233 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23234 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23236 const std::string &ConstraintsStr = IA->getConstraintString();
23237 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23238 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23239 if (clobbersFlagRegisters(AsmPieces))
23240 return IntrinsicLowering::LowerToByteSwap(CI);
23244 if (CI->getType()->isIntegerTy(32) &&
23245 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23246 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23247 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23248 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23250 const std::string &ConstraintsStr = IA->getConstraintString();
23251 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23252 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23253 if (clobbersFlagRegisters(AsmPieces))
23254 return IntrinsicLowering::LowerToByteSwap(CI);
23257 if (CI->getType()->isIntegerTy(64)) {
23258 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23259 if (Constraints.size() >= 2 &&
23260 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23261 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23262 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23263 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23264 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23265 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23266 return IntrinsicLowering::LowerToByteSwap(CI);
23274 /// getConstraintType - Given a constraint letter, return the type of
23275 /// constraint it is for this target.
23276 X86TargetLowering::ConstraintType
23277 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23278 if (Constraint.size() == 1) {
23279 switch (Constraint[0]) {
23290 return C_RegisterClass;
23314 return TargetLowering::getConstraintType(Constraint);
23317 /// Examine constraint type and operand type and determine a weight value.
23318 /// This object must already have been set up with the operand type
23319 /// and the current alternative constraint selected.
23320 TargetLowering::ConstraintWeight
23321 X86TargetLowering::getSingleConstraintMatchWeight(
23322 AsmOperandInfo &info, const char *constraint) const {
23323 ConstraintWeight weight = CW_Invalid;
23324 Value *CallOperandVal = info.CallOperandVal;
23325 // If we don't have a value, we can't do a match,
23326 // but allow it at the lowest weight.
23327 if (!CallOperandVal)
23329 Type *type = CallOperandVal->getType();
23330 // Look at the constraint type.
23331 switch (*constraint) {
23333 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23344 if (CallOperandVal->getType()->isIntegerTy())
23345 weight = CW_SpecificReg;
23350 if (type->isFloatingPointTy())
23351 weight = CW_SpecificReg;
23354 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23355 weight = CW_SpecificReg;
23359 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23360 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23361 weight = CW_Register;
23364 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23365 if (C->getZExtValue() <= 31)
23366 weight = CW_Constant;
23370 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23371 if (C->getZExtValue() <= 63)
23372 weight = CW_Constant;
23376 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23377 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23378 weight = CW_Constant;
23382 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23383 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23384 weight = CW_Constant;
23388 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23389 if (C->getZExtValue() <= 3)
23390 weight = CW_Constant;
23394 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23395 if (C->getZExtValue() <= 0xff)
23396 weight = CW_Constant;
23401 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23402 weight = CW_Constant;
23406 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23407 if ((C->getSExtValue() >= -0x80000000LL) &&
23408 (C->getSExtValue() <= 0x7fffffffLL))
23409 weight = CW_Constant;
23413 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23414 if (C->getZExtValue() <= 0xffffffff)
23415 weight = CW_Constant;
23422 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23423 /// with another that has more specific requirements based on the type of the
23424 /// corresponding operand.
23425 const char *X86TargetLowering::
23426 LowerXConstraint(EVT ConstraintVT) const {
23427 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23428 // 'f' like normal targets.
23429 if (ConstraintVT.isFloatingPoint()) {
23430 if (Subtarget->hasSSE2())
23432 if (Subtarget->hasSSE1())
23436 return TargetLowering::LowerXConstraint(ConstraintVT);
23439 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23440 /// vector. If it is invalid, don't add anything to Ops.
23441 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23442 std::string &Constraint,
23443 std::vector<SDValue>&Ops,
23444 SelectionDAG &DAG) const {
23447 // Only support length 1 constraints for now.
23448 if (Constraint.length() > 1) return;
23450 char ConstraintLetter = Constraint[0];
23451 switch (ConstraintLetter) {
23454 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23455 if (C->getZExtValue() <= 31) {
23456 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23463 if (C->getZExtValue() <= 63) {
23464 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23471 if (isInt<8>(C->getSExtValue())) {
23472 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23479 if (C->getZExtValue() <= 255) {
23480 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23486 // 32-bit signed value
23487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23488 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23489 C->getSExtValue())) {
23490 // Widen to 64 bits here to get it sign extended.
23491 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23494 // FIXME gcc accepts some relocatable values here too, but only in certain
23495 // memory models; it's complicated.
23500 // 32-bit unsigned value
23501 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23502 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23503 C->getZExtValue())) {
23504 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23508 // FIXME gcc accepts some relocatable values here too, but only in certain
23509 // memory models; it's complicated.
23513 // Literal immediates are always ok.
23514 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23515 // Widen to 64 bits here to get it sign extended.
23516 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23520 // In any sort of PIC mode addresses need to be computed at runtime by
23521 // adding in a register or some sort of table lookup. These can't
23522 // be used as immediates.
23523 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23526 // If we are in non-pic codegen mode, we allow the address of a global (with
23527 // an optional displacement) to be used with 'i'.
23528 GlobalAddressSDNode *GA = nullptr;
23529 int64_t Offset = 0;
23531 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23533 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23534 Offset += GA->getOffset();
23536 } else if (Op.getOpcode() == ISD::ADD) {
23537 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23538 Offset += C->getZExtValue();
23539 Op = Op.getOperand(0);
23542 } else if (Op.getOpcode() == ISD::SUB) {
23543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23544 Offset += -C->getZExtValue();
23545 Op = Op.getOperand(0);
23550 // Otherwise, this isn't something we can handle, reject it.
23554 const GlobalValue *GV = GA->getGlobal();
23555 // If we require an extra load to get this address, as in PIC mode, we
23556 // can't accept it.
23557 if (isGlobalStubReference(
23558 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23561 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23562 GA->getValueType(0), Offset);
23567 if (Result.getNode()) {
23568 Ops.push_back(Result);
23571 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23574 std::pair<unsigned, const TargetRegisterClass*>
23575 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23577 // First, see if this is a constraint that directly corresponds to an LLVM
23579 if (Constraint.size() == 1) {
23580 // GCC Constraint Letters
23581 switch (Constraint[0]) {
23583 // TODO: Slight differences here in allocation order and leaving
23584 // RIP in the class. Do they matter any more here than they do
23585 // in the normal allocation?
23586 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23587 if (Subtarget->is64Bit()) {
23588 if (VT == MVT::i32 || VT == MVT::f32)
23589 return std::make_pair(0U, &X86::GR32RegClass);
23590 if (VT == MVT::i16)
23591 return std::make_pair(0U, &X86::GR16RegClass);
23592 if (VT == MVT::i8 || VT == MVT::i1)
23593 return std::make_pair(0U, &X86::GR8RegClass);
23594 if (VT == MVT::i64 || VT == MVT::f64)
23595 return std::make_pair(0U, &X86::GR64RegClass);
23598 // 32-bit fallthrough
23599 case 'Q': // Q_REGS
23600 if (VT == MVT::i32 || VT == MVT::f32)
23601 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23602 if (VT == MVT::i16)
23603 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23604 if (VT == MVT::i8 || VT == MVT::i1)
23605 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23606 if (VT == MVT::i64)
23607 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23609 case 'r': // GENERAL_REGS
23610 case 'l': // INDEX_REGS
23611 if (VT == MVT::i8 || VT == MVT::i1)
23612 return std::make_pair(0U, &X86::GR8RegClass);
23613 if (VT == MVT::i16)
23614 return std::make_pair(0U, &X86::GR16RegClass);
23615 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23616 return std::make_pair(0U, &X86::GR32RegClass);
23617 return std::make_pair(0U, &X86::GR64RegClass);
23618 case 'R': // LEGACY_REGS
23619 if (VT == MVT::i8 || VT == MVT::i1)
23620 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23621 if (VT == MVT::i16)
23622 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23623 if (VT == MVT::i32 || !Subtarget->is64Bit())
23624 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23625 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23626 case 'f': // FP Stack registers.
23627 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23628 // value to the correct fpstack register class.
23629 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23630 return std::make_pair(0U, &X86::RFP32RegClass);
23631 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23632 return std::make_pair(0U, &X86::RFP64RegClass);
23633 return std::make_pair(0U, &X86::RFP80RegClass);
23634 case 'y': // MMX_REGS if MMX allowed.
23635 if (!Subtarget->hasMMX()) break;
23636 return std::make_pair(0U, &X86::VR64RegClass);
23637 case 'Y': // SSE_REGS if SSE2 allowed
23638 if (!Subtarget->hasSSE2()) break;
23640 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23641 if (!Subtarget->hasSSE1()) break;
23643 switch (VT.SimpleTy) {
23645 // Scalar SSE types.
23648 return std::make_pair(0U, &X86::FR32RegClass);
23651 return std::make_pair(0U, &X86::FR64RegClass);
23659 return std::make_pair(0U, &X86::VR128RegClass);
23667 return std::make_pair(0U, &X86::VR256RegClass);
23672 return std::make_pair(0U, &X86::VR512RegClass);
23678 // Use the default implementation in TargetLowering to convert the register
23679 // constraint into a member of a register class.
23680 std::pair<unsigned, const TargetRegisterClass*> Res;
23681 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23683 // Not found as a standard register?
23685 // Map st(0) -> st(7) -> ST0
23686 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23687 tolower(Constraint[1]) == 's' &&
23688 tolower(Constraint[2]) == 't' &&
23689 Constraint[3] == '(' &&
23690 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23691 Constraint[5] == ')' &&
23692 Constraint[6] == '}') {
23694 Res.first = X86::FP0+Constraint[4]-'0';
23695 Res.second = &X86::RFP80RegClass;
23699 // GCC allows "st(0)" to be called just plain "st".
23700 if (StringRef("{st}").equals_lower(Constraint)) {
23701 Res.first = X86::FP0;
23702 Res.second = &X86::RFP80RegClass;
23707 if (StringRef("{flags}").equals_lower(Constraint)) {
23708 Res.first = X86::EFLAGS;
23709 Res.second = &X86::CCRRegClass;
23713 // 'A' means EAX + EDX.
23714 if (Constraint == "A") {
23715 Res.first = X86::EAX;
23716 Res.second = &X86::GR32_ADRegClass;
23722 // Otherwise, check to see if this is a register class of the wrong value
23723 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23724 // turn into {ax},{dx}.
23725 if (Res.second->hasType(VT))
23726 return Res; // Correct type already, nothing to do.
23728 // All of the single-register GCC register classes map their values onto
23729 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23730 // really want an 8-bit or 32-bit register, map to the appropriate register
23731 // class and return the appropriate register.
23732 if (Res.second == &X86::GR16RegClass) {
23733 if (VT == MVT::i8 || VT == MVT::i1) {
23734 unsigned DestReg = 0;
23735 switch (Res.first) {
23737 case X86::AX: DestReg = X86::AL; break;
23738 case X86::DX: DestReg = X86::DL; break;
23739 case X86::CX: DestReg = X86::CL; break;
23740 case X86::BX: DestReg = X86::BL; break;
23743 Res.first = DestReg;
23744 Res.second = &X86::GR8RegClass;
23746 } else if (VT == MVT::i32 || VT == MVT::f32) {
23747 unsigned DestReg = 0;
23748 switch (Res.first) {
23750 case X86::AX: DestReg = X86::EAX; break;
23751 case X86::DX: DestReg = X86::EDX; break;
23752 case X86::CX: DestReg = X86::ECX; break;
23753 case X86::BX: DestReg = X86::EBX; break;
23754 case X86::SI: DestReg = X86::ESI; break;
23755 case X86::DI: DestReg = X86::EDI; break;
23756 case X86::BP: DestReg = X86::EBP; break;
23757 case X86::SP: DestReg = X86::ESP; break;
23760 Res.first = DestReg;
23761 Res.second = &X86::GR32RegClass;
23763 } else if (VT == MVT::i64 || VT == MVT::f64) {
23764 unsigned DestReg = 0;
23765 switch (Res.first) {
23767 case X86::AX: DestReg = X86::RAX; break;
23768 case X86::DX: DestReg = X86::RDX; break;
23769 case X86::CX: DestReg = X86::RCX; break;
23770 case X86::BX: DestReg = X86::RBX; break;
23771 case X86::SI: DestReg = X86::RSI; break;
23772 case X86::DI: DestReg = X86::RDI; break;
23773 case X86::BP: DestReg = X86::RBP; break;
23774 case X86::SP: DestReg = X86::RSP; break;
23777 Res.first = DestReg;
23778 Res.second = &X86::GR64RegClass;
23781 } else if (Res.second == &X86::FR32RegClass ||
23782 Res.second == &X86::FR64RegClass ||
23783 Res.second == &X86::VR128RegClass ||
23784 Res.second == &X86::VR256RegClass ||
23785 Res.second == &X86::FR32XRegClass ||
23786 Res.second == &X86::FR64XRegClass ||
23787 Res.second == &X86::VR128XRegClass ||
23788 Res.second == &X86::VR256XRegClass ||
23789 Res.second == &X86::VR512RegClass) {
23790 // Handle references to XMM physical registers that got mapped into the
23791 // wrong class. This can happen with constraints like {xmm0} where the
23792 // target independent register mapper will just pick the first match it can
23793 // find, ignoring the required type.
23795 if (VT == MVT::f32 || VT == MVT::i32)
23796 Res.second = &X86::FR32RegClass;
23797 else if (VT == MVT::f64 || VT == MVT::i64)
23798 Res.second = &X86::FR64RegClass;
23799 else if (X86::VR128RegClass.hasType(VT))
23800 Res.second = &X86::VR128RegClass;
23801 else if (X86::VR256RegClass.hasType(VT))
23802 Res.second = &X86::VR256RegClass;
23803 else if (X86::VR512RegClass.hasType(VT))
23804 Res.second = &X86::VR512RegClass;
23810 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23812 // Scaling factors are not free at all.
23813 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23814 // will take 2 allocations in the out of order engine instead of 1
23815 // for plain addressing mode, i.e. inst (reg1).
23817 // vaddps (%rsi,%drx), %ymm0, %ymm1
23818 // Requires two allocations (one for the load, one for the computation)
23820 // vaddps (%rsi), %ymm0, %ymm1
23821 // Requires just 1 allocation, i.e., freeing allocations for other operations
23822 // and having less micro operations to execute.
23824 // For some X86 architectures, this is even worse because for instance for
23825 // stores, the complex addressing mode forces the instruction to use the
23826 // "load" ports instead of the dedicated "store" port.
23827 // E.g., on Haswell:
23828 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23829 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23830 if (isLegalAddressingMode(AM, Ty))
23831 // Scale represents reg2 * scale, thus account for 1
23832 // as soon as we use a second register.
23833 return AM.Scale != 0;
23837 bool X86TargetLowering::isTargetFTOL() const {
23838 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();