1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
62 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
63 SelectionDAG &DAG, SDLoc dl,
64 unsigned vectorWidth) {
65 assert((vectorWidth == 128 || vectorWidth == 256) &&
66 "Unsupported vector width");
67 EVT VT = Vec.getValueType();
68 EVT ElVT = VT.getVectorElementType();
69 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
71 VT.getVectorNumElements()/Factor);
73 // Extract from UNDEF is UNDEF.
74 if (Vec.getOpcode() == ISD::UNDEF)
75 return DAG.getUNDEF(ResultVT);
77 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
78 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
80 // This is the index of the first element of the vectorWidth-bit chunk
82 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
85 // If the input is a buildvector just emit a smaller one.
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
88 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
90 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
97 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
98 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
99 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
100 /// instructions or a simple subregister reference. Idx is an index in the
101 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
102 /// lowering EXTRACT_VECTOR_ELT operations easier.
103 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
104 SelectionDAG &DAG, SDLoc dl) {
105 assert((Vec.getValueType().is256BitVector() ||
106 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
107 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
110 /// Generate a DAG to grab 256-bits from a 512-bit vector.
111 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
112 SelectionDAG &DAG, SDLoc dl) {
113 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
114 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
117 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
118 unsigned IdxVal, SelectionDAG &DAG,
119 SDLoc dl, unsigned vectorWidth) {
120 assert((vectorWidth == 128 || vectorWidth == 256) &&
121 "Unsupported vector width");
122 // Inserting UNDEF is Result
123 if (Vec.getOpcode() == ISD::UNDEF)
125 EVT VT = Vec.getValueType();
126 EVT ElVT = VT.getVectorElementType();
127 EVT ResultVT = Result.getValueType();
129 // Insert the relevant vectorWidth bits.
130 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
132 // This is the index of the first element of the vectorWidth-bit chunk
134 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
137 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
141 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
142 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
143 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
144 /// simple superregister reference. Idx is an index in the 128 bits
145 /// we want. It need not be aligned to a 128-bit bounday. That makes
146 /// lowering INSERT_VECTOR_ELT operations easier.
147 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
148 unsigned IdxVal, SelectionDAG &DAG,
150 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
151 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
154 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
155 unsigned IdxVal, SelectionDAG &DAG,
157 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
158 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
161 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
162 /// instructions. This is used because creating CONCAT_VECTOR nodes of
163 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
164 /// large BUILD_VECTORS.
165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
166 unsigned NumElems, SelectionDAG &DAG,
168 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
173 unsigned NumElems, SelectionDAG &DAG,
175 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
179 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
180 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
181 bool is64Bit = Subtarget->is64Bit();
183 if (Subtarget->isTargetEnvMacho()) {
185 return new X86_64MachoTargetObjectFile();
186 return new TargetLoweringObjectFileMachO();
189 if (Subtarget->isTargetLinux())
190 return new X86LinuxTargetObjectFile();
191 if (Subtarget->isTargetELF())
192 return new TargetLoweringObjectFileELF();
193 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
194 return new TargetLoweringObjectFileCOFF();
195 llvm_unreachable("unknown subtarget type");
198 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
199 : TargetLowering(TM, createTLOF(TM)) {
200 Subtarget = &TM.getSubtarget<X86Subtarget>();
201 X86ScalarSSEf64 = Subtarget->hasSSE2();
202 X86ScalarSSEf32 = Subtarget->hasSSE1();
203 TD = getDataLayout();
205 resetOperationActions();
208 void X86TargetLowering::resetOperationActions() {
209 const TargetMachine &TM = getTargetMachine();
210 static bool FirstTimeThrough = true;
212 // If none of the target options have changed, then we don't need to reset the
213 // operation actions.
214 if (!FirstTimeThrough && TO == TM.Options) return;
216 if (!FirstTimeThrough) {
217 // Reinitialize the actions.
219 FirstTimeThrough = false;
224 // Set up the TargetLowering object.
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
228 setBooleanContents(ZeroOrOneBooleanContent);
229 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // For 64-bit since we have so many registers use the ILP scheduler, for
233 // 32-bit code use the register pressure specific scheduling.
234 // For Atom, always use ILP scheduling.
235 if (Subtarget->isAtom())
236 setSchedulingPreference(Sched::ILP);
237 else if (Subtarget->is64Bit())
238 setSchedulingPreference(Sched::ILP);
240 setSchedulingPreference(Sched::RegPressure);
241 const X86RegisterInfo *RegInfo =
242 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
243 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
245 // Bypass expensive divides on Atom when compiling with O2
246 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
247 addBypassSlowDiv(32, 8);
248 if (Subtarget->is64Bit())
249 addBypassSlowDiv(64, 16);
252 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
253 // Setup Windows compiler runtime calls.
254 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
255 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
256 setLibcallName(RTLIB::SREM_I64, "_allrem");
257 setLibcallName(RTLIB::UREM_I64, "_aullrem");
258 setLibcallName(RTLIB::MUL_I64, "_allmul");
259 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
265 // The _ftol2 runtime function has an unusual calling conv, which
266 // is modeled by a special pseudo-instruction.
267 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
270 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
273 if (Subtarget->isTargetDarwin()) {
274 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
275 setUseUnderscoreSetJmp(false);
276 setUseUnderscoreLongJmp(false);
277 } else if (Subtarget->isTargetMingw()) {
278 // MS runtime is weird: it exports _setjmp, but longjmp!
279 setUseUnderscoreSetJmp(true);
280 setUseUnderscoreLongJmp(false);
282 setUseUnderscoreSetJmp(true);
283 setUseUnderscoreLongJmp(true);
286 // Set up the register classes.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
289 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 if (Subtarget->is64Bit())
291 addRegisterClass(MVT::i64, &X86::GR64RegClass);
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 // We don't accept any truncstore of integer registers.
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 // SETOEQ and SETUNE require checking two conditions.
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
311 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
313 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
320 } else if (!TM.Options.UseSoftFloat) {
321 // We have an algorithm for SSE2->double, and we turn this into a
322 // 64-bit FILD followed by conditional FADD for other targets.
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 // We have an algorithm for SSE2, and we turn this into a 64-bit
325 // FILD for other targets.
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
329 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
331 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
332 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
334 if (!TM.Options.UseSoftFloat) {
335 // SSE has no i16 to fp conversion, only i32
336 if (X86ScalarSSEf32) {
337 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 // f32 and f64 cases are Legal, f80 case is not
339 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
349 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
350 // are Legal, f80 is custom lowered.
351 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
354 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
356 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
357 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 if (X86ScalarSSEf32) {
360 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 // f32 and f64 cases are Legal, f80 case is not
362 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 // Handle FP_TO_UINT by promoting the destination to a larger signed
370 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 if (Subtarget->is64Bit()) {
375 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
377 } else if (!TM.Options.UseSoftFloat) {
378 // Since AVX is a superset of SSE3, only check for SSE here.
379 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
380 // Expand FP_TO_UINT into a select.
381 // FIXME: We would like to use a Custom expander here eventually to do
382 // the optimal thing for SSE vs. the default expansion in the legalizer.
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
385 // With SSE3 we can use fisttpll to convert to a signed i64; without
386 // SSE, we're stuck with a fistpll.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
390 if (isTargetFTOL()) {
391 // Use the _ftol2 runtime function, which has a pseudo-instruction
392 // to handle its weird calling convention.
393 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
396 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
397 if (!X86ScalarSSEf64) {
398 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
399 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 // Without SSE, i64->f64 goes through memory.
403 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
407 // Scalar integer divide and remainder are lowered to use operations that
408 // produce two results, to match the available instructions. This exposes
409 // the two-result form to trivial CSE, which is able to combine x/y and x%y
410 // into a single instruction.
412 // Scalar integer multiply-high is also lowered to use two-result
413 // operations, to match the available instructions. However, plain multiply
414 // (low) operations are left as Legal, as there are single-result
415 // instructions for this in x86. Using the two-result multiply instructions
416 // when both high and low results are needed must be arranged by dagcombine.
417 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
419 setOperationAction(ISD::MULHS, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::SDIV, VT, Expand);
422 setOperationAction(ISD::UDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UREM, VT, Expand);
426 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
427 setOperationAction(ISD::ADDC, VT, Custom);
428 setOperationAction(ISD::ADDE, VT, Custom);
429 setOperationAction(ISD::SUBC, VT, Custom);
430 setOperationAction(ISD::SUBE, VT, Custom);
433 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
434 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
435 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
448 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f64 , Expand);
451 setOperationAction(ISD::FREM , MVT::f80 , Expand);
452 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
454 // Promote the i8 variants and force them on up to i32 which has a shorter
456 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
457 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
458 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
459 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 if (Subtarget->hasBMI()) {
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
466 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
467 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 if (Subtarget->is64Bit())
469 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
472 if (Subtarget->hasLZCNT()) {
473 // When promoting the i8 variants, force them to i32 for a shorter
475 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
476 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
478 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 if (Subtarget->is64Bit()) {
491 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 if (Subtarget->hasPOPCNT()) {
497 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
499 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 if (Subtarget->is64Bit())
503 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
506 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
507 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 // These should be promoted to a larger select which is supported.
510 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 // X86 wants to expand cmov itself.
512 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 if (Subtarget->is64Bit()) {
525 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
528 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
529 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
530 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
531 // support continuation, user-level threading, and etc.. As a result, no
532 // other SjLj exception interfaces are implemented and please don't build
533 // your own exception handling based on them.
534 // LLVM/Clang supports zero-cost DWARF exception handling.
535 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
536 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
539 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
540 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
545 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
546 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
549 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
550 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
551 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
555 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 if (Subtarget->hasSSE1())
565 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
567 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
569 // Expand certain atomics
570 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
572 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
574 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
577 if (!Subtarget->is64Bit()) {
578 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 if (Subtarget->hasCmpxchg16b()) {
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
596 // FIXME - use subtarget debug flags
597 if (!Subtarget->isTargetDarwin() &&
598 !Subtarget->isTargetELF() &&
599 !Subtarget->isTargetCygMing()) {
600 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
603 if (Subtarget->is64Bit()) {
604 setExceptionPointerRegister(X86::RAX);
605 setExceptionSelectorRegister(X86::RDX);
607 setExceptionPointerRegister(X86::EAX);
608 setExceptionSelectorRegister(X86::EDX);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
613 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
614 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
616 setOperationAction(ISD::TRAP, MVT::Other, Legal);
617 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
620 setOperationAction(ISD::VASTART , MVT::Other, Custom);
621 setOperationAction(ISD::VAEND , MVT::Other, Expand);
622 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
623 // TargetInfo::X86_64ABIBuiltinVaList
624 setOperationAction(ISD::VAARG , MVT::Other, Custom);
625 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 // TargetInfo::CharPtrBuiltinVaList
628 setOperationAction(ISD::VAARG , MVT::Other, Expand);
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
632 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
633 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
635 if (Subtarget->isOSWindows() && !Subtarget->isTargetEnvMacho())
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
637 MVT::i64 : MVT::i32, Custom);
638 else if (TM.Options.EnableSegmentedStacks)
639 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
640 MVT::i64 : MVT::i32, Custom);
642 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
643 MVT::i64 : MVT::i32, Expand);
645 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
646 // f32 and f64 use SSE.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f32, &X86::FR32RegClass);
649 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 // Use ANDPD to simulate FABS.
652 setOperationAction(ISD::FABS , MVT::f64, Custom);
653 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 // Use XORP to simulate FNEG.
656 setOperationAction(ISD::FNEG , MVT::f64, Custom);
657 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 // Use ANDPD and ORPD to simulate FCOPYSIGN.
660 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 // Lower this to FGETSIGNx86 plus an AND.
664 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
665 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 // We don't support sin/cos/fmod
668 setOperationAction(ISD::FSIN , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f64, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSIN , MVT::f32, Expand);
672 setOperationAction(ISD::FCOS , MVT::f32, Expand);
673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
675 // Expand FP immediates into loads from the stack, except for the special
677 addLegalFPImmediate(APFloat(+0.0)); // xorpd
678 addLegalFPImmediate(APFloat(+0.0f)); // xorps
679 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
680 // Use SSE for f32, x87 for f64.
681 // Set up the FP register classes.
682 addRegisterClass(MVT::f32, &X86::FR32RegClass);
683 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 // Use ANDPS to simulate FABS.
686 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 // Use XORP to simulate FNEG.
689 setOperationAction(ISD::FNEG , MVT::f32, Custom);
691 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 // Use ANDPS and ORPS to simulate FCOPYSIGN.
694 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
695 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 // We don't support sin/cos/fmod
698 setOperationAction(ISD::FSIN , MVT::f32, Expand);
699 setOperationAction(ISD::FCOS , MVT::f32, Expand);
700 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
702 // Special cases we handle for FP constants.
703 addLegalFPImmediate(APFloat(+0.0f)); // xorps
704 addLegalFPImmediate(APFloat(+0.0)); // FLD0
705 addLegalFPImmediate(APFloat(+1.0)); // FLD1
706 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FCOS , MVT::f64, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
714 } else if (!TM.Options.UseSoftFloat) {
715 // f32 and f64 in x87.
716 // Set up the FP register classes.
717 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
718 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
721 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 if (!TM.Options.UnsafeFPMath) {
726 setOperationAction(ISD::FSIN , MVT::f64, Expand);
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FCOS , MVT::f32, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
737 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
738 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
739 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
740 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
743 // We don't support FMA.
744 setOperationAction(ISD::FMA, MVT::f64, Expand);
745 setOperationAction(ISD::FMA, MVT::f32, Expand);
747 // Long double always uses X87.
748 if (!TM.Options.UseSoftFloat) {
749 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
750 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
753 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
754 addLegalFPImmediate(TmpFlt); // FLD0
756 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
759 APFloat TmpFlt2(+1.0);
760 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
762 addLegalFPImmediate(TmpFlt2); // FLD1
763 TmpFlt2.changeSign();
764 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
767 if (!TM.Options.UnsafeFPMath) {
768 setOperationAction(ISD::FSIN , MVT::f80, Expand);
769 setOperationAction(ISD::FCOS , MVT::f80, Expand);
770 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
773 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
774 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
775 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
776 setOperationAction(ISD::FRINT, MVT::f80, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
778 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 // Always use a library call for pow.
782 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
786 setOperationAction(ISD::FLOG, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
792 // First set operation action for all vector types to either promote
793 // (for widening) or expand (for scalarization). Then we will selectively
794 // turn on ones that can be effectively codegen'd.
795 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
796 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
797 MVT VT = (MVT::SimpleValueType)i;
798 setOperationAction(ISD::ADD , VT, Expand);
799 setOperationAction(ISD::SUB , VT, Expand);
800 setOperationAction(ISD::FADD, VT, Expand);
801 setOperationAction(ISD::FNEG, VT, Expand);
802 setOperationAction(ISD::FSUB, VT, Expand);
803 setOperationAction(ISD::MUL , VT, Expand);
804 setOperationAction(ISD::FMUL, VT, Expand);
805 setOperationAction(ISD::SDIV, VT, Expand);
806 setOperationAction(ISD::UDIV, VT, Expand);
807 setOperationAction(ISD::FDIV, VT, Expand);
808 setOperationAction(ISD::SREM, VT, Expand);
809 setOperationAction(ISD::UREM, VT, Expand);
810 setOperationAction(ISD::LOAD, VT, Expand);
811 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
814 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::FABS, VT, Expand);
817 setOperationAction(ISD::FSIN, VT, Expand);
818 setOperationAction(ISD::FSINCOS, VT, Expand);
819 setOperationAction(ISD::FCOS, VT, Expand);
820 setOperationAction(ISD::FSINCOS, VT, Expand);
821 setOperationAction(ISD::FREM, VT, Expand);
822 setOperationAction(ISD::FMA, VT, Expand);
823 setOperationAction(ISD::FPOWI, VT, Expand);
824 setOperationAction(ISD::FSQRT, VT, Expand);
825 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
826 setOperationAction(ISD::FFLOOR, VT, Expand);
827 setOperationAction(ISD::FCEIL, VT, Expand);
828 setOperationAction(ISD::FTRUNC, VT, Expand);
829 setOperationAction(ISD::FRINT, VT, Expand);
830 setOperationAction(ISD::FNEARBYINT, VT, Expand);
831 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::SDIVREM, VT, Expand);
834 setOperationAction(ISD::UDIVREM, VT, Expand);
835 setOperationAction(ISD::FPOW, VT, Expand);
836 setOperationAction(ISD::CTPOP, VT, Expand);
837 setOperationAction(ISD::CTTZ, VT, Expand);
838 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
839 setOperationAction(ISD::CTLZ, VT, Expand);
840 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
841 setOperationAction(ISD::SHL, VT, Expand);
842 setOperationAction(ISD::SRA, VT, Expand);
843 setOperationAction(ISD::SRL, VT, Expand);
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 setOperationAction(ISD::BSWAP, VT, Expand);
847 setOperationAction(ISD::SETCC, VT, Expand);
848 setOperationAction(ISD::FLOG, VT, Expand);
849 setOperationAction(ISD::FLOG2, VT, Expand);
850 setOperationAction(ISD::FLOG10, VT, Expand);
851 setOperationAction(ISD::FEXP, VT, Expand);
852 setOperationAction(ISD::FEXP2, VT, Expand);
853 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
854 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
855 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
858 setOperationAction(ISD::TRUNCATE, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
860 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
861 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
862 setOperationAction(ISD::VSELECT, VT, Expand);
863 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
864 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 setTruncStoreAction(VT,
866 (MVT::SimpleValueType)InnerVT, Expand);
867 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
872 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
873 // with -msoft-float, disable use of MMX as well.
874 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
875 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
876 // No operations on x86mmx supported, everything uses intrinsics.
879 // MMX-sized vectors (other than x86mmx) are expected to be expanded
880 // into smaller operations.
881 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
882 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
883 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
884 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
885 setOperationAction(ISD::AND, MVT::v8i8, Expand);
886 setOperationAction(ISD::AND, MVT::v4i16, Expand);
887 setOperationAction(ISD::AND, MVT::v2i32, Expand);
888 setOperationAction(ISD::AND, MVT::v1i64, Expand);
889 setOperationAction(ISD::OR, MVT::v8i8, Expand);
890 setOperationAction(ISD::OR, MVT::v4i16, Expand);
891 setOperationAction(ISD::OR, MVT::v2i32, Expand);
892 setOperationAction(ISD::OR, MVT::v1i64, Expand);
893 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
902 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
903 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
904 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
905 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
912 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
914 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
916 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
917 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
918 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
919 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
920 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
921 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
929 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
931 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
932 // registers cannot be used even for integer operations.
933 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
934 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
935 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
936 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
938 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
939 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
940 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
941 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
945 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
946 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
947 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
948 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
949 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
951 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
954 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
955 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
959 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
960 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
969 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
970 MVT VT = (MVT::SimpleValueType)i;
971 // Do not attempt to custom lower non-power-of-2 vectors
972 if (!isPowerOf2_32(VT.getVectorNumElements()))
974 // Do not attempt to custom lower non-128-bit vectors
975 if (!VT.is128BitVector())
977 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
978 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to promote non-128-bit vectors
999 if (!VT.is128BitVector())
1002 setOperationAction(ISD::AND, VT, Promote);
1003 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 setOperationAction(ISD::OR, VT, Promote);
1005 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 setOperationAction(ISD::XOR, VT, Promote);
1007 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 setOperationAction(ISD::LOAD, VT, Promote);
1009 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 setOperationAction(ISD::SELECT, VT, Promote);
1011 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 // Custom lower v2i64 and v2f64 selects.
1017 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1019 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1027 // As there is no 64-bit GPR available, we need build a special custom
1028 // sequence to convert from v2i32 to v2f32.
1029 if (!Subtarget->is64Bit())
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1039 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1047 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 // FIXME: Do we need to handle scalar-to-vector here?
1062 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1070 // i8 and i16 vectors are custom , because the source register and source
1071 // source memory operand types are not the same width. f32 vectors are
1072 // custom since the immediate controlling the insert encodes additional
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1084 // FIXME: these should be Legal but thats only for the case where
1085 // the index is constant. For now custom expand to deal with that.
1086 if (Subtarget->is64Bit()) {
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1088 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 if (Subtarget->hasSSE2()) {
1093 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1102 // In the customized shift lowering, the legal cases in AVX2 will be
1104 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1105 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1124 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1128 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1139 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1141 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1152 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1159 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1166 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1186 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1204 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1205 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1209 setOperationAction(ISD::FMA, MVT::f32, Legal);
1210 setOperationAction(ISD::FMA, MVT::f64, Legal);
1213 if (Subtarget->hasInt256()) {
1214 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1227 // Don't lower v32i8 because there is no 128-bit byte mul
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1231 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1234 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1235 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1243 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1245 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1246 // Don't lower v32i8 because there is no 128-bit byte mul
1249 // In the customized shift lowering, the legal cases in AVX2 will be
1251 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1259 // Custom lower several nodes for 256-bit types.
1260 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1261 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262 MVT VT = (MVT::SimpleValueType)i;
1264 // Extract subvector is special because the value type
1265 // (result) is 128-bit but the source is 256-bit wide.
1266 if (VT.is128BitVector())
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1269 // Do not attempt to custom lower other non-256-bit vectors
1270 if (!VT.is256BitVector())
1273 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1275 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1278 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1279 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1310 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1312 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1315 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1316 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1317 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1319 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1326 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1332 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1334 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1336 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1337 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1340 if (Subtarget->is64Bit()) {
1341 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1343 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1346 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1348 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1349 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1350 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1353 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1355 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1356 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1357 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1359 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1360 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1361 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1364 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1371 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1374 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1377 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1379 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1380 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1381 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1382 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1383 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1385 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1388 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1389 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1391 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1393 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1399 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1400 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1402 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1403 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1404 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1405 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1406 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1407 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1409 // Custom lower several nodes.
1410 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1411 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1412 MVT VT = (MVT::SimpleValueType)i;
1414 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1415 // Extract subvector is special because the value type
1416 // (result) is 256/128-bit but the source is 512-bit wide.
1417 if (VT.is128BitVector() || VT.is256BitVector())
1418 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1420 if (VT.getVectorElementType() == MVT::i1)
1421 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1423 // Do not attempt to custom lower other non-512-bit vectors
1424 if (!VT.is512BitVector())
1427 if ( EltSize >= 32) {
1428 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1429 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1430 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1431 setOperationAction(ISD::VSELECT, VT, Legal);
1432 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1433 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1434 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1437 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1438 MVT VT = (MVT::SimpleValueType)i;
1440 // Do not attempt to promote non-256-bit vectors
1441 if (!VT.is512BitVector())
1444 setOperationAction(ISD::SELECT, VT, Promote);
1445 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1449 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1450 // of this type with custom code.
1451 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1452 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1453 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1457 // We want to custom lower some of our intrinsics.
1458 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1459 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1460 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1462 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1463 // handle type legalization for these operations here.
1465 // FIXME: We really should do custom legalization for addition and
1466 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1467 // than generic legalization for 64-bit multiplication-with-overflow, though.
1468 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1469 // Add/Sub/Mul with overflow operations are custom lowered.
1471 setOperationAction(ISD::SADDO, VT, Custom);
1472 setOperationAction(ISD::UADDO, VT, Custom);
1473 setOperationAction(ISD::SSUBO, VT, Custom);
1474 setOperationAction(ISD::USUBO, VT, Custom);
1475 setOperationAction(ISD::SMULO, VT, Custom);
1476 setOperationAction(ISD::UMULO, VT, Custom);
1479 // There are no 8-bit 3-address imul/mul instructions
1480 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1481 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1483 if (!Subtarget->is64Bit()) {
1484 // These libcalls are not available in 32-bit.
1485 setLibcallName(RTLIB::SHL_I128, 0);
1486 setLibcallName(RTLIB::SRL_I128, 0);
1487 setLibcallName(RTLIB::SRA_I128, 0);
1490 // Combine sin / cos into one node or libcall if possible.
1491 if (Subtarget->hasSinCos()) {
1492 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1493 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1494 if (Subtarget->isTargetDarwin()) {
1495 // For MacOSX, we don't want to the normal expansion of a libcall to
1496 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1498 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1499 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1503 // We have target-specific dag combine patterns for the following nodes:
1504 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1505 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1506 setTargetDAGCombine(ISD::VSELECT);
1507 setTargetDAGCombine(ISD::SELECT);
1508 setTargetDAGCombine(ISD::SHL);
1509 setTargetDAGCombine(ISD::SRA);
1510 setTargetDAGCombine(ISD::SRL);
1511 setTargetDAGCombine(ISD::OR);
1512 setTargetDAGCombine(ISD::AND);
1513 setTargetDAGCombine(ISD::ADD);
1514 setTargetDAGCombine(ISD::FADD);
1515 setTargetDAGCombine(ISD::FSUB);
1516 setTargetDAGCombine(ISD::FMA);
1517 setTargetDAGCombine(ISD::SUB);
1518 setTargetDAGCombine(ISD::LOAD);
1519 setTargetDAGCombine(ISD::STORE);
1520 setTargetDAGCombine(ISD::ZERO_EXTEND);
1521 setTargetDAGCombine(ISD::ANY_EXTEND);
1522 setTargetDAGCombine(ISD::SIGN_EXTEND);
1523 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1524 setTargetDAGCombine(ISD::TRUNCATE);
1525 setTargetDAGCombine(ISD::SINT_TO_FP);
1526 setTargetDAGCombine(ISD::SETCC);
1527 if (Subtarget->is64Bit())
1528 setTargetDAGCombine(ISD::MUL);
1529 setTargetDAGCombine(ISD::XOR);
1531 computeRegisterProperties();
1533 // On Darwin, -Os means optimize for size without hurting performance,
1534 // do not reduce the limit.
1535 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1536 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1537 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1538 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1539 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1540 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1541 setPrefLoopAlignment(4); // 2^4 bytes.
1543 // Predictable cmov don't hurt on atom because it's in-order.
1544 PredictableSelectIsExpensive = !Subtarget->isAtom();
1546 setPrefFunctionAlignment(4); // 2^4 bytes.
1549 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1553 const TargetMachine &TM = getTargetMachine();
1554 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
1555 switch(VT.getVectorNumElements()) {
1556 case 8: return MVT::v8i1;
1557 case 16: return MVT::v16i1;
1560 return VT.changeVectorElementTypeToInteger();
1563 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1564 /// the desired ByVal argument alignment.
1565 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1568 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1569 if (VTy->getBitWidth() == 128)
1571 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1572 unsigned EltAlign = 0;
1573 getMaxByValAlign(ATy->getElementType(), EltAlign);
1574 if (EltAlign > MaxAlign)
1575 MaxAlign = EltAlign;
1576 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1577 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1578 unsigned EltAlign = 0;
1579 getMaxByValAlign(STy->getElementType(i), EltAlign);
1580 if (EltAlign > MaxAlign)
1581 MaxAlign = EltAlign;
1588 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1589 /// function arguments in the caller parameter area. For X86, aggregates
1590 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1591 /// are at 4-byte boundaries.
1592 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1593 if (Subtarget->is64Bit()) {
1594 // Max of 8 and alignment of type.
1595 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1602 if (Subtarget->hasSSE1())
1603 getMaxByValAlign(Ty, Align);
1607 /// getOptimalMemOpType - Returns the target specific optimal type for load
1608 /// and store operations as a result of memset, memcpy, and memmove
1609 /// lowering. If DstAlign is zero that means it's safe to destination
1610 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1611 /// means there isn't a need to check it against alignment requirement,
1612 /// probably because the source does not need to be loaded. If 'IsMemset' is
1613 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1614 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1615 /// source is constant so it does not need to be loaded.
1616 /// It returns EVT::Other if the type should be determined using generic
1617 /// target-independent logic.
1619 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1620 unsigned DstAlign, unsigned SrcAlign,
1621 bool IsMemset, bool ZeroMemset,
1623 MachineFunction &MF) const {
1624 const Function *F = MF.getFunction();
1625 if ((!IsMemset || ZeroMemset) &&
1626 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1627 Attribute::NoImplicitFloat)) {
1629 (Subtarget->isUnalignedMemAccessFast() ||
1630 ((DstAlign == 0 || DstAlign >= 16) &&
1631 (SrcAlign == 0 || SrcAlign >= 16)))) {
1633 if (Subtarget->hasInt256())
1635 if (Subtarget->hasFp256())
1638 if (Subtarget->hasSSE2())
1640 if (Subtarget->hasSSE1())
1642 } else if (!MemcpyStrSrc && Size >= 8 &&
1643 !Subtarget->is64Bit() &&
1644 Subtarget->hasSSE2()) {
1645 // Do not use f64 to lower memcpy if source is string constant. It's
1646 // better to use i32 to avoid the loads.
1650 if (Subtarget->is64Bit() && Size >= 8)
1655 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1657 return X86ScalarSSEf32;
1658 else if (VT == MVT::f64)
1659 return X86ScalarSSEf64;
1664 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1666 *Fast = Subtarget->isUnalignedMemAccessFast();
1670 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1671 /// current function. The returned value is a member of the
1672 /// MachineJumpTableInfo::JTEntryKind enum.
1673 unsigned X86TargetLowering::getJumpTableEncoding() const {
1674 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1676 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1677 Subtarget->isPICStyleGOT())
1678 return MachineJumpTableInfo::EK_Custom32;
1680 // Otherwise, use the normal jump table encoding heuristics.
1681 return TargetLowering::getJumpTableEncoding();
1685 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1686 const MachineBasicBlock *MBB,
1687 unsigned uid,MCContext &Ctx) const{
1688 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1689 Subtarget->isPICStyleGOT());
1690 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1692 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1693 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1696 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1698 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1699 SelectionDAG &DAG) const {
1700 if (!Subtarget->is64Bit())
1701 // This doesn't have SDLoc associated with it, but is not really the
1702 // same as a Register.
1703 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1707 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1708 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1710 const MCExpr *X86TargetLowering::
1711 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1712 MCContext &Ctx) const {
1713 // X86-64 uses RIP relative addressing based on the jump table label.
1714 if (Subtarget->isPICStyleRIPRel())
1715 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1717 // Otherwise, the reference is relative to the PIC base.
1718 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1721 // FIXME: Why this routine is here? Move to RegInfo!
1722 std::pair<const TargetRegisterClass*, uint8_t>
1723 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1724 const TargetRegisterClass *RRC = 0;
1726 switch (VT.SimpleTy) {
1728 return TargetLowering::findRepresentativeClass(VT);
1729 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1730 RRC = Subtarget->is64Bit() ?
1731 (const TargetRegisterClass*)&X86::GR64RegClass :
1732 (const TargetRegisterClass*)&X86::GR32RegClass;
1735 RRC = &X86::VR64RegClass;
1737 case MVT::f32: case MVT::f64:
1738 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1739 case MVT::v4f32: case MVT::v2f64:
1740 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1742 RRC = &X86::VR128RegClass;
1745 return std::make_pair(RRC, Cost);
1748 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1749 unsigned &Offset) const {
1750 if (!Subtarget->isTargetLinux())
1753 if (Subtarget->is64Bit()) {
1754 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1756 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1768 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1769 unsigned DestAS) const {
1770 assert(SrcAS != DestAS && "Expected different address spaces!");
1772 return SrcAS < 256 && DestAS < 256;
1775 //===----------------------------------------------------------------------===//
1776 // Return Value Calling Convention Implementation
1777 //===----------------------------------------------------------------------===//
1779 #include "X86GenCallingConv.inc"
1782 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1783 MachineFunction &MF, bool isVarArg,
1784 const SmallVectorImpl<ISD::OutputArg> &Outs,
1785 LLVMContext &Context) const {
1786 SmallVector<CCValAssign, 16> RVLocs;
1787 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1789 return CCInfo.CheckReturn(Outs, RetCC_X86);
1792 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1793 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1798 X86TargetLowering::LowerReturn(SDValue Chain,
1799 CallingConv::ID CallConv, bool isVarArg,
1800 const SmallVectorImpl<ISD::OutputArg> &Outs,
1801 const SmallVectorImpl<SDValue> &OutVals,
1802 SDLoc dl, SelectionDAG &DAG) const {
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1806 SmallVector<CCValAssign, 16> RVLocs;
1807 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1808 RVLocs, *DAG.getContext());
1809 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1812 SmallVector<SDValue, 6> RetOps;
1813 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1814 // Operand #1 = Bytes To Pop
1815 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1818 // Copy the result values into the output registers.
1819 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1820 CCValAssign &VA = RVLocs[i];
1821 assert(VA.isRegLoc() && "Can only return in registers!");
1822 SDValue ValToCopy = OutVals[i];
1823 EVT ValVT = ValToCopy.getValueType();
1825 // Promote values to the appropriate types
1826 if (VA.getLocInfo() == CCValAssign::SExt)
1827 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1828 else if (VA.getLocInfo() == CCValAssign::ZExt)
1829 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1830 else if (VA.getLocInfo() == CCValAssign::AExt)
1831 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1832 else if (VA.getLocInfo() == CCValAssign::BCvt)
1833 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1835 // If this is x86-64, and we disabled SSE, we can't return FP values,
1836 // or SSE or MMX vectors.
1837 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1838 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1839 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1840 report_fatal_error("SSE register return with SSE disabled");
1842 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1843 // llvm-gcc has never done it right and no one has noticed, so this
1844 // should be OK for now.
1845 if (ValVT == MVT::f64 &&
1846 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1847 report_fatal_error("SSE2 register return with SSE2 disabled");
1849 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1850 // the RET instruction and handled by the FP Stackifier.
1851 if (VA.getLocReg() == X86::ST0 ||
1852 VA.getLocReg() == X86::ST1) {
1853 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1854 // change the value to the FP stack register class.
1855 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1856 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1857 RetOps.push_back(ValToCopy);
1858 // Don't emit a copytoreg.
1862 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1863 // which is returned in RAX / RDX.
1864 if (Subtarget->is64Bit()) {
1865 if (ValVT == MVT::x86mmx) {
1866 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1867 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1868 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1870 // If we don't have SSE2 available, convert to v4f32 so the generated
1871 // register is legal.
1872 if (!Subtarget->hasSSE2())
1873 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1878 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1879 Flag = Chain.getValue(1);
1880 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1883 // The x86-64 ABIs require that for returning structs by value we copy
1884 // the sret argument into %rax/%eax (depending on ABI) for the return.
1885 // Win32 requires us to put the sret argument to %eax as well.
1886 // We saved the argument into a virtual register in the entry block,
1887 // so now we copy the value out and into %rax/%eax.
1888 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1889 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1890 MachineFunction &MF = DAG.getMachineFunction();
1891 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1892 unsigned Reg = FuncInfo->getSRetReturnReg();
1894 "SRetReturnReg should have been set in LowerFormalArguments().");
1895 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1898 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1899 X86::RAX : X86::EAX;
1900 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1901 Flag = Chain.getValue(1);
1903 // RAX/EAX now acts like a return value.
1904 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1907 RetOps[0] = Chain; // Update chain.
1909 // Add the flag if we have it.
1911 RetOps.push_back(Flag);
1913 return DAG.getNode(X86ISD::RET_FLAG, dl,
1914 MVT::Other, &RetOps[0], RetOps.size());
1917 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1918 if (N->getNumValues() != 1)
1920 if (!N->hasNUsesOfValue(1, 0))
1923 SDValue TCChain = Chain;
1924 SDNode *Copy = *N->use_begin();
1925 if (Copy->getOpcode() == ISD::CopyToReg) {
1926 // If the copy has a glue operand, we conservatively assume it isn't safe to
1927 // perform a tail call.
1928 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1930 TCChain = Copy->getOperand(0);
1931 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1934 bool HasRet = false;
1935 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1937 if (UI->getOpcode() != X86ISD::RET_FLAG)
1950 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1951 ISD::NodeType ExtendKind) const {
1953 // TODO: Is this also valid on 32-bit?
1954 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1955 ReturnMVT = MVT::i8;
1957 ReturnMVT = MVT::i32;
1959 MVT MinVT = getRegisterType(ReturnMVT);
1960 return VT.bitsLT(MinVT) ? MinVT : VT;
1963 /// LowerCallResult - Lower the result values of a call into the
1964 /// appropriate copies out of appropriate physical registers.
1967 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1968 CallingConv::ID CallConv, bool isVarArg,
1969 const SmallVectorImpl<ISD::InputArg> &Ins,
1970 SDLoc dl, SelectionDAG &DAG,
1971 SmallVectorImpl<SDValue> &InVals) const {
1973 // Assign locations to each value returned by this call.
1974 SmallVector<CCValAssign, 16> RVLocs;
1975 bool Is64Bit = Subtarget->is64Bit();
1976 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1977 getTargetMachine(), RVLocs, *DAG.getContext());
1978 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1980 // Copy all of the result registers out of their specified physreg.
1981 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1982 CCValAssign &VA = RVLocs[i];
1983 EVT CopyVT = VA.getValVT();
1985 // If this is x86-64, and we disabled SSE, we can't return FP values
1986 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1987 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1988 report_fatal_error("SSE register return with SSE disabled");
1993 // If this is a call to a function that returns an fp value on the floating
1994 // point stack, we must guarantee the value is popped from the stack, so
1995 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1996 // if the return value is not used. We use the FpPOP_RETVAL instruction
1998 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1999 // If we prefer to use the value in xmm registers, copy it out as f80 and
2000 // use a truncate to move it from fp stack reg to xmm reg.
2001 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2002 SDValue Ops[] = { Chain, InFlag };
2003 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2004 MVT::Other, MVT::Glue, Ops), 1);
2005 Val = Chain.getValue(0);
2007 // Round the f80 to the right size, which also moves it to the appropriate
2009 if (CopyVT != VA.getValVT())
2010 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2011 // This truncation won't change the value.
2012 DAG.getIntPtrConstant(1));
2014 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2015 CopyVT, InFlag).getValue(1);
2016 Val = Chain.getValue(0);
2018 InFlag = Chain.getValue(2);
2019 InVals.push_back(Val);
2025 //===----------------------------------------------------------------------===//
2026 // C & StdCall & Fast Calling Convention implementation
2027 //===----------------------------------------------------------------------===//
2028 // StdCall calling convention seems to be standard for many Windows' API
2029 // routines and around. It differs from C calling convention just a little:
2030 // callee should clean up the stack, not caller. Symbols should be also
2031 // decorated in some fancy way :) It doesn't support any vector arguments.
2032 // For info on fast calling convention see Fast Calling Convention (tail call)
2033 // implementation LowerX86_32FastCCCallTo.
2035 /// CallIsStructReturn - Determines whether a call uses struct return
2037 enum StructReturnType {
2042 static StructReturnType
2043 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2045 return NotStructReturn;
2047 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2048 if (!Flags.isSRet())
2049 return NotStructReturn;
2050 if (Flags.isInReg())
2051 return RegStructReturn;
2052 return StackStructReturn;
2055 /// ArgsAreStructReturn - Determines whether a function uses struct
2056 /// return semantics.
2057 static StructReturnType
2058 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2060 return NotStructReturn;
2062 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2063 if (!Flags.isSRet())
2064 return NotStructReturn;
2065 if (Flags.isInReg())
2066 return RegStructReturn;
2067 return StackStructReturn;
2070 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2071 /// by "Src" to address "Dst" with size and alignment information specified by
2072 /// the specific parameter attribute. The copy will be passed as a byval
2073 /// function parameter.
2075 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2076 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2078 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2080 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2081 /*isVolatile*/false, /*AlwaysInline=*/true,
2082 MachinePointerInfo(), MachinePointerInfo());
2085 /// IsTailCallConvention - Return true if the calling convention is one that
2086 /// supports tail call optimization.
2087 static bool IsTailCallConvention(CallingConv::ID CC) {
2088 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2089 CC == CallingConv::HiPE);
2092 /// \brief Return true if the calling convention is a C calling convention.
2093 static bool IsCCallConvention(CallingConv::ID CC) {
2094 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2095 CC == CallingConv::X86_64_SysV);
2098 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2099 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2103 CallingConv::ID CalleeCC = CS.getCallingConv();
2104 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2110 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2111 /// a tailcall target by changing its ABI.
2112 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2113 bool GuaranteedTailCallOpt) {
2114 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2118 X86TargetLowering::LowerMemArgument(SDValue Chain,
2119 CallingConv::ID CallConv,
2120 const SmallVectorImpl<ISD::InputArg> &Ins,
2121 SDLoc dl, SelectionDAG &DAG,
2122 const CCValAssign &VA,
2123 MachineFrameInfo *MFI,
2125 // Create the nodes corresponding to a load from this parameter slot.
2126 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2127 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2128 getTargetMachine().Options.GuaranteedTailCallOpt);
2129 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2132 // If value is passed by pointer we have address passed instead of the value
2134 if (VA.getLocInfo() == CCValAssign::Indirect)
2135 ValVT = VA.getLocVT();
2137 ValVT = VA.getValVT();
2139 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2140 // changed with more analysis.
2141 // In case of tail call optimization mark all arguments mutable. Since they
2142 // could be overwritten by lowering of arguments in case of a tail call.
2143 if (Flags.isByVal()) {
2144 unsigned Bytes = Flags.getByValSize();
2145 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2146 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2147 return DAG.getFrameIndex(FI, getPointerTy());
2149 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2150 VA.getLocMemOffset(), isImmutable);
2151 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2152 return DAG.getLoad(ValVT, dl, Chain, FIN,
2153 MachinePointerInfo::getFixedStack(FI),
2154 false, false, false, 0);
2159 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2160 CallingConv::ID CallConv,
2162 const SmallVectorImpl<ISD::InputArg> &Ins,
2165 SmallVectorImpl<SDValue> &InVals)
2167 MachineFunction &MF = DAG.getMachineFunction();
2168 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2170 const Function* Fn = MF.getFunction();
2171 if (Fn->hasExternalLinkage() &&
2172 Subtarget->isTargetCygMing() &&
2173 Fn->getName() == "main")
2174 FuncInfo->setForceFramePointer(true);
2176 MachineFrameInfo *MFI = MF.getFrameInfo();
2177 bool Is64Bit = Subtarget->is64Bit();
2178 bool IsWindows = Subtarget->isTargetWindows();
2179 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2181 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2182 "Var args not supported with calling convention fastcc, ghc or hipe");
2184 // Assign locations to all of the incoming arguments.
2185 SmallVector<CCValAssign, 16> ArgLocs;
2186 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2187 ArgLocs, *DAG.getContext());
2189 // Allocate shadow area for Win64
2191 CCInfo.AllocateStack(32, 8);
2193 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2195 unsigned LastVal = ~0U;
2197 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2198 CCValAssign &VA = ArgLocs[i];
2199 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2201 assert(VA.getValNo() != LastVal &&
2202 "Don't support value assigned to multiple locs yet");
2204 LastVal = VA.getValNo();
2206 if (VA.isRegLoc()) {
2207 EVT RegVT = VA.getLocVT();
2208 const TargetRegisterClass *RC;
2209 if (RegVT == MVT::i32)
2210 RC = &X86::GR32RegClass;
2211 else if (Is64Bit && RegVT == MVT::i64)
2212 RC = &X86::GR64RegClass;
2213 else if (RegVT == MVT::f32)
2214 RC = &X86::FR32RegClass;
2215 else if (RegVT == MVT::f64)
2216 RC = &X86::FR64RegClass;
2217 else if (RegVT.is512BitVector())
2218 RC = &X86::VR512RegClass;
2219 else if (RegVT.is256BitVector())
2220 RC = &X86::VR256RegClass;
2221 else if (RegVT.is128BitVector())
2222 RC = &X86::VR128RegClass;
2223 else if (RegVT == MVT::x86mmx)
2224 RC = &X86::VR64RegClass;
2225 else if (RegVT == MVT::v8i1)
2226 RC = &X86::VK8RegClass;
2227 else if (RegVT == MVT::v16i1)
2228 RC = &X86::VK16RegClass;
2230 llvm_unreachable("Unknown argument type!");
2232 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2233 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2235 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2236 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2238 if (VA.getLocInfo() == CCValAssign::SExt)
2239 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2240 DAG.getValueType(VA.getValVT()));
2241 else if (VA.getLocInfo() == CCValAssign::ZExt)
2242 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2243 DAG.getValueType(VA.getValVT()));
2244 else if (VA.getLocInfo() == CCValAssign::BCvt)
2245 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2247 if (VA.isExtInLoc()) {
2248 // Handle MMX values passed in XMM regs.
2249 if (RegVT.isVector())
2250 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2252 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2255 assert(VA.isMemLoc());
2256 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2259 // If value is passed via pointer - do a load.
2260 if (VA.getLocInfo() == CCValAssign::Indirect)
2261 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2262 MachinePointerInfo(), false, false, false, 0);
2264 InVals.push_back(ArgValue);
2267 // The x86-64 ABIs require that for returning structs by value we copy
2268 // the sret argument into %rax/%eax (depending on ABI) for the return.
2269 // Win32 requires us to put the sret argument to %eax as well.
2270 // Save the argument into a virtual register so that we can access it
2271 // from the return points.
2272 if (MF.getFunction()->hasStructRetAttr() &&
2273 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2274 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2275 unsigned Reg = FuncInfo->getSRetReturnReg();
2277 MVT PtrTy = getPointerTy();
2278 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2279 FuncInfo->setSRetReturnReg(Reg);
2281 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2285 unsigned StackSize = CCInfo.getNextStackOffset();
2286 // Align stack specially for tail calls.
2287 if (FuncIsMadeTailCallSafe(CallConv,
2288 MF.getTarget().Options.GuaranteedTailCallOpt))
2289 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2291 // If the function takes variable number of arguments, make a frame index for
2292 // the start of the first vararg value... for expansion of llvm.va_start.
2294 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2295 CallConv != CallingConv::X86_ThisCall)) {
2296 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2299 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2301 // FIXME: We should really autogenerate these arrays
2302 static const uint16_t GPR64ArgRegsWin64[] = {
2303 X86::RCX, X86::RDX, X86::R8, X86::R9
2305 static const uint16_t GPR64ArgRegs64Bit[] = {
2306 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2308 static const uint16_t XMMArgRegs64Bit[] = {
2309 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2310 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2312 const uint16_t *GPR64ArgRegs;
2313 unsigned NumXMMRegs = 0;
2316 // The XMM registers which might contain var arg parameters are shadowed
2317 // in their paired GPR. So we only need to save the GPR to their home
2319 TotalNumIntRegs = 4;
2320 GPR64ArgRegs = GPR64ArgRegsWin64;
2322 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2323 GPR64ArgRegs = GPR64ArgRegs64Bit;
2325 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2328 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2331 bool NoImplicitFloatOps = Fn->getAttributes().
2332 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2333 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2334 "SSE register cannot be used when SSE is disabled!");
2335 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2336 NoImplicitFloatOps) &&
2337 "SSE register cannot be used when SSE is disabled!");
2338 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2339 !Subtarget->hasSSE1())
2340 // Kernel mode asks for SSE to be disabled, so don't push them
2342 TotalNumXMMRegs = 0;
2345 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2346 // Get to the caller-allocated home save location. Add 8 to account
2347 // for the return address.
2348 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2349 FuncInfo->setRegSaveFrameIndex(
2350 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2351 // Fixup to set vararg frame on shadow area (4 x i64).
2353 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2355 // For X86-64, if there are vararg parameters that are passed via
2356 // registers, then we must store them to their spots on the stack so
2357 // they may be loaded by deferencing the result of va_next.
2358 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2359 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2360 FuncInfo->setRegSaveFrameIndex(
2361 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2365 // Store the integer parameter registers.
2366 SmallVector<SDValue, 8> MemOps;
2367 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2369 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2370 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2371 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2372 DAG.getIntPtrConstant(Offset));
2373 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2374 &X86::GR64RegClass);
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2377 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2378 MachinePointerInfo::getFixedStack(
2379 FuncInfo->getRegSaveFrameIndex(), Offset),
2381 MemOps.push_back(Store);
2385 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2386 // Now store the XMM (fp + vector) parameter registers.
2387 SmallVector<SDValue, 11> SaveXMMOps;
2388 SaveXMMOps.push_back(Chain);
2390 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2391 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2392 SaveXMMOps.push_back(ALVal);
2394 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2395 FuncInfo->getRegSaveFrameIndex()));
2396 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2397 FuncInfo->getVarArgsFPOffset()));
2399 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2400 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2401 &X86::VR128RegClass);
2402 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2403 SaveXMMOps.push_back(Val);
2405 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2407 &SaveXMMOps[0], SaveXMMOps.size()));
2410 if (!MemOps.empty())
2411 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2412 &MemOps[0], MemOps.size());
2416 // Some CCs need callee pop.
2417 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2418 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2419 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2421 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2422 // If this is an sret function, the return should pop the hidden pointer.
2423 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2424 argsAreStructReturn(Ins) == StackStructReturn)
2425 FuncInfo->setBytesToPopOnReturn(4);
2429 // RegSaveFrameIndex is X86-64 only.
2430 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2431 if (CallConv == CallingConv::X86_FastCall ||
2432 CallConv == CallingConv::X86_ThisCall)
2433 // fastcc functions can't have varargs.
2434 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2437 FuncInfo->setArgumentStackSize(StackSize);
2443 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2444 SDValue StackPtr, SDValue Arg,
2445 SDLoc dl, SelectionDAG &DAG,
2446 const CCValAssign &VA,
2447 ISD::ArgFlagsTy Flags) const {
2448 unsigned LocMemOffset = VA.getLocMemOffset();
2449 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2450 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2451 if (Flags.isByVal())
2452 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2454 return DAG.getStore(Chain, dl, Arg, PtrOff,
2455 MachinePointerInfo::getStack(LocMemOffset),
2459 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2460 /// optimization is performed and it is required.
2462 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2463 SDValue &OutRetAddr, SDValue Chain,
2464 bool IsTailCall, bool Is64Bit,
2465 int FPDiff, SDLoc dl) const {
2466 // Adjust the Return address stack slot.
2467 EVT VT = getPointerTy();
2468 OutRetAddr = getReturnAddressFrameIndex(DAG);
2470 // Load the "old" Return address.
2471 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2472 false, false, false, 0);
2473 return SDValue(OutRetAddr.getNode(), 1);
2476 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2477 /// optimization is performed and it is required (FPDiff!=0).
2479 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2480 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2481 unsigned SlotSize, int FPDiff, SDLoc dl) {
2482 // Store the return address to the appropriate stack slot.
2483 if (!FPDiff) return Chain;
2484 // Calculate the new stack slot for the return address.
2485 int NewReturnAddrFI =
2486 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2488 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2489 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2490 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2496 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2497 SmallVectorImpl<SDValue> &InVals) const {
2498 SelectionDAG &DAG = CLI.DAG;
2500 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2501 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2502 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2503 SDValue Chain = CLI.Chain;
2504 SDValue Callee = CLI.Callee;
2505 CallingConv::ID CallConv = CLI.CallConv;
2506 bool &isTailCall = CLI.IsTailCall;
2507 bool isVarArg = CLI.IsVarArg;
2509 MachineFunction &MF = DAG.getMachineFunction();
2510 bool Is64Bit = Subtarget->is64Bit();
2511 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2512 bool IsWindows = Subtarget->isTargetWindows();
2513 StructReturnType SR = callIsStructReturn(Outs);
2514 bool IsSibcall = false;
2516 if (MF.getTarget().Options.DisableTailCalls)
2520 // Check if it's really possible to do a tail call.
2521 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2522 isVarArg, SR != NotStructReturn,
2523 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2524 Outs, OutVals, Ins, DAG);
2526 // Sibcalls are automatically detected tailcalls which do not require
2528 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2535 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2536 "Var args not supported with calling convention fastcc, ghc or hipe");
2538 // Analyze operands of the call, assigning locations to each operand.
2539 SmallVector<CCValAssign, 16> ArgLocs;
2540 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2541 ArgLocs, *DAG.getContext());
2543 // Allocate shadow area for Win64
2545 CCInfo.AllocateStack(32, 8);
2547 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2549 // Get a count of how many bytes are to be pushed on the stack.
2550 unsigned NumBytes = CCInfo.getNextStackOffset();
2552 // This is a sibcall. The memory operands are available in caller's
2553 // own caller's stack.
2555 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2556 IsTailCallConvention(CallConv))
2557 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2560 if (isTailCall && !IsSibcall) {
2561 // Lower arguments at fp - stackoffset + fpdiff.
2562 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2563 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2565 FPDiff = NumBytesCallerPushed - NumBytes;
2567 // Set the delta of movement of the returnaddr stackslot.
2568 // But only set if delta is greater than previous delta.
2569 if (FPDiff < X86Info->getTCReturnAddrDelta())
2570 X86Info->setTCReturnAddrDelta(FPDiff);
2574 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2577 SDValue RetAddrFrIdx;
2578 // Load return address for tail calls.
2579 if (isTailCall && FPDiff)
2580 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2581 Is64Bit, FPDiff, dl);
2583 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2584 SmallVector<SDValue, 8> MemOpChains;
2587 // Walk the register/memloc assignments, inserting copies/loads. In the case
2588 // of tail call optimization arguments are handle later.
2589 const X86RegisterInfo *RegInfo =
2590 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2591 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2592 CCValAssign &VA = ArgLocs[i];
2593 EVT RegVT = VA.getLocVT();
2594 SDValue Arg = OutVals[i];
2595 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2596 bool isByVal = Flags.isByVal();
2598 // Promote the value if needed.
2599 switch (VA.getLocInfo()) {
2600 default: llvm_unreachable("Unknown loc info!");
2601 case CCValAssign::Full: break;
2602 case CCValAssign::SExt:
2603 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2605 case CCValAssign::ZExt:
2606 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2608 case CCValAssign::AExt:
2609 if (RegVT.is128BitVector()) {
2610 // Special case: passing MMX values in XMM registers.
2611 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2612 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2613 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2615 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2617 case CCValAssign::BCvt:
2618 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2620 case CCValAssign::Indirect: {
2621 // Store the argument.
2622 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2623 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2624 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2625 MachinePointerInfo::getFixedStack(FI),
2632 if (VA.isRegLoc()) {
2633 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2634 if (isVarArg && IsWin64) {
2635 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2636 // shadow reg if callee is a varargs function.
2637 unsigned ShadowReg = 0;
2638 switch (VA.getLocReg()) {
2639 case X86::XMM0: ShadowReg = X86::RCX; break;
2640 case X86::XMM1: ShadowReg = X86::RDX; break;
2641 case X86::XMM2: ShadowReg = X86::R8; break;
2642 case X86::XMM3: ShadowReg = X86::R9; break;
2645 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2647 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2648 assert(VA.isMemLoc());
2649 if (StackPtr.getNode() == 0)
2650 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2652 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2653 dl, DAG, VA, Flags));
2657 if (!MemOpChains.empty())
2658 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2659 &MemOpChains[0], MemOpChains.size());
2661 if (Subtarget->isPICStyleGOT()) {
2662 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2665 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2666 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2668 // If we are tail calling a global or external symbol in GOT pic mode, we
2669 // cannot use a direct jump, since that would make lazy dynamic linking
2670 // impossible (see PR15086). So pretend this is not a tail call, to
2671 // prevent the optimization to a jump.
2672 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2673 if ((G && !G->getGlobal()->hasHiddenVisibility() &&
2674 !G->getGlobal()->hasProtectedVisibility()) ||
2675 isa<ExternalSymbolSDNode>(Callee))
2680 if (Is64Bit && isVarArg && !IsWin64) {
2681 // From AMD64 ABI document:
2682 // For calls that may call functions that use varargs or stdargs
2683 // (prototype-less calls or calls to functions containing ellipsis (...) in
2684 // the declaration) %al is used as hidden argument to specify the number
2685 // of SSE registers used. The contents of %al do not need to match exactly
2686 // the number of registers, but must be an ubound on the number of SSE
2687 // registers used and is in the range 0 - 8 inclusive.
2689 // Count the number of XMM registers allocated.
2690 static const uint16_t XMMArgRegs[] = {
2691 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2692 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2694 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2695 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2696 && "SSE registers cannot be used when SSE is disabled");
2698 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2699 DAG.getConstant(NumXMMRegs, MVT::i8)));
2702 // For tail calls lower the arguments to the 'real' stack slot.
2704 // Force all the incoming stack arguments to be loaded from the stack
2705 // before any new outgoing arguments are stored to the stack, because the
2706 // outgoing stack slots may alias the incoming argument stack slots, and
2707 // the alias isn't otherwise explicit. This is slightly more conservative
2708 // than necessary, because it means that each store effectively depends
2709 // on every argument instead of just those arguments it would clobber.
2710 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2712 SmallVector<SDValue, 8> MemOpChains2;
2715 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2716 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2717 CCValAssign &VA = ArgLocs[i];
2720 assert(VA.isMemLoc());
2721 SDValue Arg = OutVals[i];
2722 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2723 // Create frame index.
2724 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2725 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2726 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2727 FIN = DAG.getFrameIndex(FI, getPointerTy());
2729 if (Flags.isByVal()) {
2730 // Copy relative to framepointer.
2731 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2732 if (StackPtr.getNode() == 0)
2733 StackPtr = DAG.getCopyFromReg(Chain, dl,
2734 RegInfo->getStackRegister(),
2736 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2738 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2742 // Store relative to framepointer.
2743 MemOpChains2.push_back(
2744 DAG.getStore(ArgChain, dl, Arg, FIN,
2745 MachinePointerInfo::getFixedStack(FI),
2751 if (!MemOpChains2.empty())
2752 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2753 &MemOpChains2[0], MemOpChains2.size());
2755 // Store the return address to the appropriate stack slot.
2756 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2757 getPointerTy(), RegInfo->getSlotSize(),
2761 // Build a sequence of copy-to-reg nodes chained together with token chain
2762 // and flag operands which copy the outgoing args into registers.
2764 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2765 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2766 RegsToPass[i].second, InFlag);
2767 InFlag = Chain.getValue(1);
2770 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2771 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2772 // In the 64-bit large code model, we have to make all calls
2773 // through a register, since the call instruction's 32-bit
2774 // pc-relative offset may not be large enough to hold the whole
2776 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2777 // If the callee is a GlobalAddress node (quite common, every direct call
2778 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2781 // We should use extra load for direct calls to dllimported functions in
2783 const GlobalValue *GV = G->getGlobal();
2784 if (!GV->hasDLLImportLinkage()) {
2785 unsigned char OpFlags = 0;
2786 bool ExtraLoad = false;
2787 unsigned WrapperKind = ISD::DELETED_NODE;
2789 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2790 // external symbols most go through the PLT in PIC mode. If the symbol
2791 // has hidden or protected visibility, or if it is static or local, then
2792 // we don't need to use the PLT - we can directly call it.
2793 if (Subtarget->isTargetELF() &&
2794 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2795 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2796 OpFlags = X86II::MO_PLT;
2797 } else if (Subtarget->isPICStyleStubAny() &&
2798 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2799 (!Subtarget->getTargetTriple().isMacOSX() ||
2800 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2801 // PC-relative references to external symbols should go through $stub,
2802 // unless we're building with the leopard linker or later, which
2803 // automatically synthesizes these stubs.
2804 OpFlags = X86II::MO_DARWIN_STUB;
2805 } else if (Subtarget->isPICStyleRIPRel() &&
2806 isa<Function>(GV) &&
2807 cast<Function>(GV)->getAttributes().
2808 hasAttribute(AttributeSet::FunctionIndex,
2809 Attribute::NonLazyBind)) {
2810 // If the function is marked as non-lazy, generate an indirect call
2811 // which loads from the GOT directly. This avoids runtime overhead
2812 // at the cost of eager binding (and one extra byte of encoding).
2813 OpFlags = X86II::MO_GOTPCREL;
2814 WrapperKind = X86ISD::WrapperRIP;
2818 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2819 G->getOffset(), OpFlags);
2821 // Add a wrapper if needed.
2822 if (WrapperKind != ISD::DELETED_NODE)
2823 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2824 // Add extra indirection if needed.
2826 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2827 MachinePointerInfo::getGOT(),
2828 false, false, false, 0);
2830 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2831 unsigned char OpFlags = 0;
2833 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2834 // external symbols should go through the PLT.
2835 if (Subtarget->isTargetELF() &&
2836 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2837 OpFlags = X86II::MO_PLT;
2838 } else if (Subtarget->isPICStyleStubAny() &&
2839 (!Subtarget->getTargetTriple().isMacOSX() ||
2840 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2841 // PC-relative references to external symbols should go through $stub,
2842 // unless we're building with the leopard linker or later, which
2843 // automatically synthesizes these stubs.
2844 OpFlags = X86II::MO_DARWIN_STUB;
2847 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2851 // Returns a chain & a flag for retval copy to use.
2852 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2853 SmallVector<SDValue, 8> Ops;
2855 if (!IsSibcall && isTailCall) {
2856 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2857 DAG.getIntPtrConstant(0, true), InFlag, dl);
2858 InFlag = Chain.getValue(1);
2861 Ops.push_back(Chain);
2862 Ops.push_back(Callee);
2865 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2867 // Add argument registers to the end of the list so that they are known live
2869 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2870 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2871 RegsToPass[i].second.getValueType()));
2873 // Add a register mask operand representing the call-preserved registers.
2874 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2875 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2876 assert(Mask && "Missing call preserved mask for calling convention");
2877 Ops.push_back(DAG.getRegisterMask(Mask));
2879 if (InFlag.getNode())
2880 Ops.push_back(InFlag);
2884 //// If this is the first return lowered for this function, add the regs
2885 //// to the liveout set for the function.
2886 // This isn't right, although it's probably harmless on x86; liveouts
2887 // should be computed from returns not tail calls. Consider a void
2888 // function making a tail call to a function returning int.
2889 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2892 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2893 InFlag = Chain.getValue(1);
2895 // Create the CALLSEQ_END node.
2896 unsigned NumBytesForCalleeToPush;
2897 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2898 getTargetMachine().Options.GuaranteedTailCallOpt))
2899 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2900 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2901 SR == StackStructReturn)
2902 // If this is a call to a struct-return function, the callee
2903 // pops the hidden struct pointer, so we have to push it back.
2904 // This is common for Darwin/X86, Linux & Mingw32 targets.
2905 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2906 NumBytesForCalleeToPush = 4;
2908 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2910 // Returns a flag for retval copy to use.
2912 Chain = DAG.getCALLSEQ_END(Chain,
2913 DAG.getIntPtrConstant(NumBytes, true),
2914 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2917 InFlag = Chain.getValue(1);
2920 // Handle result values, copying them out of physregs into vregs that we
2922 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2923 Ins, dl, DAG, InVals);
2926 //===----------------------------------------------------------------------===//
2927 // Fast Calling Convention (tail call) implementation
2928 //===----------------------------------------------------------------------===//
2930 // Like std call, callee cleans arguments, convention except that ECX is
2931 // reserved for storing the tail called function address. Only 2 registers are
2932 // free for argument passing (inreg). Tail call optimization is performed
2934 // * tailcallopt is enabled
2935 // * caller/callee are fastcc
2936 // On X86_64 architecture with GOT-style position independent code only local
2937 // (within module) calls are supported at the moment.
2938 // To keep the stack aligned according to platform abi the function
2939 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2940 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2941 // If a tail called function callee has more arguments than the caller the
2942 // caller needs to make sure that there is room to move the RETADDR to. This is
2943 // achieved by reserving an area the size of the argument delta right after the
2944 // original REtADDR, but before the saved framepointer or the spilled registers
2945 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2957 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2958 /// for a 16 byte align requirement.
2960 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2961 SelectionDAG& DAG) const {
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 const TargetMachine &TM = MF.getTarget();
2964 const X86RegisterInfo *RegInfo =
2965 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2966 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2967 unsigned StackAlignment = TFI.getStackAlignment();
2968 uint64_t AlignMask = StackAlignment - 1;
2969 int64_t Offset = StackSize;
2970 unsigned SlotSize = RegInfo->getSlotSize();
2971 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2972 // Number smaller than 12 so just add the difference.
2973 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2975 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2976 Offset = ((~AlignMask) & Offset) + StackAlignment +
2977 (StackAlignment-SlotSize);
2982 /// MatchingStackOffset - Return true if the given stack call argument is
2983 /// already available in the same position (relatively) of the caller's
2984 /// incoming argument stack.
2986 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2987 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2988 const X86InstrInfo *TII) {
2989 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2991 if (Arg.getOpcode() == ISD::CopyFromReg) {
2992 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2993 if (!TargetRegisterInfo::isVirtualRegister(VR))
2995 MachineInstr *Def = MRI->getVRegDef(VR);
2998 if (!Flags.isByVal()) {
2999 if (!TII->isLoadFromStackSlot(Def, FI))
3002 unsigned Opcode = Def->getOpcode();
3003 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3004 Def->getOperand(1).isFI()) {
3005 FI = Def->getOperand(1).getIndex();
3006 Bytes = Flags.getByValSize();
3010 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3011 if (Flags.isByVal())
3012 // ByVal argument is passed in as a pointer but it's now being
3013 // dereferenced. e.g.
3014 // define @foo(%struct.X* %A) {
3015 // tail call @bar(%struct.X* byval %A)
3018 SDValue Ptr = Ld->getBasePtr();
3019 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3022 FI = FINode->getIndex();
3023 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3024 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3025 FI = FINode->getIndex();
3026 Bytes = Flags.getByValSize();
3030 assert(FI != INT_MAX);
3031 if (!MFI->isFixedObjectIndex(FI))
3033 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3036 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3037 /// for tail call optimization. Targets which want to do tail call
3038 /// optimization should implement this function.
3040 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3041 CallingConv::ID CalleeCC,
3043 bool isCalleeStructRet,
3044 bool isCallerStructRet,
3046 const SmallVectorImpl<ISD::OutputArg> &Outs,
3047 const SmallVectorImpl<SDValue> &OutVals,
3048 const SmallVectorImpl<ISD::InputArg> &Ins,
3049 SelectionDAG &DAG) const {
3050 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3053 // If -tailcallopt is specified, make fastcc functions tail-callable.
3054 const MachineFunction &MF = DAG.getMachineFunction();
3055 const Function *CallerF = MF.getFunction();
3057 // If the function return type is x86_fp80 and the callee return type is not,
3058 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3059 // perform a tailcall optimization here.
3060 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3063 CallingConv::ID CallerCC = CallerF->getCallingConv();
3064 bool CCMatch = CallerCC == CalleeCC;
3065 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3066 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3068 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3069 if (IsTailCallConvention(CalleeCC) && CCMatch)
3074 // Look for obvious safe cases to perform tail call optimization that do not
3075 // require ABI changes. This is what gcc calls sibcall.
3077 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3078 // emit a special epilogue.
3079 const X86RegisterInfo *RegInfo =
3080 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3081 if (RegInfo->needsStackRealignment(MF))
3084 // Also avoid sibcall optimization if either caller or callee uses struct
3085 // return semantics.
3086 if (isCalleeStructRet || isCallerStructRet)
3089 // An stdcall caller is expected to clean up its arguments; the callee
3090 // isn't going to do that.
3091 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3094 // Do not sibcall optimize vararg calls unless all arguments are passed via
3096 if (isVarArg && !Outs.empty()) {
3098 // Optimizing for varargs on Win64 is unlikely to be safe without
3099 // additional testing.
3100 if (IsCalleeWin64 || IsCallerWin64)
3103 SmallVector<CCValAssign, 16> ArgLocs;
3104 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3105 getTargetMachine(), ArgLocs, *DAG.getContext());
3107 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3108 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3109 if (!ArgLocs[i].isRegLoc())
3113 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3114 // stack. Therefore, if it's not used by the call it is not safe to optimize
3115 // this into a sibcall.
3116 bool Unused = false;
3117 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3124 SmallVector<CCValAssign, 16> RVLocs;
3125 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3126 getTargetMachine(), RVLocs, *DAG.getContext());
3127 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3128 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3129 CCValAssign &VA = RVLocs[i];
3130 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3135 // If the calling conventions do not match, then we'd better make sure the
3136 // results are returned in the same way as what the caller expects.
3138 SmallVector<CCValAssign, 16> RVLocs1;
3139 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3140 getTargetMachine(), RVLocs1, *DAG.getContext());
3141 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3143 SmallVector<CCValAssign, 16> RVLocs2;
3144 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3145 getTargetMachine(), RVLocs2, *DAG.getContext());
3146 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3148 if (RVLocs1.size() != RVLocs2.size())
3150 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3151 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3153 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3155 if (RVLocs1[i].isRegLoc()) {
3156 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3159 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3165 // If the callee takes no arguments then go on to check the results of the
3167 if (!Outs.empty()) {
3168 // Check if stack adjustment is needed. For now, do not do this if any
3169 // argument is passed on the stack.
3170 SmallVector<CCValAssign, 16> ArgLocs;
3171 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3172 getTargetMachine(), ArgLocs, *DAG.getContext());
3174 // Allocate shadow area for Win64
3176 CCInfo.AllocateStack(32, 8);
3178 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3179 if (CCInfo.getNextStackOffset()) {
3180 MachineFunction &MF = DAG.getMachineFunction();
3181 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3184 // Check if the arguments are already laid out in the right way as
3185 // the caller's fixed stack objects.
3186 MachineFrameInfo *MFI = MF.getFrameInfo();
3187 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3188 const X86InstrInfo *TII =
3189 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3190 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3191 CCValAssign &VA = ArgLocs[i];
3192 SDValue Arg = OutVals[i];
3193 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3194 if (VA.getLocInfo() == CCValAssign::Indirect)
3196 if (!VA.isRegLoc()) {
3197 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3204 // If the tailcall address may be in a register, then make sure it's
3205 // possible to register allocate for it. In 32-bit, the call address can
3206 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3207 // callee-saved registers are restored. These happen to be the same
3208 // registers used to pass 'inreg' arguments so watch out for those.
3209 if (!Subtarget->is64Bit() &&
3210 ((!isa<GlobalAddressSDNode>(Callee) &&
3211 !isa<ExternalSymbolSDNode>(Callee)) ||
3212 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3213 unsigned NumInRegs = 0;
3214 // In PIC we need an extra register to formulate the address computation
3216 unsigned MaxInRegs =
3217 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3219 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3220 CCValAssign &VA = ArgLocs[i];
3223 unsigned Reg = VA.getLocReg();
3226 case X86::EAX: case X86::EDX: case X86::ECX:
3227 if (++NumInRegs == MaxInRegs)
3239 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3240 const TargetLibraryInfo *libInfo) const {
3241 return X86::createFastISel(funcInfo, libInfo);
3244 //===----------------------------------------------------------------------===//
3245 // Other Lowering Hooks
3246 //===----------------------------------------------------------------------===//
3248 static bool MayFoldLoad(SDValue Op) {
3249 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3252 static bool MayFoldIntoStore(SDValue Op) {
3253 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3256 static bool isTargetShuffle(unsigned Opcode) {
3258 default: return false;
3259 case X86ISD::PSHUFD:
3260 case X86ISD::PSHUFHW:
3261 case X86ISD::PSHUFLW:
3263 case X86ISD::PALIGNR:
3264 case X86ISD::MOVLHPS:
3265 case X86ISD::MOVLHPD:
3266 case X86ISD::MOVHLPS:
3267 case X86ISD::MOVLPS:
3268 case X86ISD::MOVLPD:
3269 case X86ISD::MOVSHDUP:
3270 case X86ISD::MOVSLDUP:
3271 case X86ISD::MOVDDUP:
3274 case X86ISD::UNPCKL:
3275 case X86ISD::UNPCKH:
3276 case X86ISD::VPERMILP:
3277 case X86ISD::VPERM2X128:
3278 case X86ISD::VPERMI:
3283 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3284 SDValue V1, SelectionDAG &DAG) {
3286 default: llvm_unreachable("Unknown x86 shuffle node");
3287 case X86ISD::MOVSHDUP:
3288 case X86ISD::MOVSLDUP:
3289 case X86ISD::MOVDDUP:
3290 return DAG.getNode(Opc, dl, VT, V1);
3294 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3295 SDValue V1, unsigned TargetMask,
3296 SelectionDAG &DAG) {
3298 default: llvm_unreachable("Unknown x86 shuffle node");
3299 case X86ISD::PSHUFD:
3300 case X86ISD::PSHUFHW:
3301 case X86ISD::PSHUFLW:
3302 case X86ISD::VPERMILP:
3303 case X86ISD::VPERMI:
3304 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3308 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3309 SDValue V1, SDValue V2, unsigned TargetMask,
3310 SelectionDAG &DAG) {
3312 default: llvm_unreachable("Unknown x86 shuffle node");
3313 case X86ISD::PALIGNR:
3315 case X86ISD::VPERM2X128:
3316 return DAG.getNode(Opc, dl, VT, V1, V2,
3317 DAG.getConstant(TargetMask, MVT::i8));
3321 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3322 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3324 default: llvm_unreachable("Unknown x86 shuffle node");
3325 case X86ISD::MOVLHPS:
3326 case X86ISD::MOVLHPD:
3327 case X86ISD::MOVHLPS:
3328 case X86ISD::MOVLPS:
3329 case X86ISD::MOVLPD:
3332 case X86ISD::UNPCKL:
3333 case X86ISD::UNPCKH:
3334 return DAG.getNode(Opc, dl, VT, V1, V2);
3338 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3339 MachineFunction &MF = DAG.getMachineFunction();
3340 const X86RegisterInfo *RegInfo =
3341 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3342 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3343 int ReturnAddrIndex = FuncInfo->getRAIndex();
3345 if (ReturnAddrIndex == 0) {
3346 // Set up a frame object for the return address.
3347 unsigned SlotSize = RegInfo->getSlotSize();
3348 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3351 FuncInfo->setRAIndex(ReturnAddrIndex);
3354 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3357 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3358 bool hasSymbolicDisplacement) {
3359 // Offset should fit into 32 bit immediate field.
3360 if (!isInt<32>(Offset))
3363 // If we don't have a symbolic displacement - we don't have any extra
3365 if (!hasSymbolicDisplacement)
3368 // FIXME: Some tweaks might be needed for medium code model.
3369 if (M != CodeModel::Small && M != CodeModel::Kernel)
3372 // For small code model we assume that latest object is 16MB before end of 31
3373 // bits boundary. We may also accept pretty large negative constants knowing
3374 // that all objects are in the positive half of address space.
3375 if (M == CodeModel::Small && Offset < 16*1024*1024)
3378 // For kernel code model we know that all object resist in the negative half
3379 // of 32bits address space. We may not accept negative offsets, since they may
3380 // be just off and we may accept pretty large positive ones.
3381 if (M == CodeModel::Kernel && Offset > 0)
3387 /// isCalleePop - Determines whether the callee is required to pop its
3388 /// own arguments. Callee pop is necessary to support tail calls.
3389 bool X86::isCalleePop(CallingConv::ID CallingConv,
3390 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3394 switch (CallingConv) {
3397 case CallingConv::X86_StdCall:
3399 case CallingConv::X86_FastCall:
3401 case CallingConv::X86_ThisCall:
3403 case CallingConv::Fast:
3405 case CallingConv::GHC:
3407 case CallingConv::HiPE:
3412 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3413 /// specific condition code, returning the condition code and the LHS/RHS of the
3414 /// comparison to make.
3415 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3416 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3418 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3419 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3420 // X > -1 -> X == 0, jump !sign.
3421 RHS = DAG.getConstant(0, RHS.getValueType());
3422 return X86::COND_NS;
3424 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3425 // X < 0 -> X == 0, jump on sign.
3428 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3430 RHS = DAG.getConstant(0, RHS.getValueType());
3431 return X86::COND_LE;
3435 switch (SetCCOpcode) {
3436 default: llvm_unreachable("Invalid integer condition!");
3437 case ISD::SETEQ: return X86::COND_E;
3438 case ISD::SETGT: return X86::COND_G;
3439 case ISD::SETGE: return X86::COND_GE;
3440 case ISD::SETLT: return X86::COND_L;
3441 case ISD::SETLE: return X86::COND_LE;
3442 case ISD::SETNE: return X86::COND_NE;
3443 case ISD::SETULT: return X86::COND_B;
3444 case ISD::SETUGT: return X86::COND_A;
3445 case ISD::SETULE: return X86::COND_BE;
3446 case ISD::SETUGE: return X86::COND_AE;
3450 // First determine if it is required or is profitable to flip the operands.
3452 // If LHS is a foldable load, but RHS is not, flip the condition.
3453 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3454 !ISD::isNON_EXTLoad(RHS.getNode())) {
3455 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3456 std::swap(LHS, RHS);
3459 switch (SetCCOpcode) {
3465 std::swap(LHS, RHS);
3469 // On a floating point condition, the flags are set as follows:
3471 // 0 | 0 | 0 | X > Y
3472 // 0 | 0 | 1 | X < Y
3473 // 1 | 0 | 0 | X == Y
3474 // 1 | 1 | 1 | unordered
3475 switch (SetCCOpcode) {
3476 default: llvm_unreachable("Condcode should be pre-legalized away");
3478 case ISD::SETEQ: return X86::COND_E;
3479 case ISD::SETOLT: // flipped
3481 case ISD::SETGT: return X86::COND_A;
3482 case ISD::SETOLE: // flipped
3484 case ISD::SETGE: return X86::COND_AE;
3485 case ISD::SETUGT: // flipped
3487 case ISD::SETLT: return X86::COND_B;
3488 case ISD::SETUGE: // flipped
3490 case ISD::SETLE: return X86::COND_BE;
3492 case ISD::SETNE: return X86::COND_NE;
3493 case ISD::SETUO: return X86::COND_P;
3494 case ISD::SETO: return X86::COND_NP;
3496 case ISD::SETUNE: return X86::COND_INVALID;
3500 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3501 /// code. Current x86 isa includes the following FP cmov instructions:
3502 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3503 static bool hasFPCMov(unsigned X86CC) {
3519 /// isFPImmLegal - Returns true if the target can instruction select the
3520 /// specified FP immediate natively. If false, the legalizer will
3521 /// materialize the FP immediate as a load from a constant pool.
3522 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3523 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3524 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3530 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3531 /// the specified range (L, H].
3532 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3533 return (Val < 0) || (Val >= Low && Val < Hi);
3536 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3537 /// specified value.
3538 static bool isUndefOrEqual(int Val, int CmpVal) {
3539 return (Val < 0 || Val == CmpVal);
3542 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3543 /// from position Pos and ending in Pos+Size, falls within the specified
3544 /// sequential range (L, L+Pos]. or is undef.
3545 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3546 unsigned Pos, unsigned Size, int Low) {
3547 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3548 if (!isUndefOrEqual(Mask[i], Low))
3553 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3554 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3555 /// the second operand.
3556 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3557 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3558 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3559 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3560 return (Mask[0] < 2 && Mask[1] < 2);
3564 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3565 /// is suitable for input to PSHUFHW.
3566 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3567 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3570 // Lower quadword copied in order or undef.
3571 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3574 // Upper quadword shuffled.
3575 for (unsigned i = 4; i != 8; ++i)
3576 if (!isUndefOrInRange(Mask[i], 4, 8))
3579 if (VT == MVT::v16i16) {
3580 // Lower quadword copied in order or undef.
3581 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3584 // Upper quadword shuffled.
3585 for (unsigned i = 12; i != 16; ++i)
3586 if (!isUndefOrInRange(Mask[i], 12, 16))
3593 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3594 /// is suitable for input to PSHUFLW.
3595 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3596 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3599 // Upper quadword copied in order.
3600 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3603 // Lower quadword shuffled.
3604 for (unsigned i = 0; i != 4; ++i)
3605 if (!isUndefOrInRange(Mask[i], 0, 4))
3608 if (VT == MVT::v16i16) {
3609 // Upper quadword copied in order.
3610 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3613 // Lower quadword shuffled.
3614 for (unsigned i = 8; i != 12; ++i)
3615 if (!isUndefOrInRange(Mask[i], 8, 12))
3622 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3623 /// is suitable for input to PALIGNR.
3624 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3625 const X86Subtarget *Subtarget) {
3626 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3627 (VT.is256BitVector() && !Subtarget->hasInt256()))
3630 unsigned NumElts = VT.getVectorNumElements();
3631 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3632 unsigned NumLaneElts = NumElts/NumLanes;
3634 // Do not handle 64-bit element shuffles with palignr.
3635 if (NumLaneElts == 2)
3638 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3640 for (i = 0; i != NumLaneElts; ++i) {
3645 // Lane is all undef, go to next lane
3646 if (i == NumLaneElts)
3649 int Start = Mask[i+l];
3651 // Make sure its in this lane in one of the sources
3652 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3653 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3656 // If not lane 0, then we must match lane 0
3657 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3660 // Correct second source to be contiguous with first source
3661 if (Start >= (int)NumElts)
3662 Start -= NumElts - NumLaneElts;
3664 // Make sure we're shifting in the right direction.
3665 if (Start <= (int)(i+l))
3670 // Check the rest of the elements to see if they are consecutive.
3671 for (++i; i != NumLaneElts; ++i) {
3672 int Idx = Mask[i+l];
3674 // Make sure its in this lane
3675 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3676 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3679 // If not lane 0, then we must match lane 0
3680 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3683 if (Idx >= (int)NumElts)
3684 Idx -= NumElts - NumLaneElts;
3686 if (!isUndefOrEqual(Idx, Start+i))
3695 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3696 /// the two vector operands have swapped position.
3697 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3698 unsigned NumElems) {
3699 for (unsigned i = 0; i != NumElems; ++i) {
3703 else if (idx < (int)NumElems)
3704 Mask[i] = idx + NumElems;
3706 Mask[i] = idx - NumElems;
3710 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3711 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3712 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3713 /// reverse of what x86 shuffles want.
3714 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3716 unsigned NumElems = VT.getVectorNumElements();
3717 unsigned NumLanes = VT.getSizeInBits()/128;
3718 unsigned NumLaneElems = NumElems/NumLanes;
3720 if (NumLaneElems != 2 && NumLaneElems != 4)
3723 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3724 bool symetricMaskRequired =
3725 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3727 // VSHUFPSY divides the resulting vector into 4 chunks.
3728 // The sources are also splitted into 4 chunks, and each destination
3729 // chunk must come from a different source chunk.
3731 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3732 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3734 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3735 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3737 // VSHUFPDY divides the resulting vector into 4 chunks.
3738 // The sources are also splitted into 4 chunks, and each destination
3739 // chunk must come from a different source chunk.
3741 // SRC1 => X3 X2 X1 X0
3742 // SRC2 => Y3 Y2 Y1 Y0
3744 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3746 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3747 unsigned HalfLaneElems = NumLaneElems/2;
3748 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3749 for (unsigned i = 0; i != NumLaneElems; ++i) {
3750 int Idx = Mask[i+l];
3751 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3752 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3754 // For VSHUFPSY, the mask of the second half must be the same as the
3755 // first but with the appropriate offsets. This works in the same way as
3756 // VPERMILPS works with masks.
3757 if (!symetricMaskRequired || Idx < 0)
3759 if (MaskVal[i] < 0) {
3760 MaskVal[i] = Idx - l;
3763 if ((signed)(Idx - l) != MaskVal[i])
3771 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3772 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3773 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3774 if (!VT.is128BitVector())
3777 unsigned NumElems = VT.getVectorNumElements();
3782 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3783 return isUndefOrEqual(Mask[0], 6) &&
3784 isUndefOrEqual(Mask[1], 7) &&
3785 isUndefOrEqual(Mask[2], 2) &&
3786 isUndefOrEqual(Mask[3], 3);
3789 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3790 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3792 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3793 if (!VT.is128BitVector())
3796 unsigned NumElems = VT.getVectorNumElements();
3801 return isUndefOrEqual(Mask[0], 2) &&
3802 isUndefOrEqual(Mask[1], 3) &&
3803 isUndefOrEqual(Mask[2], 2) &&
3804 isUndefOrEqual(Mask[3], 3);
3807 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3808 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3809 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3810 if (!VT.is128BitVector())
3813 unsigned NumElems = VT.getVectorNumElements();
3815 if (NumElems != 2 && NumElems != 4)
3818 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3819 if (!isUndefOrEqual(Mask[i], i + NumElems))
3822 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3823 if (!isUndefOrEqual(Mask[i], i))
3829 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3830 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3831 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3832 if (!VT.is128BitVector())
3835 unsigned NumElems = VT.getVectorNumElements();
3837 if (NumElems != 2 && NumElems != 4)
3840 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3841 if (!isUndefOrEqual(Mask[i], i))
3844 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3845 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3852 // Some special combinations that can be optimized.
3855 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3856 SelectionDAG &DAG) {
3857 MVT VT = SVOp->getSimpleValueType(0);
3860 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3863 ArrayRef<int> Mask = SVOp->getMask();
3865 // These are the special masks that may be optimized.
3866 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3867 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3868 bool MatchEvenMask = true;
3869 bool MatchOddMask = true;
3870 for (int i=0; i<8; ++i) {
3871 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3872 MatchEvenMask = false;
3873 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3874 MatchOddMask = false;
3877 if (!MatchEvenMask && !MatchOddMask)
3880 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3882 SDValue Op0 = SVOp->getOperand(0);
3883 SDValue Op1 = SVOp->getOperand(1);
3885 if (MatchEvenMask) {
3886 // Shift the second operand right to 32 bits.
3887 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3888 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3890 // Shift the first operand left to 32 bits.
3891 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3892 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3894 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3895 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3898 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3899 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3900 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3901 bool HasInt256, bool V2IsSplat = false) {
3903 assert(VT.getSizeInBits() >= 128 &&
3904 "Unsupported vector type for unpckl");
3906 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3908 unsigned NumOf256BitLanes;
3909 unsigned NumElts = VT.getVectorNumElements();
3910 if (VT.is256BitVector()) {
3911 if (NumElts != 4 && NumElts != 8 &&
3912 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3915 NumOf256BitLanes = 1;
3916 } else if (VT.is512BitVector()) {
3917 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3918 "Unsupported vector type for unpckh");
3920 NumOf256BitLanes = 2;
3923 NumOf256BitLanes = 1;
3926 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3927 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3929 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3930 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3931 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3932 int BitI = Mask[l256*NumEltsInStride+l+i];
3933 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3934 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3936 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3938 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3946 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3947 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3948 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3949 bool HasInt256, bool V2IsSplat = false) {
3950 assert(VT.getSizeInBits() >= 128 &&
3951 "Unsupported vector type for unpckh");
3953 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3955 unsigned NumOf256BitLanes;
3956 unsigned NumElts = VT.getVectorNumElements();
3957 if (VT.is256BitVector()) {
3958 if (NumElts != 4 && NumElts != 8 &&
3959 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3962 NumOf256BitLanes = 1;
3963 } else if (VT.is512BitVector()) {
3964 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3965 "Unsupported vector type for unpckh");
3967 NumOf256BitLanes = 2;
3970 NumOf256BitLanes = 1;
3973 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3974 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3976 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3977 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3978 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3979 int BitI = Mask[l256*NumEltsInStride+l+i];
3980 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3981 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3983 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3985 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3993 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3994 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3996 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3997 unsigned NumElts = VT.getVectorNumElements();
3998 bool Is256BitVec = VT.is256BitVector();
4000 if (VT.is512BitVector())
4002 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4003 "Unsupported vector type for unpckh");
4005 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4006 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4009 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4010 // FIXME: Need a better way to get rid of this, there's no latency difference
4011 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4012 // the former later. We should also remove the "_undef" special mask.
4013 if (NumElts == 4 && Is256BitVec)
4016 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4017 // independently on 128-bit lanes.
4018 unsigned NumLanes = VT.getSizeInBits()/128;
4019 unsigned NumLaneElts = NumElts/NumLanes;
4021 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4022 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4023 int BitI = Mask[l+i];
4024 int BitI1 = Mask[l+i+1];
4026 if (!isUndefOrEqual(BitI, j))
4028 if (!isUndefOrEqual(BitI1, j))
4036 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4037 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4039 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4040 unsigned NumElts = VT.getVectorNumElements();
4042 if (VT.is512BitVector())
4045 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4046 "Unsupported vector type for unpckh");
4048 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4049 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4052 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4053 // independently on 128-bit lanes.
4054 unsigned NumLanes = VT.getSizeInBits()/128;
4055 unsigned NumLaneElts = NumElts/NumLanes;
4057 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4058 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4059 int BitI = Mask[l+i];
4060 int BitI1 = Mask[l+i+1];
4061 if (!isUndefOrEqual(BitI, j))
4063 if (!isUndefOrEqual(BitI1, j))
4070 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4071 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4072 /// MOVSD, and MOVD, i.e. setting the lowest element.
4073 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4074 if (VT.getVectorElementType().getSizeInBits() < 32)
4076 if (!VT.is128BitVector())
4079 unsigned NumElts = VT.getVectorNumElements();
4081 if (!isUndefOrEqual(Mask[0], NumElts))
4084 for (unsigned i = 1; i != NumElts; ++i)
4085 if (!isUndefOrEqual(Mask[i], i))
4091 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4092 /// as permutations between 128-bit chunks or halves. As an example: this
4094 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4095 /// The first half comes from the second half of V1 and the second half from the
4096 /// the second half of V2.
4097 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4098 if (!HasFp256 || !VT.is256BitVector())
4101 // The shuffle result is divided into half A and half B. In total the two
4102 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4103 // B must come from C, D, E or F.
4104 unsigned HalfSize = VT.getVectorNumElements()/2;
4105 bool MatchA = false, MatchB = false;
4107 // Check if A comes from one of C, D, E, F.
4108 for (unsigned Half = 0; Half != 4; ++Half) {
4109 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4115 // Check if B comes from one of C, D, E, F.
4116 for (unsigned Half = 0; Half != 4; ++Half) {
4117 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4123 return MatchA && MatchB;
4126 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4127 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4128 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4129 MVT VT = SVOp->getSimpleValueType(0);
4131 unsigned HalfSize = VT.getVectorNumElements()/2;
4133 unsigned FstHalf = 0, SndHalf = 0;
4134 for (unsigned i = 0; i < HalfSize; ++i) {
4135 if (SVOp->getMaskElt(i) > 0) {
4136 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4140 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4141 if (SVOp->getMaskElt(i) > 0) {
4142 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4147 return (FstHalf | (SndHalf << 4));
4150 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4151 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4152 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4156 unsigned NumElts = VT.getVectorNumElements();
4158 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4159 for (unsigned i = 0; i != NumElts; ++i) {
4162 Imm8 |= Mask[i] << (i*2);
4167 unsigned LaneSize = 4;
4168 SmallVector<int, 4> MaskVal(LaneSize, -1);
4170 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4171 for (unsigned i = 0; i != LaneSize; ++i) {
4172 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4176 if (MaskVal[i] < 0) {
4177 MaskVal[i] = Mask[i+l] - l;
4178 Imm8 |= MaskVal[i] << (i*2);
4181 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4188 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4189 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4190 /// Note that VPERMIL mask matching is different depending whether theunderlying
4191 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4192 /// to the same elements of the low, but to the higher half of the source.
4193 /// In VPERMILPD the two lanes could be shuffled independently of each other
4194 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4195 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4196 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4197 if (VT.getSizeInBits() < 256 || EltSize < 32)
4199 bool symetricMaskRequired = (EltSize == 32);
4200 unsigned NumElts = VT.getVectorNumElements();
4202 unsigned NumLanes = VT.getSizeInBits()/128;
4203 unsigned LaneSize = NumElts/NumLanes;
4204 // 2 or 4 elements in one lane
4206 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4207 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4208 for (unsigned i = 0; i != LaneSize; ++i) {
4209 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4211 if (symetricMaskRequired) {
4212 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4213 ExpectedMaskVal[i] = Mask[i+l] - l;
4216 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4224 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4225 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4226 /// element of vector 2 and the other elements to come from vector 1 in order.
4227 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4228 bool V2IsSplat = false, bool V2IsUndef = false) {
4229 if (!VT.is128BitVector())
4232 unsigned NumOps = VT.getVectorNumElements();
4233 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4236 if (!isUndefOrEqual(Mask[0], 0))
4239 for (unsigned i = 1; i != NumOps; ++i)
4240 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4241 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4242 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4248 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4249 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4250 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4251 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4252 const X86Subtarget *Subtarget) {
4253 if (!Subtarget->hasSSE3())
4256 unsigned NumElems = VT.getVectorNumElements();
4258 if ((VT.is128BitVector() && NumElems != 4) ||
4259 (VT.is256BitVector() && NumElems != 8) ||
4260 (VT.is512BitVector() && NumElems != 16))
4263 // "i+1" is the value the indexed mask element must have
4264 for (unsigned i = 0; i != NumElems; i += 2)
4265 if (!isUndefOrEqual(Mask[i], i+1) ||
4266 !isUndefOrEqual(Mask[i+1], i+1))
4272 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4273 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4274 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4275 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4276 const X86Subtarget *Subtarget) {
4277 if (!Subtarget->hasSSE3())
4280 unsigned NumElems = VT.getVectorNumElements();
4282 if ((VT.is128BitVector() && NumElems != 4) ||
4283 (VT.is256BitVector() && NumElems != 8) ||
4284 (VT.is512BitVector() && NumElems != 16))
4287 // "i" is the value the indexed mask element must have
4288 for (unsigned i = 0; i != NumElems; i += 2)
4289 if (!isUndefOrEqual(Mask[i], i) ||
4290 !isUndefOrEqual(Mask[i+1], i))
4296 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4297 /// specifies a shuffle of elements that is suitable for input to 256-bit
4298 /// version of MOVDDUP.
4299 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4300 if (!HasFp256 || !VT.is256BitVector())
4303 unsigned NumElts = VT.getVectorNumElements();
4307 for (unsigned i = 0; i != NumElts/2; ++i)
4308 if (!isUndefOrEqual(Mask[i], 0))
4310 for (unsigned i = NumElts/2; i != NumElts; ++i)
4311 if (!isUndefOrEqual(Mask[i], NumElts/2))
4316 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4317 /// specifies a shuffle of elements that is suitable for input to 128-bit
4318 /// version of MOVDDUP.
4319 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4320 if (!VT.is128BitVector())
4323 unsigned e = VT.getVectorNumElements() / 2;
4324 for (unsigned i = 0; i != e; ++i)
4325 if (!isUndefOrEqual(Mask[i], i))
4327 for (unsigned i = 0; i != e; ++i)
4328 if (!isUndefOrEqual(Mask[e+i], i))
4333 /// isVEXTRACTIndex - Return true if the specified
4334 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4335 /// suitable for instruction that extract 128 or 256 bit vectors
4336 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4337 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4338 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4341 // The index should be aligned on a vecWidth-bit boundary.
4343 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4345 MVT VT = N->getSimpleValueType(0);
4346 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4347 bool Result = (Index * ElSize) % vecWidth == 0;
4352 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4353 /// operand specifies a subvector insert that is suitable for input to
4354 /// insertion of 128 or 256-bit subvectors
4355 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4356 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4357 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4359 // The index should be aligned on a vecWidth-bit boundary.
4361 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4363 MVT VT = N->getSimpleValueType(0);
4364 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4365 bool Result = (Index * ElSize) % vecWidth == 0;
4370 bool X86::isVINSERT128Index(SDNode *N) {
4371 return isVINSERTIndex(N, 128);
4374 bool X86::isVINSERT256Index(SDNode *N) {
4375 return isVINSERTIndex(N, 256);
4378 bool X86::isVEXTRACT128Index(SDNode *N) {
4379 return isVEXTRACTIndex(N, 128);
4382 bool X86::isVEXTRACT256Index(SDNode *N) {
4383 return isVEXTRACTIndex(N, 256);
4386 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4387 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4388 /// Handles 128-bit and 256-bit.
4389 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4390 MVT VT = N->getSimpleValueType(0);
4392 assert((VT.getSizeInBits() >= 128) &&
4393 "Unsupported vector type for PSHUF/SHUFP");
4395 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumElts = VT.getVectorNumElements();
4398 unsigned NumLanes = VT.getSizeInBits()/128;
4399 unsigned NumLaneElts = NumElts/NumLanes;
4401 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4402 "Only supports 2, 4 or 8 elements per lane");
4404 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4406 for (unsigned i = 0; i != NumElts; ++i) {
4407 int Elt = N->getMaskElt(i);
4408 if (Elt < 0) continue;
4409 Elt &= NumLaneElts - 1;
4410 unsigned ShAmt = (i << Shift) % 8;
4411 Mask |= Elt << ShAmt;
4417 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4418 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4419 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4420 MVT VT = N->getSimpleValueType(0);
4422 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4423 "Unsupported vector type for PSHUFHW");
4425 unsigned NumElts = VT.getVectorNumElements();
4428 for (unsigned l = 0; l != NumElts; l += 8) {
4429 // 8 nodes per lane, but we only care about the last 4.
4430 for (unsigned i = 0; i < 4; ++i) {
4431 int Elt = N->getMaskElt(l+i+4);
4432 if (Elt < 0) continue;
4433 Elt &= 0x3; // only 2-bits.
4434 Mask |= Elt << (i * 2);
4441 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4442 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4443 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4444 MVT VT = N->getSimpleValueType(0);
4446 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4447 "Unsupported vector type for PSHUFHW");
4449 unsigned NumElts = VT.getVectorNumElements();
4452 for (unsigned l = 0; l != NumElts; l += 8) {
4453 // 8 nodes per lane, but we only care about the first 4.
4454 for (unsigned i = 0; i < 4; ++i) {
4455 int Elt = N->getMaskElt(l+i);
4456 if (Elt < 0) continue;
4457 Elt &= 0x3; // only 2-bits
4458 Mask |= Elt << (i * 2);
4465 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4466 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4467 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4468 MVT VT = SVOp->getSimpleValueType(0);
4469 unsigned EltSize = VT.is512BitVector() ? 1 :
4470 VT.getVectorElementType().getSizeInBits() >> 3;
4472 unsigned NumElts = VT.getVectorNumElements();
4473 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4474 unsigned NumLaneElts = NumElts/NumLanes;
4478 for (i = 0; i != NumElts; ++i) {
4479 Val = SVOp->getMaskElt(i);
4483 if (Val >= (int)NumElts)
4484 Val -= NumElts - NumLaneElts;
4486 assert(Val - i > 0 && "PALIGNR imm should be positive");
4487 return (Val - i) * EltSize;
4490 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4491 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4492 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4493 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4496 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4498 MVT VecVT = N->getOperand(0).getSimpleValueType();
4499 MVT ElVT = VecVT.getVectorElementType();
4501 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4502 return Index / NumElemsPerChunk;
4505 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4506 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4507 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4508 llvm_unreachable("Illegal insert subvector for VINSERT");
4511 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4513 MVT VecVT = N->getSimpleValueType(0);
4514 MVT ElVT = VecVT.getVectorElementType();
4516 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4517 return Index / NumElemsPerChunk;
4520 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4521 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4522 /// and VINSERTI128 instructions.
4523 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4524 return getExtractVEXTRACTImmediate(N, 128);
4527 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4528 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4529 /// and VINSERTI64x4 instructions.
4530 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4531 return getExtractVEXTRACTImmediate(N, 256);
4534 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4535 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4536 /// and VINSERTI128 instructions.
4537 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4538 return getInsertVINSERTImmediate(N, 128);
4541 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4542 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4543 /// and VINSERTI64x4 instructions.
4544 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4545 return getInsertVINSERTImmediate(N, 256);
4548 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4550 bool X86::isZeroNode(SDValue Elt) {
4551 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4552 return CN->isNullValue();
4553 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4554 return CFP->getValueAPF().isPosZero();
4558 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4559 /// their permute mask.
4560 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4561 SelectionDAG &DAG) {
4562 MVT VT = SVOp->getSimpleValueType(0);
4563 unsigned NumElems = VT.getVectorNumElements();
4564 SmallVector<int, 8> MaskVec;
4566 for (unsigned i = 0; i != NumElems; ++i) {
4567 int Idx = SVOp->getMaskElt(i);
4569 if (Idx < (int)NumElems)
4574 MaskVec.push_back(Idx);
4576 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4577 SVOp->getOperand(0), &MaskVec[0]);
4580 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4581 /// match movhlps. The lower half elements should come from upper half of
4582 /// V1 (and in order), and the upper half elements should come from the upper
4583 /// half of V2 (and in order).
4584 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4585 if (!VT.is128BitVector())
4587 if (VT.getVectorNumElements() != 4)
4589 for (unsigned i = 0, e = 2; i != e; ++i)
4590 if (!isUndefOrEqual(Mask[i], i+2))
4592 for (unsigned i = 2; i != 4; ++i)
4593 if (!isUndefOrEqual(Mask[i], i+4))
4598 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4599 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4601 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4602 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4604 N = N->getOperand(0).getNode();
4605 if (!ISD::isNON_EXTLoad(N))
4608 *LD = cast<LoadSDNode>(N);
4612 // Test whether the given value is a vector value which will be legalized
4614 static bool WillBeConstantPoolLoad(SDNode *N) {
4615 if (N->getOpcode() != ISD::BUILD_VECTOR)
4618 // Check for any non-constant elements.
4619 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4620 switch (N->getOperand(i).getNode()->getOpcode()) {
4622 case ISD::ConstantFP:
4629 // Vectors of all-zeros and all-ones are materialized with special
4630 // instructions rather than being loaded.
4631 return !ISD::isBuildVectorAllZeros(N) &&
4632 !ISD::isBuildVectorAllOnes(N);
4635 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4636 /// match movlp{s|d}. The lower half elements should come from lower half of
4637 /// V1 (and in order), and the upper half elements should come from the upper
4638 /// half of V2 (and in order). And since V1 will become the source of the
4639 /// MOVLP, it must be either a vector load or a scalar load to vector.
4640 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4641 ArrayRef<int> Mask, MVT VT) {
4642 if (!VT.is128BitVector())
4645 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4647 // Is V2 is a vector load, don't do this transformation. We will try to use
4648 // load folding shufps op.
4649 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4652 unsigned NumElems = VT.getVectorNumElements();
4654 if (NumElems != 2 && NumElems != 4)
4656 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4657 if (!isUndefOrEqual(Mask[i], i))
4659 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4660 if (!isUndefOrEqual(Mask[i], i+NumElems))
4665 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4667 static bool isSplatVector(SDNode *N) {
4668 if (N->getOpcode() != ISD::BUILD_VECTOR)
4671 SDValue SplatValue = N->getOperand(0);
4672 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4673 if (N->getOperand(i) != SplatValue)
4678 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4679 /// to an zero vector.
4680 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4681 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4682 SDValue V1 = N->getOperand(0);
4683 SDValue V2 = N->getOperand(1);
4684 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4685 for (unsigned i = 0; i != NumElems; ++i) {
4686 int Idx = N->getMaskElt(i);
4687 if (Idx >= (int)NumElems) {
4688 unsigned Opc = V2.getOpcode();
4689 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4691 if (Opc != ISD::BUILD_VECTOR ||
4692 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4694 } else if (Idx >= 0) {
4695 unsigned Opc = V1.getOpcode();
4696 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4698 if (Opc != ISD::BUILD_VECTOR ||
4699 !X86::isZeroNode(V1.getOperand(Idx)))
4706 /// getZeroVector - Returns a vector of specified type with all zero elements.
4708 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4709 SelectionDAG &DAG, SDLoc dl) {
4710 assert(VT.isVector() && "Expected a vector type");
4712 // Always build SSE zero vectors as <4 x i32> bitcasted
4713 // to their dest type. This ensures they get CSE'd.
4715 if (VT.is128BitVector()) { // SSE
4716 if (Subtarget->hasSSE2()) { // SSE2
4717 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4718 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4720 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4721 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4723 } else if (VT.is256BitVector()) { // AVX
4724 if (Subtarget->hasInt256()) { // AVX2
4725 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4726 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4727 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4728 array_lengthof(Ops));
4730 // 256-bit logic and arithmetic instructions in AVX are all
4731 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4732 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4733 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4734 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4735 array_lengthof(Ops));
4737 } else if (VT.is512BitVector()) { // AVX-512
4738 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4739 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4740 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4741 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4743 llvm_unreachable("Unexpected vector type");
4745 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4748 /// getOnesVector - Returns a vector of specified type with all bits set.
4749 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4750 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4751 /// Then bitcast to their original type, ensuring they get CSE'd.
4752 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4754 assert(VT.isVector() && "Expected a vector type");
4756 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4758 if (VT.is256BitVector()) {
4759 if (HasInt256) { // AVX2
4760 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4761 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4762 array_lengthof(Ops));
4764 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4765 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4767 } else if (VT.is128BitVector()) {
4768 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4770 llvm_unreachable("Unexpected vector type");
4772 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4775 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4776 /// that point to V2 points to its first element.
4777 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4778 for (unsigned i = 0; i != NumElems; ++i) {
4779 if (Mask[i] > (int)NumElems) {
4785 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4786 /// operation of specified width.
4787 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4789 unsigned NumElems = VT.getVectorNumElements();
4790 SmallVector<int, 8> Mask;
4791 Mask.push_back(NumElems);
4792 for (unsigned i = 1; i != NumElems; ++i)
4794 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4797 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4798 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4800 unsigned NumElems = VT.getVectorNumElements();
4801 SmallVector<int, 8> Mask;
4802 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4804 Mask.push_back(i + NumElems);
4806 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4809 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4810 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4812 unsigned NumElems = VT.getVectorNumElements();
4813 SmallVector<int, 8> Mask;
4814 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4815 Mask.push_back(i + Half);
4816 Mask.push_back(i + NumElems + Half);
4818 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4821 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4822 // a generic shuffle instruction because the target has no such instructions.
4823 // Generate shuffles which repeat i16 and i8 several times until they can be
4824 // represented by v4f32 and then be manipulated by target suported shuffles.
4825 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4826 MVT VT = V.getSimpleValueType();
4827 int NumElems = VT.getVectorNumElements();
4830 while (NumElems > 4) {
4831 if (EltNo < NumElems/2) {
4832 V = getUnpackl(DAG, dl, VT, V, V);
4834 V = getUnpackh(DAG, dl, VT, V, V);
4835 EltNo -= NumElems/2;
4842 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4843 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4844 MVT VT = V.getSimpleValueType();
4847 if (VT.is128BitVector()) {
4848 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4849 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4850 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4852 } else if (VT.is256BitVector()) {
4853 // To use VPERMILPS to splat scalars, the second half of indicies must
4854 // refer to the higher part, which is a duplication of the lower one,
4855 // because VPERMILPS can only handle in-lane permutations.
4856 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4857 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4859 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4860 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4863 llvm_unreachable("Vector size not supported");
4865 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4868 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4869 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4870 MVT SrcVT = SV->getSimpleValueType(0);
4871 SDValue V1 = SV->getOperand(0);
4874 int EltNo = SV->getSplatIndex();
4875 int NumElems = SrcVT.getVectorNumElements();
4876 bool Is256BitVec = SrcVT.is256BitVector();
4878 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4879 "Unknown how to promote splat for type");
4881 // Extract the 128-bit part containing the splat element and update
4882 // the splat element index when it refers to the higher register.
4884 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4885 if (EltNo >= NumElems/2)
4886 EltNo -= NumElems/2;
4889 // All i16 and i8 vector types can't be used directly by a generic shuffle
4890 // instruction because the target has no such instruction. Generate shuffles
4891 // which repeat i16 and i8 several times until they fit in i32, and then can
4892 // be manipulated by target suported shuffles.
4893 MVT EltVT = SrcVT.getVectorElementType();
4894 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4895 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4897 // Recreate the 256-bit vector and place the same 128-bit vector
4898 // into the low and high part. This is necessary because we want
4899 // to use VPERM* to shuffle the vectors
4901 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4904 return getLegalSplat(DAG, V1, EltNo);
4907 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4908 /// vector of zero or undef vector. This produces a shuffle where the low
4909 /// element of V2 is swizzled into the zero/undef vector, landing at element
4910 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4911 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4913 const X86Subtarget *Subtarget,
4914 SelectionDAG &DAG) {
4915 MVT VT = V2.getSimpleValueType();
4917 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4918 unsigned NumElems = VT.getVectorNumElements();
4919 SmallVector<int, 16> MaskVec;
4920 for (unsigned i = 0; i != NumElems; ++i)
4921 // If this is the insertion idx, put the low elt of V2 here.
4922 MaskVec.push_back(i == Idx ? NumElems : i);
4923 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4926 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4927 /// target specific opcode. Returns true if the Mask could be calculated.
4928 /// Sets IsUnary to true if only uses one source.
4929 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4930 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4931 unsigned NumElems = VT.getVectorNumElements();
4935 switch(N->getOpcode()) {
4937 ImmN = N->getOperand(N->getNumOperands()-1);
4938 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4940 case X86ISD::UNPCKH:
4941 DecodeUNPCKHMask(VT, Mask);
4943 case X86ISD::UNPCKL:
4944 DecodeUNPCKLMask(VT, Mask);
4946 case X86ISD::MOVHLPS:
4947 DecodeMOVHLPSMask(NumElems, Mask);
4949 case X86ISD::MOVLHPS:
4950 DecodeMOVLHPSMask(NumElems, Mask);
4952 case X86ISD::PALIGNR:
4953 ImmN = N->getOperand(N->getNumOperands()-1);
4954 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4956 case X86ISD::PSHUFD:
4957 case X86ISD::VPERMILP:
4958 ImmN = N->getOperand(N->getNumOperands()-1);
4959 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4962 case X86ISD::PSHUFHW:
4963 ImmN = N->getOperand(N->getNumOperands()-1);
4964 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4967 case X86ISD::PSHUFLW:
4968 ImmN = N->getOperand(N->getNumOperands()-1);
4969 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4972 case X86ISD::VPERMI:
4973 ImmN = N->getOperand(N->getNumOperands()-1);
4974 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4978 case X86ISD::MOVSD: {
4979 // The index 0 always comes from the first element of the second source,
4980 // this is why MOVSS and MOVSD are used in the first place. The other
4981 // elements come from the other positions of the first source vector
4982 Mask.push_back(NumElems);
4983 for (unsigned i = 1; i != NumElems; ++i) {
4988 case X86ISD::VPERM2X128:
4989 ImmN = N->getOperand(N->getNumOperands()-1);
4990 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4991 if (Mask.empty()) return false;
4993 case X86ISD::MOVDDUP:
4994 case X86ISD::MOVLHPD:
4995 case X86ISD::MOVLPD:
4996 case X86ISD::MOVLPS:
4997 case X86ISD::MOVSHDUP:
4998 case X86ISD::MOVSLDUP:
4999 // Not yet implemented
5001 default: llvm_unreachable("unknown target shuffle node");
5007 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5008 /// element of the result of the vector shuffle.
5009 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5012 return SDValue(); // Limit search depth.
5014 SDValue V = SDValue(N, 0);
5015 EVT VT = V.getValueType();
5016 unsigned Opcode = V.getOpcode();
5018 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5019 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5020 int Elt = SV->getMaskElt(Index);
5023 return DAG.getUNDEF(VT.getVectorElementType());
5025 unsigned NumElems = VT.getVectorNumElements();
5026 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5027 : SV->getOperand(1);
5028 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5031 // Recurse into target specific vector shuffles to find scalars.
5032 if (isTargetShuffle(Opcode)) {
5033 MVT ShufVT = V.getSimpleValueType();
5034 unsigned NumElems = ShufVT.getVectorNumElements();
5035 SmallVector<int, 16> ShuffleMask;
5038 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5041 int Elt = ShuffleMask[Index];
5043 return DAG.getUNDEF(ShufVT.getVectorElementType());
5045 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5047 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5051 // Actual nodes that may contain scalar elements
5052 if (Opcode == ISD::BITCAST) {
5053 V = V.getOperand(0);
5054 EVT SrcVT = V.getValueType();
5055 unsigned NumElems = VT.getVectorNumElements();
5057 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5061 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5062 return (Index == 0) ? V.getOperand(0)
5063 : DAG.getUNDEF(VT.getVectorElementType());
5065 if (V.getOpcode() == ISD::BUILD_VECTOR)
5066 return V.getOperand(Index);
5071 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5072 /// shuffle operation which come from a consecutively from a zero. The
5073 /// search can start in two different directions, from left or right.
5074 /// We count undefs as zeros until PreferredNum is reached.
5075 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5076 unsigned NumElems, bool ZerosFromLeft,
5078 unsigned PreferredNum = -1U) {
5079 unsigned NumZeros = 0;
5080 for (unsigned i = 0; i != NumElems; ++i) {
5081 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5082 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5086 if (X86::isZeroNode(Elt))
5088 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5089 NumZeros = std::min(NumZeros + 1, PreferredNum);
5097 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5098 /// correspond consecutively to elements from one of the vector operands,
5099 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5101 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5102 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5103 unsigned NumElems, unsigned &OpNum) {
5104 bool SeenV1 = false;
5105 bool SeenV2 = false;
5107 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5108 int Idx = SVOp->getMaskElt(i);
5109 // Ignore undef indicies
5113 if (Idx < (int)NumElems)
5118 // Only accept consecutive elements from the same vector
5119 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5123 OpNum = SeenV1 ? 0 : 1;
5127 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5128 /// logical left shift of a vector.
5129 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5130 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5132 SVOp->getSimpleValueType(0).getVectorNumElements();
5133 unsigned NumZeros = getNumOfConsecutiveZeros(
5134 SVOp, NumElems, false /* check zeros from right */, DAG,
5135 SVOp->getMaskElt(0));
5141 // Considering the elements in the mask that are not consecutive zeros,
5142 // check if they consecutively come from only one of the source vectors.
5144 // V1 = {X, A, B, C} 0
5146 // vector_shuffle V1, V2 <1, 2, 3, X>
5148 if (!isShuffleMaskConsecutive(SVOp,
5149 0, // Mask Start Index
5150 NumElems-NumZeros, // Mask End Index(exclusive)
5151 NumZeros, // Where to start looking in the src vector
5152 NumElems, // Number of elements in vector
5153 OpSrc)) // Which source operand ?
5158 ShVal = SVOp->getOperand(OpSrc);
5162 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5163 /// logical left shift of a vector.
5164 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5165 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5167 SVOp->getSimpleValueType(0).getVectorNumElements();
5168 unsigned NumZeros = getNumOfConsecutiveZeros(
5169 SVOp, NumElems, true /* check zeros from left */, DAG,
5170 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5176 // Considering the elements in the mask that are not consecutive zeros,
5177 // check if they consecutively come from only one of the source vectors.
5179 // 0 { A, B, X, X } = V2
5181 // vector_shuffle V1, V2 <X, X, 4, 5>
5183 if (!isShuffleMaskConsecutive(SVOp,
5184 NumZeros, // Mask Start Index
5185 NumElems, // Mask End Index(exclusive)
5186 0, // Where to start looking in the src vector
5187 NumElems, // Number of elements in vector
5188 OpSrc)) // Which source operand ?
5193 ShVal = SVOp->getOperand(OpSrc);
5197 /// isVectorShift - Returns true if the shuffle can be implemented as a
5198 /// logical left or right shift of a vector.
5199 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5200 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5201 // Although the logic below support any bitwidth size, there are no
5202 // shift instructions which handle more than 128-bit vectors.
5203 if (!SVOp->getSimpleValueType(0).is128BitVector())
5206 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5207 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5213 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5215 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5216 unsigned NumNonZero, unsigned NumZero,
5218 const X86Subtarget* Subtarget,
5219 const TargetLowering &TLI) {
5226 for (unsigned i = 0; i < 16; ++i) {
5227 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5228 if (ThisIsNonZero && First) {
5230 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5232 V = DAG.getUNDEF(MVT::v8i16);
5237 SDValue ThisElt(0, 0), LastElt(0, 0);
5238 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5239 if (LastIsNonZero) {
5240 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5241 MVT::i16, Op.getOperand(i-1));
5243 if (ThisIsNonZero) {
5244 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5245 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5246 ThisElt, DAG.getConstant(8, MVT::i8));
5248 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5252 if (ThisElt.getNode())
5253 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5254 DAG.getIntPtrConstant(i/2));
5258 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5261 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5263 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5264 unsigned NumNonZero, unsigned NumZero,
5266 const X86Subtarget* Subtarget,
5267 const TargetLowering &TLI) {
5274 for (unsigned i = 0; i < 8; ++i) {
5275 bool isNonZero = (NonZeros & (1 << i)) != 0;
5279 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5281 V = DAG.getUNDEF(MVT::v8i16);
5284 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5285 MVT::v8i16, V, Op.getOperand(i),
5286 DAG.getIntPtrConstant(i));
5293 /// getVShift - Return a vector logical shift node.
5295 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5296 unsigned NumBits, SelectionDAG &DAG,
5297 const TargetLowering &TLI, SDLoc dl) {
5298 assert(VT.is128BitVector() && "Unknown type for VShift");
5299 EVT ShVT = MVT::v2i64;
5300 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5301 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5302 return DAG.getNode(ISD::BITCAST, dl, VT,
5303 DAG.getNode(Opc, dl, ShVT, SrcOp,
5304 DAG.getConstant(NumBits,
5305 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5309 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5311 // Check if the scalar load can be widened into a vector load. And if
5312 // the address is "base + cst" see if the cst can be "absorbed" into
5313 // the shuffle mask.
5314 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5315 SDValue Ptr = LD->getBasePtr();
5316 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5318 EVT PVT = LD->getValueType(0);
5319 if (PVT != MVT::i32 && PVT != MVT::f32)
5324 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5325 FI = FINode->getIndex();
5327 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5328 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5329 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5330 Offset = Ptr.getConstantOperandVal(1);
5331 Ptr = Ptr.getOperand(0);
5336 // FIXME: 256-bit vector instructions don't require a strict alignment,
5337 // improve this code to support it better.
5338 unsigned RequiredAlign = VT.getSizeInBits()/8;
5339 SDValue Chain = LD->getChain();
5340 // Make sure the stack object alignment is at least 16 or 32.
5341 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5342 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5343 if (MFI->isFixedObjectIndex(FI)) {
5344 // Can't change the alignment. FIXME: It's possible to compute
5345 // the exact stack offset and reference FI + adjust offset instead.
5346 // If someone *really* cares about this. That's the way to implement it.
5349 MFI->setObjectAlignment(FI, RequiredAlign);
5353 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5354 // Ptr + (Offset & ~15).
5357 if ((Offset % RequiredAlign) & 3)
5359 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5361 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5362 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5364 int EltNo = (Offset - StartOffset) >> 2;
5365 unsigned NumElems = VT.getVectorNumElements();
5367 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5368 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5369 LD->getPointerInfo().getWithOffset(StartOffset),
5370 false, false, false, 0);
5372 SmallVector<int, 8> Mask;
5373 for (unsigned i = 0; i != NumElems; ++i)
5374 Mask.push_back(EltNo);
5376 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5382 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5383 /// vector of type 'VT', see if the elements can be replaced by a single large
5384 /// load which has the same value as a build_vector whose operands are 'elts'.
5386 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5388 /// FIXME: we'd also like to handle the case where the last elements are zero
5389 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5390 /// There's even a handy isZeroNode for that purpose.
5391 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5392 SDLoc &DL, SelectionDAG &DAG) {
5393 EVT EltVT = VT.getVectorElementType();
5394 unsigned NumElems = Elts.size();
5396 LoadSDNode *LDBase = NULL;
5397 unsigned LastLoadedElt = -1U;
5399 // For each element in the initializer, see if we've found a load or an undef.
5400 // If we don't find an initial load element, or later load elements are
5401 // non-consecutive, bail out.
5402 for (unsigned i = 0; i < NumElems; ++i) {
5403 SDValue Elt = Elts[i];
5405 if (!Elt.getNode() ||
5406 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5409 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5411 LDBase = cast<LoadSDNode>(Elt.getNode());
5415 if (Elt.getOpcode() == ISD::UNDEF)
5418 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5419 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5424 // If we have found an entire vector of loads and undefs, then return a large
5425 // load of the entire vector width starting at the base pointer. If we found
5426 // consecutive loads for the low half, generate a vzext_load node.
5427 if (LastLoadedElt == NumElems - 1) {
5428 SDValue NewLd = SDValue();
5429 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5430 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5431 LDBase->getPointerInfo(),
5432 LDBase->isVolatile(), LDBase->isNonTemporal(),
5433 LDBase->isInvariant(), 0);
5434 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5435 LDBase->getPointerInfo(),
5436 LDBase->isVolatile(), LDBase->isNonTemporal(),
5437 LDBase->isInvariant(), LDBase->getAlignment());
5439 if (LDBase->hasAnyUseOfValue(1)) {
5440 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5442 SDValue(NewLd.getNode(), 1));
5443 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5444 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5445 SDValue(NewLd.getNode(), 1));
5450 if (NumElems == 4 && LastLoadedElt == 1 &&
5451 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5452 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5453 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5455 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5456 array_lengthof(Ops), MVT::i64,
5457 LDBase->getPointerInfo(),
5458 LDBase->getAlignment(),
5459 false/*isVolatile*/, true/*ReadMem*/,
5462 // Make sure the newly-created LOAD is in the same position as LDBase in
5463 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5464 // update uses of LDBase's output chain to use the TokenFactor.
5465 if (LDBase->hasAnyUseOfValue(1)) {
5466 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5467 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5468 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5469 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5470 SDValue(ResNode.getNode(), 1));
5473 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5478 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5479 /// to generate a splat value for the following cases:
5480 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5481 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5482 /// a scalar load, or a constant.
5483 /// The VBROADCAST node is returned when a pattern is found,
5484 /// or SDValue() otherwise.
5485 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5486 SelectionDAG &DAG) {
5487 if (!Subtarget->hasFp256())
5490 MVT VT = Op.getSimpleValueType();
5493 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5494 "Unsupported vector type for broadcast.");
5499 switch (Op.getOpcode()) {
5501 // Unknown pattern found.
5504 case ISD::BUILD_VECTOR: {
5505 // The BUILD_VECTOR node must be a splat.
5506 if (!isSplatVector(Op.getNode()))
5509 Ld = Op.getOperand(0);
5510 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5511 Ld.getOpcode() == ISD::ConstantFP);
5513 // The suspected load node has several users. Make sure that all
5514 // of its users are from the BUILD_VECTOR node.
5515 // Constants may have multiple users.
5516 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5521 case ISD::VECTOR_SHUFFLE: {
5522 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5524 // Shuffles must have a splat mask where the first element is
5526 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5529 SDValue Sc = Op.getOperand(0);
5530 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5531 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5533 if (!Subtarget->hasInt256())
5536 // Use the register form of the broadcast instruction available on AVX2.
5537 if (VT.getSizeInBits() >= 256)
5538 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5539 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5542 Ld = Sc.getOperand(0);
5543 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5544 Ld.getOpcode() == ISD::ConstantFP);
5546 // The scalar_to_vector node and the suspected
5547 // load node must have exactly one user.
5548 // Constants may have multiple users.
5550 // AVX-512 has register version of the broadcast
5551 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5552 Ld.getValueType().getSizeInBits() >= 32;
5553 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5560 bool IsGE256 = (VT.getSizeInBits() >= 256);
5562 // Handle the broadcasting a single constant scalar from the constant pool
5563 // into a vector. On Sandybridge it is still better to load a constant vector
5564 // from the constant pool and not to broadcast it from a scalar.
5565 if (ConstSplatVal && Subtarget->hasInt256()) {
5566 EVT CVT = Ld.getValueType();
5567 assert(!CVT.isVector() && "Must not broadcast a vector type");
5568 unsigned ScalarSize = CVT.getSizeInBits();
5570 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5571 const Constant *C = 0;
5572 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5573 C = CI->getConstantIntValue();
5574 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5575 C = CF->getConstantFPValue();
5577 assert(C && "Invalid constant type");
5579 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5580 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5581 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5582 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5583 MachinePointerInfo::getConstantPool(),
5584 false, false, false, Alignment);
5586 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5590 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5591 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5593 // Handle AVX2 in-register broadcasts.
5594 if (!IsLoad && Subtarget->hasInt256() &&
5595 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5596 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5598 // The scalar source must be a normal load.
5602 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5603 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5605 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5606 // double since there is no vbroadcastsd xmm
5607 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5608 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5609 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5612 // Unsupported broadcast.
5616 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5617 MVT VT = Op.getSimpleValueType();
5619 // Skip if insert_vec_elt is not supported.
5620 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5621 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5625 unsigned NumElems = Op.getNumOperands();
5629 SmallVector<unsigned, 4> InsertIndices;
5630 SmallVector<int, 8> Mask(NumElems, -1);
5632 for (unsigned i = 0; i != NumElems; ++i) {
5633 unsigned Opc = Op.getOperand(i).getOpcode();
5635 if (Opc == ISD::UNDEF)
5638 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5639 // Quit if more than 1 elements need inserting.
5640 if (InsertIndices.size() > 1)
5643 InsertIndices.push_back(i);
5647 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5648 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5650 // Quit if extracted from vector of different type.
5651 if (ExtractedFromVec.getValueType() != VT)
5654 // Quit if non-constant index.
5655 if (!isa<ConstantSDNode>(ExtIdx))
5658 if (VecIn1.getNode() == 0)
5659 VecIn1 = ExtractedFromVec;
5660 else if (VecIn1 != ExtractedFromVec) {
5661 if (VecIn2.getNode() == 0)
5662 VecIn2 = ExtractedFromVec;
5663 else if (VecIn2 != ExtractedFromVec)
5664 // Quit if more than 2 vectors to shuffle
5668 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5670 if (ExtractedFromVec == VecIn1)
5672 else if (ExtractedFromVec == VecIn2)
5673 Mask[i] = Idx + NumElems;
5676 if (VecIn1.getNode() == 0)
5679 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5680 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5681 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5682 unsigned Idx = InsertIndices[i];
5683 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5684 DAG.getIntPtrConstant(Idx));
5690 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5692 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5694 MVT VT = Op.getSimpleValueType();
5695 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5696 "Unexpected type in LowerBUILD_VECTORvXi1!");
5699 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5700 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5701 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5702 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5703 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5704 Ops, VT.getVectorNumElements());
5707 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5708 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5709 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5710 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5711 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5712 Ops, VT.getVectorNumElements());
5715 bool AllContants = true;
5716 uint64_t Immediate = 0;
5717 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5718 SDValue In = Op.getOperand(idx);
5719 if (In.getOpcode() == ISD::UNDEF)
5721 if (!isa<ConstantSDNode>(In)) {
5722 AllContants = false;
5725 if (cast<ConstantSDNode>(In)->getZExtValue())
5726 Immediate |= (1ULL << idx);
5730 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5731 DAG.getConstant(Immediate, MVT::i16));
5732 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5733 DAG.getIntPtrConstant(0));
5736 // Splat vector (with undefs)
5737 SDValue In = Op.getOperand(0);
5738 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5739 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5740 llvm_unreachable("Unsupported predicate operation");
5743 SDValue EFLAGS, X86CC;
5744 if (In.getOpcode() == ISD::SETCC) {
5745 SDValue Op0 = In.getOperand(0);
5746 SDValue Op1 = In.getOperand(1);
5747 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5748 bool isFP = Op1.getValueType().isFloatingPoint();
5749 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5751 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5753 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5754 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5755 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5756 } else if (In.getOpcode() == X86ISD::SETCC) {
5757 X86CC = In.getOperand(0);
5758 EFLAGS = In.getOperand(1);
5767 // res = allOnes ### CMOVNE -1, %res
5770 MVT InVT = In.getSimpleValueType();
5771 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5772 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5773 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5776 if (VT == MVT::v16i1) {
5777 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5778 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5779 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5780 Cst0, Cst1, X86CC, EFLAGS);
5781 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5784 if (VT == MVT::v8i1) {
5785 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5786 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5787 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5788 Cst0, Cst1, X86CC, EFLAGS);
5789 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5790 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5792 llvm_unreachable("Unsupported predicate operation");
5796 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5799 MVT VT = Op.getSimpleValueType();
5800 MVT ExtVT = VT.getVectorElementType();
5801 unsigned NumElems = Op.getNumOperands();
5803 // Generate vectors for predicate vectors.
5804 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5805 return LowerBUILD_VECTORvXi1(Op, DAG);
5807 // Vectors containing all zeros can be matched by pxor and xorps later
5808 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5809 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5810 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5811 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5814 return getZeroVector(VT, Subtarget, DAG, dl);
5817 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5818 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5819 // vpcmpeqd on 256-bit vectors.
5820 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5821 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5824 if (!VT.is512BitVector())
5825 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5828 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5829 if (Broadcast.getNode())
5832 unsigned EVTBits = ExtVT.getSizeInBits();
5834 unsigned NumZero = 0;
5835 unsigned NumNonZero = 0;
5836 unsigned NonZeros = 0;
5837 bool IsAllConstants = true;
5838 SmallSet<SDValue, 8> Values;
5839 for (unsigned i = 0; i < NumElems; ++i) {
5840 SDValue Elt = Op.getOperand(i);
5841 if (Elt.getOpcode() == ISD::UNDEF)
5844 if (Elt.getOpcode() != ISD::Constant &&
5845 Elt.getOpcode() != ISD::ConstantFP)
5846 IsAllConstants = false;
5847 if (X86::isZeroNode(Elt))
5850 NonZeros |= (1 << i);
5855 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5856 if (NumNonZero == 0)
5857 return DAG.getUNDEF(VT);
5859 // Special case for single non-zero, non-undef, element.
5860 if (NumNonZero == 1) {
5861 unsigned Idx = countTrailingZeros(NonZeros);
5862 SDValue Item = Op.getOperand(Idx);
5864 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5865 // the value are obviously zero, truncate the value to i32 and do the
5866 // insertion that way. Only do this if the value is non-constant or if the
5867 // value is a constant being inserted into element 0. It is cheaper to do
5868 // a constant pool load than it is to do a movd + shuffle.
5869 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5870 (!IsAllConstants || Idx == 0)) {
5871 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5873 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5874 EVT VecVT = MVT::v4i32;
5875 unsigned VecElts = 4;
5877 // Truncate the value (which may itself be a constant) to i32, and
5878 // convert it to a vector with movd (S2V+shuffle to zero extend).
5879 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5881 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5883 // Now we have our 32-bit value zero extended in the low element of
5884 // a vector. If Idx != 0, swizzle it into place.
5886 SmallVector<int, 4> Mask;
5887 Mask.push_back(Idx);
5888 for (unsigned i = 1; i != VecElts; ++i)
5890 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5893 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5897 // If we have a constant or non-constant insertion into the low element of
5898 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5899 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5900 // depending on what the source datatype is.
5903 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5905 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5906 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5907 if (VT.is256BitVector() || VT.is512BitVector()) {
5908 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5909 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5910 Item, DAG.getIntPtrConstant(0));
5912 assert(VT.is128BitVector() && "Expected an SSE value type!");
5913 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5914 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5915 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5918 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5919 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5920 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5921 if (VT.is256BitVector()) {
5922 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5923 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5925 assert(VT.is128BitVector() && "Expected an SSE value type!");
5926 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5928 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5932 // Is it a vector logical left shift?
5933 if (NumElems == 2 && Idx == 1 &&
5934 X86::isZeroNode(Op.getOperand(0)) &&
5935 !X86::isZeroNode(Op.getOperand(1))) {
5936 unsigned NumBits = VT.getSizeInBits();
5937 return getVShift(true, VT,
5938 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5939 VT, Op.getOperand(1)),
5940 NumBits/2, DAG, *this, dl);
5943 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5946 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5947 // is a non-constant being inserted into an element other than the low one,
5948 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5949 // movd/movss) to move this into the low element, then shuffle it into
5951 if (EVTBits == 32) {
5952 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5954 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5955 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5956 SmallVector<int, 8> MaskVec;
5957 for (unsigned i = 0; i != NumElems; ++i)
5958 MaskVec.push_back(i == Idx ? 0 : 1);
5959 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5963 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5964 if (Values.size() == 1) {
5965 if (EVTBits == 32) {
5966 // Instead of a shuffle like this:
5967 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5968 // Check if it's possible to issue this instead.
5969 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5970 unsigned Idx = countTrailingZeros(NonZeros);
5971 SDValue Item = Op.getOperand(Idx);
5972 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5973 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5978 // A vector full of immediates; various special cases are already
5979 // handled, so this is best done with a single constant-pool load.
5983 // For AVX-length vectors, build the individual 128-bit pieces and use
5984 // shuffles to put them in place.
5985 if (VT.is256BitVector()) {
5986 SmallVector<SDValue, 32> V;
5987 for (unsigned i = 0; i != NumElems; ++i)
5988 V.push_back(Op.getOperand(i));
5990 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5992 // Build both the lower and upper subvector.
5993 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5994 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5997 // Recreate the wider vector with the lower and upper part.
5998 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6001 // Let legalizer expand 2-wide build_vectors.
6002 if (EVTBits == 64) {
6003 if (NumNonZero == 1) {
6004 // One half is zero or undef.
6005 unsigned Idx = countTrailingZeros(NonZeros);
6006 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6007 Op.getOperand(Idx));
6008 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6013 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6014 if (EVTBits == 8 && NumElems == 16) {
6015 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6017 if (V.getNode()) return V;
6020 if (EVTBits == 16 && NumElems == 8) {
6021 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6023 if (V.getNode()) return V;
6026 // If element VT is == 32 bits, turn it into a number of shuffles.
6027 SmallVector<SDValue, 8> V(NumElems);
6028 if (NumElems == 4 && NumZero > 0) {
6029 for (unsigned i = 0; i < 4; ++i) {
6030 bool isZero = !(NonZeros & (1 << i));
6032 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6034 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6037 for (unsigned i = 0; i < 2; ++i) {
6038 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6041 V[i] = V[i*2]; // Must be a zero vector.
6044 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6047 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6050 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6055 bool Reverse1 = (NonZeros & 0x3) == 2;
6056 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6060 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6061 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6063 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6066 if (Values.size() > 1 && VT.is128BitVector()) {
6067 // Check for a build vector of consecutive loads.
6068 for (unsigned i = 0; i < NumElems; ++i)
6069 V[i] = Op.getOperand(i);
6071 // Check for elements which are consecutive loads.
6072 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6076 // Check for a build vector from mostly shuffle plus few inserting.
6077 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6081 // For SSE 4.1, use insertps to put the high elements into the low element.
6082 if (getSubtarget()->hasSSE41()) {
6084 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6085 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6087 Result = DAG.getUNDEF(VT);
6089 for (unsigned i = 1; i < NumElems; ++i) {
6090 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6091 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6092 Op.getOperand(i), DAG.getIntPtrConstant(i));
6097 // Otherwise, expand into a number of unpckl*, start by extending each of
6098 // our (non-undef) elements to the full vector width with the element in the
6099 // bottom slot of the vector (which generates no code for SSE).
6100 for (unsigned i = 0; i < NumElems; ++i) {
6101 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6102 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6104 V[i] = DAG.getUNDEF(VT);
6107 // Next, we iteratively mix elements, e.g. for v4f32:
6108 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6109 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6110 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6111 unsigned EltStride = NumElems >> 1;
6112 while (EltStride != 0) {
6113 for (unsigned i = 0; i < EltStride; ++i) {
6114 // If V[i+EltStride] is undef and this is the first round of mixing,
6115 // then it is safe to just drop this shuffle: V[i] is already in the
6116 // right place, the one element (since it's the first round) being
6117 // inserted as undef can be dropped. This isn't safe for successive
6118 // rounds because they will permute elements within both vectors.
6119 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6120 EltStride == NumElems/2)
6123 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6132 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6133 // to create 256-bit vectors from two other 128-bit ones.
6134 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6136 MVT ResVT = Op.getSimpleValueType();
6138 assert((ResVT.is256BitVector() ||
6139 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6141 SDValue V1 = Op.getOperand(0);
6142 SDValue V2 = Op.getOperand(1);
6143 unsigned NumElems = ResVT.getVectorNumElements();
6144 if(ResVT.is256BitVector())
6145 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6147 if (Op.getNumOperands() == 4) {
6148 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6149 ResVT.getVectorNumElements()/2);
6150 SDValue V3 = Op.getOperand(2);
6151 SDValue V4 = Op.getOperand(3);
6152 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6153 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6155 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6158 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6159 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6160 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6161 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6162 Op.getNumOperands() == 4)));
6164 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6165 // from two other 128-bit ones.
6167 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6168 return LowerAVXCONCAT_VECTORS(Op, DAG);
6171 // Try to lower a shuffle node into a simple blend instruction.
6173 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6174 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6175 SDValue V1 = SVOp->getOperand(0);
6176 SDValue V2 = SVOp->getOperand(1);
6178 MVT VT = SVOp->getSimpleValueType(0);
6179 MVT EltVT = VT.getVectorElementType();
6180 unsigned NumElems = VT.getVectorNumElements();
6182 // There is no blend with immediate in AVX-512.
6183 if (VT.is512BitVector())
6186 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6188 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6191 // Check the mask for BLEND and build the value.
6192 unsigned MaskValue = 0;
6193 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6194 unsigned NumLanes = (NumElems-1)/8 + 1;
6195 unsigned NumElemsInLane = NumElems / NumLanes;
6197 // Blend for v16i16 should be symetric for the both lanes.
6198 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6200 int SndLaneEltIdx = (NumLanes == 2) ?
6201 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6202 int EltIdx = SVOp->getMaskElt(i);
6204 if ((EltIdx < 0 || EltIdx == (int)i) &&
6205 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6208 if (((unsigned)EltIdx == (i + NumElems)) &&
6209 (SndLaneEltIdx < 0 ||
6210 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6211 MaskValue |= (1<<i);
6216 // Convert i32 vectors to floating point if it is not AVX2.
6217 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6219 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6220 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6222 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6223 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6226 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6227 DAG.getConstant(MaskValue, MVT::i32));
6228 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6231 // v8i16 shuffles - Prefer shuffles in the following order:
6232 // 1. [all] pshuflw, pshufhw, optional move
6233 // 2. [ssse3] 1 x pshufb
6234 // 3. [ssse3] 2 x pshufb + 1 x por
6235 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6237 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6238 SelectionDAG &DAG) {
6239 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6240 SDValue V1 = SVOp->getOperand(0);
6241 SDValue V2 = SVOp->getOperand(1);
6243 SmallVector<int, 8> MaskVals;
6245 // Determine if more than 1 of the words in each of the low and high quadwords
6246 // of the result come from the same quadword of one of the two inputs. Undef
6247 // mask values count as coming from any quadword, for better codegen.
6248 unsigned LoQuad[] = { 0, 0, 0, 0 };
6249 unsigned HiQuad[] = { 0, 0, 0, 0 };
6250 std::bitset<4> InputQuads;
6251 for (unsigned i = 0; i < 8; ++i) {
6252 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6253 int EltIdx = SVOp->getMaskElt(i);
6254 MaskVals.push_back(EltIdx);
6263 InputQuads.set(EltIdx / 4);
6266 int BestLoQuad = -1;
6267 unsigned MaxQuad = 1;
6268 for (unsigned i = 0; i < 4; ++i) {
6269 if (LoQuad[i] > MaxQuad) {
6271 MaxQuad = LoQuad[i];
6275 int BestHiQuad = -1;
6277 for (unsigned i = 0; i < 4; ++i) {
6278 if (HiQuad[i] > MaxQuad) {
6280 MaxQuad = HiQuad[i];
6284 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6285 // of the two input vectors, shuffle them into one input vector so only a
6286 // single pshufb instruction is necessary. If There are more than 2 input
6287 // quads, disable the next transformation since it does not help SSSE3.
6288 bool V1Used = InputQuads[0] || InputQuads[1];
6289 bool V2Used = InputQuads[2] || InputQuads[3];
6290 if (Subtarget->hasSSSE3()) {
6291 if (InputQuads.count() == 2 && V1Used && V2Used) {
6292 BestLoQuad = InputQuads[0] ? 0 : 1;
6293 BestHiQuad = InputQuads[2] ? 2 : 3;
6295 if (InputQuads.count() > 2) {
6301 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6302 // the shuffle mask. If a quad is scored as -1, that means that it contains
6303 // words from all 4 input quadwords.
6305 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6307 BestLoQuad < 0 ? 0 : BestLoQuad,
6308 BestHiQuad < 0 ? 1 : BestHiQuad
6310 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6311 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6312 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6313 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6315 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6316 // source words for the shuffle, to aid later transformations.
6317 bool AllWordsInNewV = true;
6318 bool InOrder[2] = { true, true };
6319 for (unsigned i = 0; i != 8; ++i) {
6320 int idx = MaskVals[i];
6322 InOrder[i/4] = false;
6323 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6325 AllWordsInNewV = false;
6329 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6330 if (AllWordsInNewV) {
6331 for (int i = 0; i != 8; ++i) {
6332 int idx = MaskVals[i];
6335 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6336 if ((idx != i) && idx < 4)
6338 if ((idx != i) && idx > 3)
6347 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6348 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6349 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6350 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6351 unsigned TargetMask = 0;
6352 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6353 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6355 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6356 getShufflePSHUFLWImmediate(SVOp);
6357 V1 = NewV.getOperand(0);
6358 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6362 // Promote splats to a larger type which usually leads to more efficient code.
6363 // FIXME: Is this true if pshufb is available?
6364 if (SVOp->isSplat())
6365 return PromoteSplat(SVOp, DAG);
6367 // If we have SSSE3, and all words of the result are from 1 input vector,
6368 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6369 // is present, fall back to case 4.
6370 if (Subtarget->hasSSSE3()) {
6371 SmallVector<SDValue,16> pshufbMask;
6373 // If we have elements from both input vectors, set the high bit of the
6374 // shuffle mask element to zero out elements that come from V2 in the V1
6375 // mask, and elements that come from V1 in the V2 mask, so that the two
6376 // results can be OR'd together.
6377 bool TwoInputs = V1Used && V2Used;
6378 for (unsigned i = 0; i != 8; ++i) {
6379 int EltIdx = MaskVals[i] * 2;
6380 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6381 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6382 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6383 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6385 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6386 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6387 DAG.getNode(ISD::BUILD_VECTOR, dl,
6388 MVT::v16i8, &pshufbMask[0], 16));
6390 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6392 // Calculate the shuffle mask for the second input, shuffle it, and
6393 // OR it with the first shuffled input.
6395 for (unsigned i = 0; i != 8; ++i) {
6396 int EltIdx = MaskVals[i] * 2;
6397 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6398 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6399 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6400 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6402 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6403 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6404 DAG.getNode(ISD::BUILD_VECTOR, dl,
6405 MVT::v16i8, &pshufbMask[0], 16));
6406 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6407 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6410 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6411 // and update MaskVals with new element order.
6412 std::bitset<8> InOrder;
6413 if (BestLoQuad >= 0) {
6414 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6415 for (int i = 0; i != 4; ++i) {
6416 int idx = MaskVals[i];
6419 } else if ((idx / 4) == BestLoQuad) {
6424 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6427 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6429 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6431 getShufflePSHUFLWImmediate(SVOp), DAG);
6435 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6436 // and update MaskVals with the new element order.
6437 if (BestHiQuad >= 0) {
6438 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6439 for (unsigned i = 4; i != 8; ++i) {
6440 int idx = MaskVals[i];
6443 } else if ((idx / 4) == BestHiQuad) {
6444 MaskV[i] = (idx & 3) + 4;
6448 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6451 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6453 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6455 getShufflePSHUFHWImmediate(SVOp), DAG);
6459 // In case BestHi & BestLo were both -1, which means each quadword has a word
6460 // from each of the four input quadwords, calculate the InOrder bitvector now
6461 // before falling through to the insert/extract cleanup.
6462 if (BestLoQuad == -1 && BestHiQuad == -1) {
6464 for (int i = 0; i != 8; ++i)
6465 if (MaskVals[i] < 0 || MaskVals[i] == i)
6469 // The other elements are put in the right place using pextrw and pinsrw.
6470 for (unsigned i = 0; i != 8; ++i) {
6473 int EltIdx = MaskVals[i];
6476 SDValue ExtOp = (EltIdx < 8) ?
6477 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6478 DAG.getIntPtrConstant(EltIdx)) :
6479 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6480 DAG.getIntPtrConstant(EltIdx - 8));
6481 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6482 DAG.getIntPtrConstant(i));
6487 // v16i8 shuffles - Prefer shuffles in the following order:
6488 // 1. [ssse3] 1 x pshufb
6489 // 2. [ssse3] 2 x pshufb + 1 x por
6490 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6491 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6492 const X86Subtarget* Subtarget,
6493 SelectionDAG &DAG) {
6494 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6495 SDValue V1 = SVOp->getOperand(0);
6496 SDValue V2 = SVOp->getOperand(1);
6498 ArrayRef<int> MaskVals = SVOp->getMask();
6500 // Promote splats to a larger type which usually leads to more efficient code.
6501 // FIXME: Is this true if pshufb is available?
6502 if (SVOp->isSplat())
6503 return PromoteSplat(SVOp, DAG);
6505 // If we have SSSE3, case 1 is generated when all result bytes come from
6506 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6507 // present, fall back to case 3.
6509 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6510 if (Subtarget->hasSSSE3()) {
6511 SmallVector<SDValue,16> pshufbMask;
6513 // If all result elements are from one input vector, then only translate
6514 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6516 // Otherwise, we have elements from both input vectors, and must zero out
6517 // elements that come from V2 in the first mask, and V1 in the second mask
6518 // so that we can OR them together.
6519 for (unsigned i = 0; i != 16; ++i) {
6520 int EltIdx = MaskVals[i];
6521 if (EltIdx < 0 || EltIdx >= 16)
6523 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6525 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6526 DAG.getNode(ISD::BUILD_VECTOR, dl,
6527 MVT::v16i8, &pshufbMask[0], 16));
6529 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6530 // the 2nd operand if it's undefined or zero.
6531 if (V2.getOpcode() == ISD::UNDEF ||
6532 ISD::isBuildVectorAllZeros(V2.getNode()))
6535 // Calculate the shuffle mask for the second input, shuffle it, and
6536 // OR it with the first shuffled input.
6538 for (unsigned i = 0; i != 16; ++i) {
6539 int EltIdx = MaskVals[i];
6540 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6541 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6543 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6544 DAG.getNode(ISD::BUILD_VECTOR, dl,
6545 MVT::v16i8, &pshufbMask[0], 16));
6546 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6549 // No SSSE3 - Calculate in place words and then fix all out of place words
6550 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6551 // the 16 different words that comprise the two doublequadword input vectors.
6552 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6553 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6555 for (int i = 0; i != 8; ++i) {
6556 int Elt0 = MaskVals[i*2];
6557 int Elt1 = MaskVals[i*2+1];
6559 // This word of the result is all undef, skip it.
6560 if (Elt0 < 0 && Elt1 < 0)
6563 // This word of the result is already in the correct place, skip it.
6564 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6567 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6568 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6571 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6572 // using a single extract together, load it and store it.
6573 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6574 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6575 DAG.getIntPtrConstant(Elt1 / 2));
6576 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6577 DAG.getIntPtrConstant(i));
6581 // If Elt1 is defined, extract it from the appropriate source. If the
6582 // source byte is not also odd, shift the extracted word left 8 bits
6583 // otherwise clear the bottom 8 bits if we need to do an or.
6585 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6586 DAG.getIntPtrConstant(Elt1 / 2));
6587 if ((Elt1 & 1) == 0)
6588 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6590 TLI.getShiftAmountTy(InsElt.getValueType())));
6592 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6593 DAG.getConstant(0xFF00, MVT::i16));
6595 // If Elt0 is defined, extract it from the appropriate source. If the
6596 // source byte is not also even, shift the extracted word right 8 bits. If
6597 // Elt1 was also defined, OR the extracted values together before
6598 // inserting them in the result.
6600 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6601 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6602 if ((Elt0 & 1) != 0)
6603 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6605 TLI.getShiftAmountTy(InsElt0.getValueType())));
6607 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6608 DAG.getConstant(0x00FF, MVT::i16));
6609 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6612 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6613 DAG.getIntPtrConstant(i));
6615 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6618 // v32i8 shuffles - Translate to VPSHUFB if possible.
6620 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6621 const X86Subtarget *Subtarget,
6622 SelectionDAG &DAG) {
6623 MVT VT = SVOp->getSimpleValueType(0);
6624 SDValue V1 = SVOp->getOperand(0);
6625 SDValue V2 = SVOp->getOperand(1);
6627 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6629 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6630 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6631 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6633 // VPSHUFB may be generated if
6634 // (1) one of input vector is undefined or zeroinitializer.
6635 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6636 // And (2) the mask indexes don't cross the 128-bit lane.
6637 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6638 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6641 if (V1IsAllZero && !V2IsAllZero) {
6642 CommuteVectorShuffleMask(MaskVals, 32);
6645 SmallVector<SDValue, 32> pshufbMask;
6646 for (unsigned i = 0; i != 32; i++) {
6647 int EltIdx = MaskVals[i];
6648 if (EltIdx < 0 || EltIdx >= 32)
6651 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6652 // Cross lane is not allowed.
6656 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6658 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6659 DAG.getNode(ISD::BUILD_VECTOR, dl,
6660 MVT::v32i8, &pshufbMask[0], 32));
6663 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6664 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6665 /// done when every pair / quad of shuffle mask elements point to elements in
6666 /// the right sequence. e.g.
6667 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6669 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6670 SelectionDAG &DAG) {
6671 MVT VT = SVOp->getSimpleValueType(0);
6673 unsigned NumElems = VT.getVectorNumElements();
6676 switch (VT.SimpleTy) {
6677 default: llvm_unreachable("Unexpected!");
6678 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6679 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6680 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6681 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6682 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6683 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6686 SmallVector<int, 8> MaskVec;
6687 for (unsigned i = 0; i != NumElems; i += Scale) {
6689 for (unsigned j = 0; j != Scale; ++j) {
6690 int EltIdx = SVOp->getMaskElt(i+j);
6694 StartIdx = (EltIdx / Scale);
6695 if (EltIdx != (int)(StartIdx*Scale + j))
6698 MaskVec.push_back(StartIdx);
6701 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6702 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6703 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6706 /// getVZextMovL - Return a zero-extending vector move low node.
6708 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6709 SDValue SrcOp, SelectionDAG &DAG,
6710 const X86Subtarget *Subtarget, SDLoc dl) {
6711 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6712 LoadSDNode *LD = NULL;
6713 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6714 LD = dyn_cast<LoadSDNode>(SrcOp);
6716 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6718 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6719 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6720 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6721 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6722 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6724 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6725 return DAG.getNode(ISD::BITCAST, dl, VT,
6726 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6727 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6735 return DAG.getNode(ISD::BITCAST, dl, VT,
6736 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6737 DAG.getNode(ISD::BITCAST, dl,
6741 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6742 /// which could not be matched by any known target speficic shuffle
6744 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6746 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6747 if (NewOp.getNode())
6750 MVT VT = SVOp->getSimpleValueType(0);
6752 unsigned NumElems = VT.getVectorNumElements();
6753 unsigned NumLaneElems = NumElems / 2;
6756 MVT EltVT = VT.getVectorElementType();
6757 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6760 SmallVector<int, 16> Mask;
6761 for (unsigned l = 0; l < 2; ++l) {
6762 // Build a shuffle mask for the output, discovering on the fly which
6763 // input vectors to use as shuffle operands (recorded in InputUsed).
6764 // If building a suitable shuffle vector proves too hard, then bail
6765 // out with UseBuildVector set.
6766 bool UseBuildVector = false;
6767 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6768 unsigned LaneStart = l * NumLaneElems;
6769 for (unsigned i = 0; i != NumLaneElems; ++i) {
6770 // The mask element. This indexes into the input.
6771 int Idx = SVOp->getMaskElt(i+LaneStart);
6773 // the mask element does not index into any input vector.
6778 // The input vector this mask element indexes into.
6779 int Input = Idx / NumLaneElems;
6781 // Turn the index into an offset from the start of the input vector.
6782 Idx -= Input * NumLaneElems;
6784 // Find or create a shuffle vector operand to hold this input.
6786 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6787 if (InputUsed[OpNo] == Input)
6788 // This input vector is already an operand.
6790 if (InputUsed[OpNo] < 0) {
6791 // Create a new operand for this input vector.
6792 InputUsed[OpNo] = Input;
6797 if (OpNo >= array_lengthof(InputUsed)) {
6798 // More than two input vectors used! Give up on trying to create a
6799 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6800 UseBuildVector = true;
6804 // Add the mask index for the new shuffle vector.
6805 Mask.push_back(Idx + OpNo * NumLaneElems);
6808 if (UseBuildVector) {
6809 SmallVector<SDValue, 16> SVOps;
6810 for (unsigned i = 0; i != NumLaneElems; ++i) {
6811 // The mask element. This indexes into the input.
6812 int Idx = SVOp->getMaskElt(i+LaneStart);
6814 SVOps.push_back(DAG.getUNDEF(EltVT));
6818 // The input vector this mask element indexes into.
6819 int Input = Idx / NumElems;
6821 // Turn the index into an offset from the start of the input vector.
6822 Idx -= Input * NumElems;
6824 // Extract the vector element by hand.
6825 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6826 SVOp->getOperand(Input),
6827 DAG.getIntPtrConstant(Idx)));
6830 // Construct the output using a BUILD_VECTOR.
6831 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6833 } else if (InputUsed[0] < 0) {
6834 // No input vectors were used! The result is undefined.
6835 Output[l] = DAG.getUNDEF(NVT);
6837 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6838 (InputUsed[0] % 2) * NumLaneElems,
6840 // If only one input was used, use an undefined vector for the other.
6841 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6842 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6843 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6844 // At least one input vector was used. Create a new shuffle vector.
6845 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6851 // Concatenate the result back
6852 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6855 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6856 /// 4 elements, and match them with several different shuffle types.
6858 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6859 SDValue V1 = SVOp->getOperand(0);
6860 SDValue V2 = SVOp->getOperand(1);
6862 MVT VT = SVOp->getSimpleValueType(0);
6864 assert(VT.is128BitVector() && "Unsupported vector size");
6866 std::pair<int, int> Locs[4];
6867 int Mask1[] = { -1, -1, -1, -1 };
6868 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6872 for (unsigned i = 0; i != 4; ++i) {
6873 int Idx = PermMask[i];
6875 Locs[i] = std::make_pair(-1, -1);
6877 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6879 Locs[i] = std::make_pair(0, NumLo);
6883 Locs[i] = std::make_pair(1, NumHi);
6885 Mask1[2+NumHi] = Idx;
6891 if (NumLo <= 2 && NumHi <= 2) {
6892 // If no more than two elements come from either vector. This can be
6893 // implemented with two shuffles. First shuffle gather the elements.
6894 // The second shuffle, which takes the first shuffle as both of its
6895 // vector operands, put the elements into the right order.
6896 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6898 int Mask2[] = { -1, -1, -1, -1 };
6900 for (unsigned i = 0; i != 4; ++i)
6901 if (Locs[i].first != -1) {
6902 unsigned Idx = (i < 2) ? 0 : 4;
6903 Idx += Locs[i].first * 2 + Locs[i].second;
6907 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6910 if (NumLo == 3 || NumHi == 3) {
6911 // Otherwise, we must have three elements from one vector, call it X, and
6912 // one element from the other, call it Y. First, use a shufps to build an
6913 // intermediate vector with the one element from Y and the element from X
6914 // that will be in the same half in the final destination (the indexes don't
6915 // matter). Then, use a shufps to build the final vector, taking the half
6916 // containing the element from Y from the intermediate, and the other half
6919 // Normalize it so the 3 elements come from V1.
6920 CommuteVectorShuffleMask(PermMask, 4);
6924 // Find the element from V2.
6926 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6927 int Val = PermMask[HiIndex];
6934 Mask1[0] = PermMask[HiIndex];
6936 Mask1[2] = PermMask[HiIndex^1];
6938 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6941 Mask1[0] = PermMask[0];
6942 Mask1[1] = PermMask[1];
6943 Mask1[2] = HiIndex & 1 ? 6 : 4;
6944 Mask1[3] = HiIndex & 1 ? 4 : 6;
6945 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6948 Mask1[0] = HiIndex & 1 ? 2 : 0;
6949 Mask1[1] = HiIndex & 1 ? 0 : 2;
6950 Mask1[2] = PermMask[2];
6951 Mask1[3] = PermMask[3];
6956 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6959 // Break it into (shuffle shuffle_hi, shuffle_lo).
6960 int LoMask[] = { -1, -1, -1, -1 };
6961 int HiMask[] = { -1, -1, -1, -1 };
6963 int *MaskPtr = LoMask;
6964 unsigned MaskIdx = 0;
6967 for (unsigned i = 0; i != 4; ++i) {
6974 int Idx = PermMask[i];
6976 Locs[i] = std::make_pair(-1, -1);
6977 } else if (Idx < 4) {
6978 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6979 MaskPtr[LoIdx] = Idx;
6982 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6983 MaskPtr[HiIdx] = Idx;
6988 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6989 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6990 int MaskOps[] = { -1, -1, -1, -1 };
6991 for (unsigned i = 0; i != 4; ++i)
6992 if (Locs[i].first != -1)
6993 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6994 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6997 static bool MayFoldVectorLoad(SDValue V) {
6998 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6999 V = V.getOperand(0);
7001 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7002 V = V.getOperand(0);
7003 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7004 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7005 // BUILD_VECTOR (load), undef
7006 V = V.getOperand(0);
7008 return MayFoldLoad(V);
7012 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7013 MVT VT = Op.getSimpleValueType();
7015 // Canonizalize to v2f64.
7016 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7017 return DAG.getNode(ISD::BITCAST, dl, VT,
7018 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7023 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7025 SDValue V1 = Op.getOperand(0);
7026 SDValue V2 = Op.getOperand(1);
7027 MVT VT = Op.getSimpleValueType();
7029 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7031 if (HasSSE2 && VT == MVT::v2f64)
7032 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7034 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7035 return DAG.getNode(ISD::BITCAST, dl, VT,
7036 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7037 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7038 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7042 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7043 SDValue V1 = Op.getOperand(0);
7044 SDValue V2 = Op.getOperand(1);
7045 MVT VT = Op.getSimpleValueType();
7047 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7048 "unsupported shuffle type");
7050 if (V2.getOpcode() == ISD::UNDEF)
7054 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7058 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7059 SDValue V1 = Op.getOperand(0);
7060 SDValue V2 = Op.getOperand(1);
7061 MVT VT = Op.getSimpleValueType();
7062 unsigned NumElems = VT.getVectorNumElements();
7064 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7065 // operand of these instructions is only memory, so check if there's a
7066 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7068 bool CanFoldLoad = false;
7070 // Trivial case, when V2 comes from a load.
7071 if (MayFoldVectorLoad(V2))
7074 // When V1 is a load, it can be folded later into a store in isel, example:
7075 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7077 // (MOVLPSmr addr:$src1, VR128:$src2)
7078 // So, recognize this potential and also use MOVLPS or MOVLPD
7079 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7082 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7084 if (HasSSE2 && NumElems == 2)
7085 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7088 // If we don't care about the second element, proceed to use movss.
7089 if (SVOp->getMaskElt(1) != -1)
7090 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7093 // movl and movlp will both match v2i64, but v2i64 is never matched by
7094 // movl earlier because we make it strict to avoid messing with the movlp load
7095 // folding logic (see the code above getMOVLP call). Match it here then,
7096 // this is horrible, but will stay like this until we move all shuffle
7097 // matching to x86 specific nodes. Note that for the 1st condition all
7098 // types are matched with movsd.
7100 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7101 // as to remove this logic from here, as much as possible
7102 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7103 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7104 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7107 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7109 // Invert the operand order and use SHUFPS to match it.
7110 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7111 getShuffleSHUFImmediate(SVOp), DAG);
7114 // Reduce a vector shuffle to zext.
7115 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7116 SelectionDAG &DAG) {
7117 // PMOVZX is only available from SSE41.
7118 if (!Subtarget->hasSSE41())
7121 MVT VT = Op.getSimpleValueType();
7123 // Only AVX2 support 256-bit vector integer extending.
7124 if (!Subtarget->hasInt256() && VT.is256BitVector())
7127 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7129 SDValue V1 = Op.getOperand(0);
7130 SDValue V2 = Op.getOperand(1);
7131 unsigned NumElems = VT.getVectorNumElements();
7133 // Extending is an unary operation and the element type of the source vector
7134 // won't be equal to or larger than i64.
7135 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7136 VT.getVectorElementType() == MVT::i64)
7139 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7140 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7141 while ((1U << Shift) < NumElems) {
7142 if (SVOp->getMaskElt(1U << Shift) == 1)
7145 // The maximal ratio is 8, i.e. from i8 to i64.
7150 // Check the shuffle mask.
7151 unsigned Mask = (1U << Shift) - 1;
7152 for (unsigned i = 0; i != NumElems; ++i) {
7153 int EltIdx = SVOp->getMaskElt(i);
7154 if ((i & Mask) != 0 && EltIdx != -1)
7156 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7160 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7161 MVT NeVT = MVT::getIntegerVT(NBits);
7162 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7164 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7167 // Simplify the operand as it's prepared to be fed into shuffle.
7168 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7169 if (V1.getOpcode() == ISD::BITCAST &&
7170 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7171 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7172 V1.getOperand(0).getOperand(0)
7173 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7174 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7175 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7176 ConstantSDNode *CIdx =
7177 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7178 // If it's foldable, i.e. normal load with single use, we will let code
7179 // selection to fold it. Otherwise, we will short the conversion sequence.
7180 if (CIdx && CIdx->getZExtValue() == 0 &&
7181 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7182 MVT FullVT = V.getSimpleValueType();
7183 MVT V1VT = V1.getSimpleValueType();
7184 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7185 // The "ext_vec_elt" node is wider than the result node.
7186 // In this case we should extract subvector from V.
7187 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7188 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7189 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7190 FullVT.getVectorNumElements()/Ratio);
7191 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7192 DAG.getIntPtrConstant(0));
7194 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7198 return DAG.getNode(ISD::BITCAST, DL, VT,
7199 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7203 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7204 SelectionDAG &DAG) {
7205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7206 MVT VT = Op.getSimpleValueType();
7208 SDValue V1 = Op.getOperand(0);
7209 SDValue V2 = Op.getOperand(1);
7211 if (isZeroShuffle(SVOp))
7212 return getZeroVector(VT, Subtarget, DAG, dl);
7214 // Handle splat operations
7215 if (SVOp->isSplat()) {
7216 // Use vbroadcast whenever the splat comes from a foldable load
7217 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7218 if (Broadcast.getNode())
7222 // Check integer expanding shuffles.
7223 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7224 if (NewOp.getNode())
7227 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7229 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7230 VT == MVT::v16i16 || VT == MVT::v32i8) {
7231 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7232 if (NewOp.getNode())
7233 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7234 } else if ((VT == MVT::v4i32 ||
7235 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7236 // FIXME: Figure out a cleaner way to do this.
7237 // Try to make use of movq to zero out the top part.
7238 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7239 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7240 if (NewOp.getNode()) {
7241 MVT NewVT = NewOp.getSimpleValueType();
7242 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7243 NewVT, true, false))
7244 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7245 DAG, Subtarget, dl);
7247 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7248 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7249 if (NewOp.getNode()) {
7250 MVT NewVT = NewOp.getSimpleValueType();
7251 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7252 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7253 DAG, Subtarget, dl);
7261 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7263 SDValue V1 = Op.getOperand(0);
7264 SDValue V2 = Op.getOperand(1);
7265 MVT VT = Op.getSimpleValueType();
7267 unsigned NumElems = VT.getVectorNumElements();
7268 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7269 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7270 bool V1IsSplat = false;
7271 bool V2IsSplat = false;
7272 bool HasSSE2 = Subtarget->hasSSE2();
7273 bool HasFp256 = Subtarget->hasFp256();
7274 bool HasInt256 = Subtarget->hasInt256();
7275 MachineFunction &MF = DAG.getMachineFunction();
7276 bool OptForSize = MF.getFunction()->getAttributes().
7277 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7279 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7281 if (V1IsUndef && V2IsUndef)
7282 return DAG.getUNDEF(VT);
7284 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7286 // Vector shuffle lowering takes 3 steps:
7288 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7289 // narrowing and commutation of operands should be handled.
7290 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7292 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7293 // so the shuffle can be broken into other shuffles and the legalizer can
7294 // try the lowering again.
7296 // The general idea is that no vector_shuffle operation should be left to
7297 // be matched during isel, all of them must be converted to a target specific
7300 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7301 // narrowing and commutation of operands should be handled. The actual code
7302 // doesn't include all of those, work in progress...
7303 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7304 if (NewOp.getNode())
7307 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7309 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7310 // unpckh_undef). Only use pshufd if speed is more important than size.
7311 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7312 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7313 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7314 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7316 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7317 V2IsUndef && MayFoldVectorLoad(V1))
7318 return getMOVDDup(Op, dl, V1, DAG);
7320 if (isMOVHLPS_v_undef_Mask(M, VT))
7321 return getMOVHighToLow(Op, dl, DAG);
7323 // Use to match splats
7324 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7325 (VT == MVT::v2f64 || VT == MVT::v2i64))
7326 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7328 if (isPSHUFDMask(M, VT)) {
7329 // The actual implementation will match the mask in the if above and then
7330 // during isel it can match several different instructions, not only pshufd
7331 // as its name says, sad but true, emulate the behavior for now...
7332 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7333 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7335 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7337 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7338 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7340 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7341 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7344 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7348 if (isPALIGNRMask(M, VT, Subtarget))
7349 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7350 getShufflePALIGNRImmediate(SVOp),
7353 // Check if this can be converted into a logical shift.
7354 bool isLeft = false;
7357 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7358 if (isShift && ShVal.hasOneUse()) {
7359 // If the shifted value has multiple uses, it may be cheaper to use
7360 // v_set0 + movlhps or movhlps, etc.
7361 MVT EltVT = VT.getVectorElementType();
7362 ShAmt *= EltVT.getSizeInBits();
7363 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7366 if (isMOVLMask(M, VT)) {
7367 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7368 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7369 if (!isMOVLPMask(M, VT)) {
7370 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7371 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7373 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7374 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7378 // FIXME: fold these into legal mask.
7379 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7380 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7382 if (isMOVHLPSMask(M, VT))
7383 return getMOVHighToLow(Op, dl, DAG);
7385 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7386 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7388 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7389 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7391 if (isMOVLPMask(M, VT))
7392 return getMOVLP(Op, dl, DAG, HasSSE2);
7394 if (ShouldXformToMOVHLPS(M, VT) ||
7395 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7396 return CommuteVectorShuffle(SVOp, DAG);
7399 // No better options. Use a vshldq / vsrldq.
7400 MVT EltVT = VT.getVectorElementType();
7401 ShAmt *= EltVT.getSizeInBits();
7402 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7405 bool Commuted = false;
7406 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7407 // 1,1,1,1 -> v8i16 though.
7408 V1IsSplat = isSplatVector(V1.getNode());
7409 V2IsSplat = isSplatVector(V2.getNode());
7411 // Canonicalize the splat or undef, if present, to be on the RHS.
7412 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7413 CommuteVectorShuffleMask(M, NumElems);
7415 std::swap(V1IsSplat, V2IsSplat);
7419 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7420 // Shuffling low element of v1 into undef, just return v1.
7423 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7424 // the instruction selector will not match, so get a canonical MOVL with
7425 // swapped operands to undo the commute.
7426 return getMOVL(DAG, dl, VT, V2, V1);
7429 if (isUNPCKLMask(M, VT, HasInt256))
7430 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7432 if (isUNPCKHMask(M, VT, HasInt256))
7433 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7436 // Normalize mask so all entries that point to V2 points to its first
7437 // element then try to match unpck{h|l} again. If match, return a
7438 // new vector_shuffle with the corrected mask.p
7439 SmallVector<int, 8> NewMask(M.begin(), M.end());
7440 NormalizeMask(NewMask, NumElems);
7441 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7442 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7443 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7444 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7448 // Commute is back and try unpck* again.
7449 // FIXME: this seems wrong.
7450 CommuteVectorShuffleMask(M, NumElems);
7452 std::swap(V1IsSplat, V2IsSplat);
7455 if (isUNPCKLMask(M, VT, HasInt256))
7456 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7458 if (isUNPCKHMask(M, VT, HasInt256))
7459 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7462 // Normalize the node to match x86 shuffle ops if needed
7463 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7464 return CommuteVectorShuffle(SVOp, DAG);
7466 // The checks below are all present in isShuffleMaskLegal, but they are
7467 // inlined here right now to enable us to directly emit target specific
7468 // nodes, and remove one by one until they don't return Op anymore.
7470 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7471 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7472 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7473 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7476 if (isPSHUFHWMask(M, VT, HasInt256))
7477 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7478 getShufflePSHUFHWImmediate(SVOp),
7481 if (isPSHUFLWMask(M, VT, HasInt256))
7482 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7483 getShufflePSHUFLWImmediate(SVOp),
7486 if (isSHUFPMask(M, VT))
7487 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7488 getShuffleSHUFImmediate(SVOp), DAG);
7490 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7491 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7492 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7493 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7495 //===--------------------------------------------------------------------===//
7496 // Generate target specific nodes for 128 or 256-bit shuffles only
7497 // supported in the AVX instruction set.
7500 // Handle VMOVDDUPY permutations
7501 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7502 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7504 // Handle VPERMILPS/D* permutations
7505 if (isVPERMILPMask(M, VT)) {
7506 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7507 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7508 getShuffleSHUFImmediate(SVOp), DAG);
7509 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7510 getShuffleSHUFImmediate(SVOp), DAG);
7513 // Handle VPERM2F128/VPERM2I128 permutations
7514 if (isVPERM2X128Mask(M, VT, HasFp256))
7515 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7516 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7518 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7519 if (BlendOp.getNode())
7523 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7524 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7526 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7527 VT.is512BitVector()) {
7528 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7529 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7530 SmallVector<SDValue, 16> permclMask;
7531 for (unsigned i = 0; i != NumElems; ++i) {
7532 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7535 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7536 &permclMask[0], NumElems);
7538 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7539 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7540 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7541 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7542 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7545 //===--------------------------------------------------------------------===//
7546 // Since no target specific shuffle was selected for this generic one,
7547 // lower it into other known shuffles. FIXME: this isn't true yet, but
7548 // this is the plan.
7551 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7552 if (VT == MVT::v8i16) {
7553 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7554 if (NewOp.getNode())
7558 if (VT == MVT::v16i8) {
7559 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7560 if (NewOp.getNode())
7564 if (VT == MVT::v32i8) {
7565 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7566 if (NewOp.getNode())
7570 // Handle all 128-bit wide vectors with 4 elements, and match them with
7571 // several different shuffle types.
7572 if (NumElems == 4 && VT.is128BitVector())
7573 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7575 // Handle general 256-bit shuffles
7576 if (VT.is256BitVector())
7577 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7582 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7583 MVT VT = Op.getSimpleValueType();
7586 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7589 if (VT.getSizeInBits() == 8) {
7590 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7591 Op.getOperand(0), Op.getOperand(1));
7592 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7593 DAG.getValueType(VT));
7594 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7597 if (VT.getSizeInBits() == 16) {
7598 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7599 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7601 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7602 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7603 DAG.getNode(ISD::BITCAST, dl,
7607 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7608 Op.getOperand(0), Op.getOperand(1));
7609 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7610 DAG.getValueType(VT));
7611 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7614 if (VT == MVT::f32) {
7615 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7616 // the result back to FR32 register. It's only worth matching if the
7617 // result has a single use which is a store or a bitcast to i32. And in
7618 // the case of a store, it's not worth it if the index is a constant 0,
7619 // because a MOVSSmr can be used instead, which is smaller and faster.
7620 if (!Op.hasOneUse())
7622 SDNode *User = *Op.getNode()->use_begin();
7623 if ((User->getOpcode() != ISD::STORE ||
7624 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7625 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7626 (User->getOpcode() != ISD::BITCAST ||
7627 User->getValueType(0) != MVT::i32))
7629 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7630 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7633 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7636 if (VT == MVT::i32 || VT == MVT::i64) {
7637 // ExtractPS/pextrq works with constant index.
7638 if (isa<ConstantSDNode>(Op.getOperand(1)))
7645 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7646 SelectionDAG &DAG) const {
7648 SDValue Vec = Op.getOperand(0);
7649 MVT VecVT = Vec.getSimpleValueType();
7650 SDValue Idx = Op.getOperand(1);
7651 if (!isa<ConstantSDNode>(Idx)) {
7652 if (VecVT.is512BitVector() ||
7653 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7654 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7657 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7658 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7659 MaskEltVT.getSizeInBits());
7661 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7662 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7663 getZeroVector(MaskVT, Subtarget, DAG, dl),
7664 Idx, DAG.getConstant(0, getPointerTy()));
7665 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7666 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7667 Perm, DAG.getConstant(0, getPointerTy()));
7672 // If this is a 256-bit vector result, first extract the 128-bit vector and
7673 // then extract the element from the 128-bit vector.
7674 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7676 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7677 // Get the 128-bit vector.
7678 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7679 MVT EltVT = VecVT.getVectorElementType();
7681 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7683 //if (IdxVal >= NumElems/2)
7684 // IdxVal -= NumElems/2;
7685 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7686 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7687 DAG.getConstant(IdxVal, MVT::i32));
7690 assert(VecVT.is128BitVector() && "Unexpected vector length");
7692 if (Subtarget->hasSSE41()) {
7693 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7698 MVT VT = Op.getSimpleValueType();
7699 // TODO: handle v16i8.
7700 if (VT.getSizeInBits() == 16) {
7701 SDValue Vec = Op.getOperand(0);
7702 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7704 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7705 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7706 DAG.getNode(ISD::BITCAST, dl,
7709 // Transform it so it match pextrw which produces a 32-bit result.
7710 MVT EltVT = MVT::i32;
7711 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7712 Op.getOperand(0), Op.getOperand(1));
7713 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7714 DAG.getValueType(VT));
7715 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7718 if (VT.getSizeInBits() == 32) {
7719 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7723 // SHUFPS the element to the lowest double word, then movss.
7724 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7725 MVT VVT = Op.getOperand(0).getSimpleValueType();
7726 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7727 DAG.getUNDEF(VVT), Mask);
7728 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7729 DAG.getIntPtrConstant(0));
7732 if (VT.getSizeInBits() == 64) {
7733 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7734 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7735 // to match extract_elt for f64.
7736 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7740 // UNPCKHPD the element to the lowest double word, then movsd.
7741 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7742 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7743 int Mask[2] = { 1, -1 };
7744 MVT VVT = Op.getOperand(0).getSimpleValueType();
7745 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7746 DAG.getUNDEF(VVT), Mask);
7747 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7748 DAG.getIntPtrConstant(0));
7754 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7755 MVT VT = Op.getSimpleValueType();
7756 MVT EltVT = VT.getVectorElementType();
7759 SDValue N0 = Op.getOperand(0);
7760 SDValue N1 = Op.getOperand(1);
7761 SDValue N2 = Op.getOperand(2);
7763 if (!VT.is128BitVector())
7766 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7767 isa<ConstantSDNode>(N2)) {
7769 if (VT == MVT::v8i16)
7770 Opc = X86ISD::PINSRW;
7771 else if (VT == MVT::v16i8)
7772 Opc = X86ISD::PINSRB;
7774 Opc = X86ISD::PINSRB;
7776 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7778 if (N1.getValueType() != MVT::i32)
7779 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7780 if (N2.getValueType() != MVT::i32)
7781 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7782 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7785 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7786 // Bits [7:6] of the constant are the source select. This will always be
7787 // zero here. The DAG Combiner may combine an extract_elt index into these
7788 // bits. For example (insert (extract, 3), 2) could be matched by putting
7789 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7790 // Bits [5:4] of the constant are the destination select. This is the
7791 // value of the incoming immediate.
7792 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7793 // combine either bitwise AND or insert of float 0.0 to set these bits.
7794 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7795 // Create this as a scalar to vector..
7796 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7797 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7800 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7801 // PINSR* works with constant index.
7808 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7809 MVT VT = Op.getSimpleValueType();
7810 MVT EltVT = VT.getVectorElementType();
7813 SDValue N0 = Op.getOperand(0);
7814 SDValue N1 = Op.getOperand(1);
7815 SDValue N2 = Op.getOperand(2);
7817 // If this is a 256-bit vector result, first extract the 128-bit vector,
7818 // insert the element into the extracted half and then place it back.
7819 if (VT.is256BitVector() || VT.is512BitVector()) {
7820 if (!isa<ConstantSDNode>(N2))
7823 // Get the desired 128-bit vector half.
7824 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7825 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7827 // Insert the element into the desired half.
7828 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7829 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7831 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7832 DAG.getConstant(IdxIn128, MVT::i32));
7834 // Insert the changed part back to the 256-bit vector
7835 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7838 if (Subtarget->hasSSE41())
7839 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7841 if (EltVT == MVT::i8)
7844 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7845 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7846 // as its second argument.
7847 if (N1.getValueType() != MVT::i32)
7848 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7849 if (N2.getValueType() != MVT::i32)
7850 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7851 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7856 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7858 MVT OpVT = Op.getSimpleValueType();
7860 // If this is a 256-bit vector result, first insert into a 128-bit
7861 // vector and then insert into the 256-bit vector.
7862 if (!OpVT.is128BitVector()) {
7863 // Insert into a 128-bit vector.
7864 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7865 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7866 OpVT.getVectorNumElements() / SizeFactor);
7868 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7870 // Insert the 128-bit vector.
7871 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7874 if (OpVT == MVT::v1i64 &&
7875 Op.getOperand(0).getValueType() == MVT::i64)
7876 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7878 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7879 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7880 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7881 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7884 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7885 // a simple subregister reference or explicit instructions to grab
7886 // upper bits of a vector.
7887 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7888 SelectionDAG &DAG) {
7890 SDValue In = Op.getOperand(0);
7891 SDValue Idx = Op.getOperand(1);
7892 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7893 MVT ResVT = Op.getSimpleValueType();
7894 MVT InVT = In.getSimpleValueType();
7896 if (Subtarget->hasFp256()) {
7897 if (ResVT.is128BitVector() &&
7898 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7899 isa<ConstantSDNode>(Idx)) {
7900 return Extract128BitVector(In, IdxVal, DAG, dl);
7902 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7903 isa<ConstantSDNode>(Idx)) {
7904 return Extract256BitVector(In, IdxVal, DAG, dl);
7910 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7911 // simple superregister reference or explicit instructions to insert
7912 // the upper bits of a vector.
7913 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7914 SelectionDAG &DAG) {
7915 if (Subtarget->hasFp256()) {
7916 SDLoc dl(Op.getNode());
7917 SDValue Vec = Op.getNode()->getOperand(0);
7918 SDValue SubVec = Op.getNode()->getOperand(1);
7919 SDValue Idx = Op.getNode()->getOperand(2);
7921 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7922 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7923 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7924 isa<ConstantSDNode>(Idx)) {
7925 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7926 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7929 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7930 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7931 isa<ConstantSDNode>(Idx)) {
7932 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7933 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7939 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7940 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7941 // one of the above mentioned nodes. It has to be wrapped because otherwise
7942 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7943 // be used to form addressing mode. These wrapped nodes will be selected
7946 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7947 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7949 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7951 unsigned char OpFlag = 0;
7952 unsigned WrapperKind = X86ISD::Wrapper;
7953 CodeModel::Model M = getTargetMachine().getCodeModel();
7955 if (Subtarget->isPICStyleRIPRel() &&
7956 (M == CodeModel::Small || M == CodeModel::Kernel))
7957 WrapperKind = X86ISD::WrapperRIP;
7958 else if (Subtarget->isPICStyleGOT())
7959 OpFlag = X86II::MO_GOTOFF;
7960 else if (Subtarget->isPICStyleStubPIC())
7961 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7963 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7965 CP->getOffset(), OpFlag);
7967 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7968 // With PIC, the address is actually $g + Offset.
7970 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7971 DAG.getNode(X86ISD::GlobalBaseReg,
7972 SDLoc(), getPointerTy()),
7979 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7980 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7982 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7984 unsigned char OpFlag = 0;
7985 unsigned WrapperKind = X86ISD::Wrapper;
7986 CodeModel::Model M = getTargetMachine().getCodeModel();
7988 if (Subtarget->isPICStyleRIPRel() &&
7989 (M == CodeModel::Small || M == CodeModel::Kernel))
7990 WrapperKind = X86ISD::WrapperRIP;
7991 else if (Subtarget->isPICStyleGOT())
7992 OpFlag = X86II::MO_GOTOFF;
7993 else if (Subtarget->isPICStyleStubPIC())
7994 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7996 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7999 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8001 // With PIC, the address is actually $g + Offset.
8003 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8004 DAG.getNode(X86ISD::GlobalBaseReg,
8005 SDLoc(), getPointerTy()),
8012 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8013 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8015 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8017 unsigned char OpFlag = 0;
8018 unsigned WrapperKind = X86ISD::Wrapper;
8019 CodeModel::Model M = getTargetMachine().getCodeModel();
8021 if (Subtarget->isPICStyleRIPRel() &&
8022 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8023 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8024 OpFlag = X86II::MO_GOTPCREL;
8025 WrapperKind = X86ISD::WrapperRIP;
8026 } else if (Subtarget->isPICStyleGOT()) {
8027 OpFlag = X86II::MO_GOT;
8028 } else if (Subtarget->isPICStyleStubPIC()) {
8029 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8030 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8031 OpFlag = X86II::MO_DARWIN_NONLAZY;
8034 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8037 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8039 // With PIC, the address is actually $g + Offset.
8040 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8041 !Subtarget->is64Bit()) {
8042 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8043 DAG.getNode(X86ISD::GlobalBaseReg,
8044 SDLoc(), getPointerTy()),
8048 // For symbols that require a load from a stub to get the address, emit the
8050 if (isGlobalStubReference(OpFlag))
8051 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8052 MachinePointerInfo::getGOT(), false, false, false, 0);
8058 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8059 // Create the TargetBlockAddressAddress node.
8060 unsigned char OpFlags =
8061 Subtarget->ClassifyBlockAddressReference();
8062 CodeModel::Model M = getTargetMachine().getCodeModel();
8063 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8064 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8066 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8069 if (Subtarget->isPICStyleRIPRel() &&
8070 (M == CodeModel::Small || M == CodeModel::Kernel))
8071 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8073 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8075 // With PIC, the address is actually $g + Offset.
8076 if (isGlobalRelativeToPICBase(OpFlags)) {
8077 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8078 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8086 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8087 int64_t Offset, SelectionDAG &DAG) const {
8088 // Create the TargetGlobalAddress node, folding in the constant
8089 // offset if it is legal.
8090 unsigned char OpFlags =
8091 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8092 CodeModel::Model M = getTargetMachine().getCodeModel();
8094 if (OpFlags == X86II::MO_NO_FLAG &&
8095 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8096 // A direct static reference to a global.
8097 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8100 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8103 if (Subtarget->isPICStyleRIPRel() &&
8104 (M == CodeModel::Small || M == CodeModel::Kernel))
8105 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8107 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8109 // With PIC, the address is actually $g + Offset.
8110 if (isGlobalRelativeToPICBase(OpFlags)) {
8111 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8112 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8116 // For globals that require a load from a stub to get the address, emit the
8118 if (isGlobalStubReference(OpFlags))
8119 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8120 MachinePointerInfo::getGOT(), false, false, false, 0);
8122 // If there was a non-zero offset that we didn't fold, create an explicit
8125 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8126 DAG.getConstant(Offset, getPointerTy()));
8132 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8133 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8134 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8135 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8139 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8140 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8141 unsigned char OperandFlags, bool LocalDynamic = false) {
8142 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8143 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8145 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8146 GA->getValueType(0),
8150 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8154 SDValue Ops[] = { Chain, TGA, *InFlag };
8155 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8157 SDValue Ops[] = { Chain, TGA };
8158 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8161 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8162 MFI->setAdjustsStack(true);
8164 SDValue Flag = Chain.getValue(1);
8165 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8168 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8170 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8173 SDLoc dl(GA); // ? function entry point might be better
8174 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8175 DAG.getNode(X86ISD::GlobalBaseReg,
8176 SDLoc(), PtrVT), InFlag);
8177 InFlag = Chain.getValue(1);
8179 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8182 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8184 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8186 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8187 X86::RAX, X86II::MO_TLSGD);
8190 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8196 // Get the start address of the TLS block for this module.
8197 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8198 .getInfo<X86MachineFunctionInfo>();
8199 MFI->incNumLocalDynamicTLSAccesses();
8203 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8204 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8207 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8208 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8209 InFlag = Chain.getValue(1);
8210 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8211 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8214 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8218 unsigned char OperandFlags = X86II::MO_DTPOFF;
8219 unsigned WrapperKind = X86ISD::Wrapper;
8220 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8221 GA->getValueType(0),
8222 GA->getOffset(), OperandFlags);
8223 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8225 // Add x@dtpoff with the base.
8226 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8229 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8230 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8231 const EVT PtrVT, TLSModel::Model model,
8232 bool is64Bit, bool isPIC) {
8235 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8236 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8237 is64Bit ? 257 : 256));
8239 SDValue ThreadPointer =
8240 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8241 MachinePointerInfo(Ptr), false, false, false, 0);
8243 unsigned char OperandFlags = 0;
8244 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8246 unsigned WrapperKind = X86ISD::Wrapper;
8247 if (model == TLSModel::LocalExec) {
8248 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8249 } else if (model == TLSModel::InitialExec) {
8251 OperandFlags = X86II::MO_GOTTPOFF;
8252 WrapperKind = X86ISD::WrapperRIP;
8254 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8257 llvm_unreachable("Unexpected model");
8260 // emit "addl x@ntpoff,%eax" (local exec)
8261 // or "addl x@indntpoff,%eax" (initial exec)
8262 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8264 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8265 GA->getOffset(), OperandFlags);
8266 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8268 if (model == TLSModel::InitialExec) {
8269 if (isPIC && !is64Bit) {
8270 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8271 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8275 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8276 MachinePointerInfo::getGOT(), false, false, false, 0);
8279 // The address of the thread local variable is the add of the thread
8280 // pointer with the offset of the variable.
8281 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8285 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8287 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8288 const GlobalValue *GV = GA->getGlobal();
8290 if (Subtarget->isTargetELF()) {
8291 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8294 case TLSModel::GeneralDynamic:
8295 if (Subtarget->is64Bit())
8296 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8297 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8298 case TLSModel::LocalDynamic:
8299 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8300 Subtarget->is64Bit());
8301 case TLSModel::InitialExec:
8302 case TLSModel::LocalExec:
8303 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8304 Subtarget->is64Bit(),
8305 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8307 llvm_unreachable("Unknown TLS model.");
8310 if (Subtarget->isTargetDarwin()) {
8311 // Darwin only has one model of TLS. Lower to that.
8312 unsigned char OpFlag = 0;
8313 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8314 X86ISD::WrapperRIP : X86ISD::Wrapper;
8316 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8318 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8319 !Subtarget->is64Bit();
8321 OpFlag = X86II::MO_TLVP_PIC_BASE;
8323 OpFlag = X86II::MO_TLVP;
8325 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8326 GA->getValueType(0),
8327 GA->getOffset(), OpFlag);
8328 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8330 // With PIC32, the address is actually $g + Offset.
8332 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8333 DAG.getNode(X86ISD::GlobalBaseReg,
8334 SDLoc(), getPointerTy()),
8337 // Lowering the machine isd will make sure everything is in the right
8339 SDValue Chain = DAG.getEntryNode();
8340 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8341 SDValue Args[] = { Chain, Offset };
8342 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8344 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8345 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8346 MFI->setAdjustsStack(true);
8348 // And our return value (tls address) is in the standard call return value
8350 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8351 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8355 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8356 // Just use the implicit TLS architecture
8357 // Need to generate someting similar to:
8358 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8360 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8361 // mov rcx, qword [rdx+rcx*8]
8362 // mov eax, .tls$:tlsvar
8363 // [rax+rcx] contains the address
8364 // Windows 64bit: gs:0x58
8365 // Windows 32bit: fs:__tls_array
8367 // If GV is an alias then use the aliasee for determining
8368 // thread-localness.
8369 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8370 GV = GA->resolveAliasedGlobal(false);
8372 SDValue Chain = DAG.getEntryNode();
8374 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8375 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8376 // use its literal value of 0x2C.
8377 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8378 ? Type::getInt8PtrTy(*DAG.getContext(),
8380 : Type::getInt32PtrTy(*DAG.getContext(),
8383 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8384 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8385 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8387 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8388 MachinePointerInfo(Ptr),
8389 false, false, false, 0);
8391 // Load the _tls_index variable
8392 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8393 if (Subtarget->is64Bit())
8394 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8395 IDX, MachinePointerInfo(), MVT::i32,
8398 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8399 false, false, false, 0);
8401 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8403 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8405 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8406 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8407 false, false, false, 0);
8409 // Get the offset of start of .tls section
8410 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8411 GA->getValueType(0),
8412 GA->getOffset(), X86II::MO_SECREL);
8413 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8415 // The address of the thread local variable is the add of the thread
8416 // pointer with the offset of the variable.
8417 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8420 llvm_unreachable("TLS not implemented for this target.");
8423 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8424 /// and take a 2 x i32 value to shift plus a shift amount.
8425 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8426 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8427 EVT VT = Op.getValueType();
8428 unsigned VTBits = VT.getSizeInBits();
8430 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8431 SDValue ShOpLo = Op.getOperand(0);
8432 SDValue ShOpHi = Op.getOperand(1);
8433 SDValue ShAmt = Op.getOperand(2);
8434 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8435 DAG.getConstant(VTBits - 1, MVT::i8))
8436 : DAG.getConstant(0, VT);
8439 if (Op.getOpcode() == ISD::SHL_PARTS) {
8440 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8441 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8443 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8444 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8447 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8448 DAG.getConstant(VTBits, MVT::i8));
8449 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8450 AndNode, DAG.getConstant(0, MVT::i8));
8453 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8454 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8455 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8457 if (Op.getOpcode() == ISD::SHL_PARTS) {
8458 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8459 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8461 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8462 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8465 SDValue Ops[2] = { Lo, Hi };
8466 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8469 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8470 SelectionDAG &DAG) const {
8471 EVT SrcVT = Op.getOperand(0).getValueType();
8473 if (SrcVT.isVector())
8476 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8477 "Unknown SINT_TO_FP to lower!");
8479 // These are really Legal; return the operand so the caller accepts it as
8481 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8483 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8484 Subtarget->is64Bit()) {
8489 unsigned Size = SrcVT.getSizeInBits()/8;
8490 MachineFunction &MF = DAG.getMachineFunction();
8491 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8492 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8493 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8495 MachinePointerInfo::getFixedStack(SSFI),
8497 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8500 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8502 SelectionDAG &DAG) const {
8506 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8508 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8510 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8512 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8514 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8515 MachineMemOperand *MMO;
8517 int SSFI = FI->getIndex();
8519 DAG.getMachineFunction()
8520 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8521 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8523 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8524 StackSlot = StackSlot.getOperand(1);
8526 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8527 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8529 Tys, Ops, array_lengthof(Ops),
8533 Chain = Result.getValue(1);
8534 SDValue InFlag = Result.getValue(2);
8536 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8537 // shouldn't be necessary except that RFP cannot be live across
8538 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8539 MachineFunction &MF = DAG.getMachineFunction();
8540 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8541 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8542 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8543 Tys = DAG.getVTList(MVT::Other);
8545 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8547 MachineMemOperand *MMO =
8548 DAG.getMachineFunction()
8549 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8550 MachineMemOperand::MOStore, SSFISize, SSFISize);
8552 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8553 Ops, array_lengthof(Ops),
8554 Op.getValueType(), MMO);
8555 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8556 MachinePointerInfo::getFixedStack(SSFI),
8557 false, false, false, 0);
8563 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8564 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8565 SelectionDAG &DAG) const {
8566 // This algorithm is not obvious. Here it is what we're trying to output:
8569 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8570 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8574 pshufd $0x4e, %xmm0, %xmm1
8580 LLVMContext *Context = DAG.getContext();
8582 // Build some magic constants.
8583 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8584 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8585 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8587 SmallVector<Constant*,2> CV1;
8589 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8590 APInt(64, 0x4330000000000000ULL))));
8592 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8593 APInt(64, 0x4530000000000000ULL))));
8594 Constant *C1 = ConstantVector::get(CV1);
8595 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8597 // Load the 64-bit value into an XMM register.
8598 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8600 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8601 MachinePointerInfo::getConstantPool(),
8602 false, false, false, 16);
8603 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8604 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8607 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8608 MachinePointerInfo::getConstantPool(),
8609 false, false, false, 16);
8610 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8611 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8614 if (Subtarget->hasSSE3()) {
8615 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8616 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8618 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8619 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8621 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8622 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8626 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8627 DAG.getIntPtrConstant(0));
8630 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8631 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8632 SelectionDAG &DAG) const {
8634 // FP constant to bias correct the final result.
8635 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8638 // Load the 32-bit value into an XMM register.
8639 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8642 // Zero out the upper parts of the register.
8643 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8645 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8646 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8647 DAG.getIntPtrConstant(0));
8649 // Or the load with the bias.
8650 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8651 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8652 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8654 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8655 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8656 MVT::v2f64, Bias)));
8657 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8658 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8659 DAG.getIntPtrConstant(0));
8661 // Subtract the bias.
8662 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8664 // Handle final rounding.
8665 EVT DestVT = Op.getValueType();
8667 if (DestVT.bitsLT(MVT::f64))
8668 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8669 DAG.getIntPtrConstant(0));
8670 if (DestVT.bitsGT(MVT::f64))
8671 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8673 // Handle final rounding.
8677 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8678 SelectionDAG &DAG) const {
8679 SDValue N0 = Op.getOperand(0);
8680 EVT SVT = N0.getValueType();
8683 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8684 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8685 "Custom UINT_TO_FP is not supported!");
8687 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8688 SVT.getVectorNumElements());
8689 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8690 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8693 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8694 SelectionDAG &DAG) const {
8695 SDValue N0 = Op.getOperand(0);
8698 if (Op.getValueType().isVector())
8699 return lowerUINT_TO_FP_vec(Op, DAG);
8701 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8702 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8703 // the optimization here.
8704 if (DAG.SignBitIsZero(N0))
8705 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8707 EVT SrcVT = N0.getValueType();
8708 EVT DstVT = Op.getValueType();
8709 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8710 return LowerUINT_TO_FP_i64(Op, DAG);
8711 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8712 return LowerUINT_TO_FP_i32(Op, DAG);
8713 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8716 // Make a 64-bit buffer, and use it to build an FILD.
8717 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8718 if (SrcVT == MVT::i32) {
8719 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8720 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8721 getPointerTy(), StackSlot, WordOff);
8722 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8723 StackSlot, MachinePointerInfo(),
8725 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8726 OffsetSlot, MachinePointerInfo(),
8728 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8732 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8733 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8734 StackSlot, MachinePointerInfo(),
8736 // For i64 source, we need to add the appropriate power of 2 if the input
8737 // was negative. This is the same as the optimization in
8738 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8739 // we must be careful to do the computation in x87 extended precision, not
8740 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8741 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8742 MachineMemOperand *MMO =
8743 DAG.getMachineFunction()
8744 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8745 MachineMemOperand::MOLoad, 8, 8);
8747 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8748 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8749 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8750 array_lengthof(Ops), MVT::i64, MMO);
8752 APInt FF(32, 0x5F800000ULL);
8754 // Check whether the sign bit is set.
8755 SDValue SignSet = DAG.getSetCC(dl,
8756 getSetCCResultType(*DAG.getContext(), MVT::i64),
8757 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8760 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8761 SDValue FudgePtr = DAG.getConstantPool(
8762 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8765 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8766 SDValue Zero = DAG.getIntPtrConstant(0);
8767 SDValue Four = DAG.getIntPtrConstant(4);
8768 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8770 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8772 // Load the value out, extending it from f32 to f80.
8773 // FIXME: Avoid the extend by constructing the right constant pool?
8774 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8775 FudgePtr, MachinePointerInfo::getConstantPool(),
8776 MVT::f32, false, false, 4);
8777 // Extend everything to 80 bits to force it to be done on x87.
8778 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8779 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8782 std::pair<SDValue,SDValue>
8783 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8784 bool IsSigned, bool IsReplace) const {
8787 EVT DstTy = Op.getValueType();
8789 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8790 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8794 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8795 DstTy.getSimpleVT() >= MVT::i16 &&
8796 "Unknown FP_TO_INT to lower!");
8798 // These are really Legal.
8799 if (DstTy == MVT::i32 &&
8800 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8801 return std::make_pair(SDValue(), SDValue());
8802 if (Subtarget->is64Bit() &&
8803 DstTy == MVT::i64 &&
8804 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8805 return std::make_pair(SDValue(), SDValue());
8807 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8808 // stack slot, or into the FTOL runtime function.
8809 MachineFunction &MF = DAG.getMachineFunction();
8810 unsigned MemSize = DstTy.getSizeInBits()/8;
8811 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8812 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8815 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8816 Opc = X86ISD::WIN_FTOL;
8818 switch (DstTy.getSimpleVT().SimpleTy) {
8819 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8820 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8821 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8822 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8825 SDValue Chain = DAG.getEntryNode();
8826 SDValue Value = Op.getOperand(0);
8827 EVT TheVT = Op.getOperand(0).getValueType();
8828 // FIXME This causes a redundant load/store if the SSE-class value is already
8829 // in memory, such as if it is on the callstack.
8830 if (isScalarFPTypeInSSEReg(TheVT)) {
8831 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8832 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8833 MachinePointerInfo::getFixedStack(SSFI),
8835 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8837 Chain, StackSlot, DAG.getValueType(TheVT)
8840 MachineMemOperand *MMO =
8841 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8842 MachineMemOperand::MOLoad, MemSize, MemSize);
8843 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8844 array_lengthof(Ops), DstTy, MMO);
8845 Chain = Value.getValue(1);
8846 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8847 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8850 MachineMemOperand *MMO =
8851 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8852 MachineMemOperand::MOStore, MemSize, MemSize);
8854 if (Opc != X86ISD::WIN_FTOL) {
8855 // Build the FP_TO_INT*_IN_MEM
8856 SDValue Ops[] = { Chain, Value, StackSlot };
8857 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8858 Ops, array_lengthof(Ops), DstTy,
8860 return std::make_pair(FIST, StackSlot);
8862 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8863 DAG.getVTList(MVT::Other, MVT::Glue),
8865 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8866 MVT::i32, ftol.getValue(1));
8867 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8868 MVT::i32, eax.getValue(2));
8869 SDValue Ops[] = { eax, edx };
8870 SDValue pair = IsReplace
8871 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8872 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8873 return std::make_pair(pair, SDValue());
8877 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8878 const X86Subtarget *Subtarget) {
8879 MVT VT = Op->getSimpleValueType(0);
8880 SDValue In = Op->getOperand(0);
8881 MVT InVT = In.getSimpleValueType();
8884 // Optimize vectors in AVX mode:
8887 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8888 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8889 // Concat upper and lower parts.
8892 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8893 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8894 // Concat upper and lower parts.
8897 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8898 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8899 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8902 if (Subtarget->hasInt256())
8903 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8905 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8906 SDValue Undef = DAG.getUNDEF(InVT);
8907 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8908 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8909 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8911 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8912 VT.getVectorNumElements()/2);
8914 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8915 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8917 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8920 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8921 SelectionDAG &DAG) {
8922 MVT VT = Op->getValueType(0).getSimpleVT();
8923 SDValue In = Op->getOperand(0);
8924 MVT InVT = In.getValueType().getSimpleVT();
8926 unsigned int NumElts = VT.getVectorNumElements();
8927 if (NumElts != 8 && NumElts != 16)
8930 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8931 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8933 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8934 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8935 // Now we have only mask extension
8936 assert(InVT.getVectorElementType() == MVT::i1);
8937 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8938 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8939 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8940 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8941 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8942 MachinePointerInfo::getConstantPool(),
8943 false, false, false, Alignment);
8945 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8946 if (VT.is512BitVector())
8948 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8951 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8952 SelectionDAG &DAG) {
8953 if (Subtarget->hasFp256()) {
8954 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8962 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8963 SelectionDAG &DAG) {
8965 MVT VT = Op.getSimpleValueType();
8966 SDValue In = Op.getOperand(0);
8967 MVT SVT = In.getSimpleValueType();
8969 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8970 return LowerZERO_EXTEND_AVX512(Op, DAG);
8972 if (Subtarget->hasFp256()) {
8973 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8978 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
8979 VT.getVectorNumElements() != SVT.getVectorNumElements());
8983 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8985 MVT VT = Op.getSimpleValueType();
8986 SDValue In = Op.getOperand(0);
8987 MVT InVT = In.getSimpleValueType();
8988 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8989 "Invalid TRUNCATE operation");
8991 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8992 if (VT.getVectorElementType().getSizeInBits() >=8)
8993 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
8995 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
8996 unsigned NumElts = InVT.getVectorNumElements();
8997 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
8998 if (InVT.getSizeInBits() < 512) {
8999 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9000 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9003 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9004 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9005 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9006 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9007 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9008 MachinePointerInfo::getConstantPool(),
9009 false, false, false, Alignment);
9010 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9011 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9012 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9015 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9016 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9017 if (Subtarget->hasInt256()) {
9018 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9019 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9020 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9022 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9023 DAG.getIntPtrConstant(0));
9026 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9027 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9028 DAG.getIntPtrConstant(0));
9029 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9030 DAG.getIntPtrConstant(2));
9032 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9033 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9036 static const int ShufMask1[] = {0, 2, 0, 0};
9037 SDValue Undef = DAG.getUNDEF(VT);
9038 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9039 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9041 // The MOVLHPS mask:
9042 static const int ShufMask2[] = {0, 1, 4, 5};
9043 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9046 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9047 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9048 if (Subtarget->hasInt256()) {
9049 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9051 SmallVector<SDValue,32> pshufbMask;
9052 for (unsigned i = 0; i < 2; ++i) {
9053 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9054 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9055 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9056 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9057 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9058 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9059 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9060 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9061 for (unsigned j = 0; j < 8; ++j)
9062 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9064 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9065 &pshufbMask[0], 32);
9066 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9067 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9069 static const int ShufMask[] = {0, 2, -1, -1};
9070 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9072 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9073 DAG.getIntPtrConstant(0));
9074 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9077 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9078 DAG.getIntPtrConstant(0));
9080 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9081 DAG.getIntPtrConstant(4));
9083 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9084 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9087 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9088 -1, -1, -1, -1, -1, -1, -1, -1};
9090 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9091 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9092 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9094 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9095 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9097 // The MOVLHPS Mask:
9098 static const int ShufMask2[] = {0, 1, 4, 5};
9099 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9100 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9103 // Handle truncation of V256 to V128 using shuffles.
9104 if (!VT.is128BitVector() || !InVT.is256BitVector())
9107 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9109 unsigned NumElems = VT.getVectorNumElements();
9110 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9113 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9114 // Prepare truncation shuffle mask
9115 for (unsigned i = 0; i != NumElems; ++i)
9117 SDValue V = DAG.getVectorShuffle(NVT, DL,
9118 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9119 DAG.getUNDEF(NVT), &MaskVec[0]);
9120 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9121 DAG.getIntPtrConstant(0));
9124 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9125 SelectionDAG &DAG) const {
9126 MVT VT = Op.getSimpleValueType();
9127 if (VT.isVector()) {
9128 if (VT == MVT::v8i16)
9129 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9130 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9131 MVT::v8i32, Op.getOperand(0)));
9135 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9136 /*IsSigned=*/ true, /*IsReplace=*/ false);
9137 SDValue FIST = Vals.first, StackSlot = Vals.second;
9138 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9139 if (FIST.getNode() == 0) return Op;
9141 if (StackSlot.getNode())
9143 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9144 FIST, StackSlot, MachinePointerInfo(),
9145 false, false, false, 0);
9147 // The node is the result.
9151 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9152 SelectionDAG &DAG) const {
9153 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9154 /*IsSigned=*/ false, /*IsReplace=*/ false);
9155 SDValue FIST = Vals.first, StackSlot = Vals.second;
9156 assert(FIST.getNode() && "Unexpected failure");
9158 if (StackSlot.getNode())
9160 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9161 FIST, StackSlot, MachinePointerInfo(),
9162 false, false, false, 0);
9164 // The node is the result.
9168 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9170 MVT VT = Op.getSimpleValueType();
9171 SDValue In = Op.getOperand(0);
9172 MVT SVT = In.getSimpleValueType();
9174 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9176 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9177 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9178 In, DAG.getUNDEF(SVT)));
9181 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9182 LLVMContext *Context = DAG.getContext();
9184 MVT VT = Op.getSimpleValueType();
9186 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9187 if (VT.isVector()) {
9188 EltVT = VT.getVectorElementType();
9189 NumElts = VT.getVectorNumElements();
9192 if (EltVT == MVT::f64)
9193 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9194 APInt(64, ~(1ULL << 63))));
9196 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9197 APInt(32, ~(1U << 31))));
9198 C = ConstantVector::getSplat(NumElts, C);
9199 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9200 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9201 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9202 MachinePointerInfo::getConstantPool(),
9203 false, false, false, Alignment);
9204 if (VT.isVector()) {
9205 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9206 return DAG.getNode(ISD::BITCAST, dl, VT,
9207 DAG.getNode(ISD::AND, dl, ANDVT,
9208 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9210 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9212 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9215 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9216 LLVMContext *Context = DAG.getContext();
9218 MVT VT = Op.getSimpleValueType();
9220 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9221 if (VT.isVector()) {
9222 EltVT = VT.getVectorElementType();
9223 NumElts = VT.getVectorNumElements();
9226 if (EltVT == MVT::f64)
9227 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9228 APInt(64, 1ULL << 63)));
9230 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9231 APInt(32, 1U << 31)));
9232 C = ConstantVector::getSplat(NumElts, C);
9233 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9234 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9235 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9236 MachinePointerInfo::getConstantPool(),
9237 false, false, false, Alignment);
9238 if (VT.isVector()) {
9239 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9240 return DAG.getNode(ISD::BITCAST, dl, VT,
9241 DAG.getNode(ISD::XOR, dl, XORVT,
9242 DAG.getNode(ISD::BITCAST, dl, XORVT,
9244 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9247 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9250 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9251 LLVMContext *Context = DAG.getContext();
9252 SDValue Op0 = Op.getOperand(0);
9253 SDValue Op1 = Op.getOperand(1);
9255 MVT VT = Op.getSimpleValueType();
9256 MVT SrcVT = Op1.getSimpleValueType();
9258 // If second operand is smaller, extend it first.
9259 if (SrcVT.bitsLT(VT)) {
9260 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9263 // And if it is bigger, shrink it first.
9264 if (SrcVT.bitsGT(VT)) {
9265 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9269 // At this point the operands and the result should have the same
9270 // type, and that won't be f80 since that is not custom lowered.
9272 // First get the sign bit of second operand.
9273 SmallVector<Constant*,4> CV;
9274 if (SrcVT == MVT::f64) {
9275 const fltSemantics &Sem = APFloat::IEEEdouble;
9276 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9277 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9279 const fltSemantics &Sem = APFloat::IEEEsingle;
9280 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9281 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9282 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9283 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9285 Constant *C = ConstantVector::get(CV);
9286 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9287 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9288 MachinePointerInfo::getConstantPool(),
9289 false, false, false, 16);
9290 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9292 // Shift sign bit right or left if the two operands have different types.
9293 if (SrcVT.bitsGT(VT)) {
9294 // Op0 is MVT::f32, Op1 is MVT::f64.
9295 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9296 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9297 DAG.getConstant(32, MVT::i32));
9298 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9299 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9300 DAG.getIntPtrConstant(0));
9303 // Clear first operand sign bit.
9305 if (VT == MVT::f64) {
9306 const fltSemantics &Sem = APFloat::IEEEdouble;
9307 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9308 APInt(64, ~(1ULL << 63)))));
9309 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9311 const fltSemantics &Sem = APFloat::IEEEsingle;
9312 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9313 APInt(32, ~(1U << 31)))));
9314 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9315 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9316 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9318 C = ConstantVector::get(CV);
9319 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9320 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9321 MachinePointerInfo::getConstantPool(),
9322 false, false, false, 16);
9323 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9325 // Or the value with the sign bit.
9326 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9329 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9330 SDValue N0 = Op.getOperand(0);
9332 MVT VT = Op.getSimpleValueType();
9334 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9335 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9336 DAG.getConstant(1, VT));
9337 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9340 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9342 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9343 SelectionDAG &DAG) {
9344 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9346 if (!Subtarget->hasSSE41())
9349 if (!Op->hasOneUse())
9352 SDNode *N = Op.getNode();
9355 SmallVector<SDValue, 8> Opnds;
9356 DenseMap<SDValue, unsigned> VecInMap;
9357 EVT VT = MVT::Other;
9359 // Recognize a special case where a vector is casted into wide integer to
9361 Opnds.push_back(N->getOperand(0));
9362 Opnds.push_back(N->getOperand(1));
9364 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9365 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9366 // BFS traverse all OR'd operands.
9367 if (I->getOpcode() == ISD::OR) {
9368 Opnds.push_back(I->getOperand(0));
9369 Opnds.push_back(I->getOperand(1));
9370 // Re-evaluate the number of nodes to be traversed.
9371 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9375 // Quit if a non-EXTRACT_VECTOR_ELT
9376 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9379 // Quit if without a constant index.
9380 SDValue Idx = I->getOperand(1);
9381 if (!isa<ConstantSDNode>(Idx))
9384 SDValue ExtractedFromVec = I->getOperand(0);
9385 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9386 if (M == VecInMap.end()) {
9387 VT = ExtractedFromVec.getValueType();
9388 // Quit if not 128/256-bit vector.
9389 if (!VT.is128BitVector() && !VT.is256BitVector())
9391 // Quit if not the same type.
9392 if (VecInMap.begin() != VecInMap.end() &&
9393 VT != VecInMap.begin()->first.getValueType())
9395 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9397 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9400 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9401 "Not extracted from 128-/256-bit vector.");
9403 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9404 SmallVector<SDValue, 8> VecIns;
9406 for (DenseMap<SDValue, unsigned>::const_iterator
9407 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9408 // Quit if not all elements are used.
9409 if (I->second != FullMask)
9411 VecIns.push_back(I->first);
9414 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9416 // Cast all vectors into TestVT for PTEST.
9417 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9418 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9420 // If more than one full vectors are evaluated, OR them first before PTEST.
9421 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9422 // Each iteration will OR 2 nodes and append the result until there is only
9423 // 1 node left, i.e. the final OR'd value of all vectors.
9424 SDValue LHS = VecIns[Slot];
9425 SDValue RHS = VecIns[Slot + 1];
9426 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9429 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9430 VecIns.back(), VecIns.back());
9433 /// Emit nodes that will be selected as "test Op0,Op0", or something
9435 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9436 SelectionDAG &DAG) const {
9439 // CF and OF aren't always set the way we want. Determine which
9440 // of these we need.
9441 bool NeedCF = false;
9442 bool NeedOF = false;
9445 case X86::COND_A: case X86::COND_AE:
9446 case X86::COND_B: case X86::COND_BE:
9449 case X86::COND_G: case X86::COND_GE:
9450 case X86::COND_L: case X86::COND_LE:
9451 case X86::COND_O: case X86::COND_NO:
9456 // See if we can use the EFLAGS value from the operand instead of
9457 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9458 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9459 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9460 // Emit a CMP with 0, which is the TEST pattern.
9461 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9462 DAG.getConstant(0, Op.getValueType()));
9464 unsigned Opcode = 0;
9465 unsigned NumOperands = 0;
9467 // Truncate operations may prevent the merge of the SETCC instruction
9468 // and the arithmetic instruction before it. Attempt to truncate the operands
9469 // of the arithmetic instruction and use a reduced bit-width instruction.
9470 bool NeedTruncation = false;
9471 SDValue ArithOp = Op;
9472 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9473 SDValue Arith = Op->getOperand(0);
9474 // Both the trunc and the arithmetic op need to have one user each.
9475 if (Arith->hasOneUse())
9476 switch (Arith.getOpcode()) {
9483 NeedTruncation = true;
9489 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9490 // which may be the result of a CAST. We use the variable 'Op', which is the
9491 // non-casted variable when we check for possible users.
9492 switch (ArithOp.getOpcode()) {
9494 // Due to an isel shortcoming, be conservative if this add is likely to be
9495 // selected as part of a load-modify-store instruction. When the root node
9496 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9497 // uses of other nodes in the match, such as the ADD in this case. This
9498 // leads to the ADD being left around and reselected, with the result being
9499 // two adds in the output. Alas, even if none our users are stores, that
9500 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9501 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9502 // climbing the DAG back to the root, and it doesn't seem to be worth the
9504 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9505 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9506 if (UI->getOpcode() != ISD::CopyToReg &&
9507 UI->getOpcode() != ISD::SETCC &&
9508 UI->getOpcode() != ISD::STORE)
9511 if (ConstantSDNode *C =
9512 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9513 // An add of one will be selected as an INC.
9514 if (C->getAPIntValue() == 1) {
9515 Opcode = X86ISD::INC;
9520 // An add of negative one (subtract of one) will be selected as a DEC.
9521 if (C->getAPIntValue().isAllOnesValue()) {
9522 Opcode = X86ISD::DEC;
9528 // Otherwise use a regular EFLAGS-setting add.
9529 Opcode = X86ISD::ADD;
9533 // If the primary and result isn't used, don't bother using X86ISD::AND,
9534 // because a TEST instruction will be better.
9535 bool NonFlagUse = false;
9536 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9537 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9539 unsigned UOpNo = UI.getOperandNo();
9540 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9541 // Look pass truncate.
9542 UOpNo = User->use_begin().getOperandNo();
9543 User = *User->use_begin();
9546 if (User->getOpcode() != ISD::BRCOND &&
9547 User->getOpcode() != ISD::SETCC &&
9548 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9561 // Due to the ISEL shortcoming noted above, be conservative if this op is
9562 // likely to be selected as part of a load-modify-store instruction.
9563 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9564 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9565 if (UI->getOpcode() == ISD::STORE)
9568 // Otherwise use a regular EFLAGS-setting instruction.
9569 switch (ArithOp.getOpcode()) {
9570 default: llvm_unreachable("unexpected operator!");
9571 case ISD::SUB: Opcode = X86ISD::SUB; break;
9572 case ISD::XOR: Opcode = X86ISD::XOR; break;
9573 case ISD::AND: Opcode = X86ISD::AND; break;
9575 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9576 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9577 if (EFLAGS.getNode())
9580 Opcode = X86ISD::OR;
9594 return SDValue(Op.getNode(), 1);
9600 // If we found that truncation is beneficial, perform the truncation and
9602 if (NeedTruncation) {
9603 EVT VT = Op.getValueType();
9604 SDValue WideVal = Op->getOperand(0);
9605 EVT WideVT = WideVal.getValueType();
9606 unsigned ConvertedOp = 0;
9607 // Use a target machine opcode to prevent further DAGCombine
9608 // optimizations that may separate the arithmetic operations
9609 // from the setcc node.
9610 switch (WideVal.getOpcode()) {
9612 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9613 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9614 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9615 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9616 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9620 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9621 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9622 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9623 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9624 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9630 // Emit a CMP with 0, which is the TEST pattern.
9631 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9632 DAG.getConstant(0, Op.getValueType()));
9634 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9635 SmallVector<SDValue, 4> Ops;
9636 for (unsigned i = 0; i != NumOperands; ++i)
9637 Ops.push_back(Op.getOperand(i));
9639 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9640 DAG.ReplaceAllUsesWith(Op, New);
9641 return SDValue(New.getNode(), 1);
9644 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9646 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9647 SelectionDAG &DAG) const {
9648 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9649 if (C->getAPIntValue() == 0)
9650 return EmitTest(Op0, X86CC, DAG);
9653 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9654 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9655 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9656 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9657 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9659 return SDValue(Sub.getNode(), 1);
9661 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9664 /// Convert a comparison if required by the subtarget.
9665 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9666 SelectionDAG &DAG) const {
9667 // If the subtarget does not support the FUCOMI instruction, floating-point
9668 // comparisons have to be converted.
9669 if (Subtarget->hasCMov() ||
9670 Cmp.getOpcode() != X86ISD::CMP ||
9671 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9672 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9675 // The instruction selector will select an FUCOM instruction instead of
9676 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9677 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9678 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9680 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9681 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9682 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9683 DAG.getConstant(8, MVT::i8));
9684 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9685 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9688 static bool isAllOnes(SDValue V) {
9689 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9690 return C && C->isAllOnesValue();
9693 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9694 /// if it's possible.
9695 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9696 SDLoc dl, SelectionDAG &DAG) const {
9697 SDValue Op0 = And.getOperand(0);
9698 SDValue Op1 = And.getOperand(1);
9699 if (Op0.getOpcode() == ISD::TRUNCATE)
9700 Op0 = Op0.getOperand(0);
9701 if (Op1.getOpcode() == ISD::TRUNCATE)
9702 Op1 = Op1.getOperand(0);
9705 if (Op1.getOpcode() == ISD::SHL)
9706 std::swap(Op0, Op1);
9707 if (Op0.getOpcode() == ISD::SHL) {
9708 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9709 if (And00C->getZExtValue() == 1) {
9710 // If we looked past a truncate, check that it's only truncating away
9712 unsigned BitWidth = Op0.getValueSizeInBits();
9713 unsigned AndBitWidth = And.getValueSizeInBits();
9714 if (BitWidth > AndBitWidth) {
9716 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9717 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9721 RHS = Op0.getOperand(1);
9723 } else if (Op1.getOpcode() == ISD::Constant) {
9724 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9725 uint64_t AndRHSVal = AndRHS->getZExtValue();
9726 SDValue AndLHS = Op0;
9728 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9729 LHS = AndLHS.getOperand(0);
9730 RHS = AndLHS.getOperand(1);
9733 // Use BT if the immediate can't be encoded in a TEST instruction.
9734 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9736 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9740 if (LHS.getNode()) {
9741 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9742 // instruction. Since the shift amount is in-range-or-undefined, we know
9743 // that doing a bittest on the i32 value is ok. We extend to i32 because
9744 // the encoding for the i16 version is larger than the i32 version.
9745 // Also promote i16 to i32 for performance / code size reason.
9746 if (LHS.getValueType() == MVT::i8 ||
9747 LHS.getValueType() == MVT::i16)
9748 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9750 // If the operand types disagree, extend the shift amount to match. Since
9751 // BT ignores high bits (like shifts) we can use anyextend.
9752 if (LHS.getValueType() != RHS.getValueType())
9753 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9755 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9756 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9757 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9758 DAG.getConstant(Cond, MVT::i8), BT);
9764 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9766 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9771 // SSE Condition code mapping:
9780 switch (SetCCOpcode) {
9781 default: llvm_unreachable("Unexpected SETCC condition");
9783 case ISD::SETEQ: SSECC = 0; break;
9785 case ISD::SETGT: Swap = true; // Fallthrough
9787 case ISD::SETOLT: SSECC = 1; break;
9789 case ISD::SETGE: Swap = true; // Fallthrough
9791 case ISD::SETOLE: SSECC = 2; break;
9792 case ISD::SETUO: SSECC = 3; break;
9794 case ISD::SETNE: SSECC = 4; break;
9795 case ISD::SETULE: Swap = true; // Fallthrough
9796 case ISD::SETUGE: SSECC = 5; break;
9797 case ISD::SETULT: Swap = true; // Fallthrough
9798 case ISD::SETUGT: SSECC = 6; break;
9799 case ISD::SETO: SSECC = 7; break;
9801 case ISD::SETONE: SSECC = 8; break;
9804 std::swap(Op0, Op1);
9809 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9810 // ones, and then concatenate the result back.
9811 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9812 MVT VT = Op.getSimpleValueType();
9814 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9815 "Unsupported value type for operation");
9817 unsigned NumElems = VT.getVectorNumElements();
9819 SDValue CC = Op.getOperand(2);
9821 // Extract the LHS vectors
9822 SDValue LHS = Op.getOperand(0);
9823 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9824 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9826 // Extract the RHS vectors
9827 SDValue RHS = Op.getOperand(1);
9828 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9829 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9831 // Issue the operation on the smaller types and concatenate the result back
9832 MVT EltVT = VT.getVectorElementType();
9833 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9834 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9835 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9836 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9839 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9840 SDValue Op0 = Op.getOperand(0);
9841 SDValue Op1 = Op.getOperand(1);
9842 SDValue CC = Op.getOperand(2);
9843 MVT VT = Op.getSimpleValueType();
9845 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9846 Op.getValueType().getScalarType() == MVT::i1 &&
9847 "Cannot set masked compare for this operation");
9849 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9852 bool Unsigned = false;
9854 switch (SetCCOpcode) {
9855 default: llvm_unreachable("Unexpected SETCC condition");
9856 case ISD::SETNE: SSECC = 4; break;
9857 case ISD::SETEQ: SSECC = 0; break;
9858 case ISD::SETUGT: Unsigned = true;
9859 case ISD::SETGT: SSECC = 6; break; // NLE
9860 case ISD::SETULT: Unsigned = true;
9861 case ISD::SETLT: SSECC = 1; break;
9862 case ISD::SETUGE: Unsigned = true;
9863 case ISD::SETGE: SSECC = 5; break; // NLT
9864 case ISD::SETULE: Unsigned = true;
9865 case ISD::SETLE: SSECC = 2; break;
9867 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9868 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9869 DAG.getConstant(SSECC, MVT::i8));
9873 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9874 SelectionDAG &DAG) {
9875 SDValue Op0 = Op.getOperand(0);
9876 SDValue Op1 = Op.getOperand(1);
9877 SDValue CC = Op.getOperand(2);
9878 MVT VT = Op.getSimpleValueType();
9879 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9880 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9885 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9886 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9889 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9890 unsigned Opc = X86ISD::CMPP;
9891 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9892 assert(VT.getVectorNumElements() <= 16);
9895 // In the two special cases we can't handle, emit two comparisons.
9898 unsigned CombineOpc;
9899 if (SetCCOpcode == ISD::SETUEQ) {
9900 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9902 assert(SetCCOpcode == ISD::SETONE);
9903 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9906 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9907 DAG.getConstant(CC0, MVT::i8));
9908 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9909 DAG.getConstant(CC1, MVT::i8));
9910 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9912 // Handle all other FP comparisons here.
9913 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9914 DAG.getConstant(SSECC, MVT::i8));
9917 // Break 256-bit integer vector compare into smaller ones.
9918 if (VT.is256BitVector() && !Subtarget->hasInt256())
9919 return Lower256IntVSETCC(Op, DAG);
9921 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9922 EVT OpVT = Op1.getValueType();
9923 if (Subtarget->hasAVX512()) {
9924 if (Op1.getValueType().is512BitVector() ||
9925 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9926 return LowerIntVSETCC_AVX512(Op, DAG);
9928 // In AVX-512 architecture setcc returns mask with i1 elements,
9929 // But there is no compare instruction for i8 and i16 elements.
9930 // We are not talking about 512-bit operands in this case, these
9931 // types are illegal.
9933 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9934 OpVT.getVectorElementType().getSizeInBits() >= 8))
9935 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9936 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9939 // We are handling one of the integer comparisons here. Since SSE only has
9940 // GT and EQ comparisons for integer, swapping operands and multiple
9941 // operations may be required for some comparisons.
9943 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9945 switch (SetCCOpcode) {
9946 default: llvm_unreachable("Unexpected SETCC condition");
9947 case ISD::SETNE: Invert = true;
9948 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9949 case ISD::SETLT: Swap = true;
9950 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9951 case ISD::SETGE: Swap = true;
9952 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9953 Invert = true; break;
9954 case ISD::SETULT: Swap = true;
9955 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9956 FlipSigns = true; break;
9957 case ISD::SETUGE: Swap = true;
9958 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9959 FlipSigns = true; Invert = true; break;
9962 // Special case: Use min/max operations for SETULE/SETUGE
9963 MVT VET = VT.getVectorElementType();
9965 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9966 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9969 switch (SetCCOpcode) {
9971 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9972 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9975 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9979 std::swap(Op0, Op1);
9981 // Check that the operation in question is available (most are plain SSE2,
9982 // but PCMPGTQ and PCMPEQQ have different requirements).
9983 if (VT == MVT::v2i64) {
9984 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9985 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9987 // First cast everything to the right type.
9988 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9989 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9991 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9992 // bits of the inputs before performing those operations. The lower
9993 // compare is always unsigned.
9996 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9998 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9999 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10000 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10001 Sign, Zero, Sign, Zero);
10003 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10004 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10006 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10007 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10008 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10010 // Create masks for only the low parts/high parts of the 64 bit integers.
10011 static const int MaskHi[] = { 1, 1, 3, 3 };
10012 static const int MaskLo[] = { 0, 0, 2, 2 };
10013 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10014 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10015 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10017 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10018 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10021 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10023 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10026 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10027 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10028 // pcmpeqd + pshufd + pand.
10029 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10031 // First cast everything to the right type.
10032 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10033 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10036 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10038 // Make sure the lower and upper halves are both all-ones.
10039 static const int Mask[] = { 1, 0, 3, 2 };
10040 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10041 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10044 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10046 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10050 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10051 // bits of the inputs before performing those operations.
10053 EVT EltVT = VT.getVectorElementType();
10054 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10055 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10056 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10059 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10061 // If the logical-not of the result is required, perform that now.
10063 Result = DAG.getNOT(dl, Result, VT);
10066 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10071 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10073 MVT VT = Op.getSimpleValueType();
10075 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10077 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10078 SDValue Op0 = Op.getOperand(0);
10079 SDValue Op1 = Op.getOperand(1);
10081 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10083 // Optimize to BT if possible.
10084 // Lower (X & (1 << N)) == 0 to BT(X, N).
10085 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10086 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10087 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10088 Op1.getOpcode() == ISD::Constant &&
10089 cast<ConstantSDNode>(Op1)->isNullValue() &&
10090 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10091 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10092 if (NewSetCC.getNode())
10096 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10098 if (Op1.getOpcode() == ISD::Constant &&
10099 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10100 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10101 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10103 // If the input is a setcc, then reuse the input setcc or use a new one with
10104 // the inverted condition.
10105 if (Op0.getOpcode() == X86ISD::SETCC) {
10106 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10107 bool Invert = (CC == ISD::SETNE) ^
10108 cast<ConstantSDNode>(Op1)->isNullValue();
10109 if (!Invert) return Op0;
10111 CCode = X86::GetOppositeBranchCondition(CCode);
10112 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10113 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10117 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10118 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10119 if (X86CC == X86::COND_INVALID)
10122 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10123 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10124 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10125 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10128 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10129 static bool isX86LogicalCmp(SDValue Op) {
10130 unsigned Opc = Op.getNode()->getOpcode();
10131 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10132 Opc == X86ISD::SAHF)
10134 if (Op.getResNo() == 1 &&
10135 (Opc == X86ISD::ADD ||
10136 Opc == X86ISD::SUB ||
10137 Opc == X86ISD::ADC ||
10138 Opc == X86ISD::SBB ||
10139 Opc == X86ISD::SMUL ||
10140 Opc == X86ISD::UMUL ||
10141 Opc == X86ISD::INC ||
10142 Opc == X86ISD::DEC ||
10143 Opc == X86ISD::OR ||
10144 Opc == X86ISD::XOR ||
10145 Opc == X86ISD::AND))
10148 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10154 static bool isZero(SDValue V) {
10155 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10156 return C && C->isNullValue();
10159 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10160 if (V.getOpcode() != ISD::TRUNCATE)
10163 SDValue VOp0 = V.getOperand(0);
10164 unsigned InBits = VOp0.getValueSizeInBits();
10165 unsigned Bits = V.getValueSizeInBits();
10166 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10169 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10170 bool addTest = true;
10171 SDValue Cond = Op.getOperand(0);
10172 SDValue Op1 = Op.getOperand(1);
10173 SDValue Op2 = Op.getOperand(2);
10175 EVT VT = Op1.getValueType();
10178 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10179 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10180 // sequence later on.
10181 if (Cond.getOpcode() == ISD::SETCC &&
10182 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10183 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10184 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10185 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10186 int SSECC = translateX86FSETCC(
10187 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10190 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10191 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10192 DAG.getConstant(SSECC, MVT::i8));
10193 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10194 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10195 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10199 if (Cond.getOpcode() == ISD::SETCC) {
10200 SDValue NewCond = LowerSETCC(Cond, DAG);
10201 if (NewCond.getNode())
10205 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10206 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10207 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10208 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10209 if (Cond.getOpcode() == X86ISD::SETCC &&
10210 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10211 isZero(Cond.getOperand(1).getOperand(1))) {
10212 SDValue Cmp = Cond.getOperand(1);
10214 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10216 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10217 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10218 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10220 SDValue CmpOp0 = Cmp.getOperand(0);
10221 // Apply further optimizations for special cases
10222 // (select (x != 0), -1, 0) -> neg & sbb
10223 // (select (x == 0), 0, -1) -> neg & sbb
10224 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10225 if (YC->isNullValue() &&
10226 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10227 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10228 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10229 DAG.getConstant(0, CmpOp0.getValueType()),
10231 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10232 DAG.getConstant(X86::COND_B, MVT::i8),
10233 SDValue(Neg.getNode(), 1));
10237 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10238 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10239 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10241 SDValue Res = // Res = 0 or -1.
10242 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10243 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10245 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10246 Res = DAG.getNOT(DL, Res, Res.getValueType());
10248 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10249 if (N2C == 0 || !N2C->isNullValue())
10250 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10255 // Look past (and (setcc_carry (cmp ...)), 1).
10256 if (Cond.getOpcode() == ISD::AND &&
10257 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10259 if (C && C->getAPIntValue() == 1)
10260 Cond = Cond.getOperand(0);
10263 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10264 // setting operand in place of the X86ISD::SETCC.
10265 unsigned CondOpcode = Cond.getOpcode();
10266 if (CondOpcode == X86ISD::SETCC ||
10267 CondOpcode == X86ISD::SETCC_CARRY) {
10268 CC = Cond.getOperand(0);
10270 SDValue Cmp = Cond.getOperand(1);
10271 unsigned Opc = Cmp.getOpcode();
10272 MVT VT = Op.getSimpleValueType();
10274 bool IllegalFPCMov = false;
10275 if (VT.isFloatingPoint() && !VT.isVector() &&
10276 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10277 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10279 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10280 Opc == X86ISD::BT) { // FIXME
10284 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10285 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10286 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10287 Cond.getOperand(0).getValueType() != MVT::i8)) {
10288 SDValue LHS = Cond.getOperand(0);
10289 SDValue RHS = Cond.getOperand(1);
10290 unsigned X86Opcode;
10293 switch (CondOpcode) {
10294 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10295 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10296 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10297 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10298 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10299 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10300 default: llvm_unreachable("unexpected overflowing operator");
10302 if (CondOpcode == ISD::UMULO)
10303 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10306 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10308 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10310 if (CondOpcode == ISD::UMULO)
10311 Cond = X86Op.getValue(2);
10313 Cond = X86Op.getValue(1);
10315 CC = DAG.getConstant(X86Cond, MVT::i8);
10320 // Look pass the truncate if the high bits are known zero.
10321 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10322 Cond = Cond.getOperand(0);
10324 // We know the result of AND is compared against zero. Try to match
10326 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10327 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10328 if (NewSetCC.getNode()) {
10329 CC = NewSetCC.getOperand(0);
10330 Cond = NewSetCC.getOperand(1);
10337 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10338 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10341 // a < b ? -1 : 0 -> RES = ~setcc_carry
10342 // a < b ? 0 : -1 -> RES = setcc_carry
10343 // a >= b ? -1 : 0 -> RES = setcc_carry
10344 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10345 if (Cond.getOpcode() == X86ISD::SUB) {
10346 Cond = ConvertCmpIfNecessary(Cond, DAG);
10347 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10349 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10350 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10351 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10352 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10353 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10354 return DAG.getNOT(DL, Res, Res.getValueType());
10359 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10360 // widen the cmov and push the truncate through. This avoids introducing a new
10361 // branch during isel and doesn't add any extensions.
10362 if (Op.getValueType() == MVT::i8 &&
10363 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10364 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10365 if (T1.getValueType() == T2.getValueType() &&
10366 // Blacklist CopyFromReg to avoid partial register stalls.
10367 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10368 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10369 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10370 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10374 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10375 // condition is true.
10376 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10377 SDValue Ops[] = { Op2, Op1, CC, Cond };
10378 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10381 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10382 MVT VT = Op->getSimpleValueType(0);
10383 SDValue In = Op->getOperand(0);
10384 MVT InVT = In.getSimpleValueType();
10387 unsigned int NumElts = VT.getVectorNumElements();
10388 if (NumElts != 8 && NumElts != 16)
10391 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10392 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10394 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10395 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10397 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10398 Constant *C = ConstantInt::get(*DAG.getContext(),
10399 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10401 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10402 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10403 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10404 MachinePointerInfo::getConstantPool(),
10405 false, false, false, Alignment);
10406 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10407 if (VT.is512BitVector())
10409 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10412 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10413 SelectionDAG &DAG) {
10414 MVT VT = Op->getSimpleValueType(0);
10415 SDValue In = Op->getOperand(0);
10416 MVT InVT = In.getSimpleValueType();
10419 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10420 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10422 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10423 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10424 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10427 if (Subtarget->hasInt256())
10428 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10430 // Optimize vectors in AVX mode
10431 // Sign extend v8i16 to v8i32 and
10434 // Divide input vector into two parts
10435 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10436 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10437 // concat the vectors to original VT
10439 unsigned NumElems = InVT.getVectorNumElements();
10440 SDValue Undef = DAG.getUNDEF(InVT);
10442 SmallVector<int,8> ShufMask1(NumElems, -1);
10443 for (unsigned i = 0; i != NumElems/2; ++i)
10446 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10448 SmallVector<int,8> ShufMask2(NumElems, -1);
10449 for (unsigned i = 0; i != NumElems/2; ++i)
10450 ShufMask2[i] = i + NumElems/2;
10452 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10454 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10455 VT.getVectorNumElements()/2);
10457 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10458 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10460 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10463 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10464 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10465 // from the AND / OR.
10466 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10467 Opc = Op.getOpcode();
10468 if (Opc != ISD::OR && Opc != ISD::AND)
10470 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10471 Op.getOperand(0).hasOneUse() &&
10472 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10473 Op.getOperand(1).hasOneUse());
10476 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10477 // 1 and that the SETCC node has a single use.
10478 static bool isXor1OfSetCC(SDValue Op) {
10479 if (Op.getOpcode() != ISD::XOR)
10481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10482 if (N1C && N1C->getAPIntValue() == 1) {
10483 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10484 Op.getOperand(0).hasOneUse();
10489 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10490 bool addTest = true;
10491 SDValue Chain = Op.getOperand(0);
10492 SDValue Cond = Op.getOperand(1);
10493 SDValue Dest = Op.getOperand(2);
10496 bool Inverted = false;
10498 if (Cond.getOpcode() == ISD::SETCC) {
10499 // Check for setcc([su]{add,sub,mul}o == 0).
10500 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10501 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10502 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10503 Cond.getOperand(0).getResNo() == 1 &&
10504 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10505 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10506 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10507 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10508 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10509 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10511 Cond = Cond.getOperand(0);
10513 SDValue NewCond = LowerSETCC(Cond, DAG);
10514 if (NewCond.getNode())
10519 // FIXME: LowerXALUO doesn't handle these!!
10520 else if (Cond.getOpcode() == X86ISD::ADD ||
10521 Cond.getOpcode() == X86ISD::SUB ||
10522 Cond.getOpcode() == X86ISD::SMUL ||
10523 Cond.getOpcode() == X86ISD::UMUL)
10524 Cond = LowerXALUO(Cond, DAG);
10527 // Look pass (and (setcc_carry (cmp ...)), 1).
10528 if (Cond.getOpcode() == ISD::AND &&
10529 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10530 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10531 if (C && C->getAPIntValue() == 1)
10532 Cond = Cond.getOperand(0);
10535 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10536 // setting operand in place of the X86ISD::SETCC.
10537 unsigned CondOpcode = Cond.getOpcode();
10538 if (CondOpcode == X86ISD::SETCC ||
10539 CondOpcode == X86ISD::SETCC_CARRY) {
10540 CC = Cond.getOperand(0);
10542 SDValue Cmp = Cond.getOperand(1);
10543 unsigned Opc = Cmp.getOpcode();
10544 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10545 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10549 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10553 // These can only come from an arithmetic instruction with overflow,
10554 // e.g. SADDO, UADDO.
10555 Cond = Cond.getNode()->getOperand(1);
10561 CondOpcode = Cond.getOpcode();
10562 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10563 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10564 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10565 Cond.getOperand(0).getValueType() != MVT::i8)) {
10566 SDValue LHS = Cond.getOperand(0);
10567 SDValue RHS = Cond.getOperand(1);
10568 unsigned X86Opcode;
10571 switch (CondOpcode) {
10572 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10573 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10574 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10575 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10576 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10577 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10578 default: llvm_unreachable("unexpected overflowing operator");
10581 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10582 if (CondOpcode == ISD::UMULO)
10583 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10586 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10588 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10590 if (CondOpcode == ISD::UMULO)
10591 Cond = X86Op.getValue(2);
10593 Cond = X86Op.getValue(1);
10595 CC = DAG.getConstant(X86Cond, MVT::i8);
10599 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10600 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10601 if (CondOpc == ISD::OR) {
10602 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10603 // two branches instead of an explicit OR instruction with a
10605 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10606 isX86LogicalCmp(Cmp)) {
10607 CC = Cond.getOperand(0).getOperand(0);
10608 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10609 Chain, Dest, CC, Cmp);
10610 CC = Cond.getOperand(1).getOperand(0);
10614 } else { // ISD::AND
10615 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10616 // two branches instead of an explicit AND instruction with a
10617 // separate test. However, we only do this if this block doesn't
10618 // have a fall-through edge, because this requires an explicit
10619 // jmp when the condition is false.
10620 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10621 isX86LogicalCmp(Cmp) &&
10622 Op.getNode()->hasOneUse()) {
10623 X86::CondCode CCode =
10624 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10625 CCode = X86::GetOppositeBranchCondition(CCode);
10626 CC = DAG.getConstant(CCode, MVT::i8);
10627 SDNode *User = *Op.getNode()->use_begin();
10628 // Look for an unconditional branch following this conditional branch.
10629 // We need this because we need to reverse the successors in order
10630 // to implement FCMP_OEQ.
10631 if (User->getOpcode() == ISD::BR) {
10632 SDValue FalseBB = User->getOperand(1);
10634 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10635 assert(NewBR == User);
10639 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10640 Chain, Dest, CC, Cmp);
10641 X86::CondCode CCode =
10642 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10643 CCode = X86::GetOppositeBranchCondition(CCode);
10644 CC = DAG.getConstant(CCode, MVT::i8);
10650 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10651 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10652 // It should be transformed during dag combiner except when the condition
10653 // is set by a arithmetics with overflow node.
10654 X86::CondCode CCode =
10655 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10656 CCode = X86::GetOppositeBranchCondition(CCode);
10657 CC = DAG.getConstant(CCode, MVT::i8);
10658 Cond = Cond.getOperand(0).getOperand(1);
10660 } else if (Cond.getOpcode() == ISD::SETCC &&
10661 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10662 // For FCMP_OEQ, we can emit
10663 // two branches instead of an explicit AND instruction with a
10664 // separate test. However, we only do this if this block doesn't
10665 // have a fall-through edge, because this requires an explicit
10666 // jmp when the condition is false.
10667 if (Op.getNode()->hasOneUse()) {
10668 SDNode *User = *Op.getNode()->use_begin();
10669 // Look for an unconditional branch following this conditional branch.
10670 // We need this because we need to reverse the successors in order
10671 // to implement FCMP_OEQ.
10672 if (User->getOpcode() == ISD::BR) {
10673 SDValue FalseBB = User->getOperand(1);
10675 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10676 assert(NewBR == User);
10680 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10681 Cond.getOperand(0), Cond.getOperand(1));
10682 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10683 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10684 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10685 Chain, Dest, CC, Cmp);
10686 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10691 } else if (Cond.getOpcode() == ISD::SETCC &&
10692 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10693 // For FCMP_UNE, we can emit
10694 // two branches instead of an explicit AND instruction with a
10695 // separate test. However, we only do this if this block doesn't
10696 // have a fall-through edge, because this requires an explicit
10697 // jmp when the condition is false.
10698 if (Op.getNode()->hasOneUse()) {
10699 SDNode *User = *Op.getNode()->use_begin();
10700 // Look for an unconditional branch following this conditional branch.
10701 // We need this because we need to reverse the successors in order
10702 // to implement FCMP_UNE.
10703 if (User->getOpcode() == ISD::BR) {
10704 SDValue FalseBB = User->getOperand(1);
10706 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10707 assert(NewBR == User);
10710 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10711 Cond.getOperand(0), Cond.getOperand(1));
10712 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10713 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10714 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10715 Chain, Dest, CC, Cmp);
10716 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10726 // Look pass the truncate if the high bits are known zero.
10727 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10728 Cond = Cond.getOperand(0);
10730 // We know the result of AND is compared against zero. Try to match
10732 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10733 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10734 if (NewSetCC.getNode()) {
10735 CC = NewSetCC.getOperand(0);
10736 Cond = NewSetCC.getOperand(1);
10743 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10744 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10746 Cond = ConvertCmpIfNecessary(Cond, DAG);
10747 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10748 Chain, Dest, CC, Cond);
10751 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10752 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10753 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10754 // that the guard pages used by the OS virtual memory manager are allocated in
10755 // correct sequence.
10757 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10758 SelectionDAG &DAG) const {
10759 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10760 getTargetMachine().Options.EnableSegmentedStacks) &&
10761 "This should be used only on Windows targets or when segmented stacks "
10763 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10767 SDValue Chain = Op.getOperand(0);
10768 SDValue Size = Op.getOperand(1);
10769 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10770 EVT VT = Op.getNode()->getValueType(0);
10772 bool Is64Bit = Subtarget->is64Bit();
10773 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10775 if (getTargetMachine().Options.EnableSegmentedStacks) {
10776 MachineFunction &MF = DAG.getMachineFunction();
10777 MachineRegisterInfo &MRI = MF.getRegInfo();
10780 // The 64 bit implementation of segmented stacks needs to clobber both r10
10781 // r11. This makes it impossible to use it along with nested parameters.
10782 const Function *F = MF.getFunction();
10784 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10786 if (I->hasNestAttr())
10787 report_fatal_error("Cannot use segmented stacks with functions that "
10788 "have nested arguments.");
10791 const TargetRegisterClass *AddrRegClass =
10792 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10793 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10794 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10795 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10796 DAG.getRegister(Vreg, SPTy));
10797 SDValue Ops1[2] = { Value, Chain };
10798 return DAG.getMergeValues(Ops1, 2, dl);
10801 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10803 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10804 Flag = Chain.getValue(1);
10805 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10807 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10809 const X86RegisterInfo *RegInfo =
10810 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10811 unsigned SPReg = RegInfo->getStackRegister();
10812 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10813 Chain = SP.getValue(1);
10816 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10817 DAG.getConstant(-(uint64_t)Align, VT));
10818 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10821 SDValue Ops1[2] = { SP, Chain };
10822 return DAG.getMergeValues(Ops1, 2, dl);
10826 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10827 MachineFunction &MF = DAG.getMachineFunction();
10828 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10830 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10833 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10834 // vastart just stores the address of the VarArgsFrameIndex slot into the
10835 // memory location argument.
10836 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10838 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10839 MachinePointerInfo(SV), false, false, 0);
10843 // gp_offset (0 - 6 * 8)
10844 // fp_offset (48 - 48 + 8 * 16)
10845 // overflow_arg_area (point to parameters coming in memory).
10847 SmallVector<SDValue, 8> MemOps;
10848 SDValue FIN = Op.getOperand(1);
10850 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10851 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10853 FIN, MachinePointerInfo(SV), false, false, 0);
10854 MemOps.push_back(Store);
10857 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10858 FIN, DAG.getIntPtrConstant(4));
10859 Store = DAG.getStore(Op.getOperand(0), DL,
10860 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10862 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10863 MemOps.push_back(Store);
10865 // Store ptr to overflow_arg_area
10866 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10867 FIN, DAG.getIntPtrConstant(4));
10868 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10870 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10871 MachinePointerInfo(SV, 8),
10873 MemOps.push_back(Store);
10875 // Store ptr to reg_save_area.
10876 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10877 FIN, DAG.getIntPtrConstant(8));
10878 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10880 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10881 MachinePointerInfo(SV, 16), false, false, 0);
10882 MemOps.push_back(Store);
10883 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10884 &MemOps[0], MemOps.size());
10887 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10888 assert(Subtarget->is64Bit() &&
10889 "LowerVAARG only handles 64-bit va_arg!");
10890 assert((Subtarget->isTargetLinux() ||
10891 Subtarget->isTargetDarwin()) &&
10892 "Unhandled target in LowerVAARG");
10893 assert(Op.getNode()->getNumOperands() == 4);
10894 SDValue Chain = Op.getOperand(0);
10895 SDValue SrcPtr = Op.getOperand(1);
10896 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10897 unsigned Align = Op.getConstantOperandVal(3);
10900 EVT ArgVT = Op.getNode()->getValueType(0);
10901 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10902 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10905 // Decide which area this value should be read from.
10906 // TODO: Implement the AMD64 ABI in its entirety. This simple
10907 // selection mechanism works only for the basic types.
10908 if (ArgVT == MVT::f80) {
10909 llvm_unreachable("va_arg for f80 not yet implemented");
10910 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10911 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10912 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10913 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10915 llvm_unreachable("Unhandled argument type in LowerVAARG");
10918 if (ArgMode == 2) {
10919 // Sanity Check: Make sure using fp_offset makes sense.
10920 assert(!getTargetMachine().Options.UseSoftFloat &&
10921 !(DAG.getMachineFunction()
10922 .getFunction()->getAttributes()
10923 .hasAttribute(AttributeSet::FunctionIndex,
10924 Attribute::NoImplicitFloat)) &&
10925 Subtarget->hasSSE1());
10928 // Insert VAARG_64 node into the DAG
10929 // VAARG_64 returns two values: Variable Argument Address, Chain
10930 SmallVector<SDValue, 11> InstOps;
10931 InstOps.push_back(Chain);
10932 InstOps.push_back(SrcPtr);
10933 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10934 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10935 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10936 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10937 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10938 VTs, &InstOps[0], InstOps.size(),
10940 MachinePointerInfo(SV),
10942 /*Volatile=*/false,
10944 /*WriteMem=*/true);
10945 Chain = VAARG.getValue(1);
10947 // Load the next argument and return it
10948 return DAG.getLoad(ArgVT, dl,
10951 MachinePointerInfo(),
10952 false, false, false, 0);
10955 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10956 SelectionDAG &DAG) {
10957 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10958 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10959 SDValue Chain = Op.getOperand(0);
10960 SDValue DstPtr = Op.getOperand(1);
10961 SDValue SrcPtr = Op.getOperand(2);
10962 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10963 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10966 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10967 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10969 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10972 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
10973 // amount is a constant. Takes immediate version of shift as input.
10974 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
10975 SDValue SrcOp, uint64_t ShiftAmt,
10976 SelectionDAG &DAG) {
10978 // Check for ShiftAmt >= element width
10979 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
10980 if (Opc == X86ISD::VSRAI)
10981 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
10983 return DAG.getConstant(0, VT);
10986 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
10987 && "Unknown target vector shift-by-constant node");
10989 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
10992 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10993 // may or may not be a constant. Takes immediate version of shift as input.
10994 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10995 SDValue SrcOp, SDValue ShAmt,
10996 SelectionDAG &DAG) {
10997 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10999 // Catch shift-by-constant.
11000 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11001 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11002 CShAmt->getZExtValue(), DAG);
11004 // Change opcode to non-immediate version
11006 default: llvm_unreachable("Unknown target vector shift node");
11007 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11008 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11009 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11012 // Need to build a vector containing shift amount
11013 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11016 ShOps[1] = DAG.getConstant(0, MVT::i32);
11017 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11018 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11020 // The return type has to be a 128-bit type with the same element
11021 // type as the input type.
11022 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11023 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11025 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11026 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11029 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11031 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11033 default: return SDValue(); // Don't custom lower most intrinsics.
11034 // Comparison intrinsics.
11035 case Intrinsic::x86_sse_comieq_ss:
11036 case Intrinsic::x86_sse_comilt_ss:
11037 case Intrinsic::x86_sse_comile_ss:
11038 case Intrinsic::x86_sse_comigt_ss:
11039 case Intrinsic::x86_sse_comige_ss:
11040 case Intrinsic::x86_sse_comineq_ss:
11041 case Intrinsic::x86_sse_ucomieq_ss:
11042 case Intrinsic::x86_sse_ucomilt_ss:
11043 case Intrinsic::x86_sse_ucomile_ss:
11044 case Intrinsic::x86_sse_ucomigt_ss:
11045 case Intrinsic::x86_sse_ucomige_ss:
11046 case Intrinsic::x86_sse_ucomineq_ss:
11047 case Intrinsic::x86_sse2_comieq_sd:
11048 case Intrinsic::x86_sse2_comilt_sd:
11049 case Intrinsic::x86_sse2_comile_sd:
11050 case Intrinsic::x86_sse2_comigt_sd:
11051 case Intrinsic::x86_sse2_comige_sd:
11052 case Intrinsic::x86_sse2_comineq_sd:
11053 case Intrinsic::x86_sse2_ucomieq_sd:
11054 case Intrinsic::x86_sse2_ucomilt_sd:
11055 case Intrinsic::x86_sse2_ucomile_sd:
11056 case Intrinsic::x86_sse2_ucomigt_sd:
11057 case Intrinsic::x86_sse2_ucomige_sd:
11058 case Intrinsic::x86_sse2_ucomineq_sd: {
11062 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11063 case Intrinsic::x86_sse_comieq_ss:
11064 case Intrinsic::x86_sse2_comieq_sd:
11065 Opc = X86ISD::COMI;
11068 case Intrinsic::x86_sse_comilt_ss:
11069 case Intrinsic::x86_sse2_comilt_sd:
11070 Opc = X86ISD::COMI;
11073 case Intrinsic::x86_sse_comile_ss:
11074 case Intrinsic::x86_sse2_comile_sd:
11075 Opc = X86ISD::COMI;
11078 case Intrinsic::x86_sse_comigt_ss:
11079 case Intrinsic::x86_sse2_comigt_sd:
11080 Opc = X86ISD::COMI;
11083 case Intrinsic::x86_sse_comige_ss:
11084 case Intrinsic::x86_sse2_comige_sd:
11085 Opc = X86ISD::COMI;
11088 case Intrinsic::x86_sse_comineq_ss:
11089 case Intrinsic::x86_sse2_comineq_sd:
11090 Opc = X86ISD::COMI;
11093 case Intrinsic::x86_sse_ucomieq_ss:
11094 case Intrinsic::x86_sse2_ucomieq_sd:
11095 Opc = X86ISD::UCOMI;
11098 case Intrinsic::x86_sse_ucomilt_ss:
11099 case Intrinsic::x86_sse2_ucomilt_sd:
11100 Opc = X86ISD::UCOMI;
11103 case Intrinsic::x86_sse_ucomile_ss:
11104 case Intrinsic::x86_sse2_ucomile_sd:
11105 Opc = X86ISD::UCOMI;
11108 case Intrinsic::x86_sse_ucomigt_ss:
11109 case Intrinsic::x86_sse2_ucomigt_sd:
11110 Opc = X86ISD::UCOMI;
11113 case Intrinsic::x86_sse_ucomige_ss:
11114 case Intrinsic::x86_sse2_ucomige_sd:
11115 Opc = X86ISD::UCOMI;
11118 case Intrinsic::x86_sse_ucomineq_ss:
11119 case Intrinsic::x86_sse2_ucomineq_sd:
11120 Opc = X86ISD::UCOMI;
11125 SDValue LHS = Op.getOperand(1);
11126 SDValue RHS = Op.getOperand(2);
11127 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11128 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11129 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11130 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11131 DAG.getConstant(X86CC, MVT::i8), Cond);
11132 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11135 // Arithmetic intrinsics.
11136 case Intrinsic::x86_sse2_pmulu_dq:
11137 case Intrinsic::x86_avx2_pmulu_dq:
11138 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11139 Op.getOperand(1), Op.getOperand(2));
11141 // SSE2/AVX2 sub with unsigned saturation intrinsics
11142 case Intrinsic::x86_sse2_psubus_b:
11143 case Intrinsic::x86_sse2_psubus_w:
11144 case Intrinsic::x86_avx2_psubus_b:
11145 case Intrinsic::x86_avx2_psubus_w:
11146 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11147 Op.getOperand(1), Op.getOperand(2));
11149 // SSE3/AVX horizontal add/sub intrinsics
11150 case Intrinsic::x86_sse3_hadd_ps:
11151 case Intrinsic::x86_sse3_hadd_pd:
11152 case Intrinsic::x86_avx_hadd_ps_256:
11153 case Intrinsic::x86_avx_hadd_pd_256:
11154 case Intrinsic::x86_sse3_hsub_ps:
11155 case Intrinsic::x86_sse3_hsub_pd:
11156 case Intrinsic::x86_avx_hsub_ps_256:
11157 case Intrinsic::x86_avx_hsub_pd_256:
11158 case Intrinsic::x86_ssse3_phadd_w_128:
11159 case Intrinsic::x86_ssse3_phadd_d_128:
11160 case Intrinsic::x86_avx2_phadd_w:
11161 case Intrinsic::x86_avx2_phadd_d:
11162 case Intrinsic::x86_ssse3_phsub_w_128:
11163 case Intrinsic::x86_ssse3_phsub_d_128:
11164 case Intrinsic::x86_avx2_phsub_w:
11165 case Intrinsic::x86_avx2_phsub_d: {
11168 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11169 case Intrinsic::x86_sse3_hadd_ps:
11170 case Intrinsic::x86_sse3_hadd_pd:
11171 case Intrinsic::x86_avx_hadd_ps_256:
11172 case Intrinsic::x86_avx_hadd_pd_256:
11173 Opcode = X86ISD::FHADD;
11175 case Intrinsic::x86_sse3_hsub_ps:
11176 case Intrinsic::x86_sse3_hsub_pd:
11177 case Intrinsic::x86_avx_hsub_ps_256:
11178 case Intrinsic::x86_avx_hsub_pd_256:
11179 Opcode = X86ISD::FHSUB;
11181 case Intrinsic::x86_ssse3_phadd_w_128:
11182 case Intrinsic::x86_ssse3_phadd_d_128:
11183 case Intrinsic::x86_avx2_phadd_w:
11184 case Intrinsic::x86_avx2_phadd_d:
11185 Opcode = X86ISD::HADD;
11187 case Intrinsic::x86_ssse3_phsub_w_128:
11188 case Intrinsic::x86_ssse3_phsub_d_128:
11189 case Intrinsic::x86_avx2_phsub_w:
11190 case Intrinsic::x86_avx2_phsub_d:
11191 Opcode = X86ISD::HSUB;
11194 return DAG.getNode(Opcode, dl, Op.getValueType(),
11195 Op.getOperand(1), Op.getOperand(2));
11198 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11199 case Intrinsic::x86_sse2_pmaxu_b:
11200 case Intrinsic::x86_sse41_pmaxuw:
11201 case Intrinsic::x86_sse41_pmaxud:
11202 case Intrinsic::x86_avx2_pmaxu_b:
11203 case Intrinsic::x86_avx2_pmaxu_w:
11204 case Intrinsic::x86_avx2_pmaxu_d:
11205 case Intrinsic::x86_avx512_pmaxu_d:
11206 case Intrinsic::x86_avx512_pmaxu_q:
11207 case Intrinsic::x86_sse2_pminu_b:
11208 case Intrinsic::x86_sse41_pminuw:
11209 case Intrinsic::x86_sse41_pminud:
11210 case Intrinsic::x86_avx2_pminu_b:
11211 case Intrinsic::x86_avx2_pminu_w:
11212 case Intrinsic::x86_avx2_pminu_d:
11213 case Intrinsic::x86_avx512_pminu_d:
11214 case Intrinsic::x86_avx512_pminu_q:
11215 case Intrinsic::x86_sse41_pmaxsb:
11216 case Intrinsic::x86_sse2_pmaxs_w:
11217 case Intrinsic::x86_sse41_pmaxsd:
11218 case Intrinsic::x86_avx2_pmaxs_b:
11219 case Intrinsic::x86_avx2_pmaxs_w:
11220 case Intrinsic::x86_avx2_pmaxs_d:
11221 case Intrinsic::x86_avx512_pmaxs_d:
11222 case Intrinsic::x86_avx512_pmaxs_q:
11223 case Intrinsic::x86_sse41_pminsb:
11224 case Intrinsic::x86_sse2_pmins_w:
11225 case Intrinsic::x86_sse41_pminsd:
11226 case Intrinsic::x86_avx2_pmins_b:
11227 case Intrinsic::x86_avx2_pmins_w:
11228 case Intrinsic::x86_avx2_pmins_d:
11229 case Intrinsic::x86_avx512_pmins_d:
11230 case Intrinsic::x86_avx512_pmins_q: {
11233 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11234 case Intrinsic::x86_sse2_pmaxu_b:
11235 case Intrinsic::x86_sse41_pmaxuw:
11236 case Intrinsic::x86_sse41_pmaxud:
11237 case Intrinsic::x86_avx2_pmaxu_b:
11238 case Intrinsic::x86_avx2_pmaxu_w:
11239 case Intrinsic::x86_avx2_pmaxu_d:
11240 case Intrinsic::x86_avx512_pmaxu_d:
11241 case Intrinsic::x86_avx512_pmaxu_q:
11242 Opcode = X86ISD::UMAX;
11244 case Intrinsic::x86_sse2_pminu_b:
11245 case Intrinsic::x86_sse41_pminuw:
11246 case Intrinsic::x86_sse41_pminud:
11247 case Intrinsic::x86_avx2_pminu_b:
11248 case Intrinsic::x86_avx2_pminu_w:
11249 case Intrinsic::x86_avx2_pminu_d:
11250 case Intrinsic::x86_avx512_pminu_d:
11251 case Intrinsic::x86_avx512_pminu_q:
11252 Opcode = X86ISD::UMIN;
11254 case Intrinsic::x86_sse41_pmaxsb:
11255 case Intrinsic::x86_sse2_pmaxs_w:
11256 case Intrinsic::x86_sse41_pmaxsd:
11257 case Intrinsic::x86_avx2_pmaxs_b:
11258 case Intrinsic::x86_avx2_pmaxs_w:
11259 case Intrinsic::x86_avx2_pmaxs_d:
11260 case Intrinsic::x86_avx512_pmaxs_d:
11261 case Intrinsic::x86_avx512_pmaxs_q:
11262 Opcode = X86ISD::SMAX;
11264 case Intrinsic::x86_sse41_pminsb:
11265 case Intrinsic::x86_sse2_pmins_w:
11266 case Intrinsic::x86_sse41_pminsd:
11267 case Intrinsic::x86_avx2_pmins_b:
11268 case Intrinsic::x86_avx2_pmins_w:
11269 case Intrinsic::x86_avx2_pmins_d:
11270 case Intrinsic::x86_avx512_pmins_d:
11271 case Intrinsic::x86_avx512_pmins_q:
11272 Opcode = X86ISD::SMIN;
11275 return DAG.getNode(Opcode, dl, Op.getValueType(),
11276 Op.getOperand(1), Op.getOperand(2));
11279 // SSE/SSE2/AVX floating point max/min intrinsics.
11280 case Intrinsic::x86_sse_max_ps:
11281 case Intrinsic::x86_sse2_max_pd:
11282 case Intrinsic::x86_avx_max_ps_256:
11283 case Intrinsic::x86_avx_max_pd_256:
11284 case Intrinsic::x86_avx512_max_ps_512:
11285 case Intrinsic::x86_avx512_max_pd_512:
11286 case Intrinsic::x86_sse_min_ps:
11287 case Intrinsic::x86_sse2_min_pd:
11288 case Intrinsic::x86_avx_min_ps_256:
11289 case Intrinsic::x86_avx_min_pd_256:
11290 case Intrinsic::x86_avx512_min_ps_512:
11291 case Intrinsic::x86_avx512_min_pd_512: {
11294 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11295 case Intrinsic::x86_sse_max_ps:
11296 case Intrinsic::x86_sse2_max_pd:
11297 case Intrinsic::x86_avx_max_ps_256:
11298 case Intrinsic::x86_avx_max_pd_256:
11299 case Intrinsic::x86_avx512_max_ps_512:
11300 case Intrinsic::x86_avx512_max_pd_512:
11301 Opcode = X86ISD::FMAX;
11303 case Intrinsic::x86_sse_min_ps:
11304 case Intrinsic::x86_sse2_min_pd:
11305 case Intrinsic::x86_avx_min_ps_256:
11306 case Intrinsic::x86_avx_min_pd_256:
11307 case Intrinsic::x86_avx512_min_ps_512:
11308 case Intrinsic::x86_avx512_min_pd_512:
11309 Opcode = X86ISD::FMIN;
11312 return DAG.getNode(Opcode, dl, Op.getValueType(),
11313 Op.getOperand(1), Op.getOperand(2));
11316 // AVX2 variable shift intrinsics
11317 case Intrinsic::x86_avx2_psllv_d:
11318 case Intrinsic::x86_avx2_psllv_q:
11319 case Intrinsic::x86_avx2_psllv_d_256:
11320 case Intrinsic::x86_avx2_psllv_q_256:
11321 case Intrinsic::x86_avx2_psrlv_d:
11322 case Intrinsic::x86_avx2_psrlv_q:
11323 case Intrinsic::x86_avx2_psrlv_d_256:
11324 case Intrinsic::x86_avx2_psrlv_q_256:
11325 case Intrinsic::x86_avx2_psrav_d:
11326 case Intrinsic::x86_avx2_psrav_d_256: {
11329 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11330 case Intrinsic::x86_avx2_psllv_d:
11331 case Intrinsic::x86_avx2_psllv_q:
11332 case Intrinsic::x86_avx2_psllv_d_256:
11333 case Intrinsic::x86_avx2_psllv_q_256:
11336 case Intrinsic::x86_avx2_psrlv_d:
11337 case Intrinsic::x86_avx2_psrlv_q:
11338 case Intrinsic::x86_avx2_psrlv_d_256:
11339 case Intrinsic::x86_avx2_psrlv_q_256:
11342 case Intrinsic::x86_avx2_psrav_d:
11343 case Intrinsic::x86_avx2_psrav_d_256:
11347 return DAG.getNode(Opcode, dl, Op.getValueType(),
11348 Op.getOperand(1), Op.getOperand(2));
11351 case Intrinsic::x86_ssse3_pshuf_b_128:
11352 case Intrinsic::x86_avx2_pshuf_b:
11353 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11354 Op.getOperand(1), Op.getOperand(2));
11356 case Intrinsic::x86_ssse3_psign_b_128:
11357 case Intrinsic::x86_ssse3_psign_w_128:
11358 case Intrinsic::x86_ssse3_psign_d_128:
11359 case Intrinsic::x86_avx2_psign_b:
11360 case Intrinsic::x86_avx2_psign_w:
11361 case Intrinsic::x86_avx2_psign_d:
11362 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11363 Op.getOperand(1), Op.getOperand(2));
11365 case Intrinsic::x86_sse41_insertps:
11366 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11367 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11369 case Intrinsic::x86_avx_vperm2f128_ps_256:
11370 case Intrinsic::x86_avx_vperm2f128_pd_256:
11371 case Intrinsic::x86_avx_vperm2f128_si_256:
11372 case Intrinsic::x86_avx2_vperm2i128:
11373 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11374 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11376 case Intrinsic::x86_avx2_permd:
11377 case Intrinsic::x86_avx2_permps:
11378 // Operands intentionally swapped. Mask is last operand to intrinsic,
11379 // but second operand for node/instruction.
11380 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11381 Op.getOperand(2), Op.getOperand(1));
11383 case Intrinsic::x86_sse_sqrt_ps:
11384 case Intrinsic::x86_sse2_sqrt_pd:
11385 case Intrinsic::x86_avx_sqrt_ps_256:
11386 case Intrinsic::x86_avx_sqrt_pd_256:
11387 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11389 // ptest and testp intrinsics. The intrinsic these come from are designed to
11390 // return an integer value, not just an instruction so lower it to the ptest
11391 // or testp pattern and a setcc for the result.
11392 case Intrinsic::x86_sse41_ptestz:
11393 case Intrinsic::x86_sse41_ptestc:
11394 case Intrinsic::x86_sse41_ptestnzc:
11395 case Intrinsic::x86_avx_ptestz_256:
11396 case Intrinsic::x86_avx_ptestc_256:
11397 case Intrinsic::x86_avx_ptestnzc_256:
11398 case Intrinsic::x86_avx_vtestz_ps:
11399 case Intrinsic::x86_avx_vtestc_ps:
11400 case Intrinsic::x86_avx_vtestnzc_ps:
11401 case Intrinsic::x86_avx_vtestz_pd:
11402 case Intrinsic::x86_avx_vtestc_pd:
11403 case Intrinsic::x86_avx_vtestnzc_pd:
11404 case Intrinsic::x86_avx_vtestz_ps_256:
11405 case Intrinsic::x86_avx_vtestc_ps_256:
11406 case Intrinsic::x86_avx_vtestnzc_ps_256:
11407 case Intrinsic::x86_avx_vtestz_pd_256:
11408 case Intrinsic::x86_avx_vtestc_pd_256:
11409 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11410 bool IsTestPacked = false;
11413 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11414 case Intrinsic::x86_avx_vtestz_ps:
11415 case Intrinsic::x86_avx_vtestz_pd:
11416 case Intrinsic::x86_avx_vtestz_ps_256:
11417 case Intrinsic::x86_avx_vtestz_pd_256:
11418 IsTestPacked = true; // Fallthrough
11419 case Intrinsic::x86_sse41_ptestz:
11420 case Intrinsic::x86_avx_ptestz_256:
11422 X86CC = X86::COND_E;
11424 case Intrinsic::x86_avx_vtestc_ps:
11425 case Intrinsic::x86_avx_vtestc_pd:
11426 case Intrinsic::x86_avx_vtestc_ps_256:
11427 case Intrinsic::x86_avx_vtestc_pd_256:
11428 IsTestPacked = true; // Fallthrough
11429 case Intrinsic::x86_sse41_ptestc:
11430 case Intrinsic::x86_avx_ptestc_256:
11432 X86CC = X86::COND_B;
11434 case Intrinsic::x86_avx_vtestnzc_ps:
11435 case Intrinsic::x86_avx_vtestnzc_pd:
11436 case Intrinsic::x86_avx_vtestnzc_ps_256:
11437 case Intrinsic::x86_avx_vtestnzc_pd_256:
11438 IsTestPacked = true; // Fallthrough
11439 case Intrinsic::x86_sse41_ptestnzc:
11440 case Intrinsic::x86_avx_ptestnzc_256:
11442 X86CC = X86::COND_A;
11446 SDValue LHS = Op.getOperand(1);
11447 SDValue RHS = Op.getOperand(2);
11448 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11449 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11450 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11451 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11452 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11454 case Intrinsic::x86_avx512_kortestz:
11455 case Intrinsic::x86_avx512_kortestc: {
11456 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11457 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11458 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11459 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11460 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11461 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11462 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11465 // SSE/AVX shift intrinsics
11466 case Intrinsic::x86_sse2_psll_w:
11467 case Intrinsic::x86_sse2_psll_d:
11468 case Intrinsic::x86_sse2_psll_q:
11469 case Intrinsic::x86_avx2_psll_w:
11470 case Intrinsic::x86_avx2_psll_d:
11471 case Intrinsic::x86_avx2_psll_q:
11472 case Intrinsic::x86_sse2_psrl_w:
11473 case Intrinsic::x86_sse2_psrl_d:
11474 case Intrinsic::x86_sse2_psrl_q:
11475 case Intrinsic::x86_avx2_psrl_w:
11476 case Intrinsic::x86_avx2_psrl_d:
11477 case Intrinsic::x86_avx2_psrl_q:
11478 case Intrinsic::x86_sse2_psra_w:
11479 case Intrinsic::x86_sse2_psra_d:
11480 case Intrinsic::x86_avx2_psra_w:
11481 case Intrinsic::x86_avx2_psra_d: {
11484 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11485 case Intrinsic::x86_sse2_psll_w:
11486 case Intrinsic::x86_sse2_psll_d:
11487 case Intrinsic::x86_sse2_psll_q:
11488 case Intrinsic::x86_avx2_psll_w:
11489 case Intrinsic::x86_avx2_psll_d:
11490 case Intrinsic::x86_avx2_psll_q:
11491 Opcode = X86ISD::VSHL;
11493 case Intrinsic::x86_sse2_psrl_w:
11494 case Intrinsic::x86_sse2_psrl_d:
11495 case Intrinsic::x86_sse2_psrl_q:
11496 case Intrinsic::x86_avx2_psrl_w:
11497 case Intrinsic::x86_avx2_psrl_d:
11498 case Intrinsic::x86_avx2_psrl_q:
11499 Opcode = X86ISD::VSRL;
11501 case Intrinsic::x86_sse2_psra_w:
11502 case Intrinsic::x86_sse2_psra_d:
11503 case Intrinsic::x86_avx2_psra_w:
11504 case Intrinsic::x86_avx2_psra_d:
11505 Opcode = X86ISD::VSRA;
11508 return DAG.getNode(Opcode, dl, Op.getValueType(),
11509 Op.getOperand(1), Op.getOperand(2));
11512 // SSE/AVX immediate shift intrinsics
11513 case Intrinsic::x86_sse2_pslli_w:
11514 case Intrinsic::x86_sse2_pslli_d:
11515 case Intrinsic::x86_sse2_pslli_q:
11516 case Intrinsic::x86_avx2_pslli_w:
11517 case Intrinsic::x86_avx2_pslli_d:
11518 case Intrinsic::x86_avx2_pslli_q:
11519 case Intrinsic::x86_sse2_psrli_w:
11520 case Intrinsic::x86_sse2_psrli_d:
11521 case Intrinsic::x86_sse2_psrli_q:
11522 case Intrinsic::x86_avx2_psrli_w:
11523 case Intrinsic::x86_avx2_psrli_d:
11524 case Intrinsic::x86_avx2_psrli_q:
11525 case Intrinsic::x86_sse2_psrai_w:
11526 case Intrinsic::x86_sse2_psrai_d:
11527 case Intrinsic::x86_avx2_psrai_w:
11528 case Intrinsic::x86_avx2_psrai_d: {
11531 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11532 case Intrinsic::x86_sse2_pslli_w:
11533 case Intrinsic::x86_sse2_pslli_d:
11534 case Intrinsic::x86_sse2_pslli_q:
11535 case Intrinsic::x86_avx2_pslli_w:
11536 case Intrinsic::x86_avx2_pslli_d:
11537 case Intrinsic::x86_avx2_pslli_q:
11538 Opcode = X86ISD::VSHLI;
11540 case Intrinsic::x86_sse2_psrli_w:
11541 case Intrinsic::x86_sse2_psrli_d:
11542 case Intrinsic::x86_sse2_psrli_q:
11543 case Intrinsic::x86_avx2_psrli_w:
11544 case Intrinsic::x86_avx2_psrli_d:
11545 case Intrinsic::x86_avx2_psrli_q:
11546 Opcode = X86ISD::VSRLI;
11548 case Intrinsic::x86_sse2_psrai_w:
11549 case Intrinsic::x86_sse2_psrai_d:
11550 case Intrinsic::x86_avx2_psrai_w:
11551 case Intrinsic::x86_avx2_psrai_d:
11552 Opcode = X86ISD::VSRAI;
11555 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11556 Op.getOperand(1), Op.getOperand(2), DAG);
11559 case Intrinsic::x86_sse42_pcmpistria128:
11560 case Intrinsic::x86_sse42_pcmpestria128:
11561 case Intrinsic::x86_sse42_pcmpistric128:
11562 case Intrinsic::x86_sse42_pcmpestric128:
11563 case Intrinsic::x86_sse42_pcmpistrio128:
11564 case Intrinsic::x86_sse42_pcmpestrio128:
11565 case Intrinsic::x86_sse42_pcmpistris128:
11566 case Intrinsic::x86_sse42_pcmpestris128:
11567 case Intrinsic::x86_sse42_pcmpistriz128:
11568 case Intrinsic::x86_sse42_pcmpestriz128: {
11572 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11573 case Intrinsic::x86_sse42_pcmpistria128:
11574 Opcode = X86ISD::PCMPISTRI;
11575 X86CC = X86::COND_A;
11577 case Intrinsic::x86_sse42_pcmpestria128:
11578 Opcode = X86ISD::PCMPESTRI;
11579 X86CC = X86::COND_A;
11581 case Intrinsic::x86_sse42_pcmpistric128:
11582 Opcode = X86ISD::PCMPISTRI;
11583 X86CC = X86::COND_B;
11585 case Intrinsic::x86_sse42_pcmpestric128:
11586 Opcode = X86ISD::PCMPESTRI;
11587 X86CC = X86::COND_B;
11589 case Intrinsic::x86_sse42_pcmpistrio128:
11590 Opcode = X86ISD::PCMPISTRI;
11591 X86CC = X86::COND_O;
11593 case Intrinsic::x86_sse42_pcmpestrio128:
11594 Opcode = X86ISD::PCMPESTRI;
11595 X86CC = X86::COND_O;
11597 case Intrinsic::x86_sse42_pcmpistris128:
11598 Opcode = X86ISD::PCMPISTRI;
11599 X86CC = X86::COND_S;
11601 case Intrinsic::x86_sse42_pcmpestris128:
11602 Opcode = X86ISD::PCMPESTRI;
11603 X86CC = X86::COND_S;
11605 case Intrinsic::x86_sse42_pcmpistriz128:
11606 Opcode = X86ISD::PCMPISTRI;
11607 X86CC = X86::COND_E;
11609 case Intrinsic::x86_sse42_pcmpestriz128:
11610 Opcode = X86ISD::PCMPESTRI;
11611 X86CC = X86::COND_E;
11614 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11615 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11616 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11617 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11618 DAG.getConstant(X86CC, MVT::i8),
11619 SDValue(PCMP.getNode(), 1));
11620 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11623 case Intrinsic::x86_sse42_pcmpistri128:
11624 case Intrinsic::x86_sse42_pcmpestri128: {
11626 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11627 Opcode = X86ISD::PCMPISTRI;
11629 Opcode = X86ISD::PCMPESTRI;
11631 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11632 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11633 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11635 case Intrinsic::x86_fma_vfmadd_ps:
11636 case Intrinsic::x86_fma_vfmadd_pd:
11637 case Intrinsic::x86_fma_vfmsub_ps:
11638 case Intrinsic::x86_fma_vfmsub_pd:
11639 case Intrinsic::x86_fma_vfnmadd_ps:
11640 case Intrinsic::x86_fma_vfnmadd_pd:
11641 case Intrinsic::x86_fma_vfnmsub_ps:
11642 case Intrinsic::x86_fma_vfnmsub_pd:
11643 case Intrinsic::x86_fma_vfmaddsub_ps:
11644 case Intrinsic::x86_fma_vfmaddsub_pd:
11645 case Intrinsic::x86_fma_vfmsubadd_ps:
11646 case Intrinsic::x86_fma_vfmsubadd_pd:
11647 case Intrinsic::x86_fma_vfmadd_ps_256:
11648 case Intrinsic::x86_fma_vfmadd_pd_256:
11649 case Intrinsic::x86_fma_vfmsub_ps_256:
11650 case Intrinsic::x86_fma_vfmsub_pd_256:
11651 case Intrinsic::x86_fma_vfnmadd_ps_256:
11652 case Intrinsic::x86_fma_vfnmadd_pd_256:
11653 case Intrinsic::x86_fma_vfnmsub_ps_256:
11654 case Intrinsic::x86_fma_vfnmsub_pd_256:
11655 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11656 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11657 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11658 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11659 case Intrinsic::x86_fma_vfmadd_ps_512:
11660 case Intrinsic::x86_fma_vfmadd_pd_512:
11661 case Intrinsic::x86_fma_vfmsub_ps_512:
11662 case Intrinsic::x86_fma_vfmsub_pd_512:
11663 case Intrinsic::x86_fma_vfnmadd_ps_512:
11664 case Intrinsic::x86_fma_vfnmadd_pd_512:
11665 case Intrinsic::x86_fma_vfnmsub_ps_512:
11666 case Intrinsic::x86_fma_vfnmsub_pd_512:
11667 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11668 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11669 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11670 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11673 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11674 case Intrinsic::x86_fma_vfmadd_ps:
11675 case Intrinsic::x86_fma_vfmadd_pd:
11676 case Intrinsic::x86_fma_vfmadd_ps_256:
11677 case Intrinsic::x86_fma_vfmadd_pd_256:
11678 case Intrinsic::x86_fma_vfmadd_ps_512:
11679 case Intrinsic::x86_fma_vfmadd_pd_512:
11680 Opc = X86ISD::FMADD;
11682 case Intrinsic::x86_fma_vfmsub_ps:
11683 case Intrinsic::x86_fma_vfmsub_pd:
11684 case Intrinsic::x86_fma_vfmsub_ps_256:
11685 case Intrinsic::x86_fma_vfmsub_pd_256:
11686 case Intrinsic::x86_fma_vfmsub_ps_512:
11687 case Intrinsic::x86_fma_vfmsub_pd_512:
11688 Opc = X86ISD::FMSUB;
11690 case Intrinsic::x86_fma_vfnmadd_ps:
11691 case Intrinsic::x86_fma_vfnmadd_pd:
11692 case Intrinsic::x86_fma_vfnmadd_ps_256:
11693 case Intrinsic::x86_fma_vfnmadd_pd_256:
11694 case Intrinsic::x86_fma_vfnmadd_ps_512:
11695 case Intrinsic::x86_fma_vfnmadd_pd_512:
11696 Opc = X86ISD::FNMADD;
11698 case Intrinsic::x86_fma_vfnmsub_ps:
11699 case Intrinsic::x86_fma_vfnmsub_pd:
11700 case Intrinsic::x86_fma_vfnmsub_ps_256:
11701 case Intrinsic::x86_fma_vfnmsub_pd_256:
11702 case Intrinsic::x86_fma_vfnmsub_ps_512:
11703 case Intrinsic::x86_fma_vfnmsub_pd_512:
11704 Opc = X86ISD::FNMSUB;
11706 case Intrinsic::x86_fma_vfmaddsub_ps:
11707 case Intrinsic::x86_fma_vfmaddsub_pd:
11708 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11709 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11710 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11711 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11712 Opc = X86ISD::FMADDSUB;
11714 case Intrinsic::x86_fma_vfmsubadd_ps:
11715 case Intrinsic::x86_fma_vfmsubadd_pd:
11716 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11717 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11718 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11719 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11720 Opc = X86ISD::FMSUBADD;
11724 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11725 Op.getOperand(2), Op.getOperand(3));
11730 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11731 SDValue Base, SDValue Index,
11732 SDValue ScaleOp, SDValue Chain,
11733 const X86Subtarget * Subtarget) {
11735 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11736 assert(C && "Invalid scale type");
11737 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11738 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11739 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11740 Index.getValueType().getVectorNumElements());
11741 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11742 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11743 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11744 SDValue Segment = DAG.getRegister(0, MVT::i32);
11745 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11746 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11747 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11748 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11751 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11752 SDValue Src, SDValue Mask, SDValue Base,
11753 SDValue Index, SDValue ScaleOp, SDValue Chain,
11754 const X86Subtarget * Subtarget) {
11756 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11757 assert(C && "Invalid scale type");
11758 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11759 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11760 Index.getValueType().getVectorNumElements());
11761 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11762 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11763 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11764 SDValue Segment = DAG.getRegister(0, MVT::i32);
11765 if (Src.getOpcode() == ISD::UNDEF)
11766 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11767 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11768 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11769 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11770 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11773 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11774 SDValue Src, SDValue Base, SDValue Index,
11775 SDValue ScaleOp, SDValue Chain) {
11777 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11778 assert(C && "Invalid scale type");
11779 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11780 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11781 SDValue Segment = DAG.getRegister(0, MVT::i32);
11782 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11783 Index.getValueType().getVectorNumElements());
11784 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11785 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11786 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11787 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11788 return SDValue(Res, 1);
11791 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11792 SDValue Src, SDValue Mask, SDValue Base,
11793 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11795 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11796 assert(C && "Invalid scale type");
11797 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11798 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11799 SDValue Segment = DAG.getRegister(0, MVT::i32);
11800 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11801 Index.getValueType().getVectorNumElements());
11802 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11803 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11804 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11805 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11806 return SDValue(Res, 1);
11809 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11810 SelectionDAG &DAG) {
11812 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11814 default: return SDValue(); // Don't custom lower most intrinsics.
11816 // RDRAND/RDSEED intrinsics.
11817 case Intrinsic::x86_rdrand_16:
11818 case Intrinsic::x86_rdrand_32:
11819 case Intrinsic::x86_rdrand_64:
11820 case Intrinsic::x86_rdseed_16:
11821 case Intrinsic::x86_rdseed_32:
11822 case Intrinsic::x86_rdseed_64: {
11823 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11824 IntNo == Intrinsic::x86_rdseed_32 ||
11825 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11827 // Emit the node with the right value type.
11828 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11829 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11831 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11832 // Otherwise return the value from Rand, which is always 0, casted to i32.
11833 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11834 DAG.getConstant(1, Op->getValueType(1)),
11835 DAG.getConstant(X86::COND_B, MVT::i32),
11836 SDValue(Result.getNode(), 1) };
11837 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11838 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11839 Ops, array_lengthof(Ops));
11841 // Return { result, isValid, chain }.
11842 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11843 SDValue(Result.getNode(), 2));
11845 //int_gather(index, base, scale);
11846 case Intrinsic::x86_avx512_gather_qpd_512:
11847 case Intrinsic::x86_avx512_gather_qps_512:
11848 case Intrinsic::x86_avx512_gather_dpd_512:
11849 case Intrinsic::x86_avx512_gather_qpi_512:
11850 case Intrinsic::x86_avx512_gather_qpq_512:
11851 case Intrinsic::x86_avx512_gather_dpq_512:
11852 case Intrinsic::x86_avx512_gather_dps_512:
11853 case Intrinsic::x86_avx512_gather_dpi_512: {
11856 default: llvm_unreachable("Unexpected intrinsic!");
11857 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11858 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11859 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11860 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11861 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11862 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11863 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11864 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11866 SDValue Chain = Op.getOperand(0);
11867 SDValue Index = Op.getOperand(2);
11868 SDValue Base = Op.getOperand(3);
11869 SDValue Scale = Op.getOperand(4);
11870 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11872 //int_gather_mask(v1, mask, index, base, scale);
11873 case Intrinsic::x86_avx512_gather_qps_mask_512:
11874 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11875 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11876 case Intrinsic::x86_avx512_gather_dps_mask_512:
11877 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11878 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11879 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11880 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11883 default: llvm_unreachable("Unexpected intrinsic!");
11884 case Intrinsic::x86_avx512_gather_qps_mask_512:
11885 Opc = X86::VGATHERQPSZrm; break;
11886 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11887 Opc = X86::VGATHERQPDZrm; break;
11888 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11889 Opc = X86::VGATHERDPDZrm; break;
11890 case Intrinsic::x86_avx512_gather_dps_mask_512:
11891 Opc = X86::VGATHERDPSZrm; break;
11892 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11893 Opc = X86::VPGATHERQDZrm; break;
11894 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11895 Opc = X86::VPGATHERQQZrm; break;
11896 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11897 Opc = X86::VPGATHERDDZrm; break;
11898 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11899 Opc = X86::VPGATHERDQZrm; break;
11901 SDValue Chain = Op.getOperand(0);
11902 SDValue Src = Op.getOperand(2);
11903 SDValue Mask = Op.getOperand(3);
11904 SDValue Index = Op.getOperand(4);
11905 SDValue Base = Op.getOperand(5);
11906 SDValue Scale = Op.getOperand(6);
11907 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11910 //int_scatter(base, index, v1, scale);
11911 case Intrinsic::x86_avx512_scatter_qpd_512:
11912 case Intrinsic::x86_avx512_scatter_qps_512:
11913 case Intrinsic::x86_avx512_scatter_dpd_512:
11914 case Intrinsic::x86_avx512_scatter_qpi_512:
11915 case Intrinsic::x86_avx512_scatter_qpq_512:
11916 case Intrinsic::x86_avx512_scatter_dpq_512:
11917 case Intrinsic::x86_avx512_scatter_dps_512:
11918 case Intrinsic::x86_avx512_scatter_dpi_512: {
11921 default: llvm_unreachable("Unexpected intrinsic!");
11922 case Intrinsic::x86_avx512_scatter_qpd_512:
11923 Opc = X86::VSCATTERQPDZmr; break;
11924 case Intrinsic::x86_avx512_scatter_qps_512:
11925 Opc = X86::VSCATTERQPSZmr; break;
11926 case Intrinsic::x86_avx512_scatter_dpd_512:
11927 Opc = X86::VSCATTERDPDZmr; break;
11928 case Intrinsic::x86_avx512_scatter_dps_512:
11929 Opc = X86::VSCATTERDPSZmr; break;
11930 case Intrinsic::x86_avx512_scatter_qpi_512:
11931 Opc = X86::VPSCATTERQDZmr; break;
11932 case Intrinsic::x86_avx512_scatter_qpq_512:
11933 Opc = X86::VPSCATTERQQZmr; break;
11934 case Intrinsic::x86_avx512_scatter_dpq_512:
11935 Opc = X86::VPSCATTERDQZmr; break;
11936 case Intrinsic::x86_avx512_scatter_dpi_512:
11937 Opc = X86::VPSCATTERDDZmr; break;
11939 SDValue Chain = Op.getOperand(0);
11940 SDValue Base = Op.getOperand(2);
11941 SDValue Index = Op.getOperand(3);
11942 SDValue Src = Op.getOperand(4);
11943 SDValue Scale = Op.getOperand(5);
11944 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11946 //int_scatter_mask(base, mask, index, v1, scale);
11947 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11948 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11949 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11950 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11951 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11952 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11953 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11954 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11957 default: llvm_unreachable("Unexpected intrinsic!");
11958 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11959 Opc = X86::VSCATTERQPDZmr; break;
11960 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11961 Opc = X86::VSCATTERQPSZmr; break;
11962 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11963 Opc = X86::VSCATTERDPDZmr; break;
11964 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11965 Opc = X86::VSCATTERDPSZmr; break;
11966 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11967 Opc = X86::VPSCATTERQDZmr; break;
11968 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11969 Opc = X86::VPSCATTERQQZmr; break;
11970 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11971 Opc = X86::VPSCATTERDQZmr; break;
11972 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11973 Opc = X86::VPSCATTERDDZmr; break;
11975 SDValue Chain = Op.getOperand(0);
11976 SDValue Base = Op.getOperand(2);
11977 SDValue Mask = Op.getOperand(3);
11978 SDValue Index = Op.getOperand(4);
11979 SDValue Src = Op.getOperand(5);
11980 SDValue Scale = Op.getOperand(6);
11981 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11983 // XTEST intrinsics.
11984 case Intrinsic::x86_xtest: {
11985 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11986 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11987 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11988 DAG.getConstant(X86::COND_NE, MVT::i8),
11990 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11991 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11992 Ret, SDValue(InTrans.getNode(), 1));
11997 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11998 SelectionDAG &DAG) const {
11999 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12000 MFI->setReturnAddressIsTaken(true);
12002 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12004 EVT PtrVT = getPointerTy();
12007 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12008 const X86RegisterInfo *RegInfo =
12009 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12010 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12011 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12012 DAG.getNode(ISD::ADD, dl, PtrVT,
12013 FrameAddr, Offset),
12014 MachinePointerInfo(), false, false, false, 0);
12017 // Just load the return address.
12018 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12019 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12020 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12023 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12024 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12025 MFI->setFrameAddressIsTaken(true);
12027 EVT VT = Op.getValueType();
12028 SDLoc dl(Op); // FIXME probably not meaningful
12029 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12030 const X86RegisterInfo *RegInfo =
12031 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12032 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12033 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12034 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12035 "Invalid Frame Register!");
12036 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12038 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12039 MachinePointerInfo(),
12040 false, false, false, 0);
12044 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12045 SelectionDAG &DAG) const {
12046 const X86RegisterInfo *RegInfo =
12047 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12048 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12051 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12052 SDValue Chain = Op.getOperand(0);
12053 SDValue Offset = Op.getOperand(1);
12054 SDValue Handler = Op.getOperand(2);
12057 EVT PtrVT = getPointerTy();
12058 const X86RegisterInfo *RegInfo =
12059 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12060 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12061 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12062 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12063 "Invalid Frame Register!");
12064 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12065 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12067 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12068 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12069 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12070 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12072 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12074 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12075 DAG.getRegister(StoreAddrReg, PtrVT));
12078 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12079 SelectionDAG &DAG) const {
12081 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12082 DAG.getVTList(MVT::i32, MVT::Other),
12083 Op.getOperand(0), Op.getOperand(1));
12086 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12087 SelectionDAG &DAG) const {
12089 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12090 Op.getOperand(0), Op.getOperand(1));
12093 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12094 return Op.getOperand(0);
12097 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12098 SelectionDAG &DAG) const {
12099 SDValue Root = Op.getOperand(0);
12100 SDValue Trmp = Op.getOperand(1); // trampoline
12101 SDValue FPtr = Op.getOperand(2); // nested function
12102 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12105 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12106 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12108 if (Subtarget->is64Bit()) {
12109 SDValue OutChains[6];
12111 // Large code-model.
12112 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12113 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12115 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12116 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12118 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12120 // Load the pointer to the nested function into R11.
12121 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12122 SDValue Addr = Trmp;
12123 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12124 Addr, MachinePointerInfo(TrmpAddr),
12127 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12128 DAG.getConstant(2, MVT::i64));
12129 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12130 MachinePointerInfo(TrmpAddr, 2),
12133 // Load the 'nest' parameter value into R10.
12134 // R10 is specified in X86CallingConv.td
12135 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12136 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12137 DAG.getConstant(10, MVT::i64));
12138 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12139 Addr, MachinePointerInfo(TrmpAddr, 10),
12142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12143 DAG.getConstant(12, MVT::i64));
12144 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12145 MachinePointerInfo(TrmpAddr, 12),
12148 // Jump to the nested function.
12149 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12150 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12151 DAG.getConstant(20, MVT::i64));
12152 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12153 Addr, MachinePointerInfo(TrmpAddr, 20),
12156 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12157 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12158 DAG.getConstant(22, MVT::i64));
12159 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12160 MachinePointerInfo(TrmpAddr, 22),
12163 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12165 const Function *Func =
12166 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12167 CallingConv::ID CC = Func->getCallingConv();
12172 llvm_unreachable("Unsupported calling convention");
12173 case CallingConv::C:
12174 case CallingConv::X86_StdCall: {
12175 // Pass 'nest' parameter in ECX.
12176 // Must be kept in sync with X86CallingConv.td
12177 NestReg = X86::ECX;
12179 // Check that ECX wasn't needed by an 'inreg' parameter.
12180 FunctionType *FTy = Func->getFunctionType();
12181 const AttributeSet &Attrs = Func->getAttributes();
12183 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12184 unsigned InRegCount = 0;
12187 for (FunctionType::param_iterator I = FTy->param_begin(),
12188 E = FTy->param_end(); I != E; ++I, ++Idx)
12189 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12190 // FIXME: should only count parameters that are lowered to integers.
12191 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12193 if (InRegCount > 2) {
12194 report_fatal_error("Nest register in use - reduce number of inreg"
12200 case CallingConv::X86_FastCall:
12201 case CallingConv::X86_ThisCall:
12202 case CallingConv::Fast:
12203 // Pass 'nest' parameter in EAX.
12204 // Must be kept in sync with X86CallingConv.td
12205 NestReg = X86::EAX;
12209 SDValue OutChains[4];
12210 SDValue Addr, Disp;
12212 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12213 DAG.getConstant(10, MVT::i32));
12214 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12216 // This is storing the opcode for MOV32ri.
12217 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12218 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12219 OutChains[0] = DAG.getStore(Root, dl,
12220 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12221 Trmp, MachinePointerInfo(TrmpAddr),
12224 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12225 DAG.getConstant(1, MVT::i32));
12226 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12227 MachinePointerInfo(TrmpAddr, 1),
12230 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12231 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12232 DAG.getConstant(5, MVT::i32));
12233 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12234 MachinePointerInfo(TrmpAddr, 5),
12237 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12238 DAG.getConstant(6, MVT::i32));
12239 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12240 MachinePointerInfo(TrmpAddr, 6),
12243 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12247 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12248 SelectionDAG &DAG) const {
12250 The rounding mode is in bits 11:10 of FPSR, and has the following
12252 00 Round to nearest
12257 FLT_ROUNDS, on the other hand, expects the following:
12264 To perform the conversion, we do:
12265 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12268 MachineFunction &MF = DAG.getMachineFunction();
12269 const TargetMachine &TM = MF.getTarget();
12270 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12271 unsigned StackAlignment = TFI.getStackAlignment();
12272 EVT VT = Op.getValueType();
12275 // Save FP Control Word to stack slot
12276 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12277 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12279 MachineMemOperand *MMO =
12280 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12281 MachineMemOperand::MOStore, 2, 2);
12283 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12284 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12285 DAG.getVTList(MVT::Other),
12286 Ops, array_lengthof(Ops), MVT::i16,
12289 // Load FP Control Word from stack slot
12290 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12291 MachinePointerInfo(), false, false, false, 0);
12293 // Transform as necessary
12295 DAG.getNode(ISD::SRL, DL, MVT::i16,
12296 DAG.getNode(ISD::AND, DL, MVT::i16,
12297 CWD, DAG.getConstant(0x800, MVT::i16)),
12298 DAG.getConstant(11, MVT::i8));
12300 DAG.getNode(ISD::SRL, DL, MVT::i16,
12301 DAG.getNode(ISD::AND, DL, MVT::i16,
12302 CWD, DAG.getConstant(0x400, MVT::i16)),
12303 DAG.getConstant(9, MVT::i8));
12306 DAG.getNode(ISD::AND, DL, MVT::i16,
12307 DAG.getNode(ISD::ADD, DL, MVT::i16,
12308 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12309 DAG.getConstant(1, MVT::i16)),
12310 DAG.getConstant(3, MVT::i16));
12312 return DAG.getNode((VT.getSizeInBits() < 16 ?
12313 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12316 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12317 EVT VT = Op.getValueType();
12319 unsigned NumBits = VT.getSizeInBits();
12322 Op = Op.getOperand(0);
12323 if (VT == MVT::i8) {
12324 // Zero extend to i32 since there is not an i8 bsr.
12326 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12329 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12330 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12331 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12333 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12336 DAG.getConstant(NumBits+NumBits-1, OpVT),
12337 DAG.getConstant(X86::COND_E, MVT::i8),
12340 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12342 // Finally xor with NumBits-1.
12343 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12346 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12350 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12351 EVT VT = Op.getValueType();
12353 unsigned NumBits = VT.getSizeInBits();
12356 Op = Op.getOperand(0);
12357 if (VT == MVT::i8) {
12358 // Zero extend to i32 since there is not an i8 bsr.
12360 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12363 // Issue a bsr (scan bits in reverse).
12364 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12365 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12367 // And xor with NumBits-1.
12368 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12371 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12375 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12376 EVT VT = Op.getValueType();
12377 unsigned NumBits = VT.getSizeInBits();
12379 Op = Op.getOperand(0);
12381 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12382 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12383 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12385 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12388 DAG.getConstant(NumBits, VT),
12389 DAG.getConstant(X86::COND_E, MVT::i8),
12392 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12395 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12396 // ones, and then concatenate the result back.
12397 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12398 EVT VT = Op.getValueType();
12400 assert(VT.is256BitVector() && VT.isInteger() &&
12401 "Unsupported value type for operation");
12403 unsigned NumElems = VT.getVectorNumElements();
12406 // Extract the LHS vectors
12407 SDValue LHS = Op.getOperand(0);
12408 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12409 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12411 // Extract the RHS vectors
12412 SDValue RHS = Op.getOperand(1);
12413 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12414 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12416 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12417 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12419 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12420 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12421 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12424 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12425 assert(Op.getValueType().is256BitVector() &&
12426 Op.getValueType().isInteger() &&
12427 "Only handle AVX 256-bit vector integer operation");
12428 return Lower256IntArith(Op, DAG);
12431 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12432 assert(Op.getValueType().is256BitVector() &&
12433 Op.getValueType().isInteger() &&
12434 "Only handle AVX 256-bit vector integer operation");
12435 return Lower256IntArith(Op, DAG);
12438 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12439 SelectionDAG &DAG) {
12441 EVT VT = Op.getValueType();
12443 // Decompose 256-bit ops into smaller 128-bit ops.
12444 if (VT.is256BitVector() && !Subtarget->hasInt256())
12445 return Lower256IntArith(Op, DAG);
12447 SDValue A = Op.getOperand(0);
12448 SDValue B = Op.getOperand(1);
12450 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12451 if (VT == MVT::v4i32) {
12452 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12453 "Should not custom lower when pmuldq is available!");
12455 // Extract the odd parts.
12456 static const int UnpackMask[] = { 1, -1, 3, -1 };
12457 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12458 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12460 // Multiply the even parts.
12461 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12462 // Now multiply odd parts.
12463 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12465 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12466 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12468 // Merge the two vectors back together with a shuffle. This expands into 2
12470 static const int ShufMask[] = { 0, 4, 2, 6 };
12471 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12474 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12475 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12477 // Ahi = psrlqi(a, 32);
12478 // Bhi = psrlqi(b, 32);
12480 // AloBlo = pmuludq(a, b);
12481 // AloBhi = pmuludq(a, Bhi);
12482 // AhiBlo = pmuludq(Ahi, b);
12484 // AloBhi = psllqi(AloBhi, 32);
12485 // AhiBlo = psllqi(AhiBlo, 32);
12486 // return AloBlo + AloBhi + AhiBlo;
12488 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12489 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12491 // Bit cast to 32-bit vectors for MULUDQ
12492 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12493 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12494 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12495 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12496 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12497 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12499 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12500 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12501 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12503 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12504 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12506 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12507 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12510 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12511 EVT VT = Op.getValueType();
12512 EVT EltTy = VT.getVectorElementType();
12513 unsigned NumElts = VT.getVectorNumElements();
12514 SDValue N0 = Op.getOperand(0);
12517 // Lower sdiv X, pow2-const.
12518 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12522 APInt SplatValue, SplatUndef;
12523 unsigned SplatBitSize;
12525 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12527 EltTy.getSizeInBits() < SplatBitSize)
12530 if ((SplatValue != 0) &&
12531 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12532 unsigned Lg2 = SplatValue.countTrailingZeros();
12533 // Splat the sign bit.
12534 SmallVector<SDValue, 16> Sz(NumElts,
12535 DAG.getConstant(EltTy.getSizeInBits() - 1,
12537 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12538 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12540 // Add (N0 < 0) ? abs2 - 1 : 0;
12541 SmallVector<SDValue, 16> Amt(NumElts,
12542 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12544 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12545 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12547 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12548 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12549 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12550 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12553 // If we're dividing by a positive value, we're done. Otherwise, we must
12554 // negate the result.
12555 if (SplatValue.isNonNegative())
12558 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12559 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12560 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12565 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12566 const X86Subtarget *Subtarget) {
12567 EVT VT = Op.getValueType();
12569 SDValue R = Op.getOperand(0);
12570 SDValue Amt = Op.getOperand(1);
12572 // Optimize shl/srl/sra with constant shift amount.
12573 if (isSplatVector(Amt.getNode())) {
12574 SDValue SclrAmt = Amt->getOperand(0);
12575 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12576 uint64_t ShiftAmt = C->getZExtValue();
12578 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12579 (Subtarget->hasInt256() &&
12580 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12581 (Subtarget->hasAVX512() &&
12582 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12583 if (Op.getOpcode() == ISD::SHL)
12584 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12586 if (Op.getOpcode() == ISD::SRL)
12587 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12589 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12590 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12594 if (VT == MVT::v16i8) {
12595 if (Op.getOpcode() == ISD::SHL) {
12596 // Make a large shift.
12597 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12598 MVT::v8i16, R, ShiftAmt,
12600 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12601 // Zero out the rightmost bits.
12602 SmallVector<SDValue, 16> V(16,
12603 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12605 return DAG.getNode(ISD::AND, dl, VT, SHL,
12606 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12608 if (Op.getOpcode() == ISD::SRL) {
12609 // Make a large shift.
12610 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12611 MVT::v8i16, R, ShiftAmt,
12613 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12614 // Zero out the leftmost bits.
12615 SmallVector<SDValue, 16> V(16,
12616 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12618 return DAG.getNode(ISD::AND, dl, VT, SRL,
12619 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12621 if (Op.getOpcode() == ISD::SRA) {
12622 if (ShiftAmt == 7) {
12623 // R s>> 7 === R s< 0
12624 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12625 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12628 // R s>> a === ((R u>> a) ^ m) - m
12629 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12630 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12632 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12633 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12634 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12637 llvm_unreachable("Unknown shift opcode.");
12640 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12641 if (Op.getOpcode() == ISD::SHL) {
12642 // Make a large shift.
12643 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12644 MVT::v16i16, R, ShiftAmt,
12646 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12647 // Zero out the rightmost bits.
12648 SmallVector<SDValue, 32> V(32,
12649 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12651 return DAG.getNode(ISD::AND, dl, VT, SHL,
12652 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12654 if (Op.getOpcode() == ISD::SRL) {
12655 // Make a large shift.
12656 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12657 MVT::v16i16, R, ShiftAmt,
12659 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12660 // Zero out the leftmost bits.
12661 SmallVector<SDValue, 32> V(32,
12662 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12664 return DAG.getNode(ISD::AND, dl, VT, SRL,
12665 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12667 if (Op.getOpcode() == ISD::SRA) {
12668 if (ShiftAmt == 7) {
12669 // R s>> 7 === R s< 0
12670 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12671 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12674 // R s>> a === ((R u>> a) ^ m) - m
12675 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12676 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12678 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12679 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12680 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12683 llvm_unreachable("Unknown shift opcode.");
12688 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12689 if (!Subtarget->is64Bit() &&
12690 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12691 Amt.getOpcode() == ISD::BITCAST &&
12692 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12693 Amt = Amt.getOperand(0);
12694 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12695 VT.getVectorNumElements();
12696 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12697 uint64_t ShiftAmt = 0;
12698 for (unsigned i = 0; i != Ratio; ++i) {
12699 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12703 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12705 // Check remaining shift amounts.
12706 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12707 uint64_t ShAmt = 0;
12708 for (unsigned j = 0; j != Ratio; ++j) {
12709 ConstantSDNode *C =
12710 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12714 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12716 if (ShAmt != ShiftAmt)
12719 switch (Op.getOpcode()) {
12721 llvm_unreachable("Unknown shift opcode!");
12723 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12726 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12729 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12737 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12738 const X86Subtarget* Subtarget) {
12739 EVT VT = Op.getValueType();
12741 SDValue R = Op.getOperand(0);
12742 SDValue Amt = Op.getOperand(1);
12744 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12745 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12746 (Subtarget->hasInt256() &&
12747 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12748 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12749 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12751 EVT EltVT = VT.getVectorElementType();
12753 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12754 unsigned NumElts = VT.getVectorNumElements();
12756 for (i = 0; i != NumElts; ++i) {
12757 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12761 for (j = i; j != NumElts; ++j) {
12762 SDValue Arg = Amt.getOperand(j);
12763 if (Arg.getOpcode() == ISD::UNDEF) continue;
12764 if (Arg != Amt.getOperand(i))
12767 if (i != NumElts && j == NumElts)
12768 BaseShAmt = Amt.getOperand(i);
12770 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12771 Amt = Amt.getOperand(0);
12772 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12773 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12774 SDValue InVec = Amt.getOperand(0);
12775 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12776 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12778 for (; i != NumElts; ++i) {
12779 SDValue Arg = InVec.getOperand(i);
12780 if (Arg.getOpcode() == ISD::UNDEF) continue;
12784 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12785 if (ConstantSDNode *C =
12786 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12787 unsigned SplatIdx =
12788 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12789 if (C->getZExtValue() == SplatIdx)
12790 BaseShAmt = InVec.getOperand(1);
12793 if (BaseShAmt.getNode() == 0)
12794 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12795 DAG.getIntPtrConstant(0));
12799 if (BaseShAmt.getNode()) {
12800 if (EltVT.bitsGT(MVT::i32))
12801 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12802 else if (EltVT.bitsLT(MVT::i32))
12803 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12805 switch (Op.getOpcode()) {
12807 llvm_unreachable("Unknown shift opcode!");
12809 switch (VT.getSimpleVT().SimpleTy) {
12810 default: return SDValue();
12819 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12822 switch (VT.getSimpleVT().SimpleTy) {
12823 default: return SDValue();
12830 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12833 switch (VT.getSimpleVT().SimpleTy) {
12834 default: return SDValue();
12843 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12849 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12850 if (!Subtarget->is64Bit() &&
12851 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12852 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12853 Amt.getOpcode() == ISD::BITCAST &&
12854 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12855 Amt = Amt.getOperand(0);
12856 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12857 VT.getVectorNumElements();
12858 std::vector<SDValue> Vals(Ratio);
12859 for (unsigned i = 0; i != Ratio; ++i)
12860 Vals[i] = Amt.getOperand(i);
12861 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12862 for (unsigned j = 0; j != Ratio; ++j)
12863 if (Vals[j] != Amt.getOperand(i + j))
12866 switch (Op.getOpcode()) {
12868 llvm_unreachable("Unknown shift opcode!");
12870 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12872 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12874 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12881 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12882 SelectionDAG &DAG) {
12884 EVT VT = Op.getValueType();
12886 SDValue R = Op.getOperand(0);
12887 SDValue Amt = Op.getOperand(1);
12890 if (!Subtarget->hasSSE2())
12893 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12897 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12901 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12903 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12904 if (Subtarget->hasInt256()) {
12905 if (Op.getOpcode() == ISD::SRL &&
12906 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12907 VT == MVT::v4i64 || VT == MVT::v8i32))
12909 if (Op.getOpcode() == ISD::SHL &&
12910 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12911 VT == MVT::v4i64 || VT == MVT::v8i32))
12913 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12917 // Lower SHL with variable shift amount.
12918 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12919 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12921 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12922 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12923 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12924 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12926 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12927 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12930 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12931 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12933 // Turn 'a' into a mask suitable for VSELECT
12934 SDValue VSelM = DAG.getConstant(0x80, VT);
12935 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12936 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12938 SDValue CM1 = DAG.getConstant(0x0f, VT);
12939 SDValue CM2 = DAG.getConstant(0x3f, VT);
12941 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12942 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12943 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
12944 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12945 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12948 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12949 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12950 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12952 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12953 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12954 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
12955 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12956 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12959 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12960 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12961 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12963 // return VSELECT(r, r+r, a);
12964 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12965 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12969 // Decompose 256-bit shifts into smaller 128-bit shifts.
12970 if (VT.is256BitVector()) {
12971 unsigned NumElems = VT.getVectorNumElements();
12972 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12973 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12975 // Extract the two vectors
12976 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12977 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12979 // Recreate the shift amount vectors
12980 SDValue Amt1, Amt2;
12981 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12982 // Constant shift amount
12983 SmallVector<SDValue, 4> Amt1Csts;
12984 SmallVector<SDValue, 4> Amt2Csts;
12985 for (unsigned i = 0; i != NumElems/2; ++i)
12986 Amt1Csts.push_back(Amt->getOperand(i));
12987 for (unsigned i = NumElems/2; i != NumElems; ++i)
12988 Amt2Csts.push_back(Amt->getOperand(i));
12990 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12991 &Amt1Csts[0], NumElems/2);
12992 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12993 &Amt2Csts[0], NumElems/2);
12995 // Variable shift amount
12996 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12997 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13000 // Issue new vector shifts for the smaller types
13001 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13002 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13004 // Concatenate the result back
13005 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13011 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13012 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13013 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13014 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13015 // has only one use.
13016 SDNode *N = Op.getNode();
13017 SDValue LHS = N->getOperand(0);
13018 SDValue RHS = N->getOperand(1);
13019 unsigned BaseOp = 0;
13022 switch (Op.getOpcode()) {
13023 default: llvm_unreachable("Unknown ovf instruction!");
13025 // A subtract of one will be selected as a INC. Note that INC doesn't
13026 // set CF, so we can't do this for UADDO.
13027 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13029 BaseOp = X86ISD::INC;
13030 Cond = X86::COND_O;
13033 BaseOp = X86ISD::ADD;
13034 Cond = X86::COND_O;
13037 BaseOp = X86ISD::ADD;
13038 Cond = X86::COND_B;
13041 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13042 // set CF, so we can't do this for USUBO.
13043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13045 BaseOp = X86ISD::DEC;
13046 Cond = X86::COND_O;
13049 BaseOp = X86ISD::SUB;
13050 Cond = X86::COND_O;
13053 BaseOp = X86ISD::SUB;
13054 Cond = X86::COND_B;
13057 BaseOp = X86ISD::SMUL;
13058 Cond = X86::COND_O;
13060 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13061 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13063 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13066 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13067 DAG.getConstant(X86::COND_O, MVT::i32),
13068 SDValue(Sum.getNode(), 2));
13070 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13074 // Also sets EFLAGS.
13075 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13076 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13079 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13080 DAG.getConstant(Cond, MVT::i32),
13081 SDValue(Sum.getNode(), 1));
13083 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13086 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13087 SelectionDAG &DAG) const {
13089 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13090 EVT VT = Op.getValueType();
13092 if (!Subtarget->hasSSE2() || !VT.isVector())
13095 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13096 ExtraVT.getScalarType().getSizeInBits();
13098 switch (VT.getSimpleVT().SimpleTy) {
13099 default: return SDValue();
13102 if (!Subtarget->hasFp256())
13104 if (!Subtarget->hasInt256()) {
13105 // needs to be split
13106 unsigned NumElems = VT.getVectorNumElements();
13108 // Extract the LHS vectors
13109 SDValue LHS = Op.getOperand(0);
13110 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13111 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13113 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13114 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13116 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13117 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13118 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13120 SDValue Extra = DAG.getValueType(ExtraVT);
13122 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13123 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13125 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13130 // (sext (vzext x)) -> (vsext x)
13131 SDValue Op0 = Op.getOperand(0);
13132 SDValue Op00 = Op0.getOperand(0);
13134 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13135 if (Op0.getOpcode() == ISD::BITCAST &&
13136 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13137 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13138 if (Tmp1.getNode()) {
13139 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13140 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13141 "This optimization is invalid without a VZEXT.");
13142 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13145 // If the above didn't work, then just use Shift-Left + Shift-Right.
13146 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13148 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13154 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13155 SelectionDAG &DAG) {
13157 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13158 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13159 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13160 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13162 // The only fence that needs an instruction is a sequentially-consistent
13163 // cross-thread fence.
13164 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13165 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13166 // no-sse2). There isn't any reason to disable it if the target processor
13168 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13169 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13171 SDValue Chain = Op.getOperand(0);
13172 SDValue Zero = DAG.getConstant(0, MVT::i32);
13174 DAG.getRegister(X86::ESP, MVT::i32), // Base
13175 DAG.getTargetConstant(1, MVT::i8), // Scale
13176 DAG.getRegister(0, MVT::i32), // Index
13177 DAG.getTargetConstant(0, MVT::i32), // Disp
13178 DAG.getRegister(0, MVT::i32), // Segment.
13182 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13183 return SDValue(Res, 0);
13186 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13187 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13190 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13191 SelectionDAG &DAG) {
13192 EVT T = Op.getValueType();
13196 switch(T.getSimpleVT().SimpleTy) {
13197 default: llvm_unreachable("Invalid value type!");
13198 case MVT::i8: Reg = X86::AL; size = 1; break;
13199 case MVT::i16: Reg = X86::AX; size = 2; break;
13200 case MVT::i32: Reg = X86::EAX; size = 4; break;
13202 assert(Subtarget->is64Bit() && "Node not type legal!");
13203 Reg = X86::RAX; size = 8;
13206 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13207 Op.getOperand(2), SDValue());
13208 SDValue Ops[] = { cpIn.getValue(0),
13211 DAG.getTargetConstant(size, MVT::i8),
13212 cpIn.getValue(1) };
13213 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13214 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13215 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13216 Ops, array_lengthof(Ops), T, MMO);
13218 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13222 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13223 SelectionDAG &DAG) {
13224 assert(Subtarget->is64Bit() && "Result not type legalized?");
13225 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13226 SDValue TheChain = Op.getOperand(0);
13228 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13229 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13230 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13232 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13233 DAG.getConstant(32, MVT::i8));
13235 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13238 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13241 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13242 SelectionDAG &DAG) {
13243 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13244 MVT DstVT = Op.getSimpleValueType();
13245 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13246 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13247 assert((DstVT == MVT::i64 ||
13248 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13249 "Unexpected custom BITCAST");
13250 // i64 <=> MMX conversions are Legal.
13251 if (SrcVT==MVT::i64 && DstVT.isVector())
13253 if (DstVT==MVT::i64 && SrcVT.isVector())
13255 // MMX <=> MMX conversions are Legal.
13256 if (SrcVT.isVector() && DstVT.isVector())
13258 // All other conversions need to be expanded.
13262 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13263 SDNode *Node = Op.getNode();
13265 EVT T = Node->getValueType(0);
13266 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13267 DAG.getConstant(0, T), Node->getOperand(2));
13268 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13269 cast<AtomicSDNode>(Node)->getMemoryVT(),
13270 Node->getOperand(0),
13271 Node->getOperand(1), negOp,
13272 cast<AtomicSDNode>(Node)->getSrcValue(),
13273 cast<AtomicSDNode>(Node)->getAlignment(),
13274 cast<AtomicSDNode>(Node)->getOrdering(),
13275 cast<AtomicSDNode>(Node)->getSynchScope());
13278 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13279 SDNode *Node = Op.getNode();
13281 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13283 // Convert seq_cst store -> xchg
13284 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13285 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13286 // (The only way to get a 16-byte store is cmpxchg16b)
13287 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13288 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13289 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13290 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13291 cast<AtomicSDNode>(Node)->getMemoryVT(),
13292 Node->getOperand(0),
13293 Node->getOperand(1), Node->getOperand(2),
13294 cast<AtomicSDNode>(Node)->getMemOperand(),
13295 cast<AtomicSDNode>(Node)->getOrdering(),
13296 cast<AtomicSDNode>(Node)->getSynchScope());
13297 return Swap.getValue(1);
13299 // Other atomic stores have a simple pattern.
13303 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13304 EVT VT = Op.getNode()->getValueType(0);
13306 // Let legalize expand this if it isn't a legal type yet.
13307 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13310 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13313 bool ExtraOp = false;
13314 switch (Op.getOpcode()) {
13315 default: llvm_unreachable("Invalid code");
13316 case ISD::ADDC: Opc = X86ISD::ADD; break;
13317 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13318 case ISD::SUBC: Opc = X86ISD::SUB; break;
13319 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13323 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13325 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13326 Op.getOperand(1), Op.getOperand(2));
13329 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13330 SelectionDAG &DAG) {
13331 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13333 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13334 // which returns the values as { float, float } (in XMM0) or
13335 // { double, double } (which is returned in XMM0, XMM1).
13337 SDValue Arg = Op.getOperand(0);
13338 EVT ArgVT = Arg.getValueType();
13339 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13341 TargetLowering::ArgListTy Args;
13342 TargetLowering::ArgListEntry Entry;
13346 Entry.isSExt = false;
13347 Entry.isZExt = false;
13348 Args.push_back(Entry);
13350 bool isF64 = ArgVT == MVT::f64;
13351 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13352 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13353 // the results are returned via SRet in memory.
13354 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13356 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13358 Type *RetTy = isF64
13359 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13360 : (Type*)VectorType::get(ArgTy, 4);
13362 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13363 false, false, false, false, 0,
13364 CallingConv::C, /*isTaillCall=*/false,
13365 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13366 Callee, Args, DAG, dl);
13367 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13370 // Returned in xmm0 and xmm1.
13371 return CallResult.first;
13373 // Returned in bits 0:31 and 32:64 xmm0.
13374 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13375 CallResult.first, DAG.getIntPtrConstant(0));
13376 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13377 CallResult.first, DAG.getIntPtrConstant(1));
13378 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13379 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13382 /// LowerOperation - Provide custom lowering hooks for some operations.
13384 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13385 switch (Op.getOpcode()) {
13386 default: llvm_unreachable("Should not custom lower this!");
13387 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13388 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13389 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13390 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13391 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13392 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13393 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13394 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13395 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13396 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13397 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13398 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13399 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13400 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13401 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13402 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13403 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13404 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13405 case ISD::SHL_PARTS:
13406 case ISD::SRA_PARTS:
13407 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13408 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13409 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13410 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13411 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13412 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13413 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13414 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13415 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13416 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13417 case ISD::FABS: return LowerFABS(Op, DAG);
13418 case ISD::FNEG: return LowerFNEG(Op, DAG);
13419 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13420 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13421 case ISD::SETCC: return LowerSETCC(Op, DAG);
13422 case ISD::SELECT: return LowerSELECT(Op, DAG);
13423 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13424 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13425 case ISD::VASTART: return LowerVASTART(Op, DAG);
13426 case ISD::VAARG: return LowerVAARG(Op, DAG);
13427 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13428 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13429 case ISD::INTRINSIC_VOID:
13430 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13431 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13432 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13433 case ISD::FRAME_TO_ARGS_OFFSET:
13434 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13435 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13436 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13437 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13438 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13439 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13440 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13441 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13442 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13443 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13444 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13445 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13448 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13454 case ISD::UMULO: return LowerXALUO(Op, DAG);
13455 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13456 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13460 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13461 case ISD::ADD: return LowerADD(Op, DAG);
13462 case ISD::SUB: return LowerSUB(Op, DAG);
13463 case ISD::SDIV: return LowerSDIV(Op, DAG);
13464 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13468 static void ReplaceATOMIC_LOAD(SDNode *Node,
13469 SmallVectorImpl<SDValue> &Results,
13470 SelectionDAG &DAG) {
13472 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13474 // Convert wide load -> cmpxchg8b/cmpxchg16b
13475 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13476 // (The only way to get a 16-byte load is cmpxchg16b)
13477 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13478 SDValue Zero = DAG.getConstant(0, VT);
13479 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13480 Node->getOperand(0),
13481 Node->getOperand(1), Zero, Zero,
13482 cast<AtomicSDNode>(Node)->getMemOperand(),
13483 cast<AtomicSDNode>(Node)->getOrdering(),
13484 cast<AtomicSDNode>(Node)->getSynchScope());
13485 Results.push_back(Swap.getValue(0));
13486 Results.push_back(Swap.getValue(1));
13490 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13491 SelectionDAG &DAG, unsigned NewOp) {
13493 assert (Node->getValueType(0) == MVT::i64 &&
13494 "Only know how to expand i64 atomics");
13496 SDValue Chain = Node->getOperand(0);
13497 SDValue In1 = Node->getOperand(1);
13498 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13499 Node->getOperand(2), DAG.getIntPtrConstant(0));
13500 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13501 Node->getOperand(2), DAG.getIntPtrConstant(1));
13502 SDValue Ops[] = { Chain, In1, In2L, In2H };
13503 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13505 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13506 cast<MemSDNode>(Node)->getMemOperand());
13507 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13508 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13509 Results.push_back(Result.getValue(2));
13512 /// ReplaceNodeResults - Replace a node with an illegal result type
13513 /// with a new node built out of custom code.
13514 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13515 SmallVectorImpl<SDValue>&Results,
13516 SelectionDAG &DAG) const {
13518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13519 switch (N->getOpcode()) {
13521 llvm_unreachable("Do not know how to custom type legalize this operation!");
13522 case ISD::SIGN_EXTEND_INREG:
13527 // We don't want to expand or promote these.
13529 case ISD::FP_TO_SINT:
13530 case ISD::FP_TO_UINT: {
13531 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13533 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13536 std::pair<SDValue,SDValue> Vals =
13537 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13538 SDValue FIST = Vals.first, StackSlot = Vals.second;
13539 if (FIST.getNode() != 0) {
13540 EVT VT = N->getValueType(0);
13541 // Return a load from the stack slot.
13542 if (StackSlot.getNode() != 0)
13543 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13544 MachinePointerInfo(),
13545 false, false, false, 0));
13547 Results.push_back(FIST);
13551 case ISD::UINT_TO_FP: {
13552 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13553 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13554 N->getValueType(0) != MVT::v2f32)
13556 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13558 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13560 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13561 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13562 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13563 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13564 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13565 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13568 case ISD::FP_ROUND: {
13569 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13571 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13572 Results.push_back(V);
13575 case ISD::READCYCLECOUNTER: {
13576 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13577 SDValue TheChain = N->getOperand(0);
13578 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13579 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13581 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13583 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13584 SDValue Ops[] = { eax, edx };
13585 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13586 array_lengthof(Ops)));
13587 Results.push_back(edx.getValue(1));
13590 case ISD::ATOMIC_CMP_SWAP: {
13591 EVT T = N->getValueType(0);
13592 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13593 bool Regs64bit = T == MVT::i128;
13594 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13595 SDValue cpInL, cpInH;
13596 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13597 DAG.getConstant(0, HalfT));
13598 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13599 DAG.getConstant(1, HalfT));
13600 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13601 Regs64bit ? X86::RAX : X86::EAX,
13603 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13604 Regs64bit ? X86::RDX : X86::EDX,
13605 cpInH, cpInL.getValue(1));
13606 SDValue swapInL, swapInH;
13607 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13608 DAG.getConstant(0, HalfT));
13609 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13610 DAG.getConstant(1, HalfT));
13611 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13612 Regs64bit ? X86::RBX : X86::EBX,
13613 swapInL, cpInH.getValue(1));
13614 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13615 Regs64bit ? X86::RCX : X86::ECX,
13616 swapInH, swapInL.getValue(1));
13617 SDValue Ops[] = { swapInH.getValue(0),
13619 swapInH.getValue(1) };
13620 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13621 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13622 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13623 X86ISD::LCMPXCHG8_DAG;
13624 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13625 Ops, array_lengthof(Ops), T, MMO);
13626 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13627 Regs64bit ? X86::RAX : X86::EAX,
13628 HalfT, Result.getValue(1));
13629 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13630 Regs64bit ? X86::RDX : X86::EDX,
13631 HalfT, cpOutL.getValue(2));
13632 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13633 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13634 Results.push_back(cpOutH.getValue(1));
13637 case ISD::ATOMIC_LOAD_ADD:
13638 case ISD::ATOMIC_LOAD_AND:
13639 case ISD::ATOMIC_LOAD_NAND:
13640 case ISD::ATOMIC_LOAD_OR:
13641 case ISD::ATOMIC_LOAD_SUB:
13642 case ISD::ATOMIC_LOAD_XOR:
13643 case ISD::ATOMIC_LOAD_MAX:
13644 case ISD::ATOMIC_LOAD_MIN:
13645 case ISD::ATOMIC_LOAD_UMAX:
13646 case ISD::ATOMIC_LOAD_UMIN:
13647 case ISD::ATOMIC_SWAP: {
13649 switch (N->getOpcode()) {
13650 default: llvm_unreachable("Unexpected opcode");
13651 case ISD::ATOMIC_LOAD_ADD:
13652 Opc = X86ISD::ATOMADD64_DAG;
13654 case ISD::ATOMIC_LOAD_AND:
13655 Opc = X86ISD::ATOMAND64_DAG;
13657 case ISD::ATOMIC_LOAD_NAND:
13658 Opc = X86ISD::ATOMNAND64_DAG;
13660 case ISD::ATOMIC_LOAD_OR:
13661 Opc = X86ISD::ATOMOR64_DAG;
13663 case ISD::ATOMIC_LOAD_SUB:
13664 Opc = X86ISD::ATOMSUB64_DAG;
13666 case ISD::ATOMIC_LOAD_XOR:
13667 Opc = X86ISD::ATOMXOR64_DAG;
13669 case ISD::ATOMIC_LOAD_MAX:
13670 Opc = X86ISD::ATOMMAX64_DAG;
13672 case ISD::ATOMIC_LOAD_MIN:
13673 Opc = X86ISD::ATOMMIN64_DAG;
13675 case ISD::ATOMIC_LOAD_UMAX:
13676 Opc = X86ISD::ATOMUMAX64_DAG;
13678 case ISD::ATOMIC_LOAD_UMIN:
13679 Opc = X86ISD::ATOMUMIN64_DAG;
13681 case ISD::ATOMIC_SWAP:
13682 Opc = X86ISD::ATOMSWAP64_DAG;
13685 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13688 case ISD::ATOMIC_LOAD:
13689 ReplaceATOMIC_LOAD(N, Results, DAG);
13693 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13695 default: return NULL;
13696 case X86ISD::BSF: return "X86ISD::BSF";
13697 case X86ISD::BSR: return "X86ISD::BSR";
13698 case X86ISD::SHLD: return "X86ISD::SHLD";
13699 case X86ISD::SHRD: return "X86ISD::SHRD";
13700 case X86ISD::FAND: return "X86ISD::FAND";
13701 case X86ISD::FANDN: return "X86ISD::FANDN";
13702 case X86ISD::FOR: return "X86ISD::FOR";
13703 case X86ISD::FXOR: return "X86ISD::FXOR";
13704 case X86ISD::FSRL: return "X86ISD::FSRL";
13705 case X86ISD::FILD: return "X86ISD::FILD";
13706 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13707 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13708 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13709 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13710 case X86ISD::FLD: return "X86ISD::FLD";
13711 case X86ISD::FST: return "X86ISD::FST";
13712 case X86ISD::CALL: return "X86ISD::CALL";
13713 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13714 case X86ISD::BT: return "X86ISD::BT";
13715 case X86ISD::CMP: return "X86ISD::CMP";
13716 case X86ISD::COMI: return "X86ISD::COMI";
13717 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13718 case X86ISD::CMPM: return "X86ISD::CMPM";
13719 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13720 case X86ISD::SETCC: return "X86ISD::SETCC";
13721 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13722 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13723 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13724 case X86ISD::CMOV: return "X86ISD::CMOV";
13725 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13726 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13727 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13728 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13729 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13730 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13731 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13732 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13733 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13734 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13735 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13736 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13737 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13738 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13739 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13740 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13741 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13742 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13743 case X86ISD::HADD: return "X86ISD::HADD";
13744 case X86ISD::HSUB: return "X86ISD::HSUB";
13745 case X86ISD::FHADD: return "X86ISD::FHADD";
13746 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13747 case X86ISD::UMAX: return "X86ISD::UMAX";
13748 case X86ISD::UMIN: return "X86ISD::UMIN";
13749 case X86ISD::SMAX: return "X86ISD::SMAX";
13750 case X86ISD::SMIN: return "X86ISD::SMIN";
13751 case X86ISD::FMAX: return "X86ISD::FMAX";
13752 case X86ISD::FMIN: return "X86ISD::FMIN";
13753 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13754 case X86ISD::FMINC: return "X86ISD::FMINC";
13755 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13756 case X86ISD::FRCP: return "X86ISD::FRCP";
13757 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13758 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13759 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13760 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13761 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13762 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13763 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13764 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13765 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13766 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13767 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13768 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13769 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13770 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13771 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13772 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13773 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13774 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13775 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13776 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13777 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13778 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13779 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13780 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13781 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13782 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13783 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13784 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13785 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13786 case X86ISD::VSHL: return "X86ISD::VSHL";
13787 case X86ISD::VSRL: return "X86ISD::VSRL";
13788 case X86ISD::VSRA: return "X86ISD::VSRA";
13789 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13790 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13791 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13792 case X86ISD::CMPP: return "X86ISD::CMPP";
13793 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13794 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13795 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13796 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13797 case X86ISD::ADD: return "X86ISD::ADD";
13798 case X86ISD::SUB: return "X86ISD::SUB";
13799 case X86ISD::ADC: return "X86ISD::ADC";
13800 case X86ISD::SBB: return "X86ISD::SBB";
13801 case X86ISD::SMUL: return "X86ISD::SMUL";
13802 case X86ISD::UMUL: return "X86ISD::UMUL";
13803 case X86ISD::INC: return "X86ISD::INC";
13804 case X86ISD::DEC: return "X86ISD::DEC";
13805 case X86ISD::OR: return "X86ISD::OR";
13806 case X86ISD::XOR: return "X86ISD::XOR";
13807 case X86ISD::AND: return "X86ISD::AND";
13808 case X86ISD::BLSI: return "X86ISD::BLSI";
13809 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13810 case X86ISD::BLSR: return "X86ISD::BLSR";
13811 case X86ISD::BZHI: return "X86ISD::BZHI";
13812 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13813 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13814 case X86ISD::PTEST: return "X86ISD::PTEST";
13815 case X86ISD::TESTP: return "X86ISD::TESTP";
13816 case X86ISD::TESTM: return "X86ISD::TESTM";
13817 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13818 case X86ISD::KTEST: return "X86ISD::KTEST";
13819 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13820 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13821 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13822 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13823 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13824 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13825 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13826 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13827 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13828 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13829 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13830 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13831 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13832 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13833 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13834 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13835 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13836 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13837 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13838 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13839 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13840 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13841 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13842 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13843 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13844 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13845 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13846 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13847 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13848 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13849 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13850 case X86ISD::SAHF: return "X86ISD::SAHF";
13851 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13852 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13853 case X86ISD::FMADD: return "X86ISD::FMADD";
13854 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13855 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13856 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13857 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13858 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13859 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13860 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13861 case X86ISD::XTEST: return "X86ISD::XTEST";
13865 // isLegalAddressingMode - Return true if the addressing mode represented
13866 // by AM is legal for this target, for a load/store of the specified type.
13867 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13869 // X86 supports extremely general addressing modes.
13870 CodeModel::Model M = getTargetMachine().getCodeModel();
13871 Reloc::Model R = getTargetMachine().getRelocationModel();
13873 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13874 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13879 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13881 // If a reference to this global requires an extra load, we can't fold it.
13882 if (isGlobalStubReference(GVFlags))
13885 // If BaseGV requires a register for the PIC base, we cannot also have a
13886 // BaseReg specified.
13887 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13890 // If lower 4G is not available, then we must use rip-relative addressing.
13891 if ((M != CodeModel::Small || R != Reloc::Static) &&
13892 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13896 switch (AM.Scale) {
13902 // These scales always work.
13907 // These scales are formed with basereg+scalereg. Only accept if there is
13912 default: // Other stuff never works.
13919 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13920 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13922 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13923 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13924 return NumBits1 > NumBits2;
13927 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13928 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13931 if (!isTypeLegal(EVT::getEVT(Ty1)))
13934 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13936 // Assuming the caller doesn't have a zeroext or signext return parameter,
13937 // truncation all the way down to i1 is valid.
13941 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13942 return isInt<32>(Imm);
13945 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13946 // Can also use sub to handle negated immediates.
13947 return isInt<32>(Imm);
13950 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13951 if (!VT1.isInteger() || !VT2.isInteger())
13953 unsigned NumBits1 = VT1.getSizeInBits();
13954 unsigned NumBits2 = VT2.getSizeInBits();
13955 return NumBits1 > NumBits2;
13958 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13959 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13960 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13963 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13964 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13965 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13968 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13969 EVT VT1 = Val.getValueType();
13970 if (isZExtFree(VT1, VT2))
13973 if (Val.getOpcode() != ISD::LOAD)
13976 if (!VT1.isSimple() || !VT1.isInteger() ||
13977 !VT2.isSimple() || !VT2.isInteger())
13980 switch (VT1.getSimpleVT().SimpleTy) {
13985 // X86 has 8, 16, and 32-bit zero-extending loads.
13993 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13994 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13997 VT = VT.getScalarType();
13999 if (!VT.isSimple())
14002 switch (VT.getSimpleVT().SimpleTy) {
14013 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14014 // i16 instructions are longer (0x66 prefix) and potentially slower.
14015 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14018 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14019 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14020 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14021 /// are assumed to be legal.
14023 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14025 if (!VT.isSimple())
14028 MVT SVT = VT.getSimpleVT();
14030 // Very little shuffling can be done for 64-bit vectors right now.
14031 if (VT.getSizeInBits() == 64)
14034 // FIXME: pshufb, blends, shifts.
14035 return (SVT.getVectorNumElements() == 2 ||
14036 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14037 isMOVLMask(M, SVT) ||
14038 isSHUFPMask(M, SVT) ||
14039 isPSHUFDMask(M, SVT) ||
14040 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14041 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14042 isPALIGNRMask(M, SVT, Subtarget) ||
14043 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14044 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14045 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14046 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14050 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14052 if (!VT.isSimple())
14055 MVT SVT = VT.getSimpleVT();
14056 unsigned NumElts = SVT.getVectorNumElements();
14057 // FIXME: This collection of masks seems suspect.
14060 if (NumElts == 4 && SVT.is128BitVector()) {
14061 return (isMOVLMask(Mask, SVT) ||
14062 isCommutedMOVLMask(Mask, SVT, true) ||
14063 isSHUFPMask(Mask, SVT) ||
14064 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14069 //===----------------------------------------------------------------------===//
14070 // X86 Scheduler Hooks
14071 //===----------------------------------------------------------------------===//
14073 /// Utility function to emit xbegin specifying the start of an RTM region.
14074 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14075 const TargetInstrInfo *TII) {
14076 DebugLoc DL = MI->getDebugLoc();
14078 const BasicBlock *BB = MBB->getBasicBlock();
14079 MachineFunction::iterator I = MBB;
14082 // For the v = xbegin(), we generate
14093 MachineBasicBlock *thisMBB = MBB;
14094 MachineFunction *MF = MBB->getParent();
14095 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14096 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14097 MF->insert(I, mainMBB);
14098 MF->insert(I, sinkMBB);
14100 // Transfer the remainder of BB and its successor edges to sinkMBB.
14101 sinkMBB->splice(sinkMBB->begin(), MBB,
14102 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14103 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14107 // # fallthrough to mainMBB
14108 // # abortion to sinkMBB
14109 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14110 thisMBB->addSuccessor(mainMBB);
14111 thisMBB->addSuccessor(sinkMBB);
14115 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14116 mainMBB->addSuccessor(sinkMBB);
14119 // EAX is live into the sinkMBB
14120 sinkMBB->addLiveIn(X86::EAX);
14121 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14122 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14125 MI->eraseFromParent();
14129 // Get CMPXCHG opcode for the specified data type.
14130 static unsigned getCmpXChgOpcode(EVT VT) {
14131 switch (VT.getSimpleVT().SimpleTy) {
14132 case MVT::i8: return X86::LCMPXCHG8;
14133 case MVT::i16: return X86::LCMPXCHG16;
14134 case MVT::i32: return X86::LCMPXCHG32;
14135 case MVT::i64: return X86::LCMPXCHG64;
14139 llvm_unreachable("Invalid operand size!");
14142 // Get LOAD opcode for the specified data type.
14143 static unsigned getLoadOpcode(EVT VT) {
14144 switch (VT.getSimpleVT().SimpleTy) {
14145 case MVT::i8: return X86::MOV8rm;
14146 case MVT::i16: return X86::MOV16rm;
14147 case MVT::i32: return X86::MOV32rm;
14148 case MVT::i64: return X86::MOV64rm;
14152 llvm_unreachable("Invalid operand size!");
14155 // Get opcode of the non-atomic one from the specified atomic instruction.
14156 static unsigned getNonAtomicOpcode(unsigned Opc) {
14158 case X86::ATOMAND8: return X86::AND8rr;
14159 case X86::ATOMAND16: return X86::AND16rr;
14160 case X86::ATOMAND32: return X86::AND32rr;
14161 case X86::ATOMAND64: return X86::AND64rr;
14162 case X86::ATOMOR8: return X86::OR8rr;
14163 case X86::ATOMOR16: return X86::OR16rr;
14164 case X86::ATOMOR32: return X86::OR32rr;
14165 case X86::ATOMOR64: return X86::OR64rr;
14166 case X86::ATOMXOR8: return X86::XOR8rr;
14167 case X86::ATOMXOR16: return X86::XOR16rr;
14168 case X86::ATOMXOR32: return X86::XOR32rr;
14169 case X86::ATOMXOR64: return X86::XOR64rr;
14171 llvm_unreachable("Unhandled atomic-load-op opcode!");
14174 // Get opcode of the non-atomic one from the specified atomic instruction with
14176 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14177 unsigned &ExtraOpc) {
14179 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14180 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14181 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14182 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14183 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14184 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14185 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14186 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14187 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14188 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14189 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14190 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14191 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14192 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14193 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14194 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14195 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14196 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14197 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14198 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14200 llvm_unreachable("Unhandled atomic-load-op opcode!");
14203 // Get opcode of the non-atomic one from the specified atomic instruction for
14204 // 64-bit data type on 32-bit target.
14205 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14207 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14208 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14209 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14210 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14211 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14212 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14213 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14214 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14215 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14216 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14218 llvm_unreachable("Unhandled atomic-load-op opcode!");
14221 // Get opcode of the non-atomic one from the specified atomic instruction for
14222 // 64-bit data type on 32-bit target with extra opcode.
14223 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14225 unsigned &ExtraOpc) {
14227 case X86::ATOMNAND6432:
14228 ExtraOpc = X86::NOT32r;
14229 HiOpc = X86::AND32rr;
14230 return X86::AND32rr;
14232 llvm_unreachable("Unhandled atomic-load-op opcode!");
14235 // Get pseudo CMOV opcode from the specified data type.
14236 static unsigned getPseudoCMOVOpc(EVT VT) {
14237 switch (VT.getSimpleVT().SimpleTy) {
14238 case MVT::i8: return X86::CMOV_GR8;
14239 case MVT::i16: return X86::CMOV_GR16;
14240 case MVT::i32: return X86::CMOV_GR32;
14244 llvm_unreachable("Unknown CMOV opcode!");
14247 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14248 // They will be translated into a spin-loop or compare-exchange loop from
14251 // dst = atomic-fetch-op MI.addr, MI.val
14257 // t1 = LOAD MI.addr
14259 // t4 = phi(t1, t3 / loop)
14260 // t2 = OP MI.val, t4
14262 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14268 MachineBasicBlock *
14269 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14270 MachineBasicBlock *MBB) const {
14271 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14272 DebugLoc DL = MI->getDebugLoc();
14274 MachineFunction *MF = MBB->getParent();
14275 MachineRegisterInfo &MRI = MF->getRegInfo();
14277 const BasicBlock *BB = MBB->getBasicBlock();
14278 MachineFunction::iterator I = MBB;
14281 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14282 "Unexpected number of operands");
14284 assert(MI->hasOneMemOperand() &&
14285 "Expected atomic-load-op to have one memoperand");
14287 // Memory Reference
14288 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14289 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14291 unsigned DstReg, SrcReg;
14292 unsigned MemOpndSlot;
14294 unsigned CurOp = 0;
14296 DstReg = MI->getOperand(CurOp++).getReg();
14297 MemOpndSlot = CurOp;
14298 CurOp += X86::AddrNumOperands;
14299 SrcReg = MI->getOperand(CurOp++).getReg();
14301 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14302 MVT::SimpleValueType VT = *RC->vt_begin();
14303 unsigned t1 = MRI.createVirtualRegister(RC);
14304 unsigned t2 = MRI.createVirtualRegister(RC);
14305 unsigned t3 = MRI.createVirtualRegister(RC);
14306 unsigned t4 = MRI.createVirtualRegister(RC);
14307 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14309 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14310 unsigned LOADOpc = getLoadOpcode(VT);
14312 // For the atomic load-arith operator, we generate
14315 // t1 = LOAD [MI.addr]
14317 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14318 // t1 = OP MI.val, EAX
14320 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14326 MachineBasicBlock *thisMBB = MBB;
14327 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14328 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14329 MF->insert(I, mainMBB);
14330 MF->insert(I, sinkMBB);
14332 MachineInstrBuilder MIB;
14334 // Transfer the remainder of BB and its successor edges to sinkMBB.
14335 sinkMBB->splice(sinkMBB->begin(), MBB,
14336 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14337 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14340 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14341 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14342 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14344 NewMO.setIsKill(false);
14345 MIB.addOperand(NewMO);
14347 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14348 unsigned flags = (*MMOI)->getFlags();
14349 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14350 MachineMemOperand *MMO =
14351 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14352 (*MMOI)->getSize(),
14353 (*MMOI)->getBaseAlignment(),
14354 (*MMOI)->getTBAAInfo(),
14355 (*MMOI)->getRanges());
14356 MIB.addMemOperand(MMO);
14359 thisMBB->addSuccessor(mainMBB);
14362 MachineBasicBlock *origMainMBB = mainMBB;
14365 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14366 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14368 unsigned Opc = MI->getOpcode();
14371 llvm_unreachable("Unhandled atomic-load-op opcode!");
14372 case X86::ATOMAND8:
14373 case X86::ATOMAND16:
14374 case X86::ATOMAND32:
14375 case X86::ATOMAND64:
14377 case X86::ATOMOR16:
14378 case X86::ATOMOR32:
14379 case X86::ATOMOR64:
14380 case X86::ATOMXOR8:
14381 case X86::ATOMXOR16:
14382 case X86::ATOMXOR32:
14383 case X86::ATOMXOR64: {
14384 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14385 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14389 case X86::ATOMNAND8:
14390 case X86::ATOMNAND16:
14391 case X86::ATOMNAND32:
14392 case X86::ATOMNAND64: {
14393 unsigned Tmp = MRI.createVirtualRegister(RC);
14395 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14396 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14398 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14401 case X86::ATOMMAX8:
14402 case X86::ATOMMAX16:
14403 case X86::ATOMMAX32:
14404 case X86::ATOMMAX64:
14405 case X86::ATOMMIN8:
14406 case X86::ATOMMIN16:
14407 case X86::ATOMMIN32:
14408 case X86::ATOMMIN64:
14409 case X86::ATOMUMAX8:
14410 case X86::ATOMUMAX16:
14411 case X86::ATOMUMAX32:
14412 case X86::ATOMUMAX64:
14413 case X86::ATOMUMIN8:
14414 case X86::ATOMUMIN16:
14415 case X86::ATOMUMIN32:
14416 case X86::ATOMUMIN64: {
14418 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14420 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14424 if (Subtarget->hasCMov()) {
14425 if (VT != MVT::i8) {
14427 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14431 // Promote i8 to i32 to use CMOV32
14432 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14433 const TargetRegisterClass *RC32 =
14434 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14435 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14436 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14437 unsigned Tmp = MRI.createVirtualRegister(RC32);
14439 unsigned Undef = MRI.createVirtualRegister(RC32);
14440 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14442 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14445 .addImm(X86::sub_8bit);
14446 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14449 .addImm(X86::sub_8bit);
14451 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14455 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14456 .addReg(Tmp, 0, X86::sub_8bit);
14459 // Use pseudo select and lower them.
14460 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14461 "Invalid atomic-load-op transformation!");
14462 unsigned SelOpc = getPseudoCMOVOpc(VT);
14463 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14464 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14465 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14466 .addReg(SrcReg).addReg(t4)
14468 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14469 // Replace the original PHI node as mainMBB is changed after CMOV
14471 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14472 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14473 Phi->eraseFromParent();
14479 // Copy PhyReg back from virtual register.
14480 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14483 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14484 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14485 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14487 NewMO.setIsKill(false);
14488 MIB.addOperand(NewMO);
14491 MIB.setMemRefs(MMOBegin, MMOEnd);
14493 // Copy PhyReg back to virtual register.
14494 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14497 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14499 mainMBB->addSuccessor(origMainMBB);
14500 mainMBB->addSuccessor(sinkMBB);
14503 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14504 TII->get(TargetOpcode::COPY), DstReg)
14507 MI->eraseFromParent();
14511 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14512 // instructions. They will be translated into a spin-loop or compare-exchange
14516 // dst = atomic-fetch-op MI.addr, MI.val
14522 // t1L = LOAD [MI.addr + 0]
14523 // t1H = LOAD [MI.addr + 4]
14525 // t4L = phi(t1L, t3L / loop)
14526 // t4H = phi(t1H, t3H / loop)
14527 // t2L = OP MI.val.lo, t4L
14528 // t2H = OP MI.val.hi, t4H
14533 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14541 MachineBasicBlock *
14542 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14543 MachineBasicBlock *MBB) const {
14544 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14545 DebugLoc DL = MI->getDebugLoc();
14547 MachineFunction *MF = MBB->getParent();
14548 MachineRegisterInfo &MRI = MF->getRegInfo();
14550 const BasicBlock *BB = MBB->getBasicBlock();
14551 MachineFunction::iterator I = MBB;
14554 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14555 "Unexpected number of operands");
14557 assert(MI->hasOneMemOperand() &&
14558 "Expected atomic-load-op32 to have one memoperand");
14560 // Memory Reference
14561 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14562 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14564 unsigned DstLoReg, DstHiReg;
14565 unsigned SrcLoReg, SrcHiReg;
14566 unsigned MemOpndSlot;
14568 unsigned CurOp = 0;
14570 DstLoReg = MI->getOperand(CurOp++).getReg();
14571 DstHiReg = MI->getOperand(CurOp++).getReg();
14572 MemOpndSlot = CurOp;
14573 CurOp += X86::AddrNumOperands;
14574 SrcLoReg = MI->getOperand(CurOp++).getReg();
14575 SrcHiReg = MI->getOperand(CurOp++).getReg();
14577 const TargetRegisterClass *RC = &X86::GR32RegClass;
14578 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14580 unsigned t1L = MRI.createVirtualRegister(RC);
14581 unsigned t1H = MRI.createVirtualRegister(RC);
14582 unsigned t2L = MRI.createVirtualRegister(RC);
14583 unsigned t2H = MRI.createVirtualRegister(RC);
14584 unsigned t3L = MRI.createVirtualRegister(RC);
14585 unsigned t3H = MRI.createVirtualRegister(RC);
14586 unsigned t4L = MRI.createVirtualRegister(RC);
14587 unsigned t4H = MRI.createVirtualRegister(RC);
14589 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14590 unsigned LOADOpc = X86::MOV32rm;
14592 // For the atomic load-arith operator, we generate
14595 // t1L = LOAD [MI.addr + 0]
14596 // t1H = LOAD [MI.addr + 4]
14598 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14599 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14600 // t2L = OP MI.val.lo, t4L
14601 // t2H = OP MI.val.hi, t4H
14604 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14612 MachineBasicBlock *thisMBB = MBB;
14613 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14614 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14615 MF->insert(I, mainMBB);
14616 MF->insert(I, sinkMBB);
14618 MachineInstrBuilder MIB;
14620 // Transfer the remainder of BB and its successor edges to sinkMBB.
14621 sinkMBB->splice(sinkMBB->begin(), MBB,
14622 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14623 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14627 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14628 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14629 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14631 NewMO.setIsKill(false);
14632 MIB.addOperand(NewMO);
14634 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14635 unsigned flags = (*MMOI)->getFlags();
14636 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14637 MachineMemOperand *MMO =
14638 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14639 (*MMOI)->getSize(),
14640 (*MMOI)->getBaseAlignment(),
14641 (*MMOI)->getTBAAInfo(),
14642 (*MMOI)->getRanges());
14643 MIB.addMemOperand(MMO);
14645 MachineInstr *LowMI = MIB;
14648 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14649 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14650 if (i == X86::AddrDisp) {
14651 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14653 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14655 NewMO.setIsKill(false);
14656 MIB.addOperand(NewMO);
14659 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14661 thisMBB->addSuccessor(mainMBB);
14664 MachineBasicBlock *origMainMBB = mainMBB;
14667 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14668 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14669 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14670 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14672 unsigned Opc = MI->getOpcode();
14675 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14676 case X86::ATOMAND6432:
14677 case X86::ATOMOR6432:
14678 case X86::ATOMXOR6432:
14679 case X86::ATOMADD6432:
14680 case X86::ATOMSUB6432: {
14682 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14683 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14685 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14689 case X86::ATOMNAND6432: {
14690 unsigned HiOpc, NOTOpc;
14691 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14692 unsigned TmpL = MRI.createVirtualRegister(RC);
14693 unsigned TmpH = MRI.createVirtualRegister(RC);
14694 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14696 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14698 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14699 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14702 case X86::ATOMMAX6432:
14703 case X86::ATOMMIN6432:
14704 case X86::ATOMUMAX6432:
14705 case X86::ATOMUMIN6432: {
14707 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14708 unsigned cL = MRI.createVirtualRegister(RC8);
14709 unsigned cH = MRI.createVirtualRegister(RC8);
14710 unsigned cL32 = MRI.createVirtualRegister(RC);
14711 unsigned cH32 = MRI.createVirtualRegister(RC);
14712 unsigned cc = MRI.createVirtualRegister(RC);
14713 // cl := cmp src_lo, lo
14714 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14715 .addReg(SrcLoReg).addReg(t4L);
14716 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14717 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14718 // ch := cmp src_hi, hi
14719 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14720 .addReg(SrcHiReg).addReg(t4H);
14721 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14722 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14723 // cc := if (src_hi == hi) ? cl : ch;
14724 if (Subtarget->hasCMov()) {
14725 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14726 .addReg(cH32).addReg(cL32);
14728 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14729 .addReg(cH32).addReg(cL32)
14730 .addImm(X86::COND_E);
14731 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14733 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14734 if (Subtarget->hasCMov()) {
14735 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14736 .addReg(SrcLoReg).addReg(t4L);
14737 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14738 .addReg(SrcHiReg).addReg(t4H);
14740 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14741 .addReg(SrcLoReg).addReg(t4L)
14742 .addImm(X86::COND_NE);
14743 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14744 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14745 // 2nd CMOV lowering.
14746 mainMBB->addLiveIn(X86::EFLAGS);
14747 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14748 .addReg(SrcHiReg).addReg(t4H)
14749 .addImm(X86::COND_NE);
14750 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14751 // Replace the original PHI node as mainMBB is changed after CMOV
14753 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14754 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14755 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14756 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14757 PhiL->eraseFromParent();
14758 PhiH->eraseFromParent();
14762 case X86::ATOMSWAP6432: {
14764 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14765 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14766 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14771 // Copy EDX:EAX back from HiReg:LoReg
14772 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14773 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14774 // Copy ECX:EBX from t1H:t1L
14775 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14776 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14778 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14779 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14780 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14782 NewMO.setIsKill(false);
14783 MIB.addOperand(NewMO);
14785 MIB.setMemRefs(MMOBegin, MMOEnd);
14787 // Copy EDX:EAX back to t3H:t3L
14788 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14789 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14791 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14793 mainMBB->addSuccessor(origMainMBB);
14794 mainMBB->addSuccessor(sinkMBB);
14797 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14798 TII->get(TargetOpcode::COPY), DstLoReg)
14800 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14801 TII->get(TargetOpcode::COPY), DstHiReg)
14804 MI->eraseFromParent();
14808 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14809 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14810 // in the .td file.
14811 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14812 const TargetInstrInfo *TII) {
14814 switch (MI->getOpcode()) {
14815 default: llvm_unreachable("illegal opcode!");
14816 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14817 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14818 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14819 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14820 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14821 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14822 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14823 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14826 DebugLoc dl = MI->getDebugLoc();
14827 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14829 unsigned NumArgs = MI->getNumOperands();
14830 for (unsigned i = 1; i < NumArgs; ++i) {
14831 MachineOperand &Op = MI->getOperand(i);
14832 if (!(Op.isReg() && Op.isImplicit()))
14833 MIB.addOperand(Op);
14835 if (MI->hasOneMemOperand())
14836 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14838 BuildMI(*BB, MI, dl,
14839 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14840 .addReg(X86::XMM0);
14842 MI->eraseFromParent();
14846 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14847 // defs in an instruction pattern
14848 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14849 const TargetInstrInfo *TII) {
14851 switch (MI->getOpcode()) {
14852 default: llvm_unreachable("illegal opcode!");
14853 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14854 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14855 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14856 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14857 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14858 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14859 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14860 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14863 DebugLoc dl = MI->getDebugLoc();
14864 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14866 unsigned NumArgs = MI->getNumOperands(); // remove the results
14867 for (unsigned i = 1; i < NumArgs; ++i) {
14868 MachineOperand &Op = MI->getOperand(i);
14869 if (!(Op.isReg() && Op.isImplicit()))
14870 MIB.addOperand(Op);
14872 if (MI->hasOneMemOperand())
14873 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14875 BuildMI(*BB, MI, dl,
14876 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14879 MI->eraseFromParent();
14883 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14884 const TargetInstrInfo *TII,
14885 const X86Subtarget* Subtarget) {
14886 DebugLoc dl = MI->getDebugLoc();
14888 // Address into RAX/EAX, other two args into ECX, EDX.
14889 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14890 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14891 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14892 for (int i = 0; i < X86::AddrNumOperands; ++i)
14893 MIB.addOperand(MI->getOperand(i));
14895 unsigned ValOps = X86::AddrNumOperands;
14896 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14897 .addReg(MI->getOperand(ValOps).getReg());
14898 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14899 .addReg(MI->getOperand(ValOps+1).getReg());
14901 // The instruction doesn't actually take any operands though.
14902 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14904 MI->eraseFromParent(); // The pseudo is gone now.
14908 MachineBasicBlock *
14909 X86TargetLowering::EmitVAARG64WithCustomInserter(
14911 MachineBasicBlock *MBB) const {
14912 // Emit va_arg instruction on X86-64.
14914 // Operands to this pseudo-instruction:
14915 // 0 ) Output : destination address (reg)
14916 // 1-5) Input : va_list address (addr, i64mem)
14917 // 6 ) ArgSize : Size (in bytes) of vararg type
14918 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14919 // 8 ) Align : Alignment of type
14920 // 9 ) EFLAGS (implicit-def)
14922 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14923 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14925 unsigned DestReg = MI->getOperand(0).getReg();
14926 MachineOperand &Base = MI->getOperand(1);
14927 MachineOperand &Scale = MI->getOperand(2);
14928 MachineOperand &Index = MI->getOperand(3);
14929 MachineOperand &Disp = MI->getOperand(4);
14930 MachineOperand &Segment = MI->getOperand(5);
14931 unsigned ArgSize = MI->getOperand(6).getImm();
14932 unsigned ArgMode = MI->getOperand(7).getImm();
14933 unsigned Align = MI->getOperand(8).getImm();
14935 // Memory Reference
14936 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14937 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14938 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14940 // Machine Information
14941 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14942 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14943 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14944 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14945 DebugLoc DL = MI->getDebugLoc();
14947 // struct va_list {
14950 // i64 overflow_area (address)
14951 // i64 reg_save_area (address)
14953 // sizeof(va_list) = 24
14954 // alignment(va_list) = 8
14956 unsigned TotalNumIntRegs = 6;
14957 unsigned TotalNumXMMRegs = 8;
14958 bool UseGPOffset = (ArgMode == 1);
14959 bool UseFPOffset = (ArgMode == 2);
14960 unsigned MaxOffset = TotalNumIntRegs * 8 +
14961 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14963 /* Align ArgSize to a multiple of 8 */
14964 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14965 bool NeedsAlign = (Align > 8);
14967 MachineBasicBlock *thisMBB = MBB;
14968 MachineBasicBlock *overflowMBB;
14969 MachineBasicBlock *offsetMBB;
14970 MachineBasicBlock *endMBB;
14972 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14973 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14974 unsigned OffsetReg = 0;
14976 if (!UseGPOffset && !UseFPOffset) {
14977 // If we only pull from the overflow region, we don't create a branch.
14978 // We don't need to alter control flow.
14979 OffsetDestReg = 0; // unused
14980 OverflowDestReg = DestReg;
14983 overflowMBB = thisMBB;
14986 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14987 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14988 // If not, pull from overflow_area. (branch to overflowMBB)
14993 // offsetMBB overflowMBB
14998 // Registers for the PHI in endMBB
14999 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15000 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15002 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15003 MachineFunction *MF = MBB->getParent();
15004 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15005 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15006 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15008 MachineFunction::iterator MBBIter = MBB;
15011 // Insert the new basic blocks
15012 MF->insert(MBBIter, offsetMBB);
15013 MF->insert(MBBIter, overflowMBB);
15014 MF->insert(MBBIter, endMBB);
15016 // Transfer the remainder of MBB and its successor edges to endMBB.
15017 endMBB->splice(endMBB->begin(), thisMBB,
15018 llvm::next(MachineBasicBlock::iterator(MI)),
15020 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15022 // Make offsetMBB and overflowMBB successors of thisMBB
15023 thisMBB->addSuccessor(offsetMBB);
15024 thisMBB->addSuccessor(overflowMBB);
15026 // endMBB is a successor of both offsetMBB and overflowMBB
15027 offsetMBB->addSuccessor(endMBB);
15028 overflowMBB->addSuccessor(endMBB);
15030 // Load the offset value into a register
15031 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15032 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15036 .addDisp(Disp, UseFPOffset ? 4 : 0)
15037 .addOperand(Segment)
15038 .setMemRefs(MMOBegin, MMOEnd);
15040 // Check if there is enough room left to pull this argument.
15041 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15043 .addImm(MaxOffset + 8 - ArgSizeA8);
15045 // Branch to "overflowMBB" if offset >= max
15046 // Fall through to "offsetMBB" otherwise
15047 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15048 .addMBB(overflowMBB);
15051 // In offsetMBB, emit code to use the reg_save_area.
15053 assert(OffsetReg != 0);
15055 // Read the reg_save_area address.
15056 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15057 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15062 .addOperand(Segment)
15063 .setMemRefs(MMOBegin, MMOEnd);
15065 // Zero-extend the offset
15066 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15067 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15070 .addImm(X86::sub_32bit);
15072 // Add the offset to the reg_save_area to get the final address.
15073 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15074 .addReg(OffsetReg64)
15075 .addReg(RegSaveReg);
15077 // Compute the offset for the next argument
15078 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15079 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15081 .addImm(UseFPOffset ? 16 : 8);
15083 // Store it back into the va_list.
15084 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15088 .addDisp(Disp, UseFPOffset ? 4 : 0)
15089 .addOperand(Segment)
15090 .addReg(NextOffsetReg)
15091 .setMemRefs(MMOBegin, MMOEnd);
15094 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15099 // Emit code to use overflow area
15102 // Load the overflow_area address into a register.
15103 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15104 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15109 .addOperand(Segment)
15110 .setMemRefs(MMOBegin, MMOEnd);
15112 // If we need to align it, do so. Otherwise, just copy the address
15113 // to OverflowDestReg.
15115 // Align the overflow address
15116 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15117 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15119 // aligned_addr = (addr + (align-1)) & ~(align-1)
15120 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15121 .addReg(OverflowAddrReg)
15124 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15126 .addImm(~(uint64_t)(Align-1));
15128 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15129 .addReg(OverflowAddrReg);
15132 // Compute the next overflow address after this argument.
15133 // (the overflow address should be kept 8-byte aligned)
15134 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15135 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15136 .addReg(OverflowDestReg)
15137 .addImm(ArgSizeA8);
15139 // Store the new overflow address.
15140 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15145 .addOperand(Segment)
15146 .addReg(NextAddrReg)
15147 .setMemRefs(MMOBegin, MMOEnd);
15149 // If we branched, emit the PHI to the front of endMBB.
15151 BuildMI(*endMBB, endMBB->begin(), DL,
15152 TII->get(X86::PHI), DestReg)
15153 .addReg(OffsetDestReg).addMBB(offsetMBB)
15154 .addReg(OverflowDestReg).addMBB(overflowMBB);
15157 // Erase the pseudo instruction
15158 MI->eraseFromParent();
15163 MachineBasicBlock *
15164 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15166 MachineBasicBlock *MBB) const {
15167 // Emit code to save XMM registers to the stack. The ABI says that the
15168 // number of registers to save is given in %al, so it's theoretically
15169 // possible to do an indirect jump trick to avoid saving all of them,
15170 // however this code takes a simpler approach and just executes all
15171 // of the stores if %al is non-zero. It's less code, and it's probably
15172 // easier on the hardware branch predictor, and stores aren't all that
15173 // expensive anyway.
15175 // Create the new basic blocks. One block contains all the XMM stores,
15176 // and one block is the final destination regardless of whether any
15177 // stores were performed.
15178 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15179 MachineFunction *F = MBB->getParent();
15180 MachineFunction::iterator MBBIter = MBB;
15182 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15183 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15184 F->insert(MBBIter, XMMSaveMBB);
15185 F->insert(MBBIter, EndMBB);
15187 // Transfer the remainder of MBB and its successor edges to EndMBB.
15188 EndMBB->splice(EndMBB->begin(), MBB,
15189 llvm::next(MachineBasicBlock::iterator(MI)),
15191 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15193 // The original block will now fall through to the XMM save block.
15194 MBB->addSuccessor(XMMSaveMBB);
15195 // The XMMSaveMBB will fall through to the end block.
15196 XMMSaveMBB->addSuccessor(EndMBB);
15198 // Now add the instructions.
15199 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15200 DebugLoc DL = MI->getDebugLoc();
15202 unsigned CountReg = MI->getOperand(0).getReg();
15203 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15204 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15206 if (!Subtarget->isTargetWin64()) {
15207 // If %al is 0, branch around the XMM save block.
15208 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15209 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15210 MBB->addSuccessor(EndMBB);
15213 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15214 // In the XMM save block, save all the XMM argument registers.
15215 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15216 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15217 MachineMemOperand *MMO =
15218 F->getMachineMemOperand(
15219 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15220 MachineMemOperand::MOStore,
15221 /*Size=*/16, /*Align=*/16);
15222 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15223 .addFrameIndex(RegSaveFrameIndex)
15224 .addImm(/*Scale=*/1)
15225 .addReg(/*IndexReg=*/0)
15226 .addImm(/*Disp=*/Offset)
15227 .addReg(/*Segment=*/0)
15228 .addReg(MI->getOperand(i).getReg())
15229 .addMemOperand(MMO);
15232 MI->eraseFromParent(); // The pseudo instruction is gone now.
15237 // The EFLAGS operand of SelectItr might be missing a kill marker
15238 // because there were multiple uses of EFLAGS, and ISel didn't know
15239 // which to mark. Figure out whether SelectItr should have had a
15240 // kill marker, and set it if it should. Returns the correct kill
15242 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15243 MachineBasicBlock* BB,
15244 const TargetRegisterInfo* TRI) {
15245 // Scan forward through BB for a use/def of EFLAGS.
15246 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15247 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15248 const MachineInstr& mi = *miI;
15249 if (mi.readsRegister(X86::EFLAGS))
15251 if (mi.definesRegister(X86::EFLAGS))
15252 break; // Should have kill-flag - update below.
15255 // If we hit the end of the block, check whether EFLAGS is live into a
15257 if (miI == BB->end()) {
15258 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15259 sEnd = BB->succ_end();
15260 sItr != sEnd; ++sItr) {
15261 MachineBasicBlock* succ = *sItr;
15262 if (succ->isLiveIn(X86::EFLAGS))
15267 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15268 // out. SelectMI should have a kill flag on EFLAGS.
15269 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15273 MachineBasicBlock *
15274 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15275 MachineBasicBlock *BB) const {
15276 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15277 DebugLoc DL = MI->getDebugLoc();
15279 // To "insert" a SELECT_CC instruction, we actually have to insert the
15280 // diamond control-flow pattern. The incoming instruction knows the
15281 // destination vreg to set, the condition code register to branch on, the
15282 // true/false values to select between, and a branch opcode to use.
15283 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15284 MachineFunction::iterator It = BB;
15290 // cmpTY ccX, r1, r2
15292 // fallthrough --> copy0MBB
15293 MachineBasicBlock *thisMBB = BB;
15294 MachineFunction *F = BB->getParent();
15295 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15296 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15297 F->insert(It, copy0MBB);
15298 F->insert(It, sinkMBB);
15300 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15301 // live into the sink and copy blocks.
15302 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15303 if (!MI->killsRegister(X86::EFLAGS) &&
15304 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15305 copy0MBB->addLiveIn(X86::EFLAGS);
15306 sinkMBB->addLiveIn(X86::EFLAGS);
15309 // Transfer the remainder of BB and its successor edges to sinkMBB.
15310 sinkMBB->splice(sinkMBB->begin(), BB,
15311 llvm::next(MachineBasicBlock::iterator(MI)),
15313 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15315 // Add the true and fallthrough blocks as its successors.
15316 BB->addSuccessor(copy0MBB);
15317 BB->addSuccessor(sinkMBB);
15319 // Create the conditional branch instruction.
15321 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15322 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15325 // %FalseValue = ...
15326 // # fallthrough to sinkMBB
15327 copy0MBB->addSuccessor(sinkMBB);
15330 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15332 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15333 TII->get(X86::PHI), MI->getOperand(0).getReg())
15334 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15335 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15337 MI->eraseFromParent(); // The pseudo instruction is gone now.
15341 MachineBasicBlock *
15342 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15343 bool Is64Bit) const {
15344 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15345 DebugLoc DL = MI->getDebugLoc();
15346 MachineFunction *MF = BB->getParent();
15347 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15349 assert(getTargetMachine().Options.EnableSegmentedStacks);
15351 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15352 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15355 // ... [Till the alloca]
15356 // If stacklet is not large enough, jump to mallocMBB
15359 // Allocate by subtracting from RSP
15360 // Jump to continueMBB
15363 // Allocate by call to runtime
15367 // [rest of original BB]
15370 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15371 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15372 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15374 MachineRegisterInfo &MRI = MF->getRegInfo();
15375 const TargetRegisterClass *AddrRegClass =
15376 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15378 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15379 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15380 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15381 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15382 sizeVReg = MI->getOperand(1).getReg(),
15383 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15385 MachineFunction::iterator MBBIter = BB;
15388 MF->insert(MBBIter, bumpMBB);
15389 MF->insert(MBBIter, mallocMBB);
15390 MF->insert(MBBIter, continueMBB);
15392 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15393 (MachineBasicBlock::iterator(MI)), BB->end());
15394 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15396 // Add code to the main basic block to check if the stack limit has been hit,
15397 // and if so, jump to mallocMBB otherwise to bumpMBB.
15398 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15399 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15400 .addReg(tmpSPVReg).addReg(sizeVReg);
15401 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15402 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15403 .addReg(SPLimitVReg);
15404 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15406 // bumpMBB simply decreases the stack pointer, since we know the current
15407 // stacklet has enough space.
15408 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15409 .addReg(SPLimitVReg);
15410 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15411 .addReg(SPLimitVReg);
15412 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15414 // Calls into a routine in libgcc to allocate more space from the heap.
15415 const uint32_t *RegMask =
15416 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15418 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15420 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15421 .addExternalSymbol("__morestack_allocate_stack_space")
15422 .addRegMask(RegMask)
15423 .addReg(X86::RDI, RegState::Implicit)
15424 .addReg(X86::RAX, RegState::ImplicitDefine);
15426 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15428 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15429 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15430 .addExternalSymbol("__morestack_allocate_stack_space")
15431 .addRegMask(RegMask)
15432 .addReg(X86::EAX, RegState::ImplicitDefine);
15436 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15439 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15440 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15441 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15443 // Set up the CFG correctly.
15444 BB->addSuccessor(bumpMBB);
15445 BB->addSuccessor(mallocMBB);
15446 mallocMBB->addSuccessor(continueMBB);
15447 bumpMBB->addSuccessor(continueMBB);
15449 // Take care of the PHI nodes.
15450 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15451 MI->getOperand(0).getReg())
15452 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15453 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15455 // Delete the original pseudo instruction.
15456 MI->eraseFromParent();
15459 return continueMBB;
15462 MachineBasicBlock *
15463 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15464 MachineBasicBlock *BB) const {
15465 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15466 DebugLoc DL = MI->getDebugLoc();
15468 assert(!Subtarget->isTargetEnvMacho());
15470 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15471 // non-trivial part is impdef of ESP.
15473 if (Subtarget->isTargetWin64()) {
15474 if (Subtarget->isTargetCygMing()) {
15475 // ___chkstk(Mingw64):
15476 // Clobbers R10, R11, RAX and EFLAGS.
15478 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15479 .addExternalSymbol("___chkstk")
15480 .addReg(X86::RAX, RegState::Implicit)
15481 .addReg(X86::RSP, RegState::Implicit)
15482 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15483 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15484 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15486 // __chkstk(MSVCRT): does not update stack pointer.
15487 // Clobbers R10, R11 and EFLAGS.
15488 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15489 .addExternalSymbol("__chkstk")
15490 .addReg(X86::RAX, RegState::Implicit)
15491 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15492 // RAX has the offset to be subtracted from RSP.
15493 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15498 const char *StackProbeSymbol =
15499 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15501 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15502 .addExternalSymbol(StackProbeSymbol)
15503 .addReg(X86::EAX, RegState::Implicit)
15504 .addReg(X86::ESP, RegState::Implicit)
15505 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15506 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15507 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15510 MI->eraseFromParent(); // The pseudo instruction is gone now.
15514 MachineBasicBlock *
15515 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15516 MachineBasicBlock *BB) const {
15517 // This is pretty easy. We're taking the value that we received from
15518 // our load from the relocation, sticking it in either RDI (x86-64)
15519 // or EAX and doing an indirect call. The return value will then
15520 // be in the normal return register.
15521 const X86InstrInfo *TII
15522 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15523 DebugLoc DL = MI->getDebugLoc();
15524 MachineFunction *F = BB->getParent();
15526 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15527 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15529 // Get a register mask for the lowered call.
15530 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15531 // proper register mask.
15532 const uint32_t *RegMask =
15533 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15534 if (Subtarget->is64Bit()) {
15535 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15536 TII->get(X86::MOV64rm), X86::RDI)
15538 .addImm(0).addReg(0)
15539 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15540 MI->getOperand(3).getTargetFlags())
15542 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15543 addDirectMem(MIB, X86::RDI);
15544 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15545 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15546 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15547 TII->get(X86::MOV32rm), X86::EAX)
15549 .addImm(0).addReg(0)
15550 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15551 MI->getOperand(3).getTargetFlags())
15553 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15554 addDirectMem(MIB, X86::EAX);
15555 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15557 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15558 TII->get(X86::MOV32rm), X86::EAX)
15559 .addReg(TII->getGlobalBaseReg(F))
15560 .addImm(0).addReg(0)
15561 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15562 MI->getOperand(3).getTargetFlags())
15564 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15565 addDirectMem(MIB, X86::EAX);
15566 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15569 MI->eraseFromParent(); // The pseudo instruction is gone now.
15573 MachineBasicBlock *
15574 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15575 MachineBasicBlock *MBB) const {
15576 DebugLoc DL = MI->getDebugLoc();
15577 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15579 MachineFunction *MF = MBB->getParent();
15580 MachineRegisterInfo &MRI = MF->getRegInfo();
15582 const BasicBlock *BB = MBB->getBasicBlock();
15583 MachineFunction::iterator I = MBB;
15586 // Memory Reference
15587 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15588 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15591 unsigned MemOpndSlot = 0;
15593 unsigned CurOp = 0;
15595 DstReg = MI->getOperand(CurOp++).getReg();
15596 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15597 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15598 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15599 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15601 MemOpndSlot = CurOp;
15603 MVT PVT = getPointerTy();
15604 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15605 "Invalid Pointer Size!");
15607 // For v = setjmp(buf), we generate
15610 // buf[LabelOffset] = restoreMBB
15611 // SjLjSetup restoreMBB
15617 // v = phi(main, restore)
15622 MachineBasicBlock *thisMBB = MBB;
15623 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15624 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15625 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15626 MF->insert(I, mainMBB);
15627 MF->insert(I, sinkMBB);
15628 MF->push_back(restoreMBB);
15630 MachineInstrBuilder MIB;
15632 // Transfer the remainder of BB and its successor edges to sinkMBB.
15633 sinkMBB->splice(sinkMBB->begin(), MBB,
15634 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15635 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15638 unsigned PtrStoreOpc = 0;
15639 unsigned LabelReg = 0;
15640 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15641 Reloc::Model RM = getTargetMachine().getRelocationModel();
15642 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15643 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15645 // Prepare IP either in reg or imm.
15646 if (!UseImmLabel) {
15647 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15648 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15649 LabelReg = MRI.createVirtualRegister(PtrRC);
15650 if (Subtarget->is64Bit()) {
15651 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15655 .addMBB(restoreMBB)
15658 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15659 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15660 .addReg(XII->getGlobalBaseReg(MF))
15663 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15667 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15669 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15670 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15671 if (i == X86::AddrDisp)
15672 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15674 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15677 MIB.addReg(LabelReg);
15679 MIB.addMBB(restoreMBB);
15680 MIB.setMemRefs(MMOBegin, MMOEnd);
15682 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15683 .addMBB(restoreMBB);
15685 const X86RegisterInfo *RegInfo =
15686 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15687 MIB.addRegMask(RegInfo->getNoPreservedMask());
15688 thisMBB->addSuccessor(mainMBB);
15689 thisMBB->addSuccessor(restoreMBB);
15693 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15694 mainMBB->addSuccessor(sinkMBB);
15697 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15698 TII->get(X86::PHI), DstReg)
15699 .addReg(mainDstReg).addMBB(mainMBB)
15700 .addReg(restoreDstReg).addMBB(restoreMBB);
15703 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15704 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15705 restoreMBB->addSuccessor(sinkMBB);
15707 MI->eraseFromParent();
15711 MachineBasicBlock *
15712 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15713 MachineBasicBlock *MBB) const {
15714 DebugLoc DL = MI->getDebugLoc();
15715 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15717 MachineFunction *MF = MBB->getParent();
15718 MachineRegisterInfo &MRI = MF->getRegInfo();
15720 // Memory Reference
15721 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15722 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15724 MVT PVT = getPointerTy();
15725 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15726 "Invalid Pointer Size!");
15728 const TargetRegisterClass *RC =
15729 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15730 unsigned Tmp = MRI.createVirtualRegister(RC);
15731 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15732 const X86RegisterInfo *RegInfo =
15733 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15734 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15735 unsigned SP = RegInfo->getStackRegister();
15737 MachineInstrBuilder MIB;
15739 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15740 const int64_t SPOffset = 2 * PVT.getStoreSize();
15742 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15743 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15746 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15747 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15748 MIB.addOperand(MI->getOperand(i));
15749 MIB.setMemRefs(MMOBegin, MMOEnd);
15751 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15752 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15753 if (i == X86::AddrDisp)
15754 MIB.addDisp(MI->getOperand(i), LabelOffset);
15756 MIB.addOperand(MI->getOperand(i));
15758 MIB.setMemRefs(MMOBegin, MMOEnd);
15760 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15761 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15762 if (i == X86::AddrDisp)
15763 MIB.addDisp(MI->getOperand(i), SPOffset);
15765 MIB.addOperand(MI->getOperand(i));
15767 MIB.setMemRefs(MMOBegin, MMOEnd);
15769 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15771 MI->eraseFromParent();
15775 MachineBasicBlock *
15776 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15777 MachineBasicBlock *BB) const {
15778 switch (MI->getOpcode()) {
15779 default: llvm_unreachable("Unexpected instr type to insert");
15780 case X86::TAILJMPd64:
15781 case X86::TAILJMPr64:
15782 case X86::TAILJMPm64:
15783 llvm_unreachable("TAILJMP64 would not be touched here.");
15784 case X86::TCRETURNdi64:
15785 case X86::TCRETURNri64:
15786 case X86::TCRETURNmi64:
15788 case X86::WIN_ALLOCA:
15789 return EmitLoweredWinAlloca(MI, BB);
15790 case X86::SEG_ALLOCA_32:
15791 return EmitLoweredSegAlloca(MI, BB, false);
15792 case X86::SEG_ALLOCA_64:
15793 return EmitLoweredSegAlloca(MI, BB, true);
15794 case X86::TLSCall_32:
15795 case X86::TLSCall_64:
15796 return EmitLoweredTLSCall(MI, BB);
15797 case X86::CMOV_GR8:
15798 case X86::CMOV_FR32:
15799 case X86::CMOV_FR64:
15800 case X86::CMOV_V4F32:
15801 case X86::CMOV_V2F64:
15802 case X86::CMOV_V2I64:
15803 case X86::CMOV_V8F32:
15804 case X86::CMOV_V4F64:
15805 case X86::CMOV_V4I64:
15806 case X86::CMOV_V16F32:
15807 case X86::CMOV_V8F64:
15808 case X86::CMOV_V8I64:
15809 case X86::CMOV_GR16:
15810 case X86::CMOV_GR32:
15811 case X86::CMOV_RFP32:
15812 case X86::CMOV_RFP64:
15813 case X86::CMOV_RFP80:
15814 return EmitLoweredSelect(MI, BB);
15816 case X86::FP32_TO_INT16_IN_MEM:
15817 case X86::FP32_TO_INT32_IN_MEM:
15818 case X86::FP32_TO_INT64_IN_MEM:
15819 case X86::FP64_TO_INT16_IN_MEM:
15820 case X86::FP64_TO_INT32_IN_MEM:
15821 case X86::FP64_TO_INT64_IN_MEM:
15822 case X86::FP80_TO_INT16_IN_MEM:
15823 case X86::FP80_TO_INT32_IN_MEM:
15824 case X86::FP80_TO_INT64_IN_MEM: {
15825 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15826 DebugLoc DL = MI->getDebugLoc();
15828 // Change the floating point control register to use "round towards zero"
15829 // mode when truncating to an integer value.
15830 MachineFunction *F = BB->getParent();
15831 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15832 addFrameReference(BuildMI(*BB, MI, DL,
15833 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15835 // Load the old value of the high byte of the control word...
15837 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15838 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15841 // Set the high part to be round to zero...
15842 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15845 // Reload the modified control word now...
15846 addFrameReference(BuildMI(*BB, MI, DL,
15847 TII->get(X86::FLDCW16m)), CWFrameIdx);
15849 // Restore the memory image of control word to original value
15850 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15853 // Get the X86 opcode to use.
15855 switch (MI->getOpcode()) {
15856 default: llvm_unreachable("illegal opcode!");
15857 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15858 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15859 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15860 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15861 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15862 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15863 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15864 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15865 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15869 MachineOperand &Op = MI->getOperand(0);
15871 AM.BaseType = X86AddressMode::RegBase;
15872 AM.Base.Reg = Op.getReg();
15874 AM.BaseType = X86AddressMode::FrameIndexBase;
15875 AM.Base.FrameIndex = Op.getIndex();
15877 Op = MI->getOperand(1);
15879 AM.Scale = Op.getImm();
15880 Op = MI->getOperand(2);
15882 AM.IndexReg = Op.getImm();
15883 Op = MI->getOperand(3);
15884 if (Op.isGlobal()) {
15885 AM.GV = Op.getGlobal();
15887 AM.Disp = Op.getImm();
15889 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15890 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15892 // Reload the original control word now.
15893 addFrameReference(BuildMI(*BB, MI, DL,
15894 TII->get(X86::FLDCW16m)), CWFrameIdx);
15896 MI->eraseFromParent(); // The pseudo instruction is gone now.
15899 // String/text processing lowering.
15900 case X86::PCMPISTRM128REG:
15901 case X86::VPCMPISTRM128REG:
15902 case X86::PCMPISTRM128MEM:
15903 case X86::VPCMPISTRM128MEM:
15904 case X86::PCMPESTRM128REG:
15905 case X86::VPCMPESTRM128REG:
15906 case X86::PCMPESTRM128MEM:
15907 case X86::VPCMPESTRM128MEM:
15908 assert(Subtarget->hasSSE42() &&
15909 "Target must have SSE4.2 or AVX features enabled");
15910 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15912 // String/text processing lowering.
15913 case X86::PCMPISTRIREG:
15914 case X86::VPCMPISTRIREG:
15915 case X86::PCMPISTRIMEM:
15916 case X86::VPCMPISTRIMEM:
15917 case X86::PCMPESTRIREG:
15918 case X86::VPCMPESTRIREG:
15919 case X86::PCMPESTRIMEM:
15920 case X86::VPCMPESTRIMEM:
15921 assert(Subtarget->hasSSE42() &&
15922 "Target must have SSE4.2 or AVX features enabled");
15923 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15925 // Thread synchronization.
15927 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15931 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15933 // Atomic Lowering.
15934 case X86::ATOMAND8:
15935 case X86::ATOMAND16:
15936 case X86::ATOMAND32:
15937 case X86::ATOMAND64:
15940 case X86::ATOMOR16:
15941 case X86::ATOMOR32:
15942 case X86::ATOMOR64:
15944 case X86::ATOMXOR16:
15945 case X86::ATOMXOR8:
15946 case X86::ATOMXOR32:
15947 case X86::ATOMXOR64:
15949 case X86::ATOMNAND8:
15950 case X86::ATOMNAND16:
15951 case X86::ATOMNAND32:
15952 case X86::ATOMNAND64:
15954 case X86::ATOMMAX8:
15955 case X86::ATOMMAX16:
15956 case X86::ATOMMAX32:
15957 case X86::ATOMMAX64:
15959 case X86::ATOMMIN8:
15960 case X86::ATOMMIN16:
15961 case X86::ATOMMIN32:
15962 case X86::ATOMMIN64:
15964 case X86::ATOMUMAX8:
15965 case X86::ATOMUMAX16:
15966 case X86::ATOMUMAX32:
15967 case X86::ATOMUMAX64:
15969 case X86::ATOMUMIN8:
15970 case X86::ATOMUMIN16:
15971 case X86::ATOMUMIN32:
15972 case X86::ATOMUMIN64:
15973 return EmitAtomicLoadArith(MI, BB);
15975 // This group does 64-bit operations on a 32-bit host.
15976 case X86::ATOMAND6432:
15977 case X86::ATOMOR6432:
15978 case X86::ATOMXOR6432:
15979 case X86::ATOMNAND6432:
15980 case X86::ATOMADD6432:
15981 case X86::ATOMSUB6432:
15982 case X86::ATOMMAX6432:
15983 case X86::ATOMMIN6432:
15984 case X86::ATOMUMAX6432:
15985 case X86::ATOMUMIN6432:
15986 case X86::ATOMSWAP6432:
15987 return EmitAtomicLoadArith6432(MI, BB);
15989 case X86::VASTART_SAVE_XMM_REGS:
15990 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15992 case X86::VAARG_64:
15993 return EmitVAARG64WithCustomInserter(MI, BB);
15995 case X86::EH_SjLj_SetJmp32:
15996 case X86::EH_SjLj_SetJmp64:
15997 return emitEHSjLjSetJmp(MI, BB);
15999 case X86::EH_SjLj_LongJmp32:
16000 case X86::EH_SjLj_LongJmp64:
16001 return emitEHSjLjLongJmp(MI, BB);
16005 //===----------------------------------------------------------------------===//
16006 // X86 Optimization Hooks
16007 //===----------------------------------------------------------------------===//
16009 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16012 const SelectionDAG &DAG,
16013 unsigned Depth) const {
16014 unsigned BitWidth = KnownZero.getBitWidth();
16015 unsigned Opc = Op.getOpcode();
16016 assert((Opc >= ISD::BUILTIN_OP_END ||
16017 Opc == ISD::INTRINSIC_WO_CHAIN ||
16018 Opc == ISD::INTRINSIC_W_CHAIN ||
16019 Opc == ISD::INTRINSIC_VOID) &&
16020 "Should use MaskedValueIsZero if you don't know whether Op"
16021 " is a target node!");
16023 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16037 // These nodes' second result is a boolean.
16038 if (Op.getResNo() == 0)
16041 case X86ISD::SETCC:
16042 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16044 case ISD::INTRINSIC_WO_CHAIN: {
16045 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16046 unsigned NumLoBits = 0;
16049 case Intrinsic::x86_sse_movmsk_ps:
16050 case Intrinsic::x86_avx_movmsk_ps_256:
16051 case Intrinsic::x86_sse2_movmsk_pd:
16052 case Intrinsic::x86_avx_movmsk_pd_256:
16053 case Intrinsic::x86_mmx_pmovmskb:
16054 case Intrinsic::x86_sse2_pmovmskb_128:
16055 case Intrinsic::x86_avx2_pmovmskb: {
16056 // High bits of movmskp{s|d}, pmovmskb are known zero.
16058 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16059 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16060 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16061 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16062 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16063 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16064 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16065 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16067 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16076 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16077 unsigned Depth) const {
16078 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16079 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16080 return Op.getValueType().getScalarType().getSizeInBits();
16086 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16087 /// node is a GlobalAddress + offset.
16088 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16089 const GlobalValue* &GA,
16090 int64_t &Offset) const {
16091 if (N->getOpcode() == X86ISD::Wrapper) {
16092 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16093 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16094 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16098 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16101 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16102 /// same as extracting the high 128-bit part of 256-bit vector and then
16103 /// inserting the result into the low part of a new 256-bit vector
16104 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16105 EVT VT = SVOp->getValueType(0);
16106 unsigned NumElems = VT.getVectorNumElements();
16108 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16109 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16110 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16111 SVOp->getMaskElt(j) >= 0)
16117 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16118 /// same as extracting the low 128-bit part of 256-bit vector and then
16119 /// inserting the result into the high part of a new 256-bit vector
16120 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16121 EVT VT = SVOp->getValueType(0);
16122 unsigned NumElems = VT.getVectorNumElements();
16124 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16125 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16126 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16127 SVOp->getMaskElt(j) >= 0)
16133 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16134 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16135 TargetLowering::DAGCombinerInfo &DCI,
16136 const X86Subtarget* Subtarget) {
16138 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16139 SDValue V1 = SVOp->getOperand(0);
16140 SDValue V2 = SVOp->getOperand(1);
16141 EVT VT = SVOp->getValueType(0);
16142 unsigned NumElems = VT.getVectorNumElements();
16144 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16145 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16149 // V UNDEF BUILD_VECTOR UNDEF
16151 // CONCAT_VECTOR CONCAT_VECTOR
16154 // RESULT: V + zero extended
16156 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16157 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16158 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16161 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16164 // To match the shuffle mask, the first half of the mask should
16165 // be exactly the first vector, and all the rest a splat with the
16166 // first element of the second one.
16167 for (unsigned i = 0; i != NumElems/2; ++i)
16168 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16169 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16172 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16173 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16174 if (Ld->hasNUsesOfValue(1, 0)) {
16175 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16176 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16178 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16179 array_lengthof(Ops),
16181 Ld->getPointerInfo(),
16182 Ld->getAlignment(),
16183 false/*isVolatile*/, true/*ReadMem*/,
16184 false/*WriteMem*/);
16186 // Make sure the newly-created LOAD is in the same position as Ld in
16187 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16188 // and update uses of Ld's output chain to use the TokenFactor.
16189 if (Ld->hasAnyUseOfValue(1)) {
16190 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16191 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16192 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16193 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16194 SDValue(ResNode.getNode(), 1));
16197 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16201 // Emit a zeroed vector and insert the desired subvector on its
16203 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16204 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16205 return DCI.CombineTo(N, InsV);
16208 //===--------------------------------------------------------------------===//
16209 // Combine some shuffles into subvector extracts and inserts:
16212 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16213 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16214 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16215 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16216 return DCI.CombineTo(N, InsV);
16219 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16220 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16221 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16222 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16223 return DCI.CombineTo(N, InsV);
16229 /// PerformShuffleCombine - Performs several different shuffle combines.
16230 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16231 TargetLowering::DAGCombinerInfo &DCI,
16232 const X86Subtarget *Subtarget) {
16234 EVT VT = N->getValueType(0);
16236 // Don't create instructions with illegal types after legalize types has run.
16237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16238 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16241 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16242 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16243 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16244 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16246 // Only handle 128 wide vector from here on.
16247 if (!VT.is128BitVector())
16250 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16251 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16252 // consecutive, non-overlapping, and in the right order.
16253 SmallVector<SDValue, 16> Elts;
16254 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16255 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16257 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16260 /// PerformTruncateCombine - Converts truncate operation to
16261 /// a sequence of vector shuffle operations.
16262 /// It is possible when we truncate 256-bit vector to 128-bit vector
16263 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16264 TargetLowering::DAGCombinerInfo &DCI,
16265 const X86Subtarget *Subtarget) {
16269 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16270 /// specific shuffle of a load can be folded into a single element load.
16271 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16272 /// shuffles have been customed lowered so we need to handle those here.
16273 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16274 TargetLowering::DAGCombinerInfo &DCI) {
16275 if (DCI.isBeforeLegalizeOps())
16278 SDValue InVec = N->getOperand(0);
16279 SDValue EltNo = N->getOperand(1);
16281 if (!isa<ConstantSDNode>(EltNo))
16284 EVT VT = InVec.getValueType();
16286 bool HasShuffleIntoBitcast = false;
16287 if (InVec.getOpcode() == ISD::BITCAST) {
16288 // Don't duplicate a load with other uses.
16289 if (!InVec.hasOneUse())
16291 EVT BCVT = InVec.getOperand(0).getValueType();
16292 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16294 InVec = InVec.getOperand(0);
16295 HasShuffleIntoBitcast = true;
16298 if (!isTargetShuffle(InVec.getOpcode()))
16301 // Don't duplicate a load with other uses.
16302 if (!InVec.hasOneUse())
16305 SmallVector<int, 16> ShuffleMask;
16307 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16311 // Select the input vector, guarding against out of range extract vector.
16312 unsigned NumElems = VT.getVectorNumElements();
16313 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16314 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16315 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16316 : InVec.getOperand(1);
16318 // If inputs to shuffle are the same for both ops, then allow 2 uses
16319 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16321 if (LdNode.getOpcode() == ISD::BITCAST) {
16322 // Don't duplicate a load with other uses.
16323 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16326 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16327 LdNode = LdNode.getOperand(0);
16330 if (!ISD::isNormalLoad(LdNode.getNode()))
16333 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16335 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16338 if (HasShuffleIntoBitcast) {
16339 // If there's a bitcast before the shuffle, check if the load type and
16340 // alignment is valid.
16341 unsigned Align = LN0->getAlignment();
16342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16343 unsigned NewAlign = TLI.getDataLayout()->
16344 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16346 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16350 // All checks match so transform back to vector_shuffle so that DAG combiner
16351 // can finish the job
16354 // Create shuffle node taking into account the case that its a unary shuffle
16355 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16356 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16357 InVec.getOperand(0), Shuffle,
16359 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16360 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16364 /// Extract one bit from mask vector, like v16i1 or v8i1.
16365 /// AVX-512 feature.
16366 static SDValue ExtractBitFromMaskVector(SDNode *N, SelectionDAG &DAG) {
16367 SDValue Vec = N->getOperand(0);
16369 MVT VecVT = Vec.getSimpleValueType();
16370 SDValue Idx = N->getOperand(1);
16371 MVT EltVT = N->getSimpleValueType(0);
16373 assert((VecVT.getVectorElementType() == MVT::i1 && EltVT == MVT::i8) ||
16374 "Unexpected operands in ExtractBitFromMaskVector");
16377 if (!isa<ConstantSDNode>(Idx)) {
16378 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
16379 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
16380 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16381 ExtVT.getVectorElementType(), Ext);
16382 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
16385 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
16387 MVT ScalarVT = MVT::getIntegerVT(VecVT.getSizeInBits());
16388 unsigned MaxShift = VecVT.getSizeInBits() - 1;
16389 Vec = DAG.getNode(ISD::BITCAST, dl, ScalarVT, Vec);
16390 Vec = DAG.getNode(ISD::SHL, dl, ScalarVT, Vec,
16391 DAG.getConstant(MaxShift - IdxVal, ScalarVT));
16392 Vec = DAG.getNode(ISD::SRL, dl, ScalarVT, Vec,
16393 DAG.getConstant(MaxShift, ScalarVT));
16395 if (VecVT == MVT::v16i1) {
16396 Vec = DAG.getNode(ISD::BITCAST, dl, MVT::i16, Vec);
16397 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Vec);
16399 return DAG.getNode(ISD::BITCAST, dl, MVT::i8, Vec);
16402 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16403 /// generation and convert it from being a bunch of shuffles and extracts
16404 /// to a simple store and scalar loads to extract the elements.
16405 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16406 TargetLowering::DAGCombinerInfo &DCI) {
16407 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16408 if (NewOp.getNode())
16411 SDValue InputVector = N->getOperand(0);
16413 if (InputVector.getValueType().getVectorElementType() == MVT::i1 &&
16414 !DCI.isBeforeLegalize())
16415 return ExtractBitFromMaskVector(N, DAG);
16417 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16418 // from mmx to v2i32 has a single usage.
16419 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16420 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16421 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16422 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16423 N->getValueType(0),
16424 InputVector.getNode()->getOperand(0));
16426 // Only operate on vectors of 4 elements, where the alternative shuffling
16427 // gets to be more expensive.
16428 if (InputVector.getValueType() != MVT::v4i32)
16431 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16432 // single use which is a sign-extend or zero-extend, and all elements are
16434 SmallVector<SDNode *, 4> Uses;
16435 unsigned ExtractedElements = 0;
16436 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16437 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16438 if (UI.getUse().getResNo() != InputVector.getResNo())
16441 SDNode *Extract = *UI;
16442 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16445 if (Extract->getValueType(0) != MVT::i32)
16447 if (!Extract->hasOneUse())
16449 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16450 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16452 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16455 // Record which element was extracted.
16456 ExtractedElements |=
16457 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16459 Uses.push_back(Extract);
16462 // If not all the elements were used, this may not be worthwhile.
16463 if (ExtractedElements != 15)
16466 // Ok, we've now decided to do the transformation.
16467 SDLoc dl(InputVector);
16469 // Store the value to a temporary stack slot.
16470 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16471 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16472 MachinePointerInfo(), false, false, 0);
16474 // Replace each use (extract) with a load of the appropriate element.
16475 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16476 UE = Uses.end(); UI != UE; ++UI) {
16477 SDNode *Extract = *UI;
16479 // cOMpute the element's address.
16480 SDValue Idx = Extract->getOperand(1);
16482 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16483 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16484 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16485 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16487 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16488 StackPtr, OffsetVal);
16490 // Load the scalar.
16491 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16492 ScalarAddr, MachinePointerInfo(),
16493 false, false, false, 0);
16495 // Replace the exact with the load.
16496 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16499 // The replacement was made in place; don't return anything.
16503 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16504 static std::pair<unsigned, bool>
16505 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16506 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16507 if (!VT.isVector())
16508 return std::make_pair(0, false);
16510 bool NeedSplit = false;
16511 switch (VT.getSimpleVT().SimpleTy) {
16512 default: return std::make_pair(0, false);
16516 if (!Subtarget->hasAVX2())
16518 if (!Subtarget->hasAVX())
16519 return std::make_pair(0, false);
16524 if (!Subtarget->hasSSE2())
16525 return std::make_pair(0, false);
16528 // SSE2 has only a small subset of the operations.
16529 bool hasUnsigned = Subtarget->hasSSE41() ||
16530 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16531 bool hasSigned = Subtarget->hasSSE41() ||
16532 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16534 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16537 // Check for x CC y ? x : y.
16538 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16539 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16544 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16547 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16550 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16553 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16555 // Check for x CC y ? y : x -- a min/max with reversed arms.
16556 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16557 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16562 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16565 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16568 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16571 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16575 return std::make_pair(Opc, NeedSplit);
16578 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16580 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16581 TargetLowering::DAGCombinerInfo &DCI,
16582 const X86Subtarget *Subtarget) {
16584 SDValue Cond = N->getOperand(0);
16585 // Get the LHS/RHS of the select.
16586 SDValue LHS = N->getOperand(1);
16587 SDValue RHS = N->getOperand(2);
16588 EVT VT = LHS.getValueType();
16589 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16591 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16592 // instructions match the semantics of the common C idiom x<y?x:y but not
16593 // x<=y?x:y, because of how they handle negative zero (which can be
16594 // ignored in unsafe-math mode).
16595 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16596 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16597 (Subtarget->hasSSE2() ||
16598 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16599 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16601 unsigned Opcode = 0;
16602 // Check for x CC y ? x : y.
16603 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16604 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16608 // Converting this to a min would handle NaNs incorrectly, and swapping
16609 // the operands would cause it to handle comparisons between positive
16610 // and negative zero incorrectly.
16611 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16612 if (!DAG.getTarget().Options.UnsafeFPMath &&
16613 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16615 std::swap(LHS, RHS);
16617 Opcode = X86ISD::FMIN;
16620 // Converting this to a min would handle comparisons between positive
16621 // and negative zero incorrectly.
16622 if (!DAG.getTarget().Options.UnsafeFPMath &&
16623 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16625 Opcode = X86ISD::FMIN;
16628 // Converting this to a min would handle both negative zeros and NaNs
16629 // incorrectly, but we can swap the operands to fix both.
16630 std::swap(LHS, RHS);
16634 Opcode = X86ISD::FMIN;
16638 // Converting this to a max would handle comparisons between positive
16639 // and negative zero incorrectly.
16640 if (!DAG.getTarget().Options.UnsafeFPMath &&
16641 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16643 Opcode = X86ISD::FMAX;
16646 // Converting this to a max would handle NaNs incorrectly, and swapping
16647 // the operands would cause it to handle comparisons between positive
16648 // and negative zero incorrectly.
16649 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16650 if (!DAG.getTarget().Options.UnsafeFPMath &&
16651 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16653 std::swap(LHS, RHS);
16655 Opcode = X86ISD::FMAX;
16658 // Converting this to a max would handle both negative zeros and NaNs
16659 // incorrectly, but we can swap the operands to fix both.
16660 std::swap(LHS, RHS);
16664 Opcode = X86ISD::FMAX;
16667 // Check for x CC y ? y : x -- a min/max with reversed arms.
16668 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16669 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16673 // Converting this to a min would handle comparisons between positive
16674 // and negative zero incorrectly, and swapping the operands would
16675 // cause it to handle NaNs incorrectly.
16676 if (!DAG.getTarget().Options.UnsafeFPMath &&
16677 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16678 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16680 std::swap(LHS, RHS);
16682 Opcode = X86ISD::FMIN;
16685 // Converting this to a min would handle NaNs incorrectly.
16686 if (!DAG.getTarget().Options.UnsafeFPMath &&
16687 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16689 Opcode = X86ISD::FMIN;
16692 // Converting this to a min would handle both negative zeros and NaNs
16693 // incorrectly, but we can swap the operands to fix both.
16694 std::swap(LHS, RHS);
16698 Opcode = X86ISD::FMIN;
16702 // Converting this to a max would handle NaNs incorrectly.
16703 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16705 Opcode = X86ISD::FMAX;
16708 // Converting this to a max would handle comparisons between positive
16709 // and negative zero incorrectly, and swapping the operands would
16710 // cause it to handle NaNs incorrectly.
16711 if (!DAG.getTarget().Options.UnsafeFPMath &&
16712 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16713 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16715 std::swap(LHS, RHS);
16717 Opcode = X86ISD::FMAX;
16720 // Converting this to a max would handle both negative zeros and NaNs
16721 // incorrectly, but we can swap the operands to fix both.
16722 std::swap(LHS, RHS);
16726 Opcode = X86ISD::FMAX;
16732 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16735 EVT CondVT = Cond.getValueType();
16736 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16737 CondVT.getVectorElementType() == MVT::i1) {
16738 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16739 // lowering on AVX-512. In this case we convert it to
16740 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16741 // The same situation for all 128 and 256-bit vectors of i8 and i16
16742 EVT OpVT = LHS.getValueType();
16743 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16744 (OpVT.getVectorElementType() == MVT::i8 ||
16745 OpVT.getVectorElementType() == MVT::i16)) {
16746 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16747 DCI.AddToWorklist(Cond.getNode());
16748 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16751 // If this is a select between two integer constants, try to do some
16753 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16754 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16755 // Don't do this for crazy integer types.
16756 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16757 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16758 // so that TrueC (the true value) is larger than FalseC.
16759 bool NeedsCondInvert = false;
16761 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16762 // Efficiently invertible.
16763 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16764 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16765 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16766 NeedsCondInvert = true;
16767 std::swap(TrueC, FalseC);
16770 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16771 if (FalseC->getAPIntValue() == 0 &&
16772 TrueC->getAPIntValue().isPowerOf2()) {
16773 if (NeedsCondInvert) // Invert the condition if needed.
16774 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16775 DAG.getConstant(1, Cond.getValueType()));
16777 // Zero extend the condition if needed.
16778 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16780 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16781 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16782 DAG.getConstant(ShAmt, MVT::i8));
16785 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16786 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16787 if (NeedsCondInvert) // Invert the condition if needed.
16788 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16789 DAG.getConstant(1, Cond.getValueType()));
16791 // Zero extend the condition if needed.
16792 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16793 FalseC->getValueType(0), Cond);
16794 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16795 SDValue(FalseC, 0));
16798 // Optimize cases that will turn into an LEA instruction. This requires
16799 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16800 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16801 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16802 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16804 bool isFastMultiplier = false;
16806 switch ((unsigned char)Diff) {
16808 case 1: // result = add base, cond
16809 case 2: // result = lea base( , cond*2)
16810 case 3: // result = lea base(cond, cond*2)
16811 case 4: // result = lea base( , cond*4)
16812 case 5: // result = lea base(cond, cond*4)
16813 case 8: // result = lea base( , cond*8)
16814 case 9: // result = lea base(cond, cond*8)
16815 isFastMultiplier = true;
16820 if (isFastMultiplier) {
16821 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16822 if (NeedsCondInvert) // Invert the condition if needed.
16823 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16824 DAG.getConstant(1, Cond.getValueType()));
16826 // Zero extend the condition if needed.
16827 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16829 // Scale the condition by the difference.
16831 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16832 DAG.getConstant(Diff, Cond.getValueType()));
16834 // Add the base if non-zero.
16835 if (FalseC->getAPIntValue() != 0)
16836 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16837 SDValue(FalseC, 0));
16844 // Canonicalize max and min:
16845 // (x > y) ? x : y -> (x >= y) ? x : y
16846 // (x < y) ? x : y -> (x <= y) ? x : y
16847 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16848 // the need for an extra compare
16849 // against zero. e.g.
16850 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16852 // testl %edi, %edi
16854 // cmovgl %edi, %eax
16858 // cmovsl %eax, %edi
16859 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16860 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16861 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16862 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16867 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16868 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16869 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16870 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16875 // Early exit check
16876 if (!TLI.isTypeLegal(VT))
16879 // Match VSELECTs into subs with unsigned saturation.
16880 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16881 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16882 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16883 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16884 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16886 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16887 // left side invert the predicate to simplify logic below.
16889 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16891 CC = ISD::getSetCCInverse(CC, true);
16892 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16896 if (Other.getNode() && Other->getNumOperands() == 2 &&
16897 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16898 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16899 SDValue CondRHS = Cond->getOperand(1);
16901 // Look for a general sub with unsigned saturation first.
16902 // x >= y ? x-y : 0 --> subus x, y
16903 // x > y ? x-y : 0 --> subus x, y
16904 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16905 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16906 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16908 // If the RHS is a constant we have to reverse the const canonicalization.
16909 // x > C-1 ? x+-C : 0 --> subus x, C
16910 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16911 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16912 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16913 if (CondRHS.getConstantOperandVal(0) == -A-1)
16914 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16915 DAG.getConstant(-A, VT));
16918 // Another special case: If C was a sign bit, the sub has been
16919 // canonicalized into a xor.
16920 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16921 // it's safe to decanonicalize the xor?
16922 // x s< 0 ? x^C : 0 --> subus x, C
16923 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16924 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16925 isSplatVector(OpRHS.getNode())) {
16926 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16928 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16933 // Try to match a min/max vector operation.
16934 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16935 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16936 unsigned Opc = ret.first;
16937 bool NeedSplit = ret.second;
16939 if (Opc && NeedSplit) {
16940 unsigned NumElems = VT.getVectorNumElements();
16941 // Extract the LHS vectors
16942 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16943 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16945 // Extract the RHS vectors
16946 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16947 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16949 // Create min/max for each subvector
16950 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16951 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16953 // Merge the result
16954 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16956 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16959 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16960 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16961 // Check if SETCC has already been promoted
16962 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16964 assert(Cond.getValueType().isVector() &&
16965 "vector select expects a vector selector!");
16967 EVT IntVT = Cond.getValueType();
16968 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16969 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16971 if (!TValIsAllOnes && !FValIsAllZeros) {
16972 // Try invert the condition if true value is not all 1s and false value
16974 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16975 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16977 if (TValIsAllZeros || FValIsAllOnes) {
16978 SDValue CC = Cond.getOperand(2);
16979 ISD::CondCode NewCC =
16980 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16981 Cond.getOperand(0).getValueType().isInteger());
16982 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16983 std::swap(LHS, RHS);
16984 TValIsAllOnes = FValIsAllOnes;
16985 FValIsAllZeros = TValIsAllZeros;
16989 if (TValIsAllOnes || FValIsAllZeros) {
16992 if (TValIsAllOnes && FValIsAllZeros)
16994 else if (TValIsAllOnes)
16995 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16996 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16997 else if (FValIsAllZeros)
16998 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16999 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
17001 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17005 // If we know that this node is legal then we know that it is going to be
17006 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17007 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17008 // to simplify previous instructions.
17009 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17010 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17011 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17013 // Don't optimize vector selects that map to mask-registers.
17017 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17018 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17020 APInt KnownZero, KnownOne;
17021 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17022 DCI.isBeforeLegalizeOps());
17023 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17024 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17025 DCI.CommitTargetLoweringOpt(TLO);
17031 // Check whether a boolean test is testing a boolean value generated by
17032 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17035 // Simplify the following patterns:
17036 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17037 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17038 // to (Op EFLAGS Cond)
17040 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17041 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17042 // to (Op EFLAGS !Cond)
17044 // where Op could be BRCOND or CMOV.
17046 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17047 // Quit if not CMP and SUB with its value result used.
17048 if (Cmp.getOpcode() != X86ISD::CMP &&
17049 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17052 // Quit if not used as a boolean value.
17053 if (CC != X86::COND_E && CC != X86::COND_NE)
17056 // Check CMP operands. One of them should be 0 or 1 and the other should be
17057 // an SetCC or extended from it.
17058 SDValue Op1 = Cmp.getOperand(0);
17059 SDValue Op2 = Cmp.getOperand(1);
17062 const ConstantSDNode* C = 0;
17063 bool needOppositeCond = (CC == X86::COND_E);
17064 bool checkAgainstTrue = false; // Is it a comparison against 1?
17066 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17068 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17070 else // Quit if all operands are not constants.
17073 if (C->getZExtValue() == 1) {
17074 needOppositeCond = !needOppositeCond;
17075 checkAgainstTrue = true;
17076 } else if (C->getZExtValue() != 0)
17077 // Quit if the constant is neither 0 or 1.
17080 bool truncatedToBoolWithAnd = false;
17081 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17082 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17083 SetCC.getOpcode() == ISD::TRUNCATE ||
17084 SetCC.getOpcode() == ISD::AND) {
17085 if (SetCC.getOpcode() == ISD::AND) {
17087 ConstantSDNode *CS;
17088 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17089 CS->getZExtValue() == 1)
17091 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17092 CS->getZExtValue() == 1)
17096 SetCC = SetCC.getOperand(OpIdx);
17097 truncatedToBoolWithAnd = true;
17099 SetCC = SetCC.getOperand(0);
17102 switch (SetCC.getOpcode()) {
17103 case X86ISD::SETCC_CARRY:
17104 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17105 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17106 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17107 // truncated to i1 using 'and'.
17108 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17110 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17111 "Invalid use of SETCC_CARRY!");
17113 case X86ISD::SETCC:
17114 // Set the condition code or opposite one if necessary.
17115 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17116 if (needOppositeCond)
17117 CC = X86::GetOppositeBranchCondition(CC);
17118 return SetCC.getOperand(1);
17119 case X86ISD::CMOV: {
17120 // Check whether false/true value has canonical one, i.e. 0 or 1.
17121 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17122 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17123 // Quit if true value is not a constant.
17126 // Quit if false value is not a constant.
17128 SDValue Op = SetCC.getOperand(0);
17129 // Skip 'zext' or 'trunc' node.
17130 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17131 Op.getOpcode() == ISD::TRUNCATE)
17132 Op = Op.getOperand(0);
17133 // A special case for rdrand/rdseed, where 0 is set if false cond is
17135 if ((Op.getOpcode() != X86ISD::RDRAND &&
17136 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17139 // Quit if false value is not the constant 0 or 1.
17140 bool FValIsFalse = true;
17141 if (FVal && FVal->getZExtValue() != 0) {
17142 if (FVal->getZExtValue() != 1)
17144 // If FVal is 1, opposite cond is needed.
17145 needOppositeCond = !needOppositeCond;
17146 FValIsFalse = false;
17148 // Quit if TVal is not the constant opposite of FVal.
17149 if (FValIsFalse && TVal->getZExtValue() != 1)
17151 if (!FValIsFalse && TVal->getZExtValue() != 0)
17153 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17154 if (needOppositeCond)
17155 CC = X86::GetOppositeBranchCondition(CC);
17156 return SetCC.getOperand(3);
17163 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17164 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17165 TargetLowering::DAGCombinerInfo &DCI,
17166 const X86Subtarget *Subtarget) {
17169 // If the flag operand isn't dead, don't touch this CMOV.
17170 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17173 SDValue FalseOp = N->getOperand(0);
17174 SDValue TrueOp = N->getOperand(1);
17175 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17176 SDValue Cond = N->getOperand(3);
17178 if (CC == X86::COND_E || CC == X86::COND_NE) {
17179 switch (Cond.getOpcode()) {
17183 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17184 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17185 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17191 Flags = checkBoolTestSetCCCombine(Cond, CC);
17192 if (Flags.getNode() &&
17193 // Extra check as FCMOV only supports a subset of X86 cond.
17194 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17195 SDValue Ops[] = { FalseOp, TrueOp,
17196 DAG.getConstant(CC, MVT::i8), Flags };
17197 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17198 Ops, array_lengthof(Ops));
17201 // If this is a select between two integer constants, try to do some
17202 // optimizations. Note that the operands are ordered the opposite of SELECT
17204 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17205 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17206 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17207 // larger than FalseC (the false value).
17208 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17209 CC = X86::GetOppositeBranchCondition(CC);
17210 std::swap(TrueC, FalseC);
17211 std::swap(TrueOp, FalseOp);
17214 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17215 // This is efficient for any integer data type (including i8/i16) and
17217 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17218 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17219 DAG.getConstant(CC, MVT::i8), Cond);
17221 // Zero extend the condition if needed.
17222 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17224 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17225 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17226 DAG.getConstant(ShAmt, MVT::i8));
17227 if (N->getNumValues() == 2) // Dead flag value?
17228 return DCI.CombineTo(N, Cond, SDValue());
17232 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17233 // for any integer data type, including i8/i16.
17234 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17235 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17236 DAG.getConstant(CC, MVT::i8), Cond);
17238 // Zero extend the condition if needed.
17239 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17240 FalseC->getValueType(0), Cond);
17241 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17242 SDValue(FalseC, 0));
17244 if (N->getNumValues() == 2) // Dead flag value?
17245 return DCI.CombineTo(N, Cond, SDValue());
17249 // Optimize cases that will turn into an LEA instruction. This requires
17250 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17251 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17252 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17253 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17255 bool isFastMultiplier = false;
17257 switch ((unsigned char)Diff) {
17259 case 1: // result = add base, cond
17260 case 2: // result = lea base( , cond*2)
17261 case 3: // result = lea base(cond, cond*2)
17262 case 4: // result = lea base( , cond*4)
17263 case 5: // result = lea base(cond, cond*4)
17264 case 8: // result = lea base( , cond*8)
17265 case 9: // result = lea base(cond, cond*8)
17266 isFastMultiplier = true;
17271 if (isFastMultiplier) {
17272 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17273 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17274 DAG.getConstant(CC, MVT::i8), Cond);
17275 // Zero extend the condition if needed.
17276 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17278 // Scale the condition by the difference.
17280 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17281 DAG.getConstant(Diff, Cond.getValueType()));
17283 // Add the base if non-zero.
17284 if (FalseC->getAPIntValue() != 0)
17285 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17286 SDValue(FalseC, 0));
17287 if (N->getNumValues() == 2) // Dead flag value?
17288 return DCI.CombineTo(N, Cond, SDValue());
17295 // Handle these cases:
17296 // (select (x != c), e, c) -> select (x != c), e, x),
17297 // (select (x == c), c, e) -> select (x == c), x, e)
17298 // where the c is an integer constant, and the "select" is the combination
17299 // of CMOV and CMP.
17301 // The rationale for this change is that the conditional-move from a constant
17302 // needs two instructions, however, conditional-move from a register needs
17303 // only one instruction.
17305 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17306 // some instruction-combining opportunities. This opt needs to be
17307 // postponed as late as possible.
17309 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17310 // the DCI.xxxx conditions are provided to postpone the optimization as
17311 // late as possible.
17313 ConstantSDNode *CmpAgainst = 0;
17314 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17315 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17316 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17318 if (CC == X86::COND_NE &&
17319 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17320 CC = X86::GetOppositeBranchCondition(CC);
17321 std::swap(TrueOp, FalseOp);
17324 if (CC == X86::COND_E &&
17325 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17326 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17327 DAG.getConstant(CC, MVT::i8), Cond };
17328 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17329 array_lengthof(Ops));
17337 /// PerformMulCombine - Optimize a single multiply with constant into two
17338 /// in order to implement it with two cheaper instructions, e.g.
17339 /// LEA + SHL, LEA + LEA.
17340 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17341 TargetLowering::DAGCombinerInfo &DCI) {
17342 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17345 EVT VT = N->getValueType(0);
17346 if (VT != MVT::i64)
17349 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17352 uint64_t MulAmt = C->getZExtValue();
17353 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17356 uint64_t MulAmt1 = 0;
17357 uint64_t MulAmt2 = 0;
17358 if ((MulAmt % 9) == 0) {
17360 MulAmt2 = MulAmt / 9;
17361 } else if ((MulAmt % 5) == 0) {
17363 MulAmt2 = MulAmt / 5;
17364 } else if ((MulAmt % 3) == 0) {
17366 MulAmt2 = MulAmt / 3;
17369 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17372 if (isPowerOf2_64(MulAmt2) &&
17373 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17374 // If second multiplifer is pow2, issue it first. We want the multiply by
17375 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17377 std::swap(MulAmt1, MulAmt2);
17380 if (isPowerOf2_64(MulAmt1))
17381 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17382 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17384 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17385 DAG.getConstant(MulAmt1, VT));
17387 if (isPowerOf2_64(MulAmt2))
17388 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17389 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17391 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17392 DAG.getConstant(MulAmt2, VT));
17394 // Do not add new nodes to DAG combiner worklist.
17395 DCI.CombineTo(N, NewMul, false);
17400 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17401 SDValue N0 = N->getOperand(0);
17402 SDValue N1 = N->getOperand(1);
17403 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17404 EVT VT = N0.getValueType();
17406 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17407 // since the result of setcc_c is all zero's or all ones.
17408 if (VT.isInteger() && !VT.isVector() &&
17409 N1C && N0.getOpcode() == ISD::AND &&
17410 N0.getOperand(1).getOpcode() == ISD::Constant) {
17411 SDValue N00 = N0.getOperand(0);
17412 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17413 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17414 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17415 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17416 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17417 APInt ShAmt = N1C->getAPIntValue();
17418 Mask = Mask.shl(ShAmt);
17420 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17421 N00, DAG.getConstant(Mask, VT));
17425 // Hardware support for vector shifts is sparse which makes us scalarize the
17426 // vector operations in many cases. Also, on sandybridge ADD is faster than
17428 // (shl V, 1) -> add V,V
17429 if (isSplatVector(N1.getNode())) {
17430 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17431 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17432 // We shift all of the values by one. In many cases we do not have
17433 // hardware support for this operation. This is better expressed as an ADD
17435 if (N1C && (1 == N1C->getZExtValue())) {
17436 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17443 /// \brief Returns a vector of 0s if the node in input is a vector logical
17444 /// shift by a constant amount which is known to be bigger than or equal
17445 /// to the vector element size in bits.
17446 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17447 const X86Subtarget *Subtarget) {
17448 EVT VT = N->getValueType(0);
17450 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17451 (!Subtarget->hasInt256() ||
17452 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17455 SDValue Amt = N->getOperand(1);
17457 if (isSplatVector(Amt.getNode())) {
17458 SDValue SclrAmt = Amt->getOperand(0);
17459 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17460 APInt ShiftAmt = C->getAPIntValue();
17461 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17463 // SSE2/AVX2 logical shifts always return a vector of 0s
17464 // if the shift amount is bigger than or equal to
17465 // the element size. The constant shift amount will be
17466 // encoded as a 8-bit immediate.
17467 if (ShiftAmt.trunc(8).uge(MaxAmount))
17468 return getZeroVector(VT, Subtarget, DAG, DL);
17475 /// PerformShiftCombine - Combine shifts.
17476 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17477 TargetLowering::DAGCombinerInfo &DCI,
17478 const X86Subtarget *Subtarget) {
17479 if (N->getOpcode() == ISD::SHL) {
17480 SDValue V = PerformSHLCombine(N, DAG);
17481 if (V.getNode()) return V;
17484 if (N->getOpcode() != ISD::SRA) {
17485 // Try to fold this logical shift into a zero vector.
17486 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17487 if (V.getNode()) return V;
17493 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17494 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17495 // and friends. Likewise for OR -> CMPNEQSS.
17496 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17497 TargetLowering::DAGCombinerInfo &DCI,
17498 const X86Subtarget *Subtarget) {
17501 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17502 // we're requiring SSE2 for both.
17503 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17504 SDValue N0 = N->getOperand(0);
17505 SDValue N1 = N->getOperand(1);
17506 SDValue CMP0 = N0->getOperand(1);
17507 SDValue CMP1 = N1->getOperand(1);
17510 // The SETCCs should both refer to the same CMP.
17511 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17514 SDValue CMP00 = CMP0->getOperand(0);
17515 SDValue CMP01 = CMP0->getOperand(1);
17516 EVT VT = CMP00.getValueType();
17518 if (VT == MVT::f32 || VT == MVT::f64) {
17519 bool ExpectingFlags = false;
17520 // Check for any users that want flags:
17521 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17522 !ExpectingFlags && UI != UE; ++UI)
17523 switch (UI->getOpcode()) {
17528 ExpectingFlags = true;
17530 case ISD::CopyToReg:
17531 case ISD::SIGN_EXTEND:
17532 case ISD::ZERO_EXTEND:
17533 case ISD::ANY_EXTEND:
17537 if (!ExpectingFlags) {
17538 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17539 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17541 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17542 X86::CondCode tmp = cc0;
17547 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17548 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17549 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17550 X86ISD::NodeType NTOperator = is64BitFP ?
17551 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17552 // FIXME: need symbolic constants for these magic numbers.
17553 // See X86ATTInstPrinter.cpp:printSSECC().
17554 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17555 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17556 DAG.getConstant(x86cc, MVT::i8));
17557 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17559 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17560 DAG.getConstant(1, MVT::i32));
17561 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17562 return OneBitOfTruth;
17570 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17571 /// so it can be folded inside ANDNP.
17572 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17573 EVT VT = N->getValueType(0);
17575 // Match direct AllOnes for 128 and 256-bit vectors
17576 if (ISD::isBuildVectorAllOnes(N))
17579 // Look through a bit convert.
17580 if (N->getOpcode() == ISD::BITCAST)
17581 N = N->getOperand(0).getNode();
17583 // Sometimes the operand may come from a insert_subvector building a 256-bit
17585 if (VT.is256BitVector() &&
17586 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17587 SDValue V1 = N->getOperand(0);
17588 SDValue V2 = N->getOperand(1);
17590 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17591 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17592 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17593 ISD::isBuildVectorAllOnes(V2.getNode()))
17600 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17601 // register. In most cases we actually compare or select YMM-sized registers
17602 // and mixing the two types creates horrible code. This method optimizes
17603 // some of the transition sequences.
17604 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17605 TargetLowering::DAGCombinerInfo &DCI,
17606 const X86Subtarget *Subtarget) {
17607 EVT VT = N->getValueType(0);
17608 if (!VT.is256BitVector())
17611 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17612 N->getOpcode() == ISD::ZERO_EXTEND ||
17613 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17615 SDValue Narrow = N->getOperand(0);
17616 EVT NarrowVT = Narrow->getValueType(0);
17617 if (!NarrowVT.is128BitVector())
17620 if (Narrow->getOpcode() != ISD::XOR &&
17621 Narrow->getOpcode() != ISD::AND &&
17622 Narrow->getOpcode() != ISD::OR)
17625 SDValue N0 = Narrow->getOperand(0);
17626 SDValue N1 = Narrow->getOperand(1);
17629 // The Left side has to be a trunc.
17630 if (N0.getOpcode() != ISD::TRUNCATE)
17633 // The type of the truncated inputs.
17634 EVT WideVT = N0->getOperand(0)->getValueType(0);
17638 // The right side has to be a 'trunc' or a constant vector.
17639 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17640 bool RHSConst = (isSplatVector(N1.getNode()) &&
17641 isa<ConstantSDNode>(N1->getOperand(0)));
17642 if (!RHSTrunc && !RHSConst)
17645 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17647 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17650 // Set N0 and N1 to hold the inputs to the new wide operation.
17651 N0 = N0->getOperand(0);
17653 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17654 N1->getOperand(0));
17655 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17656 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17657 } else if (RHSTrunc) {
17658 N1 = N1->getOperand(0);
17661 // Generate the wide operation.
17662 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17663 unsigned Opcode = N->getOpcode();
17665 case ISD::ANY_EXTEND:
17667 case ISD::ZERO_EXTEND: {
17668 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17669 APInt Mask = APInt::getAllOnesValue(InBits);
17670 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17671 return DAG.getNode(ISD::AND, DL, VT,
17672 Op, DAG.getConstant(Mask, VT));
17674 case ISD::SIGN_EXTEND:
17675 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17676 Op, DAG.getValueType(NarrowVT));
17678 llvm_unreachable("Unexpected opcode");
17682 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17683 TargetLowering::DAGCombinerInfo &DCI,
17684 const X86Subtarget *Subtarget) {
17685 EVT VT = N->getValueType(0);
17686 if (DCI.isBeforeLegalizeOps())
17689 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17693 // Create BLSI, BLSR, and BZHI instructions
17694 // BLSI is X & (-X)
17695 // BLSR is X & (X-1)
17696 // BZHI is X & ((1 << Y) - 1)
17697 // BEXTR is ((X >> imm) & (2**size-1))
17698 if (VT == MVT::i32 || VT == MVT::i64) {
17699 SDValue N0 = N->getOperand(0);
17700 SDValue N1 = N->getOperand(1);
17703 if (Subtarget->hasBMI()) {
17704 // Check LHS for neg
17705 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17706 isZero(N0.getOperand(0)))
17707 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17709 // Check RHS for neg
17710 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17711 isZero(N1.getOperand(0)))
17712 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17714 // Check LHS for X-1
17715 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17716 isAllOnes(N0.getOperand(1)))
17717 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17719 // Check RHS for X-1
17720 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17721 isAllOnes(N1.getOperand(1)))
17722 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17725 if (Subtarget->hasBMI2()) {
17726 // Check for (and (add (shl 1, Y), -1), X)
17727 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17728 SDValue N00 = N0.getOperand(0);
17729 if (N00.getOpcode() == ISD::SHL) {
17730 SDValue N001 = N00.getOperand(1);
17731 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17732 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17733 if (C && C->getZExtValue() == 1)
17734 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17738 // Check for (and X, (add (shl 1, Y), -1))
17739 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17740 SDValue N10 = N1.getOperand(0);
17741 if (N10.getOpcode() == ISD::SHL) {
17742 SDValue N101 = N10.getOperand(1);
17743 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17744 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17745 if (C && C->getZExtValue() == 1)
17746 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17751 // Check for BEXTR.
17752 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17753 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17754 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17755 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17756 if (MaskNode && ShiftNode) {
17757 uint64_t Mask = MaskNode->getZExtValue();
17758 uint64_t Shift = ShiftNode->getZExtValue();
17759 if (isMask_64(Mask)) {
17760 uint64_t MaskSize = CountPopulation_64(Mask);
17761 if (Shift + MaskSize <= VT.getSizeInBits())
17762 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17763 DAG.getConstant(Shift | (MaskSize << 8), VT));
17771 // Want to form ANDNP nodes:
17772 // 1) In the hopes of then easily combining them with OR and AND nodes
17773 // to form PBLEND/PSIGN.
17774 // 2) To match ANDN packed intrinsics
17775 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17778 SDValue N0 = N->getOperand(0);
17779 SDValue N1 = N->getOperand(1);
17782 // Check LHS for vnot
17783 if (N0.getOpcode() == ISD::XOR &&
17784 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17785 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17786 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17788 // Check RHS for vnot
17789 if (N1.getOpcode() == ISD::XOR &&
17790 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17791 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17792 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17797 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17798 TargetLowering::DAGCombinerInfo &DCI,
17799 const X86Subtarget *Subtarget) {
17800 EVT VT = N->getValueType(0);
17801 if (DCI.isBeforeLegalizeOps())
17804 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17808 SDValue N0 = N->getOperand(0);
17809 SDValue N1 = N->getOperand(1);
17811 // look for psign/blend
17812 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17813 if (!Subtarget->hasSSSE3() ||
17814 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17817 // Canonicalize pandn to RHS
17818 if (N0.getOpcode() == X86ISD::ANDNP)
17820 // or (and (m, y), (pandn m, x))
17821 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17822 SDValue Mask = N1.getOperand(0);
17823 SDValue X = N1.getOperand(1);
17825 if (N0.getOperand(0) == Mask)
17826 Y = N0.getOperand(1);
17827 if (N0.getOperand(1) == Mask)
17828 Y = N0.getOperand(0);
17830 // Check to see if the mask appeared in both the AND and ANDNP and
17834 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17835 // Look through mask bitcast.
17836 if (Mask.getOpcode() == ISD::BITCAST)
17837 Mask = Mask.getOperand(0);
17838 if (X.getOpcode() == ISD::BITCAST)
17839 X = X.getOperand(0);
17840 if (Y.getOpcode() == ISD::BITCAST)
17841 Y = Y.getOperand(0);
17843 EVT MaskVT = Mask.getValueType();
17845 // Validate that the Mask operand is a vector sra node.
17846 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17847 // there is no psrai.b
17848 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17849 unsigned SraAmt = ~0;
17850 if (Mask.getOpcode() == ISD::SRA) {
17851 SDValue Amt = Mask.getOperand(1);
17852 if (isSplatVector(Amt.getNode())) {
17853 SDValue SclrAmt = Amt->getOperand(0);
17854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17855 SraAmt = C->getZExtValue();
17857 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17858 SDValue SraC = Mask.getOperand(1);
17859 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17861 if ((SraAmt + 1) != EltBits)
17866 // Now we know we at least have a plendvb with the mask val. See if
17867 // we can form a psignb/w/d.
17868 // psign = x.type == y.type == mask.type && y = sub(0, x);
17869 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17870 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17871 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17872 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17873 "Unsupported VT for PSIGN");
17874 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17875 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17877 // PBLENDVB only available on SSE 4.1
17878 if (!Subtarget->hasSSE41())
17881 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17883 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17884 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17885 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17886 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17887 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17891 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17894 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17895 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17897 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17899 if (!N0.hasOneUse() || !N1.hasOneUse())
17902 SDValue ShAmt0 = N0.getOperand(1);
17903 if (ShAmt0.getValueType() != MVT::i8)
17905 SDValue ShAmt1 = N1.getOperand(1);
17906 if (ShAmt1.getValueType() != MVT::i8)
17908 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17909 ShAmt0 = ShAmt0.getOperand(0);
17910 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17911 ShAmt1 = ShAmt1.getOperand(0);
17914 unsigned Opc = X86ISD::SHLD;
17915 SDValue Op0 = N0.getOperand(0);
17916 SDValue Op1 = N1.getOperand(0);
17917 if (ShAmt0.getOpcode() == ISD::SUB) {
17918 Opc = X86ISD::SHRD;
17919 std::swap(Op0, Op1);
17920 std::swap(ShAmt0, ShAmt1);
17923 unsigned Bits = VT.getSizeInBits();
17924 if (ShAmt1.getOpcode() == ISD::SUB) {
17925 SDValue Sum = ShAmt1.getOperand(0);
17926 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17927 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17928 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17929 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17930 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17931 return DAG.getNode(Opc, DL, VT,
17933 DAG.getNode(ISD::TRUNCATE, DL,
17936 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17937 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17939 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17940 return DAG.getNode(Opc, DL, VT,
17941 N0.getOperand(0), N1.getOperand(0),
17942 DAG.getNode(ISD::TRUNCATE, DL,
17949 // Generate NEG and CMOV for integer abs.
17950 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17951 EVT VT = N->getValueType(0);
17953 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17954 // 8-bit integer abs to NEG and CMOV.
17955 if (VT.isInteger() && VT.getSizeInBits() == 8)
17958 SDValue N0 = N->getOperand(0);
17959 SDValue N1 = N->getOperand(1);
17962 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17963 // and change it to SUB and CMOV.
17964 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17965 N0.getOpcode() == ISD::ADD &&
17966 N0.getOperand(1) == N1 &&
17967 N1.getOpcode() == ISD::SRA &&
17968 N1.getOperand(0) == N0.getOperand(0))
17969 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17970 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17971 // Generate SUB & CMOV.
17972 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17973 DAG.getConstant(0, VT), N0.getOperand(0));
17975 SDValue Ops[] = { N0.getOperand(0), Neg,
17976 DAG.getConstant(X86::COND_GE, MVT::i8),
17977 SDValue(Neg.getNode(), 1) };
17978 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17979 Ops, array_lengthof(Ops));
17984 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17985 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17986 TargetLowering::DAGCombinerInfo &DCI,
17987 const X86Subtarget *Subtarget) {
17988 EVT VT = N->getValueType(0);
17989 if (DCI.isBeforeLegalizeOps())
17992 if (Subtarget->hasCMov()) {
17993 SDValue RV = performIntegerAbsCombine(N, DAG);
17998 // Try forming BMI if it is available.
17999 if (!Subtarget->hasBMI())
18002 if (VT != MVT::i32 && VT != MVT::i64)
18005 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18007 // Create BLSMSK instructions by finding X ^ (X-1)
18008 SDValue N0 = N->getOperand(0);
18009 SDValue N1 = N->getOperand(1);
18012 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18013 isAllOnes(N0.getOperand(1)))
18014 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18016 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18017 isAllOnes(N1.getOperand(1)))
18018 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18023 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18024 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18025 TargetLowering::DAGCombinerInfo &DCI,
18026 const X86Subtarget *Subtarget) {
18027 LoadSDNode *Ld = cast<LoadSDNode>(N);
18028 EVT RegVT = Ld->getValueType(0);
18029 EVT MemVT = Ld->getMemoryVT();
18031 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18032 unsigned RegSz = RegVT.getSizeInBits();
18034 // On Sandybridge unaligned 256bit loads are inefficient.
18035 ISD::LoadExtType Ext = Ld->getExtensionType();
18036 unsigned Alignment = Ld->getAlignment();
18037 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18038 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18039 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18040 unsigned NumElems = RegVT.getVectorNumElements();
18044 SDValue Ptr = Ld->getBasePtr();
18045 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18047 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18049 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18050 Ld->getPointerInfo(), Ld->isVolatile(),
18051 Ld->isNonTemporal(), Ld->isInvariant(),
18053 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18054 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18055 Ld->getPointerInfo(), Ld->isVolatile(),
18056 Ld->isNonTemporal(), Ld->isInvariant(),
18057 std::min(16U, Alignment));
18058 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18060 Load2.getValue(1));
18062 SDValue NewVec = DAG.getUNDEF(RegVT);
18063 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18064 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18065 return DCI.CombineTo(N, NewVec, TF, true);
18068 // If this is a vector EXT Load then attempt to optimize it using a
18069 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18070 // expansion is still better than scalar code.
18071 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18072 // emit a shuffle and a arithmetic shift.
18073 // TODO: It is possible to support ZExt by zeroing the undef values
18074 // during the shuffle phase or after the shuffle.
18075 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18076 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18077 assert(MemVT != RegVT && "Cannot extend to the same type");
18078 assert(MemVT.isVector() && "Must load a vector from memory");
18080 unsigned NumElems = RegVT.getVectorNumElements();
18081 unsigned MemSz = MemVT.getSizeInBits();
18082 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18084 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18087 // All sizes must be a power of two.
18088 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18091 // Attempt to load the original value using scalar loads.
18092 // Find the largest scalar type that divides the total loaded size.
18093 MVT SclrLoadTy = MVT::i8;
18094 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18095 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18096 MVT Tp = (MVT::SimpleValueType)tp;
18097 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18102 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18103 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18105 SclrLoadTy = MVT::f64;
18107 // Calculate the number of scalar loads that we need to perform
18108 // in order to load our vector from memory.
18109 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18110 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18113 unsigned loadRegZize = RegSz;
18114 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18117 // Represent our vector as a sequence of elements which are the
18118 // largest scalar that we can load.
18119 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18120 loadRegZize/SclrLoadTy.getSizeInBits());
18122 // Represent the data using the same element type that is stored in
18123 // memory. In practice, we ''widen'' MemVT.
18125 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18126 loadRegZize/MemVT.getScalarType().getSizeInBits());
18128 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18129 "Invalid vector type");
18131 // We can't shuffle using an illegal type.
18132 if (!TLI.isTypeLegal(WideVecVT))
18135 SmallVector<SDValue, 8> Chains;
18136 SDValue Ptr = Ld->getBasePtr();
18137 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18138 TLI.getPointerTy());
18139 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18141 for (unsigned i = 0; i < NumLoads; ++i) {
18142 // Perform a single load.
18143 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18144 Ptr, Ld->getPointerInfo(),
18145 Ld->isVolatile(), Ld->isNonTemporal(),
18146 Ld->isInvariant(), Ld->getAlignment());
18147 Chains.push_back(ScalarLoad.getValue(1));
18148 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18149 // another round of DAGCombining.
18151 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18153 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18154 ScalarLoad, DAG.getIntPtrConstant(i));
18156 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18159 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18162 // Bitcast the loaded value to a vector of the original element type, in
18163 // the size of the target vector type.
18164 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18165 unsigned SizeRatio = RegSz/MemSz;
18167 if (Ext == ISD::SEXTLOAD) {
18168 // If we have SSE4.1 we can directly emit a VSEXT node.
18169 if (Subtarget->hasSSE41()) {
18170 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18171 return DCI.CombineTo(N, Sext, TF, true);
18174 // Otherwise we'll shuffle the small elements in the high bits of the
18175 // larger type and perform an arithmetic shift. If the shift is not legal
18176 // it's better to scalarize.
18177 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18180 // Redistribute the loaded elements into the different locations.
18181 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18182 for (unsigned i = 0; i != NumElems; ++i)
18183 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18185 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18186 DAG.getUNDEF(WideVecVT),
18189 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18191 // Build the arithmetic shift.
18192 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18193 MemVT.getVectorElementType().getSizeInBits();
18194 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18195 DAG.getConstant(Amt, RegVT));
18197 return DCI.CombineTo(N, Shuff, TF, true);
18200 // Redistribute the loaded elements into the different locations.
18201 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18202 for (unsigned i = 0; i != NumElems; ++i)
18203 ShuffleVec[i*SizeRatio] = i;
18205 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18206 DAG.getUNDEF(WideVecVT),
18209 // Bitcast to the requested type.
18210 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18211 // Replace the original load with the new sequence
18212 // and return the new chain.
18213 return DCI.CombineTo(N, Shuff, TF, true);
18219 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18220 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18221 const X86Subtarget *Subtarget) {
18222 StoreSDNode *St = cast<StoreSDNode>(N);
18223 EVT VT = St->getValue().getValueType();
18224 EVT StVT = St->getMemoryVT();
18226 SDValue StoredVal = St->getOperand(1);
18227 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18229 // If we are saving a concatenation of two XMM registers, perform two stores.
18230 // On Sandy Bridge, 256-bit memory operations are executed by two
18231 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18232 // memory operation.
18233 unsigned Alignment = St->getAlignment();
18234 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18235 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18236 StVT == VT && !IsAligned) {
18237 unsigned NumElems = VT.getVectorNumElements();
18241 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18242 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18244 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18245 SDValue Ptr0 = St->getBasePtr();
18246 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18248 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18249 St->getPointerInfo(), St->isVolatile(),
18250 St->isNonTemporal(), Alignment);
18251 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18252 St->getPointerInfo(), St->isVolatile(),
18253 St->isNonTemporal(),
18254 std::min(16U, Alignment));
18255 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18258 // Optimize trunc store (of multiple scalars) to shuffle and store.
18259 // First, pack all of the elements in one place. Next, store to memory
18260 // in fewer chunks.
18261 if (St->isTruncatingStore() && VT.isVector()) {
18262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18263 unsigned NumElems = VT.getVectorNumElements();
18264 assert(StVT != VT && "Cannot truncate to the same type");
18265 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18266 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18268 // From, To sizes and ElemCount must be pow of two
18269 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18270 // We are going to use the original vector elt for storing.
18271 // Accumulated smaller vector elements must be a multiple of the store size.
18272 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18274 unsigned SizeRatio = FromSz / ToSz;
18276 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18278 // Create a type on which we perform the shuffle
18279 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18280 StVT.getScalarType(), NumElems*SizeRatio);
18282 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18284 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18285 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18286 for (unsigned i = 0; i != NumElems; ++i)
18287 ShuffleVec[i] = i * SizeRatio;
18289 // Can't shuffle using an illegal type.
18290 if (!TLI.isTypeLegal(WideVecVT))
18293 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18294 DAG.getUNDEF(WideVecVT),
18296 // At this point all of the data is stored at the bottom of the
18297 // register. We now need to save it to mem.
18299 // Find the largest store unit
18300 MVT StoreType = MVT::i8;
18301 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18302 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18303 MVT Tp = (MVT::SimpleValueType)tp;
18304 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18308 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18309 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18310 (64 <= NumElems * ToSz))
18311 StoreType = MVT::f64;
18313 // Bitcast the original vector into a vector of store-size units
18314 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18315 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18316 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18317 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18318 SmallVector<SDValue, 8> Chains;
18319 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18320 TLI.getPointerTy());
18321 SDValue Ptr = St->getBasePtr();
18323 // Perform one or more big stores into memory.
18324 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18325 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18326 StoreType, ShuffWide,
18327 DAG.getIntPtrConstant(i));
18328 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18329 St->getPointerInfo(), St->isVolatile(),
18330 St->isNonTemporal(), St->getAlignment());
18331 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18332 Chains.push_back(Ch);
18335 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18339 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18340 // the FP state in cases where an emms may be missing.
18341 // A preferable solution to the general problem is to figure out the right
18342 // places to insert EMMS. This qualifies as a quick hack.
18344 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18345 if (VT.getSizeInBits() != 64)
18348 const Function *F = DAG.getMachineFunction().getFunction();
18349 bool NoImplicitFloatOps = F->getAttributes().
18350 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18351 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18352 && Subtarget->hasSSE2();
18353 if ((VT.isVector() ||
18354 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18355 isa<LoadSDNode>(St->getValue()) &&
18356 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18357 St->getChain().hasOneUse() && !St->isVolatile()) {
18358 SDNode* LdVal = St->getValue().getNode();
18359 LoadSDNode *Ld = 0;
18360 int TokenFactorIndex = -1;
18361 SmallVector<SDValue, 8> Ops;
18362 SDNode* ChainVal = St->getChain().getNode();
18363 // Must be a store of a load. We currently handle two cases: the load
18364 // is a direct child, and it's under an intervening TokenFactor. It is
18365 // possible to dig deeper under nested TokenFactors.
18366 if (ChainVal == LdVal)
18367 Ld = cast<LoadSDNode>(St->getChain());
18368 else if (St->getValue().hasOneUse() &&
18369 ChainVal->getOpcode() == ISD::TokenFactor) {
18370 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18371 if (ChainVal->getOperand(i).getNode() == LdVal) {
18372 TokenFactorIndex = i;
18373 Ld = cast<LoadSDNode>(St->getValue());
18375 Ops.push_back(ChainVal->getOperand(i));
18379 if (!Ld || !ISD::isNormalLoad(Ld))
18382 // If this is not the MMX case, i.e. we are just turning i64 load/store
18383 // into f64 load/store, avoid the transformation if there are multiple
18384 // uses of the loaded value.
18385 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18390 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18391 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18393 if (Subtarget->is64Bit() || F64IsLegal) {
18394 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18395 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18396 Ld->getPointerInfo(), Ld->isVolatile(),
18397 Ld->isNonTemporal(), Ld->isInvariant(),
18398 Ld->getAlignment());
18399 SDValue NewChain = NewLd.getValue(1);
18400 if (TokenFactorIndex != -1) {
18401 Ops.push_back(NewChain);
18402 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18405 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18406 St->getPointerInfo(),
18407 St->isVolatile(), St->isNonTemporal(),
18408 St->getAlignment());
18411 // Otherwise, lower to two pairs of 32-bit loads / stores.
18412 SDValue LoAddr = Ld->getBasePtr();
18413 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18414 DAG.getConstant(4, MVT::i32));
18416 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18417 Ld->getPointerInfo(),
18418 Ld->isVolatile(), Ld->isNonTemporal(),
18419 Ld->isInvariant(), Ld->getAlignment());
18420 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18421 Ld->getPointerInfo().getWithOffset(4),
18422 Ld->isVolatile(), Ld->isNonTemporal(),
18424 MinAlign(Ld->getAlignment(), 4));
18426 SDValue NewChain = LoLd.getValue(1);
18427 if (TokenFactorIndex != -1) {
18428 Ops.push_back(LoLd);
18429 Ops.push_back(HiLd);
18430 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18434 LoAddr = St->getBasePtr();
18435 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18436 DAG.getConstant(4, MVT::i32));
18438 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18439 St->getPointerInfo(),
18440 St->isVolatile(), St->isNonTemporal(),
18441 St->getAlignment());
18442 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18443 St->getPointerInfo().getWithOffset(4),
18445 St->isNonTemporal(),
18446 MinAlign(St->getAlignment(), 4));
18447 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18452 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18453 /// and return the operands for the horizontal operation in LHS and RHS. A
18454 /// horizontal operation performs the binary operation on successive elements
18455 /// of its first operand, then on successive elements of its second operand,
18456 /// returning the resulting values in a vector. For example, if
18457 /// A = < float a0, float a1, float a2, float a3 >
18459 /// B = < float b0, float b1, float b2, float b3 >
18460 /// then the result of doing a horizontal operation on A and B is
18461 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18462 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18463 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18464 /// set to A, RHS to B, and the routine returns 'true'.
18465 /// Note that the binary operation should have the property that if one of the
18466 /// operands is UNDEF then the result is UNDEF.
18467 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18468 // Look for the following pattern: if
18469 // A = < float a0, float a1, float a2, float a3 >
18470 // B = < float b0, float b1, float b2, float b3 >
18472 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18473 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18474 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18475 // which is A horizontal-op B.
18477 // At least one of the operands should be a vector shuffle.
18478 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18479 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18482 MVT VT = LHS.getSimpleValueType();
18484 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18485 "Unsupported vector type for horizontal add/sub");
18487 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18488 // operate independently on 128-bit lanes.
18489 unsigned NumElts = VT.getVectorNumElements();
18490 unsigned NumLanes = VT.getSizeInBits()/128;
18491 unsigned NumLaneElts = NumElts / NumLanes;
18492 assert((NumLaneElts % 2 == 0) &&
18493 "Vector type should have an even number of elements in each lane");
18494 unsigned HalfLaneElts = NumLaneElts/2;
18496 // View LHS in the form
18497 // LHS = VECTOR_SHUFFLE A, B, LMask
18498 // If LHS is not a shuffle then pretend it is the shuffle
18499 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18500 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18503 SmallVector<int, 16> LMask(NumElts);
18504 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18505 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18506 A = LHS.getOperand(0);
18507 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18508 B = LHS.getOperand(1);
18509 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18510 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18512 if (LHS.getOpcode() != ISD::UNDEF)
18514 for (unsigned i = 0; i != NumElts; ++i)
18518 // Likewise, view RHS in the form
18519 // RHS = VECTOR_SHUFFLE C, D, RMask
18521 SmallVector<int, 16> RMask(NumElts);
18522 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18523 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18524 C = RHS.getOperand(0);
18525 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18526 D = RHS.getOperand(1);
18527 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18528 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18530 if (RHS.getOpcode() != ISD::UNDEF)
18532 for (unsigned i = 0; i != NumElts; ++i)
18536 // Check that the shuffles are both shuffling the same vectors.
18537 if (!(A == C && B == D) && !(A == D && B == C))
18540 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18541 if (!A.getNode() && !B.getNode())
18544 // If A and B occur in reverse order in RHS, then "swap" them (which means
18545 // rewriting the mask).
18547 CommuteVectorShuffleMask(RMask, NumElts);
18549 // At this point LHS and RHS are equivalent to
18550 // LHS = VECTOR_SHUFFLE A, B, LMask
18551 // RHS = VECTOR_SHUFFLE A, B, RMask
18552 // Check that the masks correspond to performing a horizontal operation.
18553 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18554 for (unsigned i = 0; i != NumLaneElts; ++i) {
18555 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18557 // Ignore any UNDEF components.
18558 if (LIdx < 0 || RIdx < 0 ||
18559 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18560 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18563 // Check that successive elements are being operated on. If not, this is
18564 // not a horizontal operation.
18565 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18566 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18567 if (!(LIdx == Index && RIdx == Index + 1) &&
18568 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18573 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18574 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18578 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18579 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18580 const X86Subtarget *Subtarget) {
18581 EVT VT = N->getValueType(0);
18582 SDValue LHS = N->getOperand(0);
18583 SDValue RHS = N->getOperand(1);
18585 // Try to synthesize horizontal adds from adds of shuffles.
18586 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18587 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18588 isHorizontalBinOp(LHS, RHS, true))
18589 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18593 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18594 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18595 const X86Subtarget *Subtarget) {
18596 EVT VT = N->getValueType(0);
18597 SDValue LHS = N->getOperand(0);
18598 SDValue RHS = N->getOperand(1);
18600 // Try to synthesize horizontal subs from subs of shuffles.
18601 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18602 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18603 isHorizontalBinOp(LHS, RHS, false))
18604 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18608 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18609 /// X86ISD::FXOR nodes.
18610 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18611 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18612 // F[X]OR(0.0, x) -> x
18613 // F[X]OR(x, 0.0) -> x
18614 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18615 if (C->getValueAPF().isPosZero())
18616 return N->getOperand(1);
18617 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18618 if (C->getValueAPF().isPosZero())
18619 return N->getOperand(0);
18623 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18624 /// X86ISD::FMAX nodes.
18625 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18626 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18628 // Only perform optimizations if UnsafeMath is used.
18629 if (!DAG.getTarget().Options.UnsafeFPMath)
18632 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18633 // into FMINC and FMAXC, which are Commutative operations.
18634 unsigned NewOp = 0;
18635 switch (N->getOpcode()) {
18636 default: llvm_unreachable("unknown opcode");
18637 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18638 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18641 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18642 N->getOperand(0), N->getOperand(1));
18645 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18646 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18647 // FAND(0.0, x) -> 0.0
18648 // FAND(x, 0.0) -> 0.0
18649 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18650 if (C->getValueAPF().isPosZero())
18651 return N->getOperand(0);
18652 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18653 if (C->getValueAPF().isPosZero())
18654 return N->getOperand(1);
18658 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18659 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18660 // FANDN(x, 0.0) -> 0.0
18661 // FANDN(0.0, x) -> x
18662 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18663 if (C->getValueAPF().isPosZero())
18664 return N->getOperand(1);
18665 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18666 if (C->getValueAPF().isPosZero())
18667 return N->getOperand(1);
18671 static SDValue PerformBTCombine(SDNode *N,
18673 TargetLowering::DAGCombinerInfo &DCI) {
18674 // BT ignores high bits in the bit index operand.
18675 SDValue Op1 = N->getOperand(1);
18676 if (Op1.hasOneUse()) {
18677 unsigned BitWidth = Op1.getValueSizeInBits();
18678 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18679 APInt KnownZero, KnownOne;
18680 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18681 !DCI.isBeforeLegalizeOps());
18682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18683 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18684 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18685 DCI.CommitTargetLoweringOpt(TLO);
18690 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18691 SDValue Op = N->getOperand(0);
18692 if (Op.getOpcode() == ISD::BITCAST)
18693 Op = Op.getOperand(0);
18694 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18695 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18696 VT.getVectorElementType().getSizeInBits() ==
18697 OpVT.getVectorElementType().getSizeInBits()) {
18698 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18703 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18704 const X86Subtarget *Subtarget) {
18705 EVT VT = N->getValueType(0);
18706 if (!VT.isVector())
18709 SDValue N0 = N->getOperand(0);
18710 SDValue N1 = N->getOperand(1);
18711 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18714 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18715 // both SSE and AVX2 since there is no sign-extended shift right
18716 // operation on a vector with 64-bit elements.
18717 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18718 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18719 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18720 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18721 SDValue N00 = N0.getOperand(0);
18723 // EXTLOAD has a better solution on AVX2,
18724 // it may be replaced with X86ISD::VSEXT node.
18725 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18726 if (!ISD::isNormalLoad(N00.getNode()))
18729 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18730 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18732 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18738 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18739 TargetLowering::DAGCombinerInfo &DCI,
18740 const X86Subtarget *Subtarget) {
18741 if (!DCI.isBeforeLegalizeOps())
18744 if (!Subtarget->hasFp256())
18747 EVT VT = N->getValueType(0);
18748 if (VT.isVector() && VT.getSizeInBits() == 256) {
18749 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18757 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18758 const X86Subtarget* Subtarget) {
18760 EVT VT = N->getValueType(0);
18762 // Let legalize expand this if it isn't a legal type yet.
18763 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18766 EVT ScalarVT = VT.getScalarType();
18767 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18768 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18771 SDValue A = N->getOperand(0);
18772 SDValue B = N->getOperand(1);
18773 SDValue C = N->getOperand(2);
18775 bool NegA = (A.getOpcode() == ISD::FNEG);
18776 bool NegB = (B.getOpcode() == ISD::FNEG);
18777 bool NegC = (C.getOpcode() == ISD::FNEG);
18779 // Negative multiplication when NegA xor NegB
18780 bool NegMul = (NegA != NegB);
18782 A = A.getOperand(0);
18784 B = B.getOperand(0);
18786 C = C.getOperand(0);
18790 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18792 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18794 return DAG.getNode(Opcode, dl, VT, A, B, C);
18797 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18798 TargetLowering::DAGCombinerInfo &DCI,
18799 const X86Subtarget *Subtarget) {
18800 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18801 // (and (i32 x86isd::setcc_carry), 1)
18802 // This eliminates the zext. This transformation is necessary because
18803 // ISD::SETCC is always legalized to i8.
18805 SDValue N0 = N->getOperand(0);
18806 EVT VT = N->getValueType(0);
18808 if (N0.getOpcode() == ISD::AND &&
18810 N0.getOperand(0).hasOneUse()) {
18811 SDValue N00 = N0.getOperand(0);
18812 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18813 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18814 if (!C || C->getZExtValue() != 1)
18816 return DAG.getNode(ISD::AND, dl, VT,
18817 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18818 N00.getOperand(0), N00.getOperand(1)),
18819 DAG.getConstant(1, VT));
18823 if (VT.is256BitVector()) {
18824 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18832 // Optimize x == -y --> x+y == 0
18833 // x != -y --> x+y != 0
18834 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18835 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18836 SDValue LHS = N->getOperand(0);
18837 SDValue RHS = N->getOperand(1);
18839 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18841 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18842 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18843 LHS.getValueType(), RHS, LHS.getOperand(1));
18844 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18845 addV, DAG.getConstant(0, addV.getValueType()), CC);
18847 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18848 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18849 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18850 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18851 RHS.getValueType(), LHS, RHS.getOperand(1));
18852 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18853 addV, DAG.getConstant(0, addV.getValueType()), CC);
18858 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18859 // as "sbb reg,reg", since it can be extended without zext and produces
18860 // an all-ones bit which is more useful than 0/1 in some cases.
18861 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18862 return DAG.getNode(ISD::AND, DL, MVT::i8,
18863 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18864 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18865 DAG.getConstant(1, MVT::i8));
18868 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18869 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18870 TargetLowering::DAGCombinerInfo &DCI,
18871 const X86Subtarget *Subtarget) {
18873 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18874 SDValue EFLAGS = N->getOperand(1);
18876 if (CC == X86::COND_A) {
18877 // Try to convert COND_A into COND_B in an attempt to facilitate
18878 // materializing "setb reg".
18880 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18881 // cannot take an immediate as its first operand.
18883 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18884 EFLAGS.getValueType().isInteger() &&
18885 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18886 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18887 EFLAGS.getNode()->getVTList(),
18888 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18889 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18890 return MaterializeSETB(DL, NewEFLAGS, DAG);
18894 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18895 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18897 if (CC == X86::COND_B)
18898 return MaterializeSETB(DL, EFLAGS, DAG);
18902 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18903 if (Flags.getNode()) {
18904 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18905 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18911 // Optimize branch condition evaluation.
18913 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18914 TargetLowering::DAGCombinerInfo &DCI,
18915 const X86Subtarget *Subtarget) {
18917 SDValue Chain = N->getOperand(0);
18918 SDValue Dest = N->getOperand(1);
18919 SDValue EFLAGS = N->getOperand(3);
18920 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18924 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18925 if (Flags.getNode()) {
18926 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18927 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18934 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18935 const X86TargetLowering *XTLI) {
18936 SDValue Op0 = N->getOperand(0);
18937 EVT InVT = Op0->getValueType(0);
18939 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18940 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18942 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18943 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18944 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18947 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18948 // a 32-bit target where SSE doesn't support i64->FP operations.
18949 if (Op0.getOpcode() == ISD::LOAD) {
18950 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18951 EVT VT = Ld->getValueType(0);
18952 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18953 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18954 !XTLI->getSubtarget()->is64Bit() &&
18956 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18957 Ld->getChain(), Op0, DAG);
18958 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18965 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18966 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18967 X86TargetLowering::DAGCombinerInfo &DCI) {
18968 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18969 // the result is either zero or one (depending on the input carry bit).
18970 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18971 if (X86::isZeroNode(N->getOperand(0)) &&
18972 X86::isZeroNode(N->getOperand(1)) &&
18973 // We don't have a good way to replace an EFLAGS use, so only do this when
18975 SDValue(N, 1).use_empty()) {
18977 EVT VT = N->getValueType(0);
18978 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18979 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18980 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18981 DAG.getConstant(X86::COND_B,MVT::i8),
18983 DAG.getConstant(1, VT));
18984 return DCI.CombineTo(N, Res1, CarryOut);
18990 // fold (add Y, (sete X, 0)) -> adc 0, Y
18991 // (add Y, (setne X, 0)) -> sbb -1, Y
18992 // (sub (sete X, 0), Y) -> sbb 0, Y
18993 // (sub (setne X, 0), Y) -> adc -1, Y
18994 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18997 // Look through ZExts.
18998 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18999 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19002 SDValue SetCC = Ext.getOperand(0);
19003 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19006 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19007 if (CC != X86::COND_E && CC != X86::COND_NE)
19010 SDValue Cmp = SetCC.getOperand(1);
19011 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19012 !X86::isZeroNode(Cmp.getOperand(1)) ||
19013 !Cmp.getOperand(0).getValueType().isInteger())
19016 SDValue CmpOp0 = Cmp.getOperand(0);
19017 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19018 DAG.getConstant(1, CmpOp0.getValueType()));
19020 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19021 if (CC == X86::COND_NE)
19022 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19023 DL, OtherVal.getValueType(), OtherVal,
19024 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19025 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19026 DL, OtherVal.getValueType(), OtherVal,
19027 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19030 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19031 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19032 const X86Subtarget *Subtarget) {
19033 EVT VT = N->getValueType(0);
19034 SDValue Op0 = N->getOperand(0);
19035 SDValue Op1 = N->getOperand(1);
19037 // Try to synthesize horizontal adds from adds of shuffles.
19038 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19039 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19040 isHorizontalBinOp(Op0, Op1, true))
19041 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19043 return OptimizeConditionalInDecrement(N, DAG);
19046 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19047 const X86Subtarget *Subtarget) {
19048 SDValue Op0 = N->getOperand(0);
19049 SDValue Op1 = N->getOperand(1);
19051 // X86 can't encode an immediate LHS of a sub. See if we can push the
19052 // negation into a preceding instruction.
19053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19054 // If the RHS of the sub is a XOR with one use and a constant, invert the
19055 // immediate. Then add one to the LHS of the sub so we can turn
19056 // X-Y -> X+~Y+1, saving one register.
19057 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19058 isa<ConstantSDNode>(Op1.getOperand(1))) {
19059 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19060 EVT VT = Op0.getValueType();
19061 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19063 DAG.getConstant(~XorC, VT));
19064 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19065 DAG.getConstant(C->getAPIntValue()+1, VT));
19069 // Try to synthesize horizontal adds from adds of shuffles.
19070 EVT VT = N->getValueType(0);
19071 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19072 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19073 isHorizontalBinOp(Op0, Op1, true))
19074 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19076 return OptimizeConditionalInDecrement(N, DAG);
19079 /// performVZEXTCombine - Performs build vector combines
19080 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19081 TargetLowering::DAGCombinerInfo &DCI,
19082 const X86Subtarget *Subtarget) {
19083 // (vzext (bitcast (vzext (x)) -> (vzext x)
19084 SDValue In = N->getOperand(0);
19085 while (In.getOpcode() == ISD::BITCAST)
19086 In = In.getOperand(0);
19088 if (In.getOpcode() != X86ISD::VZEXT)
19091 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19095 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19096 DAGCombinerInfo &DCI) const {
19097 SelectionDAG &DAG = DCI.DAG;
19098 switch (N->getOpcode()) {
19100 case ISD::EXTRACT_VECTOR_ELT:
19101 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19103 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19104 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19105 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19106 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19107 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19108 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19111 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19112 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19113 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19114 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19115 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19116 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19117 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19118 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19119 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19121 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19123 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19124 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19125 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19126 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19127 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19128 case ISD::ANY_EXTEND:
19129 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19130 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19131 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19132 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19133 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19134 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19135 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19136 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19137 case X86ISD::SHUFP: // Handle all target specific shuffles
19138 case X86ISD::PALIGNR:
19139 case X86ISD::UNPCKH:
19140 case X86ISD::UNPCKL:
19141 case X86ISD::MOVHLPS:
19142 case X86ISD::MOVLHPS:
19143 case X86ISD::PSHUFD:
19144 case X86ISD::PSHUFHW:
19145 case X86ISD::PSHUFLW:
19146 case X86ISD::MOVSS:
19147 case X86ISD::MOVSD:
19148 case X86ISD::VPERMILP:
19149 case X86ISD::VPERM2X128:
19150 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19151 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19157 /// isTypeDesirableForOp - Return true if the target has native support for
19158 /// the specified value type and it is 'desirable' to use the type for the
19159 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19160 /// instruction encodings are longer and some i16 instructions are slow.
19161 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19162 if (!isTypeLegal(VT))
19164 if (VT != MVT::i16)
19171 case ISD::SIGN_EXTEND:
19172 case ISD::ZERO_EXTEND:
19173 case ISD::ANY_EXTEND:
19186 /// IsDesirableToPromoteOp - This method query the target whether it is
19187 /// beneficial for dag combiner to promote the specified node. If true, it
19188 /// should return the desired promotion type by reference.
19189 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19190 EVT VT = Op.getValueType();
19191 if (VT != MVT::i16)
19194 bool Promote = false;
19195 bool Commute = false;
19196 switch (Op.getOpcode()) {
19199 LoadSDNode *LD = cast<LoadSDNode>(Op);
19200 // If the non-extending load has a single use and it's not live out, then it
19201 // might be folded.
19202 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19203 Op.hasOneUse()*/) {
19204 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19205 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19206 // The only case where we'd want to promote LOAD (rather then it being
19207 // promoted as an operand is when it's only use is liveout.
19208 if (UI->getOpcode() != ISD::CopyToReg)
19215 case ISD::SIGN_EXTEND:
19216 case ISD::ZERO_EXTEND:
19217 case ISD::ANY_EXTEND:
19222 SDValue N0 = Op.getOperand(0);
19223 // Look out for (store (shl (load), x)).
19224 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19237 SDValue N0 = Op.getOperand(0);
19238 SDValue N1 = Op.getOperand(1);
19239 if (!Commute && MayFoldLoad(N1))
19241 // Avoid disabling potential load folding opportunities.
19242 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19244 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19254 //===----------------------------------------------------------------------===//
19255 // X86 Inline Assembly Support
19256 //===----------------------------------------------------------------------===//
19259 // Helper to match a string separated by whitespace.
19260 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19261 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19263 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19264 StringRef piece(*args[i]);
19265 if (!s.startswith(piece)) // Check if the piece matches.
19268 s = s.substr(piece.size());
19269 StringRef::size_type pos = s.find_first_not_of(" \t");
19270 if (pos == 0) // We matched a prefix.
19278 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19281 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19283 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19284 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19285 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19286 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19288 if (AsmPieces.size() == 3)
19290 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19297 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19298 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19300 std::string AsmStr = IA->getAsmString();
19302 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19303 if (!Ty || Ty->getBitWidth() % 16 != 0)
19306 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19307 SmallVector<StringRef, 4> AsmPieces;
19308 SplitString(AsmStr, AsmPieces, ";\n");
19310 switch (AsmPieces.size()) {
19311 default: return false;
19313 // FIXME: this should verify that we are targeting a 486 or better. If not,
19314 // we will turn this bswap into something that will be lowered to logical
19315 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19316 // lower so don't worry about this.
19318 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19319 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19320 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19321 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19322 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19323 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19324 // No need to check constraints, nothing other than the equivalent of
19325 // "=r,0" would be valid here.
19326 return IntrinsicLowering::LowerToByteSwap(CI);
19329 // rorw $$8, ${0:w} --> llvm.bswap.i16
19330 if (CI->getType()->isIntegerTy(16) &&
19331 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19332 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19333 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19335 const std::string &ConstraintsStr = IA->getConstraintString();
19336 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19337 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19338 if (clobbersFlagRegisters(AsmPieces))
19339 return IntrinsicLowering::LowerToByteSwap(CI);
19343 if (CI->getType()->isIntegerTy(32) &&
19344 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19345 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19346 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19347 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19349 const std::string &ConstraintsStr = IA->getConstraintString();
19350 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19351 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19352 if (clobbersFlagRegisters(AsmPieces))
19353 return IntrinsicLowering::LowerToByteSwap(CI);
19356 if (CI->getType()->isIntegerTy(64)) {
19357 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19358 if (Constraints.size() >= 2 &&
19359 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19360 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19361 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19362 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19363 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19364 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19365 return IntrinsicLowering::LowerToByteSwap(CI);
19373 /// getConstraintType - Given a constraint letter, return the type of
19374 /// constraint it is for this target.
19375 X86TargetLowering::ConstraintType
19376 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19377 if (Constraint.size() == 1) {
19378 switch (Constraint[0]) {
19389 return C_RegisterClass;
19413 return TargetLowering::getConstraintType(Constraint);
19416 /// Examine constraint type and operand type and determine a weight value.
19417 /// This object must already have been set up with the operand type
19418 /// and the current alternative constraint selected.
19419 TargetLowering::ConstraintWeight
19420 X86TargetLowering::getSingleConstraintMatchWeight(
19421 AsmOperandInfo &info, const char *constraint) const {
19422 ConstraintWeight weight = CW_Invalid;
19423 Value *CallOperandVal = info.CallOperandVal;
19424 // If we don't have a value, we can't do a match,
19425 // but allow it at the lowest weight.
19426 if (CallOperandVal == NULL)
19428 Type *type = CallOperandVal->getType();
19429 // Look at the constraint type.
19430 switch (*constraint) {
19432 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19443 if (CallOperandVal->getType()->isIntegerTy())
19444 weight = CW_SpecificReg;
19449 if (type->isFloatingPointTy())
19450 weight = CW_SpecificReg;
19453 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19454 weight = CW_SpecificReg;
19458 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19459 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19460 weight = CW_Register;
19463 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19464 if (C->getZExtValue() <= 31)
19465 weight = CW_Constant;
19469 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19470 if (C->getZExtValue() <= 63)
19471 weight = CW_Constant;
19475 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19476 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19477 weight = CW_Constant;
19481 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19482 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19483 weight = CW_Constant;
19487 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19488 if (C->getZExtValue() <= 3)
19489 weight = CW_Constant;
19493 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19494 if (C->getZExtValue() <= 0xff)
19495 weight = CW_Constant;
19500 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19501 weight = CW_Constant;
19505 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19506 if ((C->getSExtValue() >= -0x80000000LL) &&
19507 (C->getSExtValue() <= 0x7fffffffLL))
19508 weight = CW_Constant;
19512 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19513 if (C->getZExtValue() <= 0xffffffff)
19514 weight = CW_Constant;
19521 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19522 /// with another that has more specific requirements based on the type of the
19523 /// corresponding operand.
19524 const char *X86TargetLowering::
19525 LowerXConstraint(EVT ConstraintVT) const {
19526 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19527 // 'f' like normal targets.
19528 if (ConstraintVT.isFloatingPoint()) {
19529 if (Subtarget->hasSSE2())
19531 if (Subtarget->hasSSE1())
19535 return TargetLowering::LowerXConstraint(ConstraintVT);
19538 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19539 /// vector. If it is invalid, don't add anything to Ops.
19540 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19541 std::string &Constraint,
19542 std::vector<SDValue>&Ops,
19543 SelectionDAG &DAG) const {
19544 SDValue Result(0, 0);
19546 // Only support length 1 constraints for now.
19547 if (Constraint.length() > 1) return;
19549 char ConstraintLetter = Constraint[0];
19550 switch (ConstraintLetter) {
19553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19554 if (C->getZExtValue() <= 31) {
19555 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19561 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19562 if (C->getZExtValue() <= 63) {
19563 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19569 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19570 if (isInt<8>(C->getSExtValue())) {
19571 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19577 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19578 if (C->getZExtValue() <= 255) {
19579 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19585 // 32-bit signed value
19586 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19587 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19588 C->getSExtValue())) {
19589 // Widen to 64 bits here to get it sign extended.
19590 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19593 // FIXME gcc accepts some relocatable values here too, but only in certain
19594 // memory models; it's complicated.
19599 // 32-bit unsigned value
19600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19601 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19602 C->getZExtValue())) {
19603 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19607 // FIXME gcc accepts some relocatable values here too, but only in certain
19608 // memory models; it's complicated.
19612 // Literal immediates are always ok.
19613 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19614 // Widen to 64 bits here to get it sign extended.
19615 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19619 // In any sort of PIC mode addresses need to be computed at runtime by
19620 // adding in a register or some sort of table lookup. These can't
19621 // be used as immediates.
19622 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19625 // If we are in non-pic codegen mode, we allow the address of a global (with
19626 // an optional displacement) to be used with 'i'.
19627 GlobalAddressSDNode *GA = 0;
19628 int64_t Offset = 0;
19630 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19632 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19633 Offset += GA->getOffset();
19635 } else if (Op.getOpcode() == ISD::ADD) {
19636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19637 Offset += C->getZExtValue();
19638 Op = Op.getOperand(0);
19641 } else if (Op.getOpcode() == ISD::SUB) {
19642 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19643 Offset += -C->getZExtValue();
19644 Op = Op.getOperand(0);
19649 // Otherwise, this isn't something we can handle, reject it.
19653 const GlobalValue *GV = GA->getGlobal();
19654 // If we require an extra load to get this address, as in PIC mode, we
19655 // can't accept it.
19656 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19657 getTargetMachine())))
19660 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19661 GA->getValueType(0), Offset);
19666 if (Result.getNode()) {
19667 Ops.push_back(Result);
19670 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19673 std::pair<unsigned, const TargetRegisterClass*>
19674 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19676 // First, see if this is a constraint that directly corresponds to an LLVM
19678 if (Constraint.size() == 1) {
19679 // GCC Constraint Letters
19680 switch (Constraint[0]) {
19682 // TODO: Slight differences here in allocation order and leaving
19683 // RIP in the class. Do they matter any more here than they do
19684 // in the normal allocation?
19685 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19686 if (Subtarget->is64Bit()) {
19687 if (VT == MVT::i32 || VT == MVT::f32)
19688 return std::make_pair(0U, &X86::GR32RegClass);
19689 if (VT == MVT::i16)
19690 return std::make_pair(0U, &X86::GR16RegClass);
19691 if (VT == MVT::i8 || VT == MVT::i1)
19692 return std::make_pair(0U, &X86::GR8RegClass);
19693 if (VT == MVT::i64 || VT == MVT::f64)
19694 return std::make_pair(0U, &X86::GR64RegClass);
19697 // 32-bit fallthrough
19698 case 'Q': // Q_REGS
19699 if (VT == MVT::i32 || VT == MVT::f32)
19700 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19701 if (VT == MVT::i16)
19702 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19703 if (VT == MVT::i8 || VT == MVT::i1)
19704 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19705 if (VT == MVT::i64)
19706 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19708 case 'r': // GENERAL_REGS
19709 case 'l': // INDEX_REGS
19710 if (VT == MVT::i8 || VT == MVT::i1)
19711 return std::make_pair(0U, &X86::GR8RegClass);
19712 if (VT == MVT::i16)
19713 return std::make_pair(0U, &X86::GR16RegClass);
19714 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19715 return std::make_pair(0U, &X86::GR32RegClass);
19716 return std::make_pair(0U, &X86::GR64RegClass);
19717 case 'R': // LEGACY_REGS
19718 if (VT == MVT::i8 || VT == MVT::i1)
19719 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19720 if (VT == MVT::i16)
19721 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19722 if (VT == MVT::i32 || !Subtarget->is64Bit())
19723 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19724 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19725 case 'f': // FP Stack registers.
19726 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19727 // value to the correct fpstack register class.
19728 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19729 return std::make_pair(0U, &X86::RFP32RegClass);
19730 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19731 return std::make_pair(0U, &X86::RFP64RegClass);
19732 return std::make_pair(0U, &X86::RFP80RegClass);
19733 case 'y': // MMX_REGS if MMX allowed.
19734 if (!Subtarget->hasMMX()) break;
19735 return std::make_pair(0U, &X86::VR64RegClass);
19736 case 'Y': // SSE_REGS if SSE2 allowed
19737 if (!Subtarget->hasSSE2()) break;
19739 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19740 if (!Subtarget->hasSSE1()) break;
19742 switch (VT.SimpleTy) {
19744 // Scalar SSE types.
19747 return std::make_pair(0U, &X86::FR32RegClass);
19750 return std::make_pair(0U, &X86::FR64RegClass);
19758 return std::make_pair(0U, &X86::VR128RegClass);
19766 return std::make_pair(0U, &X86::VR256RegClass);
19771 return std::make_pair(0U, &X86::VR512RegClass);
19777 // Use the default implementation in TargetLowering to convert the register
19778 // constraint into a member of a register class.
19779 std::pair<unsigned, const TargetRegisterClass*> Res;
19780 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19782 // Not found as a standard register?
19783 if (Res.second == 0) {
19784 // Map st(0) -> st(7) -> ST0
19785 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19786 tolower(Constraint[1]) == 's' &&
19787 tolower(Constraint[2]) == 't' &&
19788 Constraint[3] == '(' &&
19789 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19790 Constraint[5] == ')' &&
19791 Constraint[6] == '}') {
19793 Res.first = X86::ST0+Constraint[4]-'0';
19794 Res.second = &X86::RFP80RegClass;
19798 // GCC allows "st(0)" to be called just plain "st".
19799 if (StringRef("{st}").equals_lower(Constraint)) {
19800 Res.first = X86::ST0;
19801 Res.second = &X86::RFP80RegClass;
19806 if (StringRef("{flags}").equals_lower(Constraint)) {
19807 Res.first = X86::EFLAGS;
19808 Res.second = &X86::CCRRegClass;
19812 // 'A' means EAX + EDX.
19813 if (Constraint == "A") {
19814 Res.first = X86::EAX;
19815 Res.second = &X86::GR32_ADRegClass;
19821 // Otherwise, check to see if this is a register class of the wrong value
19822 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19823 // turn into {ax},{dx}.
19824 if (Res.second->hasType(VT))
19825 return Res; // Correct type already, nothing to do.
19827 // All of the single-register GCC register classes map their values onto
19828 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19829 // really want an 8-bit or 32-bit register, map to the appropriate register
19830 // class and return the appropriate register.
19831 if (Res.second == &X86::GR16RegClass) {
19832 if (VT == MVT::i8 || VT == MVT::i1) {
19833 unsigned DestReg = 0;
19834 switch (Res.first) {
19836 case X86::AX: DestReg = X86::AL; break;
19837 case X86::DX: DestReg = X86::DL; break;
19838 case X86::CX: DestReg = X86::CL; break;
19839 case X86::BX: DestReg = X86::BL; break;
19842 Res.first = DestReg;
19843 Res.second = &X86::GR8RegClass;
19845 } else if (VT == MVT::i32 || VT == MVT::f32) {
19846 unsigned DestReg = 0;
19847 switch (Res.first) {
19849 case X86::AX: DestReg = X86::EAX; break;
19850 case X86::DX: DestReg = X86::EDX; break;
19851 case X86::CX: DestReg = X86::ECX; break;
19852 case X86::BX: DestReg = X86::EBX; break;
19853 case X86::SI: DestReg = X86::ESI; break;
19854 case X86::DI: DestReg = X86::EDI; break;
19855 case X86::BP: DestReg = X86::EBP; break;
19856 case X86::SP: DestReg = X86::ESP; break;
19859 Res.first = DestReg;
19860 Res.second = &X86::GR32RegClass;
19862 } else if (VT == MVT::i64 || VT == MVT::f64) {
19863 unsigned DestReg = 0;
19864 switch (Res.first) {
19866 case X86::AX: DestReg = X86::RAX; break;
19867 case X86::DX: DestReg = X86::RDX; break;
19868 case X86::CX: DestReg = X86::RCX; break;
19869 case X86::BX: DestReg = X86::RBX; break;
19870 case X86::SI: DestReg = X86::RSI; break;
19871 case X86::DI: DestReg = X86::RDI; break;
19872 case X86::BP: DestReg = X86::RBP; break;
19873 case X86::SP: DestReg = X86::RSP; break;
19876 Res.first = DestReg;
19877 Res.second = &X86::GR64RegClass;
19880 } else if (Res.second == &X86::FR32RegClass ||
19881 Res.second == &X86::FR64RegClass ||
19882 Res.second == &X86::VR128RegClass ||
19883 Res.second == &X86::VR256RegClass ||
19884 Res.second == &X86::FR32XRegClass ||
19885 Res.second == &X86::FR64XRegClass ||
19886 Res.second == &X86::VR128XRegClass ||
19887 Res.second == &X86::VR256XRegClass ||
19888 Res.second == &X86::VR512RegClass) {
19889 // Handle references to XMM physical registers that got mapped into the
19890 // wrong class. This can happen with constraints like {xmm0} where the
19891 // target independent register mapper will just pick the first match it can
19892 // find, ignoring the required type.
19894 if (VT == MVT::f32 || VT == MVT::i32)
19895 Res.second = &X86::FR32RegClass;
19896 else if (VT == MVT::f64 || VT == MVT::i64)
19897 Res.second = &X86::FR64RegClass;
19898 else if (X86::VR128RegClass.hasType(VT))
19899 Res.second = &X86::VR128RegClass;
19900 else if (X86::VR256RegClass.hasType(VT))
19901 Res.second = &X86::VR256RegClass;
19902 else if (X86::VR512RegClass.hasType(VT))
19903 Res.second = &X86::VR512RegClass;