1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
122 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
123 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
125 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
128 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
130 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
132 // SSE has no i16 to fp conversion, only i32
133 if (X86ScalarSSEf32) {
134 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
135 // f32 and f64 cases are Legal, f80 case is not
136 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
138 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
142 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
143 // are Legal, f80 is custom lowered.
144 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
145 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
147 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
149 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
152 if (X86ScalarSSEf32) {
153 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
154 // f32 and f64 cases are Legal, f80 case is not
155 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
157 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
161 // Handle FP_TO_UINT by promoting the destination to a larger signed
163 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
164 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
165 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
167 if (Subtarget->is64Bit()) {
168 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
169 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
171 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
172 // Expand FP_TO_UINT into a select.
173 // FIXME: We would like to use a Custom expander here eventually to do
174 // the optimal thing for SSE vs. the default expansion in the legalizer.
175 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
177 // With SSE3 we can use fisttpll to convert to a signed i64.
178 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
181 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
182 if (!X86ScalarSSEf64) {
183 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
184 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
187 // Scalar integer divide and remainder are lowered to use operations that
188 // produce two results, to match the available instructions. This exposes
189 // the two-result form to trivial CSE, which is able to combine x/y and x%y
190 // into a single instruction.
192 // Scalar integer multiply-high is also lowered to use two-result
193 // operations, to match the available instructions. However, plain multiply
194 // (low) operations are left as Legal, as there are single-result
195 // instructions for this in x86. Using the two-result multiply instructions
196 // when both high and low results are needed must be arranged by dagcombine.
197 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
198 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
199 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
200 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
201 setOperationAction(ISD::SREM , MVT::i8 , Expand);
202 setOperationAction(ISD::UREM , MVT::i8 , Expand);
203 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
204 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
205 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
206 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
207 setOperationAction(ISD::SREM , MVT::i16 , Expand);
208 setOperationAction(ISD::UREM , MVT::i16 , Expand);
209 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
210 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
211 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
212 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
213 setOperationAction(ISD::SREM , MVT::i32 , Expand);
214 setOperationAction(ISD::UREM , MVT::i32 , Expand);
215 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
216 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
217 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
218 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
219 setOperationAction(ISD::SREM , MVT::i64 , Expand);
220 setOperationAction(ISD::UREM , MVT::i64 , Expand);
222 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
223 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
224 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
225 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
226 if (Subtarget->is64Bit())
227 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
231 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
232 setOperationAction(ISD::FREM , MVT::f32 , Expand);
233 setOperationAction(ISD::FREM , MVT::f64 , Expand);
234 setOperationAction(ISD::FREM , MVT::f80 , Expand);
235 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
237 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
238 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
239 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
240 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
241 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
242 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
243 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
244 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
245 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
246 if (Subtarget->is64Bit()) {
247 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
248 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
249 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
252 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
253 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
255 // These should be promoted to a larger select which is supported.
256 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
257 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
258 // X86 wants to expand cmov itself.
259 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
260 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
261 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
262 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
263 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
264 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
265 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
267 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
268 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
269 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
270 if (Subtarget->is64Bit()) {
271 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
272 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
274 // X86 ret instruction may pop stack.
275 setOperationAction(ISD::RET , MVT::Other, Custom);
276 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
279 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
280 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
281 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
282 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
283 if (Subtarget->is64Bit())
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
286 if (Subtarget->is64Bit()) {
287 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
288 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
289 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
290 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
292 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
293 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
294 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
295 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
296 if (Subtarget->is64Bit()) {
297 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
298 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
299 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
302 if (Subtarget->hasSSE1())
303 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
305 if (!Subtarget->hasSSE2())
306 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
308 // Expand certain atomics
309 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
314 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
319 if (!Subtarget->is64Bit()) {
320 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
321 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
329 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
330 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
331 // FIXME - use subtarget debug flags
332 if (!Subtarget->isTargetDarwin() &&
333 !Subtarget->isTargetELF() &&
334 !Subtarget->isTargetCygMing()) {
335 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
336 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
339 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
340 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
341 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
342 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
343 if (Subtarget->is64Bit()) {
344 setExceptionPointerRegister(X86::RAX);
345 setExceptionSelectorRegister(X86::RDX);
347 setExceptionPointerRegister(X86::EAX);
348 setExceptionSelectorRegister(X86::EDX);
350 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
353 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
355 setOperationAction(ISD::TRAP, MVT::Other, Legal);
357 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
358 setOperationAction(ISD::VASTART , MVT::Other, Custom);
359 setOperationAction(ISD::VAEND , MVT::Other, Expand);
360 if (Subtarget->is64Bit()) {
361 setOperationAction(ISD::VAARG , MVT::Other, Custom);
362 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
364 setOperationAction(ISD::VAARG , MVT::Other, Expand);
365 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
368 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
369 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
372 if (Subtarget->isTargetCygMing())
373 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
375 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
377 if (X86ScalarSSEf64) {
378 // f32 and f64 use SSE.
379 // Set up the FP register classes.
380 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
381 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
383 // Use ANDPD to simulate FABS.
384 setOperationAction(ISD::FABS , MVT::f64, Custom);
385 setOperationAction(ISD::FABS , MVT::f32, Custom);
387 // Use XORP to simulate FNEG.
388 setOperationAction(ISD::FNEG , MVT::f64, Custom);
389 setOperationAction(ISD::FNEG , MVT::f32, Custom);
391 // Use ANDPD and ORPD to simulate FCOPYSIGN.
392 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
393 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
395 // We don't support sin/cos/fmod
396 setOperationAction(ISD::FSIN , MVT::f64, Expand);
397 setOperationAction(ISD::FCOS , MVT::f64, Expand);
398 setOperationAction(ISD::FSIN , MVT::f32, Expand);
399 setOperationAction(ISD::FCOS , MVT::f32, Expand);
401 // Expand FP immediates into loads from the stack, except for the special
403 addLegalFPImmediate(APFloat(+0.0)); // xorpd
404 addLegalFPImmediate(APFloat(+0.0f)); // xorps
406 // Floating truncations from f80 and extensions to f80 go through memory.
407 // If optimizing, we lie about this though and handle it in
408 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
410 setConvertAction(MVT::f32, MVT::f80, Expand);
411 setConvertAction(MVT::f64, MVT::f80, Expand);
412 setConvertAction(MVT::f80, MVT::f32, Expand);
413 setConvertAction(MVT::f80, MVT::f64, Expand);
415 } else if (X86ScalarSSEf32) {
416 // Use SSE for f32, x87 for f64.
417 // Set up the FP register classes.
418 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
419 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
421 // Use ANDPS to simulate FABS.
422 setOperationAction(ISD::FABS , MVT::f32, Custom);
424 // Use XORP to simulate FNEG.
425 setOperationAction(ISD::FNEG , MVT::f32, Custom);
427 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
429 // Use ANDPS and ORPS to simulate FCOPYSIGN.
430 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
431 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
433 // We don't support sin/cos/fmod
434 setOperationAction(ISD::FSIN , MVT::f32, Expand);
435 setOperationAction(ISD::FCOS , MVT::f32, Expand);
437 // Special cases we handle for FP constants.
438 addLegalFPImmediate(APFloat(+0.0f)); // xorps
439 addLegalFPImmediate(APFloat(+0.0)); // FLD0
440 addLegalFPImmediate(APFloat(+1.0)); // FLD1
441 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
442 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
444 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
445 // this though and handle it in InstructionSelectPreprocess so that
446 // dagcombine2 can hack on these.
448 setConvertAction(MVT::f32, MVT::f64, Expand);
449 setConvertAction(MVT::f32, MVT::f80, Expand);
450 setConvertAction(MVT::f80, MVT::f32, Expand);
451 setConvertAction(MVT::f64, MVT::f32, Expand);
452 // And x87->x87 truncations also.
453 setConvertAction(MVT::f80, MVT::f64, Expand);
457 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
458 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
461 // f32 and f64 in x87.
462 // Set up the FP register classes.
463 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
464 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
466 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
467 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
471 // Floating truncations go through memory. If optimizing, we lie about
472 // this though and handle it in InstructionSelectPreprocess so that
473 // dagcombine2 can hack on these.
475 setConvertAction(MVT::f80, MVT::f32, Expand);
476 setConvertAction(MVT::f64, MVT::f32, Expand);
477 setConvertAction(MVT::f80, MVT::f64, Expand);
481 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
482 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
484 addLegalFPImmediate(APFloat(+0.0)); // FLD0
485 addLegalFPImmediate(APFloat(+1.0)); // FLD1
486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
488 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
489 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
490 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
491 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
494 // Long double always uses X87.
495 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
496 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
500 APFloat TmpFlt(+0.0);
501 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
503 addLegalFPImmediate(TmpFlt); // FLD0
505 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
506 APFloat TmpFlt2(+1.0);
507 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
509 addLegalFPImmediate(TmpFlt2); // FLD1
510 TmpFlt2.changeSign();
511 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
515 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
516 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
519 // Always use a library call for pow.
520 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
521 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
522 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
524 setOperationAction(ISD::FLOG, MVT::f80, Expand);
525 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
526 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
527 setOperationAction(ISD::FEXP, MVT::f80, Expand);
528 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
530 // First set operation action for all vector types to either promote
531 // (for widening) or expand (for scalarization). Then we will selectively
532 // turn on ones that can be effectively codegen'd.
533 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
534 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
535 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
550 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
580 if (!DisableMMX && Subtarget->hasMMX()) {
581 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
582 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
585 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
587 // FIXME: add MMX packed arithmetics
589 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
590 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
591 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
592 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
594 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
595 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
596 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
597 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
599 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
600 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
602 setOperationAction(ISD::AND, MVT::v8i8, Promote);
603 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
604 setOperationAction(ISD::AND, MVT::v4i16, Promote);
605 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
606 setOperationAction(ISD::AND, MVT::v2i32, Promote);
607 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
608 setOperationAction(ISD::AND, MVT::v1i64, Legal);
610 setOperationAction(ISD::OR, MVT::v8i8, Promote);
611 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
612 setOperationAction(ISD::OR, MVT::v4i16, Promote);
613 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
614 setOperationAction(ISD::OR, MVT::v2i32, Promote);
615 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
616 setOperationAction(ISD::OR, MVT::v1i64, Legal);
618 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
619 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
620 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
621 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
622 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
623 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
624 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
626 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
627 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
628 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
629 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
630 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
631 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
632 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
633 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
634 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
636 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
640 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
654 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
655 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
656 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
657 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
658 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
659 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
662 if (Subtarget->hasSSE1()) {
663 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
665 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
666 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
667 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
668 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
669 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
670 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
671 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
675 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
676 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
679 if (Subtarget->hasSSE2()) {
680 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
681 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
682 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
683 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
684 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
686 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
687 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
688 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
689 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
690 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
691 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
692 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
693 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
694 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
695 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
696 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
697 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
698 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
699 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
700 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
701 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
703 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
704 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
705 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
708 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
710 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
714 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
715 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
716 MVT VT = (MVT::SimpleValueType)i;
717 // Do not attempt to custom lower non-power-of-2 vectors
718 if (!isPowerOf2_32(VT.getVectorNumElements()))
720 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
721 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
724 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
725 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
726 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
727 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
728 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
729 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
730 if (Subtarget->is64Bit()) {
731 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
732 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
735 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
736 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
737 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
738 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
739 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
740 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
741 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
742 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
743 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
744 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
745 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
746 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
749 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
751 // Custom lower v2i64 and v2f64 selects.
752 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
753 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
754 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
755 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
759 if (Subtarget->hasSSE41()) {
760 // FIXME: Do we need to handle scalar-to-vector here?
761 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
763 // i8 and i16 vectors are custom , because the source register and source
764 // source memory operand types are not the same width. f32 vectors are
765 // custom since the immediate controlling the insert encodes additional
767 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
777 if (Subtarget->is64Bit()) {
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
783 if (Subtarget->hasSSE42()) {
784 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
787 // We want to custom lower some of our intrinsics.
788 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
790 // Add/Sub/Mul with overflow operations are custom lowered.
791 setOperationAction(ISD::SADDO, MVT::i32, Custom);
792 setOperationAction(ISD::SADDO, MVT::i64, Custom);
793 setOperationAction(ISD::UADDO, MVT::i32, Custom);
794 setOperationAction(ISD::UADDO, MVT::i64, Custom);
795 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
796 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
797 setOperationAction(ISD::USUBO, MVT::i32, Custom);
798 setOperationAction(ISD::USUBO, MVT::i64, Custom);
799 setOperationAction(ISD::SMULO, MVT::i32, Custom);
800 setOperationAction(ISD::SMULO, MVT::i64, Custom);
801 setOperationAction(ISD::UMULO, MVT::i32, Custom);
802 setOperationAction(ISD::UMULO, MVT::i64, Custom);
804 // We have target-specific dag combine patterns for the following nodes:
805 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
806 setTargetDAGCombine(ISD::BUILD_VECTOR);
807 setTargetDAGCombine(ISD::SELECT);
808 setTargetDAGCombine(ISD::STORE);
810 computeRegisterProperties();
812 // FIXME: These should be based on subtarget info. Plus, the values should
813 // be smaller when we are in optimizing for size mode.
814 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
815 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
816 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
817 allowUnalignedMemoryAccesses = true; // x86 supports it!
818 setPrefLoopAlignment(16);
822 MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
827 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
828 /// the desired ByVal argument alignment.
829 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
832 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
833 if (VTy->getBitWidth() == 128)
835 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
836 unsigned EltAlign = 0;
837 getMaxByValAlign(ATy->getElementType(), EltAlign);
838 if (EltAlign > MaxAlign)
840 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
841 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
842 unsigned EltAlign = 0;
843 getMaxByValAlign(STy->getElementType(i), EltAlign);
844 if (EltAlign > MaxAlign)
853 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
854 /// function arguments in the caller parameter area. For X86, aggregates
855 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
856 /// are at 4-byte boundaries.
857 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
858 if (Subtarget->is64Bit()) {
859 // Max of 8 and alignment of type.
860 unsigned TyAlign = TD->getABITypeAlignment(Ty);
867 if (Subtarget->hasSSE1())
868 getMaxByValAlign(Ty, Align);
872 /// getOptimalMemOpType - Returns the target specific optimal type for load
873 /// and store operations as a result of memset, memcpy, and memmove
874 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
877 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
878 bool isSrcConst, bool isSrcStr) const {
879 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
880 // linux. This is because the stack realignment code can't handle certain
881 // cases like PR2962. This should be removed when PR2962 is fixed.
882 if (Subtarget->getStackAlignment() >= 16) {
883 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
885 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
888 if (Subtarget->is64Bit() && Size >= 8)
894 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
896 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
897 SelectionDAG &DAG) const {
898 if (usesGlobalOffsetTable())
899 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
900 if (!Subtarget->isPICStyleRIPRel())
901 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
905 //===----------------------------------------------------------------------===//
906 // Return Value Calling Convention Implementation
907 //===----------------------------------------------------------------------===//
909 #include "X86GenCallingConv.inc"
911 /// LowerRET - Lower an ISD::RET node.
912 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
913 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
915 SmallVector<CCValAssign, 16> RVLocs;
916 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
917 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
918 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
919 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
921 // If this is the first return lowered for this function, add the regs to the
922 // liveout set for the function.
923 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
924 for (unsigned i = 0; i != RVLocs.size(); ++i)
925 if (RVLocs[i].isRegLoc())
926 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
928 SDValue Chain = Op.getOperand(0);
930 // Handle tail call return.
931 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
932 if (Chain.getOpcode() == X86ISD::TAILCALL) {
933 SDValue TailCall = Chain;
934 SDValue TargetAddress = TailCall.getOperand(1);
935 SDValue StackAdjustment = TailCall.getOperand(2);
936 assert(((TargetAddress.getOpcode() == ISD::Register &&
937 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
938 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
939 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
940 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
941 "Expecting an global address, external symbol, or register");
942 assert(StackAdjustment.getOpcode() == ISD::Constant &&
943 "Expecting a const value");
945 SmallVector<SDValue,8> Operands;
946 Operands.push_back(Chain.getOperand(0));
947 Operands.push_back(TargetAddress);
948 Operands.push_back(StackAdjustment);
949 // Copy registers used by the call. Last operand is a flag so it is not
951 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
952 Operands.push_back(Chain.getOperand(i));
954 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
961 SmallVector<SDValue, 6> RetOps;
962 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
963 // Operand #1 = Bytes To Pop
964 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
966 // Copy the result values into the output registers.
967 for (unsigned i = 0; i != RVLocs.size(); ++i) {
968 CCValAssign &VA = RVLocs[i];
969 assert(VA.isRegLoc() && "Can only return in registers!");
970 SDValue ValToCopy = Op.getOperand(i*2+1);
972 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
973 // the RET instruction and handled by the FP Stackifier.
974 if (RVLocs[i].getLocReg() == X86::ST0 ||
975 RVLocs[i].getLocReg() == X86::ST1) {
976 // If this is a copy from an xmm register to ST(0), use an FPExtend to
977 // change the value to the FP stack register class.
978 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
979 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
980 RetOps.push_back(ValToCopy);
981 // Don't emit a copytoreg.
985 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
986 Flag = Chain.getValue(1);
989 // The x86-64 ABI for returning structs by value requires that we copy
990 // the sret argument into %rax for the return. We saved the argument into
991 // a virtual register in the entry block, so now we copy the value out
993 if (Subtarget->is64Bit() &&
994 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
995 MachineFunction &MF = DAG.getMachineFunction();
996 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
997 unsigned Reg = FuncInfo->getSRetReturnReg();
999 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1000 FuncInfo->setSRetReturnReg(Reg);
1002 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
1004 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
1005 Flag = Chain.getValue(1);
1008 RetOps[0] = Chain; // Update chain.
1010 // Add the flag if we have it.
1012 RetOps.push_back(Flag);
1014 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
1018 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1019 /// appropriate copies out of appropriate physical registers. This assumes that
1020 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1021 /// being lowered. The returns a SDNode with the same number of values as the
1023 SDNode *X86TargetLowering::
1024 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1025 unsigned CallingConv, SelectionDAG &DAG) {
1027 // Assign locations to each value returned by this call.
1028 SmallVector<CCValAssign, 16> RVLocs;
1029 bool isVarArg = TheCall->isVarArg();
1030 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1031 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1033 SmallVector<SDValue, 8> ResultVals;
1035 // Copy all of the result registers out of their specified physreg.
1036 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1037 MVT CopyVT = RVLocs[i].getValVT();
1039 // If this is a call to a function that returns an fp value on the floating
1040 // point stack, but where we prefer to use the value in xmm registers, copy
1041 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1042 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1043 RVLocs[i].getLocReg() == X86::ST1) &&
1044 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1048 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1049 CopyVT, InFlag).getValue(1);
1050 SDValue Val = Chain.getValue(0);
1051 InFlag = Chain.getValue(2);
1053 if (CopyVT != RVLocs[i].getValVT()) {
1054 // Round the F80 the right size, which also moves to the appropriate xmm
1056 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1057 // This truncation won't change the value.
1058 DAG.getIntPtrConstant(1));
1061 ResultVals.push_back(Val);
1064 // Merge everything together with a MERGE_VALUES node.
1065 ResultVals.push_back(Chain);
1066 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0],
1067 ResultVals.size()).getNode();
1071 //===----------------------------------------------------------------------===//
1072 // C & StdCall & Fast Calling Convention implementation
1073 //===----------------------------------------------------------------------===//
1074 // StdCall calling convention seems to be standard for many Windows' API
1075 // routines and around. It differs from C calling convention just a little:
1076 // callee should clean up the stack, not caller. Symbols should be also
1077 // decorated in some fancy way :) It doesn't support any vector arguments.
1078 // For info on fast calling convention see Fast Calling Convention (tail call)
1079 // implementation LowerX86_32FastCCCallTo.
1081 /// AddLiveIn - This helper function adds the specified physical register to the
1082 /// MachineFunction as a live in value. It also creates a corresponding virtual
1083 /// register for it.
1084 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1085 const TargetRegisterClass *RC) {
1086 assert(RC->contains(PReg) && "Not the correct regclass!");
1087 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1088 MF.getRegInfo().addLiveIn(PReg, VReg);
1092 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1094 static bool CallIsStructReturn(CallSDNode *TheCall) {
1095 unsigned NumOps = TheCall->getNumArgs();
1099 return TheCall->getArgFlags(0).isSRet();
1102 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1103 /// return semantics.
1104 static bool ArgsAreStructReturn(SDValue Op) {
1105 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1109 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1112 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1113 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1115 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1119 switch (CallingConv) {
1122 case CallingConv::X86_StdCall:
1123 return !Subtarget->is64Bit();
1124 case CallingConv::X86_FastCall:
1125 return !Subtarget->is64Bit();
1126 case CallingConv::Fast:
1127 return PerformTailCallOpt;
1131 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1132 /// given CallingConvention value.
1133 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1134 if (Subtarget->is64Bit()) {
1135 if (Subtarget->isTargetWin64())
1136 return CC_X86_Win64_C;
1137 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1138 return CC_X86_64_TailCall;
1143 if (CC == CallingConv::X86_FastCall)
1144 return CC_X86_32_FastCall;
1145 else if (CC == CallingConv::Fast)
1146 return CC_X86_32_FastCC;
1151 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1152 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1154 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1155 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1156 if (CC == CallingConv::X86_FastCall)
1158 else if (CC == CallingConv::X86_StdCall)
1164 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1165 /// in a register before calling.
1166 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1167 return !IsTailCall && !Is64Bit &&
1168 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1169 Subtarget->isPICStyleGOT();
1172 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1173 /// address to be loaded in a register.
1175 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1176 return !Is64Bit && IsTailCall &&
1177 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1178 Subtarget->isPICStyleGOT();
1181 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1182 /// by "Src" to address "Dst" with size and alignment information specified by
1183 /// the specific parameter attribute. The copy will be passed as a byval
1184 /// function parameter.
1186 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1187 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1188 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1189 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1190 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1193 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1194 const CCValAssign &VA,
1195 MachineFrameInfo *MFI,
1197 SDValue Root, unsigned i) {
1198 // Create the nodes corresponding to a load from this parameter slot.
1199 ISD::ArgFlagsTy Flags =
1200 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1201 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1202 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1204 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1205 // changed with more analysis.
1206 // In case of tail call optimization mark all arguments mutable. Since they
1207 // could be overwritten by lowering of arguments in case of a tail call.
1208 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1209 VA.getLocMemOffset(), isImmutable);
1210 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1211 if (Flags.isByVal())
1213 return DAG.getLoad(VA.getValVT(), Root, FIN,
1214 PseudoSourceValue::getFixedStack(FI), 0);
1218 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1219 MachineFunction &MF = DAG.getMachineFunction();
1220 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1222 const Function* Fn = MF.getFunction();
1223 if (Fn->hasExternalLinkage() &&
1224 Subtarget->isTargetCygMing() &&
1225 Fn->getName() == "main")
1226 FuncInfo->setForceFramePointer(true);
1228 // Decorate the function name.
1229 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1231 MachineFrameInfo *MFI = MF.getFrameInfo();
1232 SDValue Root = Op.getOperand(0);
1233 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1234 unsigned CC = MF.getFunction()->getCallingConv();
1235 bool Is64Bit = Subtarget->is64Bit();
1236 bool IsWin64 = Subtarget->isTargetWin64();
1238 assert(!(isVarArg && CC == CallingConv::Fast) &&
1239 "Var args not supported with calling convention fastcc");
1241 // Assign locations to all of the incoming arguments.
1242 SmallVector<CCValAssign, 16> ArgLocs;
1243 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1244 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1246 SmallVector<SDValue, 8> ArgValues;
1247 unsigned LastVal = ~0U;
1248 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1249 CCValAssign &VA = ArgLocs[i];
1250 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1252 assert(VA.getValNo() != LastVal &&
1253 "Don't support value assigned to multiple locs yet");
1254 LastVal = VA.getValNo();
1256 if (VA.isRegLoc()) {
1257 MVT RegVT = VA.getLocVT();
1258 TargetRegisterClass *RC;
1259 if (RegVT == MVT::i32)
1260 RC = X86::GR32RegisterClass;
1261 else if (Is64Bit && RegVT == MVT::i64)
1262 RC = X86::GR64RegisterClass;
1263 else if (RegVT == MVT::f32)
1264 RC = X86::FR32RegisterClass;
1265 else if (RegVT == MVT::f64)
1266 RC = X86::FR64RegisterClass;
1267 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1268 RC = X86::VR128RegisterClass;
1269 else if (RegVT.isVector()) {
1270 assert(RegVT.getSizeInBits() == 64);
1272 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1274 // Darwin calling convention passes MMX values in either GPRs or
1275 // XMMs in x86-64. Other targets pass them in memory.
1276 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1277 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1280 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1285 assert(0 && "Unknown argument type!");
1288 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1289 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1291 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1292 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1294 if (VA.getLocInfo() == CCValAssign::SExt)
1295 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1296 DAG.getValueType(VA.getValVT()));
1297 else if (VA.getLocInfo() == CCValAssign::ZExt)
1298 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1299 DAG.getValueType(VA.getValVT()));
1301 if (VA.getLocInfo() != CCValAssign::Full)
1302 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1304 // Handle MMX values passed in GPRs.
1305 if (Is64Bit && RegVT != VA.getLocVT()) {
1306 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1307 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1308 else if (RC == X86::VR128RegisterClass) {
1309 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1310 DAG.getConstant(0, MVT::i64));
1311 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1315 ArgValues.push_back(ArgValue);
1317 assert(VA.isMemLoc());
1318 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1322 // The x86-64 ABI for returning structs by value requires that we copy
1323 // the sret argument into %rax for the return. Save the argument into
1324 // a virtual register so that we can access it from the return points.
1325 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1326 MachineFunction &MF = DAG.getMachineFunction();
1327 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1328 unsigned Reg = FuncInfo->getSRetReturnReg();
1330 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1331 FuncInfo->setSRetReturnReg(Reg);
1333 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1334 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1337 unsigned StackSize = CCInfo.getNextStackOffset();
1338 // align stack specially for tail calls
1339 if (PerformTailCallOpt && CC == CallingConv::Fast)
1340 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1342 // If the function takes variable number of arguments, make a frame index for
1343 // the start of the first vararg value... for expansion of llvm.va_start.
1345 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1346 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1349 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1351 // FIXME: We should really autogenerate these arrays
1352 static const unsigned GPR64ArgRegsWin64[] = {
1353 X86::RCX, X86::RDX, X86::R8, X86::R9
1355 static const unsigned XMMArgRegsWin64[] = {
1356 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1358 static const unsigned GPR64ArgRegs64Bit[] = {
1359 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1361 static const unsigned XMMArgRegs64Bit[] = {
1362 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1363 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1365 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1368 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1369 GPR64ArgRegs = GPR64ArgRegsWin64;
1370 XMMArgRegs = XMMArgRegsWin64;
1372 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1373 GPR64ArgRegs = GPR64ArgRegs64Bit;
1374 XMMArgRegs = XMMArgRegs64Bit;
1376 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1378 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1381 // For X86-64, if there are vararg parameters that are passed via
1382 // registers, then we must store them to their spots on the stack so they
1383 // may be loaded by deferencing the result of va_next.
1384 VarArgsGPOffset = NumIntRegs * 8;
1385 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1386 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1387 TotalNumXMMRegs * 16, 16);
1389 // Store the integer parameter registers.
1390 SmallVector<SDValue, 8> MemOps;
1391 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1392 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1393 DAG.getIntPtrConstant(VarArgsGPOffset));
1394 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1395 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1396 X86::GR64RegisterClass);
1397 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1399 DAG.getStore(Val.getValue(1), Val, FIN,
1400 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1401 MemOps.push_back(Store);
1402 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1403 DAG.getIntPtrConstant(8));
1406 // Now store the XMM (fp + vector) parameter registers.
1407 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1408 DAG.getIntPtrConstant(VarArgsFPOffset));
1409 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1410 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1411 X86::VR128RegisterClass);
1412 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1414 DAG.getStore(Val.getValue(1), Val, FIN,
1415 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1416 MemOps.push_back(Store);
1417 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1418 DAG.getIntPtrConstant(16));
1420 if (!MemOps.empty())
1421 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1422 &MemOps[0], MemOps.size());
1426 ArgValues.push_back(Root);
1428 // Some CCs need callee pop.
1429 if (IsCalleePop(isVarArg, CC)) {
1430 BytesToPopOnReturn = StackSize; // Callee pops everything.
1431 BytesCallerReserves = 0;
1433 BytesToPopOnReturn = 0; // Callee pops nothing.
1434 // If this is an sret function, the return should pop the hidden pointer.
1435 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1436 BytesToPopOnReturn = 4;
1437 BytesCallerReserves = StackSize;
1441 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1442 if (CC == CallingConv::X86_FastCall)
1443 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1446 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1448 // Return the new list of results.
1449 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
1450 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1454 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1455 const SDValue &StackPtr,
1456 const CCValAssign &VA,
1458 SDValue Arg, ISD::ArgFlagsTy Flags) {
1459 unsigned LocMemOffset = VA.getLocMemOffset();
1460 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1461 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1462 if (Flags.isByVal()) {
1463 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1465 return DAG.getStore(Chain, Arg, PtrOff,
1466 PseudoSourceValue::getStack(), LocMemOffset);
1469 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1470 /// optimization is performed and it is required.
1472 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1473 SDValue &OutRetAddr,
1478 if (!IsTailCall || FPDiff==0) return Chain;
1480 // Adjust the Return address stack slot.
1481 MVT VT = getPointerTy();
1482 OutRetAddr = getReturnAddressFrameIndex(DAG);
1483 // Load the "old" Return address.
1484 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1485 return SDValue(OutRetAddr.getNode(), 1);
1488 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1489 /// optimization is performed and it is required (FPDiff!=0).
1491 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1492 SDValue Chain, SDValue RetAddrFrIdx,
1493 bool Is64Bit, int FPDiff) {
1494 // Store the return address to the appropriate stack slot.
1495 if (!FPDiff) return Chain;
1496 // Calculate the new stack slot for the return address.
1497 int SlotSize = Is64Bit ? 8 : 4;
1498 int NewReturnAddrFI =
1499 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1500 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1501 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1502 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1503 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1507 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1508 MachineFunction &MF = DAG.getMachineFunction();
1509 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1510 SDValue Chain = TheCall->getChain();
1511 unsigned CC = TheCall->getCallingConv();
1512 bool isVarArg = TheCall->isVarArg();
1513 bool IsTailCall = TheCall->isTailCall() &&
1514 CC == CallingConv::Fast && PerformTailCallOpt;
1515 SDValue Callee = TheCall->getCallee();
1516 bool Is64Bit = Subtarget->is64Bit();
1517 bool IsStructRet = CallIsStructReturn(TheCall);
1519 assert(!(isVarArg && CC == CallingConv::Fast) &&
1520 "Var args not supported with calling convention fastcc");
1522 // Analyze operands of the call, assigning locations to each operand.
1523 SmallVector<CCValAssign, 16> ArgLocs;
1524 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1525 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1527 // Get a count of how many bytes are to be pushed on the stack.
1528 unsigned NumBytes = CCInfo.getNextStackOffset();
1529 if (PerformTailCallOpt && CC == CallingConv::Fast)
1530 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1534 // Lower arguments at fp - stackoffset + fpdiff.
1535 unsigned NumBytesCallerPushed =
1536 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1537 FPDiff = NumBytesCallerPushed - NumBytes;
1539 // Set the delta of movement of the returnaddr stackslot.
1540 // But only set if delta is greater than previous delta.
1541 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1542 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1545 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1547 SDValue RetAddrFrIdx;
1548 // Load return adress for tail calls.
1549 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1552 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1553 SmallVector<SDValue, 8> MemOpChains;
1556 // Walk the register/memloc assignments, inserting copies/loads. In the case
1557 // of tail call optimization arguments are handle later.
1558 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1559 CCValAssign &VA = ArgLocs[i];
1560 SDValue Arg = TheCall->getArg(i);
1561 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1562 bool isByVal = Flags.isByVal();
1564 // Promote the value if needed.
1565 switch (VA.getLocInfo()) {
1566 default: assert(0 && "Unknown loc info!");
1567 case CCValAssign::Full: break;
1568 case CCValAssign::SExt:
1569 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1571 case CCValAssign::ZExt:
1572 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1574 case CCValAssign::AExt:
1575 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1579 if (VA.isRegLoc()) {
1581 MVT RegVT = VA.getLocVT();
1582 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1583 switch (VA.getLocReg()) {
1586 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1588 // Special case: passing MMX values in GPR registers.
1589 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1592 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1593 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1594 // Special case: passing MMX values in XMM registers.
1595 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1596 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1597 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1598 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1599 getMOVLMask(2, DAG));
1604 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1606 if (!IsTailCall || (IsTailCall && isByVal)) {
1607 assert(VA.isMemLoc());
1608 if (StackPtr.getNode() == 0)
1609 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1611 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1612 Chain, Arg, Flags));
1617 if (!MemOpChains.empty())
1618 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1619 &MemOpChains[0], MemOpChains.size());
1621 // Build a sequence of copy-to-reg nodes chained together with token chain
1622 // and flag operands which copy the outgoing args into registers.
1624 // Tail call byval lowering might overwrite argument registers so in case of
1625 // tail call optimization the copies to registers are lowered later.
1627 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1628 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1630 InFlag = Chain.getValue(1);
1633 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1635 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1636 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1637 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1639 InFlag = Chain.getValue(1);
1641 // If we are tail calling and generating PIC/GOT style code load the address
1642 // of the callee into ecx. The value in ecx is used as target of the tail
1643 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1644 // calls on PIC/GOT architectures. Normally we would just put the address of
1645 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1646 // restored (since ebx is callee saved) before jumping to the target@PLT.
1647 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1648 // Note: The actual moving to ecx is done further down.
1649 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1650 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1651 !G->getGlobal()->hasProtectedVisibility())
1652 Callee = LowerGlobalAddress(Callee, DAG);
1653 else if (isa<ExternalSymbolSDNode>(Callee))
1654 Callee = LowerExternalSymbol(Callee,DAG);
1657 if (Is64Bit && isVarArg) {
1658 // From AMD64 ABI document:
1659 // For calls that may call functions that use varargs or stdargs
1660 // (prototype-less calls or calls to functions containing ellipsis (...) in
1661 // the declaration) %al is used as hidden argument to specify the number
1662 // of SSE registers used. The contents of %al do not need to match exactly
1663 // the number of registers, but must be an ubound on the number of SSE
1664 // registers used and is in the range 0 - 8 inclusive.
1666 // FIXME: Verify this on Win64
1667 // Count the number of XMM registers allocated.
1668 static const unsigned XMMArgRegs[] = {
1669 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1670 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1672 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1674 Chain = DAG.getCopyToReg(Chain, X86::AL,
1675 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1676 InFlag = Chain.getValue(1);
1680 // For tail calls lower the arguments to the 'real' stack slot.
1682 SmallVector<SDValue, 8> MemOpChains2;
1685 // Do not flag preceeding copytoreg stuff together with the following stuff.
1687 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1688 CCValAssign &VA = ArgLocs[i];
1689 if (!VA.isRegLoc()) {
1690 assert(VA.isMemLoc());
1691 SDValue Arg = TheCall->getArg(i);
1692 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1693 // Create frame index.
1694 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1695 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1696 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1697 FIN = DAG.getFrameIndex(FI, getPointerTy());
1699 if (Flags.isByVal()) {
1700 // Copy relative to framepointer.
1701 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1702 if (StackPtr.getNode() == 0)
1703 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1704 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1706 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1709 // Store relative to framepointer.
1710 MemOpChains2.push_back(
1711 DAG.getStore(Chain, Arg, FIN,
1712 PseudoSourceValue::getFixedStack(FI), 0));
1717 if (!MemOpChains2.empty())
1718 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1719 &MemOpChains2[0], MemOpChains2.size());
1721 // Copy arguments to their registers.
1722 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1723 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1725 InFlag = Chain.getValue(1);
1729 // Store the return address to the appropriate stack slot.
1730 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1734 // If the callee is a GlobalAddress node (quite common, every direct call is)
1735 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1736 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1737 // We should use extra load for direct calls to dllimported functions in
1739 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1740 getTargetMachine(), true))
1741 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1743 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1744 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1745 } else if (IsTailCall) {
1746 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1748 Chain = DAG.getCopyToReg(Chain,
1749 DAG.getRegister(Opc, getPointerTy()),
1751 Callee = DAG.getRegister(Opc, getPointerTy());
1752 // Add register as live out.
1753 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1756 // Returns a chain & a flag for retval copy to use.
1757 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1758 SmallVector<SDValue, 8> Ops;
1761 Ops.push_back(Chain);
1762 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
1763 Ops.push_back(DAG.getIntPtrConstant(0, true));
1764 if (InFlag.getNode())
1765 Ops.push_back(InFlag);
1766 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1767 InFlag = Chain.getValue(1);
1769 // Returns a chain & a flag for retval copy to use.
1770 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1774 Ops.push_back(Chain);
1775 Ops.push_back(Callee);
1778 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1780 // Add argument registers to the end of the list so that they are known live
1782 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1783 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1784 RegsToPass[i].second.getValueType()));
1786 // Add an implicit use GOT pointer in EBX.
1787 if (!IsTailCall && !Is64Bit &&
1788 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1789 Subtarget->isPICStyleGOT())
1790 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1792 // Add an implicit use of AL for x86 vararg functions.
1793 if (Is64Bit && isVarArg)
1794 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1796 if (InFlag.getNode())
1797 Ops.push_back(InFlag);
1800 assert(InFlag.getNode() &&
1801 "Flag must be set. Depend on flag being set in LowerRET");
1802 Chain = DAG.getNode(X86ISD::TAILCALL,
1803 TheCall->getVTList(), &Ops[0], Ops.size());
1805 return SDValue(Chain.getNode(), Op.getResNo());
1808 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1809 InFlag = Chain.getValue(1);
1811 // Create the CALLSEQ_END node.
1812 unsigned NumBytesForCalleeToPush;
1813 if (IsCalleePop(isVarArg, CC))
1814 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1815 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1816 // If this is is a call to a struct-return function, the callee
1817 // pops the hidden struct pointer, so we have to push it back.
1818 // This is common for Darwin/X86, Linux & Mingw32 targets.
1819 NumBytesForCalleeToPush = 4;
1821 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1823 // Returns a flag for retval copy to use.
1824 Chain = DAG.getCALLSEQ_END(Chain,
1825 DAG.getIntPtrConstant(NumBytes, true),
1826 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1829 InFlag = Chain.getValue(1);
1831 // Handle result values, copying them out of physregs into vregs that we
1833 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1838 //===----------------------------------------------------------------------===//
1839 // Fast Calling Convention (tail call) implementation
1840 //===----------------------------------------------------------------------===//
1842 // Like std call, callee cleans arguments, convention except that ECX is
1843 // reserved for storing the tail called function address. Only 2 registers are
1844 // free for argument passing (inreg). Tail call optimization is performed
1846 // * tailcallopt is enabled
1847 // * caller/callee are fastcc
1848 // On X86_64 architecture with GOT-style position independent code only local
1849 // (within module) calls are supported at the moment.
1850 // To keep the stack aligned according to platform abi the function
1851 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1852 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1853 // If a tail called function callee has more arguments than the caller the
1854 // caller needs to make sure that there is room to move the RETADDR to. This is
1855 // achieved by reserving an area the size of the argument delta right after the
1856 // original REtADDR, but before the saved framepointer or the spilled registers
1857 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1869 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1870 /// for a 16 byte align requirement.
1871 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1872 SelectionDAG& DAG) {
1873 MachineFunction &MF = DAG.getMachineFunction();
1874 const TargetMachine &TM = MF.getTarget();
1875 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1876 unsigned StackAlignment = TFI.getStackAlignment();
1877 uint64_t AlignMask = StackAlignment - 1;
1878 int64_t Offset = StackSize;
1879 uint64_t SlotSize = TD->getPointerSize();
1880 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1881 // Number smaller than 12 so just add the difference.
1882 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1884 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1885 Offset = ((~AlignMask) & Offset) + StackAlignment +
1886 (StackAlignment-SlotSize);
1891 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1892 /// following the call is a return. A function is eligible if caller/callee
1893 /// calling conventions match, currently only fastcc supports tail calls, and
1894 /// the function CALL is immediatly followed by a RET.
1895 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1897 SelectionDAG& DAG) const {
1898 if (!PerformTailCallOpt)
1901 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1902 MachineFunction &MF = DAG.getMachineFunction();
1903 unsigned CallerCC = MF.getFunction()->getCallingConv();
1904 unsigned CalleeCC= TheCall->getCallingConv();
1905 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1906 SDValue Callee = TheCall->getCallee();
1907 // On x86/32Bit PIC/GOT tail calls are supported.
1908 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1909 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1912 // Can only do local tail calls (in same module, hidden or protected) on
1913 // x86_64 PIC/GOT at the moment.
1914 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1915 return G->getGlobal()->hasHiddenVisibility()
1916 || G->getGlobal()->hasProtectedVisibility();
1924 X86TargetLowering::createFastISel(MachineFunction &mf,
1925 MachineModuleInfo *mmo,
1926 DenseMap<const Value *, unsigned> &vm,
1927 DenseMap<const BasicBlock *,
1928 MachineBasicBlock *> &bm,
1929 DenseMap<const AllocaInst *, int> &am
1931 , SmallSet<Instruction*, 8> &cil
1934 return X86::createFastISel(mf, mmo, vm, bm, am
1942 //===----------------------------------------------------------------------===//
1943 // Other Lowering Hooks
1944 //===----------------------------------------------------------------------===//
1947 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1948 MachineFunction &MF = DAG.getMachineFunction();
1949 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1950 int ReturnAddrIndex = FuncInfo->getRAIndex();
1951 uint64_t SlotSize = TD->getPointerSize();
1953 if (ReturnAddrIndex == 0) {
1954 // Set up a frame object for the return address.
1955 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1956 FuncInfo->setRAIndex(ReturnAddrIndex);
1959 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1963 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1964 /// specific condition code. It returns a false if it cannot do a direct
1965 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1967 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1968 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
1969 SelectionDAG &DAG) {
1970 X86CC = X86::COND_INVALID;
1972 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1973 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1974 // X > -1 -> X == 0, jump !sign.
1975 RHS = DAG.getConstant(0, RHS.getValueType());
1976 X86CC = X86::COND_NS;
1978 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1979 // X < 0 -> X == 0, jump on sign.
1980 X86CC = X86::COND_S;
1982 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1984 RHS = DAG.getConstant(0, RHS.getValueType());
1985 X86CC = X86::COND_LE;
1990 switch (SetCCOpcode) {
1991 default: assert(0 && "Invalid integer condition!");
1992 case ISD::SETEQ: X86CC = X86::COND_E; break;
1993 case ISD::SETGT: X86CC = X86::COND_G; break;
1994 case ISD::SETGE: X86CC = X86::COND_GE; break;
1995 case ISD::SETLT: X86CC = X86::COND_L; break;
1996 case ISD::SETLE: X86CC = X86::COND_LE; break;
1997 case ISD::SETNE: X86CC = X86::COND_NE; break;
1998 case ISD::SETULT: X86CC = X86::COND_B; break;
1999 case ISD::SETUGT: X86CC = X86::COND_A; break;
2000 case ISD::SETULE: X86CC = X86::COND_BE; break;
2001 case ISD::SETUGE: X86CC = X86::COND_AE; break;
2006 // First determine if it is required or is profitable to flip the operands.
2008 // If LHS is a foldable load, but RHS is not, flip the condition.
2009 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2010 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2011 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2012 std::swap(LHS, RHS);
2015 switch (SetCCOpcode) {
2021 std::swap(LHS, RHS);
2025 // On a floating point condition, the flags are set as follows:
2027 // 0 | 0 | 0 | X > Y
2028 // 0 | 0 | 1 | X < Y
2029 // 1 | 0 | 0 | X == Y
2030 // 1 | 1 | 1 | unordered
2031 switch (SetCCOpcode) {
2032 default: return false;
2034 case ISD::SETEQ: X86CC = X86::COND_E; return true;
2035 case ISD::SETOLT: // flipped
2037 case ISD::SETGT: X86CC = X86::COND_A; return true;
2038 case ISD::SETOLE: // flipped
2040 case ISD::SETGE: X86CC = X86::COND_AE; return true;
2041 case ISD::SETUGT: // flipped
2043 case ISD::SETLT: X86CC = X86::COND_B; return true;
2044 case ISD::SETUGE: // flipped
2046 case ISD::SETLE: X86CC = X86::COND_BE; return true;
2048 case ISD::SETNE: X86CC = X86::COND_NE; return true;
2049 case ISD::SETUO: X86CC = X86::COND_P; return true;
2050 case ISD::SETO: X86CC = X86::COND_NP; return true;
2054 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2055 /// code. Current x86 isa includes the following FP cmov instructions:
2056 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2057 static bool hasFPCMov(unsigned X86CC) {
2073 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2074 /// true if Op is undef or if its value falls within the specified range (L, H].
2075 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2076 if (Op.getOpcode() == ISD::UNDEF)
2079 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2080 return (Val >= Low && Val < Hi);
2083 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2084 /// true if Op is undef or if its value equal to the specified value.
2085 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2086 if (Op.getOpcode() == ISD::UNDEF)
2088 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2091 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2092 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2093 bool X86::isPSHUFDMask(SDNode *N) {
2094 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2096 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2099 // Check if the value doesn't reference the second vector.
2100 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2101 SDValue Arg = N->getOperand(i);
2102 if (Arg.getOpcode() == ISD::UNDEF) continue;
2103 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2104 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2111 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2112 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2113 bool X86::isPSHUFHWMask(SDNode *N) {
2114 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2116 if (N->getNumOperands() != 8)
2119 // Lower quadword copied in order.
2120 for (unsigned i = 0; i != 4; ++i) {
2121 SDValue Arg = N->getOperand(i);
2122 if (Arg.getOpcode() == ISD::UNDEF) continue;
2123 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2124 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2128 // Upper quadword shuffled.
2129 for (unsigned i = 4; i != 8; ++i) {
2130 SDValue Arg = N->getOperand(i);
2131 if (Arg.getOpcode() == ISD::UNDEF) continue;
2132 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2133 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2134 if (Val < 4 || Val > 7)
2141 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2142 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2143 bool X86::isPSHUFLWMask(SDNode *N) {
2144 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2146 if (N->getNumOperands() != 8)
2149 // Upper quadword copied in order.
2150 for (unsigned i = 4; i != 8; ++i)
2151 if (!isUndefOrEqual(N->getOperand(i), i))
2154 // Lower quadword shuffled.
2155 for (unsigned i = 0; i != 4; ++i)
2156 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2162 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2163 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2164 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2165 if (NumElems != 2 && NumElems != 4) return false;
2167 unsigned Half = NumElems / 2;
2168 for (unsigned i = 0; i < Half; ++i)
2169 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2171 for (unsigned i = Half; i < NumElems; ++i)
2172 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2178 bool X86::isSHUFPMask(SDNode *N) {
2179 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2180 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2183 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2184 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2185 /// half elements to come from vector 1 (which would equal the dest.) and
2186 /// the upper half to come from vector 2.
2187 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2188 if (NumOps != 2 && NumOps != 4) return false;
2190 unsigned Half = NumOps / 2;
2191 for (unsigned i = 0; i < Half; ++i)
2192 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2194 for (unsigned i = Half; i < NumOps; ++i)
2195 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2200 static bool isCommutedSHUFP(SDNode *N) {
2201 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2202 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2205 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2206 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2207 bool X86::isMOVHLPSMask(SDNode *N) {
2208 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2210 if (N->getNumOperands() != 4)
2213 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2214 return isUndefOrEqual(N->getOperand(0), 6) &&
2215 isUndefOrEqual(N->getOperand(1), 7) &&
2216 isUndefOrEqual(N->getOperand(2), 2) &&
2217 isUndefOrEqual(N->getOperand(3), 3);
2220 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2221 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2223 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2224 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2226 if (N->getNumOperands() != 4)
2229 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2230 return isUndefOrEqual(N->getOperand(0), 2) &&
2231 isUndefOrEqual(N->getOperand(1), 3) &&
2232 isUndefOrEqual(N->getOperand(2), 2) &&
2233 isUndefOrEqual(N->getOperand(3), 3);
2236 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2237 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2238 bool X86::isMOVLPMask(SDNode *N) {
2239 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2241 unsigned NumElems = N->getNumOperands();
2242 if (NumElems != 2 && NumElems != 4)
2245 for (unsigned i = 0; i < NumElems/2; ++i)
2246 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2249 for (unsigned i = NumElems/2; i < NumElems; ++i)
2250 if (!isUndefOrEqual(N->getOperand(i), i))
2256 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2257 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2259 bool X86::isMOVHPMask(SDNode *N) {
2260 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2262 unsigned NumElems = N->getNumOperands();
2263 if (NumElems != 2 && NumElems != 4)
2266 for (unsigned i = 0; i < NumElems/2; ++i)
2267 if (!isUndefOrEqual(N->getOperand(i), i))
2270 for (unsigned i = 0; i < NumElems/2; ++i) {
2271 SDValue Arg = N->getOperand(i + NumElems/2);
2272 if (!isUndefOrEqual(Arg, i + NumElems))
2279 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2280 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2281 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2282 bool V2IsSplat = false) {
2283 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2286 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2287 SDValue BitI = Elts[i];
2288 SDValue BitI1 = Elts[i+1];
2289 if (!isUndefOrEqual(BitI, j))
2292 if (isUndefOrEqual(BitI1, NumElts))
2295 if (!isUndefOrEqual(BitI1, j + NumElts))
2303 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2304 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2305 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2308 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2309 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2310 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2311 bool V2IsSplat = false) {
2312 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2315 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2316 SDValue BitI = Elts[i];
2317 SDValue BitI1 = Elts[i+1];
2318 if (!isUndefOrEqual(BitI, j + NumElts/2))
2321 if (isUndefOrEqual(BitI1, NumElts))
2324 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2332 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2333 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2334 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2337 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2338 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2340 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2341 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2343 unsigned NumElems = N->getNumOperands();
2344 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2347 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2348 SDValue BitI = N->getOperand(i);
2349 SDValue BitI1 = N->getOperand(i+1);
2351 if (!isUndefOrEqual(BitI, j))
2353 if (!isUndefOrEqual(BitI1, j))
2360 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2361 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2363 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2364 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2366 unsigned NumElems = N->getNumOperands();
2367 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2370 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2371 SDValue BitI = N->getOperand(i);
2372 SDValue BitI1 = N->getOperand(i + 1);
2374 if (!isUndefOrEqual(BitI, j))
2376 if (!isUndefOrEqual(BitI1, j))
2383 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2384 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2385 /// MOVSD, and MOVD, i.e. setting the lowest element.
2386 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2387 if (NumElts != 2 && NumElts != 4)
2390 if (!isUndefOrEqual(Elts[0], NumElts))
2393 for (unsigned i = 1; i < NumElts; ++i) {
2394 if (!isUndefOrEqual(Elts[i], i))
2401 bool X86::isMOVLMask(SDNode *N) {
2402 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2403 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2406 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2407 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2408 /// element of vector 2 and the other elements to come from vector 1 in order.
2409 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2410 bool V2IsSplat = false,
2411 bool V2IsUndef = false) {
2412 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2415 if (!isUndefOrEqual(Ops[0], 0))
2418 for (unsigned i = 1; i < NumOps; ++i) {
2419 SDValue Arg = Ops[i];
2420 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2421 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2422 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2429 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2430 bool V2IsUndef = false) {
2431 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2432 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2433 V2IsSplat, V2IsUndef);
2436 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2437 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2438 bool X86::isMOVSHDUPMask(SDNode *N) {
2439 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2441 if (N->getNumOperands() != 4)
2444 // Expect 1, 1, 3, 3
2445 for (unsigned i = 0; i < 2; ++i) {
2446 SDValue Arg = N->getOperand(i);
2447 if (Arg.getOpcode() == ISD::UNDEF) continue;
2448 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2449 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2450 if (Val != 1) return false;
2454 for (unsigned i = 2; i < 4; ++i) {
2455 SDValue Arg = N->getOperand(i);
2456 if (Arg.getOpcode() == ISD::UNDEF) continue;
2457 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2458 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2459 if (Val != 3) return false;
2463 // Don't use movshdup if it can be done with a shufps.
2467 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2468 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2469 bool X86::isMOVSLDUPMask(SDNode *N) {
2470 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2472 if (N->getNumOperands() != 4)
2475 // Expect 0, 0, 2, 2
2476 for (unsigned i = 0; i < 2; ++i) {
2477 SDValue Arg = N->getOperand(i);
2478 if (Arg.getOpcode() == ISD::UNDEF) continue;
2479 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2480 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2481 if (Val != 0) return false;
2485 for (unsigned i = 2; i < 4; ++i) {
2486 SDValue Arg = N->getOperand(i);
2487 if (Arg.getOpcode() == ISD::UNDEF) continue;
2488 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2489 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2490 if (Val != 2) return false;
2494 // Don't use movshdup if it can be done with a shufps.
2498 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2499 /// specifies a identity operation on the LHS or RHS.
2500 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2501 unsigned NumElems = N->getNumOperands();
2502 for (unsigned i = 0; i < NumElems; ++i)
2503 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2508 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2509 /// a splat of a single element.
2510 static bool isSplatMask(SDNode *N) {
2511 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2513 // This is a splat operation if each element of the permute is the same, and
2514 // if the value doesn't reference the second vector.
2515 unsigned NumElems = N->getNumOperands();
2516 SDValue ElementBase;
2518 for (; i != NumElems; ++i) {
2519 SDValue Elt = N->getOperand(i);
2520 if (isa<ConstantSDNode>(Elt)) {
2526 if (!ElementBase.getNode())
2529 for (; i != NumElems; ++i) {
2530 SDValue Arg = N->getOperand(i);
2531 if (Arg.getOpcode() == ISD::UNDEF) continue;
2532 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2533 if (Arg != ElementBase) return false;
2536 // Make sure it is a splat of the first vector operand.
2537 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2540 /// getSplatMaskEltNo - Given a splat mask, return the index to the element
2541 /// we want to splat.
2542 static SDValue getSplatMaskEltNo(SDNode *N) {
2543 assert(isSplatMask(N) && "Not a splat mask");
2544 unsigned NumElems = N->getNumOperands();
2545 SDValue ElementBase;
2547 for (; i != NumElems; ++i) {
2548 SDValue Elt = N->getOperand(i);
2549 if (isa<ConstantSDNode>(Elt))
2552 assert(0 && " No splat value found!");
2557 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2558 /// a splat of a single element and it's a 2 or 4 element mask.
2559 bool X86::isSplatMask(SDNode *N) {
2560 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2562 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2563 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2565 return ::isSplatMask(N);
2568 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2569 /// specifies a splat of zero element.
2570 bool X86::isSplatLoMask(SDNode *N) {
2571 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2573 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2574 if (!isUndefOrEqual(N->getOperand(i), 0))
2579 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2580 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2581 bool X86::isMOVDDUPMask(SDNode *N) {
2582 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2584 unsigned e = N->getNumOperands() / 2;
2585 for (unsigned i = 0; i < e; ++i)
2586 if (!isUndefOrEqual(N->getOperand(i), i))
2588 for (unsigned i = 0; i < e; ++i)
2589 if (!isUndefOrEqual(N->getOperand(e+i), i))
2594 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2595 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2597 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2598 unsigned NumOperands = N->getNumOperands();
2599 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2601 for (unsigned i = 0; i < NumOperands; ++i) {
2603 SDValue Arg = N->getOperand(NumOperands-i-1);
2604 if (Arg.getOpcode() != ISD::UNDEF)
2605 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2606 if (Val >= NumOperands) Val -= NumOperands;
2608 if (i != NumOperands - 1)
2615 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2616 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2618 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2620 // 8 nodes, but we only care about the last 4.
2621 for (unsigned i = 7; i >= 4; --i) {
2623 SDValue Arg = N->getOperand(i);
2624 if (Arg.getOpcode() != ISD::UNDEF)
2625 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2634 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2635 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2637 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2639 // 8 nodes, but we only care about the first 4.
2640 for (int i = 3; i >= 0; --i) {
2642 SDValue Arg = N->getOperand(i);
2643 if (Arg.getOpcode() != ISD::UNDEF)
2644 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2653 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2654 /// specifies a 8 element shuffle that can be broken into a pair of
2655 /// PSHUFHW and PSHUFLW.
2656 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2657 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2659 if (N->getNumOperands() != 8)
2662 // Lower quadword shuffled.
2663 for (unsigned i = 0; i != 4; ++i) {
2664 SDValue Arg = N->getOperand(i);
2665 if (Arg.getOpcode() == ISD::UNDEF) continue;
2666 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2667 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2672 // Upper quadword shuffled.
2673 for (unsigned i = 4; i != 8; ++i) {
2674 SDValue Arg = N->getOperand(i);
2675 if (Arg.getOpcode() == ISD::UNDEF) continue;
2676 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2677 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2678 if (Val < 4 || Val > 7)
2685 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2686 /// values in ther permute mask.
2687 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2688 SDValue &V2, SDValue &Mask,
2689 SelectionDAG &DAG) {
2690 MVT VT = Op.getValueType();
2691 MVT MaskVT = Mask.getValueType();
2692 MVT EltVT = MaskVT.getVectorElementType();
2693 unsigned NumElems = Mask.getNumOperands();
2694 SmallVector<SDValue, 8> MaskVec;
2696 for (unsigned i = 0; i != NumElems; ++i) {
2697 SDValue Arg = Mask.getOperand(i);
2698 if (Arg.getOpcode() == ISD::UNDEF) {
2699 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2702 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2703 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2705 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2707 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2711 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2712 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2715 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2716 /// the two vector operands have swapped position.
2718 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2719 MVT MaskVT = Mask.getValueType();
2720 MVT EltVT = MaskVT.getVectorElementType();
2721 unsigned NumElems = Mask.getNumOperands();
2722 SmallVector<SDValue, 8> MaskVec;
2723 for (unsigned i = 0; i != NumElems; ++i) {
2724 SDValue Arg = Mask.getOperand(i);
2725 if (Arg.getOpcode() == ISD::UNDEF) {
2726 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2729 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2730 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2732 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2734 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2736 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2740 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2741 /// match movhlps. The lower half elements should come from upper half of
2742 /// V1 (and in order), and the upper half elements should come from the upper
2743 /// half of V2 (and in order).
2744 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2745 unsigned NumElems = Mask->getNumOperands();
2748 for (unsigned i = 0, e = 2; i != e; ++i)
2749 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2751 for (unsigned i = 2; i != 4; ++i)
2752 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2757 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2758 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2760 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2761 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2763 N = N->getOperand(0).getNode();
2764 if (!ISD::isNON_EXTLoad(N))
2767 *LD = cast<LoadSDNode>(N);
2771 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2772 /// match movlp{s|d}. The lower half elements should come from lower half of
2773 /// V1 (and in order), and the upper half elements should come from the upper
2774 /// half of V2 (and in order). And since V1 will become the source of the
2775 /// MOVLP, it must be either a vector load or a scalar load to vector.
2776 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2777 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2779 // Is V2 is a vector load, don't do this transformation. We will try to use
2780 // load folding shufps op.
2781 if (ISD::isNON_EXTLoad(V2))
2784 unsigned NumElems = Mask->getNumOperands();
2785 if (NumElems != 2 && NumElems != 4)
2787 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2788 if (!isUndefOrEqual(Mask->getOperand(i), i))
2790 for (unsigned i = NumElems/2; i != NumElems; ++i)
2791 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2796 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2798 static bool isSplatVector(SDNode *N) {
2799 if (N->getOpcode() != ISD::BUILD_VECTOR)
2802 SDValue SplatValue = N->getOperand(0);
2803 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2804 if (N->getOperand(i) != SplatValue)
2809 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2811 static bool isUndefShuffle(SDNode *N) {
2812 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2815 SDValue V1 = N->getOperand(0);
2816 SDValue V2 = N->getOperand(1);
2817 SDValue Mask = N->getOperand(2);
2818 unsigned NumElems = Mask.getNumOperands();
2819 for (unsigned i = 0; i != NumElems; ++i) {
2820 SDValue Arg = Mask.getOperand(i);
2821 if (Arg.getOpcode() != ISD::UNDEF) {
2822 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2823 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2825 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2832 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2834 static inline bool isZeroNode(SDValue Elt) {
2835 return ((isa<ConstantSDNode>(Elt) &&
2836 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2837 (isa<ConstantFPSDNode>(Elt) &&
2838 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2841 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2842 /// to an zero vector.
2843 static bool isZeroShuffle(SDNode *N) {
2844 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2847 SDValue V1 = N->getOperand(0);
2848 SDValue V2 = N->getOperand(1);
2849 SDValue Mask = N->getOperand(2);
2850 unsigned NumElems = Mask.getNumOperands();
2851 for (unsigned i = 0; i != NumElems; ++i) {
2852 SDValue Arg = Mask.getOperand(i);
2853 if (Arg.getOpcode() == ISD::UNDEF)
2856 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2857 if (Idx < NumElems) {
2858 unsigned Opc = V1.getNode()->getOpcode();
2859 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2861 if (Opc != ISD::BUILD_VECTOR ||
2862 !isZeroNode(V1.getNode()->getOperand(Idx)))
2864 } else if (Idx >= NumElems) {
2865 unsigned Opc = V2.getNode()->getOpcode();
2866 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2868 if (Opc != ISD::BUILD_VECTOR ||
2869 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2876 /// getZeroVector - Returns a vector of specified type with all zero elements.
2878 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2879 assert(VT.isVector() && "Expected a vector type");
2881 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2882 // type. This ensures they get CSE'd.
2884 if (VT.getSizeInBits() == 64) { // MMX
2885 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2886 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2887 } else if (HasSSE2) { // SSE2
2888 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2889 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2891 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2892 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2894 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2897 /// getOnesVector - Returns a vector of specified type with all bits set.
2899 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2900 assert(VT.isVector() && "Expected a vector type");
2902 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2903 // type. This ensures they get CSE'd.
2904 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2906 if (VT.getSizeInBits() == 64) // MMX
2907 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2909 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2910 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2914 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2915 /// that point to V2 points to its first element.
2916 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2917 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2919 bool Changed = false;
2920 SmallVector<SDValue, 8> MaskVec;
2921 unsigned NumElems = Mask.getNumOperands();
2922 for (unsigned i = 0; i != NumElems; ++i) {
2923 SDValue Arg = Mask.getOperand(i);
2924 if (Arg.getOpcode() != ISD::UNDEF) {
2925 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2926 if (Val > NumElems) {
2927 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2931 MaskVec.push_back(Arg);
2935 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2936 &MaskVec[0], MaskVec.size());
2940 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2941 /// operation of specified width.
2942 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2943 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2944 MVT BaseVT = MaskVT.getVectorElementType();
2946 SmallVector<SDValue, 8> MaskVec;
2947 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2948 for (unsigned i = 1; i != NumElems; ++i)
2949 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2950 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2953 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2954 /// of specified width.
2955 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2956 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2957 MVT BaseVT = MaskVT.getVectorElementType();
2958 SmallVector<SDValue, 8> MaskVec;
2959 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2960 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2961 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2963 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2966 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2967 /// of specified width.
2968 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2969 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2970 MVT BaseVT = MaskVT.getVectorElementType();
2971 unsigned Half = NumElems/2;
2972 SmallVector<SDValue, 8> MaskVec;
2973 for (unsigned i = 0; i != Half; ++i) {
2974 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2975 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2977 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2980 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2981 /// element #0 of a vector with the specified index, leaving the rest of the
2982 /// elements in place.
2983 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2984 SelectionDAG &DAG) {
2985 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2986 MVT BaseVT = MaskVT.getVectorElementType();
2987 SmallVector<SDValue, 8> MaskVec;
2988 // Element #0 of the result gets the elt we are replacing.
2989 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2990 for (unsigned i = 1; i != NumElems; ++i)
2991 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2992 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2995 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2996 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2997 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2998 MVT VT = Op.getValueType();
3001 SDValue V1 = Op.getOperand(0);
3002 SDValue Mask = Op.getOperand(2);
3003 unsigned MaskNumElems = Mask.getNumOperands();
3004 unsigned NumElems = MaskNumElems;
3005 // Special handling of v4f32 -> v4i32.
3006 if (VT != MVT::v4f32) {
3007 // Find which element we want to splat.
3008 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode();
3009 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue();
3010 // unpack elements to the correct location
3011 while (NumElems > 4) {
3012 if (EltNo < NumElems/2) {
3013 Mask = getUnpacklMask(MaskNumElems, DAG);
3015 Mask = getUnpackhMask(MaskNumElems, DAG);
3016 EltNo -= NumElems/2;
3018 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
3021 SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
3022 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
3025 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3026 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3027 DAG.getNode(ISD::UNDEF, PVT), Mask);
3028 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3031 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3032 /// load that's promoted to vector, or a load bitcasted.
3033 static bool isVectorLoad(SDValue Op) {
3034 assert(Op.getValueType().isVector() && "Expected a vector type");
3035 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3036 Op.getOpcode() == ISD::BIT_CONVERT) {
3037 return isa<LoadSDNode>(Op.getOperand(0));
3039 return isa<LoadSDNode>(Op);
3043 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3045 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3046 SelectionDAG &DAG, bool HasSSE3) {
3047 // If we have sse3 and shuffle has more than one use or input is a load, then
3048 // use movddup. Otherwise, use movlhps.
3049 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3050 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3051 MVT VT = Op.getValueType();
3054 unsigned NumElems = PVT.getVectorNumElements();
3055 if (NumElems == 2) {
3056 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3057 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
3059 assert(NumElems == 4);
3060 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3061 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3062 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1);
3065 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3066 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3067 DAG.getNode(ISD::UNDEF, PVT), Mask);
3068 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3071 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3072 /// vector of zero or undef vector. This produces a shuffle where the low
3073 /// element of V2 is swizzled into the zero/undef vector, landing at element
3074 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3075 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3076 bool isZero, bool HasSSE2,
3077 SelectionDAG &DAG) {
3078 MVT VT = V2.getValueType();
3080 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
3081 unsigned NumElems = V2.getValueType().getVectorNumElements();
3082 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3083 MVT EVT = MaskVT.getVectorElementType();
3084 SmallVector<SDValue, 16> MaskVec;
3085 for (unsigned i = 0; i != NumElems; ++i)
3086 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3087 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3089 MaskVec.push_back(DAG.getConstant(i, EVT));
3090 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3091 &MaskVec[0], MaskVec.size());
3092 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3095 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3096 /// a shuffle that is zero.
3098 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3099 unsigned NumElems, bool Low,
3100 SelectionDAG &DAG) {
3101 unsigned NumZeros = 0;
3102 for (unsigned i = 0; i < NumElems; ++i) {
3103 unsigned Index = Low ? i : NumElems-i-1;
3104 SDValue Idx = Mask.getOperand(Index);
3105 if (Idx.getOpcode() == ISD::UNDEF) {
3109 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3110 if (Elt.getNode() && isZeroNode(Elt))
3118 /// isVectorShift - Returns true if the shuffle can be implemented as a
3119 /// logical left or right shift of a vector.
3120 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3121 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3122 unsigned NumElems = Mask.getNumOperands();
3125 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3128 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3133 bool SeenV1 = false;
3134 bool SeenV2 = false;
3135 for (unsigned i = NumZeros; i < NumElems; ++i) {
3136 unsigned Val = isLeft ? (i - NumZeros) : i;
3137 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3138 if (Idx.getOpcode() == ISD::UNDEF)
3140 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3141 if (Index < NumElems)
3150 if (SeenV1 && SeenV2)
3153 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3159 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3161 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3162 unsigned NumNonZero, unsigned NumZero,
3163 SelectionDAG &DAG, TargetLowering &TLI) {
3169 for (unsigned i = 0; i < 16; ++i) {
3170 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3171 if (ThisIsNonZero && First) {
3173 V = getZeroVector(MVT::v8i16, true, DAG);
3175 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3180 SDValue ThisElt(0, 0), LastElt(0, 0);
3181 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3182 if (LastIsNonZero) {
3183 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3185 if (ThisIsNonZero) {
3186 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3187 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3188 ThisElt, DAG.getConstant(8, MVT::i8));
3190 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3194 if (ThisElt.getNode())
3195 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3196 DAG.getIntPtrConstant(i/2));
3200 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3203 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3205 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3206 unsigned NumNonZero, unsigned NumZero,
3207 SelectionDAG &DAG, TargetLowering &TLI) {
3213 for (unsigned i = 0; i < 8; ++i) {
3214 bool isNonZero = (NonZeros & (1 << i)) != 0;
3218 V = getZeroVector(MVT::v8i16, true, DAG);
3220 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3223 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3224 DAG.getIntPtrConstant(i));
3231 /// getVShift - Return a vector logical shift node.
3233 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3234 unsigned NumBits, SelectionDAG &DAG,
3235 const TargetLowering &TLI) {
3236 bool isMMX = VT.getSizeInBits() == 64;
3237 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3238 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3239 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3240 return DAG.getNode(ISD::BIT_CONVERT, VT,
3241 DAG.getNode(Opc, ShVT, SrcOp,
3242 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3246 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3247 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3248 if (ISD::isBuildVectorAllZeros(Op.getNode())
3249 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3250 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3251 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3252 // eliminated on x86-32 hosts.
3253 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3256 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3257 return getOnesVector(Op.getValueType(), DAG);
3258 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3261 MVT VT = Op.getValueType();
3262 MVT EVT = VT.getVectorElementType();
3263 unsigned EVTBits = EVT.getSizeInBits();
3265 unsigned NumElems = Op.getNumOperands();
3266 unsigned NumZero = 0;
3267 unsigned NumNonZero = 0;
3268 unsigned NonZeros = 0;
3269 bool IsAllConstants = true;
3270 SmallSet<SDValue, 8> Values;
3271 for (unsigned i = 0; i < NumElems; ++i) {
3272 SDValue Elt = Op.getOperand(i);
3273 if (Elt.getOpcode() == ISD::UNDEF)
3276 if (Elt.getOpcode() != ISD::Constant &&
3277 Elt.getOpcode() != ISD::ConstantFP)
3278 IsAllConstants = false;
3279 if (isZeroNode(Elt))
3282 NonZeros |= (1 << i);
3287 if (NumNonZero == 0) {
3288 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3289 return DAG.getNode(ISD::UNDEF, VT);
3292 // Special case for single non-zero, non-undef, element.
3293 if (NumNonZero == 1 && NumElems <= 4) {
3294 unsigned Idx = CountTrailingZeros_32(NonZeros);
3295 SDValue Item = Op.getOperand(Idx);
3297 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3298 // the value are obviously zero, truncate the value to i32 and do the
3299 // insertion that way. Only do this if the value is non-constant or if the
3300 // value is a constant being inserted into element 0. It is cheaper to do
3301 // a constant pool load than it is to do a movd + shuffle.
3302 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3303 (!IsAllConstants || Idx == 0)) {
3304 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3305 // Handle MMX and SSE both.
3306 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3307 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3309 // Truncate the value (which may itself be a constant) to i32, and
3310 // convert it to a vector with movd (S2V+shuffle to zero extend).
3311 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3312 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3313 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3314 Subtarget->hasSSE2(), DAG);
3316 // Now we have our 32-bit value zero extended in the low element of
3317 // a vector. If Idx != 0, swizzle it into place.
3320 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3321 getSwapEltZeroMask(VecElts, Idx, DAG)
3323 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3325 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3329 // If we have a constant or non-constant insertion into the low element of
3330 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3331 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3332 // depending on what the source datatype is. Because we can only get here
3333 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3335 // Don't do this for i64 values on x86-32.
3336 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3337 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3338 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3339 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3340 Subtarget->hasSSE2(), DAG);
3343 // Is it a vector logical left shift?
3344 if (NumElems == 2 && Idx == 1 &&
3345 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3346 unsigned NumBits = VT.getSizeInBits();
3347 return getVShift(true, VT,
3348 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3349 NumBits/2, DAG, *this);
3352 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3355 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3356 // is a non-constant being inserted into an element other than the low one,
3357 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3358 // movd/movss) to move this into the low element, then shuffle it into
3360 if (EVTBits == 32) {
3361 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3363 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3364 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3365 Subtarget->hasSSE2(), DAG);
3366 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3367 MVT MaskEVT = MaskVT.getVectorElementType();
3368 SmallVector<SDValue, 8> MaskVec;
3369 for (unsigned i = 0; i < NumElems; i++)
3370 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3371 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3372 &MaskVec[0], MaskVec.size());
3373 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3374 DAG.getNode(ISD::UNDEF, VT), Mask);
3378 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3379 if (Values.size() == 1)
3382 // A vector full of immediates; various special cases are already
3383 // handled, so this is best done with a single constant-pool load.
3387 // Let legalizer expand 2-wide build_vectors.
3388 if (EVTBits == 64) {
3389 if (NumNonZero == 1) {
3390 // One half is zero or undef.
3391 unsigned Idx = CountTrailingZeros_32(NonZeros);
3392 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3393 Op.getOperand(Idx));
3394 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3395 Subtarget->hasSSE2(), DAG);
3400 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3401 if (EVTBits == 8 && NumElems == 16) {
3402 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3404 if (V.getNode()) return V;
3407 if (EVTBits == 16 && NumElems == 8) {
3408 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3410 if (V.getNode()) return V;
3413 // If element VT is == 32 bits, turn it into a number of shuffles.
3414 SmallVector<SDValue, 8> V;
3416 if (NumElems == 4 && NumZero > 0) {
3417 for (unsigned i = 0; i < 4; ++i) {
3418 bool isZero = !(NonZeros & (1 << i));
3420 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3422 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3425 for (unsigned i = 0; i < 2; ++i) {
3426 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3429 V[i] = V[i*2]; // Must be a zero vector.
3432 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3433 getMOVLMask(NumElems, DAG));
3436 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3437 getMOVLMask(NumElems, DAG));
3440 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3441 getUnpacklMask(NumElems, DAG));
3446 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3447 MVT EVT = MaskVT.getVectorElementType();
3448 SmallVector<SDValue, 8> MaskVec;
3449 bool Reverse = (NonZeros & 0x3) == 2;
3450 for (unsigned i = 0; i < 2; ++i)
3452 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3454 MaskVec.push_back(DAG.getConstant(i, EVT));
3455 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3456 for (unsigned i = 0; i < 2; ++i)
3458 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3460 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3461 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3462 &MaskVec[0], MaskVec.size());
3463 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3466 if (Values.size() > 2) {
3467 // Expand into a number of unpckl*.
3469 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3470 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3471 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3472 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3473 for (unsigned i = 0; i < NumElems; ++i)
3474 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3476 while (NumElems != 0) {
3477 for (unsigned i = 0; i < NumElems; ++i)
3478 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3489 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3490 SDValue PermMask, SelectionDAG &DAG,
3491 TargetLowering &TLI) {
3493 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3494 MVT MaskEVT = MaskVT.getVectorElementType();
3495 MVT PtrVT = TLI.getPointerTy();
3496 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3497 PermMask.getNode()->op_end());
3499 // First record which half of which vector the low elements come from.
3500 SmallVector<unsigned, 4> LowQuad(4);
3501 for (unsigned i = 0; i < 4; ++i) {
3502 SDValue Elt = MaskElts[i];
3503 if (Elt.getOpcode() == ISD::UNDEF)
3505 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3506 int QuadIdx = EltIdx / 4;
3510 int BestLowQuad = -1;
3511 unsigned MaxQuad = 1;
3512 for (unsigned i = 0; i < 4; ++i) {
3513 if (LowQuad[i] > MaxQuad) {
3515 MaxQuad = LowQuad[i];
3519 // Record which half of which vector the high elements come from.
3520 SmallVector<unsigned, 4> HighQuad(4);
3521 for (unsigned i = 4; i < 8; ++i) {
3522 SDValue Elt = MaskElts[i];
3523 if (Elt.getOpcode() == ISD::UNDEF)
3525 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3526 int QuadIdx = EltIdx / 4;
3527 ++HighQuad[QuadIdx];
3530 int BestHighQuad = -1;
3532 for (unsigned i = 0; i < 4; ++i) {
3533 if (HighQuad[i] > MaxQuad) {
3535 MaxQuad = HighQuad[i];
3539 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3540 if (BestLowQuad != -1 || BestHighQuad != -1) {
3541 // First sort the 4 chunks in order using shufpd.
3542 SmallVector<SDValue, 8> MaskVec;
3544 if (BestLowQuad != -1)
3545 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3547 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3549 if (BestHighQuad != -1)
3550 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3552 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3554 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3555 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3556 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3557 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3558 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3560 // Now sort high and low parts separately.
3561 BitVector InOrder(8);
3562 if (BestLowQuad != -1) {
3563 // Sort lower half in order using PSHUFLW.
3565 bool AnyOutOrder = false;
3567 for (unsigned i = 0; i != 4; ++i) {
3568 SDValue Elt = MaskElts[i];
3569 if (Elt.getOpcode() == ISD::UNDEF) {
3570 MaskVec.push_back(Elt);
3573 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3577 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3579 // If this element is in the right place after this shuffle, then
3581 if ((int)(EltIdx / 4) == BestLowQuad)
3586 for (unsigned i = 4; i != 8; ++i)
3587 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3588 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3589 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3593 if (BestHighQuad != -1) {
3594 // Sort high half in order using PSHUFHW if possible.
3597 for (unsigned i = 0; i != 4; ++i)
3598 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3600 bool AnyOutOrder = false;
3601 for (unsigned i = 4; i != 8; ++i) {
3602 SDValue Elt = MaskElts[i];
3603 if (Elt.getOpcode() == ISD::UNDEF) {
3604 MaskVec.push_back(Elt);
3607 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3611 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3613 // If this element is in the right place after this shuffle, then
3615 if ((int)(EltIdx / 4) == BestHighQuad)
3621 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3622 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3626 // The other elements are put in the right place using pextrw and pinsrw.
3627 for (unsigned i = 0; i != 8; ++i) {
3630 SDValue Elt = MaskElts[i];
3631 if (Elt.getOpcode() == ISD::UNDEF)
3633 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3634 SDValue ExtOp = (EltIdx < 8)
3635 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3636 DAG.getConstant(EltIdx, PtrVT))
3637 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3638 DAG.getConstant(EltIdx - 8, PtrVT));
3639 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3640 DAG.getConstant(i, PtrVT));
3646 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3647 // few as possible. First, let's find out how many elements are already in the
3649 unsigned V1InOrder = 0;
3650 unsigned V1FromV1 = 0;
3651 unsigned V2InOrder = 0;
3652 unsigned V2FromV2 = 0;
3653 SmallVector<SDValue, 8> V1Elts;
3654 SmallVector<SDValue, 8> V2Elts;
3655 for (unsigned i = 0; i < 8; ++i) {
3656 SDValue Elt = MaskElts[i];
3657 if (Elt.getOpcode() == ISD::UNDEF) {
3658 V1Elts.push_back(Elt);
3659 V2Elts.push_back(Elt);
3664 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3666 V1Elts.push_back(Elt);
3667 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3669 } else if (EltIdx == i+8) {
3670 V1Elts.push_back(Elt);
3671 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3673 } else if (EltIdx < 8) {
3674 V1Elts.push_back(Elt);
3675 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3678 V1Elts.push_back(Elt);
3679 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3684 if (V2InOrder > V1InOrder) {
3685 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3687 std::swap(V1Elts, V2Elts);
3688 std::swap(V1FromV1, V2FromV2);
3691 if ((V1FromV1 + V1InOrder) != 8) {
3692 // Some elements are from V2.
3694 // If there are elements that are from V1 but out of place,
3695 // then first sort them in place
3696 SmallVector<SDValue, 8> MaskVec;
3697 for (unsigned i = 0; i < 8; ++i) {
3698 SDValue Elt = V1Elts[i];
3699 if (Elt.getOpcode() == ISD::UNDEF) {
3700 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3703 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3705 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3707 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3709 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3710 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3714 for (unsigned i = 0; i < 8; ++i) {
3715 SDValue Elt = V1Elts[i];
3716 if (Elt.getOpcode() == ISD::UNDEF)
3718 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3721 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3722 DAG.getConstant(EltIdx - 8, PtrVT));
3723 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3724 DAG.getConstant(i, PtrVT));
3728 // All elements are from V1.
3730 for (unsigned i = 0; i < 8; ++i) {
3731 SDValue Elt = V1Elts[i];
3732 if (Elt.getOpcode() == ISD::UNDEF)
3734 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3735 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3736 DAG.getConstant(EltIdx, PtrVT));
3737 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3738 DAG.getConstant(i, PtrVT));
3744 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3745 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3746 /// done when every pair / quad of shuffle mask elements point to elements in
3747 /// the right sequence. e.g.
3748 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3750 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3752 SDValue PermMask, SelectionDAG &DAG,
3753 TargetLowering &TLI) {
3754 unsigned NumElems = PermMask.getNumOperands();
3755 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3756 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3757 MVT MaskEltVT = MaskVT.getVectorElementType();
3759 switch (VT.getSimpleVT()) {
3760 default: assert(false && "Unexpected!");
3761 case MVT::v4f32: NewVT = MVT::v2f64; break;
3762 case MVT::v4i32: NewVT = MVT::v2i64; break;
3763 case MVT::v8i16: NewVT = MVT::v4i32; break;
3764 case MVT::v16i8: NewVT = MVT::v4i32; break;
3767 if (NewWidth == 2) {
3773 unsigned Scale = NumElems / NewWidth;
3774 SmallVector<SDValue, 8> MaskVec;
3775 for (unsigned i = 0; i < NumElems; i += Scale) {
3776 unsigned StartIdx = ~0U;
3777 for (unsigned j = 0; j < Scale; ++j) {
3778 SDValue Elt = PermMask.getOperand(i+j);
3779 if (Elt.getOpcode() == ISD::UNDEF)
3781 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3782 if (StartIdx == ~0U)
3783 StartIdx = EltIdx - (EltIdx % Scale);
3784 if (EltIdx != StartIdx + j)
3787 if (StartIdx == ~0U)
3788 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3790 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3793 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3794 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3795 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3796 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3797 &MaskVec[0], MaskVec.size()));
3800 /// getVZextMovL - Return a zero-extending vector move low node.
3802 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3803 SDValue SrcOp, SelectionDAG &DAG,
3804 const X86Subtarget *Subtarget) {
3805 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3806 LoadSDNode *LD = NULL;
3807 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3808 LD = dyn_cast<LoadSDNode>(SrcOp);
3810 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3812 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3813 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3814 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3815 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3816 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3818 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3819 return DAG.getNode(ISD::BIT_CONVERT, VT,
3820 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3821 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3828 return DAG.getNode(ISD::BIT_CONVERT, VT,
3829 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3830 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3833 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3836 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3837 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3838 MVT MaskVT = PermMask.getValueType();
3839 MVT MaskEVT = MaskVT.getVectorElementType();
3840 SmallVector<std::pair<int, int>, 8> Locs;
3842 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3845 for (unsigned i = 0; i != 4; ++i) {
3846 SDValue Elt = PermMask.getOperand(i);
3847 if (Elt.getOpcode() == ISD::UNDEF) {
3848 Locs[i] = std::make_pair(-1, -1);
3850 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3851 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3853 Locs[i] = std::make_pair(0, NumLo);
3857 Locs[i] = std::make_pair(1, NumHi);
3859 Mask1[2+NumHi] = Elt;
3865 if (NumLo <= 2 && NumHi <= 2) {
3866 // If no more than two elements come from either vector. This can be
3867 // implemented with two shuffles. First shuffle gather the elements.
3868 // The second shuffle, which takes the first shuffle as both of its
3869 // vector operands, put the elements into the right order.
3870 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3871 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3872 &Mask1[0], Mask1.size()));
3874 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3875 for (unsigned i = 0; i != 4; ++i) {
3876 if (Locs[i].first == -1)
3879 unsigned Idx = (i < 2) ? 0 : 4;
3880 Idx += Locs[i].first * 2 + Locs[i].second;
3881 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3885 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3886 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3887 &Mask2[0], Mask2.size()));
3888 } else if (NumLo == 3 || NumHi == 3) {
3889 // Otherwise, we must have three elements from one vector, call it X, and
3890 // one element from the other, call it Y. First, use a shufps to build an
3891 // intermediate vector with the one element from Y and the element from X
3892 // that will be in the same half in the final destination (the indexes don't
3893 // matter). Then, use a shufps to build the final vector, taking the half
3894 // containing the element from Y from the intermediate, and the other half
3897 // Normalize it so the 3 elements come from V1.
3898 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3902 // Find the element from V2.
3904 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3905 SDValue Elt = PermMask.getOperand(HiIndex);
3906 if (Elt.getOpcode() == ISD::UNDEF)
3908 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3913 Mask1[0] = PermMask.getOperand(HiIndex);
3914 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3915 Mask1[2] = PermMask.getOperand(HiIndex^1);
3916 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3917 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3918 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3921 Mask1[0] = PermMask.getOperand(0);
3922 Mask1[1] = PermMask.getOperand(1);
3923 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3924 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3925 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3926 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3928 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3929 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3930 Mask1[2] = PermMask.getOperand(2);
3931 Mask1[3] = PermMask.getOperand(3);
3932 if (Mask1[2].getOpcode() != ISD::UNDEF)
3934 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3936 if (Mask1[3].getOpcode() != ISD::UNDEF)
3938 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3940 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3941 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3945 // Break it into (shuffle shuffle_hi, shuffle_lo).
3947 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3948 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3949 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3950 unsigned MaskIdx = 0;
3953 for (unsigned i = 0; i != 4; ++i) {
3960 SDValue Elt = PermMask.getOperand(i);
3961 if (Elt.getOpcode() == ISD::UNDEF) {
3962 Locs[i] = std::make_pair(-1, -1);
3963 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
3964 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3965 (*MaskPtr)[LoIdx] = Elt;
3968 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3969 (*MaskPtr)[HiIdx] = Elt;
3974 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3975 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3976 &LoMask[0], LoMask.size()));
3977 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3978 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3979 &HiMask[0], HiMask.size()));
3980 SmallVector<SDValue, 8> MaskOps;
3981 for (unsigned i = 0; i != 4; ++i) {
3982 if (Locs[i].first == -1) {
3983 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3985 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3986 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3989 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3990 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3991 &MaskOps[0], MaskOps.size()));
3995 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3996 SDValue V1 = Op.getOperand(0);
3997 SDValue V2 = Op.getOperand(1);
3998 SDValue PermMask = Op.getOperand(2);
3999 MVT VT = Op.getValueType();
4000 unsigned NumElems = PermMask.getNumOperands();
4001 bool isMMX = VT.getSizeInBits() == 64;
4002 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4003 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4004 bool V1IsSplat = false;
4005 bool V2IsSplat = false;
4007 if (isUndefShuffle(Op.getNode()))
4008 return DAG.getNode(ISD::UNDEF, VT);
4010 if (isZeroShuffle(Op.getNode()))
4011 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
4013 if (isIdentityMask(PermMask.getNode()))
4015 else if (isIdentityMask(PermMask.getNode(), true))
4018 // Canonicalize movddup shuffles.
4019 if (V2IsUndef && Subtarget->hasSSE2() &&
4020 VT.getSizeInBits() == 128 &&
4021 X86::isMOVDDUPMask(PermMask.getNode()))
4022 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
4024 if (isSplatMask(PermMask.getNode())) {
4025 if (isMMX || NumElems < 4) return Op;
4026 // Promote it to a v4{if}32 splat.
4027 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
4030 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4032 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4033 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
4034 if (NewOp.getNode())
4035 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
4036 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4037 // FIXME: Figure out a cleaner way to do this.
4038 // Try to make use of movq to zero out the top part.
4039 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4040 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4042 if (NewOp.getNode()) {
4043 SDValue NewV1 = NewOp.getOperand(0);
4044 SDValue NewV2 = NewOp.getOperand(1);
4045 SDValue NewMask = NewOp.getOperand(2);
4046 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4047 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4048 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
4051 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4052 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4054 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4055 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4060 // Check if this can be converted into a logical shift.
4061 bool isLeft = false;
4064 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4065 if (isShift && ShVal.hasOneUse()) {
4066 // If the shifted value has multiple uses, it may be cheaper to use
4067 // v_set0 + movlhps or movhlps, etc.
4068 MVT EVT = VT.getVectorElementType();
4069 ShAmt *= EVT.getSizeInBits();
4070 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4073 if (X86::isMOVLMask(PermMask.getNode())) {
4076 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4077 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
4082 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4083 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4084 X86::isMOVHLPSMask(PermMask.getNode()) ||
4085 X86::isMOVHPMask(PermMask.getNode()) ||
4086 X86::isMOVLPMask(PermMask.getNode())))
4089 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4090 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4091 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4094 // No better options. Use a vshl / vsrl.
4095 MVT EVT = VT.getVectorElementType();
4096 ShAmt *= EVT.getSizeInBits();
4097 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4100 bool Commuted = false;
4101 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4102 // 1,1,1,1 -> v8i16 though.
4103 V1IsSplat = isSplatVector(V1.getNode());
4104 V2IsSplat = isSplatVector(V2.getNode());
4106 // Canonicalize the splat or undef, if present, to be on the RHS.
4107 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4108 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4109 std::swap(V1IsSplat, V2IsSplat);
4110 std::swap(V1IsUndef, V2IsUndef);
4114 // FIXME: Figure out a cleaner way to do this.
4115 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4116 if (V2IsUndef) return V1;
4117 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4119 // V2 is a splat, so the mask may be malformed. That is, it may point
4120 // to any V2 element. The instruction selectior won't like this. Get
4121 // a corrected mask and commute to form a proper MOVS{S|D}.
4122 SDValue NewMask = getMOVLMask(NumElems, DAG);
4123 if (NewMask.getNode() != PermMask.getNode())
4124 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4129 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4130 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4131 X86::isUNPCKLMask(PermMask.getNode()) ||
4132 X86::isUNPCKHMask(PermMask.getNode()))
4136 // Normalize mask so all entries that point to V2 points to its first
4137 // element then try to match unpck{h|l} again. If match, return a
4138 // new vector_shuffle with the corrected mask.
4139 SDValue NewMask = NormalizeMask(PermMask, DAG);
4140 if (NewMask.getNode() != PermMask.getNode()) {
4141 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4142 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4143 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4144 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4145 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4146 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4151 // Normalize the node to match x86 shuffle ops if needed
4152 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4153 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4156 // Commute is back and try unpck* again.
4157 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4158 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4159 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4160 X86::isUNPCKLMask(PermMask.getNode()) ||
4161 X86::isUNPCKHMask(PermMask.getNode()))
4165 // Try PSHUF* first, then SHUFP*.
4166 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4167 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4168 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4169 if (V2.getOpcode() != ISD::UNDEF)
4170 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4171 DAG.getNode(ISD::UNDEF, VT), PermMask);
4176 if (Subtarget->hasSSE2() &&
4177 (X86::isPSHUFDMask(PermMask.getNode()) ||
4178 X86::isPSHUFHWMask(PermMask.getNode()) ||
4179 X86::isPSHUFLWMask(PermMask.getNode()))) {
4181 if (VT == MVT::v4f32) {
4183 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4184 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4185 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4186 } else if (V2.getOpcode() != ISD::UNDEF)
4187 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4188 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4190 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4194 // Binary or unary shufps.
4195 if (X86::isSHUFPMask(PermMask.getNode()) ||
4196 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4200 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4201 if (VT == MVT::v8i16) {
4202 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4203 if (NewOp.getNode())
4207 // Handle all 4 wide cases with a number of shuffles except for MMX.
4208 if (NumElems == 4 && !isMMX)
4209 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4215 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4216 SelectionDAG &DAG) {
4217 MVT VT = Op.getValueType();
4218 if (VT.getSizeInBits() == 8) {
4219 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4220 Op.getOperand(0), Op.getOperand(1));
4221 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4222 DAG.getValueType(VT));
4223 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4224 } else if (VT.getSizeInBits() == 16) {
4225 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4226 Op.getOperand(0), Op.getOperand(1));
4227 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4228 DAG.getValueType(VT));
4229 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4230 } else if (VT == MVT::f32) {
4231 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4232 // the result back to FR32 register. It's only worth matching if the
4233 // result has a single use which is a store or a bitcast to i32. And in
4234 // the case of a store, it's not worth it if the index is a constant 0,
4235 // because a MOVSSmr can be used instead, which is smaller and faster.
4236 if (!Op.hasOneUse())
4238 SDNode *User = *Op.getNode()->use_begin();
4239 if ((User->getOpcode() != ISD::STORE ||
4240 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4241 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4242 (User->getOpcode() != ISD::BIT_CONVERT ||
4243 User->getValueType(0) != MVT::i32))
4245 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4246 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4248 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4255 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4256 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4259 if (Subtarget->hasSSE41()) {
4260 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4265 MVT VT = Op.getValueType();
4266 // TODO: handle v16i8.
4267 if (VT.getSizeInBits() == 16) {
4268 SDValue Vec = Op.getOperand(0);
4269 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4271 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4272 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4273 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4275 // Transform it so it match pextrw which produces a 32-bit result.
4276 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4277 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4278 Op.getOperand(0), Op.getOperand(1));
4279 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4280 DAG.getValueType(VT));
4281 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4282 } else if (VT.getSizeInBits() == 32) {
4283 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4286 // SHUFPS the element to the lowest double word, then movss.
4287 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4288 SmallVector<SDValue, 8> IdxVec;
4290 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4292 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4294 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4296 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4297 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4298 &IdxVec[0], IdxVec.size());
4299 SDValue Vec = Op.getOperand(0);
4300 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4301 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4302 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4303 DAG.getIntPtrConstant(0));
4304 } else if (VT.getSizeInBits() == 64) {
4305 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4306 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4307 // to match extract_elt for f64.
4308 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4312 // UNPCKHPD the element to the lowest double word, then movsd.
4313 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4314 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4315 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4316 SmallVector<SDValue, 8> IdxVec;
4317 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4319 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4320 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4321 &IdxVec[0], IdxVec.size());
4322 SDValue Vec = Op.getOperand(0);
4323 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4324 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4325 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4326 DAG.getIntPtrConstant(0));
4333 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4334 MVT VT = Op.getValueType();
4335 MVT EVT = VT.getVectorElementType();
4337 SDValue N0 = Op.getOperand(0);
4338 SDValue N1 = Op.getOperand(1);
4339 SDValue N2 = Op.getOperand(2);
4341 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4342 isa<ConstantSDNode>(N2)) {
4343 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4345 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4347 if (N1.getValueType() != MVT::i32)
4348 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4349 if (N2.getValueType() != MVT::i32)
4350 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4351 return DAG.getNode(Opc, VT, N0, N1, N2);
4352 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4353 // Bits [7:6] of the constant are the source select. This will always be
4354 // zero here. The DAG Combiner may combine an extract_elt index into these
4355 // bits. For example (insert (extract, 3), 2) could be matched by putting
4356 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4357 // Bits [5:4] of the constant are the destination select. This is the
4358 // value of the incoming immediate.
4359 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4360 // combine either bitwise AND or insert of float 0.0 to set these bits.
4361 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4362 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4368 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4369 MVT VT = Op.getValueType();
4370 MVT EVT = VT.getVectorElementType();
4372 if (Subtarget->hasSSE41())
4373 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4378 SDValue N0 = Op.getOperand(0);
4379 SDValue N1 = Op.getOperand(1);
4380 SDValue N2 = Op.getOperand(2);
4382 if (EVT.getSizeInBits() == 16) {
4383 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4384 // as its second argument.
4385 if (N1.getValueType() != MVT::i32)
4386 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4387 if (N2.getValueType() != MVT::i32)
4388 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4389 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4395 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4396 if (Op.getValueType() == MVT::v2f32)
4397 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4398 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4399 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4400 Op.getOperand(0))));
4402 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4403 MVT VT = MVT::v2i32;
4404 switch (Op.getValueType().getSimpleVT()) {
4411 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4412 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4415 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4416 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4417 // one of the above mentioned nodes. It has to be wrapped because otherwise
4418 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4419 // be used to form addressing mode. These wrapped nodes will be selected
4422 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4423 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4424 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4426 CP->getAlignment());
4427 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4428 // With PIC, the address is actually $g + Offset.
4429 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4430 !Subtarget->isPICStyleRIPRel()) {
4431 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4432 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4440 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
4442 SelectionDAG &DAG) const {
4443 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4444 bool ExtraLoadRequired =
4445 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4447 // Create the TargetGlobalAddress node, folding in the constant
4448 // offset if it is legal.
4450 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4451 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4454 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4455 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4457 // With PIC, the address is actually $g + Offset.
4458 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4459 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4460 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4464 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4465 // load the value at address GV, not the value of GV itself. This means that
4466 // the GlobalAddress must be in the base or index register of the address, not
4467 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4468 // The same applies for external symbols during PIC codegen
4469 if (ExtraLoadRequired)
4470 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4471 PseudoSourceValue::getGOT(), 0);
4473 // If there was a non-zero offset that we didn't fold, create an explicit
4476 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result,
4477 DAG.getConstant(Offset, getPointerTy()));
4483 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4484 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4485 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4486 return LowerGlobalAddress(GV, Offset, DAG);
4489 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4491 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4494 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4495 DAG.getNode(X86ISD::GlobalBaseReg,
4497 InFlag = Chain.getValue(1);
4499 // emit leal symbol@TLSGD(,%ebx,1), %eax
4500 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4501 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4502 GA->getValueType(0),
4504 SDValue Ops[] = { Chain, TGA, InFlag };
4505 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4506 InFlag = Result.getValue(2);
4507 Chain = Result.getValue(1);
4509 // call ___tls_get_addr. This function receives its argument in
4510 // the register EAX.
4511 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4512 InFlag = Chain.getValue(1);
4514 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4515 SDValue Ops1[] = { Chain,
4516 DAG.getTargetExternalSymbol("___tls_get_addr",
4518 DAG.getRegister(X86::EAX, PtrVT),
4519 DAG.getRegister(X86::EBX, PtrVT),
4521 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4522 InFlag = Chain.getValue(1);
4524 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4527 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4529 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4531 SDValue InFlag, Chain;
4533 // emit leaq symbol@TLSGD(%rip), %rdi
4534 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4535 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4536 GA->getValueType(0),
4538 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4539 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4540 Chain = Result.getValue(1);
4541 InFlag = Result.getValue(2);
4543 // call __tls_get_addr. This function receives its argument in
4544 // the register RDI.
4545 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4546 InFlag = Chain.getValue(1);
4548 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4549 SDValue Ops1[] = { Chain,
4550 DAG.getTargetExternalSymbol("__tls_get_addr",
4552 DAG.getRegister(X86::RDI, PtrVT),
4554 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4555 InFlag = Chain.getValue(1);
4557 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4560 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4561 // "local exec" model.
4562 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4564 // Get the Thread Pointer
4565 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4566 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4568 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4569 GA->getValueType(0),
4571 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4573 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4574 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4575 PseudoSourceValue::getGOT(), 0);
4577 // The address of the thread local variable is the add of the thread
4578 // pointer with the offset of the variable.
4579 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4583 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4584 // TODO: implement the "local dynamic" model
4585 // TODO: implement the "initial exec"model for pic executables
4586 assert(Subtarget->isTargetELF() &&
4587 "TLS not implemented for non-ELF targets");
4588 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4589 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4590 // otherwise use the "Local Exec"TLS Model
4591 if (Subtarget->is64Bit()) {
4592 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4594 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4595 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4597 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4602 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4603 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4604 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4605 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4606 // With PIC, the address is actually $g + Offset.
4607 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4608 !Subtarget->isPICStyleRIPRel()) {
4609 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4610 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4617 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4618 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4619 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4620 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4621 // With PIC, the address is actually $g + Offset.
4622 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4623 !Subtarget->isPICStyleRIPRel()) {
4624 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4625 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4632 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4633 /// take a 2 x i32 value to shift plus a shift amount.
4634 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4635 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4636 MVT VT = Op.getValueType();
4637 unsigned VTBits = VT.getSizeInBits();
4638 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4639 SDValue ShOpLo = Op.getOperand(0);
4640 SDValue ShOpHi = Op.getOperand(1);
4641 SDValue ShAmt = Op.getOperand(2);
4642 SDValue Tmp1 = isSRA ?
4643 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4644 DAG.getConstant(0, VT);
4647 if (Op.getOpcode() == ISD::SHL_PARTS) {
4648 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4649 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4651 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4652 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4655 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4656 DAG.getConstant(VTBits, MVT::i8));
4657 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4658 AndNode, DAG.getConstant(0, MVT::i8));
4661 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4662 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4663 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4665 if (Op.getOpcode() == ISD::SHL_PARTS) {
4666 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4667 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4669 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4670 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4673 SDValue Ops[2] = { Lo, Hi };
4674 return DAG.getMergeValues(Ops, 2);
4677 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4678 MVT SrcVT = Op.getOperand(0).getValueType();
4679 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4680 "Unknown SINT_TO_FP to lower!");
4682 // These are really Legal; caller falls through into that case.
4683 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4685 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4686 Subtarget->is64Bit())
4689 unsigned Size = SrcVT.getSizeInBits()/8;
4690 MachineFunction &MF = DAG.getMachineFunction();
4691 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4692 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4693 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4695 PseudoSourceValue::getFixedStack(SSFI), 0);
4699 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4701 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4703 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4704 SmallVector<SDValue, 8> Ops;
4705 Ops.push_back(Chain);
4706 Ops.push_back(StackSlot);
4707 Ops.push_back(DAG.getValueType(SrcVT));
4708 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4709 Tys, &Ops[0], Ops.size());
4712 Chain = Result.getValue(1);
4713 SDValue InFlag = Result.getValue(2);
4715 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4716 // shouldn't be necessary except that RFP cannot be live across
4717 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4718 MachineFunction &MF = DAG.getMachineFunction();
4719 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4720 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4721 Tys = DAG.getVTList(MVT::Other);
4722 SmallVector<SDValue, 8> Ops;
4723 Ops.push_back(Chain);
4724 Ops.push_back(Result);
4725 Ops.push_back(StackSlot);
4726 Ops.push_back(DAG.getValueType(Op.getValueType()));
4727 Ops.push_back(InFlag);
4728 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4729 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4730 PseudoSourceValue::getFixedStack(SSFI), 0);
4736 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4737 MVT SrcVT = Op.getOperand(0).getValueType();
4738 assert(SrcVT.getSimpleVT() == MVT::i64 && "Unknown UINT_TO_FP to lower!");
4740 // We only handle SSE2 f64 target here; caller can handle the rest.
4741 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
4744 // This algorithm is not obvious. Here it is in C code, more or less:
4746 double uint64_to_double( uint32_t hi, uint32_t lo )
4748 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4749 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4751 // copy ints to xmm registers
4752 __m128i xh = _mm_cvtsi32_si128( hi );
4753 __m128i xl = _mm_cvtsi32_si128( lo );
4755 // combine into low half of a single xmm register
4756 __m128i x = _mm_unpacklo_epi32( xh, xl );
4760 // merge in appropriate exponents to give the integer bits the
4762 x = _mm_unpacklo_epi32( x, exp );
4764 // subtract away the biases to deal with the IEEE-754 double precision
4766 d = _mm_sub_pd( (__m128d) x, bias );
4768 // All conversions up to here are exact. The correctly rounded result is
4769 // calculated using the
4770 // current rounding mode using the following horizontal add.
4771 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4772 _mm_store_sd( &sd, d ); //since we are returning doubles in XMM, this
4773 // store doesn't really need to be here (except maybe to zero the other
4779 // Build some magic constants.
4780 std::vector<Constant*>CV0;
4781 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4782 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4783 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4784 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4785 Constant *C0 = ConstantVector::get(CV0);
4786 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4);
4788 std::vector<Constant*>CV1;
4789 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4790 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4791 Constant *C1 = ConstantVector::get(CV1);
4792 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4);
4794 SmallVector<SDValue, 4> MaskVec;
4795 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
4796 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
4797 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
4798 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
4799 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0],
4801 SmallVector<SDValue, 4> MaskVec2;
4802 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
4803 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
4804 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0],
4807 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4808 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4810 DAG.getIntPtrConstant(1)));
4811 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4812 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4814 DAG.getIntPtrConstant(0)));
4815 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4816 XR1, XR2, UnpcklMask);
4817 SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0,
4818 PseudoSourceValue::getConstantPool(), 0, false, 16);
4819 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4820 Unpck1, CLod0, UnpcklMask);
4821 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2);
4822 SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1,
4823 PseudoSourceValue::getConstantPool(), 0, false, 16);
4824 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1);
4825 // Add the halves; easiest way is to swap them into another reg first.
4826 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64,
4827 Sub, Sub, ShufMask);
4828 SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub);
4829 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add,
4830 DAG.getIntPtrConstant(0));
4833 std::pair<SDValue,SDValue> X86TargetLowering::
4834 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4835 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4836 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4837 "Unknown FP_TO_SINT to lower!");
4839 // These are really Legal.
4840 if (Op.getValueType() == MVT::i32 &&
4841 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4842 return std::make_pair(SDValue(), SDValue());
4843 if (Subtarget->is64Bit() &&
4844 Op.getValueType() == MVT::i64 &&
4845 Op.getOperand(0).getValueType() != MVT::f80)
4846 return std::make_pair(SDValue(), SDValue());
4848 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4850 MachineFunction &MF = DAG.getMachineFunction();
4851 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4852 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4853 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4855 switch (Op.getValueType().getSimpleVT()) {
4856 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4857 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4858 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4859 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4862 SDValue Chain = DAG.getEntryNode();
4863 SDValue Value = Op.getOperand(0);
4864 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4865 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4866 Chain = DAG.getStore(Chain, Value, StackSlot,
4867 PseudoSourceValue::getFixedStack(SSFI), 0);
4868 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4870 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4872 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4873 Chain = Value.getValue(1);
4874 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4875 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4878 // Build the FP_TO_INT*_IN_MEM
4879 SDValue Ops[] = { Chain, Value, StackSlot };
4880 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4882 return std::make_pair(FIST, StackSlot);
4885 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4886 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4887 SDValue FIST = Vals.first, StackSlot = Vals.second;
4888 if (FIST.getNode() == 0) return SDValue();
4891 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4894 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4895 MVT VT = Op.getValueType();
4898 EltVT = VT.getVectorElementType();
4899 std::vector<Constant*> CV;
4900 if (EltVT == MVT::f64) {
4901 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4905 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4911 Constant *C = ConstantVector::get(CV);
4912 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4913 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4914 PseudoSourceValue::getConstantPool(), 0,
4916 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4919 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
4920 MVT VT = Op.getValueType();
4922 unsigned EltNum = 1;
4923 if (VT.isVector()) {
4924 EltVT = VT.getVectorElementType();
4925 EltNum = VT.getVectorNumElements();
4927 std::vector<Constant*> CV;
4928 if (EltVT == MVT::f64) {
4929 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4933 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4939 Constant *C = ConstantVector::get(CV);
4940 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4941 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4942 PseudoSourceValue::getConstantPool(), 0,
4944 if (VT.isVector()) {
4945 return DAG.getNode(ISD::BIT_CONVERT, VT,
4946 DAG.getNode(ISD::XOR, MVT::v2i64,
4947 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4948 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4950 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4954 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4955 SDValue Op0 = Op.getOperand(0);
4956 SDValue Op1 = Op.getOperand(1);
4957 MVT VT = Op.getValueType();
4958 MVT SrcVT = Op1.getValueType();
4960 // If second operand is smaller, extend it first.
4961 if (SrcVT.bitsLT(VT)) {
4962 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4965 // And if it is bigger, shrink it first.
4966 if (SrcVT.bitsGT(VT)) {
4967 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4971 // At this point the operands and the result should have the same
4972 // type, and that won't be f80 since that is not custom lowered.
4974 // First get the sign bit of second operand.
4975 std::vector<Constant*> CV;
4976 if (SrcVT == MVT::f64) {
4977 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4978 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4980 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4981 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4982 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4983 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4985 Constant *C = ConstantVector::get(CV);
4986 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4987 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4988 PseudoSourceValue::getConstantPool(), 0,
4990 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4992 // Shift sign bit right or left if the two operands have different types.
4993 if (SrcVT.bitsGT(VT)) {
4994 // Op0 is MVT::f32, Op1 is MVT::f64.
4995 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4996 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4997 DAG.getConstant(32, MVT::i32));
4998 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4999 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
5000 DAG.getIntPtrConstant(0));
5003 // Clear first operand sign bit.
5005 if (VT == MVT::f64) {
5006 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5007 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5009 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5010 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5011 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5012 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5014 C = ConstantVector::get(CV);
5015 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5016 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5017 PseudoSourceValue::getConstantPool(), 0,
5019 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
5021 // Or the value with the sign bit.
5022 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
5025 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5026 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5028 SDValue Op0 = Op.getOperand(0);
5029 SDValue Op1 = Op.getOperand(1);
5030 SDValue CC = Op.getOperand(2);
5031 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5034 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
5036 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
5037 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5038 DAG.getConstant(X86CC, MVT::i8), Cond);
5041 assert(0 && "Illegal SetCC!");
5045 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5047 SDValue Op0 = Op.getOperand(0);
5048 SDValue Op1 = Op.getOperand(1);
5049 SDValue CC = Op.getOperand(2);
5050 MVT VT = Op.getValueType();
5051 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5052 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5056 MVT VT0 = Op0.getValueType();
5057 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5058 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5061 switch (SetCCOpcode) {
5064 case ISD::SETEQ: SSECC = 0; break;
5066 case ISD::SETGT: Swap = true; // Fallthrough
5068 case ISD::SETOLT: SSECC = 1; break;
5070 case ISD::SETGE: Swap = true; // Fallthrough
5072 case ISD::SETOLE: SSECC = 2; break;
5073 case ISD::SETUO: SSECC = 3; break;
5075 case ISD::SETNE: SSECC = 4; break;
5076 case ISD::SETULE: Swap = true;
5077 case ISD::SETUGE: SSECC = 5; break;
5078 case ISD::SETULT: Swap = true;
5079 case ISD::SETUGT: SSECC = 6; break;
5080 case ISD::SETO: SSECC = 7; break;
5083 std::swap(Op0, Op1);
5085 // In the two special cases we can't handle, emit two comparisons.
5087 if (SetCCOpcode == ISD::SETUEQ) {
5089 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5090 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5091 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
5093 else if (SetCCOpcode == ISD::SETONE) {
5095 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5096 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5097 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
5099 assert(0 && "Illegal FP comparison");
5101 // Handle all other FP comparisons here.
5102 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5105 // We are handling one of the integer comparisons here. Since SSE only has
5106 // GT and EQ comparisons for integer, swapping operands and multiple
5107 // operations may be required for some comparisons.
5108 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5109 bool Swap = false, Invert = false, FlipSigns = false;
5111 switch (VT.getSimpleVT()) {
5113 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5114 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5115 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5116 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5119 switch (SetCCOpcode) {
5121 case ISD::SETNE: Invert = true;
5122 case ISD::SETEQ: Opc = EQOpc; break;
5123 case ISD::SETLT: Swap = true;
5124 case ISD::SETGT: Opc = GTOpc; break;
5125 case ISD::SETGE: Swap = true;
5126 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5127 case ISD::SETULT: Swap = true;
5128 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5129 case ISD::SETUGE: Swap = true;
5130 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5133 std::swap(Op0, Op1);
5135 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5136 // bits of the inputs before performing those operations.
5138 MVT EltVT = VT.getVectorElementType();
5139 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
5140 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5141 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
5143 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
5144 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
5147 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
5149 // If the logical-not of the result is required, perform that now.
5151 MVT EltVT = VT.getVectorElementType();
5152 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
5153 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
5154 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
5156 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
5161 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5162 static bool isX86LogicalCmp(unsigned Opc) {
5163 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI;
5166 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5167 bool addTest = true;
5168 SDValue Cond = Op.getOperand(0);
5171 if (Cond.getOpcode() == ISD::SETCC)
5172 Cond = LowerSETCC(Cond, DAG);
5174 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5175 // setting operand in place of the X86ISD::SETCC.
5176 if (Cond.getOpcode() == X86ISD::SETCC) {
5177 CC = Cond.getOperand(0);
5179 SDValue Cmp = Cond.getOperand(1);
5180 unsigned Opc = Cmp.getOpcode();
5181 MVT VT = Op.getValueType();
5183 bool IllegalFPCMov = false;
5184 if (VT.isFloatingPoint() && !VT.isVector() &&
5185 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5186 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5188 if (isX86LogicalCmp(Opc) && !IllegalFPCMov) {
5195 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5196 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5199 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5201 SmallVector<SDValue, 4> Ops;
5202 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5203 // condition is true.
5204 Ops.push_back(Op.getOperand(2));
5205 Ops.push_back(Op.getOperand(1));
5207 Ops.push_back(Cond);
5208 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
5211 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5212 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5213 // from the AND / OR.
5214 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5215 Opc = Op.getOpcode();
5216 if (Opc != ISD::OR && Opc != ISD::AND)
5218 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5219 Op.getOperand(0).hasOneUse() &&
5220 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5221 Op.getOperand(1).hasOneUse());
5224 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5225 bool addTest = true;
5226 SDValue Chain = Op.getOperand(0);
5227 SDValue Cond = Op.getOperand(1);
5228 SDValue Dest = Op.getOperand(2);
5231 if (Cond.getOpcode() == ISD::SETCC)
5232 Cond = LowerSETCC(Cond, DAG);
5233 else if (Cond.getOpcode() == X86ISD::ADD ||
5234 Cond.getOpcode() == X86ISD::SUB ||
5235 Cond.getOpcode() == X86ISD::SMUL ||
5236 Cond.getOpcode() == X86ISD::UMUL)
5237 Cond = LowerXALUO(Cond, DAG);
5239 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5240 // setting operand in place of the X86ISD::SETCC.
5241 if (Cond.getOpcode() == X86ISD::SETCC) {
5242 CC = Cond.getOperand(0);
5244 SDValue Cmp = Cond.getOperand(1);
5245 unsigned Opc = Cmp.getOpcode();
5246 if (isX86LogicalCmp(Opc)) {
5250 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5254 // These can only come from an arithmetic instruction with overflow, e.g.
5256 Cond = Cond.getNode()->getOperand(1);
5263 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5264 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5265 unsigned Opc = Cmp.getOpcode();
5266 if (CondOpc == ISD::OR) {
5267 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5268 // two branches instead of an explicit OR instruction with a
5270 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5271 isX86LogicalCmp(Opc)) {
5272 CC = Cond.getOperand(0).getOperand(0);
5273 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5274 Chain, Dest, CC, Cmp);
5275 CC = Cond.getOperand(1).getOperand(0);
5279 } else { // ISD::AND
5280 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5281 // two branches instead of an explicit AND instruction with a
5282 // separate test. However, we only do this if this block doesn't
5283 // have a fall-through edge, because this requires an explicit
5284 // jmp when the condition is false.
5285 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5286 isX86LogicalCmp(Opc) &&
5287 Op.getNode()->hasOneUse()) {
5288 X86::CondCode CCode =
5289 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5290 CCode = X86::GetOppositeBranchCondition(CCode);
5291 CC = DAG.getConstant(CCode, MVT::i8);
5292 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5293 // Look for an unconditional branch following this conditional branch.
5294 // We need this because we need to reverse the successors in order
5295 // to implement FCMP_OEQ.
5296 if (User.getOpcode() == ISD::BR) {
5297 SDValue FalseBB = User.getOperand(1);
5299 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5300 assert(NewBR == User);
5303 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5304 Chain, Dest, CC, Cmp);
5305 X86::CondCode CCode =
5306 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5307 CCode = X86::GetOppositeBranchCondition(CCode);
5308 CC = DAG.getConstant(CCode, MVT::i8);
5318 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5319 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5321 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5322 Chain, Dest, CC, Cond);
5326 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5327 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5328 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5329 // that the guard pages used by the OS virtual memory manager are allocated in
5330 // correct sequence.
5332 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5333 SelectionDAG &DAG) {
5334 assert(Subtarget->isTargetCygMing() &&
5335 "This should be used only on Cygwin/Mingw targets");
5338 SDValue Chain = Op.getOperand(0);
5339 SDValue Size = Op.getOperand(1);
5340 // FIXME: Ensure alignment here
5344 MVT IntPtr = getPointerTy();
5345 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5347 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5349 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5350 Flag = Chain.getValue(1);
5352 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5353 SDValue Ops[] = { Chain,
5354 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5355 DAG.getRegister(X86::EAX, IntPtr),
5356 DAG.getRegister(X86StackPtr, SPTy),
5358 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5359 Flag = Chain.getValue(1);
5361 Chain = DAG.getCALLSEQ_END(Chain,
5362 DAG.getIntPtrConstant(0, true),
5363 DAG.getIntPtrConstant(0, true),
5366 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5368 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5369 return DAG.getMergeValues(Ops1, 2);
5373 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5375 SDValue Dst, SDValue Src,
5376 SDValue Size, unsigned Align,
5378 uint64_t DstSVOff) {
5379 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5381 // If not DWORD aligned or size is more than the threshold, call the library.
5382 // The libc version is likely to be faster for these cases. It can use the
5383 // address value and run time information about the CPU.
5384 if ((Align & 3) != 0 ||
5386 ConstantSize->getZExtValue() >
5387 getSubtarget()->getMaxInlineSizeThreshold()) {
5388 SDValue InFlag(0, 0);
5390 // Check to see if there is a specialized entry-point for memory zeroing.
5391 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5393 if (const char *bzeroEntry = V &&
5394 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5395 MVT IntPtr = getPointerTy();
5396 const Type *IntPtrTy = TD->getIntPtrType();
5397 TargetLowering::ArgListTy Args;
5398 TargetLowering::ArgListEntry Entry;
5400 Entry.Ty = IntPtrTy;
5401 Args.push_back(Entry);
5403 Args.push_back(Entry);
5404 std::pair<SDValue,SDValue> CallResult =
5405 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5406 CallingConv::C, false,
5407 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG);
5408 return CallResult.second;
5411 // Otherwise have the target-independent code call memset.
5415 uint64_t SizeVal = ConstantSize->getZExtValue();
5416 SDValue InFlag(0, 0);
5419 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5420 unsigned BytesLeft = 0;
5421 bool TwoRepStos = false;
5424 uint64_t Val = ValC->getZExtValue() & 255;
5426 // If the value is a constant, then we can potentially use larger sets.
5427 switch (Align & 3) {
5428 case 2: // WORD aligned
5431 Val = (Val << 8) | Val;
5433 case 0: // DWORD aligned
5436 Val = (Val << 8) | Val;
5437 Val = (Val << 16) | Val;
5438 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5441 Val = (Val << 32) | Val;
5444 default: // Byte aligned
5447 Count = DAG.getIntPtrConstant(SizeVal);
5451 if (AVT.bitsGT(MVT::i8)) {
5452 unsigned UBytes = AVT.getSizeInBits() / 8;
5453 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5454 BytesLeft = SizeVal % UBytes;
5457 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5459 InFlag = Chain.getValue(1);
5462 Count = DAG.getIntPtrConstant(SizeVal);
5463 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5464 InFlag = Chain.getValue(1);
5467 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5469 InFlag = Chain.getValue(1);
5470 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5472 InFlag = Chain.getValue(1);
5474 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5475 SmallVector<SDValue, 8> Ops;
5476 Ops.push_back(Chain);
5477 Ops.push_back(DAG.getValueType(AVT));
5478 Ops.push_back(InFlag);
5479 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5482 InFlag = Chain.getValue(1);
5484 MVT CVT = Count.getValueType();
5485 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5486 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5487 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5489 InFlag = Chain.getValue(1);
5490 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5492 Ops.push_back(Chain);
5493 Ops.push_back(DAG.getValueType(MVT::i8));
5494 Ops.push_back(InFlag);
5495 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5496 } else if (BytesLeft) {
5497 // Handle the last 1 - 7 bytes.
5498 unsigned Offset = SizeVal - BytesLeft;
5499 MVT AddrVT = Dst.getValueType();
5500 MVT SizeVT = Size.getValueType();
5502 Chain = DAG.getMemset(Chain,
5503 DAG.getNode(ISD::ADD, AddrVT, Dst,
5504 DAG.getConstant(Offset, AddrVT)),
5506 DAG.getConstant(BytesLeft, SizeVT),
5507 Align, DstSV, DstSVOff + Offset);
5510 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5515 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5516 SDValue Chain, SDValue Dst, SDValue Src,
5517 SDValue Size, unsigned Align,
5519 const Value *DstSV, uint64_t DstSVOff,
5520 const Value *SrcSV, uint64_t SrcSVOff) {
5521 // This requires the copy size to be a constant, preferrably
5522 // within a subtarget-specific limit.
5523 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5526 uint64_t SizeVal = ConstantSize->getZExtValue();
5527 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5530 /// If not DWORD aligned, call the library.
5531 if ((Align & 3) != 0)
5536 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5539 unsigned UBytes = AVT.getSizeInBits() / 8;
5540 unsigned CountVal = SizeVal / UBytes;
5541 SDValue Count = DAG.getIntPtrConstant(CountVal);
5542 unsigned BytesLeft = SizeVal % UBytes;
5544 SDValue InFlag(0, 0);
5545 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5547 InFlag = Chain.getValue(1);
5548 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5550 InFlag = Chain.getValue(1);
5551 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5553 InFlag = Chain.getValue(1);
5555 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5556 SmallVector<SDValue, 8> Ops;
5557 Ops.push_back(Chain);
5558 Ops.push_back(DAG.getValueType(AVT));
5559 Ops.push_back(InFlag);
5560 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5562 SmallVector<SDValue, 4> Results;
5563 Results.push_back(RepMovs);
5565 // Handle the last 1 - 7 bytes.
5566 unsigned Offset = SizeVal - BytesLeft;
5567 MVT DstVT = Dst.getValueType();
5568 MVT SrcVT = Src.getValueType();
5569 MVT SizeVT = Size.getValueType();
5570 Results.push_back(DAG.getMemcpy(Chain,
5571 DAG.getNode(ISD::ADD, DstVT, Dst,
5572 DAG.getConstant(Offset, DstVT)),
5573 DAG.getNode(ISD::ADD, SrcVT, Src,
5574 DAG.getConstant(Offset, SrcVT)),
5575 DAG.getConstant(BytesLeft, SizeVT),
5576 Align, AlwaysInline,
5577 DstSV, DstSVOff + Offset,
5578 SrcSV, SrcSVOff + Offset));
5581 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5584 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5585 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5587 if (!Subtarget->is64Bit()) {
5588 // vastart just stores the address of the VarArgsFrameIndex slot into the
5589 // memory location argument.
5590 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5591 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5595 // gp_offset (0 - 6 * 8)
5596 // fp_offset (48 - 48 + 8 * 16)
5597 // overflow_arg_area (point to parameters coming in memory).
5599 SmallVector<SDValue, 8> MemOps;
5600 SDValue FIN = Op.getOperand(1);
5602 SDValue Store = DAG.getStore(Op.getOperand(0),
5603 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5605 MemOps.push_back(Store);
5608 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5609 Store = DAG.getStore(Op.getOperand(0),
5610 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5612 MemOps.push_back(Store);
5614 // Store ptr to overflow_arg_area
5615 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5616 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5617 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5618 MemOps.push_back(Store);
5620 // Store ptr to reg_save_area.
5621 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5622 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5623 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5624 MemOps.push_back(Store);
5625 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5628 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5629 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5630 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5631 SDValue Chain = Op.getOperand(0);
5632 SDValue SrcPtr = Op.getOperand(1);
5633 SDValue SrcSV = Op.getOperand(2);
5635 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5640 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5641 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5642 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5643 SDValue Chain = Op.getOperand(0);
5644 SDValue DstPtr = Op.getOperand(1);
5645 SDValue SrcPtr = Op.getOperand(2);
5646 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5647 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5649 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5650 DAG.getIntPtrConstant(24), 8, false,
5651 DstSV, 0, SrcSV, 0);
5655 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5656 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5658 default: return SDValue(); // Don't custom lower most intrinsics.
5659 // Comparison intrinsics.
5660 case Intrinsic::x86_sse_comieq_ss:
5661 case Intrinsic::x86_sse_comilt_ss:
5662 case Intrinsic::x86_sse_comile_ss:
5663 case Intrinsic::x86_sse_comigt_ss:
5664 case Intrinsic::x86_sse_comige_ss:
5665 case Intrinsic::x86_sse_comineq_ss:
5666 case Intrinsic::x86_sse_ucomieq_ss:
5667 case Intrinsic::x86_sse_ucomilt_ss:
5668 case Intrinsic::x86_sse_ucomile_ss:
5669 case Intrinsic::x86_sse_ucomigt_ss:
5670 case Intrinsic::x86_sse_ucomige_ss:
5671 case Intrinsic::x86_sse_ucomineq_ss:
5672 case Intrinsic::x86_sse2_comieq_sd:
5673 case Intrinsic::x86_sse2_comilt_sd:
5674 case Intrinsic::x86_sse2_comile_sd:
5675 case Intrinsic::x86_sse2_comigt_sd:
5676 case Intrinsic::x86_sse2_comige_sd:
5677 case Intrinsic::x86_sse2_comineq_sd:
5678 case Intrinsic::x86_sse2_ucomieq_sd:
5679 case Intrinsic::x86_sse2_ucomilt_sd:
5680 case Intrinsic::x86_sse2_ucomile_sd:
5681 case Intrinsic::x86_sse2_ucomigt_sd:
5682 case Intrinsic::x86_sse2_ucomige_sd:
5683 case Intrinsic::x86_sse2_ucomineq_sd: {
5685 ISD::CondCode CC = ISD::SETCC_INVALID;
5688 case Intrinsic::x86_sse_comieq_ss:
5689 case Intrinsic::x86_sse2_comieq_sd:
5693 case Intrinsic::x86_sse_comilt_ss:
5694 case Intrinsic::x86_sse2_comilt_sd:
5698 case Intrinsic::x86_sse_comile_ss:
5699 case Intrinsic::x86_sse2_comile_sd:
5703 case Intrinsic::x86_sse_comigt_ss:
5704 case Intrinsic::x86_sse2_comigt_sd:
5708 case Intrinsic::x86_sse_comige_ss:
5709 case Intrinsic::x86_sse2_comige_sd:
5713 case Intrinsic::x86_sse_comineq_ss:
5714 case Intrinsic::x86_sse2_comineq_sd:
5718 case Intrinsic::x86_sse_ucomieq_ss:
5719 case Intrinsic::x86_sse2_ucomieq_sd:
5720 Opc = X86ISD::UCOMI;
5723 case Intrinsic::x86_sse_ucomilt_ss:
5724 case Intrinsic::x86_sse2_ucomilt_sd:
5725 Opc = X86ISD::UCOMI;
5728 case Intrinsic::x86_sse_ucomile_ss:
5729 case Intrinsic::x86_sse2_ucomile_sd:
5730 Opc = X86ISD::UCOMI;
5733 case Intrinsic::x86_sse_ucomigt_ss:
5734 case Intrinsic::x86_sse2_ucomigt_sd:
5735 Opc = X86ISD::UCOMI;
5738 case Intrinsic::x86_sse_ucomige_ss:
5739 case Intrinsic::x86_sse2_ucomige_sd:
5740 Opc = X86ISD::UCOMI;
5743 case Intrinsic::x86_sse_ucomineq_ss:
5744 case Intrinsic::x86_sse2_ucomineq_sd:
5745 Opc = X86ISD::UCOMI;
5751 SDValue LHS = Op.getOperand(1);
5752 SDValue RHS = Op.getOperand(2);
5753 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5755 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5756 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5757 DAG.getConstant(X86CC, MVT::i8), Cond);
5758 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5761 // Fix vector shift instructions where the last operand is a non-immediate
5763 case Intrinsic::x86_sse2_pslli_w:
5764 case Intrinsic::x86_sse2_pslli_d:
5765 case Intrinsic::x86_sse2_pslli_q:
5766 case Intrinsic::x86_sse2_psrli_w:
5767 case Intrinsic::x86_sse2_psrli_d:
5768 case Intrinsic::x86_sse2_psrli_q:
5769 case Intrinsic::x86_sse2_psrai_w:
5770 case Intrinsic::x86_sse2_psrai_d:
5771 case Intrinsic::x86_mmx_pslli_w:
5772 case Intrinsic::x86_mmx_pslli_d:
5773 case Intrinsic::x86_mmx_pslli_q:
5774 case Intrinsic::x86_mmx_psrli_w:
5775 case Intrinsic::x86_mmx_psrli_d:
5776 case Intrinsic::x86_mmx_psrli_q:
5777 case Intrinsic::x86_mmx_psrai_w:
5778 case Intrinsic::x86_mmx_psrai_d: {
5779 SDValue ShAmt = Op.getOperand(2);
5780 if (isa<ConstantSDNode>(ShAmt))
5783 unsigned NewIntNo = 0;
5784 MVT ShAmtVT = MVT::v4i32;
5786 case Intrinsic::x86_sse2_pslli_w:
5787 NewIntNo = Intrinsic::x86_sse2_psll_w;
5789 case Intrinsic::x86_sse2_pslli_d:
5790 NewIntNo = Intrinsic::x86_sse2_psll_d;
5792 case Intrinsic::x86_sse2_pslli_q:
5793 NewIntNo = Intrinsic::x86_sse2_psll_q;
5795 case Intrinsic::x86_sse2_psrli_w:
5796 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5798 case Intrinsic::x86_sse2_psrli_d:
5799 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5801 case Intrinsic::x86_sse2_psrli_q:
5802 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5804 case Intrinsic::x86_sse2_psrai_w:
5805 NewIntNo = Intrinsic::x86_sse2_psra_w;
5807 case Intrinsic::x86_sse2_psrai_d:
5808 NewIntNo = Intrinsic::x86_sse2_psra_d;
5811 ShAmtVT = MVT::v2i32;
5813 case Intrinsic::x86_mmx_pslli_w:
5814 NewIntNo = Intrinsic::x86_mmx_psll_w;
5816 case Intrinsic::x86_mmx_pslli_d:
5817 NewIntNo = Intrinsic::x86_mmx_psll_d;
5819 case Intrinsic::x86_mmx_pslli_q:
5820 NewIntNo = Intrinsic::x86_mmx_psll_q;
5822 case Intrinsic::x86_mmx_psrli_w:
5823 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5825 case Intrinsic::x86_mmx_psrli_d:
5826 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5828 case Intrinsic::x86_mmx_psrli_q:
5829 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5831 case Intrinsic::x86_mmx_psrai_w:
5832 NewIntNo = Intrinsic::x86_mmx_psra_w;
5834 case Intrinsic::x86_mmx_psrai_d:
5835 NewIntNo = Intrinsic::x86_mmx_psra_d;
5837 default: abort(); // Can't reach here.
5842 MVT VT = Op.getValueType();
5843 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5844 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5845 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5846 DAG.getConstant(NewIntNo, MVT::i32),
5847 Op.getOperand(1), ShAmt);
5852 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5853 // Depths > 0 not supported yet!
5854 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5857 // Just load the return address
5858 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5859 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5862 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5863 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5864 MFI->setFrameAddressIsTaken(true);
5865 MVT VT = Op.getValueType();
5866 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5867 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
5868 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
5870 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
5874 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5875 SelectionDAG &DAG) {
5876 return DAG.getIntPtrConstant(2*TD->getPointerSize());
5879 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5881 MachineFunction &MF = DAG.getMachineFunction();
5882 SDValue Chain = Op.getOperand(0);
5883 SDValue Offset = Op.getOperand(1);
5884 SDValue Handler = Op.getOperand(2);
5886 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
5888 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
5890 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5891 DAG.getIntPtrConstant(-TD->getPointerSize()));
5892 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5893 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5894 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
5895 MF.getRegInfo().addLiveOut(StoreAddrReg);
5897 return DAG.getNode(X86ISD::EH_RETURN,
5899 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
5902 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
5903 SelectionDAG &DAG) {
5904 SDValue Root = Op.getOperand(0);
5905 SDValue Trmp = Op.getOperand(1); // trampoline
5906 SDValue FPtr = Op.getOperand(2); // nested function
5907 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
5909 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5911 const X86InstrInfo *TII =
5912 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5914 if (Subtarget->is64Bit()) {
5915 SDValue OutChains[6];
5917 // Large code-model.
5919 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5920 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5922 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5923 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5925 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5927 // Load the pointer to the nested function into R11.
5928 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5929 SDValue Addr = Trmp;
5930 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5933 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5934 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5936 // Load the 'nest' parameter value into R10.
5937 // R10 is specified in X86CallingConv.td
5938 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5939 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5940 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5943 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5944 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5946 // Jump to the nested function.
5947 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5948 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5949 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5952 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5953 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5954 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5958 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5959 return DAG.getMergeValues(Ops, 2);
5961 const Function *Func =
5962 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5963 unsigned CC = Func->getCallingConv();
5968 assert(0 && "Unsupported calling convention");
5969 case CallingConv::C:
5970 case CallingConv::X86_StdCall: {
5971 // Pass 'nest' parameter in ECX.
5972 // Must be kept in sync with X86CallingConv.td
5975 // Check that ECX wasn't needed by an 'inreg' parameter.
5976 const FunctionType *FTy = Func->getFunctionType();
5977 const AttrListPtr &Attrs = Func->getAttributes();
5979 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5980 unsigned InRegCount = 0;
5983 for (FunctionType::param_iterator I = FTy->param_begin(),
5984 E = FTy->param_end(); I != E; ++I, ++Idx)
5985 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
5986 // FIXME: should only count parameters that are lowered to integers.
5987 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
5989 if (InRegCount > 2) {
5990 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5996 case CallingConv::X86_FastCall:
5997 case CallingConv::Fast:
5998 // Pass 'nest' parameter in EAX.
5999 // Must be kept in sync with X86CallingConv.td
6004 SDValue OutChains[4];
6007 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
6008 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
6010 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6011 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6012 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6015 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
6016 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
6018 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6019 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
6020 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
6021 TrmpAddr, 5, false, 1);
6023 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
6024 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
6027 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
6028 return DAG.getMergeValues(Ops, 2);
6032 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6034 The rounding mode is in bits 11:10 of FPSR, and has the following
6041 FLT_ROUNDS, on the other hand, expects the following:
6048 To perform the conversion, we do:
6049 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6052 MachineFunction &MF = DAG.getMachineFunction();
6053 const TargetMachine &TM = MF.getTarget();
6054 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6055 unsigned StackAlignment = TFI.getStackAlignment();
6056 MVT VT = Op.getValueType();
6058 // Save FP Control Word to stack slot
6059 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6060 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6062 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
6063 DAG.getEntryNode(), StackSlot);
6065 // Load FP Control Word from stack slot
6066 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
6068 // Transform as necessary
6070 DAG.getNode(ISD::SRL, MVT::i16,
6071 DAG.getNode(ISD::AND, MVT::i16,
6072 CWD, DAG.getConstant(0x800, MVT::i16)),
6073 DAG.getConstant(11, MVT::i8));
6075 DAG.getNode(ISD::SRL, MVT::i16,
6076 DAG.getNode(ISD::AND, MVT::i16,
6077 CWD, DAG.getConstant(0x400, MVT::i16)),
6078 DAG.getConstant(9, MVT::i8));
6081 DAG.getNode(ISD::AND, MVT::i16,
6082 DAG.getNode(ISD::ADD, MVT::i16,
6083 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
6084 DAG.getConstant(1, MVT::i16)),
6085 DAG.getConstant(3, MVT::i16));
6088 return DAG.getNode((VT.getSizeInBits() < 16 ?
6089 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
6092 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6093 MVT VT = Op.getValueType();
6095 unsigned NumBits = VT.getSizeInBits();
6097 Op = Op.getOperand(0);
6098 if (VT == MVT::i8) {
6099 // Zero extend to i32 since there is not an i8 bsr.
6101 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6104 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6105 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6106 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
6108 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6109 SmallVector<SDValue, 4> Ops;
6111 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6112 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6113 Ops.push_back(Op.getValue(1));
6114 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6116 // Finally xor with NumBits-1.
6117 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6120 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6124 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6125 MVT VT = Op.getValueType();
6127 unsigned NumBits = VT.getSizeInBits();
6129 Op = Op.getOperand(0);
6130 if (VT == MVT::i8) {
6132 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6135 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6136 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6137 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
6139 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6140 SmallVector<SDValue, 4> Ops;
6142 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6143 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6144 Ops.push_back(Op.getValue(1));
6145 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6148 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6152 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6153 MVT VT = Op.getValueType();
6154 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6156 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6157 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6158 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6159 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6160 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6162 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6163 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6164 // return AloBlo + AloBhi + AhiBlo;
6166 SDValue A = Op.getOperand(0);
6167 SDValue B = Op.getOperand(1);
6169 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6170 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6171 A, DAG.getConstant(32, MVT::i32));
6172 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6173 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6174 B, DAG.getConstant(32, MVT::i32));
6175 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6176 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6178 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6179 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6181 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6182 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6184 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6185 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6186 AloBhi, DAG.getConstant(32, MVT::i32));
6187 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6188 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6189 AhiBlo, DAG.getConstant(32, MVT::i32));
6190 SDValue Res = DAG.getNode(ISD::ADD, VT, AloBlo, AloBhi);
6191 Res = DAG.getNode(ISD::ADD, VT, Res, AhiBlo);
6196 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6197 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6198 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6199 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6200 // has only one use.
6201 SDNode *N = Op.getNode();
6202 SDValue LHS = N->getOperand(0);
6203 SDValue RHS = N->getOperand(1);
6204 unsigned BaseOp = 0;
6207 switch (Op.getOpcode()) {
6208 default: assert(0 && "Unknown ovf instruction!");
6210 BaseOp = X86ISD::ADD;
6214 BaseOp = X86ISD::ADD;
6218 BaseOp = X86ISD::SUB;
6222 BaseOp = X86ISD::SUB;
6226 BaseOp = X86ISD::SMUL;
6230 BaseOp = X86ISD::UMUL;
6235 // Also sets EFLAGS.
6236 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6237 SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS);
6240 DAG.getNode(X86ISD::SETCC, N->getValueType(1),
6241 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6243 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6247 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6248 MVT T = Op.getValueType();
6251 switch(T.getSimpleVT()) {
6253 assert(false && "Invalid value type!");
6254 case MVT::i8: Reg = X86::AL; size = 1; break;
6255 case MVT::i16: Reg = X86::AX; size = 2; break;
6256 case MVT::i32: Reg = X86::EAX; size = 4; break;
6258 assert(Subtarget->is64Bit() && "Node not type legal!");
6259 Reg = X86::RAX; size = 8;
6262 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
6263 Op.getOperand(2), SDValue());
6264 SDValue Ops[] = { cpIn.getValue(0),
6267 DAG.getTargetConstant(size, MVT::i8),
6269 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6270 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
6272 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
6276 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6277 SelectionDAG &DAG) {
6278 assert(Subtarget->is64Bit() && "Result not type legalized?");
6279 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6280 SDValue TheChain = Op.getOperand(0);
6281 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6282 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
6283 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64,
6285 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
6286 DAG.getConstant(32, MVT::i8));
6288 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp),
6291 return DAG.getMergeValues(Ops, 2);
6294 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6295 SDNode *Node = Op.getNode();
6296 MVT T = Node->getValueType(0);
6297 SDValue negOp = DAG.getNode(ISD::SUB, T,
6298 DAG.getConstant(0, T), Node->getOperand(2));
6299 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD,
6300 cast<AtomicSDNode>(Node)->getMemoryVT(),
6301 Node->getOperand(0),
6302 Node->getOperand(1), negOp,
6303 cast<AtomicSDNode>(Node)->getSrcValue(),
6304 cast<AtomicSDNode>(Node)->getAlignment());
6307 /// LowerOperation - Provide custom lowering hooks for some operations.
6309 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6310 switch (Op.getOpcode()) {
6311 default: assert(0 && "Should not custom lower this!");
6312 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6313 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6314 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6315 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6316 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6317 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6318 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6319 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6320 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6321 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6322 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6323 case ISD::SHL_PARTS:
6324 case ISD::SRA_PARTS:
6325 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6326 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6327 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6328 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6329 case ISD::FABS: return LowerFABS(Op, DAG);
6330 case ISD::FNEG: return LowerFNEG(Op, DAG);
6331 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6332 case ISD::SETCC: return LowerSETCC(Op, DAG);
6333 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6334 case ISD::SELECT: return LowerSELECT(Op, DAG);
6335 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6336 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6337 case ISD::CALL: return LowerCALL(Op, DAG);
6338 case ISD::RET: return LowerRET(Op, DAG);
6339 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6340 case ISD::VASTART: return LowerVASTART(Op, DAG);
6341 case ISD::VAARG: return LowerVAARG(Op, DAG);
6342 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6343 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6344 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6345 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6346 case ISD::FRAME_TO_ARGS_OFFSET:
6347 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6348 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6349 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6350 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6351 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6352 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6353 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6354 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6360 case ISD::UMULO: return LowerXALUO(Op, DAG);
6361 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6365 void X86TargetLowering::
6366 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6367 SelectionDAG &DAG, unsigned NewOp) {
6368 MVT T = Node->getValueType(0);
6369 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6371 SDValue Chain = Node->getOperand(0);
6372 SDValue In1 = Node->getOperand(1);
6373 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6374 Node->getOperand(2), DAG.getIntPtrConstant(0));
6375 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6376 Node->getOperand(2), DAG.getIntPtrConstant(1));
6377 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6378 // have a MemOperand. Pass the info through as a normal operand.
6379 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6380 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6381 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6382 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
6383 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6384 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6385 Results.push_back(Result.getValue(2));
6388 /// ReplaceNodeResults - Replace a node with an illegal result type
6389 /// with a new node built out of custom code.
6390 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6391 SmallVectorImpl<SDValue>&Results,
6392 SelectionDAG &DAG) {
6393 switch (N->getOpcode()) {
6395 assert(false && "Do not know how to custom type legalize this operation!");
6397 case ISD::FP_TO_SINT: {
6398 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
6399 SDValue FIST = Vals.first, StackSlot = Vals.second;
6400 if (FIST.getNode() != 0) {
6401 MVT VT = N->getValueType(0);
6402 // Return a load from the stack slot.
6403 Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0));
6407 case ISD::READCYCLECOUNTER: {
6408 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6409 SDValue TheChain = N->getOperand(0);
6410 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6411 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
6412 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32,
6414 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6415 SDValue Ops[] = { eax, edx };
6416 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2));
6417 Results.push_back(edx.getValue(1));
6420 case ISD::ATOMIC_CMP_SWAP: {
6421 MVT T = N->getValueType(0);
6422 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6423 SDValue cpInL, cpInH;
6424 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6425 DAG.getConstant(0, MVT::i32));
6426 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6427 DAG.getConstant(1, MVT::i32));
6428 cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue());
6429 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH,
6431 SDValue swapInL, swapInH;
6432 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6433 DAG.getConstant(0, MVT::i32));
6434 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6435 DAG.getConstant(1, MVT::i32));
6436 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL,
6438 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH,
6439 swapInL.getValue(1));
6440 SDValue Ops[] = { swapInH.getValue(0),
6442 swapInH.getValue(1) };
6443 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6444 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
6445 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
6446 Result.getValue(1));
6447 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
6448 cpOutL.getValue(2));
6449 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6450 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6451 Results.push_back(cpOutH.getValue(1));
6454 case ISD::ATOMIC_LOAD_ADD:
6455 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6457 case ISD::ATOMIC_LOAD_AND:
6458 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6460 case ISD::ATOMIC_LOAD_NAND:
6461 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6463 case ISD::ATOMIC_LOAD_OR:
6464 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6466 case ISD::ATOMIC_LOAD_SUB:
6467 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6469 case ISD::ATOMIC_LOAD_XOR:
6470 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6472 case ISD::ATOMIC_SWAP:
6473 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6478 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6480 default: return NULL;
6481 case X86ISD::BSF: return "X86ISD::BSF";
6482 case X86ISD::BSR: return "X86ISD::BSR";
6483 case X86ISD::SHLD: return "X86ISD::SHLD";
6484 case X86ISD::SHRD: return "X86ISD::SHRD";
6485 case X86ISD::FAND: return "X86ISD::FAND";
6486 case X86ISD::FOR: return "X86ISD::FOR";
6487 case X86ISD::FXOR: return "X86ISD::FXOR";
6488 case X86ISD::FSRL: return "X86ISD::FSRL";
6489 case X86ISD::FILD: return "X86ISD::FILD";
6490 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6491 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6492 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6493 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6494 case X86ISD::FLD: return "X86ISD::FLD";
6495 case X86ISD::FST: return "X86ISD::FST";
6496 case X86ISD::CALL: return "X86ISD::CALL";
6497 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6498 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6499 case X86ISD::BT: return "X86ISD::BT";
6500 case X86ISD::CMP: return "X86ISD::CMP";
6501 case X86ISD::COMI: return "X86ISD::COMI";
6502 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6503 case X86ISD::SETCC: return "X86ISD::SETCC";
6504 case X86ISD::CMOV: return "X86ISD::CMOV";
6505 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6506 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6507 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6508 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6509 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6510 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6511 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6512 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6513 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6514 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6515 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6516 case X86ISD::FMAX: return "X86ISD::FMAX";
6517 case X86ISD::FMIN: return "X86ISD::FMIN";
6518 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6519 case X86ISD::FRCP: return "X86ISD::FRCP";
6520 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6521 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6522 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6523 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6524 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6525 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6526 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6527 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6528 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6529 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6530 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6531 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6532 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
6533 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6534 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6535 case X86ISD::VSHL: return "X86ISD::VSHL";
6536 case X86ISD::VSRL: return "X86ISD::VSRL";
6537 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6538 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6539 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6540 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6541 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6542 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6543 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6544 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6545 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6546 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6547 case X86ISD::ADD: return "X86ISD::ADD";
6548 case X86ISD::SUB: return "X86ISD::SUB";
6549 case X86ISD::SMUL: return "X86ISD::SMUL";
6550 case X86ISD::UMUL: return "X86ISD::UMUL";
6554 // isLegalAddressingMode - Return true if the addressing mode represented
6555 // by AM is legal for this target, for a load/store of the specified type.
6556 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6557 const Type *Ty) const {
6558 // X86 supports extremely general addressing modes.
6560 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6561 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6565 // We can only fold this if we don't need an extra load.
6566 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6568 // If BaseGV requires a register, we cannot also have a BaseReg.
6569 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
6573 // X86-64 only supports addr of globals in small code model.
6574 if (Subtarget->is64Bit()) {
6575 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6577 // If lower 4G is not available, then we must use rip-relative addressing.
6578 if (AM.BaseOffs || AM.Scale > 1)
6589 // These scales always work.
6594 // These scales are formed with basereg+scalereg. Only accept if there is
6599 default: // Other stuff never works.
6607 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6608 if (!Ty1->isInteger() || !Ty2->isInteger())
6610 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6611 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6612 if (NumBits1 <= NumBits2)
6614 return Subtarget->is64Bit() || NumBits1 < 64;
6617 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6618 if (!VT1.isInteger() || !VT2.isInteger())
6620 unsigned NumBits1 = VT1.getSizeInBits();
6621 unsigned NumBits2 = VT2.getSizeInBits();
6622 if (NumBits1 <= NumBits2)
6624 return Subtarget->is64Bit() || NumBits1 < 64;
6627 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6628 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6629 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6630 /// are assumed to be legal.
6632 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6633 // Only do shuffles on 128-bit vector types for now.
6634 if (VT.getSizeInBits() == 64) return false;
6635 return (Mask.getNode()->getNumOperands() <= 4 ||
6636 isIdentityMask(Mask.getNode()) ||
6637 isIdentityMask(Mask.getNode(), true) ||
6638 isSplatMask(Mask.getNode()) ||
6639 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6640 X86::isUNPCKLMask(Mask.getNode()) ||
6641 X86::isUNPCKHMask(Mask.getNode()) ||
6642 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6643 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6647 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6648 MVT EVT, SelectionDAG &DAG) const {
6649 unsigned NumElts = BVOps.size();
6650 // Only do shuffles on 128-bit vector types for now.
6651 if (EVT.getSizeInBits() * NumElts == 64) return false;
6652 if (NumElts == 2) return true;
6654 return (isMOVLMask(&BVOps[0], 4) ||
6655 isCommutedMOVL(&BVOps[0], 4, true) ||
6656 isSHUFPMask(&BVOps[0], 4) ||
6657 isCommutedSHUFP(&BVOps[0], 4));
6662 //===----------------------------------------------------------------------===//
6663 // X86 Scheduler Hooks
6664 //===----------------------------------------------------------------------===//
6666 // private utility function
6668 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6669 MachineBasicBlock *MBB,
6677 TargetRegisterClass *RC,
6679 // For the atomic bitwise operator, we generate
6682 // ld t1 = [bitinstr.addr]
6683 // op t2 = t1, [bitinstr.val]
6685 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6687 // fallthrough -->nextMBB
6688 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6689 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6690 MachineFunction::iterator MBBIter = MBB;
6693 /// First build the CFG
6694 MachineFunction *F = MBB->getParent();
6695 MachineBasicBlock *thisMBB = MBB;
6696 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6697 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6698 F->insert(MBBIter, newMBB);
6699 F->insert(MBBIter, nextMBB);
6701 // Move all successors to thisMBB to nextMBB
6702 nextMBB->transferSuccessors(thisMBB);
6704 // Update thisMBB to fall through to newMBB
6705 thisMBB->addSuccessor(newMBB);
6707 // newMBB jumps to itself and fall through to nextMBB
6708 newMBB->addSuccessor(nextMBB);
6709 newMBB->addSuccessor(newMBB);
6711 // Insert instructions into newMBB based on incoming instruction
6712 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6713 MachineOperand& destOper = bInstr->getOperand(0);
6714 MachineOperand* argOpers[6];
6715 int numArgs = bInstr->getNumOperands() - 1;
6716 for (int i=0; i < numArgs; ++i)
6717 argOpers[i] = &bInstr->getOperand(i+1);
6719 // x86 address has 4 operands: base, index, scale, and displacement
6720 int lastAddrIndx = 3; // [0,3]
6723 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6724 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6725 for (int i=0; i <= lastAddrIndx; ++i)
6726 (*MIB).addOperand(*argOpers[i]);
6728 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6730 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6735 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6736 assert((argOpers[valArgIndx]->isReg() ||
6737 argOpers[valArgIndx]->isImm()) &&
6739 if (argOpers[valArgIndx]->isReg())
6740 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6742 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6744 (*MIB).addOperand(*argOpers[valArgIndx]);
6746 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6749 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6750 for (int i=0; i <= lastAddrIndx; ++i)
6751 (*MIB).addOperand(*argOpers[i]);
6753 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6754 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6756 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6760 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6762 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6766 // private utility function: 64 bit atomics on 32 bit host.
6768 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
6769 MachineBasicBlock *MBB,
6775 // For the atomic bitwise operator, we generate
6776 // thisMBB (instructions are in pairs, except cmpxchg8b)
6777 // ld t1,t2 = [bitinstr.addr]
6779 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
6780 // op t5, t6 <- out1, out2, [bitinstr.val]
6781 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
6782 // mov ECX, EBX <- t5, t6
6783 // mov EAX, EDX <- t1, t2
6784 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
6785 // mov t3, t4 <- EAX, EDX
6787 // result in out1, out2
6788 // fallthrough -->nextMBB
6790 const TargetRegisterClass *RC = X86::GR32RegisterClass;
6791 const unsigned LoadOpc = X86::MOV32rm;
6792 const unsigned copyOpc = X86::MOV32rr;
6793 const unsigned NotOpc = X86::NOT32r;
6794 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6795 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6796 MachineFunction::iterator MBBIter = MBB;
6799 /// First build the CFG
6800 MachineFunction *F = MBB->getParent();
6801 MachineBasicBlock *thisMBB = MBB;
6802 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6803 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6804 F->insert(MBBIter, newMBB);
6805 F->insert(MBBIter, nextMBB);
6807 // Move all successors to thisMBB to nextMBB
6808 nextMBB->transferSuccessors(thisMBB);
6810 // Update thisMBB to fall through to newMBB
6811 thisMBB->addSuccessor(newMBB);
6813 // newMBB jumps to itself and fall through to nextMBB
6814 newMBB->addSuccessor(nextMBB);
6815 newMBB->addSuccessor(newMBB);
6817 // Insert instructions into newMBB based on incoming instruction
6818 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
6819 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
6820 MachineOperand& dest1Oper = bInstr->getOperand(0);
6821 MachineOperand& dest2Oper = bInstr->getOperand(1);
6822 MachineOperand* argOpers[6];
6823 for (int i=0; i < 6; ++i)
6824 argOpers[i] = &bInstr->getOperand(i+2);
6826 // x86 address has 4 operands: base, index, scale, and displacement
6827 int lastAddrIndx = 3; // [0,3]
6829 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6830 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
6831 for (int i=0; i <= lastAddrIndx; ++i)
6832 (*MIB).addOperand(*argOpers[i]);
6833 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6834 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6835 // add 4 to displacement.
6836 for (int i=0; i <= lastAddrIndx-1; ++i)
6837 (*MIB).addOperand(*argOpers[i]);
6838 MachineOperand newOp3 = *(argOpers[3]);
6840 newOp3.setImm(newOp3.getImm()+4);
6842 newOp3.setOffset(newOp3.getOffset()+4);
6843 (*MIB).addOperand(newOp3);
6845 // t3/4 are defined later, at the bottom of the loop
6846 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
6847 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
6848 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
6849 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
6850 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
6851 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
6853 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
6854 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
6856 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
6857 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
6863 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
6865 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
6866 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
6867 if (argOpers[4]->isReg())
6868 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
6870 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
6871 if (regOpcL != X86::MOV32rr)
6873 (*MIB).addOperand(*argOpers[4]);
6874 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
6875 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
6876 if (argOpers[5]->isReg())
6877 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
6879 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
6880 if (regOpcH != X86::MOV32rr)
6882 (*MIB).addOperand(*argOpers[5]);
6884 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
6886 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
6889 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
6891 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
6894 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
6895 for (int i=0; i <= lastAddrIndx; ++i)
6896 (*MIB).addOperand(*argOpers[i]);
6898 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6899 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6901 MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
6902 MIB.addReg(X86::EAX);
6903 MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
6904 MIB.addReg(X86::EDX);
6907 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6909 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6913 // private utility function
6915 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6916 MachineBasicBlock *MBB,
6918 // For the atomic min/max operator, we generate
6921 // ld t1 = [min/max.addr]
6922 // mov t2 = [min/max.val]
6924 // cmov[cond] t2 = t1
6926 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6928 // fallthrough -->nextMBB
6930 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6931 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6932 MachineFunction::iterator MBBIter = MBB;
6935 /// First build the CFG
6936 MachineFunction *F = MBB->getParent();
6937 MachineBasicBlock *thisMBB = MBB;
6938 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6939 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6940 F->insert(MBBIter, newMBB);
6941 F->insert(MBBIter, nextMBB);
6943 // Move all successors to thisMBB to nextMBB
6944 nextMBB->transferSuccessors(thisMBB);
6946 // Update thisMBB to fall through to newMBB
6947 thisMBB->addSuccessor(newMBB);
6949 // newMBB jumps to newMBB and fall through to nextMBB
6950 newMBB->addSuccessor(nextMBB);
6951 newMBB->addSuccessor(newMBB);
6953 // Insert instructions into newMBB based on incoming instruction
6954 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6955 MachineOperand& destOper = mInstr->getOperand(0);
6956 MachineOperand* argOpers[6];
6957 int numArgs = mInstr->getNumOperands() - 1;
6958 for (int i=0; i < numArgs; ++i)
6959 argOpers[i] = &mInstr->getOperand(i+1);
6961 // x86 address has 4 operands: base, index, scale, and displacement
6962 int lastAddrIndx = 3; // [0,3]
6965 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6966 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6967 for (int i=0; i <= lastAddrIndx; ++i)
6968 (*MIB).addOperand(*argOpers[i]);
6970 // We only support register and immediate values
6971 assert((argOpers[valArgIndx]->isReg() ||
6972 argOpers[valArgIndx]->isImm()) &&
6975 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6976 if (argOpers[valArgIndx]->isReg())
6977 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6979 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6980 (*MIB).addOperand(*argOpers[valArgIndx]);
6982 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6985 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6990 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6991 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6995 // Cmp and exchange if none has modified the memory location
6996 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6997 for (int i=0; i <= lastAddrIndx; ++i)
6998 (*MIB).addOperand(*argOpers[i]);
7000 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7001 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7003 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
7004 MIB.addReg(X86::EAX);
7007 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
7009 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7015 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7016 MachineBasicBlock *BB) {
7017 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7018 switch (MI->getOpcode()) {
7019 default: assert(false && "Unexpected instr type to insert");
7020 case X86::CMOV_V1I64:
7021 case X86::CMOV_FR32:
7022 case X86::CMOV_FR64:
7023 case X86::CMOV_V4F32:
7024 case X86::CMOV_V2F64:
7025 case X86::CMOV_V2I64: {
7026 // To "insert" a SELECT_CC instruction, we actually have to insert the
7027 // diamond control-flow pattern. The incoming instruction knows the
7028 // destination vreg to set, the condition code register to branch on, the
7029 // true/false values to select between, and a branch opcode to use.
7030 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7031 MachineFunction::iterator It = BB;
7037 // cmpTY ccX, r1, r2
7039 // fallthrough --> copy0MBB
7040 MachineBasicBlock *thisMBB = BB;
7041 MachineFunction *F = BB->getParent();
7042 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7043 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7045 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7046 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
7047 F->insert(It, copy0MBB);
7048 F->insert(It, sinkMBB);
7049 // Update machine-CFG edges by transferring all successors of the current
7050 // block to the new block which will contain the Phi node for the select.
7051 sinkMBB->transferSuccessors(BB);
7053 // Add the true and fallthrough blocks as its successors.
7054 BB->addSuccessor(copy0MBB);
7055 BB->addSuccessor(sinkMBB);
7058 // %FalseValue = ...
7059 // # fallthrough to sinkMBB
7062 // Update machine-CFG edges
7063 BB->addSuccessor(sinkMBB);
7066 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7069 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
7070 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7071 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7073 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7077 case X86::FP32_TO_INT16_IN_MEM:
7078 case X86::FP32_TO_INT32_IN_MEM:
7079 case X86::FP32_TO_INT64_IN_MEM:
7080 case X86::FP64_TO_INT16_IN_MEM:
7081 case X86::FP64_TO_INT32_IN_MEM:
7082 case X86::FP64_TO_INT64_IN_MEM:
7083 case X86::FP80_TO_INT16_IN_MEM:
7084 case X86::FP80_TO_INT32_IN_MEM:
7085 case X86::FP80_TO_INT64_IN_MEM: {
7086 // Change the floating point control register to use "round towards zero"
7087 // mode when truncating to an integer value.
7088 MachineFunction *F = BB->getParent();
7089 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7090 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7092 // Load the old value of the high byte of the control word...
7094 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7095 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
7097 // Set the high part to be round to zero...
7098 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
7101 // Reload the modified control word now...
7102 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7104 // Restore the memory image of control word to original value
7105 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
7108 // Get the X86 opcode to use.
7110 switch (MI->getOpcode()) {
7111 default: assert(0 && "illegal opcode!");
7112 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7113 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7114 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7115 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7116 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7117 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7118 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7119 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7120 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7124 MachineOperand &Op = MI->getOperand(0);
7126 AM.BaseType = X86AddressMode::RegBase;
7127 AM.Base.Reg = Op.getReg();
7129 AM.BaseType = X86AddressMode::FrameIndexBase;
7130 AM.Base.FrameIndex = Op.getIndex();
7132 Op = MI->getOperand(1);
7134 AM.Scale = Op.getImm();
7135 Op = MI->getOperand(2);
7137 AM.IndexReg = Op.getImm();
7138 Op = MI->getOperand(3);
7139 if (Op.isGlobal()) {
7140 AM.GV = Op.getGlobal();
7142 AM.Disp = Op.getImm();
7144 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
7145 .addReg(MI->getOperand(4).getReg());
7147 // Reload the original control word now.
7148 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7150 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7153 case X86::ATOMAND32:
7154 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7155 X86::AND32ri, X86::MOV32rm,
7156 X86::LCMPXCHG32, X86::MOV32rr,
7157 X86::NOT32r, X86::EAX,
7158 X86::GR32RegisterClass);
7160 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7161 X86::OR32ri, X86::MOV32rm,
7162 X86::LCMPXCHG32, X86::MOV32rr,
7163 X86::NOT32r, X86::EAX,
7164 X86::GR32RegisterClass);
7165 case X86::ATOMXOR32:
7166 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7167 X86::XOR32ri, X86::MOV32rm,
7168 X86::LCMPXCHG32, X86::MOV32rr,
7169 X86::NOT32r, X86::EAX,
7170 X86::GR32RegisterClass);
7171 case X86::ATOMNAND32:
7172 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7173 X86::AND32ri, X86::MOV32rm,
7174 X86::LCMPXCHG32, X86::MOV32rr,
7175 X86::NOT32r, X86::EAX,
7176 X86::GR32RegisterClass, true);
7177 case X86::ATOMMIN32:
7178 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7179 case X86::ATOMMAX32:
7180 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7181 case X86::ATOMUMIN32:
7182 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7183 case X86::ATOMUMAX32:
7184 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7186 case X86::ATOMAND16:
7187 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7188 X86::AND16ri, X86::MOV16rm,
7189 X86::LCMPXCHG16, X86::MOV16rr,
7190 X86::NOT16r, X86::AX,
7191 X86::GR16RegisterClass);
7193 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7194 X86::OR16ri, X86::MOV16rm,
7195 X86::LCMPXCHG16, X86::MOV16rr,
7196 X86::NOT16r, X86::AX,
7197 X86::GR16RegisterClass);
7198 case X86::ATOMXOR16:
7199 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7200 X86::XOR16ri, X86::MOV16rm,
7201 X86::LCMPXCHG16, X86::MOV16rr,
7202 X86::NOT16r, X86::AX,
7203 X86::GR16RegisterClass);
7204 case X86::ATOMNAND16:
7205 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7206 X86::AND16ri, X86::MOV16rm,
7207 X86::LCMPXCHG16, X86::MOV16rr,
7208 X86::NOT16r, X86::AX,
7209 X86::GR16RegisterClass, true);
7210 case X86::ATOMMIN16:
7211 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7212 case X86::ATOMMAX16:
7213 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7214 case X86::ATOMUMIN16:
7215 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7216 case X86::ATOMUMAX16:
7217 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7220 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7221 X86::AND8ri, X86::MOV8rm,
7222 X86::LCMPXCHG8, X86::MOV8rr,
7223 X86::NOT8r, X86::AL,
7224 X86::GR8RegisterClass);
7226 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7227 X86::OR8ri, X86::MOV8rm,
7228 X86::LCMPXCHG8, X86::MOV8rr,
7229 X86::NOT8r, X86::AL,
7230 X86::GR8RegisterClass);
7232 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7233 X86::XOR8ri, X86::MOV8rm,
7234 X86::LCMPXCHG8, X86::MOV8rr,
7235 X86::NOT8r, X86::AL,
7236 X86::GR8RegisterClass);
7237 case X86::ATOMNAND8:
7238 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7239 X86::AND8ri, X86::MOV8rm,
7240 X86::LCMPXCHG8, X86::MOV8rr,
7241 X86::NOT8r, X86::AL,
7242 X86::GR8RegisterClass, true);
7243 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7244 // This group is for 64-bit host.
7245 case X86::ATOMAND64:
7246 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7247 X86::AND64ri32, X86::MOV64rm,
7248 X86::LCMPXCHG64, X86::MOV64rr,
7249 X86::NOT64r, X86::RAX,
7250 X86::GR64RegisterClass);
7252 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7253 X86::OR64ri32, X86::MOV64rm,
7254 X86::LCMPXCHG64, X86::MOV64rr,
7255 X86::NOT64r, X86::RAX,
7256 X86::GR64RegisterClass);
7257 case X86::ATOMXOR64:
7258 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7259 X86::XOR64ri32, X86::MOV64rm,
7260 X86::LCMPXCHG64, X86::MOV64rr,
7261 X86::NOT64r, X86::RAX,
7262 X86::GR64RegisterClass);
7263 case X86::ATOMNAND64:
7264 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7265 X86::AND64ri32, X86::MOV64rm,
7266 X86::LCMPXCHG64, X86::MOV64rr,
7267 X86::NOT64r, X86::RAX,
7268 X86::GR64RegisterClass, true);
7269 case X86::ATOMMIN64:
7270 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7271 case X86::ATOMMAX64:
7272 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7273 case X86::ATOMUMIN64:
7274 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7275 case X86::ATOMUMAX64:
7276 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7278 // This group does 64-bit operations on a 32-bit host.
7279 case X86::ATOMAND6432:
7280 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7281 X86::AND32rr, X86::AND32rr,
7282 X86::AND32ri, X86::AND32ri,
7284 case X86::ATOMOR6432:
7285 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7286 X86::OR32rr, X86::OR32rr,
7287 X86::OR32ri, X86::OR32ri,
7289 case X86::ATOMXOR6432:
7290 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7291 X86::XOR32rr, X86::XOR32rr,
7292 X86::XOR32ri, X86::XOR32ri,
7294 case X86::ATOMNAND6432:
7295 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7296 X86::AND32rr, X86::AND32rr,
7297 X86::AND32ri, X86::AND32ri,
7299 case X86::ATOMADD6432:
7300 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7301 X86::ADD32rr, X86::ADC32rr,
7302 X86::ADD32ri, X86::ADC32ri,
7304 case X86::ATOMSUB6432:
7305 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7306 X86::SUB32rr, X86::SBB32rr,
7307 X86::SUB32ri, X86::SBB32ri,
7309 case X86::ATOMSWAP6432:
7310 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7311 X86::MOV32rr, X86::MOV32rr,
7312 X86::MOV32ri, X86::MOV32ri,
7317 //===----------------------------------------------------------------------===//
7318 // X86 Optimization Hooks
7319 //===----------------------------------------------------------------------===//
7321 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7325 const SelectionDAG &DAG,
7326 unsigned Depth) const {
7327 unsigned Opc = Op.getOpcode();
7328 assert((Opc >= ISD::BUILTIN_OP_END ||
7329 Opc == ISD::INTRINSIC_WO_CHAIN ||
7330 Opc == ISD::INTRINSIC_W_CHAIN ||
7331 Opc == ISD::INTRINSIC_VOID) &&
7332 "Should use MaskedValueIsZero if you don't know whether Op"
7333 " is a target node!");
7335 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7339 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7340 Mask.getBitWidth() - 1);
7345 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7346 /// node is a GlobalAddress + offset.
7347 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7348 GlobalValue* &GA, int64_t &Offset) const{
7349 if (N->getOpcode() == X86ISD::Wrapper) {
7350 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7351 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7352 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7356 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7359 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7360 const TargetLowering &TLI) {
7363 if (TLI.isGAPlusOffset(Base, GV, Offset))
7364 return (GV->getAlignment() >= N && (Offset % N) == 0);
7365 // DAG combine handles the stack object case.
7369 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7370 unsigned NumElems, MVT EVT,
7372 SelectionDAG &DAG, MachineFrameInfo *MFI,
7373 const TargetLowering &TLI) {
7375 for (unsigned i = 0; i < NumElems; ++i) {
7376 SDValue Idx = PermMask.getOperand(i);
7377 if (Idx.getOpcode() == ISD::UNDEF) {
7383 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7384 if (!Elt.getNode() ||
7385 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7388 Base = Elt.getNode();
7389 if (Base->getOpcode() == ISD::UNDEF)
7393 if (Elt.getOpcode() == ISD::UNDEF)
7396 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7397 EVT.getSizeInBits()/8, i, MFI))
7403 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7404 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7405 /// if the load addresses are consecutive, non-overlapping, and in the right
7407 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7408 const TargetLowering &TLI) {
7409 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7410 MVT VT = N->getValueType(0);
7411 MVT EVT = VT.getVectorElementType();
7412 SDValue PermMask = N->getOperand(2);
7413 unsigned NumElems = PermMask.getNumOperands();
7414 SDNode *Base = NULL;
7415 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
7419 LoadSDNode *LD = cast<LoadSDNode>(Base);
7420 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
7421 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7422 LD->getSrcValueOffset(), LD->isVolatile());
7423 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7424 LD->getSrcValueOffset(), LD->isVolatile(),
7425 LD->getAlignment());
7428 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
7429 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7430 const X86Subtarget *Subtarget,
7431 const TargetLowering &TLI) {
7432 unsigned NumOps = N->getNumOperands();
7434 // Ignore single operand BUILD_VECTOR.
7438 MVT VT = N->getValueType(0);
7439 MVT EVT = VT.getVectorElementType();
7440 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
7441 // We are looking for load i64 and zero extend. We want to transform
7442 // it before legalizer has a chance to expand it. Also look for i64
7443 // BUILD_PAIR bit casted to f64.
7445 // This must be an insertion into a zero vector.
7446 SDValue HighElt = N->getOperand(1);
7447 if (!isZeroNode(HighElt))
7450 // Value must be a load.
7451 SDNode *Base = N->getOperand(0).getNode();
7452 if (!isa<LoadSDNode>(Base)) {
7453 if (Base->getOpcode() != ISD::BIT_CONVERT)
7455 Base = Base->getOperand(0).getNode();
7456 if (!isa<LoadSDNode>(Base))
7460 // Transform it into VZEXT_LOAD addr.
7461 LoadSDNode *LD = cast<LoadSDNode>(Base);
7463 // Load must not be an extload.
7464 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
7467 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
7468 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7469 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
7470 DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
7474 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7475 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7476 const X86Subtarget *Subtarget) {
7477 SDValue Cond = N->getOperand(0);
7479 // If we have SSE[12] support, try to form min/max nodes.
7480 if (Subtarget->hasSSE2() &&
7481 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
7482 if (Cond.getOpcode() == ISD::SETCC) {
7483 // Get the LHS/RHS of the select.
7484 SDValue LHS = N->getOperand(1);
7485 SDValue RHS = N->getOperand(2);
7486 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7488 unsigned Opcode = 0;
7489 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7492 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7495 if (!UnsafeFPMath) break;
7497 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7499 Opcode = X86ISD::FMIN;
7502 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7505 if (!UnsafeFPMath) break;
7507 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7509 Opcode = X86ISD::FMAX;
7512 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7515 case ISD::SETOGT: // (X > Y) ? Y : X -> min
7518 if (!UnsafeFPMath) break;
7520 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
7522 Opcode = X86ISD::FMIN;
7525 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
7528 if (!UnsafeFPMath) break;
7530 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
7532 Opcode = X86ISD::FMAX;
7538 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
7546 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
7547 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
7548 const X86Subtarget *Subtarget) {
7549 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
7550 // the FP state in cases where an emms may be missing.
7551 // A preferable solution to the general problem is to figure out the right
7552 // places to insert EMMS. This qualifies as a quick hack.
7553 StoreSDNode *St = cast<StoreSDNode>(N);
7554 if (St->getValue().getValueType().isVector() &&
7555 St->getValue().getValueType().getSizeInBits() == 64 &&
7556 isa<LoadSDNode>(St->getValue()) &&
7557 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
7558 St->getChain().hasOneUse() && !St->isVolatile()) {
7559 SDNode* LdVal = St->getValue().getNode();
7561 int TokenFactorIndex = -1;
7562 SmallVector<SDValue, 8> Ops;
7563 SDNode* ChainVal = St->getChain().getNode();
7564 // Must be a store of a load. We currently handle two cases: the load
7565 // is a direct child, and it's under an intervening TokenFactor. It is
7566 // possible to dig deeper under nested TokenFactors.
7567 if (ChainVal == LdVal)
7568 Ld = cast<LoadSDNode>(St->getChain());
7569 else if (St->getValue().hasOneUse() &&
7570 ChainVal->getOpcode() == ISD::TokenFactor) {
7571 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
7572 if (ChainVal->getOperand(i).getNode() == LdVal) {
7573 TokenFactorIndex = i;
7574 Ld = cast<LoadSDNode>(St->getValue());
7576 Ops.push_back(ChainVal->getOperand(i));
7580 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
7581 if (Subtarget->is64Bit()) {
7582 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
7583 Ld->getBasePtr(), Ld->getSrcValue(),
7584 Ld->getSrcValueOffset(), Ld->isVolatile(),
7585 Ld->getAlignment());
7586 SDValue NewChain = NewLd.getValue(1);
7587 if (TokenFactorIndex != -1) {
7588 Ops.push_back(NewChain);
7589 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7592 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
7593 St->getSrcValue(), St->getSrcValueOffset(),
7594 St->isVolatile(), St->getAlignment());
7597 // Otherwise, lower to two 32-bit copies.
7598 SDValue LoAddr = Ld->getBasePtr();
7599 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7600 DAG.getConstant(4, MVT::i32));
7602 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
7603 Ld->getSrcValue(), Ld->getSrcValueOffset(),
7604 Ld->isVolatile(), Ld->getAlignment());
7605 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
7606 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
7608 MinAlign(Ld->getAlignment(), 4));
7610 SDValue NewChain = LoLd.getValue(1);
7611 if (TokenFactorIndex != -1) {
7612 Ops.push_back(LoLd);
7613 Ops.push_back(HiLd);
7614 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7618 LoAddr = St->getBasePtr();
7619 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7620 DAG.getConstant(4, MVT::i32));
7622 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
7623 St->getSrcValue(), St->getSrcValueOffset(),
7624 St->isVolatile(), St->getAlignment());
7625 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
7627 St->getSrcValueOffset() + 4,
7629 MinAlign(St->getAlignment(), 4));
7630 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
7636 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
7637 /// X86ISD::FXOR nodes.
7638 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
7639 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
7640 // F[X]OR(0.0, x) -> x
7641 // F[X]OR(x, 0.0) -> x
7642 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7643 if (C->getValueAPF().isPosZero())
7644 return N->getOperand(1);
7645 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7646 if (C->getValueAPF().isPosZero())
7647 return N->getOperand(0);
7651 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
7652 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
7653 // FAND(0.0, x) -> 0.0
7654 // FAND(x, 0.0) -> 0.0
7655 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7656 if (C->getValueAPF().isPosZero())
7657 return N->getOperand(0);
7658 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7659 if (C->getValueAPF().isPosZero())
7660 return N->getOperand(1);
7665 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7666 DAGCombinerInfo &DCI) const {
7667 SelectionDAG &DAG = DCI.DAG;
7668 switch (N->getOpcode()) {
7670 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7671 case ISD::BUILD_VECTOR:
7672 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7673 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7674 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7676 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7677 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7683 //===----------------------------------------------------------------------===//
7684 // X86 Inline Assembly Support
7685 //===----------------------------------------------------------------------===//
7687 /// getConstraintType - Given a constraint letter, return the type of
7688 /// constraint it is for this target.
7689 X86TargetLowering::ConstraintType
7690 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7691 if (Constraint.size() == 1) {
7692 switch (Constraint[0]) {
7704 return C_RegisterClass;
7709 return TargetLowering::getConstraintType(Constraint);
7712 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7713 /// with another that has more specific requirements based on the type of the
7714 /// corresponding operand.
7715 const char *X86TargetLowering::
7716 LowerXConstraint(MVT ConstraintVT) const {
7717 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7718 // 'f' like normal targets.
7719 if (ConstraintVT.isFloatingPoint()) {
7720 if (Subtarget->hasSSE2())
7722 if (Subtarget->hasSSE1())
7726 return TargetLowering::LowerXConstraint(ConstraintVT);
7729 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7730 /// vector. If it is invalid, don't add anything to Ops.
7731 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7734 std::vector<SDValue>&Ops,
7735 SelectionDAG &DAG) const {
7736 SDValue Result(0, 0);
7738 switch (Constraint) {
7741 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7742 if (C->getZExtValue() <= 31) {
7743 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7749 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7750 if (C->getZExtValue() <= 63) {
7751 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7758 if (C->getZExtValue() <= 255) {
7759 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7765 // Literal immediates are always ok.
7766 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7767 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
7771 // If we are in non-pic codegen mode, we allow the address of a global (with
7772 // an optional displacement) to be used with 'i'.
7773 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7776 // Match either (GA) or (GA+C)
7778 Offset = GA->getOffset();
7779 } else if (Op.getOpcode() == ISD::ADD) {
7780 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7781 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7783 Offset = GA->getOffset()+C->getZExtValue();
7785 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7786 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7788 Offset = GA->getOffset()+C->getZExtValue();
7796 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG);
7798 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7804 // Otherwise, not valid for this mode.
7809 if (Result.getNode()) {
7810 Ops.push_back(Result);
7813 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
7817 std::vector<unsigned> X86TargetLowering::
7818 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7820 if (Constraint.size() == 1) {
7821 // FIXME: not handling fp-stack yet!
7822 switch (Constraint[0]) { // GCC X86 Constraint Letters
7823 default: break; // Unknown constraint letter
7824 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7827 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7828 else if (VT == MVT::i16)
7829 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7830 else if (VT == MVT::i8)
7831 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
7832 else if (VT == MVT::i64)
7833 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7838 return std::vector<unsigned>();
7841 std::pair<unsigned, const TargetRegisterClass*>
7842 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7844 // First, see if this is a constraint that directly corresponds to an LLVM
7846 if (Constraint.size() == 1) {
7847 // GCC Constraint Letters
7848 switch (Constraint[0]) {
7850 case 'r': // GENERAL_REGS
7851 case 'R': // LEGACY_REGS
7852 case 'l': // INDEX_REGS
7854 return std::make_pair(0U, X86::GR8RegisterClass);
7856 return std::make_pair(0U, X86::GR16RegisterClass);
7857 if (VT == MVT::i32 || !Subtarget->is64Bit())
7858 return std::make_pair(0U, X86::GR32RegisterClass);
7859 return std::make_pair(0U, X86::GR64RegisterClass);
7860 case 'f': // FP Stack registers.
7861 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7862 // value to the correct fpstack register class.
7863 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7864 return std::make_pair(0U, X86::RFP32RegisterClass);
7865 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7866 return std::make_pair(0U, X86::RFP64RegisterClass);
7867 return std::make_pair(0U, X86::RFP80RegisterClass);
7868 case 'y': // MMX_REGS if MMX allowed.
7869 if (!Subtarget->hasMMX()) break;
7870 return std::make_pair(0U, X86::VR64RegisterClass);
7871 case 'Y': // SSE_REGS if SSE2 allowed
7872 if (!Subtarget->hasSSE2()) break;
7874 case 'x': // SSE_REGS if SSE1 allowed
7875 if (!Subtarget->hasSSE1()) break;
7877 switch (VT.getSimpleVT()) {
7879 // Scalar SSE types.
7882 return std::make_pair(0U, X86::FR32RegisterClass);
7885 return std::make_pair(0U, X86::FR64RegisterClass);
7893 return std::make_pair(0U, X86::VR128RegisterClass);
7899 // Use the default implementation in TargetLowering to convert the register
7900 // constraint into a member of a register class.
7901 std::pair<unsigned, const TargetRegisterClass*> Res;
7902 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7904 // Not found as a standard register?
7905 if (Res.second == 0) {
7906 // GCC calls "st(0)" just plain "st".
7907 if (StringsEqualNoCase("{st}", Constraint)) {
7908 Res.first = X86::ST0;
7909 Res.second = X86::RFP80RegisterClass;
7911 // 'A' means EAX + EDX.
7912 if (Constraint == "A") {
7913 Res.first = X86::EAX;
7914 Res.second = X86::GRADRegisterClass;
7919 // Otherwise, check to see if this is a register class of the wrong value
7920 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7921 // turn into {ax},{dx}.
7922 if (Res.second->hasType(VT))
7923 return Res; // Correct type already, nothing to do.
7925 // All of the single-register GCC register classes map their values onto
7926 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7927 // really want an 8-bit or 32-bit register, map to the appropriate register
7928 // class and return the appropriate register.
7929 if (Res.second == X86::GR16RegisterClass) {
7930 if (VT == MVT::i8) {
7931 unsigned DestReg = 0;
7932 switch (Res.first) {
7934 case X86::AX: DestReg = X86::AL; break;
7935 case X86::DX: DestReg = X86::DL; break;
7936 case X86::CX: DestReg = X86::CL; break;
7937 case X86::BX: DestReg = X86::BL; break;
7940 Res.first = DestReg;
7941 Res.second = Res.second = X86::GR8RegisterClass;
7943 } else if (VT == MVT::i32) {
7944 unsigned DestReg = 0;
7945 switch (Res.first) {
7947 case X86::AX: DestReg = X86::EAX; break;
7948 case X86::DX: DestReg = X86::EDX; break;
7949 case X86::CX: DestReg = X86::ECX; break;
7950 case X86::BX: DestReg = X86::EBX; break;
7951 case X86::SI: DestReg = X86::ESI; break;
7952 case X86::DI: DestReg = X86::EDI; break;
7953 case X86::BP: DestReg = X86::EBP; break;
7954 case X86::SP: DestReg = X86::ESP; break;
7957 Res.first = DestReg;
7958 Res.second = Res.second = X86::GR32RegisterClass;
7960 } else if (VT == MVT::i64) {
7961 unsigned DestReg = 0;
7962 switch (Res.first) {
7964 case X86::AX: DestReg = X86::RAX; break;
7965 case X86::DX: DestReg = X86::RDX; break;
7966 case X86::CX: DestReg = X86::RCX; break;
7967 case X86::BX: DestReg = X86::RBX; break;
7968 case X86::SI: DestReg = X86::RSI; break;
7969 case X86::DI: DestReg = X86::RDI; break;
7970 case X86::BP: DestReg = X86::RBP; break;
7971 case X86::SP: DestReg = X86::RSP; break;
7974 Res.first = DestReg;
7975 Res.second = Res.second = X86::GR64RegisterClass;
7978 } else if (Res.second == X86::FR32RegisterClass ||
7979 Res.second == X86::FR64RegisterClass ||
7980 Res.second == X86::VR128RegisterClass) {
7981 // Handle references to XMM physical registers that got mapped into the
7982 // wrong class. This can happen with constraints like {xmm0} where the
7983 // target independent register mapper will just pick the first match it can
7984 // find, ignoring the required type.
7986 Res.second = X86::FR32RegisterClass;
7987 else if (VT == MVT::f64)
7988 Res.second = X86::FR64RegisterClass;
7989 else if (X86::VR128RegisterClass->hasType(VT))
7990 Res.second = X86::VR128RegisterClass;
7996 //===----------------------------------------------------------------------===//
7997 // X86 Widen vector type
7998 //===----------------------------------------------------------------------===//
8000 /// getWidenVectorType: given a vector type, returns the type to widen
8001 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
8002 /// If there is no vector type that we want to widen to, returns MVT::Other
8003 /// When and where to widen is target dependent based on the cost of
8004 /// scalarizing vs using the wider vector type.
8006 MVT X86TargetLowering::getWidenVectorType(MVT VT) {
8007 assert(VT.isVector());
8008 if (isTypeLegal(VT))
8011 // TODO: In computeRegisterProperty, we can compute the list of legal vector
8012 // type based on element type. This would speed up our search (though
8013 // it may not be worth it since the size of the list is relatively
8015 MVT EltVT = VT.getVectorElementType();
8016 unsigned NElts = VT.getVectorNumElements();
8018 // On X86, it make sense to widen any vector wider than 1
8022 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
8023 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
8024 MVT SVT = (MVT::SimpleValueType)nVT;
8026 if (isTypeLegal(SVT) &&
8027 SVT.getVectorElementType() == EltVT &&
8028 SVT.getVectorNumElements() > NElts)