1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
62 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
63 SelectionDAG &DAG, SDLoc dl,
64 unsigned vectorWidth) {
65 assert((vectorWidth == 128 || vectorWidth == 256) &&
66 "Unsupported vector width");
67 EVT VT = Vec.getValueType();
68 EVT ElVT = VT.getVectorElementType();
69 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
71 VT.getVectorNumElements()/Factor);
73 // Extract from UNDEF is UNDEF.
74 if (Vec.getOpcode() == ISD::UNDEF)
75 return DAG.getUNDEF(ResultVT);
77 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
78 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
80 // This is the index of the first element of the vectorWidth-bit chunk
82 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
85 // If the input is a buildvector just emit a smaller one.
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
88 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
90 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
97 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
98 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
99 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
100 /// instructions or a simple subregister reference. Idx is an index in the
101 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
102 /// lowering EXTRACT_VECTOR_ELT operations easier.
103 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
104 SelectionDAG &DAG, SDLoc dl) {
105 assert((Vec.getValueType().is256BitVector() ||
106 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
107 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
110 /// Generate a DAG to grab 256-bits from a 512-bit vector.
111 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
112 SelectionDAG &DAG, SDLoc dl) {
113 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
114 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
117 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
118 unsigned IdxVal, SelectionDAG &DAG,
119 SDLoc dl, unsigned vectorWidth) {
120 assert((vectorWidth == 128 || vectorWidth == 256) &&
121 "Unsupported vector width");
122 // Inserting UNDEF is Result
123 if (Vec.getOpcode() == ISD::UNDEF)
125 EVT VT = Vec.getValueType();
126 EVT ElVT = VT.getVectorElementType();
127 EVT ResultVT = Result.getValueType();
129 // Insert the relevant vectorWidth bits.
130 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
132 // This is the index of the first element of the vectorWidth-bit chunk
134 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
137 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
141 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
142 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
143 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
144 /// simple superregister reference. Idx is an index in the 128 bits
145 /// we want. It need not be aligned to a 128-bit bounday. That makes
146 /// lowering INSERT_VECTOR_ELT operations easier.
147 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
148 unsigned IdxVal, SelectionDAG &DAG,
150 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
151 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
154 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
155 unsigned IdxVal, SelectionDAG &DAG,
157 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
158 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
161 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
162 /// instructions. This is used because creating CONCAT_VECTOR nodes of
163 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
164 /// large BUILD_VECTORS.
165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
166 unsigned NumElems, SelectionDAG &DAG,
168 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
173 unsigned NumElems, SelectionDAG &DAG,
175 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
179 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
180 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
181 bool is64Bit = Subtarget->is64Bit();
183 if (Subtarget->isTargetMacho()) {
185 return new X86_64MachoTargetObjectFile();
186 return new TargetLoweringObjectFileMachO();
189 if (Subtarget->isTargetLinux())
190 return new X86LinuxTargetObjectFile();
191 if (Subtarget->isTargetELF())
192 return new TargetLoweringObjectFileELF();
193 if (Subtarget->isTargetCOFF())
194 return new TargetLoweringObjectFileCOFF();
195 llvm_unreachable("unknown subtarget type");
198 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
199 : TargetLowering(TM, createTLOF(TM)) {
200 Subtarget = &TM.getSubtarget<X86Subtarget>();
201 X86ScalarSSEf64 = Subtarget->hasSSE2();
202 X86ScalarSSEf32 = Subtarget->hasSSE1();
203 TD = getDataLayout();
205 resetOperationActions();
208 void X86TargetLowering::resetOperationActions() {
209 const TargetMachine &TM = getTargetMachine();
210 static bool FirstTimeThrough = true;
212 // If none of the target options have changed, then we don't need to reset the
213 // operation actions.
214 if (!FirstTimeThrough && TO == TM.Options) return;
216 if (!FirstTimeThrough) {
217 // Reinitialize the actions.
219 FirstTimeThrough = false;
224 // Set up the TargetLowering object.
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
228 setBooleanContents(ZeroOrOneBooleanContent);
229 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // For 64-bit since we have so many registers use the ILP scheduler, for
233 // 32-bit code use the register pressure specific scheduling.
234 // For Atom, always use ILP scheduling.
235 if (Subtarget->isAtom())
236 setSchedulingPreference(Sched::ILP);
237 else if (Subtarget->is64Bit())
238 setSchedulingPreference(Sched::ILP);
240 setSchedulingPreference(Sched::RegPressure);
241 const X86RegisterInfo *RegInfo =
242 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
243 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
245 // Bypass expensive divides on Atom when compiling with O2
246 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
247 addBypassSlowDiv(32, 8);
248 if (Subtarget->is64Bit())
249 addBypassSlowDiv(64, 16);
252 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
253 // Setup Windows compiler runtime calls.
254 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
255 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
256 setLibcallName(RTLIB::SREM_I64, "_allrem");
257 setLibcallName(RTLIB::UREM_I64, "_aullrem");
258 setLibcallName(RTLIB::MUL_I64, "_allmul");
259 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
265 // The _ftol2 runtime function has an unusual calling conv, which
266 // is modeled by a special pseudo-instruction.
267 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
270 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
273 if (Subtarget->isTargetDarwin()) {
274 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
275 setUseUnderscoreSetJmp(false);
276 setUseUnderscoreLongJmp(false);
277 } else if (Subtarget->isTargetMingw()) {
278 // MS runtime is weird: it exports _setjmp, but longjmp!
279 setUseUnderscoreSetJmp(true);
280 setUseUnderscoreLongJmp(false);
282 setUseUnderscoreSetJmp(true);
283 setUseUnderscoreLongJmp(true);
286 // Set up the register classes.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
289 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 if (Subtarget->is64Bit())
291 addRegisterClass(MVT::i64, &X86::GR64RegClass);
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 // We don't accept any truncstore of integer registers.
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 // SETOEQ and SETUNE require checking two conditions.
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
311 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
313 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
320 } else if (!TM.Options.UseSoftFloat) {
321 // We have an algorithm for SSE2->double, and we turn this into a
322 // 64-bit FILD followed by conditional FADD for other targets.
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 // We have an algorithm for SSE2, and we turn this into a 64-bit
325 // FILD for other targets.
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
329 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
331 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
332 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
334 if (!TM.Options.UseSoftFloat) {
335 // SSE has no i16 to fp conversion, only i32
336 if (X86ScalarSSEf32) {
337 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 // f32 and f64 cases are Legal, f80 case is not
339 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
349 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
350 // are Legal, f80 is custom lowered.
351 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
354 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
356 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
357 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 if (X86ScalarSSEf32) {
360 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 // f32 and f64 cases are Legal, f80 case is not
362 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 // Handle FP_TO_UINT by promoting the destination to a larger signed
370 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 if (Subtarget->is64Bit()) {
375 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
377 } else if (!TM.Options.UseSoftFloat) {
378 // Since AVX is a superset of SSE3, only check for SSE here.
379 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
380 // Expand FP_TO_UINT into a select.
381 // FIXME: We would like to use a Custom expander here eventually to do
382 // the optimal thing for SSE vs. the default expansion in the legalizer.
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
385 // With SSE3 we can use fisttpll to convert to a signed i64; without
386 // SSE, we're stuck with a fistpll.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
390 if (isTargetFTOL()) {
391 // Use the _ftol2 runtime function, which has a pseudo-instruction
392 // to handle its weird calling convention.
393 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
396 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
397 if (!X86ScalarSSEf64) {
398 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
399 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 // Without SSE, i64->f64 goes through memory.
403 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
407 // Scalar integer divide and remainder are lowered to use operations that
408 // produce two results, to match the available instructions. This exposes
409 // the two-result form to trivial CSE, which is able to combine x/y and x%y
410 // into a single instruction.
412 // Scalar integer multiply-high is also lowered to use two-result
413 // operations, to match the available instructions. However, plain multiply
414 // (low) operations are left as Legal, as there are single-result
415 // instructions for this in x86. Using the two-result multiply instructions
416 // when both high and low results are needed must be arranged by dagcombine.
417 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
419 setOperationAction(ISD::MULHS, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::SDIV, VT, Expand);
422 setOperationAction(ISD::UDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UREM, VT, Expand);
426 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
427 setOperationAction(ISD::ADDC, VT, Custom);
428 setOperationAction(ISD::ADDE, VT, Custom);
429 setOperationAction(ISD::SUBC, VT, Custom);
430 setOperationAction(ISD::SUBE, VT, Custom);
433 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
434 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
435 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
448 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f64 , Expand);
451 setOperationAction(ISD::FREM , MVT::f80 , Expand);
452 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
454 // Promote the i8 variants and force them on up to i32 which has a shorter
456 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
457 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
458 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
459 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 if (Subtarget->hasBMI()) {
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
466 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
467 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 if (Subtarget->is64Bit())
469 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
472 if (Subtarget->hasLZCNT()) {
473 // When promoting the i8 variants, force them to i32 for a shorter
475 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
476 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
478 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 if (Subtarget->is64Bit()) {
491 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 if (Subtarget->hasPOPCNT()) {
497 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
499 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 if (Subtarget->is64Bit())
503 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
506 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
507 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 // These should be promoted to a larger select which is supported.
510 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 // X86 wants to expand cmov itself.
512 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 if (Subtarget->is64Bit()) {
525 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
528 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
529 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
530 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
531 // support continuation, user-level threading, and etc.. As a result, no
532 // other SjLj exception interfaces are implemented and please don't build
533 // your own exception handling based on them.
534 // LLVM/Clang supports zero-cost DWARF exception handling.
535 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
536 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
539 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
540 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
545 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
546 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
549 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
550 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
551 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
555 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 if (Subtarget->hasSSE1())
565 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
567 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
569 // Expand certain atomics
570 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
572 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
574 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
577 if (!Subtarget->is64Bit()) {
578 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 if (Subtarget->hasCmpxchg16b()) {
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
596 // FIXME - use subtarget debug flags
597 if (!Subtarget->isTargetDarwin() &&
598 !Subtarget->isTargetELF() &&
599 !Subtarget->isTargetCygMing()) {
600 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
603 if (Subtarget->is64Bit()) {
604 setExceptionPointerRegister(X86::RAX);
605 setExceptionSelectorRegister(X86::RDX);
607 setExceptionPointerRegister(X86::EAX);
608 setExceptionSelectorRegister(X86::EDX);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
613 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
614 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
616 setOperationAction(ISD::TRAP, MVT::Other, Legal);
617 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
620 setOperationAction(ISD::VASTART , MVT::Other, Custom);
621 setOperationAction(ISD::VAEND , MVT::Other, Expand);
622 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
623 // TargetInfo::X86_64ABIBuiltinVaList
624 setOperationAction(ISD::VAARG , MVT::Other, Custom);
625 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 // TargetInfo::CharPtrBuiltinVaList
628 setOperationAction(ISD::VAARG , MVT::Other, Expand);
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
632 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
633 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
635 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
637 MVT::i64 : MVT::i32, Custom);
638 else if (TM.Options.EnableSegmentedStacks)
639 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
640 MVT::i64 : MVT::i32, Custom);
642 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
643 MVT::i64 : MVT::i32, Expand);
645 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
646 // f32 and f64 use SSE.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f32, &X86::FR32RegClass);
649 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 // Use ANDPD to simulate FABS.
652 setOperationAction(ISD::FABS , MVT::f64, Custom);
653 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 // Use XORP to simulate FNEG.
656 setOperationAction(ISD::FNEG , MVT::f64, Custom);
657 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 // Use ANDPD and ORPD to simulate FCOPYSIGN.
660 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 // Lower this to FGETSIGNx86 plus an AND.
664 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
665 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 // We don't support sin/cos/fmod
668 setOperationAction(ISD::FSIN , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f64, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSIN , MVT::f32, Expand);
672 setOperationAction(ISD::FCOS , MVT::f32, Expand);
673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
675 // Expand FP immediates into loads from the stack, except for the special
677 addLegalFPImmediate(APFloat(+0.0)); // xorpd
678 addLegalFPImmediate(APFloat(+0.0f)); // xorps
679 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
680 // Use SSE for f32, x87 for f64.
681 // Set up the FP register classes.
682 addRegisterClass(MVT::f32, &X86::FR32RegClass);
683 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 // Use ANDPS to simulate FABS.
686 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 // Use XORP to simulate FNEG.
689 setOperationAction(ISD::FNEG , MVT::f32, Custom);
691 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 // Use ANDPS and ORPS to simulate FCOPYSIGN.
694 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
695 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 // We don't support sin/cos/fmod
698 setOperationAction(ISD::FSIN , MVT::f32, Expand);
699 setOperationAction(ISD::FCOS , MVT::f32, Expand);
700 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
702 // Special cases we handle for FP constants.
703 addLegalFPImmediate(APFloat(+0.0f)); // xorps
704 addLegalFPImmediate(APFloat(+0.0)); // FLD0
705 addLegalFPImmediate(APFloat(+1.0)); // FLD1
706 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FCOS , MVT::f64, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
714 } else if (!TM.Options.UseSoftFloat) {
715 // f32 and f64 in x87.
716 // Set up the FP register classes.
717 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
718 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
721 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 if (!TM.Options.UnsafeFPMath) {
726 setOperationAction(ISD::FSIN , MVT::f64, Expand);
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FCOS , MVT::f32, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
737 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
738 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
739 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
740 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
743 // We don't support FMA.
744 setOperationAction(ISD::FMA, MVT::f64, Expand);
745 setOperationAction(ISD::FMA, MVT::f32, Expand);
747 // Long double always uses X87.
748 if (!TM.Options.UseSoftFloat) {
749 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
750 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
753 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
754 addLegalFPImmediate(TmpFlt); // FLD0
756 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
759 APFloat TmpFlt2(+1.0);
760 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
762 addLegalFPImmediate(TmpFlt2); // FLD1
763 TmpFlt2.changeSign();
764 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
767 if (!TM.Options.UnsafeFPMath) {
768 setOperationAction(ISD::FSIN , MVT::f80, Expand);
769 setOperationAction(ISD::FCOS , MVT::f80, Expand);
770 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
773 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
774 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
775 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
776 setOperationAction(ISD::FRINT, MVT::f80, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
778 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 // Always use a library call for pow.
782 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
786 setOperationAction(ISD::FLOG, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
792 // First set operation action for all vector types to either promote
793 // (for widening) or expand (for scalarization). Then we will selectively
794 // turn on ones that can be effectively codegen'd.
795 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
796 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
797 MVT VT = (MVT::SimpleValueType)i;
798 setOperationAction(ISD::ADD , VT, Expand);
799 setOperationAction(ISD::SUB , VT, Expand);
800 setOperationAction(ISD::FADD, VT, Expand);
801 setOperationAction(ISD::FNEG, VT, Expand);
802 setOperationAction(ISD::FSUB, VT, Expand);
803 setOperationAction(ISD::MUL , VT, Expand);
804 setOperationAction(ISD::FMUL, VT, Expand);
805 setOperationAction(ISD::SDIV, VT, Expand);
806 setOperationAction(ISD::UDIV, VT, Expand);
807 setOperationAction(ISD::FDIV, VT, Expand);
808 setOperationAction(ISD::SREM, VT, Expand);
809 setOperationAction(ISD::UREM, VT, Expand);
810 setOperationAction(ISD::LOAD, VT, Expand);
811 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
814 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::FABS, VT, Expand);
817 setOperationAction(ISD::FSIN, VT, Expand);
818 setOperationAction(ISD::FSINCOS, VT, Expand);
819 setOperationAction(ISD::FCOS, VT, Expand);
820 setOperationAction(ISD::FSINCOS, VT, Expand);
821 setOperationAction(ISD::FREM, VT, Expand);
822 setOperationAction(ISD::FMA, VT, Expand);
823 setOperationAction(ISD::FPOWI, VT, Expand);
824 setOperationAction(ISD::FSQRT, VT, Expand);
825 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
826 setOperationAction(ISD::FFLOOR, VT, Expand);
827 setOperationAction(ISD::FCEIL, VT, Expand);
828 setOperationAction(ISD::FTRUNC, VT, Expand);
829 setOperationAction(ISD::FRINT, VT, Expand);
830 setOperationAction(ISD::FNEARBYINT, VT, Expand);
831 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::SDIVREM, VT, Expand);
834 setOperationAction(ISD::UDIVREM, VT, Expand);
835 setOperationAction(ISD::FPOW, VT, Expand);
836 setOperationAction(ISD::CTPOP, VT, Expand);
837 setOperationAction(ISD::CTTZ, VT, Expand);
838 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
839 setOperationAction(ISD::CTLZ, VT, Expand);
840 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
841 setOperationAction(ISD::SHL, VT, Expand);
842 setOperationAction(ISD::SRA, VT, Expand);
843 setOperationAction(ISD::SRL, VT, Expand);
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 setOperationAction(ISD::BSWAP, VT, Expand);
847 setOperationAction(ISD::SETCC, VT, Expand);
848 setOperationAction(ISD::FLOG, VT, Expand);
849 setOperationAction(ISD::FLOG2, VT, Expand);
850 setOperationAction(ISD::FLOG10, VT, Expand);
851 setOperationAction(ISD::FEXP, VT, Expand);
852 setOperationAction(ISD::FEXP2, VT, Expand);
853 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
854 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
855 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
858 setOperationAction(ISD::TRUNCATE, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
860 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
861 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
862 setOperationAction(ISD::VSELECT, VT, Expand);
863 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
864 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 setTruncStoreAction(VT,
866 (MVT::SimpleValueType)InnerVT, Expand);
867 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
872 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
873 // with -msoft-float, disable use of MMX as well.
874 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
875 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
876 // No operations on x86mmx supported, everything uses intrinsics.
879 // MMX-sized vectors (other than x86mmx) are expected to be expanded
880 // into smaller operations.
881 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
882 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
883 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
884 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
885 setOperationAction(ISD::AND, MVT::v8i8, Expand);
886 setOperationAction(ISD::AND, MVT::v4i16, Expand);
887 setOperationAction(ISD::AND, MVT::v2i32, Expand);
888 setOperationAction(ISD::AND, MVT::v1i64, Expand);
889 setOperationAction(ISD::OR, MVT::v8i8, Expand);
890 setOperationAction(ISD::OR, MVT::v4i16, Expand);
891 setOperationAction(ISD::OR, MVT::v2i32, Expand);
892 setOperationAction(ISD::OR, MVT::v1i64, Expand);
893 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
902 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
903 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
904 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
905 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
912 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
914 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
916 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
917 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
918 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
919 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
920 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
921 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
929 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
931 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
932 // registers cannot be used even for integer operations.
933 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
934 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
935 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
936 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
938 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
939 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
940 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
941 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
945 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
946 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
947 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
948 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
949 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
951 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
954 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
955 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
959 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
960 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
969 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
970 MVT VT = (MVT::SimpleValueType)i;
971 // Do not attempt to custom lower non-power-of-2 vectors
972 if (!isPowerOf2_32(VT.getVectorNumElements()))
974 // Do not attempt to custom lower non-128-bit vectors
975 if (!VT.is128BitVector())
977 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
978 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to promote non-128-bit vectors
999 if (!VT.is128BitVector())
1002 setOperationAction(ISD::AND, VT, Promote);
1003 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 setOperationAction(ISD::OR, VT, Promote);
1005 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 setOperationAction(ISD::XOR, VT, Promote);
1007 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 setOperationAction(ISD::LOAD, VT, Promote);
1009 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 setOperationAction(ISD::SELECT, VT, Promote);
1011 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 // Custom lower v2i64 and v2f64 selects.
1017 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1019 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1027 // As there is no 64-bit GPR available, we need build a special custom
1028 // sequence to convert from v2i32 to v2f32.
1029 if (!Subtarget->is64Bit())
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1039 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1047 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 // FIXME: Do we need to handle scalar-to-vector here?
1062 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1070 // i8 and i16 vectors are custom , because the source register and source
1071 // source memory operand types are not the same width. f32 vectors are
1072 // custom since the immediate controlling the insert encodes additional
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1084 // FIXME: these should be Legal but thats only for the case where
1085 // the index is constant. For now custom expand to deal with that.
1086 if (Subtarget->is64Bit()) {
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1088 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 if (Subtarget->hasSSE2()) {
1093 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1102 // In the customized shift lowering, the legal cases in AVX2 will be
1104 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1105 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1124 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1128 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1139 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1141 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1152 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1159 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1166 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1186 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1204 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1205 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1209 setOperationAction(ISD::FMA, MVT::f32, Legal);
1210 setOperationAction(ISD::FMA, MVT::f64, Legal);
1213 if (Subtarget->hasInt256()) {
1214 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1227 // Don't lower v32i8 because there is no 128-bit byte mul
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1231 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1234 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1235 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1243 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1245 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1246 // Don't lower v32i8 because there is no 128-bit byte mul
1249 // In the customized shift lowering, the legal cases in AVX2 will be
1251 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1259 // Custom lower several nodes for 256-bit types.
1260 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1261 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262 MVT VT = (MVT::SimpleValueType)i;
1264 // Extract subvector is special because the value type
1265 // (result) is 128-bit but the source is 256-bit wide.
1266 if (VT.is128BitVector())
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1269 // Do not attempt to custom lower other non-256-bit vectors
1270 if (!VT.is256BitVector())
1273 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1275 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1278 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1279 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1314 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1315 setOperationAction(ISD::XOR, MVT::i1, Legal);
1316 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1317 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1318 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1319 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1323 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1330 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1336 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1338 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1340 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1341 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1342 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1344 if (Subtarget->is64Bit()) {
1345 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1346 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1347 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1348 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1350 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1351 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1352 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1353 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1354 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1355 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1357 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1359 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1360 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1361 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1362 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1364 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1365 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1367 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1368 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1369 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1373 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1374 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1375 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1378 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1379 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1381 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1383 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1384 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1385 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1386 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1387 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1388 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1389 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1391 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1392 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1394 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1395 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1397 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1399 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1400 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1402 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1403 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1405 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1406 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1408 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1409 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1410 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1411 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1412 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1413 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1415 // Custom lower several nodes.
1416 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1417 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1418 MVT VT = (MVT::SimpleValueType)i;
1420 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1421 // Extract subvector is special because the value type
1422 // (result) is 256/128-bit but the source is 512-bit wide.
1423 if (VT.is128BitVector() || VT.is256BitVector())
1424 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1426 if (VT.getVectorElementType() == MVT::i1)
1427 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1429 // Do not attempt to custom lower other non-512-bit vectors
1430 if (!VT.is512BitVector())
1433 if ( EltSize >= 32) {
1434 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1435 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1436 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1437 setOperationAction(ISD::VSELECT, VT, Legal);
1438 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1439 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1440 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1443 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1444 MVT VT = (MVT::SimpleValueType)i;
1446 // Do not attempt to promote non-256-bit vectors
1447 if (!VT.is512BitVector())
1450 setOperationAction(ISD::SELECT, VT, Promote);
1451 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1455 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1456 // of this type with custom code.
1457 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1458 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1459 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1463 // We want to custom lower some of our intrinsics.
1464 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1465 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1466 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1468 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1469 // handle type legalization for these operations here.
1471 // FIXME: We really should do custom legalization for addition and
1472 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1473 // than generic legalization for 64-bit multiplication-with-overflow, though.
1474 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1475 // Add/Sub/Mul with overflow operations are custom lowered.
1477 setOperationAction(ISD::SADDO, VT, Custom);
1478 setOperationAction(ISD::UADDO, VT, Custom);
1479 setOperationAction(ISD::SSUBO, VT, Custom);
1480 setOperationAction(ISD::USUBO, VT, Custom);
1481 setOperationAction(ISD::SMULO, VT, Custom);
1482 setOperationAction(ISD::UMULO, VT, Custom);
1485 // There are no 8-bit 3-address imul/mul instructions
1486 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1487 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1489 if (!Subtarget->is64Bit()) {
1490 // These libcalls are not available in 32-bit.
1491 setLibcallName(RTLIB::SHL_I128, 0);
1492 setLibcallName(RTLIB::SRL_I128, 0);
1493 setLibcallName(RTLIB::SRA_I128, 0);
1496 // Combine sin / cos into one node or libcall if possible.
1497 if (Subtarget->hasSinCos()) {
1498 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1499 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1500 if (Subtarget->isTargetDarwin()) {
1501 // For MacOSX, we don't want to the normal expansion of a libcall to
1502 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1504 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1505 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1509 // We have target-specific dag combine patterns for the following nodes:
1510 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1511 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1512 setTargetDAGCombine(ISD::VSELECT);
1513 setTargetDAGCombine(ISD::SELECT);
1514 setTargetDAGCombine(ISD::SHL);
1515 setTargetDAGCombine(ISD::SRA);
1516 setTargetDAGCombine(ISD::SRL);
1517 setTargetDAGCombine(ISD::OR);
1518 setTargetDAGCombine(ISD::AND);
1519 setTargetDAGCombine(ISD::ADD);
1520 setTargetDAGCombine(ISD::FADD);
1521 setTargetDAGCombine(ISD::FSUB);
1522 setTargetDAGCombine(ISD::FMA);
1523 setTargetDAGCombine(ISD::SUB);
1524 setTargetDAGCombine(ISD::LOAD);
1525 setTargetDAGCombine(ISD::STORE);
1526 setTargetDAGCombine(ISD::ZERO_EXTEND);
1527 setTargetDAGCombine(ISD::ANY_EXTEND);
1528 setTargetDAGCombine(ISD::SIGN_EXTEND);
1529 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1530 setTargetDAGCombine(ISD::TRUNCATE);
1531 setTargetDAGCombine(ISD::SINT_TO_FP);
1532 setTargetDAGCombine(ISD::SETCC);
1533 if (Subtarget->is64Bit())
1534 setTargetDAGCombine(ISD::MUL);
1535 setTargetDAGCombine(ISD::XOR);
1537 computeRegisterProperties();
1539 // On Darwin, -Os means optimize for size without hurting performance,
1540 // do not reduce the limit.
1541 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1542 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1543 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1544 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1545 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1546 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1547 setPrefLoopAlignment(4); // 2^4 bytes.
1549 // Predictable cmov don't hurt on atom because it's in-order.
1550 PredictableSelectIsExpensive = !Subtarget->isAtom();
1552 setPrefFunctionAlignment(4); // 2^4 bytes.
1555 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1559 const TargetMachine &TM = getTargetMachine();
1560 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
1561 switch(VT.getVectorNumElements()) {
1562 case 8: return MVT::v8i1;
1563 case 16: return MVT::v16i1;
1566 return VT.changeVectorElementTypeToInteger();
1569 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1570 /// the desired ByVal argument alignment.
1571 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1574 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1575 if (VTy->getBitWidth() == 128)
1577 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1578 unsigned EltAlign = 0;
1579 getMaxByValAlign(ATy->getElementType(), EltAlign);
1580 if (EltAlign > MaxAlign)
1581 MaxAlign = EltAlign;
1582 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1583 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1584 unsigned EltAlign = 0;
1585 getMaxByValAlign(STy->getElementType(i), EltAlign);
1586 if (EltAlign > MaxAlign)
1587 MaxAlign = EltAlign;
1594 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1595 /// function arguments in the caller parameter area. For X86, aggregates
1596 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1597 /// are at 4-byte boundaries.
1598 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1599 if (Subtarget->is64Bit()) {
1600 // Max of 8 and alignment of type.
1601 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1608 if (Subtarget->hasSSE1())
1609 getMaxByValAlign(Ty, Align);
1613 /// getOptimalMemOpType - Returns the target specific optimal type for load
1614 /// and store operations as a result of memset, memcpy, and memmove
1615 /// lowering. If DstAlign is zero that means it's safe to destination
1616 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1617 /// means there isn't a need to check it against alignment requirement,
1618 /// probably because the source does not need to be loaded. If 'IsMemset' is
1619 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1620 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1621 /// source is constant so it does not need to be loaded.
1622 /// It returns EVT::Other if the type should be determined using generic
1623 /// target-independent logic.
1625 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1626 unsigned DstAlign, unsigned SrcAlign,
1627 bool IsMemset, bool ZeroMemset,
1629 MachineFunction &MF) const {
1630 const Function *F = MF.getFunction();
1631 if ((!IsMemset || ZeroMemset) &&
1632 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1633 Attribute::NoImplicitFloat)) {
1635 (Subtarget->isUnalignedMemAccessFast() ||
1636 ((DstAlign == 0 || DstAlign >= 16) &&
1637 (SrcAlign == 0 || SrcAlign >= 16)))) {
1639 if (Subtarget->hasInt256())
1641 if (Subtarget->hasFp256())
1644 if (Subtarget->hasSSE2())
1646 if (Subtarget->hasSSE1())
1648 } else if (!MemcpyStrSrc && Size >= 8 &&
1649 !Subtarget->is64Bit() &&
1650 Subtarget->hasSSE2()) {
1651 // Do not use f64 to lower memcpy if source is string constant. It's
1652 // better to use i32 to avoid the loads.
1656 if (Subtarget->is64Bit() && Size >= 8)
1661 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1663 return X86ScalarSSEf32;
1664 else if (VT == MVT::f64)
1665 return X86ScalarSSEf64;
1670 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1672 *Fast = Subtarget->isUnalignedMemAccessFast();
1676 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1677 /// current function. The returned value is a member of the
1678 /// MachineJumpTableInfo::JTEntryKind enum.
1679 unsigned X86TargetLowering::getJumpTableEncoding() const {
1680 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1682 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1683 Subtarget->isPICStyleGOT())
1684 return MachineJumpTableInfo::EK_Custom32;
1686 // Otherwise, use the normal jump table encoding heuristics.
1687 return TargetLowering::getJumpTableEncoding();
1691 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1692 const MachineBasicBlock *MBB,
1693 unsigned uid,MCContext &Ctx) const{
1694 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1695 Subtarget->isPICStyleGOT());
1696 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1698 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1699 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1702 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1704 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1705 SelectionDAG &DAG) const {
1706 if (!Subtarget->is64Bit())
1707 // This doesn't have SDLoc associated with it, but is not really the
1708 // same as a Register.
1709 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1713 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1714 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1716 const MCExpr *X86TargetLowering::
1717 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1718 MCContext &Ctx) const {
1719 // X86-64 uses RIP relative addressing based on the jump table label.
1720 if (Subtarget->isPICStyleRIPRel())
1721 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1723 // Otherwise, the reference is relative to the PIC base.
1724 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1727 // FIXME: Why this routine is here? Move to RegInfo!
1728 std::pair<const TargetRegisterClass*, uint8_t>
1729 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1730 const TargetRegisterClass *RRC = 0;
1732 switch (VT.SimpleTy) {
1734 return TargetLowering::findRepresentativeClass(VT);
1735 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1736 RRC = Subtarget->is64Bit() ?
1737 (const TargetRegisterClass*)&X86::GR64RegClass :
1738 (const TargetRegisterClass*)&X86::GR32RegClass;
1741 RRC = &X86::VR64RegClass;
1743 case MVT::f32: case MVT::f64:
1744 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1745 case MVT::v4f32: case MVT::v2f64:
1746 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1748 RRC = &X86::VR128RegClass;
1751 return std::make_pair(RRC, Cost);
1754 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1755 unsigned &Offset) const {
1756 if (!Subtarget->isTargetLinux())
1759 if (Subtarget->is64Bit()) {
1760 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1762 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1774 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1775 unsigned DestAS) const {
1776 assert(SrcAS != DestAS && "Expected different address spaces!");
1778 return SrcAS < 256 && DestAS < 256;
1781 //===----------------------------------------------------------------------===//
1782 // Return Value Calling Convention Implementation
1783 //===----------------------------------------------------------------------===//
1785 #include "X86GenCallingConv.inc"
1788 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1789 MachineFunction &MF, bool isVarArg,
1790 const SmallVectorImpl<ISD::OutputArg> &Outs,
1791 LLVMContext &Context) const {
1792 SmallVector<CCValAssign, 16> RVLocs;
1793 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1795 return CCInfo.CheckReturn(Outs, RetCC_X86);
1798 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1799 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1804 X86TargetLowering::LowerReturn(SDValue Chain,
1805 CallingConv::ID CallConv, bool isVarArg,
1806 const SmallVectorImpl<ISD::OutputArg> &Outs,
1807 const SmallVectorImpl<SDValue> &OutVals,
1808 SDLoc dl, SelectionDAG &DAG) const {
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1812 SmallVector<CCValAssign, 16> RVLocs;
1813 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1814 RVLocs, *DAG.getContext());
1815 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1818 SmallVector<SDValue, 6> RetOps;
1819 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1820 // Operand #1 = Bytes To Pop
1821 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1824 // Copy the result values into the output registers.
1825 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1826 CCValAssign &VA = RVLocs[i];
1827 assert(VA.isRegLoc() && "Can only return in registers!");
1828 SDValue ValToCopy = OutVals[i];
1829 EVT ValVT = ValToCopy.getValueType();
1831 // Promote values to the appropriate types
1832 if (VA.getLocInfo() == CCValAssign::SExt)
1833 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1834 else if (VA.getLocInfo() == CCValAssign::ZExt)
1835 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1836 else if (VA.getLocInfo() == CCValAssign::AExt)
1837 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1838 else if (VA.getLocInfo() == CCValAssign::BCvt)
1839 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1841 // If this is x86-64, and we disabled SSE, we can't return FP values,
1842 // or SSE or MMX vectors.
1843 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1844 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1845 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1846 report_fatal_error("SSE register return with SSE disabled");
1848 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1849 // llvm-gcc has never done it right and no one has noticed, so this
1850 // should be OK for now.
1851 if (ValVT == MVT::f64 &&
1852 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1853 report_fatal_error("SSE2 register return with SSE2 disabled");
1855 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1856 // the RET instruction and handled by the FP Stackifier.
1857 if (VA.getLocReg() == X86::ST0 ||
1858 VA.getLocReg() == X86::ST1) {
1859 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1860 // change the value to the FP stack register class.
1861 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1862 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1863 RetOps.push_back(ValToCopy);
1864 // Don't emit a copytoreg.
1868 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1869 // which is returned in RAX / RDX.
1870 if (Subtarget->is64Bit()) {
1871 if (ValVT == MVT::x86mmx) {
1872 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1873 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1874 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1876 // If we don't have SSE2 available, convert to v4f32 so the generated
1877 // register is legal.
1878 if (!Subtarget->hasSSE2())
1879 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1884 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1885 Flag = Chain.getValue(1);
1886 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1889 // The x86-64 ABIs require that for returning structs by value we copy
1890 // the sret argument into %rax/%eax (depending on ABI) for the return.
1891 // Win32 requires us to put the sret argument to %eax as well.
1892 // We saved the argument into a virtual register in the entry block,
1893 // so now we copy the value out and into %rax/%eax.
1894 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1895 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1896 MachineFunction &MF = DAG.getMachineFunction();
1897 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1898 unsigned Reg = FuncInfo->getSRetReturnReg();
1900 "SRetReturnReg should have been set in LowerFormalArguments().");
1901 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1904 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1905 X86::RAX : X86::EAX;
1906 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1907 Flag = Chain.getValue(1);
1909 // RAX/EAX now acts like a return value.
1910 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1913 RetOps[0] = Chain; // Update chain.
1915 // Add the flag if we have it.
1917 RetOps.push_back(Flag);
1919 return DAG.getNode(X86ISD::RET_FLAG, dl,
1920 MVT::Other, &RetOps[0], RetOps.size());
1923 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1924 if (N->getNumValues() != 1)
1926 if (!N->hasNUsesOfValue(1, 0))
1929 SDValue TCChain = Chain;
1930 SDNode *Copy = *N->use_begin();
1931 if (Copy->getOpcode() == ISD::CopyToReg) {
1932 // If the copy has a glue operand, we conservatively assume it isn't safe to
1933 // perform a tail call.
1934 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1936 TCChain = Copy->getOperand(0);
1937 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1940 bool HasRet = false;
1941 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1943 if (UI->getOpcode() != X86ISD::RET_FLAG)
1956 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1957 ISD::NodeType ExtendKind) const {
1959 // TODO: Is this also valid on 32-bit?
1960 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1961 ReturnMVT = MVT::i8;
1963 ReturnMVT = MVT::i32;
1965 MVT MinVT = getRegisterType(ReturnMVT);
1966 return VT.bitsLT(MinVT) ? MinVT : VT;
1969 /// LowerCallResult - Lower the result values of a call into the
1970 /// appropriate copies out of appropriate physical registers.
1973 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1974 CallingConv::ID CallConv, bool isVarArg,
1975 const SmallVectorImpl<ISD::InputArg> &Ins,
1976 SDLoc dl, SelectionDAG &DAG,
1977 SmallVectorImpl<SDValue> &InVals) const {
1979 // Assign locations to each value returned by this call.
1980 SmallVector<CCValAssign, 16> RVLocs;
1981 bool Is64Bit = Subtarget->is64Bit();
1982 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1983 getTargetMachine(), RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1986 // Copy all of the result registers out of their specified physreg.
1987 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1988 CCValAssign &VA = RVLocs[i];
1989 EVT CopyVT = VA.getValVT();
1991 // If this is x86-64, and we disabled SSE, we can't return FP values
1992 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1993 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1994 report_fatal_error("SSE register return with SSE disabled");
1999 // If this is a call to a function that returns an fp value on the floating
2000 // point stack, we must guarantee the value is popped from the stack, so
2001 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2002 // if the return value is not used. We use the FpPOP_RETVAL instruction
2004 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2005 // If we prefer to use the value in xmm registers, copy it out as f80 and
2006 // use a truncate to move it from fp stack reg to xmm reg.
2007 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2008 SDValue Ops[] = { Chain, InFlag };
2009 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2010 MVT::Other, MVT::Glue, Ops), 1);
2011 Val = Chain.getValue(0);
2013 // Round the f80 to the right size, which also moves it to the appropriate
2015 if (CopyVT != VA.getValVT())
2016 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2017 // This truncation won't change the value.
2018 DAG.getIntPtrConstant(1));
2020 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2021 CopyVT, InFlag).getValue(1);
2022 Val = Chain.getValue(0);
2024 InFlag = Chain.getValue(2);
2025 InVals.push_back(Val);
2031 //===----------------------------------------------------------------------===//
2032 // C & StdCall & Fast Calling Convention implementation
2033 //===----------------------------------------------------------------------===//
2034 // StdCall calling convention seems to be standard for many Windows' API
2035 // routines and around. It differs from C calling convention just a little:
2036 // callee should clean up the stack, not caller. Symbols should be also
2037 // decorated in some fancy way :) It doesn't support any vector arguments.
2038 // For info on fast calling convention see Fast Calling Convention (tail call)
2039 // implementation LowerX86_32FastCCCallTo.
2041 /// CallIsStructReturn - Determines whether a call uses struct return
2043 enum StructReturnType {
2048 static StructReturnType
2049 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2051 return NotStructReturn;
2053 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2054 if (!Flags.isSRet())
2055 return NotStructReturn;
2056 if (Flags.isInReg())
2057 return RegStructReturn;
2058 return StackStructReturn;
2061 /// ArgsAreStructReturn - Determines whether a function uses struct
2062 /// return semantics.
2063 static StructReturnType
2064 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2066 return NotStructReturn;
2068 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2069 if (!Flags.isSRet())
2070 return NotStructReturn;
2071 if (Flags.isInReg())
2072 return RegStructReturn;
2073 return StackStructReturn;
2076 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2077 /// by "Src" to address "Dst" with size and alignment information specified by
2078 /// the specific parameter attribute. The copy will be passed as a byval
2079 /// function parameter.
2081 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2082 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2084 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2086 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2087 /*isVolatile*/false, /*AlwaysInline=*/true,
2088 MachinePointerInfo(), MachinePointerInfo());
2091 /// IsTailCallConvention - Return true if the calling convention is one that
2092 /// supports tail call optimization.
2093 static bool IsTailCallConvention(CallingConv::ID CC) {
2094 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2095 CC == CallingConv::HiPE);
2098 /// \brief Return true if the calling convention is a C calling convention.
2099 static bool IsCCallConvention(CallingConv::ID CC) {
2100 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2101 CC == CallingConv::X86_64_SysV);
2104 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2105 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2109 CallingConv::ID CalleeCC = CS.getCallingConv();
2110 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2116 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2117 /// a tailcall target by changing its ABI.
2118 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2119 bool GuaranteedTailCallOpt) {
2120 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2124 X86TargetLowering::LowerMemArgument(SDValue Chain,
2125 CallingConv::ID CallConv,
2126 const SmallVectorImpl<ISD::InputArg> &Ins,
2127 SDLoc dl, SelectionDAG &DAG,
2128 const CCValAssign &VA,
2129 MachineFrameInfo *MFI,
2131 // Create the nodes corresponding to a load from this parameter slot.
2132 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2133 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2134 getTargetMachine().Options.GuaranteedTailCallOpt);
2135 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2138 // If value is passed by pointer we have address passed instead of the value
2140 if (VA.getLocInfo() == CCValAssign::Indirect)
2141 ValVT = VA.getLocVT();
2143 ValVT = VA.getValVT();
2145 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2146 // changed with more analysis.
2147 // In case of tail call optimization mark all arguments mutable. Since they
2148 // could be overwritten by lowering of arguments in case of a tail call.
2149 if (Flags.isByVal()) {
2150 unsigned Bytes = Flags.getByValSize();
2151 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2152 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2153 return DAG.getFrameIndex(FI, getPointerTy());
2155 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2156 VA.getLocMemOffset(), isImmutable);
2157 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2158 return DAG.getLoad(ValVT, dl, Chain, FIN,
2159 MachinePointerInfo::getFixedStack(FI),
2160 false, false, false, 0);
2165 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2166 CallingConv::ID CallConv,
2168 const SmallVectorImpl<ISD::InputArg> &Ins,
2171 SmallVectorImpl<SDValue> &InVals)
2173 MachineFunction &MF = DAG.getMachineFunction();
2174 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2176 const Function* Fn = MF.getFunction();
2177 if (Fn->hasExternalLinkage() &&
2178 Subtarget->isTargetCygMing() &&
2179 Fn->getName() == "main")
2180 FuncInfo->setForceFramePointer(true);
2182 MachineFrameInfo *MFI = MF.getFrameInfo();
2183 bool Is64Bit = Subtarget->is64Bit();
2184 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2186 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2187 "Var args not supported with calling convention fastcc, ghc or hipe");
2189 // Assign locations to all of the incoming arguments.
2190 SmallVector<CCValAssign, 16> ArgLocs;
2191 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2192 ArgLocs, *DAG.getContext());
2194 // Allocate shadow area for Win64
2196 CCInfo.AllocateStack(32, 8);
2198 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2200 unsigned LastVal = ~0U;
2202 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2203 CCValAssign &VA = ArgLocs[i];
2204 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2206 assert(VA.getValNo() != LastVal &&
2207 "Don't support value assigned to multiple locs yet");
2209 LastVal = VA.getValNo();
2211 if (VA.isRegLoc()) {
2212 EVT RegVT = VA.getLocVT();
2213 const TargetRegisterClass *RC;
2214 if (RegVT == MVT::i32)
2215 RC = &X86::GR32RegClass;
2216 else if (Is64Bit && RegVT == MVT::i64)
2217 RC = &X86::GR64RegClass;
2218 else if (RegVT == MVT::f32)
2219 RC = &X86::FR32RegClass;
2220 else if (RegVT == MVT::f64)
2221 RC = &X86::FR64RegClass;
2222 else if (RegVT.is512BitVector())
2223 RC = &X86::VR512RegClass;
2224 else if (RegVT.is256BitVector())
2225 RC = &X86::VR256RegClass;
2226 else if (RegVT.is128BitVector())
2227 RC = &X86::VR128RegClass;
2228 else if (RegVT == MVT::x86mmx)
2229 RC = &X86::VR64RegClass;
2230 else if (RegVT == MVT::i1)
2231 RC = &X86::VK1RegClass;
2232 else if (RegVT == MVT::v8i1)
2233 RC = &X86::VK8RegClass;
2234 else if (RegVT == MVT::v16i1)
2235 RC = &X86::VK16RegClass;
2237 llvm_unreachable("Unknown argument type!");
2239 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2240 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2242 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2243 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2245 if (VA.getLocInfo() == CCValAssign::SExt)
2246 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2247 DAG.getValueType(VA.getValVT()));
2248 else if (VA.getLocInfo() == CCValAssign::ZExt)
2249 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2250 DAG.getValueType(VA.getValVT()));
2251 else if (VA.getLocInfo() == CCValAssign::BCvt)
2252 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2254 if (VA.isExtInLoc()) {
2255 // Handle MMX values passed in XMM regs.
2256 if (RegVT.isVector())
2257 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2259 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2262 assert(VA.isMemLoc());
2263 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2266 // If value is passed via pointer - do a load.
2267 if (VA.getLocInfo() == CCValAssign::Indirect)
2268 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2269 MachinePointerInfo(), false, false, false, 0);
2271 InVals.push_back(ArgValue);
2274 // The x86-64 ABIs require that for returning structs by value we copy
2275 // the sret argument into %rax/%eax (depending on ABI) for the return.
2276 // Win32 requires us to put the sret argument to %eax as well.
2277 // Save the argument into a virtual register so that we can access it
2278 // from the return points.
2279 if (MF.getFunction()->hasStructRetAttr() &&
2280 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2281 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2282 unsigned Reg = FuncInfo->getSRetReturnReg();
2284 MVT PtrTy = getPointerTy();
2285 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2286 FuncInfo->setSRetReturnReg(Reg);
2288 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2289 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2292 unsigned StackSize = CCInfo.getNextStackOffset();
2293 // Align stack specially for tail calls.
2294 if (FuncIsMadeTailCallSafe(CallConv,
2295 MF.getTarget().Options.GuaranteedTailCallOpt))
2296 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2298 // If the function takes variable number of arguments, make a frame index for
2299 // the start of the first vararg value... for expansion of llvm.va_start.
2301 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2302 CallConv != CallingConv::X86_ThisCall)) {
2303 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2306 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2308 // FIXME: We should really autogenerate these arrays
2309 static const uint16_t GPR64ArgRegsWin64[] = {
2310 X86::RCX, X86::RDX, X86::R8, X86::R9
2312 static const uint16_t GPR64ArgRegs64Bit[] = {
2313 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2315 static const uint16_t XMMArgRegs64Bit[] = {
2316 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2317 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2319 const uint16_t *GPR64ArgRegs;
2320 unsigned NumXMMRegs = 0;
2323 // The XMM registers which might contain var arg parameters are shadowed
2324 // in their paired GPR. So we only need to save the GPR to their home
2326 TotalNumIntRegs = 4;
2327 GPR64ArgRegs = GPR64ArgRegsWin64;
2329 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2330 GPR64ArgRegs = GPR64ArgRegs64Bit;
2332 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2335 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2338 bool NoImplicitFloatOps = Fn->getAttributes().
2339 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2340 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2341 "SSE register cannot be used when SSE is disabled!");
2342 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2343 NoImplicitFloatOps) &&
2344 "SSE register cannot be used when SSE is disabled!");
2345 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2346 !Subtarget->hasSSE1())
2347 // Kernel mode asks for SSE to be disabled, so don't push them
2349 TotalNumXMMRegs = 0;
2352 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2353 // Get to the caller-allocated home save location. Add 8 to account
2354 // for the return address.
2355 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2356 FuncInfo->setRegSaveFrameIndex(
2357 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2358 // Fixup to set vararg frame on shadow area (4 x i64).
2360 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2362 // For X86-64, if there are vararg parameters that are passed via
2363 // registers, then we must store them to their spots on the stack so
2364 // they may be loaded by deferencing the result of va_next.
2365 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2366 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2367 FuncInfo->setRegSaveFrameIndex(
2368 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2372 // Store the integer parameter registers.
2373 SmallVector<SDValue, 8> MemOps;
2374 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2376 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2377 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2378 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2379 DAG.getIntPtrConstant(Offset));
2380 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2381 &X86::GR64RegClass);
2382 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2384 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2385 MachinePointerInfo::getFixedStack(
2386 FuncInfo->getRegSaveFrameIndex(), Offset),
2388 MemOps.push_back(Store);
2392 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2393 // Now store the XMM (fp + vector) parameter registers.
2394 SmallVector<SDValue, 11> SaveXMMOps;
2395 SaveXMMOps.push_back(Chain);
2397 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2398 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2399 SaveXMMOps.push_back(ALVal);
2401 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2402 FuncInfo->getRegSaveFrameIndex()));
2403 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2404 FuncInfo->getVarArgsFPOffset()));
2406 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2407 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2408 &X86::VR128RegClass);
2409 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2410 SaveXMMOps.push_back(Val);
2412 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2414 &SaveXMMOps[0], SaveXMMOps.size()));
2417 if (!MemOps.empty())
2418 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2419 &MemOps[0], MemOps.size());
2423 // Some CCs need callee pop.
2424 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2425 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2426 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2428 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2429 // If this is an sret function, the return should pop the hidden pointer.
2430 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2431 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2432 argsAreStructReturn(Ins) == StackStructReturn)
2433 FuncInfo->setBytesToPopOnReturn(4);
2437 // RegSaveFrameIndex is X86-64 only.
2438 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2439 if (CallConv == CallingConv::X86_FastCall ||
2440 CallConv == CallingConv::X86_ThisCall)
2441 // fastcc functions can't have varargs.
2442 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2445 FuncInfo->setArgumentStackSize(StackSize);
2451 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2452 SDValue StackPtr, SDValue Arg,
2453 SDLoc dl, SelectionDAG &DAG,
2454 const CCValAssign &VA,
2455 ISD::ArgFlagsTy Flags) const {
2456 unsigned LocMemOffset = VA.getLocMemOffset();
2457 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2458 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2459 if (Flags.isByVal())
2460 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2462 return DAG.getStore(Chain, dl, Arg, PtrOff,
2463 MachinePointerInfo::getStack(LocMemOffset),
2467 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2468 /// optimization is performed and it is required.
2470 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2471 SDValue &OutRetAddr, SDValue Chain,
2472 bool IsTailCall, bool Is64Bit,
2473 int FPDiff, SDLoc dl) const {
2474 // Adjust the Return address stack slot.
2475 EVT VT = getPointerTy();
2476 OutRetAddr = getReturnAddressFrameIndex(DAG);
2478 // Load the "old" Return address.
2479 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2480 false, false, false, 0);
2481 return SDValue(OutRetAddr.getNode(), 1);
2484 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2485 /// optimization is performed and it is required (FPDiff!=0).
2487 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2488 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2489 unsigned SlotSize, int FPDiff, SDLoc dl) {
2490 // Store the return address to the appropriate stack slot.
2491 if (!FPDiff) return Chain;
2492 // Calculate the new stack slot for the return address.
2493 int NewReturnAddrFI =
2494 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2496 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2497 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2498 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2504 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2505 SmallVectorImpl<SDValue> &InVals) const {
2506 SelectionDAG &DAG = CLI.DAG;
2508 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2509 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2510 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2511 SDValue Chain = CLI.Chain;
2512 SDValue Callee = CLI.Callee;
2513 CallingConv::ID CallConv = CLI.CallConv;
2514 bool &isTailCall = CLI.IsTailCall;
2515 bool isVarArg = CLI.IsVarArg;
2517 MachineFunction &MF = DAG.getMachineFunction();
2518 bool Is64Bit = Subtarget->is64Bit();
2519 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2520 StructReturnType SR = callIsStructReturn(Outs);
2521 bool IsSibcall = false;
2523 if (MF.getTarget().Options.DisableTailCalls)
2527 // Check if it's really possible to do a tail call.
2528 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2529 isVarArg, SR != NotStructReturn,
2530 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2531 Outs, OutVals, Ins, DAG);
2533 // Sibcalls are automatically detected tailcalls which do not require
2535 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2542 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2543 "Var args not supported with calling convention fastcc, ghc or hipe");
2545 // Analyze operands of the call, assigning locations to each operand.
2546 SmallVector<CCValAssign, 16> ArgLocs;
2547 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2548 ArgLocs, *DAG.getContext());
2550 // Allocate shadow area for Win64
2552 CCInfo.AllocateStack(32, 8);
2554 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2556 // Get a count of how many bytes are to be pushed on the stack.
2557 unsigned NumBytes = CCInfo.getNextStackOffset();
2559 // This is a sibcall. The memory operands are available in caller's
2560 // own caller's stack.
2562 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2563 IsTailCallConvention(CallConv))
2564 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2567 if (isTailCall && !IsSibcall) {
2568 // Lower arguments at fp - stackoffset + fpdiff.
2569 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2570 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2572 FPDiff = NumBytesCallerPushed - NumBytes;
2574 // Set the delta of movement of the returnaddr stackslot.
2575 // But only set if delta is greater than previous delta.
2576 if (FPDiff < X86Info->getTCReturnAddrDelta())
2577 X86Info->setTCReturnAddrDelta(FPDiff);
2581 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2584 SDValue RetAddrFrIdx;
2585 // Load return address for tail calls.
2586 if (isTailCall && FPDiff)
2587 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2588 Is64Bit, FPDiff, dl);
2590 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2591 SmallVector<SDValue, 8> MemOpChains;
2594 // Walk the register/memloc assignments, inserting copies/loads. In the case
2595 // of tail call optimization arguments are handle later.
2596 const X86RegisterInfo *RegInfo =
2597 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2598 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2599 CCValAssign &VA = ArgLocs[i];
2600 EVT RegVT = VA.getLocVT();
2601 SDValue Arg = OutVals[i];
2602 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2603 bool isByVal = Flags.isByVal();
2605 // Promote the value if needed.
2606 switch (VA.getLocInfo()) {
2607 default: llvm_unreachable("Unknown loc info!");
2608 case CCValAssign::Full: break;
2609 case CCValAssign::SExt:
2610 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2612 case CCValAssign::ZExt:
2613 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2615 case CCValAssign::AExt:
2616 if (RegVT.is128BitVector()) {
2617 // Special case: passing MMX values in XMM registers.
2618 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2619 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2620 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2622 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2624 case CCValAssign::BCvt:
2625 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2627 case CCValAssign::Indirect: {
2628 // Store the argument.
2629 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2630 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2631 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2632 MachinePointerInfo::getFixedStack(FI),
2639 if (VA.isRegLoc()) {
2640 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2641 if (isVarArg && IsWin64) {
2642 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2643 // shadow reg if callee is a varargs function.
2644 unsigned ShadowReg = 0;
2645 switch (VA.getLocReg()) {
2646 case X86::XMM0: ShadowReg = X86::RCX; break;
2647 case X86::XMM1: ShadowReg = X86::RDX; break;
2648 case X86::XMM2: ShadowReg = X86::R8; break;
2649 case X86::XMM3: ShadowReg = X86::R9; break;
2652 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2654 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2655 assert(VA.isMemLoc());
2656 if (StackPtr.getNode() == 0)
2657 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2659 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2660 dl, DAG, VA, Flags));
2664 if (!MemOpChains.empty())
2665 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2666 &MemOpChains[0], MemOpChains.size());
2668 if (Subtarget->isPICStyleGOT()) {
2669 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2672 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2673 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2675 // If we are tail calling and generating PIC/GOT style code load the
2676 // address of the callee into ECX. The value in ecx is used as target of
2677 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2678 // for tail calls on PIC/GOT architectures. Normally we would just put the
2679 // address of GOT into ebx and then call target@PLT. But for tail calls
2680 // ebx would be restored (since ebx is callee saved) before jumping to the
2683 // Note: The actual moving to ECX is done further down.
2684 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2685 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2686 !G->getGlobal()->hasProtectedVisibility())
2687 Callee = LowerGlobalAddress(Callee, DAG);
2688 else if (isa<ExternalSymbolSDNode>(Callee))
2689 Callee = LowerExternalSymbol(Callee, DAG);
2693 if (Is64Bit && isVarArg && !IsWin64) {
2694 // From AMD64 ABI document:
2695 // For calls that may call functions that use varargs or stdargs
2696 // (prototype-less calls or calls to functions containing ellipsis (...) in
2697 // the declaration) %al is used as hidden argument to specify the number
2698 // of SSE registers used. The contents of %al do not need to match exactly
2699 // the number of registers, but must be an ubound on the number of SSE
2700 // registers used and is in the range 0 - 8 inclusive.
2702 // Count the number of XMM registers allocated.
2703 static const uint16_t XMMArgRegs[] = {
2704 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2705 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2707 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2708 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2709 && "SSE registers cannot be used when SSE is disabled");
2711 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2712 DAG.getConstant(NumXMMRegs, MVT::i8)));
2715 // For tail calls lower the arguments to the 'real' stack slot.
2717 // Force all the incoming stack arguments to be loaded from the stack
2718 // before any new outgoing arguments are stored to the stack, because the
2719 // outgoing stack slots may alias the incoming argument stack slots, and
2720 // the alias isn't otherwise explicit. This is slightly more conservative
2721 // than necessary, because it means that each store effectively depends
2722 // on every argument instead of just those arguments it would clobber.
2723 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2725 SmallVector<SDValue, 8> MemOpChains2;
2728 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2729 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2730 CCValAssign &VA = ArgLocs[i];
2733 assert(VA.isMemLoc());
2734 SDValue Arg = OutVals[i];
2735 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2736 // Create frame index.
2737 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2738 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2739 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2740 FIN = DAG.getFrameIndex(FI, getPointerTy());
2742 if (Flags.isByVal()) {
2743 // Copy relative to framepointer.
2744 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2745 if (StackPtr.getNode() == 0)
2746 StackPtr = DAG.getCopyFromReg(Chain, dl,
2747 RegInfo->getStackRegister(),
2749 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2751 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2755 // Store relative to framepointer.
2756 MemOpChains2.push_back(
2757 DAG.getStore(ArgChain, dl, Arg, FIN,
2758 MachinePointerInfo::getFixedStack(FI),
2764 if (!MemOpChains2.empty())
2765 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2766 &MemOpChains2[0], MemOpChains2.size());
2768 // Store the return address to the appropriate stack slot.
2769 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2770 getPointerTy(), RegInfo->getSlotSize(),
2774 // Build a sequence of copy-to-reg nodes chained together with token chain
2775 // and flag operands which copy the outgoing args into registers.
2777 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2778 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2779 RegsToPass[i].second, InFlag);
2780 InFlag = Chain.getValue(1);
2783 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2784 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2785 // In the 64-bit large code model, we have to make all calls
2786 // through a register, since the call instruction's 32-bit
2787 // pc-relative offset may not be large enough to hold the whole
2789 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2790 // If the callee is a GlobalAddress node (quite common, every direct call
2791 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2794 // We should use extra load for direct calls to dllimported functions in
2796 const GlobalValue *GV = G->getGlobal();
2797 if (!GV->hasDLLImportLinkage()) {
2798 unsigned char OpFlags = 0;
2799 bool ExtraLoad = false;
2800 unsigned WrapperKind = ISD::DELETED_NODE;
2802 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2803 // external symbols most go through the PLT in PIC mode. If the symbol
2804 // has hidden or protected visibility, or if it is static or local, then
2805 // we don't need to use the PLT - we can directly call it.
2806 if (Subtarget->isTargetELF() &&
2807 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2808 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2809 OpFlags = X86II::MO_PLT;
2810 } else if (Subtarget->isPICStyleStubAny() &&
2811 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2812 (!Subtarget->getTargetTriple().isMacOSX() ||
2813 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2814 // PC-relative references to external symbols should go through $stub,
2815 // unless we're building with the leopard linker or later, which
2816 // automatically synthesizes these stubs.
2817 OpFlags = X86II::MO_DARWIN_STUB;
2818 } else if (Subtarget->isPICStyleRIPRel() &&
2819 isa<Function>(GV) &&
2820 cast<Function>(GV)->getAttributes().
2821 hasAttribute(AttributeSet::FunctionIndex,
2822 Attribute::NonLazyBind)) {
2823 // If the function is marked as non-lazy, generate an indirect call
2824 // which loads from the GOT directly. This avoids runtime overhead
2825 // at the cost of eager binding (and one extra byte of encoding).
2826 OpFlags = X86II::MO_GOTPCREL;
2827 WrapperKind = X86ISD::WrapperRIP;
2831 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2832 G->getOffset(), OpFlags);
2834 // Add a wrapper if needed.
2835 if (WrapperKind != ISD::DELETED_NODE)
2836 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2837 // Add extra indirection if needed.
2839 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2840 MachinePointerInfo::getGOT(),
2841 false, false, false, 0);
2843 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2844 unsigned char OpFlags = 0;
2846 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2847 // external symbols should go through the PLT.
2848 if (Subtarget->isTargetELF() &&
2849 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2850 OpFlags = X86II::MO_PLT;
2851 } else if (Subtarget->isPICStyleStubAny() &&
2852 (!Subtarget->getTargetTriple().isMacOSX() ||
2853 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2854 // PC-relative references to external symbols should go through $stub,
2855 // unless we're building with the leopard linker or later, which
2856 // automatically synthesizes these stubs.
2857 OpFlags = X86II::MO_DARWIN_STUB;
2860 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2864 // Returns a chain & a flag for retval copy to use.
2865 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2866 SmallVector<SDValue, 8> Ops;
2868 if (!IsSibcall && isTailCall) {
2869 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2870 DAG.getIntPtrConstant(0, true), InFlag, dl);
2871 InFlag = Chain.getValue(1);
2874 Ops.push_back(Chain);
2875 Ops.push_back(Callee);
2878 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2880 // Add argument registers to the end of the list so that they are known live
2882 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2883 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2884 RegsToPass[i].second.getValueType()));
2886 // Add a register mask operand representing the call-preserved registers.
2887 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2888 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2889 assert(Mask && "Missing call preserved mask for calling convention");
2890 Ops.push_back(DAG.getRegisterMask(Mask));
2892 if (InFlag.getNode())
2893 Ops.push_back(InFlag);
2897 //// If this is the first return lowered for this function, add the regs
2898 //// to the liveout set for the function.
2899 // This isn't right, although it's probably harmless on x86; liveouts
2900 // should be computed from returns not tail calls. Consider a void
2901 // function making a tail call to a function returning int.
2902 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2905 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2906 InFlag = Chain.getValue(1);
2908 // Create the CALLSEQ_END node.
2909 unsigned NumBytesForCalleeToPush;
2910 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2911 getTargetMachine().Options.GuaranteedTailCallOpt))
2912 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2913 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2914 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2915 SR == StackStructReturn)
2916 // If this is a call to a struct-return function, the callee
2917 // pops the hidden struct pointer, so we have to push it back.
2918 // This is common for Darwin/X86, Linux & Mingw32 targets.
2919 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2920 NumBytesForCalleeToPush = 4;
2922 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2924 // Returns a flag for retval copy to use.
2926 Chain = DAG.getCALLSEQ_END(Chain,
2927 DAG.getIntPtrConstant(NumBytes, true),
2928 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2931 InFlag = Chain.getValue(1);
2934 // Handle result values, copying them out of physregs into vregs that we
2936 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2937 Ins, dl, DAG, InVals);
2940 //===----------------------------------------------------------------------===//
2941 // Fast Calling Convention (tail call) implementation
2942 //===----------------------------------------------------------------------===//
2944 // Like std call, callee cleans arguments, convention except that ECX is
2945 // reserved for storing the tail called function address. Only 2 registers are
2946 // free for argument passing (inreg). Tail call optimization is performed
2948 // * tailcallopt is enabled
2949 // * caller/callee are fastcc
2950 // On X86_64 architecture with GOT-style position independent code only local
2951 // (within module) calls are supported at the moment.
2952 // To keep the stack aligned according to platform abi the function
2953 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2954 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2955 // If a tail called function callee has more arguments than the caller the
2956 // caller needs to make sure that there is room to move the RETADDR to. This is
2957 // achieved by reserving an area the size of the argument delta right after the
2958 // original REtADDR, but before the saved framepointer or the spilled registers
2959 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2971 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2972 /// for a 16 byte align requirement.
2974 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2975 SelectionDAG& DAG) const {
2976 MachineFunction &MF = DAG.getMachineFunction();
2977 const TargetMachine &TM = MF.getTarget();
2978 const X86RegisterInfo *RegInfo =
2979 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2980 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2981 unsigned StackAlignment = TFI.getStackAlignment();
2982 uint64_t AlignMask = StackAlignment - 1;
2983 int64_t Offset = StackSize;
2984 unsigned SlotSize = RegInfo->getSlotSize();
2985 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2986 // Number smaller than 12 so just add the difference.
2987 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2989 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2990 Offset = ((~AlignMask) & Offset) + StackAlignment +
2991 (StackAlignment-SlotSize);
2996 /// MatchingStackOffset - Return true if the given stack call argument is
2997 /// already available in the same position (relatively) of the caller's
2998 /// incoming argument stack.
3000 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3001 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3002 const X86InstrInfo *TII) {
3003 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3005 if (Arg.getOpcode() == ISD::CopyFromReg) {
3006 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3007 if (!TargetRegisterInfo::isVirtualRegister(VR))
3009 MachineInstr *Def = MRI->getVRegDef(VR);
3012 if (!Flags.isByVal()) {
3013 if (!TII->isLoadFromStackSlot(Def, FI))
3016 unsigned Opcode = Def->getOpcode();
3017 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3018 Def->getOperand(1).isFI()) {
3019 FI = Def->getOperand(1).getIndex();
3020 Bytes = Flags.getByValSize();
3024 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3025 if (Flags.isByVal())
3026 // ByVal argument is passed in as a pointer but it's now being
3027 // dereferenced. e.g.
3028 // define @foo(%struct.X* %A) {
3029 // tail call @bar(%struct.X* byval %A)
3032 SDValue Ptr = Ld->getBasePtr();
3033 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3036 FI = FINode->getIndex();
3037 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3038 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3039 FI = FINode->getIndex();
3040 Bytes = Flags.getByValSize();
3044 assert(FI != INT_MAX);
3045 if (!MFI->isFixedObjectIndex(FI))
3047 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3050 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3051 /// for tail call optimization. Targets which want to do tail call
3052 /// optimization should implement this function.
3054 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3055 CallingConv::ID CalleeCC,
3057 bool isCalleeStructRet,
3058 bool isCallerStructRet,
3060 const SmallVectorImpl<ISD::OutputArg> &Outs,
3061 const SmallVectorImpl<SDValue> &OutVals,
3062 const SmallVectorImpl<ISD::InputArg> &Ins,
3063 SelectionDAG &DAG) const {
3064 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3067 // If -tailcallopt is specified, make fastcc functions tail-callable.
3068 const MachineFunction &MF = DAG.getMachineFunction();
3069 const Function *CallerF = MF.getFunction();
3071 // If the function return type is x86_fp80 and the callee return type is not,
3072 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3073 // perform a tailcall optimization here.
3074 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3077 CallingConv::ID CallerCC = CallerF->getCallingConv();
3078 bool CCMatch = CallerCC == CalleeCC;
3079 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3080 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3082 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3083 if (IsTailCallConvention(CalleeCC) && CCMatch)
3088 // Look for obvious safe cases to perform tail call optimization that do not
3089 // require ABI changes. This is what gcc calls sibcall.
3091 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3092 // emit a special epilogue.
3093 const X86RegisterInfo *RegInfo =
3094 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3095 if (RegInfo->needsStackRealignment(MF))
3098 // Also avoid sibcall optimization if either caller or callee uses struct
3099 // return semantics.
3100 if (isCalleeStructRet || isCallerStructRet)
3103 // An stdcall/thiscall caller is expected to clean up its arguments; the
3104 // callee isn't going to do that.
3105 // FIXME: this is more restrictive than needed. We could produce a tailcall
3106 // when the stack adjustment matches. For example, with a thiscall that takes
3107 // only one argument.
3108 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3109 CallerCC == CallingConv::X86_ThisCall))
3112 // Do not sibcall optimize vararg calls unless all arguments are passed via
3114 if (isVarArg && !Outs.empty()) {
3116 // Optimizing for varargs on Win64 is unlikely to be safe without
3117 // additional testing.
3118 if (IsCalleeWin64 || IsCallerWin64)
3121 SmallVector<CCValAssign, 16> ArgLocs;
3122 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3123 getTargetMachine(), ArgLocs, *DAG.getContext());
3125 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3126 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3127 if (!ArgLocs[i].isRegLoc())
3131 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3132 // stack. Therefore, if it's not used by the call it is not safe to optimize
3133 // this into a sibcall.
3134 bool Unused = false;
3135 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3142 SmallVector<CCValAssign, 16> RVLocs;
3143 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3144 getTargetMachine(), RVLocs, *DAG.getContext());
3145 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3146 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3147 CCValAssign &VA = RVLocs[i];
3148 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3153 // If the calling conventions do not match, then we'd better make sure the
3154 // results are returned in the same way as what the caller expects.
3156 SmallVector<CCValAssign, 16> RVLocs1;
3157 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3158 getTargetMachine(), RVLocs1, *DAG.getContext());
3159 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3161 SmallVector<CCValAssign, 16> RVLocs2;
3162 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3163 getTargetMachine(), RVLocs2, *DAG.getContext());
3164 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3166 if (RVLocs1.size() != RVLocs2.size())
3168 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3169 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3171 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3173 if (RVLocs1[i].isRegLoc()) {
3174 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3177 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3183 // If the callee takes no arguments then go on to check the results of the
3185 if (!Outs.empty()) {
3186 // Check if stack adjustment is needed. For now, do not do this if any
3187 // argument is passed on the stack.
3188 SmallVector<CCValAssign, 16> ArgLocs;
3189 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3190 getTargetMachine(), ArgLocs, *DAG.getContext());
3192 // Allocate shadow area for Win64
3194 CCInfo.AllocateStack(32, 8);
3196 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3197 if (CCInfo.getNextStackOffset()) {
3198 MachineFunction &MF = DAG.getMachineFunction();
3199 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3202 // Check if the arguments are already laid out in the right way as
3203 // the caller's fixed stack objects.
3204 MachineFrameInfo *MFI = MF.getFrameInfo();
3205 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3206 const X86InstrInfo *TII =
3207 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3208 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3209 CCValAssign &VA = ArgLocs[i];
3210 SDValue Arg = OutVals[i];
3211 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3212 if (VA.getLocInfo() == CCValAssign::Indirect)
3214 if (!VA.isRegLoc()) {
3215 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3222 // If the tailcall address may be in a register, then make sure it's
3223 // possible to register allocate for it. In 32-bit, the call address can
3224 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3225 // callee-saved registers are restored. These happen to be the same
3226 // registers used to pass 'inreg' arguments so watch out for those.
3227 if (!Subtarget->is64Bit() &&
3228 ((!isa<GlobalAddressSDNode>(Callee) &&
3229 !isa<ExternalSymbolSDNode>(Callee)) ||
3230 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3231 unsigned NumInRegs = 0;
3232 // In PIC we need an extra register to formulate the address computation
3234 unsigned MaxInRegs =
3235 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3237 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3238 CCValAssign &VA = ArgLocs[i];
3241 unsigned Reg = VA.getLocReg();
3244 case X86::EAX: case X86::EDX: case X86::ECX:
3245 if (++NumInRegs == MaxInRegs)
3257 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3258 const TargetLibraryInfo *libInfo) const {
3259 return X86::createFastISel(funcInfo, libInfo);
3262 //===----------------------------------------------------------------------===//
3263 // Other Lowering Hooks
3264 //===----------------------------------------------------------------------===//
3266 static bool MayFoldLoad(SDValue Op) {
3267 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3270 static bool MayFoldIntoStore(SDValue Op) {
3271 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3274 static bool isTargetShuffle(unsigned Opcode) {
3276 default: return false;
3277 case X86ISD::PSHUFD:
3278 case X86ISD::PSHUFHW:
3279 case X86ISD::PSHUFLW:
3281 case X86ISD::PALIGNR:
3282 case X86ISD::MOVLHPS:
3283 case X86ISD::MOVLHPD:
3284 case X86ISD::MOVHLPS:
3285 case X86ISD::MOVLPS:
3286 case X86ISD::MOVLPD:
3287 case X86ISD::MOVSHDUP:
3288 case X86ISD::MOVSLDUP:
3289 case X86ISD::MOVDDUP:
3292 case X86ISD::UNPCKL:
3293 case X86ISD::UNPCKH:
3294 case X86ISD::VPERMILP:
3295 case X86ISD::VPERM2X128:
3296 case X86ISD::VPERMI:
3301 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3302 SDValue V1, SelectionDAG &DAG) {
3304 default: llvm_unreachable("Unknown x86 shuffle node");
3305 case X86ISD::MOVSHDUP:
3306 case X86ISD::MOVSLDUP:
3307 case X86ISD::MOVDDUP:
3308 return DAG.getNode(Opc, dl, VT, V1);
3312 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3313 SDValue V1, unsigned TargetMask,
3314 SelectionDAG &DAG) {
3316 default: llvm_unreachable("Unknown x86 shuffle node");
3317 case X86ISD::PSHUFD:
3318 case X86ISD::PSHUFHW:
3319 case X86ISD::PSHUFLW:
3320 case X86ISD::VPERMILP:
3321 case X86ISD::VPERMI:
3322 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3326 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3327 SDValue V1, SDValue V2, unsigned TargetMask,
3328 SelectionDAG &DAG) {
3330 default: llvm_unreachable("Unknown x86 shuffle node");
3331 case X86ISD::PALIGNR:
3333 case X86ISD::VPERM2X128:
3334 return DAG.getNode(Opc, dl, VT, V1, V2,
3335 DAG.getConstant(TargetMask, MVT::i8));
3339 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3340 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3342 default: llvm_unreachable("Unknown x86 shuffle node");
3343 case X86ISD::MOVLHPS:
3344 case X86ISD::MOVLHPD:
3345 case X86ISD::MOVHLPS:
3346 case X86ISD::MOVLPS:
3347 case X86ISD::MOVLPD:
3350 case X86ISD::UNPCKL:
3351 case X86ISD::UNPCKH:
3352 return DAG.getNode(Opc, dl, VT, V1, V2);
3356 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3357 MachineFunction &MF = DAG.getMachineFunction();
3358 const X86RegisterInfo *RegInfo =
3359 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3360 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3361 int ReturnAddrIndex = FuncInfo->getRAIndex();
3363 if (ReturnAddrIndex == 0) {
3364 // Set up a frame object for the return address.
3365 unsigned SlotSize = RegInfo->getSlotSize();
3366 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3369 FuncInfo->setRAIndex(ReturnAddrIndex);
3372 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3375 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3376 bool hasSymbolicDisplacement) {
3377 // Offset should fit into 32 bit immediate field.
3378 if (!isInt<32>(Offset))
3381 // If we don't have a symbolic displacement - we don't have any extra
3383 if (!hasSymbolicDisplacement)
3386 // FIXME: Some tweaks might be needed for medium code model.
3387 if (M != CodeModel::Small && M != CodeModel::Kernel)
3390 // For small code model we assume that latest object is 16MB before end of 31
3391 // bits boundary. We may also accept pretty large negative constants knowing
3392 // that all objects are in the positive half of address space.
3393 if (M == CodeModel::Small && Offset < 16*1024*1024)
3396 // For kernel code model we know that all object resist in the negative half
3397 // of 32bits address space. We may not accept negative offsets, since they may
3398 // be just off and we may accept pretty large positive ones.
3399 if (M == CodeModel::Kernel && Offset > 0)
3405 /// isCalleePop - Determines whether the callee is required to pop its
3406 /// own arguments. Callee pop is necessary to support tail calls.
3407 bool X86::isCalleePop(CallingConv::ID CallingConv,
3408 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3412 switch (CallingConv) {
3415 case CallingConv::X86_StdCall:
3417 case CallingConv::X86_FastCall:
3419 case CallingConv::X86_ThisCall:
3421 case CallingConv::Fast:
3423 case CallingConv::GHC:
3425 case CallingConv::HiPE:
3430 /// \brief Return true if the condition is an unsigned comparison operation.
3431 static bool isX86CCUnsigned(unsigned X86CC) {
3433 default: llvm_unreachable("Invalid integer condition!");
3434 case X86::COND_E: return true;
3435 case X86::COND_G: return false;
3436 case X86::COND_GE: return false;
3437 case X86::COND_L: return false;
3438 case X86::COND_LE: return false;
3439 case X86::COND_NE: return true;
3440 case X86::COND_B: return true;
3441 case X86::COND_A: return true;
3442 case X86::COND_BE: return true;
3443 case X86::COND_AE: return true;
3445 llvm_unreachable("covered switch fell through?!");
3448 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3449 /// specific condition code, returning the condition code and the LHS/RHS of the
3450 /// comparison to make.
3451 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3452 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3454 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3455 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3456 // X > -1 -> X == 0, jump !sign.
3457 RHS = DAG.getConstant(0, RHS.getValueType());
3458 return X86::COND_NS;
3460 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3461 // X < 0 -> X == 0, jump on sign.
3464 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3466 RHS = DAG.getConstant(0, RHS.getValueType());
3467 return X86::COND_LE;
3471 switch (SetCCOpcode) {
3472 default: llvm_unreachable("Invalid integer condition!");
3473 case ISD::SETEQ: return X86::COND_E;
3474 case ISD::SETGT: return X86::COND_G;
3475 case ISD::SETGE: return X86::COND_GE;
3476 case ISD::SETLT: return X86::COND_L;
3477 case ISD::SETLE: return X86::COND_LE;
3478 case ISD::SETNE: return X86::COND_NE;
3479 case ISD::SETULT: return X86::COND_B;
3480 case ISD::SETUGT: return X86::COND_A;
3481 case ISD::SETULE: return X86::COND_BE;
3482 case ISD::SETUGE: return X86::COND_AE;
3486 // First determine if it is required or is profitable to flip the operands.
3488 // If LHS is a foldable load, but RHS is not, flip the condition.
3489 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3490 !ISD::isNON_EXTLoad(RHS.getNode())) {
3491 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3492 std::swap(LHS, RHS);
3495 switch (SetCCOpcode) {
3501 std::swap(LHS, RHS);
3505 // On a floating point condition, the flags are set as follows:
3507 // 0 | 0 | 0 | X > Y
3508 // 0 | 0 | 1 | X < Y
3509 // 1 | 0 | 0 | X == Y
3510 // 1 | 1 | 1 | unordered
3511 switch (SetCCOpcode) {
3512 default: llvm_unreachable("Condcode should be pre-legalized away");
3514 case ISD::SETEQ: return X86::COND_E;
3515 case ISD::SETOLT: // flipped
3517 case ISD::SETGT: return X86::COND_A;
3518 case ISD::SETOLE: // flipped
3520 case ISD::SETGE: return X86::COND_AE;
3521 case ISD::SETUGT: // flipped
3523 case ISD::SETLT: return X86::COND_B;
3524 case ISD::SETUGE: // flipped
3526 case ISD::SETLE: return X86::COND_BE;
3528 case ISD::SETNE: return X86::COND_NE;
3529 case ISD::SETUO: return X86::COND_P;
3530 case ISD::SETO: return X86::COND_NP;
3532 case ISD::SETUNE: return X86::COND_INVALID;
3536 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3537 /// code. Current x86 isa includes the following FP cmov instructions:
3538 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3539 static bool hasFPCMov(unsigned X86CC) {
3555 /// isFPImmLegal - Returns true if the target can instruction select the
3556 /// specified FP immediate natively. If false, the legalizer will
3557 /// materialize the FP immediate as a load from a constant pool.
3558 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3559 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3560 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3566 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3567 /// the specified range (L, H].
3568 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3569 return (Val < 0) || (Val >= Low && Val < Hi);
3572 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3573 /// specified value.
3574 static bool isUndefOrEqual(int Val, int CmpVal) {
3575 return (Val < 0 || Val == CmpVal);
3578 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3579 /// from position Pos and ending in Pos+Size, falls within the specified
3580 /// sequential range (L, L+Pos]. or is undef.
3581 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3582 unsigned Pos, unsigned Size, int Low) {
3583 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3584 if (!isUndefOrEqual(Mask[i], Low))
3589 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3590 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3591 /// the second operand.
3592 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3593 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3594 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3595 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3596 return (Mask[0] < 2 && Mask[1] < 2);
3600 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3601 /// is suitable for input to PSHUFHW.
3602 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3603 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3606 // Lower quadword copied in order or undef.
3607 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3610 // Upper quadword shuffled.
3611 for (unsigned i = 4; i != 8; ++i)
3612 if (!isUndefOrInRange(Mask[i], 4, 8))
3615 if (VT == MVT::v16i16) {
3616 // Lower quadword copied in order or undef.
3617 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3620 // Upper quadword shuffled.
3621 for (unsigned i = 12; i != 16; ++i)
3622 if (!isUndefOrInRange(Mask[i], 12, 16))
3629 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3630 /// is suitable for input to PSHUFLW.
3631 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3632 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3635 // Upper quadword copied in order.
3636 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3639 // Lower quadword shuffled.
3640 for (unsigned i = 0; i != 4; ++i)
3641 if (!isUndefOrInRange(Mask[i], 0, 4))
3644 if (VT == MVT::v16i16) {
3645 // Upper quadword copied in order.
3646 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3649 // Lower quadword shuffled.
3650 for (unsigned i = 8; i != 12; ++i)
3651 if (!isUndefOrInRange(Mask[i], 8, 12))
3658 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3659 /// is suitable for input to PALIGNR.
3660 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3661 const X86Subtarget *Subtarget) {
3662 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3663 (VT.is256BitVector() && !Subtarget->hasInt256()))
3666 unsigned NumElts = VT.getVectorNumElements();
3667 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3668 unsigned NumLaneElts = NumElts/NumLanes;
3670 // Do not handle 64-bit element shuffles with palignr.
3671 if (NumLaneElts == 2)
3674 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3676 for (i = 0; i != NumLaneElts; ++i) {
3681 // Lane is all undef, go to next lane
3682 if (i == NumLaneElts)
3685 int Start = Mask[i+l];
3687 // Make sure its in this lane in one of the sources
3688 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3689 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3692 // If not lane 0, then we must match lane 0
3693 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3696 // Correct second source to be contiguous with first source
3697 if (Start >= (int)NumElts)
3698 Start -= NumElts - NumLaneElts;
3700 // Make sure we're shifting in the right direction.
3701 if (Start <= (int)(i+l))
3706 // Check the rest of the elements to see if they are consecutive.
3707 for (++i; i != NumLaneElts; ++i) {
3708 int Idx = Mask[i+l];
3710 // Make sure its in this lane
3711 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3712 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3715 // If not lane 0, then we must match lane 0
3716 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3719 if (Idx >= (int)NumElts)
3720 Idx -= NumElts - NumLaneElts;
3722 if (!isUndefOrEqual(Idx, Start+i))
3731 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3732 /// the two vector operands have swapped position.
3733 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3734 unsigned NumElems) {
3735 for (unsigned i = 0; i != NumElems; ++i) {
3739 else if (idx < (int)NumElems)
3740 Mask[i] = idx + NumElems;
3742 Mask[i] = idx - NumElems;
3746 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3747 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3748 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3749 /// reverse of what x86 shuffles want.
3750 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3752 unsigned NumElems = VT.getVectorNumElements();
3753 unsigned NumLanes = VT.getSizeInBits()/128;
3754 unsigned NumLaneElems = NumElems/NumLanes;
3756 if (NumLaneElems != 2 && NumLaneElems != 4)
3759 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3760 bool symetricMaskRequired =
3761 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3763 // VSHUFPSY divides the resulting vector into 4 chunks.
3764 // The sources are also splitted into 4 chunks, and each destination
3765 // chunk must come from a different source chunk.
3767 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3768 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3770 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3771 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3773 // VSHUFPDY divides the resulting vector into 4 chunks.
3774 // The sources are also splitted into 4 chunks, and each destination
3775 // chunk must come from a different source chunk.
3777 // SRC1 => X3 X2 X1 X0
3778 // SRC2 => Y3 Y2 Y1 Y0
3780 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3782 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3783 unsigned HalfLaneElems = NumLaneElems/2;
3784 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3785 for (unsigned i = 0; i != NumLaneElems; ++i) {
3786 int Idx = Mask[i+l];
3787 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3788 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3790 // For VSHUFPSY, the mask of the second half must be the same as the
3791 // first but with the appropriate offsets. This works in the same way as
3792 // VPERMILPS works with masks.
3793 if (!symetricMaskRequired || Idx < 0)
3795 if (MaskVal[i] < 0) {
3796 MaskVal[i] = Idx - l;
3799 if ((signed)(Idx - l) != MaskVal[i])
3807 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3808 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3809 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3810 if (!VT.is128BitVector())
3813 unsigned NumElems = VT.getVectorNumElements();
3818 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3819 return isUndefOrEqual(Mask[0], 6) &&
3820 isUndefOrEqual(Mask[1], 7) &&
3821 isUndefOrEqual(Mask[2], 2) &&
3822 isUndefOrEqual(Mask[3], 3);
3825 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3826 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3828 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3829 if (!VT.is128BitVector())
3832 unsigned NumElems = VT.getVectorNumElements();
3837 return isUndefOrEqual(Mask[0], 2) &&
3838 isUndefOrEqual(Mask[1], 3) &&
3839 isUndefOrEqual(Mask[2], 2) &&
3840 isUndefOrEqual(Mask[3], 3);
3843 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3844 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3845 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3846 if (!VT.is128BitVector())
3849 unsigned NumElems = VT.getVectorNumElements();
3851 if (NumElems != 2 && NumElems != 4)
3854 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3855 if (!isUndefOrEqual(Mask[i], i + NumElems))
3858 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3859 if (!isUndefOrEqual(Mask[i], i))
3865 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3866 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3867 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3868 if (!VT.is128BitVector())
3871 unsigned NumElems = VT.getVectorNumElements();
3873 if (NumElems != 2 && NumElems != 4)
3876 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3877 if (!isUndefOrEqual(Mask[i], i))
3880 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3881 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3888 // Some special combinations that can be optimized.
3891 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3892 SelectionDAG &DAG) {
3893 MVT VT = SVOp->getSimpleValueType(0);
3896 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3899 ArrayRef<int> Mask = SVOp->getMask();
3901 // These are the special masks that may be optimized.
3902 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3903 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3904 bool MatchEvenMask = true;
3905 bool MatchOddMask = true;
3906 for (int i=0; i<8; ++i) {
3907 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3908 MatchEvenMask = false;
3909 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3910 MatchOddMask = false;
3913 if (!MatchEvenMask && !MatchOddMask)
3916 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3918 SDValue Op0 = SVOp->getOperand(0);
3919 SDValue Op1 = SVOp->getOperand(1);
3921 if (MatchEvenMask) {
3922 // Shift the second operand right to 32 bits.
3923 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3924 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3926 // Shift the first operand left to 32 bits.
3927 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3928 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3930 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3931 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3934 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3935 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3936 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3937 bool HasInt256, bool V2IsSplat = false) {
3939 assert(VT.getSizeInBits() >= 128 &&
3940 "Unsupported vector type for unpckl");
3942 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3944 unsigned NumOf256BitLanes;
3945 unsigned NumElts = VT.getVectorNumElements();
3946 if (VT.is256BitVector()) {
3947 if (NumElts != 4 && NumElts != 8 &&
3948 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3951 NumOf256BitLanes = 1;
3952 } else if (VT.is512BitVector()) {
3953 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3954 "Unsupported vector type for unpckh");
3956 NumOf256BitLanes = 2;
3959 NumOf256BitLanes = 1;
3962 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3963 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3965 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3966 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3967 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3968 int BitI = Mask[l256*NumEltsInStride+l+i];
3969 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3970 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3972 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3974 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3982 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3983 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3984 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3985 bool HasInt256, bool V2IsSplat = false) {
3986 assert(VT.getSizeInBits() >= 128 &&
3987 "Unsupported vector type for unpckh");
3989 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3991 unsigned NumOf256BitLanes;
3992 unsigned NumElts = VT.getVectorNumElements();
3993 if (VT.is256BitVector()) {
3994 if (NumElts != 4 && NumElts != 8 &&
3995 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3998 NumOf256BitLanes = 1;
3999 } else if (VT.is512BitVector()) {
4000 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4001 "Unsupported vector type for unpckh");
4003 NumOf256BitLanes = 2;
4006 NumOf256BitLanes = 1;
4009 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4010 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4012 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4013 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4014 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4015 int BitI = Mask[l256*NumEltsInStride+l+i];
4016 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4017 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4019 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4021 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4029 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4030 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4032 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4033 unsigned NumElts = VT.getVectorNumElements();
4034 bool Is256BitVec = VT.is256BitVector();
4036 if (VT.is512BitVector())
4038 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4039 "Unsupported vector type for unpckh");
4041 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4042 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4045 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4046 // FIXME: Need a better way to get rid of this, there's no latency difference
4047 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4048 // the former later. We should also remove the "_undef" special mask.
4049 if (NumElts == 4 && Is256BitVec)
4052 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4053 // independently on 128-bit lanes.
4054 unsigned NumLanes = VT.getSizeInBits()/128;
4055 unsigned NumLaneElts = NumElts/NumLanes;
4057 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4058 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4059 int BitI = Mask[l+i];
4060 int BitI1 = Mask[l+i+1];
4062 if (!isUndefOrEqual(BitI, j))
4064 if (!isUndefOrEqual(BitI1, j))
4072 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4073 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4075 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4076 unsigned NumElts = VT.getVectorNumElements();
4078 if (VT.is512BitVector())
4081 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4082 "Unsupported vector type for unpckh");
4084 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4085 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4088 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4089 // independently on 128-bit lanes.
4090 unsigned NumLanes = VT.getSizeInBits()/128;
4091 unsigned NumLaneElts = NumElts/NumLanes;
4093 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4094 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4095 int BitI = Mask[l+i];
4096 int BitI1 = Mask[l+i+1];
4097 if (!isUndefOrEqual(BitI, j))
4099 if (!isUndefOrEqual(BitI1, j))
4106 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4107 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4108 /// MOVSD, and MOVD, i.e. setting the lowest element.
4109 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4110 if (VT.getVectorElementType().getSizeInBits() < 32)
4112 if (!VT.is128BitVector())
4115 unsigned NumElts = VT.getVectorNumElements();
4117 if (!isUndefOrEqual(Mask[0], NumElts))
4120 for (unsigned i = 1; i != NumElts; ++i)
4121 if (!isUndefOrEqual(Mask[i], i))
4127 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4128 /// as permutations between 128-bit chunks or halves. As an example: this
4130 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4131 /// The first half comes from the second half of V1 and the second half from the
4132 /// the second half of V2.
4133 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4134 if (!HasFp256 || !VT.is256BitVector())
4137 // The shuffle result is divided into half A and half B. In total the two
4138 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4139 // B must come from C, D, E or F.
4140 unsigned HalfSize = VT.getVectorNumElements()/2;
4141 bool MatchA = false, MatchB = false;
4143 // Check if A comes from one of C, D, E, F.
4144 for (unsigned Half = 0; Half != 4; ++Half) {
4145 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4151 // Check if B comes from one of C, D, E, F.
4152 for (unsigned Half = 0; Half != 4; ++Half) {
4153 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4159 return MatchA && MatchB;
4162 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4163 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4164 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4165 MVT VT = SVOp->getSimpleValueType(0);
4167 unsigned HalfSize = VT.getVectorNumElements()/2;
4169 unsigned FstHalf = 0, SndHalf = 0;
4170 for (unsigned i = 0; i < HalfSize; ++i) {
4171 if (SVOp->getMaskElt(i) > 0) {
4172 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4176 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4177 if (SVOp->getMaskElt(i) > 0) {
4178 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4183 return (FstHalf | (SndHalf << 4));
4186 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4187 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4188 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4192 unsigned NumElts = VT.getVectorNumElements();
4194 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4195 for (unsigned i = 0; i != NumElts; ++i) {
4198 Imm8 |= Mask[i] << (i*2);
4203 unsigned LaneSize = 4;
4204 SmallVector<int, 4> MaskVal(LaneSize, -1);
4206 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4207 for (unsigned i = 0; i != LaneSize; ++i) {
4208 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4212 if (MaskVal[i] < 0) {
4213 MaskVal[i] = Mask[i+l] - l;
4214 Imm8 |= MaskVal[i] << (i*2);
4217 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4224 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4225 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4226 /// Note that VPERMIL mask matching is different depending whether theunderlying
4227 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4228 /// to the same elements of the low, but to the higher half of the source.
4229 /// In VPERMILPD the two lanes could be shuffled independently of each other
4230 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4231 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4232 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4233 if (VT.getSizeInBits() < 256 || EltSize < 32)
4235 bool symetricMaskRequired = (EltSize == 32);
4236 unsigned NumElts = VT.getVectorNumElements();
4238 unsigned NumLanes = VT.getSizeInBits()/128;
4239 unsigned LaneSize = NumElts/NumLanes;
4240 // 2 or 4 elements in one lane
4242 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4243 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4244 for (unsigned i = 0; i != LaneSize; ++i) {
4245 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4247 if (symetricMaskRequired) {
4248 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4249 ExpectedMaskVal[i] = Mask[i+l] - l;
4252 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4260 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4261 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4262 /// element of vector 2 and the other elements to come from vector 1 in order.
4263 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4264 bool V2IsSplat = false, bool V2IsUndef = false) {
4265 if (!VT.is128BitVector())
4268 unsigned NumOps = VT.getVectorNumElements();
4269 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4272 if (!isUndefOrEqual(Mask[0], 0))
4275 for (unsigned i = 1; i != NumOps; ++i)
4276 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4277 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4278 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4284 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4285 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4286 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4287 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4288 const X86Subtarget *Subtarget) {
4289 if (!Subtarget->hasSSE3())
4292 unsigned NumElems = VT.getVectorNumElements();
4294 if ((VT.is128BitVector() && NumElems != 4) ||
4295 (VT.is256BitVector() && NumElems != 8) ||
4296 (VT.is512BitVector() && NumElems != 16))
4299 // "i+1" is the value the indexed mask element must have
4300 for (unsigned i = 0; i != NumElems; i += 2)
4301 if (!isUndefOrEqual(Mask[i], i+1) ||
4302 !isUndefOrEqual(Mask[i+1], i+1))
4308 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4309 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4310 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4311 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4312 const X86Subtarget *Subtarget) {
4313 if (!Subtarget->hasSSE3())
4316 unsigned NumElems = VT.getVectorNumElements();
4318 if ((VT.is128BitVector() && NumElems != 4) ||
4319 (VT.is256BitVector() && NumElems != 8) ||
4320 (VT.is512BitVector() && NumElems != 16))
4323 // "i" is the value the indexed mask element must have
4324 for (unsigned i = 0; i != NumElems; i += 2)
4325 if (!isUndefOrEqual(Mask[i], i) ||
4326 !isUndefOrEqual(Mask[i+1], i))
4332 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4333 /// specifies a shuffle of elements that is suitable for input to 256-bit
4334 /// version of MOVDDUP.
4335 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4336 if (!HasFp256 || !VT.is256BitVector())
4339 unsigned NumElts = VT.getVectorNumElements();
4343 for (unsigned i = 0; i != NumElts/2; ++i)
4344 if (!isUndefOrEqual(Mask[i], 0))
4346 for (unsigned i = NumElts/2; i != NumElts; ++i)
4347 if (!isUndefOrEqual(Mask[i], NumElts/2))
4352 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4353 /// specifies a shuffle of elements that is suitable for input to 128-bit
4354 /// version of MOVDDUP.
4355 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4356 if (!VT.is128BitVector())
4359 unsigned e = VT.getVectorNumElements() / 2;
4360 for (unsigned i = 0; i != e; ++i)
4361 if (!isUndefOrEqual(Mask[i], i))
4363 for (unsigned i = 0; i != e; ++i)
4364 if (!isUndefOrEqual(Mask[e+i], i))
4369 /// isVEXTRACTIndex - Return true if the specified
4370 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4371 /// suitable for instruction that extract 128 or 256 bit vectors
4372 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4373 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4374 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4377 // The index should be aligned on a vecWidth-bit boundary.
4379 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4381 MVT VT = N->getSimpleValueType(0);
4382 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4383 bool Result = (Index * ElSize) % vecWidth == 0;
4388 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4389 /// operand specifies a subvector insert that is suitable for input to
4390 /// insertion of 128 or 256-bit subvectors
4391 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4392 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4393 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4395 // The index should be aligned on a vecWidth-bit boundary.
4397 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4399 MVT VT = N->getSimpleValueType(0);
4400 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4401 bool Result = (Index * ElSize) % vecWidth == 0;
4406 bool X86::isVINSERT128Index(SDNode *N) {
4407 return isVINSERTIndex(N, 128);
4410 bool X86::isVINSERT256Index(SDNode *N) {
4411 return isVINSERTIndex(N, 256);
4414 bool X86::isVEXTRACT128Index(SDNode *N) {
4415 return isVEXTRACTIndex(N, 128);
4418 bool X86::isVEXTRACT256Index(SDNode *N) {
4419 return isVEXTRACTIndex(N, 256);
4422 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4423 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4424 /// Handles 128-bit and 256-bit.
4425 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4426 MVT VT = N->getSimpleValueType(0);
4428 assert((VT.getSizeInBits() >= 128) &&
4429 "Unsupported vector type for PSHUF/SHUFP");
4431 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4432 // independently on 128-bit lanes.
4433 unsigned NumElts = VT.getVectorNumElements();
4434 unsigned NumLanes = VT.getSizeInBits()/128;
4435 unsigned NumLaneElts = NumElts/NumLanes;
4437 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4438 "Only supports 2, 4 or 8 elements per lane");
4440 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4442 for (unsigned i = 0; i != NumElts; ++i) {
4443 int Elt = N->getMaskElt(i);
4444 if (Elt < 0) continue;
4445 Elt &= NumLaneElts - 1;
4446 unsigned ShAmt = (i << Shift) % 8;
4447 Mask |= Elt << ShAmt;
4453 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4454 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4455 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4456 MVT VT = N->getSimpleValueType(0);
4458 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4459 "Unsupported vector type for PSHUFHW");
4461 unsigned NumElts = VT.getVectorNumElements();
4464 for (unsigned l = 0; l != NumElts; l += 8) {
4465 // 8 nodes per lane, but we only care about the last 4.
4466 for (unsigned i = 0; i < 4; ++i) {
4467 int Elt = N->getMaskElt(l+i+4);
4468 if (Elt < 0) continue;
4469 Elt &= 0x3; // only 2-bits.
4470 Mask |= Elt << (i * 2);
4477 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4478 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4479 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4480 MVT VT = N->getSimpleValueType(0);
4482 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4483 "Unsupported vector type for PSHUFHW");
4485 unsigned NumElts = VT.getVectorNumElements();
4488 for (unsigned l = 0; l != NumElts; l += 8) {
4489 // 8 nodes per lane, but we only care about the first 4.
4490 for (unsigned i = 0; i < 4; ++i) {
4491 int Elt = N->getMaskElt(l+i);
4492 if (Elt < 0) continue;
4493 Elt &= 0x3; // only 2-bits
4494 Mask |= Elt << (i * 2);
4501 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4502 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4503 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4504 MVT VT = SVOp->getSimpleValueType(0);
4505 unsigned EltSize = VT.is512BitVector() ? 1 :
4506 VT.getVectorElementType().getSizeInBits() >> 3;
4508 unsigned NumElts = VT.getVectorNumElements();
4509 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4510 unsigned NumLaneElts = NumElts/NumLanes;
4514 for (i = 0; i != NumElts; ++i) {
4515 Val = SVOp->getMaskElt(i);
4519 if (Val >= (int)NumElts)
4520 Val -= NumElts - NumLaneElts;
4522 assert(Val - i > 0 && "PALIGNR imm should be positive");
4523 return (Val - i) * EltSize;
4526 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4527 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4528 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4529 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4532 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4534 MVT VecVT = N->getOperand(0).getSimpleValueType();
4535 MVT ElVT = VecVT.getVectorElementType();
4537 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4538 return Index / NumElemsPerChunk;
4541 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4542 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4543 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4544 llvm_unreachable("Illegal insert subvector for VINSERT");
4547 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4549 MVT VecVT = N->getSimpleValueType(0);
4550 MVT ElVT = VecVT.getVectorElementType();
4552 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4553 return Index / NumElemsPerChunk;
4556 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4557 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4558 /// and VINSERTI128 instructions.
4559 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4560 return getExtractVEXTRACTImmediate(N, 128);
4563 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4564 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4565 /// and VINSERTI64x4 instructions.
4566 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4567 return getExtractVEXTRACTImmediate(N, 256);
4570 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4571 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4572 /// and VINSERTI128 instructions.
4573 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4574 return getInsertVINSERTImmediate(N, 128);
4577 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4578 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4579 /// and VINSERTI64x4 instructions.
4580 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4581 return getInsertVINSERTImmediate(N, 256);
4584 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4586 bool X86::isZeroNode(SDValue Elt) {
4587 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4588 return CN->isNullValue();
4589 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4590 return CFP->getValueAPF().isPosZero();
4594 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4595 /// their permute mask.
4596 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4597 SelectionDAG &DAG) {
4598 MVT VT = SVOp->getSimpleValueType(0);
4599 unsigned NumElems = VT.getVectorNumElements();
4600 SmallVector<int, 8> MaskVec;
4602 for (unsigned i = 0; i != NumElems; ++i) {
4603 int Idx = SVOp->getMaskElt(i);
4605 if (Idx < (int)NumElems)
4610 MaskVec.push_back(Idx);
4612 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4613 SVOp->getOperand(0), &MaskVec[0]);
4616 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4617 /// match movhlps. The lower half elements should come from upper half of
4618 /// V1 (and in order), and the upper half elements should come from the upper
4619 /// half of V2 (and in order).
4620 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4621 if (!VT.is128BitVector())
4623 if (VT.getVectorNumElements() != 4)
4625 for (unsigned i = 0, e = 2; i != e; ++i)
4626 if (!isUndefOrEqual(Mask[i], i+2))
4628 for (unsigned i = 2; i != 4; ++i)
4629 if (!isUndefOrEqual(Mask[i], i+4))
4634 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4635 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4637 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4638 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4640 N = N->getOperand(0).getNode();
4641 if (!ISD::isNON_EXTLoad(N))
4644 *LD = cast<LoadSDNode>(N);
4648 // Test whether the given value is a vector value which will be legalized
4650 static bool WillBeConstantPoolLoad(SDNode *N) {
4651 if (N->getOpcode() != ISD::BUILD_VECTOR)
4654 // Check for any non-constant elements.
4655 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4656 switch (N->getOperand(i).getNode()->getOpcode()) {
4658 case ISD::ConstantFP:
4665 // Vectors of all-zeros and all-ones are materialized with special
4666 // instructions rather than being loaded.
4667 return !ISD::isBuildVectorAllZeros(N) &&
4668 !ISD::isBuildVectorAllOnes(N);
4671 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4672 /// match movlp{s|d}. The lower half elements should come from lower half of
4673 /// V1 (and in order), and the upper half elements should come from the upper
4674 /// half of V2 (and in order). And since V1 will become the source of the
4675 /// MOVLP, it must be either a vector load or a scalar load to vector.
4676 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4677 ArrayRef<int> Mask, MVT VT) {
4678 if (!VT.is128BitVector())
4681 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4683 // Is V2 is a vector load, don't do this transformation. We will try to use
4684 // load folding shufps op.
4685 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4688 unsigned NumElems = VT.getVectorNumElements();
4690 if (NumElems != 2 && NumElems != 4)
4692 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[i], i))
4695 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4696 if (!isUndefOrEqual(Mask[i], i+NumElems))
4701 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4703 static bool isSplatVector(SDNode *N) {
4704 if (N->getOpcode() != ISD::BUILD_VECTOR)
4707 SDValue SplatValue = N->getOperand(0);
4708 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4709 if (N->getOperand(i) != SplatValue)
4714 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4715 /// to an zero vector.
4716 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4717 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4718 SDValue V1 = N->getOperand(0);
4719 SDValue V2 = N->getOperand(1);
4720 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4721 for (unsigned i = 0; i != NumElems; ++i) {
4722 int Idx = N->getMaskElt(i);
4723 if (Idx >= (int)NumElems) {
4724 unsigned Opc = V2.getOpcode();
4725 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4727 if (Opc != ISD::BUILD_VECTOR ||
4728 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4730 } else if (Idx >= 0) {
4731 unsigned Opc = V1.getOpcode();
4732 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4734 if (Opc != ISD::BUILD_VECTOR ||
4735 !X86::isZeroNode(V1.getOperand(Idx)))
4742 /// getZeroVector - Returns a vector of specified type with all zero elements.
4744 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4745 SelectionDAG &DAG, SDLoc dl) {
4746 assert(VT.isVector() && "Expected a vector type");
4748 // Always build SSE zero vectors as <4 x i32> bitcasted
4749 // to their dest type. This ensures they get CSE'd.
4751 if (VT.is128BitVector()) { // SSE
4752 if (Subtarget->hasSSE2()) { // SSE2
4753 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4754 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4756 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4757 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4759 } else if (VT.is256BitVector()) { // AVX
4760 if (Subtarget->hasInt256()) { // AVX2
4761 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4762 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4763 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4764 array_lengthof(Ops));
4766 // 256-bit logic and arithmetic instructions in AVX are all
4767 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4768 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4769 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4770 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4771 array_lengthof(Ops));
4773 } else if (VT.is512BitVector()) { // AVX-512
4774 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4775 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4776 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4777 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4779 llvm_unreachable("Unexpected vector type");
4781 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4784 /// getOnesVector - Returns a vector of specified type with all bits set.
4785 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4786 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4787 /// Then bitcast to their original type, ensuring they get CSE'd.
4788 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4790 assert(VT.isVector() && "Expected a vector type");
4792 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4794 if (VT.is256BitVector()) {
4795 if (HasInt256) { // AVX2
4796 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4797 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4798 array_lengthof(Ops));
4800 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4801 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4803 } else if (VT.is128BitVector()) {
4804 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4806 llvm_unreachable("Unexpected vector type");
4808 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4811 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4812 /// that point to V2 points to its first element.
4813 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4814 for (unsigned i = 0; i != NumElems; ++i) {
4815 if (Mask[i] > (int)NumElems) {
4821 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4822 /// operation of specified width.
4823 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4825 unsigned NumElems = VT.getVectorNumElements();
4826 SmallVector<int, 8> Mask;
4827 Mask.push_back(NumElems);
4828 for (unsigned i = 1; i != NumElems; ++i)
4830 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4833 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4834 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4836 unsigned NumElems = VT.getVectorNumElements();
4837 SmallVector<int, 8> Mask;
4838 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4840 Mask.push_back(i + NumElems);
4842 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4845 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4846 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4848 unsigned NumElems = VT.getVectorNumElements();
4849 SmallVector<int, 8> Mask;
4850 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4851 Mask.push_back(i + Half);
4852 Mask.push_back(i + NumElems + Half);
4854 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4857 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4858 // a generic shuffle instruction because the target has no such instructions.
4859 // Generate shuffles which repeat i16 and i8 several times until they can be
4860 // represented by v4f32 and then be manipulated by target suported shuffles.
4861 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4862 MVT VT = V.getSimpleValueType();
4863 int NumElems = VT.getVectorNumElements();
4866 while (NumElems > 4) {
4867 if (EltNo < NumElems/2) {
4868 V = getUnpackl(DAG, dl, VT, V, V);
4870 V = getUnpackh(DAG, dl, VT, V, V);
4871 EltNo -= NumElems/2;
4878 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4879 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4880 MVT VT = V.getSimpleValueType();
4883 if (VT.is128BitVector()) {
4884 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4885 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4886 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4888 } else if (VT.is256BitVector()) {
4889 // To use VPERMILPS to splat scalars, the second half of indicies must
4890 // refer to the higher part, which is a duplication of the lower one,
4891 // because VPERMILPS can only handle in-lane permutations.
4892 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4893 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4895 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4896 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4899 llvm_unreachable("Vector size not supported");
4901 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4904 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4905 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4906 MVT SrcVT = SV->getSimpleValueType(0);
4907 SDValue V1 = SV->getOperand(0);
4910 int EltNo = SV->getSplatIndex();
4911 int NumElems = SrcVT.getVectorNumElements();
4912 bool Is256BitVec = SrcVT.is256BitVector();
4914 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4915 "Unknown how to promote splat for type");
4917 // Extract the 128-bit part containing the splat element and update
4918 // the splat element index when it refers to the higher register.
4920 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4921 if (EltNo >= NumElems/2)
4922 EltNo -= NumElems/2;
4925 // All i16 and i8 vector types can't be used directly by a generic shuffle
4926 // instruction because the target has no such instruction. Generate shuffles
4927 // which repeat i16 and i8 several times until they fit in i32, and then can
4928 // be manipulated by target suported shuffles.
4929 MVT EltVT = SrcVT.getVectorElementType();
4930 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4931 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4933 // Recreate the 256-bit vector and place the same 128-bit vector
4934 // into the low and high part. This is necessary because we want
4935 // to use VPERM* to shuffle the vectors
4937 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4940 return getLegalSplat(DAG, V1, EltNo);
4943 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4944 /// vector of zero or undef vector. This produces a shuffle where the low
4945 /// element of V2 is swizzled into the zero/undef vector, landing at element
4946 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4947 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4949 const X86Subtarget *Subtarget,
4950 SelectionDAG &DAG) {
4951 MVT VT = V2.getSimpleValueType();
4953 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4954 unsigned NumElems = VT.getVectorNumElements();
4955 SmallVector<int, 16> MaskVec;
4956 for (unsigned i = 0; i != NumElems; ++i)
4957 // If this is the insertion idx, put the low elt of V2 here.
4958 MaskVec.push_back(i == Idx ? NumElems : i);
4959 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4962 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4963 /// target specific opcode. Returns true if the Mask could be calculated.
4964 /// Sets IsUnary to true if only uses one source.
4965 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4966 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4967 unsigned NumElems = VT.getVectorNumElements();
4971 switch(N->getOpcode()) {
4973 ImmN = N->getOperand(N->getNumOperands()-1);
4974 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4976 case X86ISD::UNPCKH:
4977 DecodeUNPCKHMask(VT, Mask);
4979 case X86ISD::UNPCKL:
4980 DecodeUNPCKLMask(VT, Mask);
4982 case X86ISD::MOVHLPS:
4983 DecodeMOVHLPSMask(NumElems, Mask);
4985 case X86ISD::MOVLHPS:
4986 DecodeMOVLHPSMask(NumElems, Mask);
4988 case X86ISD::PALIGNR:
4989 ImmN = N->getOperand(N->getNumOperands()-1);
4990 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4992 case X86ISD::PSHUFD:
4993 case X86ISD::VPERMILP:
4994 ImmN = N->getOperand(N->getNumOperands()-1);
4995 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4998 case X86ISD::PSHUFHW:
4999 ImmN = N->getOperand(N->getNumOperands()-1);
5000 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5003 case X86ISD::PSHUFLW:
5004 ImmN = N->getOperand(N->getNumOperands()-1);
5005 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5008 case X86ISD::VPERMI:
5009 ImmN = N->getOperand(N->getNumOperands()-1);
5010 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5014 case X86ISD::MOVSD: {
5015 // The index 0 always comes from the first element of the second source,
5016 // this is why MOVSS and MOVSD are used in the first place. The other
5017 // elements come from the other positions of the first source vector
5018 Mask.push_back(NumElems);
5019 for (unsigned i = 1; i != NumElems; ++i) {
5024 case X86ISD::VPERM2X128:
5025 ImmN = N->getOperand(N->getNumOperands()-1);
5026 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5027 if (Mask.empty()) return false;
5029 case X86ISD::MOVDDUP:
5030 case X86ISD::MOVLHPD:
5031 case X86ISD::MOVLPD:
5032 case X86ISD::MOVLPS:
5033 case X86ISD::MOVSHDUP:
5034 case X86ISD::MOVSLDUP:
5035 // Not yet implemented
5037 default: llvm_unreachable("unknown target shuffle node");
5043 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5044 /// element of the result of the vector shuffle.
5045 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5048 return SDValue(); // Limit search depth.
5050 SDValue V = SDValue(N, 0);
5051 EVT VT = V.getValueType();
5052 unsigned Opcode = V.getOpcode();
5054 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5055 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5056 int Elt = SV->getMaskElt(Index);
5059 return DAG.getUNDEF(VT.getVectorElementType());
5061 unsigned NumElems = VT.getVectorNumElements();
5062 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5063 : SV->getOperand(1);
5064 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5067 // Recurse into target specific vector shuffles to find scalars.
5068 if (isTargetShuffle(Opcode)) {
5069 MVT ShufVT = V.getSimpleValueType();
5070 unsigned NumElems = ShufVT.getVectorNumElements();
5071 SmallVector<int, 16> ShuffleMask;
5074 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5077 int Elt = ShuffleMask[Index];
5079 return DAG.getUNDEF(ShufVT.getVectorElementType());
5081 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5083 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5087 // Actual nodes that may contain scalar elements
5088 if (Opcode == ISD::BITCAST) {
5089 V = V.getOperand(0);
5090 EVT SrcVT = V.getValueType();
5091 unsigned NumElems = VT.getVectorNumElements();
5093 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5097 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5098 return (Index == 0) ? V.getOperand(0)
5099 : DAG.getUNDEF(VT.getVectorElementType());
5101 if (V.getOpcode() == ISD::BUILD_VECTOR)
5102 return V.getOperand(Index);
5107 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5108 /// shuffle operation which come from a consecutively from a zero. The
5109 /// search can start in two different directions, from left or right.
5110 /// We count undefs as zeros until PreferredNum is reached.
5111 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5112 unsigned NumElems, bool ZerosFromLeft,
5114 unsigned PreferredNum = -1U) {
5115 unsigned NumZeros = 0;
5116 for (unsigned i = 0; i != NumElems; ++i) {
5117 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5118 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5122 if (X86::isZeroNode(Elt))
5124 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5125 NumZeros = std::min(NumZeros + 1, PreferredNum);
5133 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5134 /// correspond consecutively to elements from one of the vector operands,
5135 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5137 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5138 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5139 unsigned NumElems, unsigned &OpNum) {
5140 bool SeenV1 = false;
5141 bool SeenV2 = false;
5143 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5144 int Idx = SVOp->getMaskElt(i);
5145 // Ignore undef indicies
5149 if (Idx < (int)NumElems)
5154 // Only accept consecutive elements from the same vector
5155 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5159 OpNum = SeenV1 ? 0 : 1;
5163 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5164 /// logical left shift of a vector.
5165 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5166 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5168 SVOp->getSimpleValueType(0).getVectorNumElements();
5169 unsigned NumZeros = getNumOfConsecutiveZeros(
5170 SVOp, NumElems, false /* check zeros from right */, DAG,
5171 SVOp->getMaskElt(0));
5177 // Considering the elements in the mask that are not consecutive zeros,
5178 // check if they consecutively come from only one of the source vectors.
5180 // V1 = {X, A, B, C} 0
5182 // vector_shuffle V1, V2 <1, 2, 3, X>
5184 if (!isShuffleMaskConsecutive(SVOp,
5185 0, // Mask Start Index
5186 NumElems-NumZeros, // Mask End Index(exclusive)
5187 NumZeros, // Where to start looking in the src vector
5188 NumElems, // Number of elements in vector
5189 OpSrc)) // Which source operand ?
5194 ShVal = SVOp->getOperand(OpSrc);
5198 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5199 /// logical left shift of a vector.
5200 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5201 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5203 SVOp->getSimpleValueType(0).getVectorNumElements();
5204 unsigned NumZeros = getNumOfConsecutiveZeros(
5205 SVOp, NumElems, true /* check zeros from left */, DAG,
5206 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5212 // Considering the elements in the mask that are not consecutive zeros,
5213 // check if they consecutively come from only one of the source vectors.
5215 // 0 { A, B, X, X } = V2
5217 // vector_shuffle V1, V2 <X, X, 4, 5>
5219 if (!isShuffleMaskConsecutive(SVOp,
5220 NumZeros, // Mask Start Index
5221 NumElems, // Mask End Index(exclusive)
5222 0, // Where to start looking in the src vector
5223 NumElems, // Number of elements in vector
5224 OpSrc)) // Which source operand ?
5229 ShVal = SVOp->getOperand(OpSrc);
5233 /// isVectorShift - Returns true if the shuffle can be implemented as a
5234 /// logical left or right shift of a vector.
5235 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5236 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5237 // Although the logic below support any bitwidth size, there are no
5238 // shift instructions which handle more than 128-bit vectors.
5239 if (!SVOp->getSimpleValueType(0).is128BitVector())
5242 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5243 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5249 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5251 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5252 unsigned NumNonZero, unsigned NumZero,
5254 const X86Subtarget* Subtarget,
5255 const TargetLowering &TLI) {
5262 for (unsigned i = 0; i < 16; ++i) {
5263 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5264 if (ThisIsNonZero && First) {
5266 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5268 V = DAG.getUNDEF(MVT::v8i16);
5273 SDValue ThisElt(0, 0), LastElt(0, 0);
5274 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5275 if (LastIsNonZero) {
5276 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5277 MVT::i16, Op.getOperand(i-1));
5279 if (ThisIsNonZero) {
5280 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5281 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5282 ThisElt, DAG.getConstant(8, MVT::i8));
5284 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5288 if (ThisElt.getNode())
5289 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5290 DAG.getIntPtrConstant(i/2));
5294 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5297 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5299 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5300 unsigned NumNonZero, unsigned NumZero,
5302 const X86Subtarget* Subtarget,
5303 const TargetLowering &TLI) {
5310 for (unsigned i = 0; i < 8; ++i) {
5311 bool isNonZero = (NonZeros & (1 << i)) != 0;
5315 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5317 V = DAG.getUNDEF(MVT::v8i16);
5320 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5321 MVT::v8i16, V, Op.getOperand(i),
5322 DAG.getIntPtrConstant(i));
5329 /// getVShift - Return a vector logical shift node.
5331 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5332 unsigned NumBits, SelectionDAG &DAG,
5333 const TargetLowering &TLI, SDLoc dl) {
5334 assert(VT.is128BitVector() && "Unknown type for VShift");
5335 EVT ShVT = MVT::v2i64;
5336 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5337 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5338 return DAG.getNode(ISD::BITCAST, dl, VT,
5339 DAG.getNode(Opc, dl, ShVT, SrcOp,
5340 DAG.getConstant(NumBits,
5341 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5345 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5347 // Check if the scalar load can be widened into a vector load. And if
5348 // the address is "base + cst" see if the cst can be "absorbed" into
5349 // the shuffle mask.
5350 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5351 SDValue Ptr = LD->getBasePtr();
5352 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5354 EVT PVT = LD->getValueType(0);
5355 if (PVT != MVT::i32 && PVT != MVT::f32)
5360 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5361 FI = FINode->getIndex();
5363 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5364 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5365 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5366 Offset = Ptr.getConstantOperandVal(1);
5367 Ptr = Ptr.getOperand(0);
5372 // FIXME: 256-bit vector instructions don't require a strict alignment,
5373 // improve this code to support it better.
5374 unsigned RequiredAlign = VT.getSizeInBits()/8;
5375 SDValue Chain = LD->getChain();
5376 // Make sure the stack object alignment is at least 16 or 32.
5377 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5378 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5379 if (MFI->isFixedObjectIndex(FI)) {
5380 // Can't change the alignment. FIXME: It's possible to compute
5381 // the exact stack offset and reference FI + adjust offset instead.
5382 // If someone *really* cares about this. That's the way to implement it.
5385 MFI->setObjectAlignment(FI, RequiredAlign);
5389 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5390 // Ptr + (Offset & ~15).
5393 if ((Offset % RequiredAlign) & 3)
5395 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5397 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5398 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5400 int EltNo = (Offset - StartOffset) >> 2;
5401 unsigned NumElems = VT.getVectorNumElements();
5403 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5404 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5405 LD->getPointerInfo().getWithOffset(StartOffset),
5406 false, false, false, 0);
5408 SmallVector<int, 8> Mask;
5409 for (unsigned i = 0; i != NumElems; ++i)
5410 Mask.push_back(EltNo);
5412 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5418 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5419 /// vector of type 'VT', see if the elements can be replaced by a single large
5420 /// load which has the same value as a build_vector whose operands are 'elts'.
5422 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5424 /// FIXME: we'd also like to handle the case where the last elements are zero
5425 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5426 /// There's even a handy isZeroNode for that purpose.
5427 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5428 SDLoc &DL, SelectionDAG &DAG) {
5429 EVT EltVT = VT.getVectorElementType();
5430 unsigned NumElems = Elts.size();
5432 LoadSDNode *LDBase = NULL;
5433 unsigned LastLoadedElt = -1U;
5435 // For each element in the initializer, see if we've found a load or an undef.
5436 // If we don't find an initial load element, or later load elements are
5437 // non-consecutive, bail out.
5438 for (unsigned i = 0; i < NumElems; ++i) {
5439 SDValue Elt = Elts[i];
5441 if (!Elt.getNode() ||
5442 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5445 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5447 LDBase = cast<LoadSDNode>(Elt.getNode());
5451 if (Elt.getOpcode() == ISD::UNDEF)
5454 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5455 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5460 // If we have found an entire vector of loads and undefs, then return a large
5461 // load of the entire vector width starting at the base pointer. If we found
5462 // consecutive loads for the low half, generate a vzext_load node.
5463 if (LastLoadedElt == NumElems - 1) {
5464 SDValue NewLd = SDValue();
5465 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5466 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5467 LDBase->getPointerInfo(),
5468 LDBase->isVolatile(), LDBase->isNonTemporal(),
5469 LDBase->isInvariant(), 0);
5470 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5471 LDBase->getPointerInfo(),
5472 LDBase->isVolatile(), LDBase->isNonTemporal(),
5473 LDBase->isInvariant(), LDBase->getAlignment());
5475 if (LDBase->hasAnyUseOfValue(1)) {
5476 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5478 SDValue(NewLd.getNode(), 1));
5479 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5480 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5481 SDValue(NewLd.getNode(), 1));
5486 if (NumElems == 4 && LastLoadedElt == 1 &&
5487 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5488 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5489 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5491 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5492 array_lengthof(Ops), MVT::i64,
5493 LDBase->getPointerInfo(),
5494 LDBase->getAlignment(),
5495 false/*isVolatile*/, true/*ReadMem*/,
5498 // Make sure the newly-created LOAD is in the same position as LDBase in
5499 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5500 // update uses of LDBase's output chain to use the TokenFactor.
5501 if (LDBase->hasAnyUseOfValue(1)) {
5502 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5503 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5504 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5505 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5506 SDValue(ResNode.getNode(), 1));
5509 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5514 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5515 /// to generate a splat value for the following cases:
5516 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5517 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5518 /// a scalar load, or a constant.
5519 /// The VBROADCAST node is returned when a pattern is found,
5520 /// or SDValue() otherwise.
5521 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5522 SelectionDAG &DAG) {
5523 if (!Subtarget->hasFp256())
5526 MVT VT = Op.getSimpleValueType();
5529 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5530 "Unsupported vector type for broadcast.");
5535 switch (Op.getOpcode()) {
5537 // Unknown pattern found.
5540 case ISD::BUILD_VECTOR: {
5541 // The BUILD_VECTOR node must be a splat.
5542 if (!isSplatVector(Op.getNode()))
5545 Ld = Op.getOperand(0);
5546 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5547 Ld.getOpcode() == ISD::ConstantFP);
5549 // The suspected load node has several users. Make sure that all
5550 // of its users are from the BUILD_VECTOR node.
5551 // Constants may have multiple users.
5552 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5557 case ISD::VECTOR_SHUFFLE: {
5558 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5560 // Shuffles must have a splat mask where the first element is
5562 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5565 SDValue Sc = Op.getOperand(0);
5566 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5567 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5569 if (!Subtarget->hasInt256())
5572 // Use the register form of the broadcast instruction available on AVX2.
5573 if (VT.getSizeInBits() >= 256)
5574 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5575 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5578 Ld = Sc.getOperand(0);
5579 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5580 Ld.getOpcode() == ISD::ConstantFP);
5582 // The scalar_to_vector node and the suspected
5583 // load node must have exactly one user.
5584 // Constants may have multiple users.
5586 // AVX-512 has register version of the broadcast
5587 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5588 Ld.getValueType().getSizeInBits() >= 32;
5589 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5596 bool IsGE256 = (VT.getSizeInBits() >= 256);
5598 // Handle the broadcasting a single constant scalar from the constant pool
5599 // into a vector. On Sandybridge it is still better to load a constant vector
5600 // from the constant pool and not to broadcast it from a scalar.
5601 if (ConstSplatVal && Subtarget->hasInt256()) {
5602 EVT CVT = Ld.getValueType();
5603 assert(!CVT.isVector() && "Must not broadcast a vector type");
5604 unsigned ScalarSize = CVT.getSizeInBits();
5606 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5607 const Constant *C = 0;
5608 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5609 C = CI->getConstantIntValue();
5610 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5611 C = CF->getConstantFPValue();
5613 assert(C && "Invalid constant type");
5615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5616 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5617 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5618 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5619 MachinePointerInfo::getConstantPool(),
5620 false, false, false, Alignment);
5622 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5626 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5627 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5629 // Handle AVX2 in-register broadcasts.
5630 if (!IsLoad && Subtarget->hasInt256() &&
5631 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5632 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5634 // The scalar source must be a normal load.
5638 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5639 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5641 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5642 // double since there is no vbroadcastsd xmm
5643 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5644 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5645 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5648 // Unsupported broadcast.
5652 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5653 MVT VT = Op.getSimpleValueType();
5655 // Skip if insert_vec_elt is not supported.
5656 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5657 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5661 unsigned NumElems = Op.getNumOperands();
5665 SmallVector<unsigned, 4> InsertIndices;
5666 SmallVector<int, 8> Mask(NumElems, -1);
5668 for (unsigned i = 0; i != NumElems; ++i) {
5669 unsigned Opc = Op.getOperand(i).getOpcode();
5671 if (Opc == ISD::UNDEF)
5674 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5675 // Quit if more than 1 elements need inserting.
5676 if (InsertIndices.size() > 1)
5679 InsertIndices.push_back(i);
5683 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5684 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5686 // Quit if extracted from vector of different type.
5687 if (ExtractedFromVec.getValueType() != VT)
5690 // Quit if non-constant index.
5691 if (!isa<ConstantSDNode>(ExtIdx))
5694 if (VecIn1.getNode() == 0)
5695 VecIn1 = ExtractedFromVec;
5696 else if (VecIn1 != ExtractedFromVec) {
5697 if (VecIn2.getNode() == 0)
5698 VecIn2 = ExtractedFromVec;
5699 else if (VecIn2 != ExtractedFromVec)
5700 // Quit if more than 2 vectors to shuffle
5704 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5706 if (ExtractedFromVec == VecIn1)
5708 else if (ExtractedFromVec == VecIn2)
5709 Mask[i] = Idx + NumElems;
5712 if (VecIn1.getNode() == 0)
5715 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5716 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5717 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5718 unsigned Idx = InsertIndices[i];
5719 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5720 DAG.getIntPtrConstant(Idx));
5726 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5728 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5730 MVT VT = Op.getSimpleValueType();
5731 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5732 "Unexpected type in LowerBUILD_VECTORvXi1!");
5735 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5736 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5737 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5738 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5739 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5740 Ops, VT.getVectorNumElements());
5743 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5744 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5745 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5746 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5747 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5748 Ops, VT.getVectorNumElements());
5751 bool AllContants = true;
5752 uint64_t Immediate = 0;
5753 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5754 SDValue In = Op.getOperand(idx);
5755 if (In.getOpcode() == ISD::UNDEF)
5757 if (!isa<ConstantSDNode>(In)) {
5758 AllContants = false;
5761 if (cast<ConstantSDNode>(In)->getZExtValue())
5762 Immediate |= (1ULL << idx);
5766 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5767 DAG.getConstant(Immediate, MVT::i16));
5768 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5769 DAG.getIntPtrConstant(0));
5772 // Splat vector (with undefs)
5773 SDValue In = Op.getOperand(0);
5774 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5775 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5776 llvm_unreachable("Unsupported predicate operation");
5779 SDValue EFLAGS, X86CC;
5780 if (In.getOpcode() == ISD::SETCC) {
5781 SDValue Op0 = In.getOperand(0);
5782 SDValue Op1 = In.getOperand(1);
5783 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5784 bool isFP = Op1.getValueType().isFloatingPoint();
5785 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5787 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5789 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5790 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5791 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5792 } else if (In.getOpcode() == X86ISD::SETCC) {
5793 X86CC = In.getOperand(0);
5794 EFLAGS = In.getOperand(1);
5803 // res = allOnes ### CMOVNE -1, %res
5806 MVT InVT = In.getSimpleValueType();
5807 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5808 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5809 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5812 if (VT == MVT::v16i1) {
5813 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5814 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5815 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5816 Cst0, Cst1, X86CC, EFLAGS);
5817 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5820 if (VT == MVT::v8i1) {
5821 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5822 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5823 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5824 Cst0, Cst1, X86CC, EFLAGS);
5825 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5826 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5828 llvm_unreachable("Unsupported predicate operation");
5832 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5835 MVT VT = Op.getSimpleValueType();
5836 MVT ExtVT = VT.getVectorElementType();
5837 unsigned NumElems = Op.getNumOperands();
5839 // Generate vectors for predicate vectors.
5840 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5841 return LowerBUILD_VECTORvXi1(Op, DAG);
5843 // Vectors containing all zeros can be matched by pxor and xorps later
5844 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5845 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5846 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5847 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5850 return getZeroVector(VT, Subtarget, DAG, dl);
5853 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5854 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5855 // vpcmpeqd on 256-bit vectors.
5856 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5857 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5860 if (!VT.is512BitVector())
5861 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5864 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5865 if (Broadcast.getNode())
5868 unsigned EVTBits = ExtVT.getSizeInBits();
5870 unsigned NumZero = 0;
5871 unsigned NumNonZero = 0;
5872 unsigned NonZeros = 0;
5873 bool IsAllConstants = true;
5874 SmallSet<SDValue, 8> Values;
5875 for (unsigned i = 0; i < NumElems; ++i) {
5876 SDValue Elt = Op.getOperand(i);
5877 if (Elt.getOpcode() == ISD::UNDEF)
5880 if (Elt.getOpcode() != ISD::Constant &&
5881 Elt.getOpcode() != ISD::ConstantFP)
5882 IsAllConstants = false;
5883 if (X86::isZeroNode(Elt))
5886 NonZeros |= (1 << i);
5891 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5892 if (NumNonZero == 0)
5893 return DAG.getUNDEF(VT);
5895 // Special case for single non-zero, non-undef, element.
5896 if (NumNonZero == 1) {
5897 unsigned Idx = countTrailingZeros(NonZeros);
5898 SDValue Item = Op.getOperand(Idx);
5900 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5901 // the value are obviously zero, truncate the value to i32 and do the
5902 // insertion that way. Only do this if the value is non-constant or if the
5903 // value is a constant being inserted into element 0. It is cheaper to do
5904 // a constant pool load than it is to do a movd + shuffle.
5905 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5906 (!IsAllConstants || Idx == 0)) {
5907 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5909 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5910 EVT VecVT = MVT::v4i32;
5911 unsigned VecElts = 4;
5913 // Truncate the value (which may itself be a constant) to i32, and
5914 // convert it to a vector with movd (S2V+shuffle to zero extend).
5915 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5916 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5917 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5919 // Now we have our 32-bit value zero extended in the low element of
5920 // a vector. If Idx != 0, swizzle it into place.
5922 SmallVector<int, 4> Mask;
5923 Mask.push_back(Idx);
5924 for (unsigned i = 1; i != VecElts; ++i)
5926 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5929 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5933 // If we have a constant or non-constant insertion into the low element of
5934 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5935 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5936 // depending on what the source datatype is.
5939 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5941 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5942 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5943 if (VT.is256BitVector() || VT.is512BitVector()) {
5944 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5945 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5946 Item, DAG.getIntPtrConstant(0));
5948 assert(VT.is128BitVector() && "Expected an SSE value type!");
5949 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5950 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5951 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5954 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5955 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5956 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5957 if (VT.is256BitVector()) {
5958 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5959 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5961 assert(VT.is128BitVector() && "Expected an SSE value type!");
5962 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5964 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5968 // Is it a vector logical left shift?
5969 if (NumElems == 2 && Idx == 1 &&
5970 X86::isZeroNode(Op.getOperand(0)) &&
5971 !X86::isZeroNode(Op.getOperand(1))) {
5972 unsigned NumBits = VT.getSizeInBits();
5973 return getVShift(true, VT,
5974 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5975 VT, Op.getOperand(1)),
5976 NumBits/2, DAG, *this, dl);
5979 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5982 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5983 // is a non-constant being inserted into an element other than the low one,
5984 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5985 // movd/movss) to move this into the low element, then shuffle it into
5987 if (EVTBits == 32) {
5988 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5990 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5991 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5992 SmallVector<int, 8> MaskVec;
5993 for (unsigned i = 0; i != NumElems; ++i)
5994 MaskVec.push_back(i == Idx ? 0 : 1);
5995 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5999 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6000 if (Values.size() == 1) {
6001 if (EVTBits == 32) {
6002 // Instead of a shuffle like this:
6003 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6004 // Check if it's possible to issue this instead.
6005 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6006 unsigned Idx = countTrailingZeros(NonZeros);
6007 SDValue Item = Op.getOperand(Idx);
6008 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6009 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6014 // A vector full of immediates; various special cases are already
6015 // handled, so this is best done with a single constant-pool load.
6019 // For AVX-length vectors, build the individual 128-bit pieces and use
6020 // shuffles to put them in place.
6021 if (VT.is256BitVector()) {
6022 SmallVector<SDValue, 32> V;
6023 for (unsigned i = 0; i != NumElems; ++i)
6024 V.push_back(Op.getOperand(i));
6026 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6028 // Build both the lower and upper subvector.
6029 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6030 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6033 // Recreate the wider vector with the lower and upper part.
6034 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6037 // Let legalizer expand 2-wide build_vectors.
6038 if (EVTBits == 64) {
6039 if (NumNonZero == 1) {
6040 // One half is zero or undef.
6041 unsigned Idx = countTrailingZeros(NonZeros);
6042 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6043 Op.getOperand(Idx));
6044 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6049 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6050 if (EVTBits == 8 && NumElems == 16) {
6051 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6053 if (V.getNode()) return V;
6056 if (EVTBits == 16 && NumElems == 8) {
6057 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6059 if (V.getNode()) return V;
6062 // If element VT is == 32 bits, turn it into a number of shuffles.
6063 SmallVector<SDValue, 8> V(NumElems);
6064 if (NumElems == 4 && NumZero > 0) {
6065 for (unsigned i = 0; i < 4; ++i) {
6066 bool isZero = !(NonZeros & (1 << i));
6068 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6070 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6073 for (unsigned i = 0; i < 2; ++i) {
6074 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6077 V[i] = V[i*2]; // Must be a zero vector.
6080 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6083 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6086 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6091 bool Reverse1 = (NonZeros & 0x3) == 2;
6092 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6096 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6097 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6099 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6102 if (Values.size() > 1 && VT.is128BitVector()) {
6103 // Check for a build vector of consecutive loads.
6104 for (unsigned i = 0; i < NumElems; ++i)
6105 V[i] = Op.getOperand(i);
6107 // Check for elements which are consecutive loads.
6108 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6112 // Check for a build vector from mostly shuffle plus few inserting.
6113 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6117 // For SSE 4.1, use insertps to put the high elements into the low element.
6118 if (getSubtarget()->hasSSE41()) {
6120 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6121 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6123 Result = DAG.getUNDEF(VT);
6125 for (unsigned i = 1; i < NumElems; ++i) {
6126 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6127 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6128 Op.getOperand(i), DAG.getIntPtrConstant(i));
6133 // Otherwise, expand into a number of unpckl*, start by extending each of
6134 // our (non-undef) elements to the full vector width with the element in the
6135 // bottom slot of the vector (which generates no code for SSE).
6136 for (unsigned i = 0; i < NumElems; ++i) {
6137 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6138 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6140 V[i] = DAG.getUNDEF(VT);
6143 // Next, we iteratively mix elements, e.g. for v4f32:
6144 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6145 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6146 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6147 unsigned EltStride = NumElems >> 1;
6148 while (EltStride != 0) {
6149 for (unsigned i = 0; i < EltStride; ++i) {
6150 // If V[i+EltStride] is undef and this is the first round of mixing,
6151 // then it is safe to just drop this shuffle: V[i] is already in the
6152 // right place, the one element (since it's the first round) being
6153 // inserted as undef can be dropped. This isn't safe for successive
6154 // rounds because they will permute elements within both vectors.
6155 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6156 EltStride == NumElems/2)
6159 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6168 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6169 // to create 256-bit vectors from two other 128-bit ones.
6170 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6172 MVT ResVT = Op.getSimpleValueType();
6174 assert((ResVT.is256BitVector() ||
6175 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6177 SDValue V1 = Op.getOperand(0);
6178 SDValue V2 = Op.getOperand(1);
6179 unsigned NumElems = ResVT.getVectorNumElements();
6180 if(ResVT.is256BitVector())
6181 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6183 if (Op.getNumOperands() == 4) {
6184 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6185 ResVT.getVectorNumElements()/2);
6186 SDValue V3 = Op.getOperand(2);
6187 SDValue V4 = Op.getOperand(3);
6188 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6189 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6191 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6194 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6195 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6196 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6197 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6198 Op.getNumOperands() == 4)));
6200 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6201 // from two other 128-bit ones.
6203 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6204 return LowerAVXCONCAT_VECTORS(Op, DAG);
6207 // Try to lower a shuffle node into a simple blend instruction.
6209 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6210 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6211 SDValue V1 = SVOp->getOperand(0);
6212 SDValue V2 = SVOp->getOperand(1);
6214 MVT VT = SVOp->getSimpleValueType(0);
6215 MVT EltVT = VT.getVectorElementType();
6216 unsigned NumElems = VT.getVectorNumElements();
6218 // There is no blend with immediate in AVX-512.
6219 if (VT.is512BitVector())
6222 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6224 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6227 // Check the mask for BLEND and build the value.
6228 unsigned MaskValue = 0;
6229 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6230 unsigned NumLanes = (NumElems-1)/8 + 1;
6231 unsigned NumElemsInLane = NumElems / NumLanes;
6233 // Blend for v16i16 should be symetric for the both lanes.
6234 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6236 int SndLaneEltIdx = (NumLanes == 2) ?
6237 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6238 int EltIdx = SVOp->getMaskElt(i);
6240 if ((EltIdx < 0 || EltIdx == (int)i) &&
6241 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6244 if (((unsigned)EltIdx == (i + NumElems)) &&
6245 (SndLaneEltIdx < 0 ||
6246 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6247 MaskValue |= (1<<i);
6252 // Convert i32 vectors to floating point if it is not AVX2.
6253 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6255 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6256 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6258 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6259 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6262 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6263 DAG.getConstant(MaskValue, MVT::i32));
6264 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6267 // v8i16 shuffles - Prefer shuffles in the following order:
6268 // 1. [all] pshuflw, pshufhw, optional move
6269 // 2. [ssse3] 1 x pshufb
6270 // 3. [ssse3] 2 x pshufb + 1 x por
6271 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6273 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6274 SelectionDAG &DAG) {
6275 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6276 SDValue V1 = SVOp->getOperand(0);
6277 SDValue V2 = SVOp->getOperand(1);
6279 SmallVector<int, 8> MaskVals;
6281 // Determine if more than 1 of the words in each of the low and high quadwords
6282 // of the result come from the same quadword of one of the two inputs. Undef
6283 // mask values count as coming from any quadword, for better codegen.
6284 unsigned LoQuad[] = { 0, 0, 0, 0 };
6285 unsigned HiQuad[] = { 0, 0, 0, 0 };
6286 std::bitset<4> InputQuads;
6287 for (unsigned i = 0; i < 8; ++i) {
6288 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6289 int EltIdx = SVOp->getMaskElt(i);
6290 MaskVals.push_back(EltIdx);
6299 InputQuads.set(EltIdx / 4);
6302 int BestLoQuad = -1;
6303 unsigned MaxQuad = 1;
6304 for (unsigned i = 0; i < 4; ++i) {
6305 if (LoQuad[i] > MaxQuad) {
6307 MaxQuad = LoQuad[i];
6311 int BestHiQuad = -1;
6313 for (unsigned i = 0; i < 4; ++i) {
6314 if (HiQuad[i] > MaxQuad) {
6316 MaxQuad = HiQuad[i];
6320 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6321 // of the two input vectors, shuffle them into one input vector so only a
6322 // single pshufb instruction is necessary. If There are more than 2 input
6323 // quads, disable the next transformation since it does not help SSSE3.
6324 bool V1Used = InputQuads[0] || InputQuads[1];
6325 bool V2Used = InputQuads[2] || InputQuads[3];
6326 if (Subtarget->hasSSSE3()) {
6327 if (InputQuads.count() == 2 && V1Used && V2Used) {
6328 BestLoQuad = InputQuads[0] ? 0 : 1;
6329 BestHiQuad = InputQuads[2] ? 2 : 3;
6331 if (InputQuads.count() > 2) {
6337 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6338 // the shuffle mask. If a quad is scored as -1, that means that it contains
6339 // words from all 4 input quadwords.
6341 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6343 BestLoQuad < 0 ? 0 : BestLoQuad,
6344 BestHiQuad < 0 ? 1 : BestHiQuad
6346 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6347 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6348 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6349 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6351 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6352 // source words for the shuffle, to aid later transformations.
6353 bool AllWordsInNewV = true;
6354 bool InOrder[2] = { true, true };
6355 for (unsigned i = 0; i != 8; ++i) {
6356 int idx = MaskVals[i];
6358 InOrder[i/4] = false;
6359 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6361 AllWordsInNewV = false;
6365 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6366 if (AllWordsInNewV) {
6367 for (int i = 0; i != 8; ++i) {
6368 int idx = MaskVals[i];
6371 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6372 if ((idx != i) && idx < 4)
6374 if ((idx != i) && idx > 3)
6383 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6384 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6385 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6386 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6387 unsigned TargetMask = 0;
6388 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6389 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6391 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6392 getShufflePSHUFLWImmediate(SVOp);
6393 V1 = NewV.getOperand(0);
6394 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6398 // Promote splats to a larger type which usually leads to more efficient code.
6399 // FIXME: Is this true if pshufb is available?
6400 if (SVOp->isSplat())
6401 return PromoteSplat(SVOp, DAG);
6403 // If we have SSSE3, and all words of the result are from 1 input vector,
6404 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6405 // is present, fall back to case 4.
6406 if (Subtarget->hasSSSE3()) {
6407 SmallVector<SDValue,16> pshufbMask;
6409 // If we have elements from both input vectors, set the high bit of the
6410 // shuffle mask element to zero out elements that come from V2 in the V1
6411 // mask, and elements that come from V1 in the V2 mask, so that the two
6412 // results can be OR'd together.
6413 bool TwoInputs = V1Used && V2Used;
6414 for (unsigned i = 0; i != 8; ++i) {
6415 int EltIdx = MaskVals[i] * 2;
6416 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6417 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6418 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6419 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6421 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6422 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6423 DAG.getNode(ISD::BUILD_VECTOR, dl,
6424 MVT::v16i8, &pshufbMask[0], 16));
6426 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6428 // Calculate the shuffle mask for the second input, shuffle it, and
6429 // OR it with the first shuffled input.
6431 for (unsigned i = 0; i != 8; ++i) {
6432 int EltIdx = MaskVals[i] * 2;
6433 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6434 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6435 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6436 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6438 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6439 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6440 DAG.getNode(ISD::BUILD_VECTOR, dl,
6441 MVT::v16i8, &pshufbMask[0], 16));
6442 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6443 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6446 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6447 // and update MaskVals with new element order.
6448 std::bitset<8> InOrder;
6449 if (BestLoQuad >= 0) {
6450 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6451 for (int i = 0; i != 4; ++i) {
6452 int idx = MaskVals[i];
6455 } else if ((idx / 4) == BestLoQuad) {
6460 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6463 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6464 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6465 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6467 getShufflePSHUFLWImmediate(SVOp), DAG);
6471 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6472 // and update MaskVals with the new element order.
6473 if (BestHiQuad >= 0) {
6474 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6475 for (unsigned i = 4; i != 8; ++i) {
6476 int idx = MaskVals[i];
6479 } else if ((idx / 4) == BestHiQuad) {
6480 MaskV[i] = (idx & 3) + 4;
6484 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6487 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6488 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6489 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6491 getShufflePSHUFHWImmediate(SVOp), DAG);
6495 // In case BestHi & BestLo were both -1, which means each quadword has a word
6496 // from each of the four input quadwords, calculate the InOrder bitvector now
6497 // before falling through to the insert/extract cleanup.
6498 if (BestLoQuad == -1 && BestHiQuad == -1) {
6500 for (int i = 0; i != 8; ++i)
6501 if (MaskVals[i] < 0 || MaskVals[i] == i)
6505 // The other elements are put in the right place using pextrw and pinsrw.
6506 for (unsigned i = 0; i != 8; ++i) {
6509 int EltIdx = MaskVals[i];
6512 SDValue ExtOp = (EltIdx < 8) ?
6513 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6514 DAG.getIntPtrConstant(EltIdx)) :
6515 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6516 DAG.getIntPtrConstant(EltIdx - 8));
6517 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6518 DAG.getIntPtrConstant(i));
6523 // v16i8 shuffles - Prefer shuffles in the following order:
6524 // 1. [ssse3] 1 x pshufb
6525 // 2. [ssse3] 2 x pshufb + 1 x por
6526 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6527 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6528 const X86Subtarget* Subtarget,
6529 SelectionDAG &DAG) {
6530 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6531 SDValue V1 = SVOp->getOperand(0);
6532 SDValue V2 = SVOp->getOperand(1);
6534 ArrayRef<int> MaskVals = SVOp->getMask();
6536 // Promote splats to a larger type which usually leads to more efficient code.
6537 // FIXME: Is this true if pshufb is available?
6538 if (SVOp->isSplat())
6539 return PromoteSplat(SVOp, DAG);
6541 // If we have SSSE3, case 1 is generated when all result bytes come from
6542 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6543 // present, fall back to case 3.
6545 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6546 if (Subtarget->hasSSSE3()) {
6547 SmallVector<SDValue,16> pshufbMask;
6549 // If all result elements are from one input vector, then only translate
6550 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6552 // Otherwise, we have elements from both input vectors, and must zero out
6553 // elements that come from V2 in the first mask, and V1 in the second mask
6554 // so that we can OR them together.
6555 for (unsigned i = 0; i != 16; ++i) {
6556 int EltIdx = MaskVals[i];
6557 if (EltIdx < 0 || EltIdx >= 16)
6559 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6561 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6562 DAG.getNode(ISD::BUILD_VECTOR, dl,
6563 MVT::v16i8, &pshufbMask[0], 16));
6565 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6566 // the 2nd operand if it's undefined or zero.
6567 if (V2.getOpcode() == ISD::UNDEF ||
6568 ISD::isBuildVectorAllZeros(V2.getNode()))
6571 // Calculate the shuffle mask for the second input, shuffle it, and
6572 // OR it with the first shuffled input.
6574 for (unsigned i = 0; i != 16; ++i) {
6575 int EltIdx = MaskVals[i];
6576 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6577 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6579 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6580 DAG.getNode(ISD::BUILD_VECTOR, dl,
6581 MVT::v16i8, &pshufbMask[0], 16));
6582 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6585 // No SSSE3 - Calculate in place words and then fix all out of place words
6586 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6587 // the 16 different words that comprise the two doublequadword input vectors.
6588 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6589 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6591 for (int i = 0; i != 8; ++i) {
6592 int Elt0 = MaskVals[i*2];
6593 int Elt1 = MaskVals[i*2+1];
6595 // This word of the result is all undef, skip it.
6596 if (Elt0 < 0 && Elt1 < 0)
6599 // This word of the result is already in the correct place, skip it.
6600 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6603 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6604 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6607 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6608 // using a single extract together, load it and store it.
6609 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6610 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6611 DAG.getIntPtrConstant(Elt1 / 2));
6612 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6613 DAG.getIntPtrConstant(i));
6617 // If Elt1 is defined, extract it from the appropriate source. If the
6618 // source byte is not also odd, shift the extracted word left 8 bits
6619 // otherwise clear the bottom 8 bits if we need to do an or.
6621 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6622 DAG.getIntPtrConstant(Elt1 / 2));
6623 if ((Elt1 & 1) == 0)
6624 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6626 TLI.getShiftAmountTy(InsElt.getValueType())));
6628 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6629 DAG.getConstant(0xFF00, MVT::i16));
6631 // If Elt0 is defined, extract it from the appropriate source. If the
6632 // source byte is not also even, shift the extracted word right 8 bits. If
6633 // Elt1 was also defined, OR the extracted values together before
6634 // inserting them in the result.
6636 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6637 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6638 if ((Elt0 & 1) != 0)
6639 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6641 TLI.getShiftAmountTy(InsElt0.getValueType())));
6643 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6644 DAG.getConstant(0x00FF, MVT::i16));
6645 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6648 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6649 DAG.getIntPtrConstant(i));
6651 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6654 // v32i8 shuffles - Translate to VPSHUFB if possible.
6656 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6657 const X86Subtarget *Subtarget,
6658 SelectionDAG &DAG) {
6659 MVT VT = SVOp->getSimpleValueType(0);
6660 SDValue V1 = SVOp->getOperand(0);
6661 SDValue V2 = SVOp->getOperand(1);
6663 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6665 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6666 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6667 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6669 // VPSHUFB may be generated if
6670 // (1) one of input vector is undefined or zeroinitializer.
6671 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6672 // And (2) the mask indexes don't cross the 128-bit lane.
6673 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6674 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6677 if (V1IsAllZero && !V2IsAllZero) {
6678 CommuteVectorShuffleMask(MaskVals, 32);
6681 SmallVector<SDValue, 32> pshufbMask;
6682 for (unsigned i = 0; i != 32; i++) {
6683 int EltIdx = MaskVals[i];
6684 if (EltIdx < 0 || EltIdx >= 32)
6687 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6688 // Cross lane is not allowed.
6692 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6694 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6695 DAG.getNode(ISD::BUILD_VECTOR, dl,
6696 MVT::v32i8, &pshufbMask[0], 32));
6699 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6700 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6701 /// done when every pair / quad of shuffle mask elements point to elements in
6702 /// the right sequence. e.g.
6703 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6705 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6706 SelectionDAG &DAG) {
6707 MVT VT = SVOp->getSimpleValueType(0);
6709 unsigned NumElems = VT.getVectorNumElements();
6712 switch (VT.SimpleTy) {
6713 default: llvm_unreachable("Unexpected!");
6714 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6715 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6716 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6717 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6718 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6719 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6722 SmallVector<int, 8> MaskVec;
6723 for (unsigned i = 0; i != NumElems; i += Scale) {
6725 for (unsigned j = 0; j != Scale; ++j) {
6726 int EltIdx = SVOp->getMaskElt(i+j);
6730 StartIdx = (EltIdx / Scale);
6731 if (EltIdx != (int)(StartIdx*Scale + j))
6734 MaskVec.push_back(StartIdx);
6737 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6738 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6739 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6742 /// getVZextMovL - Return a zero-extending vector move low node.
6744 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6745 SDValue SrcOp, SelectionDAG &DAG,
6746 const X86Subtarget *Subtarget, SDLoc dl) {
6747 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6748 LoadSDNode *LD = NULL;
6749 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6750 LD = dyn_cast<LoadSDNode>(SrcOp);
6752 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6754 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6755 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6756 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6757 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6758 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6760 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6761 return DAG.getNode(ISD::BITCAST, dl, VT,
6762 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6763 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6771 return DAG.getNode(ISD::BITCAST, dl, VT,
6772 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6773 DAG.getNode(ISD::BITCAST, dl,
6777 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6778 /// which could not be matched by any known target speficic shuffle
6780 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6782 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6783 if (NewOp.getNode())
6786 MVT VT = SVOp->getSimpleValueType(0);
6788 unsigned NumElems = VT.getVectorNumElements();
6789 unsigned NumLaneElems = NumElems / 2;
6792 MVT EltVT = VT.getVectorElementType();
6793 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6796 SmallVector<int, 16> Mask;
6797 for (unsigned l = 0; l < 2; ++l) {
6798 // Build a shuffle mask for the output, discovering on the fly which
6799 // input vectors to use as shuffle operands (recorded in InputUsed).
6800 // If building a suitable shuffle vector proves too hard, then bail
6801 // out with UseBuildVector set.
6802 bool UseBuildVector = false;
6803 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6804 unsigned LaneStart = l * NumLaneElems;
6805 for (unsigned i = 0; i != NumLaneElems; ++i) {
6806 // The mask element. This indexes into the input.
6807 int Idx = SVOp->getMaskElt(i+LaneStart);
6809 // the mask element does not index into any input vector.
6814 // The input vector this mask element indexes into.
6815 int Input = Idx / NumLaneElems;
6817 // Turn the index into an offset from the start of the input vector.
6818 Idx -= Input * NumLaneElems;
6820 // Find or create a shuffle vector operand to hold this input.
6822 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6823 if (InputUsed[OpNo] == Input)
6824 // This input vector is already an operand.
6826 if (InputUsed[OpNo] < 0) {
6827 // Create a new operand for this input vector.
6828 InputUsed[OpNo] = Input;
6833 if (OpNo >= array_lengthof(InputUsed)) {
6834 // More than two input vectors used! Give up on trying to create a
6835 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6836 UseBuildVector = true;
6840 // Add the mask index for the new shuffle vector.
6841 Mask.push_back(Idx + OpNo * NumLaneElems);
6844 if (UseBuildVector) {
6845 SmallVector<SDValue, 16> SVOps;
6846 for (unsigned i = 0; i != NumLaneElems; ++i) {
6847 // The mask element. This indexes into the input.
6848 int Idx = SVOp->getMaskElt(i+LaneStart);
6850 SVOps.push_back(DAG.getUNDEF(EltVT));
6854 // The input vector this mask element indexes into.
6855 int Input = Idx / NumElems;
6857 // Turn the index into an offset from the start of the input vector.
6858 Idx -= Input * NumElems;
6860 // Extract the vector element by hand.
6861 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6862 SVOp->getOperand(Input),
6863 DAG.getIntPtrConstant(Idx)));
6866 // Construct the output using a BUILD_VECTOR.
6867 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6869 } else if (InputUsed[0] < 0) {
6870 // No input vectors were used! The result is undefined.
6871 Output[l] = DAG.getUNDEF(NVT);
6873 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6874 (InputUsed[0] % 2) * NumLaneElems,
6876 // If only one input was used, use an undefined vector for the other.
6877 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6878 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6879 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6880 // At least one input vector was used. Create a new shuffle vector.
6881 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6887 // Concatenate the result back
6888 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6891 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6892 /// 4 elements, and match them with several different shuffle types.
6894 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6895 SDValue V1 = SVOp->getOperand(0);
6896 SDValue V2 = SVOp->getOperand(1);
6898 MVT VT = SVOp->getSimpleValueType(0);
6900 assert(VT.is128BitVector() && "Unsupported vector size");
6902 std::pair<int, int> Locs[4];
6903 int Mask1[] = { -1, -1, -1, -1 };
6904 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6908 for (unsigned i = 0; i != 4; ++i) {
6909 int Idx = PermMask[i];
6911 Locs[i] = std::make_pair(-1, -1);
6913 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6915 Locs[i] = std::make_pair(0, NumLo);
6919 Locs[i] = std::make_pair(1, NumHi);
6921 Mask1[2+NumHi] = Idx;
6927 if (NumLo <= 2 && NumHi <= 2) {
6928 // If no more than two elements come from either vector. This can be
6929 // implemented with two shuffles. First shuffle gather the elements.
6930 // The second shuffle, which takes the first shuffle as both of its
6931 // vector operands, put the elements into the right order.
6932 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6934 int Mask2[] = { -1, -1, -1, -1 };
6936 for (unsigned i = 0; i != 4; ++i)
6937 if (Locs[i].first != -1) {
6938 unsigned Idx = (i < 2) ? 0 : 4;
6939 Idx += Locs[i].first * 2 + Locs[i].second;
6943 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6946 if (NumLo == 3 || NumHi == 3) {
6947 // Otherwise, we must have three elements from one vector, call it X, and
6948 // one element from the other, call it Y. First, use a shufps to build an
6949 // intermediate vector with the one element from Y and the element from X
6950 // that will be in the same half in the final destination (the indexes don't
6951 // matter). Then, use a shufps to build the final vector, taking the half
6952 // containing the element from Y from the intermediate, and the other half
6955 // Normalize it so the 3 elements come from V1.
6956 CommuteVectorShuffleMask(PermMask, 4);
6960 // Find the element from V2.
6962 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6963 int Val = PermMask[HiIndex];
6970 Mask1[0] = PermMask[HiIndex];
6972 Mask1[2] = PermMask[HiIndex^1];
6974 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6977 Mask1[0] = PermMask[0];
6978 Mask1[1] = PermMask[1];
6979 Mask1[2] = HiIndex & 1 ? 6 : 4;
6980 Mask1[3] = HiIndex & 1 ? 4 : 6;
6981 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6984 Mask1[0] = HiIndex & 1 ? 2 : 0;
6985 Mask1[1] = HiIndex & 1 ? 0 : 2;
6986 Mask1[2] = PermMask[2];
6987 Mask1[3] = PermMask[3];
6992 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6995 // Break it into (shuffle shuffle_hi, shuffle_lo).
6996 int LoMask[] = { -1, -1, -1, -1 };
6997 int HiMask[] = { -1, -1, -1, -1 };
6999 int *MaskPtr = LoMask;
7000 unsigned MaskIdx = 0;
7003 for (unsigned i = 0; i != 4; ++i) {
7010 int Idx = PermMask[i];
7012 Locs[i] = std::make_pair(-1, -1);
7013 } else if (Idx < 4) {
7014 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7015 MaskPtr[LoIdx] = Idx;
7018 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7019 MaskPtr[HiIdx] = Idx;
7024 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7025 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7026 int MaskOps[] = { -1, -1, -1, -1 };
7027 for (unsigned i = 0; i != 4; ++i)
7028 if (Locs[i].first != -1)
7029 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7030 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7033 static bool MayFoldVectorLoad(SDValue V) {
7034 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7035 V = V.getOperand(0);
7037 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7038 V = V.getOperand(0);
7039 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7040 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7041 // BUILD_VECTOR (load), undef
7042 V = V.getOperand(0);
7044 return MayFoldLoad(V);
7048 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7049 MVT VT = Op.getSimpleValueType();
7051 // Canonizalize to v2f64.
7052 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7053 return DAG.getNode(ISD::BITCAST, dl, VT,
7054 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7059 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7061 SDValue V1 = Op.getOperand(0);
7062 SDValue V2 = Op.getOperand(1);
7063 MVT VT = Op.getSimpleValueType();
7065 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7067 if (HasSSE2 && VT == MVT::v2f64)
7068 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7070 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7071 return DAG.getNode(ISD::BITCAST, dl, VT,
7072 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7073 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7074 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7078 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7079 SDValue V1 = Op.getOperand(0);
7080 SDValue V2 = Op.getOperand(1);
7081 MVT VT = Op.getSimpleValueType();
7083 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7084 "unsupported shuffle type");
7086 if (V2.getOpcode() == ISD::UNDEF)
7090 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7094 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7095 SDValue V1 = Op.getOperand(0);
7096 SDValue V2 = Op.getOperand(1);
7097 MVT VT = Op.getSimpleValueType();
7098 unsigned NumElems = VT.getVectorNumElements();
7100 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7101 // operand of these instructions is only memory, so check if there's a
7102 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7104 bool CanFoldLoad = false;
7106 // Trivial case, when V2 comes from a load.
7107 if (MayFoldVectorLoad(V2))
7110 // When V1 is a load, it can be folded later into a store in isel, example:
7111 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7113 // (MOVLPSmr addr:$src1, VR128:$src2)
7114 // So, recognize this potential and also use MOVLPS or MOVLPD
7115 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7118 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7120 if (HasSSE2 && NumElems == 2)
7121 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7124 // If we don't care about the second element, proceed to use movss.
7125 if (SVOp->getMaskElt(1) != -1)
7126 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7129 // movl and movlp will both match v2i64, but v2i64 is never matched by
7130 // movl earlier because we make it strict to avoid messing with the movlp load
7131 // folding logic (see the code above getMOVLP call). Match it here then,
7132 // this is horrible, but will stay like this until we move all shuffle
7133 // matching to x86 specific nodes. Note that for the 1st condition all
7134 // types are matched with movsd.
7136 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7137 // as to remove this logic from here, as much as possible
7138 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7139 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7140 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7143 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7145 // Invert the operand order and use SHUFPS to match it.
7146 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7147 getShuffleSHUFImmediate(SVOp), DAG);
7150 // Reduce a vector shuffle to zext.
7151 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7152 SelectionDAG &DAG) {
7153 // PMOVZX is only available from SSE41.
7154 if (!Subtarget->hasSSE41())
7157 MVT VT = Op.getSimpleValueType();
7159 // Only AVX2 support 256-bit vector integer extending.
7160 if (!Subtarget->hasInt256() && VT.is256BitVector())
7163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7165 SDValue V1 = Op.getOperand(0);
7166 SDValue V2 = Op.getOperand(1);
7167 unsigned NumElems = VT.getVectorNumElements();
7169 // Extending is an unary operation and the element type of the source vector
7170 // won't be equal to or larger than i64.
7171 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7172 VT.getVectorElementType() == MVT::i64)
7175 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7176 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7177 while ((1U << Shift) < NumElems) {
7178 if (SVOp->getMaskElt(1U << Shift) == 1)
7181 // The maximal ratio is 8, i.e. from i8 to i64.
7186 // Check the shuffle mask.
7187 unsigned Mask = (1U << Shift) - 1;
7188 for (unsigned i = 0; i != NumElems; ++i) {
7189 int EltIdx = SVOp->getMaskElt(i);
7190 if ((i & Mask) != 0 && EltIdx != -1)
7192 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7196 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7197 MVT NeVT = MVT::getIntegerVT(NBits);
7198 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7200 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7203 // Simplify the operand as it's prepared to be fed into shuffle.
7204 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7205 if (V1.getOpcode() == ISD::BITCAST &&
7206 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7207 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7208 V1.getOperand(0).getOperand(0)
7209 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7210 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7211 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7212 ConstantSDNode *CIdx =
7213 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7214 // If it's foldable, i.e. normal load with single use, we will let code
7215 // selection to fold it. Otherwise, we will short the conversion sequence.
7216 if (CIdx && CIdx->getZExtValue() == 0 &&
7217 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7218 MVT FullVT = V.getSimpleValueType();
7219 MVT V1VT = V1.getSimpleValueType();
7220 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7221 // The "ext_vec_elt" node is wider than the result node.
7222 // In this case we should extract subvector from V.
7223 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7224 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7225 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7226 FullVT.getVectorNumElements()/Ratio);
7227 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7228 DAG.getIntPtrConstant(0));
7230 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7234 return DAG.getNode(ISD::BITCAST, DL, VT,
7235 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7239 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7240 SelectionDAG &DAG) {
7241 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7242 MVT VT = Op.getSimpleValueType();
7244 SDValue V1 = Op.getOperand(0);
7245 SDValue V2 = Op.getOperand(1);
7247 if (isZeroShuffle(SVOp))
7248 return getZeroVector(VT, Subtarget, DAG, dl);
7250 // Handle splat operations
7251 if (SVOp->isSplat()) {
7252 // Use vbroadcast whenever the splat comes from a foldable load
7253 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7254 if (Broadcast.getNode())
7258 // Check integer expanding shuffles.
7259 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7260 if (NewOp.getNode())
7263 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7265 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7266 VT == MVT::v16i16 || VT == MVT::v32i8) {
7267 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7268 if (NewOp.getNode())
7269 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7270 } else if ((VT == MVT::v4i32 ||
7271 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7272 // FIXME: Figure out a cleaner way to do this.
7273 // Try to make use of movq to zero out the top part.
7274 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7275 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7276 if (NewOp.getNode()) {
7277 MVT NewVT = NewOp.getSimpleValueType();
7278 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7279 NewVT, true, false))
7280 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7281 DAG, Subtarget, dl);
7283 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7284 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7285 if (NewOp.getNode()) {
7286 MVT NewVT = NewOp.getSimpleValueType();
7287 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7288 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7289 DAG, Subtarget, dl);
7297 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7299 SDValue V1 = Op.getOperand(0);
7300 SDValue V2 = Op.getOperand(1);
7301 MVT VT = Op.getSimpleValueType();
7303 unsigned NumElems = VT.getVectorNumElements();
7304 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7305 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7306 bool V1IsSplat = false;
7307 bool V2IsSplat = false;
7308 bool HasSSE2 = Subtarget->hasSSE2();
7309 bool HasFp256 = Subtarget->hasFp256();
7310 bool HasInt256 = Subtarget->hasInt256();
7311 MachineFunction &MF = DAG.getMachineFunction();
7312 bool OptForSize = MF.getFunction()->getAttributes().
7313 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7315 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7317 if (V1IsUndef && V2IsUndef)
7318 return DAG.getUNDEF(VT);
7320 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7322 // Vector shuffle lowering takes 3 steps:
7324 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7325 // narrowing and commutation of operands should be handled.
7326 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7328 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7329 // so the shuffle can be broken into other shuffles and the legalizer can
7330 // try the lowering again.
7332 // The general idea is that no vector_shuffle operation should be left to
7333 // be matched during isel, all of them must be converted to a target specific
7336 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7337 // narrowing and commutation of operands should be handled. The actual code
7338 // doesn't include all of those, work in progress...
7339 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7340 if (NewOp.getNode())
7343 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7345 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7346 // unpckh_undef). Only use pshufd if speed is more important than size.
7347 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7348 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7349 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7350 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7352 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7353 V2IsUndef && MayFoldVectorLoad(V1))
7354 return getMOVDDup(Op, dl, V1, DAG);
7356 if (isMOVHLPS_v_undef_Mask(M, VT))
7357 return getMOVHighToLow(Op, dl, DAG);
7359 // Use to match splats
7360 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7361 (VT == MVT::v2f64 || VT == MVT::v2i64))
7362 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7364 if (isPSHUFDMask(M, VT)) {
7365 // The actual implementation will match the mask in the if above and then
7366 // during isel it can match several different instructions, not only pshufd
7367 // as its name says, sad but true, emulate the behavior for now...
7368 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7369 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7371 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7373 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7374 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7376 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7377 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7380 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7384 if (isPALIGNRMask(M, VT, Subtarget))
7385 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7386 getShufflePALIGNRImmediate(SVOp),
7389 // Check if this can be converted into a logical shift.
7390 bool isLeft = false;
7393 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7394 if (isShift && ShVal.hasOneUse()) {
7395 // If the shifted value has multiple uses, it may be cheaper to use
7396 // v_set0 + movlhps or movhlps, etc.
7397 MVT EltVT = VT.getVectorElementType();
7398 ShAmt *= EltVT.getSizeInBits();
7399 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7402 if (isMOVLMask(M, VT)) {
7403 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7404 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7405 if (!isMOVLPMask(M, VT)) {
7406 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7407 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7409 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7410 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7414 // FIXME: fold these into legal mask.
7415 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7416 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7418 if (isMOVHLPSMask(M, VT))
7419 return getMOVHighToLow(Op, dl, DAG);
7421 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7422 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7424 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7425 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7427 if (isMOVLPMask(M, VT))
7428 return getMOVLP(Op, dl, DAG, HasSSE2);
7430 if (ShouldXformToMOVHLPS(M, VT) ||
7431 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7432 return CommuteVectorShuffle(SVOp, DAG);
7435 // No better options. Use a vshldq / vsrldq.
7436 MVT EltVT = VT.getVectorElementType();
7437 ShAmt *= EltVT.getSizeInBits();
7438 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7441 bool Commuted = false;
7442 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7443 // 1,1,1,1 -> v8i16 though.
7444 V1IsSplat = isSplatVector(V1.getNode());
7445 V2IsSplat = isSplatVector(V2.getNode());
7447 // Canonicalize the splat or undef, if present, to be on the RHS.
7448 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7449 CommuteVectorShuffleMask(M, NumElems);
7451 std::swap(V1IsSplat, V2IsSplat);
7455 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7456 // Shuffling low element of v1 into undef, just return v1.
7459 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7460 // the instruction selector will not match, so get a canonical MOVL with
7461 // swapped operands to undo the commute.
7462 return getMOVL(DAG, dl, VT, V2, V1);
7465 if (isUNPCKLMask(M, VT, HasInt256))
7466 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7468 if (isUNPCKHMask(M, VT, HasInt256))
7469 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7472 // Normalize mask so all entries that point to V2 points to its first
7473 // element then try to match unpck{h|l} again. If match, return a
7474 // new vector_shuffle with the corrected mask.p
7475 SmallVector<int, 8> NewMask(M.begin(), M.end());
7476 NormalizeMask(NewMask, NumElems);
7477 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7478 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7479 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7480 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7484 // Commute is back and try unpck* again.
7485 // FIXME: this seems wrong.
7486 CommuteVectorShuffleMask(M, NumElems);
7488 std::swap(V1IsSplat, V2IsSplat);
7491 if (isUNPCKLMask(M, VT, HasInt256))
7492 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7494 if (isUNPCKHMask(M, VT, HasInt256))
7495 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7498 // Normalize the node to match x86 shuffle ops if needed
7499 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7500 return CommuteVectorShuffle(SVOp, DAG);
7502 // The checks below are all present in isShuffleMaskLegal, but they are
7503 // inlined here right now to enable us to directly emit target specific
7504 // nodes, and remove one by one until they don't return Op anymore.
7506 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7507 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7508 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7509 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7512 if (isPSHUFHWMask(M, VT, HasInt256))
7513 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7514 getShufflePSHUFHWImmediate(SVOp),
7517 if (isPSHUFLWMask(M, VT, HasInt256))
7518 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7519 getShufflePSHUFLWImmediate(SVOp),
7522 if (isSHUFPMask(M, VT))
7523 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7524 getShuffleSHUFImmediate(SVOp), DAG);
7526 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7527 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7528 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7529 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7531 //===--------------------------------------------------------------------===//
7532 // Generate target specific nodes for 128 or 256-bit shuffles only
7533 // supported in the AVX instruction set.
7536 // Handle VMOVDDUPY permutations
7537 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7538 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7540 // Handle VPERMILPS/D* permutations
7541 if (isVPERMILPMask(M, VT)) {
7542 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7543 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7544 getShuffleSHUFImmediate(SVOp), DAG);
7545 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7546 getShuffleSHUFImmediate(SVOp), DAG);
7549 // Handle VPERM2F128/VPERM2I128 permutations
7550 if (isVPERM2X128Mask(M, VT, HasFp256))
7551 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7552 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7554 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7555 if (BlendOp.getNode())
7559 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7560 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7562 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7563 VT.is512BitVector()) {
7564 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7565 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7566 SmallVector<SDValue, 16> permclMask;
7567 for (unsigned i = 0; i != NumElems; ++i) {
7568 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7571 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7572 &permclMask[0], NumElems);
7574 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7575 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7576 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7577 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7578 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7581 //===--------------------------------------------------------------------===//
7582 // Since no target specific shuffle was selected for this generic one,
7583 // lower it into other known shuffles. FIXME: this isn't true yet, but
7584 // this is the plan.
7587 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7588 if (VT == MVT::v8i16) {
7589 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7590 if (NewOp.getNode())
7594 if (VT == MVT::v16i8) {
7595 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7596 if (NewOp.getNode())
7600 if (VT == MVT::v32i8) {
7601 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7602 if (NewOp.getNode())
7606 // Handle all 128-bit wide vectors with 4 elements, and match them with
7607 // several different shuffle types.
7608 if (NumElems == 4 && VT.is128BitVector())
7609 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7611 // Handle general 256-bit shuffles
7612 if (VT.is256BitVector())
7613 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7618 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7619 MVT VT = Op.getSimpleValueType();
7622 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7625 if (VT.getSizeInBits() == 8) {
7626 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7627 Op.getOperand(0), Op.getOperand(1));
7628 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7629 DAG.getValueType(VT));
7630 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7633 if (VT.getSizeInBits() == 16) {
7634 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7635 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7637 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7638 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7639 DAG.getNode(ISD::BITCAST, dl,
7643 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7644 Op.getOperand(0), Op.getOperand(1));
7645 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7646 DAG.getValueType(VT));
7647 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7650 if (VT == MVT::f32) {
7651 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7652 // the result back to FR32 register. It's only worth matching if the
7653 // result has a single use which is a store or a bitcast to i32. And in
7654 // the case of a store, it's not worth it if the index is a constant 0,
7655 // because a MOVSSmr can be used instead, which is smaller and faster.
7656 if (!Op.hasOneUse())
7658 SDNode *User = *Op.getNode()->use_begin();
7659 if ((User->getOpcode() != ISD::STORE ||
7660 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7661 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7662 (User->getOpcode() != ISD::BITCAST ||
7663 User->getValueType(0) != MVT::i32))
7665 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7666 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7669 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7672 if (VT == MVT::i32 || VT == MVT::i64) {
7673 // ExtractPS/pextrq works with constant index.
7674 if (isa<ConstantSDNode>(Op.getOperand(1)))
7680 /// Extract one bit from mask vector, like v16i1 or v8i1.
7681 /// AVX-512 feature.
7682 static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
7683 SDValue Vec = Op.getOperand(0);
7685 MVT VecVT = Vec.getSimpleValueType();
7686 SDValue Idx = Op.getOperand(1);
7687 MVT EltVT = Op.getSimpleValueType();
7689 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7691 // variable index can't be handled in mask registers,
7692 // extend vector to VR512
7693 if (!isa<ConstantSDNode>(Idx)) {
7694 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7695 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7696 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7697 ExtVT.getVectorElementType(), Ext, Idx);
7698 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7701 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7703 unsigned MaxSift = VecVT.getSizeInBits() - 1;
7704 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7705 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7706 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7707 DAG.getConstant(MaxSift, MVT::i8));
7709 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i1, Vec,
7710 DAG.getIntPtrConstant(0));
7714 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7715 SelectionDAG &DAG) const {
7717 SDValue Vec = Op.getOperand(0);
7718 MVT VecVT = Vec.getSimpleValueType();
7719 SDValue Idx = Op.getOperand(1);
7721 if (Op.getSimpleValueType() == MVT::i1)
7722 return ExtractBitFromMaskVector(Op, DAG);
7724 if (!isa<ConstantSDNode>(Idx)) {
7725 if (VecVT.is512BitVector() ||
7726 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7727 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7730 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7731 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7732 MaskEltVT.getSizeInBits());
7734 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7735 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7736 getZeroVector(MaskVT, Subtarget, DAG, dl),
7737 Idx, DAG.getConstant(0, getPointerTy()));
7738 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7739 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7740 Perm, DAG.getConstant(0, getPointerTy()));
7745 // If this is a 256-bit vector result, first extract the 128-bit vector and
7746 // then extract the element from the 128-bit vector.
7747 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7749 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7750 // Get the 128-bit vector.
7751 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7752 MVT EltVT = VecVT.getVectorElementType();
7754 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7756 //if (IdxVal >= NumElems/2)
7757 // IdxVal -= NumElems/2;
7758 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7759 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7760 DAG.getConstant(IdxVal, MVT::i32));
7763 assert(VecVT.is128BitVector() && "Unexpected vector length");
7765 if (Subtarget->hasSSE41()) {
7766 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7771 MVT VT = Op.getSimpleValueType();
7772 // TODO: handle v16i8.
7773 if (VT.getSizeInBits() == 16) {
7774 SDValue Vec = Op.getOperand(0);
7775 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7777 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7778 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7779 DAG.getNode(ISD::BITCAST, dl,
7782 // Transform it so it match pextrw which produces a 32-bit result.
7783 MVT EltVT = MVT::i32;
7784 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7785 Op.getOperand(0), Op.getOperand(1));
7786 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7787 DAG.getValueType(VT));
7788 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7791 if (VT.getSizeInBits() == 32) {
7792 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7796 // SHUFPS the element to the lowest double word, then movss.
7797 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7798 MVT VVT = Op.getOperand(0).getSimpleValueType();
7799 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7800 DAG.getUNDEF(VVT), Mask);
7801 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7802 DAG.getIntPtrConstant(0));
7805 if (VT.getSizeInBits() == 64) {
7806 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7807 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7808 // to match extract_elt for f64.
7809 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7813 // UNPCKHPD the element to the lowest double word, then movsd.
7814 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7815 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7816 int Mask[2] = { 1, -1 };
7817 MVT VVT = Op.getOperand(0).getSimpleValueType();
7818 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7819 DAG.getUNDEF(VVT), Mask);
7820 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7821 DAG.getIntPtrConstant(0));
7827 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7828 MVT VT = Op.getSimpleValueType();
7829 MVT EltVT = VT.getVectorElementType();
7832 SDValue N0 = Op.getOperand(0);
7833 SDValue N1 = Op.getOperand(1);
7834 SDValue N2 = Op.getOperand(2);
7836 if (!VT.is128BitVector())
7839 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7840 isa<ConstantSDNode>(N2)) {
7842 if (VT == MVT::v8i16)
7843 Opc = X86ISD::PINSRW;
7844 else if (VT == MVT::v16i8)
7845 Opc = X86ISD::PINSRB;
7847 Opc = X86ISD::PINSRB;
7849 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7851 if (N1.getValueType() != MVT::i32)
7852 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7853 if (N2.getValueType() != MVT::i32)
7854 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7855 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7858 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7859 // Bits [7:6] of the constant are the source select. This will always be
7860 // zero here. The DAG Combiner may combine an extract_elt index into these
7861 // bits. For example (insert (extract, 3), 2) could be matched by putting
7862 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7863 // Bits [5:4] of the constant are the destination select. This is the
7864 // value of the incoming immediate.
7865 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7866 // combine either bitwise AND or insert of float 0.0 to set these bits.
7867 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7868 // Create this as a scalar to vector..
7869 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7870 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7873 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7874 // PINSR* works with constant index.
7881 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7882 MVT VT = Op.getSimpleValueType();
7883 MVT EltVT = VT.getVectorElementType();
7886 SDValue N0 = Op.getOperand(0);
7887 SDValue N1 = Op.getOperand(1);
7888 SDValue N2 = Op.getOperand(2);
7890 // If this is a 256-bit vector result, first extract the 128-bit vector,
7891 // insert the element into the extracted half and then place it back.
7892 if (VT.is256BitVector() || VT.is512BitVector()) {
7893 if (!isa<ConstantSDNode>(N2))
7896 // Get the desired 128-bit vector half.
7897 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7898 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7900 // Insert the element into the desired half.
7901 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7902 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7904 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7905 DAG.getConstant(IdxIn128, MVT::i32));
7907 // Insert the changed part back to the 256-bit vector
7908 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7911 if (Subtarget->hasSSE41())
7912 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7914 if (EltVT == MVT::i8)
7917 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7918 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7919 // as its second argument.
7920 if (N1.getValueType() != MVT::i32)
7921 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7922 if (N2.getValueType() != MVT::i32)
7923 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7924 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7929 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7931 MVT OpVT = Op.getSimpleValueType();
7933 // If this is a 256-bit vector result, first insert into a 128-bit
7934 // vector and then insert into the 256-bit vector.
7935 if (!OpVT.is128BitVector()) {
7936 // Insert into a 128-bit vector.
7937 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7938 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7939 OpVT.getVectorNumElements() / SizeFactor);
7941 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7943 // Insert the 128-bit vector.
7944 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7947 if (OpVT == MVT::v1i64 &&
7948 Op.getOperand(0).getValueType() == MVT::i64)
7949 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7951 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7952 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7953 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7954 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7957 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7958 // a simple subregister reference or explicit instructions to grab
7959 // upper bits of a vector.
7960 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7961 SelectionDAG &DAG) {
7963 SDValue In = Op.getOperand(0);
7964 SDValue Idx = Op.getOperand(1);
7965 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7966 MVT ResVT = Op.getSimpleValueType();
7967 MVT InVT = In.getSimpleValueType();
7969 if (Subtarget->hasFp256()) {
7970 if (ResVT.is128BitVector() &&
7971 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7972 isa<ConstantSDNode>(Idx)) {
7973 return Extract128BitVector(In, IdxVal, DAG, dl);
7975 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7976 isa<ConstantSDNode>(Idx)) {
7977 return Extract256BitVector(In, IdxVal, DAG, dl);
7983 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7984 // simple superregister reference or explicit instructions to insert
7985 // the upper bits of a vector.
7986 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7987 SelectionDAG &DAG) {
7988 if (Subtarget->hasFp256()) {
7989 SDLoc dl(Op.getNode());
7990 SDValue Vec = Op.getNode()->getOperand(0);
7991 SDValue SubVec = Op.getNode()->getOperand(1);
7992 SDValue Idx = Op.getNode()->getOperand(2);
7994 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7995 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7996 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7997 isa<ConstantSDNode>(Idx)) {
7998 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7999 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8002 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8003 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8004 isa<ConstantSDNode>(Idx)) {
8005 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8006 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8012 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8013 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8014 // one of the above mentioned nodes. It has to be wrapped because otherwise
8015 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8016 // be used to form addressing mode. These wrapped nodes will be selected
8019 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8020 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8022 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8024 unsigned char OpFlag = 0;
8025 unsigned WrapperKind = X86ISD::Wrapper;
8026 CodeModel::Model M = getTargetMachine().getCodeModel();
8028 if (Subtarget->isPICStyleRIPRel() &&
8029 (M == CodeModel::Small || M == CodeModel::Kernel))
8030 WrapperKind = X86ISD::WrapperRIP;
8031 else if (Subtarget->isPICStyleGOT())
8032 OpFlag = X86II::MO_GOTOFF;
8033 else if (Subtarget->isPICStyleStubPIC())
8034 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8036 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8038 CP->getOffset(), OpFlag);
8040 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8041 // With PIC, the address is actually $g + Offset.
8043 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8044 DAG.getNode(X86ISD::GlobalBaseReg,
8045 SDLoc(), getPointerTy()),
8052 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8053 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8055 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8057 unsigned char OpFlag = 0;
8058 unsigned WrapperKind = X86ISD::Wrapper;
8059 CodeModel::Model M = getTargetMachine().getCodeModel();
8061 if (Subtarget->isPICStyleRIPRel() &&
8062 (M == CodeModel::Small || M == CodeModel::Kernel))
8063 WrapperKind = X86ISD::WrapperRIP;
8064 else if (Subtarget->isPICStyleGOT())
8065 OpFlag = X86II::MO_GOTOFF;
8066 else if (Subtarget->isPICStyleStubPIC())
8067 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8069 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8072 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8074 // With PIC, the address is actually $g + Offset.
8076 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8077 DAG.getNode(X86ISD::GlobalBaseReg,
8078 SDLoc(), getPointerTy()),
8085 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8086 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8088 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8090 unsigned char OpFlag = 0;
8091 unsigned WrapperKind = X86ISD::Wrapper;
8092 CodeModel::Model M = getTargetMachine().getCodeModel();
8094 if (Subtarget->isPICStyleRIPRel() &&
8095 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8096 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8097 OpFlag = X86II::MO_GOTPCREL;
8098 WrapperKind = X86ISD::WrapperRIP;
8099 } else if (Subtarget->isPICStyleGOT()) {
8100 OpFlag = X86II::MO_GOT;
8101 } else if (Subtarget->isPICStyleStubPIC()) {
8102 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8103 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8104 OpFlag = X86II::MO_DARWIN_NONLAZY;
8107 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8110 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8112 // With PIC, the address is actually $g + Offset.
8113 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8114 !Subtarget->is64Bit()) {
8115 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8116 DAG.getNode(X86ISD::GlobalBaseReg,
8117 SDLoc(), getPointerTy()),
8121 // For symbols that require a load from a stub to get the address, emit the
8123 if (isGlobalStubReference(OpFlag))
8124 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8125 MachinePointerInfo::getGOT(), false, false, false, 0);
8131 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8132 // Create the TargetBlockAddressAddress node.
8133 unsigned char OpFlags =
8134 Subtarget->ClassifyBlockAddressReference();
8135 CodeModel::Model M = getTargetMachine().getCodeModel();
8136 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8137 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8139 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8142 if (Subtarget->isPICStyleRIPRel() &&
8143 (M == CodeModel::Small || M == CodeModel::Kernel))
8144 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8146 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8148 // With PIC, the address is actually $g + Offset.
8149 if (isGlobalRelativeToPICBase(OpFlags)) {
8150 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8151 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8159 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8160 int64_t Offset, SelectionDAG &DAG) const {
8161 // Create the TargetGlobalAddress node, folding in the constant
8162 // offset if it is legal.
8163 unsigned char OpFlags =
8164 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8165 CodeModel::Model M = getTargetMachine().getCodeModel();
8167 if (OpFlags == X86II::MO_NO_FLAG &&
8168 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8169 // A direct static reference to a global.
8170 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8173 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8176 if (Subtarget->isPICStyleRIPRel() &&
8177 (M == CodeModel::Small || M == CodeModel::Kernel))
8178 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8180 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8182 // With PIC, the address is actually $g + Offset.
8183 if (isGlobalRelativeToPICBase(OpFlags)) {
8184 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8185 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8189 // For globals that require a load from a stub to get the address, emit the
8191 if (isGlobalStubReference(OpFlags))
8192 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8193 MachinePointerInfo::getGOT(), false, false, false, 0);
8195 // If there was a non-zero offset that we didn't fold, create an explicit
8198 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8199 DAG.getConstant(Offset, getPointerTy()));
8205 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8206 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8207 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8208 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8212 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8213 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8214 unsigned char OperandFlags, bool LocalDynamic = false) {
8215 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8216 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8218 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8219 GA->getValueType(0),
8223 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8227 SDValue Ops[] = { Chain, TGA, *InFlag };
8228 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8230 SDValue Ops[] = { Chain, TGA };
8231 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8234 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8235 MFI->setAdjustsStack(true);
8237 SDValue Flag = Chain.getValue(1);
8238 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8241 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8243 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8246 SDLoc dl(GA); // ? function entry point might be better
8247 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8248 DAG.getNode(X86ISD::GlobalBaseReg,
8249 SDLoc(), PtrVT), InFlag);
8250 InFlag = Chain.getValue(1);
8252 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8255 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8257 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8259 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8260 X86::RAX, X86II::MO_TLSGD);
8263 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8269 // Get the start address of the TLS block for this module.
8270 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8271 .getInfo<X86MachineFunctionInfo>();
8272 MFI->incNumLocalDynamicTLSAccesses();
8276 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8277 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8280 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8281 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8282 InFlag = Chain.getValue(1);
8283 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8284 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8287 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8291 unsigned char OperandFlags = X86II::MO_DTPOFF;
8292 unsigned WrapperKind = X86ISD::Wrapper;
8293 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8294 GA->getValueType(0),
8295 GA->getOffset(), OperandFlags);
8296 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8298 // Add x@dtpoff with the base.
8299 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8302 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8303 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8304 const EVT PtrVT, TLSModel::Model model,
8305 bool is64Bit, bool isPIC) {
8308 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8309 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8310 is64Bit ? 257 : 256));
8312 SDValue ThreadPointer =
8313 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8314 MachinePointerInfo(Ptr), false, false, false, 0);
8316 unsigned char OperandFlags = 0;
8317 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8319 unsigned WrapperKind = X86ISD::Wrapper;
8320 if (model == TLSModel::LocalExec) {
8321 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8322 } else if (model == TLSModel::InitialExec) {
8324 OperandFlags = X86II::MO_GOTTPOFF;
8325 WrapperKind = X86ISD::WrapperRIP;
8327 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8330 llvm_unreachable("Unexpected model");
8333 // emit "addl x@ntpoff,%eax" (local exec)
8334 // or "addl x@indntpoff,%eax" (initial exec)
8335 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8337 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8338 GA->getOffset(), OperandFlags);
8339 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8341 if (model == TLSModel::InitialExec) {
8342 if (isPIC && !is64Bit) {
8343 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8344 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8348 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8349 MachinePointerInfo::getGOT(), false, false, false, 0);
8352 // The address of the thread local variable is the add of the thread
8353 // pointer with the offset of the variable.
8354 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8358 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8360 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8361 const GlobalValue *GV = GA->getGlobal();
8363 if (Subtarget->isTargetELF()) {
8364 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8367 case TLSModel::GeneralDynamic:
8368 if (Subtarget->is64Bit())
8369 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8370 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8371 case TLSModel::LocalDynamic:
8372 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8373 Subtarget->is64Bit());
8374 case TLSModel::InitialExec:
8375 case TLSModel::LocalExec:
8376 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8377 Subtarget->is64Bit(),
8378 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8380 llvm_unreachable("Unknown TLS model.");
8383 if (Subtarget->isTargetDarwin()) {
8384 // Darwin only has one model of TLS. Lower to that.
8385 unsigned char OpFlag = 0;
8386 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8387 X86ISD::WrapperRIP : X86ISD::Wrapper;
8389 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8391 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8392 !Subtarget->is64Bit();
8394 OpFlag = X86II::MO_TLVP_PIC_BASE;
8396 OpFlag = X86II::MO_TLVP;
8398 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8399 GA->getValueType(0),
8400 GA->getOffset(), OpFlag);
8401 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8403 // With PIC32, the address is actually $g + Offset.
8405 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8406 DAG.getNode(X86ISD::GlobalBaseReg,
8407 SDLoc(), getPointerTy()),
8410 // Lowering the machine isd will make sure everything is in the right
8412 SDValue Chain = DAG.getEntryNode();
8413 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8414 SDValue Args[] = { Chain, Offset };
8415 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8417 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8418 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8419 MFI->setAdjustsStack(true);
8421 // And our return value (tls address) is in the standard call return value
8423 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8424 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8428 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8429 // Just use the implicit TLS architecture
8430 // Need to generate someting similar to:
8431 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8433 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8434 // mov rcx, qword [rdx+rcx*8]
8435 // mov eax, .tls$:tlsvar
8436 // [rax+rcx] contains the address
8437 // Windows 64bit: gs:0x58
8438 // Windows 32bit: fs:__tls_array
8440 // If GV is an alias then use the aliasee for determining
8441 // thread-localness.
8442 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8443 GV = GA->resolveAliasedGlobal(false);
8445 SDValue Chain = DAG.getEntryNode();
8447 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8448 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8449 // use its literal value of 0x2C.
8450 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8451 ? Type::getInt8PtrTy(*DAG.getContext(),
8453 : Type::getInt32PtrTy(*DAG.getContext(),
8456 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8457 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8458 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8460 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8461 MachinePointerInfo(Ptr),
8462 false, false, false, 0);
8464 // Load the _tls_index variable
8465 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8466 if (Subtarget->is64Bit())
8467 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8468 IDX, MachinePointerInfo(), MVT::i32,
8471 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8472 false, false, false, 0);
8474 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8476 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8478 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8479 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8480 false, false, false, 0);
8482 // Get the offset of start of .tls section
8483 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8484 GA->getValueType(0),
8485 GA->getOffset(), X86II::MO_SECREL);
8486 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8488 // The address of the thread local variable is the add of the thread
8489 // pointer with the offset of the variable.
8490 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8493 llvm_unreachable("TLS not implemented for this target.");
8496 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8497 /// and take a 2 x i32 value to shift plus a shift amount.
8498 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8499 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8500 EVT VT = Op.getValueType();
8501 unsigned VTBits = VT.getSizeInBits();
8503 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8504 SDValue ShOpLo = Op.getOperand(0);
8505 SDValue ShOpHi = Op.getOperand(1);
8506 SDValue ShAmt = Op.getOperand(2);
8507 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8508 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8510 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8511 DAG.getConstant(VTBits - 1, MVT::i8));
8512 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8513 DAG.getConstant(VTBits - 1, MVT::i8))
8514 : DAG.getConstant(0, VT);
8517 if (Op.getOpcode() == ISD::SHL_PARTS) {
8518 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8519 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8521 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8522 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8525 // If the shift amount is larger or equal than the width of a part we can't
8526 // rely on the results of shld/shrd. Insert a test and select the appropriate
8527 // values for large shift amounts.
8528 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8529 DAG.getConstant(VTBits, MVT::i8));
8530 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8531 AndNode, DAG.getConstant(0, MVT::i8));
8534 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8535 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8536 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8538 if (Op.getOpcode() == ISD::SHL_PARTS) {
8539 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8540 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8542 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8543 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8546 SDValue Ops[2] = { Lo, Hi };
8547 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8550 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8551 SelectionDAG &DAG) const {
8552 EVT SrcVT = Op.getOperand(0).getValueType();
8554 if (SrcVT.isVector())
8557 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8558 "Unknown SINT_TO_FP to lower!");
8560 // These are really Legal; return the operand so the caller accepts it as
8562 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8564 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8565 Subtarget->is64Bit()) {
8570 unsigned Size = SrcVT.getSizeInBits()/8;
8571 MachineFunction &MF = DAG.getMachineFunction();
8572 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8573 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8574 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8576 MachinePointerInfo::getFixedStack(SSFI),
8578 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8581 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8583 SelectionDAG &DAG) const {
8587 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8589 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8591 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8593 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8595 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8596 MachineMemOperand *MMO;
8598 int SSFI = FI->getIndex();
8600 DAG.getMachineFunction()
8601 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8602 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8604 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8605 StackSlot = StackSlot.getOperand(1);
8607 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8608 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8610 Tys, Ops, array_lengthof(Ops),
8614 Chain = Result.getValue(1);
8615 SDValue InFlag = Result.getValue(2);
8617 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8618 // shouldn't be necessary except that RFP cannot be live across
8619 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8620 MachineFunction &MF = DAG.getMachineFunction();
8621 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8622 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8623 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8624 Tys = DAG.getVTList(MVT::Other);
8626 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8628 MachineMemOperand *MMO =
8629 DAG.getMachineFunction()
8630 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8631 MachineMemOperand::MOStore, SSFISize, SSFISize);
8633 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8634 Ops, array_lengthof(Ops),
8635 Op.getValueType(), MMO);
8636 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8637 MachinePointerInfo::getFixedStack(SSFI),
8638 false, false, false, 0);
8644 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8645 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8646 SelectionDAG &DAG) const {
8647 // This algorithm is not obvious. Here it is what we're trying to output:
8650 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8651 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8655 pshufd $0x4e, %xmm0, %xmm1
8661 LLVMContext *Context = DAG.getContext();
8663 // Build some magic constants.
8664 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8665 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8666 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8668 SmallVector<Constant*,2> CV1;
8670 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8671 APInt(64, 0x4330000000000000ULL))));
8673 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8674 APInt(64, 0x4530000000000000ULL))));
8675 Constant *C1 = ConstantVector::get(CV1);
8676 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8678 // Load the 64-bit value into an XMM register.
8679 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8681 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8682 MachinePointerInfo::getConstantPool(),
8683 false, false, false, 16);
8684 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8685 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8688 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8689 MachinePointerInfo::getConstantPool(),
8690 false, false, false, 16);
8691 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8692 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8695 if (Subtarget->hasSSE3()) {
8696 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8697 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8699 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8700 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8702 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8703 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8707 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8708 DAG.getIntPtrConstant(0));
8711 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8712 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8713 SelectionDAG &DAG) const {
8715 // FP constant to bias correct the final result.
8716 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8719 // Load the 32-bit value into an XMM register.
8720 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8723 // Zero out the upper parts of the register.
8724 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8726 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8727 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8728 DAG.getIntPtrConstant(0));
8730 // Or the load with the bias.
8731 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8732 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8733 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8735 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8736 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8737 MVT::v2f64, Bias)));
8738 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8739 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8740 DAG.getIntPtrConstant(0));
8742 // Subtract the bias.
8743 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8745 // Handle final rounding.
8746 EVT DestVT = Op.getValueType();
8748 if (DestVT.bitsLT(MVT::f64))
8749 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8750 DAG.getIntPtrConstant(0));
8751 if (DestVT.bitsGT(MVT::f64))
8752 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8754 // Handle final rounding.
8758 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8759 SelectionDAG &DAG) const {
8760 SDValue N0 = Op.getOperand(0);
8761 EVT SVT = N0.getValueType();
8764 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8765 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8766 "Custom UINT_TO_FP is not supported!");
8768 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8769 SVT.getVectorNumElements());
8770 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8771 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8774 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8775 SelectionDAG &DAG) const {
8776 SDValue N0 = Op.getOperand(0);
8779 if (Op.getValueType().isVector())
8780 return lowerUINT_TO_FP_vec(Op, DAG);
8782 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8783 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8784 // the optimization here.
8785 if (DAG.SignBitIsZero(N0))
8786 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8788 EVT SrcVT = N0.getValueType();
8789 EVT DstVT = Op.getValueType();
8790 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8791 return LowerUINT_TO_FP_i64(Op, DAG);
8792 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8793 return LowerUINT_TO_FP_i32(Op, DAG);
8794 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8797 // Make a 64-bit buffer, and use it to build an FILD.
8798 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8799 if (SrcVT == MVT::i32) {
8800 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8801 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8802 getPointerTy(), StackSlot, WordOff);
8803 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8804 StackSlot, MachinePointerInfo(),
8806 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8807 OffsetSlot, MachinePointerInfo(),
8809 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8813 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8814 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8815 StackSlot, MachinePointerInfo(),
8817 // For i64 source, we need to add the appropriate power of 2 if the input
8818 // was negative. This is the same as the optimization in
8819 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8820 // we must be careful to do the computation in x87 extended precision, not
8821 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8822 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8823 MachineMemOperand *MMO =
8824 DAG.getMachineFunction()
8825 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8826 MachineMemOperand::MOLoad, 8, 8);
8828 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8829 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8830 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8831 array_lengthof(Ops), MVT::i64, MMO);
8833 APInt FF(32, 0x5F800000ULL);
8835 // Check whether the sign bit is set.
8836 SDValue SignSet = DAG.getSetCC(dl,
8837 getSetCCResultType(*DAG.getContext(), MVT::i64),
8838 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8841 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8842 SDValue FudgePtr = DAG.getConstantPool(
8843 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8846 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8847 SDValue Zero = DAG.getIntPtrConstant(0);
8848 SDValue Four = DAG.getIntPtrConstant(4);
8849 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8851 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8853 // Load the value out, extending it from f32 to f80.
8854 // FIXME: Avoid the extend by constructing the right constant pool?
8855 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8856 FudgePtr, MachinePointerInfo::getConstantPool(),
8857 MVT::f32, false, false, 4);
8858 // Extend everything to 80 bits to force it to be done on x87.
8859 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8860 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8863 std::pair<SDValue,SDValue>
8864 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8865 bool IsSigned, bool IsReplace) const {
8868 EVT DstTy = Op.getValueType();
8870 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8871 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8875 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8876 DstTy.getSimpleVT() >= MVT::i16 &&
8877 "Unknown FP_TO_INT to lower!");
8879 // These are really Legal.
8880 if (DstTy == MVT::i32 &&
8881 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8882 return std::make_pair(SDValue(), SDValue());
8883 if (Subtarget->is64Bit() &&
8884 DstTy == MVT::i64 &&
8885 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8886 return std::make_pair(SDValue(), SDValue());
8888 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8889 // stack slot, or into the FTOL runtime function.
8890 MachineFunction &MF = DAG.getMachineFunction();
8891 unsigned MemSize = DstTy.getSizeInBits()/8;
8892 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8893 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8896 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8897 Opc = X86ISD::WIN_FTOL;
8899 switch (DstTy.getSimpleVT().SimpleTy) {
8900 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8901 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8902 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8903 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8906 SDValue Chain = DAG.getEntryNode();
8907 SDValue Value = Op.getOperand(0);
8908 EVT TheVT = Op.getOperand(0).getValueType();
8909 // FIXME This causes a redundant load/store if the SSE-class value is already
8910 // in memory, such as if it is on the callstack.
8911 if (isScalarFPTypeInSSEReg(TheVT)) {
8912 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8913 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8914 MachinePointerInfo::getFixedStack(SSFI),
8916 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8918 Chain, StackSlot, DAG.getValueType(TheVT)
8921 MachineMemOperand *MMO =
8922 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8923 MachineMemOperand::MOLoad, MemSize, MemSize);
8924 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8925 array_lengthof(Ops), DstTy, MMO);
8926 Chain = Value.getValue(1);
8927 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8928 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8931 MachineMemOperand *MMO =
8932 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8933 MachineMemOperand::MOStore, MemSize, MemSize);
8935 if (Opc != X86ISD::WIN_FTOL) {
8936 // Build the FP_TO_INT*_IN_MEM
8937 SDValue Ops[] = { Chain, Value, StackSlot };
8938 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8939 Ops, array_lengthof(Ops), DstTy,
8941 return std::make_pair(FIST, StackSlot);
8943 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8944 DAG.getVTList(MVT::Other, MVT::Glue),
8946 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8947 MVT::i32, ftol.getValue(1));
8948 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8949 MVT::i32, eax.getValue(2));
8950 SDValue Ops[] = { eax, edx };
8951 SDValue pair = IsReplace
8952 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8953 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8954 return std::make_pair(pair, SDValue());
8958 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8959 const X86Subtarget *Subtarget) {
8960 MVT VT = Op->getSimpleValueType(0);
8961 SDValue In = Op->getOperand(0);
8962 MVT InVT = In.getSimpleValueType();
8965 // Optimize vectors in AVX mode:
8968 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8969 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8970 // Concat upper and lower parts.
8973 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8974 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8975 // Concat upper and lower parts.
8978 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8979 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8980 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8983 if (Subtarget->hasInt256())
8984 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8986 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8987 SDValue Undef = DAG.getUNDEF(InVT);
8988 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8989 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8990 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8992 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8993 VT.getVectorNumElements()/2);
8995 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8996 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8998 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9001 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9002 SelectionDAG &DAG) {
9003 MVT VT = Op->getValueType(0).getSimpleVT();
9004 SDValue In = Op->getOperand(0);
9005 MVT InVT = In.getValueType().getSimpleVT();
9007 unsigned int NumElts = VT.getVectorNumElements();
9008 if (NumElts != 8 && NumElts != 16)
9011 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9012 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9014 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9015 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9016 // Now we have only mask extension
9017 assert(InVT.getVectorElementType() == MVT::i1);
9018 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9019 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9020 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9021 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9022 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9023 MachinePointerInfo::getConstantPool(),
9024 false, false, false, Alignment);
9026 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9027 if (VT.is512BitVector())
9029 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9032 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9033 SelectionDAG &DAG) {
9034 if (Subtarget->hasFp256()) {
9035 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9043 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9044 SelectionDAG &DAG) {
9046 MVT VT = Op.getSimpleValueType();
9047 SDValue In = Op.getOperand(0);
9048 MVT SVT = In.getSimpleValueType();
9050 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9051 return LowerZERO_EXTEND_AVX512(Op, DAG);
9053 if (Subtarget->hasFp256()) {
9054 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9059 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9060 VT.getVectorNumElements() != SVT.getVectorNumElements());
9064 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9066 MVT VT = Op.getSimpleValueType();
9067 SDValue In = Op.getOperand(0);
9068 MVT InVT = In.getSimpleValueType();
9069 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9070 "Invalid TRUNCATE operation");
9072 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9073 if (VT.getVectorElementType().getSizeInBits() >=8)
9074 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9076 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9077 unsigned NumElts = InVT.getVectorNumElements();
9078 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9079 if (InVT.getSizeInBits() < 512) {
9080 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9081 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9084 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9085 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9086 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9087 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9088 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9089 MachinePointerInfo::getConstantPool(),
9090 false, false, false, Alignment);
9091 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9092 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9093 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9096 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9097 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9098 if (Subtarget->hasInt256()) {
9099 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9100 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9101 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9103 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9104 DAG.getIntPtrConstant(0));
9107 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9108 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9109 DAG.getIntPtrConstant(0));
9110 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9111 DAG.getIntPtrConstant(2));
9113 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9114 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9117 static const int ShufMask1[] = {0, 2, 0, 0};
9118 SDValue Undef = DAG.getUNDEF(VT);
9119 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9120 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9122 // The MOVLHPS mask:
9123 static const int ShufMask2[] = {0, 1, 4, 5};
9124 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9127 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9128 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9129 if (Subtarget->hasInt256()) {
9130 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9132 SmallVector<SDValue,32> pshufbMask;
9133 for (unsigned i = 0; i < 2; ++i) {
9134 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9135 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9136 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9137 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9138 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9139 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9140 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9141 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9142 for (unsigned j = 0; j < 8; ++j)
9143 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9145 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9146 &pshufbMask[0], 32);
9147 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9148 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9150 static const int ShufMask[] = {0, 2, -1, -1};
9151 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9153 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9154 DAG.getIntPtrConstant(0));
9155 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9158 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9159 DAG.getIntPtrConstant(0));
9161 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9162 DAG.getIntPtrConstant(4));
9164 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9165 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9168 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9169 -1, -1, -1, -1, -1, -1, -1, -1};
9171 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9172 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9173 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9175 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9176 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9178 // The MOVLHPS Mask:
9179 static const int ShufMask2[] = {0, 1, 4, 5};
9180 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9181 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9184 // Handle truncation of V256 to V128 using shuffles.
9185 if (!VT.is128BitVector() || !InVT.is256BitVector())
9188 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9190 unsigned NumElems = VT.getVectorNumElements();
9191 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9194 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9195 // Prepare truncation shuffle mask
9196 for (unsigned i = 0; i != NumElems; ++i)
9198 SDValue V = DAG.getVectorShuffle(NVT, DL,
9199 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9200 DAG.getUNDEF(NVT), &MaskVec[0]);
9201 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9202 DAG.getIntPtrConstant(0));
9205 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9206 SelectionDAG &DAG) const {
9207 MVT VT = Op.getSimpleValueType();
9208 if (VT.isVector()) {
9209 if (VT == MVT::v8i16)
9210 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9211 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9212 MVT::v8i32, Op.getOperand(0)));
9216 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9217 /*IsSigned=*/ true, /*IsReplace=*/ false);
9218 SDValue FIST = Vals.first, StackSlot = Vals.second;
9219 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9220 if (FIST.getNode() == 0) return Op;
9222 if (StackSlot.getNode())
9224 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9225 FIST, StackSlot, MachinePointerInfo(),
9226 false, false, false, 0);
9228 // The node is the result.
9232 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9233 SelectionDAG &DAG) const {
9234 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9235 /*IsSigned=*/ false, /*IsReplace=*/ false);
9236 SDValue FIST = Vals.first, StackSlot = Vals.second;
9237 assert(FIST.getNode() && "Unexpected failure");
9239 if (StackSlot.getNode())
9241 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9242 FIST, StackSlot, MachinePointerInfo(),
9243 false, false, false, 0);
9245 // The node is the result.
9249 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9251 MVT VT = Op.getSimpleValueType();
9252 SDValue In = Op.getOperand(0);
9253 MVT SVT = In.getSimpleValueType();
9255 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9257 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9258 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9259 In, DAG.getUNDEF(SVT)));
9262 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9263 LLVMContext *Context = DAG.getContext();
9265 MVT VT = Op.getSimpleValueType();
9267 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9268 if (VT.isVector()) {
9269 EltVT = VT.getVectorElementType();
9270 NumElts = VT.getVectorNumElements();
9273 if (EltVT == MVT::f64)
9274 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9275 APInt(64, ~(1ULL << 63))));
9277 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9278 APInt(32, ~(1U << 31))));
9279 C = ConstantVector::getSplat(NumElts, C);
9280 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9281 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9282 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9283 MachinePointerInfo::getConstantPool(),
9284 false, false, false, Alignment);
9285 if (VT.isVector()) {
9286 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9287 return DAG.getNode(ISD::BITCAST, dl, VT,
9288 DAG.getNode(ISD::AND, dl, ANDVT,
9289 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9291 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9293 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9296 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9297 LLVMContext *Context = DAG.getContext();
9299 MVT VT = Op.getSimpleValueType();
9301 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9302 if (VT.isVector()) {
9303 EltVT = VT.getVectorElementType();
9304 NumElts = VT.getVectorNumElements();
9307 if (EltVT == MVT::f64)
9308 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9309 APInt(64, 1ULL << 63)));
9311 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9312 APInt(32, 1U << 31)));
9313 C = ConstantVector::getSplat(NumElts, C);
9314 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9315 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9316 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9317 MachinePointerInfo::getConstantPool(),
9318 false, false, false, Alignment);
9319 if (VT.isVector()) {
9320 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9321 return DAG.getNode(ISD::BITCAST, dl, VT,
9322 DAG.getNode(ISD::XOR, dl, XORVT,
9323 DAG.getNode(ISD::BITCAST, dl, XORVT,
9325 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9328 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9331 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9332 LLVMContext *Context = DAG.getContext();
9333 SDValue Op0 = Op.getOperand(0);
9334 SDValue Op1 = Op.getOperand(1);
9336 MVT VT = Op.getSimpleValueType();
9337 MVT SrcVT = Op1.getSimpleValueType();
9339 // If second operand is smaller, extend it first.
9340 if (SrcVT.bitsLT(VT)) {
9341 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9344 // And if it is bigger, shrink it first.
9345 if (SrcVT.bitsGT(VT)) {
9346 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9350 // At this point the operands and the result should have the same
9351 // type, and that won't be f80 since that is not custom lowered.
9353 // First get the sign bit of second operand.
9354 SmallVector<Constant*,4> CV;
9355 if (SrcVT == MVT::f64) {
9356 const fltSemantics &Sem = APFloat::IEEEdouble;
9357 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9358 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9360 const fltSemantics &Sem = APFloat::IEEEsingle;
9361 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9362 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9363 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9364 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9366 Constant *C = ConstantVector::get(CV);
9367 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9368 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9369 MachinePointerInfo::getConstantPool(),
9370 false, false, false, 16);
9371 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9373 // Shift sign bit right or left if the two operands have different types.
9374 if (SrcVT.bitsGT(VT)) {
9375 // Op0 is MVT::f32, Op1 is MVT::f64.
9376 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9377 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9378 DAG.getConstant(32, MVT::i32));
9379 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9380 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9381 DAG.getIntPtrConstant(0));
9384 // Clear first operand sign bit.
9386 if (VT == MVT::f64) {
9387 const fltSemantics &Sem = APFloat::IEEEdouble;
9388 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9389 APInt(64, ~(1ULL << 63)))));
9390 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9392 const fltSemantics &Sem = APFloat::IEEEsingle;
9393 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9394 APInt(32, ~(1U << 31)))));
9395 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9396 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9397 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9399 C = ConstantVector::get(CV);
9400 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9401 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9402 MachinePointerInfo::getConstantPool(),
9403 false, false, false, 16);
9404 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9406 // Or the value with the sign bit.
9407 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9410 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9411 SDValue N0 = Op.getOperand(0);
9413 MVT VT = Op.getSimpleValueType();
9415 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9416 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9417 DAG.getConstant(1, VT));
9418 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9421 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9423 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9424 SelectionDAG &DAG) {
9425 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9427 if (!Subtarget->hasSSE41())
9430 if (!Op->hasOneUse())
9433 SDNode *N = Op.getNode();
9436 SmallVector<SDValue, 8> Opnds;
9437 DenseMap<SDValue, unsigned> VecInMap;
9438 EVT VT = MVT::Other;
9440 // Recognize a special case where a vector is casted into wide integer to
9442 Opnds.push_back(N->getOperand(0));
9443 Opnds.push_back(N->getOperand(1));
9445 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9446 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9447 // BFS traverse all OR'd operands.
9448 if (I->getOpcode() == ISD::OR) {
9449 Opnds.push_back(I->getOperand(0));
9450 Opnds.push_back(I->getOperand(1));
9451 // Re-evaluate the number of nodes to be traversed.
9452 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9456 // Quit if a non-EXTRACT_VECTOR_ELT
9457 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9460 // Quit if without a constant index.
9461 SDValue Idx = I->getOperand(1);
9462 if (!isa<ConstantSDNode>(Idx))
9465 SDValue ExtractedFromVec = I->getOperand(0);
9466 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9467 if (M == VecInMap.end()) {
9468 VT = ExtractedFromVec.getValueType();
9469 // Quit if not 128/256-bit vector.
9470 if (!VT.is128BitVector() && !VT.is256BitVector())
9472 // Quit if not the same type.
9473 if (VecInMap.begin() != VecInMap.end() &&
9474 VT != VecInMap.begin()->first.getValueType())
9476 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9478 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9481 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9482 "Not extracted from 128-/256-bit vector.");
9484 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9485 SmallVector<SDValue, 8> VecIns;
9487 for (DenseMap<SDValue, unsigned>::const_iterator
9488 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9489 // Quit if not all elements are used.
9490 if (I->second != FullMask)
9492 VecIns.push_back(I->first);
9495 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9497 // Cast all vectors into TestVT for PTEST.
9498 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9499 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9501 // If more than one full vectors are evaluated, OR them first before PTEST.
9502 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9503 // Each iteration will OR 2 nodes and append the result until there is only
9504 // 1 node left, i.e. the final OR'd value of all vectors.
9505 SDValue LHS = VecIns[Slot];
9506 SDValue RHS = VecIns[Slot + 1];
9507 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9510 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9511 VecIns.back(), VecIns.back());
9514 /// Emit nodes that will be selected as "test Op0,Op0", or something
9516 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9517 SelectionDAG &DAG) const {
9520 // CF and OF aren't always set the way we want. Determine which
9521 // of these we need.
9522 bool NeedCF = false;
9523 bool NeedOF = false;
9526 case X86::COND_A: case X86::COND_AE:
9527 case X86::COND_B: case X86::COND_BE:
9530 case X86::COND_G: case X86::COND_GE:
9531 case X86::COND_L: case X86::COND_LE:
9532 case X86::COND_O: case X86::COND_NO:
9537 // See if we can use the EFLAGS value from the operand instead of
9538 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9539 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9540 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9541 // Emit a CMP with 0, which is the TEST pattern.
9542 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9543 DAG.getConstant(0, Op.getValueType()));
9545 unsigned Opcode = 0;
9546 unsigned NumOperands = 0;
9548 // Truncate operations may prevent the merge of the SETCC instruction
9549 // and the arithmetic instruction before it. Attempt to truncate the operands
9550 // of the arithmetic instruction and use a reduced bit-width instruction.
9551 bool NeedTruncation = false;
9552 SDValue ArithOp = Op;
9553 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9554 SDValue Arith = Op->getOperand(0);
9555 // Both the trunc and the arithmetic op need to have one user each.
9556 if (Arith->hasOneUse())
9557 switch (Arith.getOpcode()) {
9564 NeedTruncation = true;
9570 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9571 // which may be the result of a CAST. We use the variable 'Op', which is the
9572 // non-casted variable when we check for possible users.
9573 switch (ArithOp.getOpcode()) {
9575 // Due to an isel shortcoming, be conservative if this add is likely to be
9576 // selected as part of a load-modify-store instruction. When the root node
9577 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9578 // uses of other nodes in the match, such as the ADD in this case. This
9579 // leads to the ADD being left around and reselected, with the result being
9580 // two adds in the output. Alas, even if none our users are stores, that
9581 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9582 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9583 // climbing the DAG back to the root, and it doesn't seem to be worth the
9585 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9586 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9587 if (UI->getOpcode() != ISD::CopyToReg &&
9588 UI->getOpcode() != ISD::SETCC &&
9589 UI->getOpcode() != ISD::STORE)
9592 if (ConstantSDNode *C =
9593 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9594 // An add of one will be selected as an INC.
9595 if (C->getAPIntValue() == 1) {
9596 Opcode = X86ISD::INC;
9601 // An add of negative one (subtract of one) will be selected as a DEC.
9602 if (C->getAPIntValue().isAllOnesValue()) {
9603 Opcode = X86ISD::DEC;
9609 // Otherwise use a regular EFLAGS-setting add.
9610 Opcode = X86ISD::ADD;
9614 // If the primary and result isn't used, don't bother using X86ISD::AND,
9615 // because a TEST instruction will be better.
9616 bool NonFlagUse = false;
9617 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9618 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9620 unsigned UOpNo = UI.getOperandNo();
9621 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9622 // Look pass truncate.
9623 UOpNo = User->use_begin().getOperandNo();
9624 User = *User->use_begin();
9627 if (User->getOpcode() != ISD::BRCOND &&
9628 User->getOpcode() != ISD::SETCC &&
9629 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9642 // Due to the ISEL shortcoming noted above, be conservative if this op is
9643 // likely to be selected as part of a load-modify-store instruction.
9644 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9645 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9646 if (UI->getOpcode() == ISD::STORE)
9649 // Otherwise use a regular EFLAGS-setting instruction.
9650 switch (ArithOp.getOpcode()) {
9651 default: llvm_unreachable("unexpected operator!");
9652 case ISD::SUB: Opcode = X86ISD::SUB; break;
9653 case ISD::XOR: Opcode = X86ISD::XOR; break;
9654 case ISD::AND: Opcode = X86ISD::AND; break;
9656 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9657 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9658 if (EFLAGS.getNode())
9661 Opcode = X86ISD::OR;
9675 return SDValue(Op.getNode(), 1);
9681 // If we found that truncation is beneficial, perform the truncation and
9683 if (NeedTruncation) {
9684 EVT VT = Op.getValueType();
9685 SDValue WideVal = Op->getOperand(0);
9686 EVT WideVT = WideVal.getValueType();
9687 unsigned ConvertedOp = 0;
9688 // Use a target machine opcode to prevent further DAGCombine
9689 // optimizations that may separate the arithmetic operations
9690 // from the setcc node.
9691 switch (WideVal.getOpcode()) {
9693 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9694 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9695 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9696 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9697 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9702 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9703 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9704 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9705 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9711 // Emit a CMP with 0, which is the TEST pattern.
9712 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9713 DAG.getConstant(0, Op.getValueType()));
9715 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9716 SmallVector<SDValue, 4> Ops;
9717 for (unsigned i = 0; i != NumOperands; ++i)
9718 Ops.push_back(Op.getOperand(i));
9720 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9721 DAG.ReplaceAllUsesWith(Op, New);
9722 return SDValue(New.getNode(), 1);
9725 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9727 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9728 SelectionDAG &DAG) const {
9730 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9731 if (C->getAPIntValue() == 0)
9732 return EmitTest(Op0, X86CC, DAG);
9734 if (Op0.getValueType() == MVT::i1) {
9735 Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0, DAG.getConstant(-1, MVT::i1));
9736 return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op0, Op0);
9740 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9741 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9742 // Do the comparison at i32 if it's smaller. This avoids subregister
9743 // aliasing issues. Keep the smaller reference if we're optimizing for
9744 // size, however, as that'll allow better folding of memory operations.
9745 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9746 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9747 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9749 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9750 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9751 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9753 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9754 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9755 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9757 return SDValue(Sub.getNode(), 1);
9759 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9762 /// Convert a comparison if required by the subtarget.
9763 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9764 SelectionDAG &DAG) const {
9765 // If the subtarget does not support the FUCOMI instruction, floating-point
9766 // comparisons have to be converted.
9767 if (Subtarget->hasCMov() ||
9768 Cmp.getOpcode() != X86ISD::CMP ||
9769 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9770 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9773 // The instruction selector will select an FUCOM instruction instead of
9774 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9775 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9776 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9778 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9779 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9780 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9781 DAG.getConstant(8, MVT::i8));
9782 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9783 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9786 static bool isAllOnes(SDValue V) {
9787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9788 return C && C->isAllOnesValue();
9791 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9792 /// if it's possible.
9793 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9794 SDLoc dl, SelectionDAG &DAG) const {
9795 SDValue Op0 = And.getOperand(0);
9796 SDValue Op1 = And.getOperand(1);
9797 if (Op0.getOpcode() == ISD::TRUNCATE)
9798 Op0 = Op0.getOperand(0);
9799 if (Op1.getOpcode() == ISD::TRUNCATE)
9800 Op1 = Op1.getOperand(0);
9803 if (Op1.getOpcode() == ISD::SHL)
9804 std::swap(Op0, Op1);
9805 if (Op0.getOpcode() == ISD::SHL) {
9806 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9807 if (And00C->getZExtValue() == 1) {
9808 // If we looked past a truncate, check that it's only truncating away
9810 unsigned BitWidth = Op0.getValueSizeInBits();
9811 unsigned AndBitWidth = And.getValueSizeInBits();
9812 if (BitWidth > AndBitWidth) {
9814 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9815 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9819 RHS = Op0.getOperand(1);
9821 } else if (Op1.getOpcode() == ISD::Constant) {
9822 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9823 uint64_t AndRHSVal = AndRHS->getZExtValue();
9824 SDValue AndLHS = Op0;
9826 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9827 LHS = AndLHS.getOperand(0);
9828 RHS = AndLHS.getOperand(1);
9831 // Use BT if the immediate can't be encoded in a TEST instruction.
9832 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9834 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9838 if (LHS.getNode()) {
9839 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9840 // instruction. Since the shift amount is in-range-or-undefined, we know
9841 // that doing a bittest on the i32 value is ok. We extend to i32 because
9842 // the encoding for the i16 version is larger than the i32 version.
9843 // Also promote i16 to i32 for performance / code size reason.
9844 if (LHS.getValueType() == MVT::i8 ||
9845 LHS.getValueType() == MVT::i16)
9846 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9848 // If the operand types disagree, extend the shift amount to match. Since
9849 // BT ignores high bits (like shifts) we can use anyextend.
9850 if (LHS.getValueType() != RHS.getValueType())
9851 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9853 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9854 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9855 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9856 DAG.getConstant(Cond, MVT::i8), BT);
9862 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9864 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9869 // SSE Condition code mapping:
9878 switch (SetCCOpcode) {
9879 default: llvm_unreachable("Unexpected SETCC condition");
9881 case ISD::SETEQ: SSECC = 0; break;
9883 case ISD::SETGT: Swap = true; // Fallthrough
9885 case ISD::SETOLT: SSECC = 1; break;
9887 case ISD::SETGE: Swap = true; // Fallthrough
9889 case ISD::SETOLE: SSECC = 2; break;
9890 case ISD::SETUO: SSECC = 3; break;
9892 case ISD::SETNE: SSECC = 4; break;
9893 case ISD::SETULE: Swap = true; // Fallthrough
9894 case ISD::SETUGE: SSECC = 5; break;
9895 case ISD::SETULT: Swap = true; // Fallthrough
9896 case ISD::SETUGT: SSECC = 6; break;
9897 case ISD::SETO: SSECC = 7; break;
9899 case ISD::SETONE: SSECC = 8; break;
9902 std::swap(Op0, Op1);
9907 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9908 // ones, and then concatenate the result back.
9909 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9910 MVT VT = Op.getSimpleValueType();
9912 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9913 "Unsupported value type for operation");
9915 unsigned NumElems = VT.getVectorNumElements();
9917 SDValue CC = Op.getOperand(2);
9919 // Extract the LHS vectors
9920 SDValue LHS = Op.getOperand(0);
9921 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9922 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9924 // Extract the RHS vectors
9925 SDValue RHS = Op.getOperand(1);
9926 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9927 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9929 // Issue the operation on the smaller types and concatenate the result back
9930 MVT EltVT = VT.getVectorElementType();
9931 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9932 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9933 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9934 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9937 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9938 SDValue Op0 = Op.getOperand(0);
9939 SDValue Op1 = Op.getOperand(1);
9940 SDValue CC = Op.getOperand(2);
9941 MVT VT = Op.getSimpleValueType();
9943 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9944 Op.getValueType().getScalarType() == MVT::i1 &&
9945 "Cannot set masked compare for this operation");
9947 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9950 bool Unsigned = false;
9952 switch (SetCCOpcode) {
9953 default: llvm_unreachable("Unexpected SETCC condition");
9954 case ISD::SETNE: SSECC = 4; break;
9955 case ISD::SETEQ: SSECC = 0; break;
9956 case ISD::SETUGT: Unsigned = true;
9957 case ISD::SETGT: SSECC = 6; break; // NLE
9958 case ISD::SETULT: Unsigned = true;
9959 case ISD::SETLT: SSECC = 1; break;
9960 case ISD::SETUGE: Unsigned = true;
9961 case ISD::SETGE: SSECC = 5; break; // NLT
9962 case ISD::SETULE: Unsigned = true;
9963 case ISD::SETLE: SSECC = 2; break;
9965 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9966 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9967 DAG.getConstant(SSECC, MVT::i8));
9971 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9972 SelectionDAG &DAG) {
9973 SDValue Op0 = Op.getOperand(0);
9974 SDValue Op1 = Op.getOperand(1);
9975 SDValue CC = Op.getOperand(2);
9976 MVT VT = Op.getSimpleValueType();
9977 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9978 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9983 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9984 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9987 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9988 unsigned Opc = X86ISD::CMPP;
9989 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9990 assert(VT.getVectorNumElements() <= 16);
9993 // In the two special cases we can't handle, emit two comparisons.
9996 unsigned CombineOpc;
9997 if (SetCCOpcode == ISD::SETUEQ) {
9998 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10000 assert(SetCCOpcode == ISD::SETONE);
10001 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10004 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10005 DAG.getConstant(CC0, MVT::i8));
10006 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10007 DAG.getConstant(CC1, MVT::i8));
10008 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10010 // Handle all other FP comparisons here.
10011 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10012 DAG.getConstant(SSECC, MVT::i8));
10015 // Break 256-bit integer vector compare into smaller ones.
10016 if (VT.is256BitVector() && !Subtarget->hasInt256())
10017 return Lower256IntVSETCC(Op, DAG);
10019 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10020 EVT OpVT = Op1.getValueType();
10021 if (Subtarget->hasAVX512()) {
10022 if (Op1.getValueType().is512BitVector() ||
10023 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10024 return LowerIntVSETCC_AVX512(Op, DAG);
10026 // In AVX-512 architecture setcc returns mask with i1 elements,
10027 // But there is no compare instruction for i8 and i16 elements.
10028 // We are not talking about 512-bit operands in this case, these
10029 // types are illegal.
10031 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10032 OpVT.getVectorElementType().getSizeInBits() >= 8))
10033 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10034 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10037 // We are handling one of the integer comparisons here. Since SSE only has
10038 // GT and EQ comparisons for integer, swapping operands and multiple
10039 // operations may be required for some comparisons.
10041 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10043 switch (SetCCOpcode) {
10044 default: llvm_unreachable("Unexpected SETCC condition");
10045 case ISD::SETNE: Invert = true;
10046 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
10047 case ISD::SETLT: Swap = true;
10048 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
10049 case ISD::SETGE: Swap = true;
10050 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10051 Invert = true; break;
10052 case ISD::SETULT: Swap = true;
10053 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10054 FlipSigns = true; break;
10055 case ISD::SETUGE: Swap = true;
10056 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10057 FlipSigns = true; Invert = true; break;
10060 // Special case: Use min/max operations for SETULE/SETUGE
10061 MVT VET = VT.getVectorElementType();
10063 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10064 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10067 switch (SetCCOpcode) {
10069 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10070 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10073 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10077 std::swap(Op0, Op1);
10079 // Check that the operation in question is available (most are plain SSE2,
10080 // but PCMPGTQ and PCMPEQQ have different requirements).
10081 if (VT == MVT::v2i64) {
10082 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10083 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10085 // First cast everything to the right type.
10086 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10087 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10089 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10090 // bits of the inputs before performing those operations. The lower
10091 // compare is always unsigned.
10094 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10096 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10097 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10098 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10099 Sign, Zero, Sign, Zero);
10101 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10102 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10104 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10105 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10106 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10108 // Create masks for only the low parts/high parts of the 64 bit integers.
10109 static const int MaskHi[] = { 1, 1, 3, 3 };
10110 static const int MaskLo[] = { 0, 0, 2, 2 };
10111 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10112 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10113 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10115 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10116 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10119 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10121 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10124 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10125 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10126 // pcmpeqd + pshufd + pand.
10127 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10129 // First cast everything to the right type.
10130 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10131 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10134 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10136 // Make sure the lower and upper halves are both all-ones.
10137 static const int Mask[] = { 1, 0, 3, 2 };
10138 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10139 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10142 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10144 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10148 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10149 // bits of the inputs before performing those operations.
10151 EVT EltVT = VT.getVectorElementType();
10152 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10153 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10154 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10157 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10159 // If the logical-not of the result is required, perform that now.
10161 Result = DAG.getNOT(dl, Result, VT);
10164 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10169 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10171 MVT VT = Op.getSimpleValueType();
10173 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10175 assert((VT == MVT::i8 || (Subtarget->hasAVX512() && VT == MVT::i1))
10176 && "SetCC type must be 8-bit or 1-bit integer");
10177 SDValue Op0 = Op.getOperand(0);
10178 SDValue Op1 = Op.getOperand(1);
10180 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10182 // Optimize to BT if possible.
10183 // Lower (X & (1 << N)) == 0 to BT(X, N).
10184 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10185 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10186 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10187 Op1.getOpcode() == ISD::Constant &&
10188 cast<ConstantSDNode>(Op1)->isNullValue() &&
10189 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10190 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10191 if (NewSetCC.getNode())
10195 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10197 if (Op1.getOpcode() == ISD::Constant &&
10198 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10199 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10200 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10202 // If the input is a setcc, then reuse the input setcc or use a new one with
10203 // the inverted condition.
10204 if (Op0.getOpcode() == X86ISD::SETCC) {
10205 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10206 bool Invert = (CC == ISD::SETNE) ^
10207 cast<ConstantSDNode>(Op1)->isNullValue();
10208 if (!Invert) return Op0;
10210 CCode = X86::GetOppositeBranchCondition(CCode);
10211 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10212 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10216 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10217 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10218 if (X86CC == X86::COND_INVALID)
10221 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10222 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10223 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10224 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10227 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10228 static bool isX86LogicalCmp(SDValue Op) {
10229 unsigned Opc = Op.getNode()->getOpcode();
10230 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10231 Opc == X86ISD::SAHF)
10233 if (Op.getResNo() == 1 &&
10234 (Opc == X86ISD::ADD ||
10235 Opc == X86ISD::SUB ||
10236 Opc == X86ISD::ADC ||
10237 Opc == X86ISD::SBB ||
10238 Opc == X86ISD::SMUL ||
10239 Opc == X86ISD::UMUL ||
10240 Opc == X86ISD::INC ||
10241 Opc == X86ISD::DEC ||
10242 Opc == X86ISD::OR ||
10243 Opc == X86ISD::XOR ||
10244 Opc == X86ISD::AND))
10247 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10253 static bool isZero(SDValue V) {
10254 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10255 return C && C->isNullValue();
10258 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10259 if (V.getOpcode() != ISD::TRUNCATE)
10262 SDValue VOp0 = V.getOperand(0);
10263 unsigned InBits = VOp0.getValueSizeInBits();
10264 unsigned Bits = V.getValueSizeInBits();
10265 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10268 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10269 bool addTest = true;
10270 SDValue Cond = Op.getOperand(0);
10271 SDValue Op1 = Op.getOperand(1);
10272 SDValue Op2 = Op.getOperand(2);
10274 EVT VT = Op1.getValueType();
10277 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10278 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10279 // sequence later on.
10280 if (Cond.getOpcode() == ISD::SETCC &&
10281 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10282 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10283 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10284 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10285 int SSECC = translateX86FSETCC(
10286 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10289 if (Subtarget->hasAVX512()) {
10290 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10291 DAG.getConstant(SSECC, MVT::i8));
10292 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10294 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10295 DAG.getConstant(SSECC, MVT::i8));
10296 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10297 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10298 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10302 if (Cond.getOpcode() == ISD::SETCC) {
10303 SDValue NewCond = LowerSETCC(Cond, DAG);
10304 if (NewCond.getNode())
10308 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10309 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10310 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10311 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10312 if (Cond.getOpcode() == X86ISD::SETCC &&
10313 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10314 isZero(Cond.getOperand(1).getOperand(1))) {
10315 SDValue Cmp = Cond.getOperand(1);
10317 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10319 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10320 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10321 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10323 SDValue CmpOp0 = Cmp.getOperand(0);
10324 // Apply further optimizations for special cases
10325 // (select (x != 0), -1, 0) -> neg & sbb
10326 // (select (x == 0), 0, -1) -> neg & sbb
10327 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10328 if (YC->isNullValue() &&
10329 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10330 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10331 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10332 DAG.getConstant(0, CmpOp0.getValueType()),
10334 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10335 DAG.getConstant(X86::COND_B, MVT::i8),
10336 SDValue(Neg.getNode(), 1));
10340 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10341 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10342 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10344 SDValue Res = // Res = 0 or -1.
10345 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10346 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10348 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10349 Res = DAG.getNOT(DL, Res, Res.getValueType());
10351 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10352 if (N2C == 0 || !N2C->isNullValue())
10353 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10358 // Look past (and (setcc_carry (cmp ...)), 1).
10359 if (Cond.getOpcode() == ISD::AND &&
10360 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10361 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10362 if (C && C->getAPIntValue() == 1)
10363 Cond = Cond.getOperand(0);
10366 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10367 // setting operand in place of the X86ISD::SETCC.
10368 unsigned CondOpcode = Cond.getOpcode();
10369 if (CondOpcode == X86ISD::SETCC ||
10370 CondOpcode == X86ISD::SETCC_CARRY) {
10371 CC = Cond.getOperand(0);
10373 SDValue Cmp = Cond.getOperand(1);
10374 unsigned Opc = Cmp.getOpcode();
10375 MVT VT = Op.getSimpleValueType();
10377 bool IllegalFPCMov = false;
10378 if (VT.isFloatingPoint() && !VT.isVector() &&
10379 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10380 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10382 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10383 Opc == X86ISD::BT) { // FIXME
10387 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10388 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10389 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10390 Cond.getOperand(0).getValueType() != MVT::i8)) {
10391 SDValue LHS = Cond.getOperand(0);
10392 SDValue RHS = Cond.getOperand(1);
10393 unsigned X86Opcode;
10396 switch (CondOpcode) {
10397 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10398 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10399 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10400 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10401 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10402 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10403 default: llvm_unreachable("unexpected overflowing operator");
10405 if (CondOpcode == ISD::UMULO)
10406 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10409 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10411 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10413 if (CondOpcode == ISD::UMULO)
10414 Cond = X86Op.getValue(2);
10416 Cond = X86Op.getValue(1);
10418 CC = DAG.getConstant(X86Cond, MVT::i8);
10423 // Look pass the truncate if the high bits are known zero.
10424 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10425 Cond = Cond.getOperand(0);
10427 // We know the result of AND is compared against zero. Try to match
10429 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10430 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10431 if (NewSetCC.getNode()) {
10432 CC = NewSetCC.getOperand(0);
10433 Cond = NewSetCC.getOperand(1);
10440 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10441 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10444 // a < b ? -1 : 0 -> RES = ~setcc_carry
10445 // a < b ? 0 : -1 -> RES = setcc_carry
10446 // a >= b ? -1 : 0 -> RES = setcc_carry
10447 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10448 if (Cond.getOpcode() == X86ISD::SUB) {
10449 Cond = ConvertCmpIfNecessary(Cond, DAG);
10450 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10452 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10453 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10454 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10455 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10456 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10457 return DAG.getNOT(DL, Res, Res.getValueType());
10462 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10463 // widen the cmov and push the truncate through. This avoids introducing a new
10464 // branch during isel and doesn't add any extensions.
10465 if (Op.getValueType() == MVT::i8 &&
10466 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10467 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10468 if (T1.getValueType() == T2.getValueType() &&
10469 // Blacklist CopyFromReg to avoid partial register stalls.
10470 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10471 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10472 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10473 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10477 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10478 // condition is true.
10479 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10480 SDValue Ops[] = { Op2, Op1, CC, Cond };
10481 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10484 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10485 MVT VT = Op->getSimpleValueType(0);
10486 SDValue In = Op->getOperand(0);
10487 MVT InVT = In.getSimpleValueType();
10490 unsigned int NumElts = VT.getVectorNumElements();
10491 if (NumElts != 8 && NumElts != 16)
10494 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10495 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10498 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10500 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10501 Constant *C = ConstantInt::get(*DAG.getContext(),
10502 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10504 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10505 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10506 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10507 MachinePointerInfo::getConstantPool(),
10508 false, false, false, Alignment);
10509 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10510 if (VT.is512BitVector())
10512 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10515 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10516 SelectionDAG &DAG) {
10517 MVT VT = Op->getSimpleValueType(0);
10518 SDValue In = Op->getOperand(0);
10519 MVT InVT = In.getSimpleValueType();
10522 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10523 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10525 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10526 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10527 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10530 if (Subtarget->hasInt256())
10531 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10533 // Optimize vectors in AVX mode
10534 // Sign extend v8i16 to v8i32 and
10537 // Divide input vector into two parts
10538 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10539 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10540 // concat the vectors to original VT
10542 unsigned NumElems = InVT.getVectorNumElements();
10543 SDValue Undef = DAG.getUNDEF(InVT);
10545 SmallVector<int,8> ShufMask1(NumElems, -1);
10546 for (unsigned i = 0; i != NumElems/2; ++i)
10549 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10551 SmallVector<int,8> ShufMask2(NumElems, -1);
10552 for (unsigned i = 0; i != NumElems/2; ++i)
10553 ShufMask2[i] = i + NumElems/2;
10555 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10557 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10558 VT.getVectorNumElements()/2);
10560 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10561 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10563 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10566 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10567 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10568 // from the AND / OR.
10569 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10570 Opc = Op.getOpcode();
10571 if (Opc != ISD::OR && Opc != ISD::AND)
10573 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10574 Op.getOperand(0).hasOneUse() &&
10575 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10576 Op.getOperand(1).hasOneUse());
10579 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10580 // 1 and that the SETCC node has a single use.
10581 static bool isXor1OfSetCC(SDValue Op) {
10582 if (Op.getOpcode() != ISD::XOR)
10584 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10585 if (N1C && N1C->getAPIntValue() == 1) {
10586 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10587 Op.getOperand(0).hasOneUse();
10592 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10593 bool addTest = true;
10594 SDValue Chain = Op.getOperand(0);
10595 SDValue Cond = Op.getOperand(1);
10596 SDValue Dest = Op.getOperand(2);
10599 bool Inverted = false;
10601 if (Cond.getOpcode() == ISD::SETCC) {
10602 // Check for setcc([su]{add,sub,mul}o == 0).
10603 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10604 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10605 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10606 Cond.getOperand(0).getResNo() == 1 &&
10607 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10608 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10609 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10610 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10611 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10612 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10614 Cond = Cond.getOperand(0);
10616 SDValue NewCond = LowerSETCC(Cond, DAG);
10617 if (NewCond.getNode())
10622 // FIXME: LowerXALUO doesn't handle these!!
10623 else if (Cond.getOpcode() == X86ISD::ADD ||
10624 Cond.getOpcode() == X86ISD::SUB ||
10625 Cond.getOpcode() == X86ISD::SMUL ||
10626 Cond.getOpcode() == X86ISD::UMUL)
10627 Cond = LowerXALUO(Cond, DAG);
10630 // Look pass (and (setcc_carry (cmp ...)), 1).
10631 if (Cond.getOpcode() == ISD::AND &&
10632 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10634 if (C && C->getAPIntValue() == 1)
10635 Cond = Cond.getOperand(0);
10638 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10639 // setting operand in place of the X86ISD::SETCC.
10640 unsigned CondOpcode = Cond.getOpcode();
10641 if (CondOpcode == X86ISD::SETCC ||
10642 CondOpcode == X86ISD::SETCC_CARRY) {
10643 CC = Cond.getOperand(0);
10645 SDValue Cmp = Cond.getOperand(1);
10646 unsigned Opc = Cmp.getOpcode();
10647 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10648 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10652 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10656 // These can only come from an arithmetic instruction with overflow,
10657 // e.g. SADDO, UADDO.
10658 Cond = Cond.getNode()->getOperand(1);
10664 CondOpcode = Cond.getOpcode();
10665 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10666 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10667 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10668 Cond.getOperand(0).getValueType() != MVT::i8)) {
10669 SDValue LHS = Cond.getOperand(0);
10670 SDValue RHS = Cond.getOperand(1);
10671 unsigned X86Opcode;
10674 switch (CondOpcode) {
10675 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10676 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10677 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10678 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10679 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10680 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10681 default: llvm_unreachable("unexpected overflowing operator");
10684 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10685 if (CondOpcode == ISD::UMULO)
10686 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10689 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10691 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10693 if (CondOpcode == ISD::UMULO)
10694 Cond = X86Op.getValue(2);
10696 Cond = X86Op.getValue(1);
10698 CC = DAG.getConstant(X86Cond, MVT::i8);
10702 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10703 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10704 if (CondOpc == ISD::OR) {
10705 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10706 // two branches instead of an explicit OR instruction with a
10708 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10709 isX86LogicalCmp(Cmp)) {
10710 CC = Cond.getOperand(0).getOperand(0);
10711 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10712 Chain, Dest, CC, Cmp);
10713 CC = Cond.getOperand(1).getOperand(0);
10717 } else { // ISD::AND
10718 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10719 // two branches instead of an explicit AND instruction with a
10720 // separate test. However, we only do this if this block doesn't
10721 // have a fall-through edge, because this requires an explicit
10722 // jmp when the condition is false.
10723 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10724 isX86LogicalCmp(Cmp) &&
10725 Op.getNode()->hasOneUse()) {
10726 X86::CondCode CCode =
10727 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10728 CCode = X86::GetOppositeBranchCondition(CCode);
10729 CC = DAG.getConstant(CCode, MVT::i8);
10730 SDNode *User = *Op.getNode()->use_begin();
10731 // Look for an unconditional branch following this conditional branch.
10732 // We need this because we need to reverse the successors in order
10733 // to implement FCMP_OEQ.
10734 if (User->getOpcode() == ISD::BR) {
10735 SDValue FalseBB = User->getOperand(1);
10737 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10738 assert(NewBR == User);
10742 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10743 Chain, Dest, CC, Cmp);
10744 X86::CondCode CCode =
10745 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10746 CCode = X86::GetOppositeBranchCondition(CCode);
10747 CC = DAG.getConstant(CCode, MVT::i8);
10753 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10754 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10755 // It should be transformed during dag combiner except when the condition
10756 // is set by a arithmetics with overflow node.
10757 X86::CondCode CCode =
10758 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10759 CCode = X86::GetOppositeBranchCondition(CCode);
10760 CC = DAG.getConstant(CCode, MVT::i8);
10761 Cond = Cond.getOperand(0).getOperand(1);
10763 } else if (Cond.getOpcode() == ISD::SETCC &&
10764 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10765 // For FCMP_OEQ, we can emit
10766 // two branches instead of an explicit AND instruction with a
10767 // separate test. However, we only do this if this block doesn't
10768 // have a fall-through edge, because this requires an explicit
10769 // jmp when the condition is false.
10770 if (Op.getNode()->hasOneUse()) {
10771 SDNode *User = *Op.getNode()->use_begin();
10772 // Look for an unconditional branch following this conditional branch.
10773 // We need this because we need to reverse the successors in order
10774 // to implement FCMP_OEQ.
10775 if (User->getOpcode() == ISD::BR) {
10776 SDValue FalseBB = User->getOperand(1);
10778 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10779 assert(NewBR == User);
10783 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10784 Cond.getOperand(0), Cond.getOperand(1));
10785 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10786 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10787 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10788 Chain, Dest, CC, Cmp);
10789 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10794 } else if (Cond.getOpcode() == ISD::SETCC &&
10795 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10796 // For FCMP_UNE, we can emit
10797 // two branches instead of an explicit AND instruction with a
10798 // separate test. However, we only do this if this block doesn't
10799 // have a fall-through edge, because this requires an explicit
10800 // jmp when the condition is false.
10801 if (Op.getNode()->hasOneUse()) {
10802 SDNode *User = *Op.getNode()->use_begin();
10803 // Look for an unconditional branch following this conditional branch.
10804 // We need this because we need to reverse the successors in order
10805 // to implement FCMP_UNE.
10806 if (User->getOpcode() == ISD::BR) {
10807 SDValue FalseBB = User->getOperand(1);
10809 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10810 assert(NewBR == User);
10813 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10814 Cond.getOperand(0), Cond.getOperand(1));
10815 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10816 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10817 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10818 Chain, Dest, CC, Cmp);
10819 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10829 // Look pass the truncate if the high bits are known zero.
10830 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10831 Cond = Cond.getOperand(0);
10833 // We know the result of AND is compared against zero. Try to match
10835 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10836 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10837 if (NewSetCC.getNode()) {
10838 CC = NewSetCC.getOperand(0);
10839 Cond = NewSetCC.getOperand(1);
10846 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10847 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10849 Cond = ConvertCmpIfNecessary(Cond, DAG);
10850 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10851 Chain, Dest, CC, Cond);
10854 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10855 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10856 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10857 // that the guard pages used by the OS virtual memory manager are allocated in
10858 // correct sequence.
10860 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10861 SelectionDAG &DAG) const {
10862 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10863 getTargetMachine().Options.EnableSegmentedStacks) &&
10864 "This should be used only on Windows targets or when segmented stacks "
10866 assert(!Subtarget->isTargetMacho() && "Not implemented");
10870 SDValue Chain = Op.getOperand(0);
10871 SDValue Size = Op.getOperand(1);
10872 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10873 EVT VT = Op.getNode()->getValueType(0);
10875 bool Is64Bit = Subtarget->is64Bit();
10876 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10878 if (getTargetMachine().Options.EnableSegmentedStacks) {
10879 MachineFunction &MF = DAG.getMachineFunction();
10880 MachineRegisterInfo &MRI = MF.getRegInfo();
10883 // The 64 bit implementation of segmented stacks needs to clobber both r10
10884 // r11. This makes it impossible to use it along with nested parameters.
10885 const Function *F = MF.getFunction();
10887 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10889 if (I->hasNestAttr())
10890 report_fatal_error("Cannot use segmented stacks with functions that "
10891 "have nested arguments.");
10894 const TargetRegisterClass *AddrRegClass =
10895 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10896 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10897 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10898 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10899 DAG.getRegister(Vreg, SPTy));
10900 SDValue Ops1[2] = { Value, Chain };
10901 return DAG.getMergeValues(Ops1, 2, dl);
10904 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10906 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10907 Flag = Chain.getValue(1);
10908 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10910 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10912 const X86RegisterInfo *RegInfo =
10913 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10914 unsigned SPReg = RegInfo->getStackRegister();
10915 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10916 Chain = SP.getValue(1);
10919 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10920 DAG.getConstant(-(uint64_t)Align, VT));
10921 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10924 SDValue Ops1[2] = { SP, Chain };
10925 return DAG.getMergeValues(Ops1, 2, dl);
10929 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10930 MachineFunction &MF = DAG.getMachineFunction();
10931 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10933 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10936 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10937 // vastart just stores the address of the VarArgsFrameIndex slot into the
10938 // memory location argument.
10939 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10941 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10942 MachinePointerInfo(SV), false, false, 0);
10946 // gp_offset (0 - 6 * 8)
10947 // fp_offset (48 - 48 + 8 * 16)
10948 // overflow_arg_area (point to parameters coming in memory).
10950 SmallVector<SDValue, 8> MemOps;
10951 SDValue FIN = Op.getOperand(1);
10953 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10954 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10956 FIN, MachinePointerInfo(SV), false, false, 0);
10957 MemOps.push_back(Store);
10960 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10961 FIN, DAG.getIntPtrConstant(4));
10962 Store = DAG.getStore(Op.getOperand(0), DL,
10963 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10965 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10966 MemOps.push_back(Store);
10968 // Store ptr to overflow_arg_area
10969 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10970 FIN, DAG.getIntPtrConstant(4));
10971 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10973 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10974 MachinePointerInfo(SV, 8),
10976 MemOps.push_back(Store);
10978 // Store ptr to reg_save_area.
10979 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10980 FIN, DAG.getIntPtrConstant(8));
10981 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10983 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10984 MachinePointerInfo(SV, 16), false, false, 0);
10985 MemOps.push_back(Store);
10986 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10987 &MemOps[0], MemOps.size());
10990 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10991 assert(Subtarget->is64Bit() &&
10992 "LowerVAARG only handles 64-bit va_arg!");
10993 assert((Subtarget->isTargetLinux() ||
10994 Subtarget->isTargetDarwin()) &&
10995 "Unhandled target in LowerVAARG");
10996 assert(Op.getNode()->getNumOperands() == 4);
10997 SDValue Chain = Op.getOperand(0);
10998 SDValue SrcPtr = Op.getOperand(1);
10999 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11000 unsigned Align = Op.getConstantOperandVal(3);
11003 EVT ArgVT = Op.getNode()->getValueType(0);
11004 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11005 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11008 // Decide which area this value should be read from.
11009 // TODO: Implement the AMD64 ABI in its entirety. This simple
11010 // selection mechanism works only for the basic types.
11011 if (ArgVT == MVT::f80) {
11012 llvm_unreachable("va_arg for f80 not yet implemented");
11013 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11014 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11015 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11016 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11018 llvm_unreachable("Unhandled argument type in LowerVAARG");
11021 if (ArgMode == 2) {
11022 // Sanity Check: Make sure using fp_offset makes sense.
11023 assert(!getTargetMachine().Options.UseSoftFloat &&
11024 !(DAG.getMachineFunction()
11025 .getFunction()->getAttributes()
11026 .hasAttribute(AttributeSet::FunctionIndex,
11027 Attribute::NoImplicitFloat)) &&
11028 Subtarget->hasSSE1());
11031 // Insert VAARG_64 node into the DAG
11032 // VAARG_64 returns two values: Variable Argument Address, Chain
11033 SmallVector<SDValue, 11> InstOps;
11034 InstOps.push_back(Chain);
11035 InstOps.push_back(SrcPtr);
11036 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11037 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11038 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11039 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11040 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11041 VTs, &InstOps[0], InstOps.size(),
11043 MachinePointerInfo(SV),
11045 /*Volatile=*/false,
11047 /*WriteMem=*/true);
11048 Chain = VAARG.getValue(1);
11050 // Load the next argument and return it
11051 return DAG.getLoad(ArgVT, dl,
11054 MachinePointerInfo(),
11055 false, false, false, 0);
11058 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11059 SelectionDAG &DAG) {
11060 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11061 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11062 SDValue Chain = Op.getOperand(0);
11063 SDValue DstPtr = Op.getOperand(1);
11064 SDValue SrcPtr = Op.getOperand(2);
11065 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11066 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11069 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11070 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11072 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11075 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11076 // amount is a constant. Takes immediate version of shift as input.
11077 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
11078 SDValue SrcOp, uint64_t ShiftAmt,
11079 SelectionDAG &DAG) {
11081 // Check for ShiftAmt >= element width
11082 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
11083 if (Opc == X86ISD::VSRAI)
11084 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
11086 return DAG.getConstant(0, VT);
11089 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11090 && "Unknown target vector shift-by-constant node");
11092 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11095 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11096 // may or may not be a constant. Takes immediate version of shift as input.
11097 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
11098 SDValue SrcOp, SDValue ShAmt,
11099 SelectionDAG &DAG) {
11100 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11102 // Catch shift-by-constant.
11103 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11104 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11105 CShAmt->getZExtValue(), DAG);
11107 // Change opcode to non-immediate version
11109 default: llvm_unreachable("Unknown target vector shift node");
11110 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11111 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11112 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11115 // Need to build a vector containing shift amount
11116 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11119 ShOps[1] = DAG.getConstant(0, MVT::i32);
11120 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11121 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11123 // The return type has to be a 128-bit type with the same element
11124 // type as the input type.
11125 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11126 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11128 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11129 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11132 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11134 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11136 default: return SDValue(); // Don't custom lower most intrinsics.
11137 // Comparison intrinsics.
11138 case Intrinsic::x86_sse_comieq_ss:
11139 case Intrinsic::x86_sse_comilt_ss:
11140 case Intrinsic::x86_sse_comile_ss:
11141 case Intrinsic::x86_sse_comigt_ss:
11142 case Intrinsic::x86_sse_comige_ss:
11143 case Intrinsic::x86_sse_comineq_ss:
11144 case Intrinsic::x86_sse_ucomieq_ss:
11145 case Intrinsic::x86_sse_ucomilt_ss:
11146 case Intrinsic::x86_sse_ucomile_ss:
11147 case Intrinsic::x86_sse_ucomigt_ss:
11148 case Intrinsic::x86_sse_ucomige_ss:
11149 case Intrinsic::x86_sse_ucomineq_ss:
11150 case Intrinsic::x86_sse2_comieq_sd:
11151 case Intrinsic::x86_sse2_comilt_sd:
11152 case Intrinsic::x86_sse2_comile_sd:
11153 case Intrinsic::x86_sse2_comigt_sd:
11154 case Intrinsic::x86_sse2_comige_sd:
11155 case Intrinsic::x86_sse2_comineq_sd:
11156 case Intrinsic::x86_sse2_ucomieq_sd:
11157 case Intrinsic::x86_sse2_ucomilt_sd:
11158 case Intrinsic::x86_sse2_ucomile_sd:
11159 case Intrinsic::x86_sse2_ucomigt_sd:
11160 case Intrinsic::x86_sse2_ucomige_sd:
11161 case Intrinsic::x86_sse2_ucomineq_sd: {
11165 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11166 case Intrinsic::x86_sse_comieq_ss:
11167 case Intrinsic::x86_sse2_comieq_sd:
11168 Opc = X86ISD::COMI;
11171 case Intrinsic::x86_sse_comilt_ss:
11172 case Intrinsic::x86_sse2_comilt_sd:
11173 Opc = X86ISD::COMI;
11176 case Intrinsic::x86_sse_comile_ss:
11177 case Intrinsic::x86_sse2_comile_sd:
11178 Opc = X86ISD::COMI;
11181 case Intrinsic::x86_sse_comigt_ss:
11182 case Intrinsic::x86_sse2_comigt_sd:
11183 Opc = X86ISD::COMI;
11186 case Intrinsic::x86_sse_comige_ss:
11187 case Intrinsic::x86_sse2_comige_sd:
11188 Opc = X86ISD::COMI;
11191 case Intrinsic::x86_sse_comineq_ss:
11192 case Intrinsic::x86_sse2_comineq_sd:
11193 Opc = X86ISD::COMI;
11196 case Intrinsic::x86_sse_ucomieq_ss:
11197 case Intrinsic::x86_sse2_ucomieq_sd:
11198 Opc = X86ISD::UCOMI;
11201 case Intrinsic::x86_sse_ucomilt_ss:
11202 case Intrinsic::x86_sse2_ucomilt_sd:
11203 Opc = X86ISD::UCOMI;
11206 case Intrinsic::x86_sse_ucomile_ss:
11207 case Intrinsic::x86_sse2_ucomile_sd:
11208 Opc = X86ISD::UCOMI;
11211 case Intrinsic::x86_sse_ucomigt_ss:
11212 case Intrinsic::x86_sse2_ucomigt_sd:
11213 Opc = X86ISD::UCOMI;
11216 case Intrinsic::x86_sse_ucomige_ss:
11217 case Intrinsic::x86_sse2_ucomige_sd:
11218 Opc = X86ISD::UCOMI;
11221 case Intrinsic::x86_sse_ucomineq_ss:
11222 case Intrinsic::x86_sse2_ucomineq_sd:
11223 Opc = X86ISD::UCOMI;
11228 SDValue LHS = Op.getOperand(1);
11229 SDValue RHS = Op.getOperand(2);
11230 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11231 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11232 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11233 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11234 DAG.getConstant(X86CC, MVT::i8), Cond);
11235 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11238 // Arithmetic intrinsics.
11239 case Intrinsic::x86_sse2_pmulu_dq:
11240 case Intrinsic::x86_avx2_pmulu_dq:
11241 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11242 Op.getOperand(1), Op.getOperand(2));
11244 // SSE2/AVX2 sub with unsigned saturation intrinsics
11245 case Intrinsic::x86_sse2_psubus_b:
11246 case Intrinsic::x86_sse2_psubus_w:
11247 case Intrinsic::x86_avx2_psubus_b:
11248 case Intrinsic::x86_avx2_psubus_w:
11249 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11250 Op.getOperand(1), Op.getOperand(2));
11252 // SSE3/AVX horizontal add/sub intrinsics
11253 case Intrinsic::x86_sse3_hadd_ps:
11254 case Intrinsic::x86_sse3_hadd_pd:
11255 case Intrinsic::x86_avx_hadd_ps_256:
11256 case Intrinsic::x86_avx_hadd_pd_256:
11257 case Intrinsic::x86_sse3_hsub_ps:
11258 case Intrinsic::x86_sse3_hsub_pd:
11259 case Intrinsic::x86_avx_hsub_ps_256:
11260 case Intrinsic::x86_avx_hsub_pd_256:
11261 case Intrinsic::x86_ssse3_phadd_w_128:
11262 case Intrinsic::x86_ssse3_phadd_d_128:
11263 case Intrinsic::x86_avx2_phadd_w:
11264 case Intrinsic::x86_avx2_phadd_d:
11265 case Intrinsic::x86_ssse3_phsub_w_128:
11266 case Intrinsic::x86_ssse3_phsub_d_128:
11267 case Intrinsic::x86_avx2_phsub_w:
11268 case Intrinsic::x86_avx2_phsub_d: {
11271 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11272 case Intrinsic::x86_sse3_hadd_ps:
11273 case Intrinsic::x86_sse3_hadd_pd:
11274 case Intrinsic::x86_avx_hadd_ps_256:
11275 case Intrinsic::x86_avx_hadd_pd_256:
11276 Opcode = X86ISD::FHADD;
11278 case Intrinsic::x86_sse3_hsub_ps:
11279 case Intrinsic::x86_sse3_hsub_pd:
11280 case Intrinsic::x86_avx_hsub_ps_256:
11281 case Intrinsic::x86_avx_hsub_pd_256:
11282 Opcode = X86ISD::FHSUB;
11284 case Intrinsic::x86_ssse3_phadd_w_128:
11285 case Intrinsic::x86_ssse3_phadd_d_128:
11286 case Intrinsic::x86_avx2_phadd_w:
11287 case Intrinsic::x86_avx2_phadd_d:
11288 Opcode = X86ISD::HADD;
11290 case Intrinsic::x86_ssse3_phsub_w_128:
11291 case Intrinsic::x86_ssse3_phsub_d_128:
11292 case Intrinsic::x86_avx2_phsub_w:
11293 case Intrinsic::x86_avx2_phsub_d:
11294 Opcode = X86ISD::HSUB;
11297 return DAG.getNode(Opcode, dl, Op.getValueType(),
11298 Op.getOperand(1), Op.getOperand(2));
11301 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11302 case Intrinsic::x86_sse2_pmaxu_b:
11303 case Intrinsic::x86_sse41_pmaxuw:
11304 case Intrinsic::x86_sse41_pmaxud:
11305 case Intrinsic::x86_avx2_pmaxu_b:
11306 case Intrinsic::x86_avx2_pmaxu_w:
11307 case Intrinsic::x86_avx2_pmaxu_d:
11308 case Intrinsic::x86_avx512_pmaxu_d:
11309 case Intrinsic::x86_avx512_pmaxu_q:
11310 case Intrinsic::x86_sse2_pminu_b:
11311 case Intrinsic::x86_sse41_pminuw:
11312 case Intrinsic::x86_sse41_pminud:
11313 case Intrinsic::x86_avx2_pminu_b:
11314 case Intrinsic::x86_avx2_pminu_w:
11315 case Intrinsic::x86_avx2_pminu_d:
11316 case Intrinsic::x86_avx512_pminu_d:
11317 case Intrinsic::x86_avx512_pminu_q:
11318 case Intrinsic::x86_sse41_pmaxsb:
11319 case Intrinsic::x86_sse2_pmaxs_w:
11320 case Intrinsic::x86_sse41_pmaxsd:
11321 case Intrinsic::x86_avx2_pmaxs_b:
11322 case Intrinsic::x86_avx2_pmaxs_w:
11323 case Intrinsic::x86_avx2_pmaxs_d:
11324 case Intrinsic::x86_avx512_pmaxs_d:
11325 case Intrinsic::x86_avx512_pmaxs_q:
11326 case Intrinsic::x86_sse41_pminsb:
11327 case Intrinsic::x86_sse2_pmins_w:
11328 case Intrinsic::x86_sse41_pminsd:
11329 case Intrinsic::x86_avx2_pmins_b:
11330 case Intrinsic::x86_avx2_pmins_w:
11331 case Intrinsic::x86_avx2_pmins_d:
11332 case Intrinsic::x86_avx512_pmins_d:
11333 case Intrinsic::x86_avx512_pmins_q: {
11336 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11337 case Intrinsic::x86_sse2_pmaxu_b:
11338 case Intrinsic::x86_sse41_pmaxuw:
11339 case Intrinsic::x86_sse41_pmaxud:
11340 case Intrinsic::x86_avx2_pmaxu_b:
11341 case Intrinsic::x86_avx2_pmaxu_w:
11342 case Intrinsic::x86_avx2_pmaxu_d:
11343 case Intrinsic::x86_avx512_pmaxu_d:
11344 case Intrinsic::x86_avx512_pmaxu_q:
11345 Opcode = X86ISD::UMAX;
11347 case Intrinsic::x86_sse2_pminu_b:
11348 case Intrinsic::x86_sse41_pminuw:
11349 case Intrinsic::x86_sse41_pminud:
11350 case Intrinsic::x86_avx2_pminu_b:
11351 case Intrinsic::x86_avx2_pminu_w:
11352 case Intrinsic::x86_avx2_pminu_d:
11353 case Intrinsic::x86_avx512_pminu_d:
11354 case Intrinsic::x86_avx512_pminu_q:
11355 Opcode = X86ISD::UMIN;
11357 case Intrinsic::x86_sse41_pmaxsb:
11358 case Intrinsic::x86_sse2_pmaxs_w:
11359 case Intrinsic::x86_sse41_pmaxsd:
11360 case Intrinsic::x86_avx2_pmaxs_b:
11361 case Intrinsic::x86_avx2_pmaxs_w:
11362 case Intrinsic::x86_avx2_pmaxs_d:
11363 case Intrinsic::x86_avx512_pmaxs_d:
11364 case Intrinsic::x86_avx512_pmaxs_q:
11365 Opcode = X86ISD::SMAX;
11367 case Intrinsic::x86_sse41_pminsb:
11368 case Intrinsic::x86_sse2_pmins_w:
11369 case Intrinsic::x86_sse41_pminsd:
11370 case Intrinsic::x86_avx2_pmins_b:
11371 case Intrinsic::x86_avx2_pmins_w:
11372 case Intrinsic::x86_avx2_pmins_d:
11373 case Intrinsic::x86_avx512_pmins_d:
11374 case Intrinsic::x86_avx512_pmins_q:
11375 Opcode = X86ISD::SMIN;
11378 return DAG.getNode(Opcode, dl, Op.getValueType(),
11379 Op.getOperand(1), Op.getOperand(2));
11382 // SSE/SSE2/AVX floating point max/min intrinsics.
11383 case Intrinsic::x86_sse_max_ps:
11384 case Intrinsic::x86_sse2_max_pd:
11385 case Intrinsic::x86_avx_max_ps_256:
11386 case Intrinsic::x86_avx_max_pd_256:
11387 case Intrinsic::x86_avx512_max_ps_512:
11388 case Intrinsic::x86_avx512_max_pd_512:
11389 case Intrinsic::x86_sse_min_ps:
11390 case Intrinsic::x86_sse2_min_pd:
11391 case Intrinsic::x86_avx_min_ps_256:
11392 case Intrinsic::x86_avx_min_pd_256:
11393 case Intrinsic::x86_avx512_min_ps_512:
11394 case Intrinsic::x86_avx512_min_pd_512: {
11397 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11398 case Intrinsic::x86_sse_max_ps:
11399 case Intrinsic::x86_sse2_max_pd:
11400 case Intrinsic::x86_avx_max_ps_256:
11401 case Intrinsic::x86_avx_max_pd_256:
11402 case Intrinsic::x86_avx512_max_ps_512:
11403 case Intrinsic::x86_avx512_max_pd_512:
11404 Opcode = X86ISD::FMAX;
11406 case Intrinsic::x86_sse_min_ps:
11407 case Intrinsic::x86_sse2_min_pd:
11408 case Intrinsic::x86_avx_min_ps_256:
11409 case Intrinsic::x86_avx_min_pd_256:
11410 case Intrinsic::x86_avx512_min_ps_512:
11411 case Intrinsic::x86_avx512_min_pd_512:
11412 Opcode = X86ISD::FMIN;
11415 return DAG.getNode(Opcode, dl, Op.getValueType(),
11416 Op.getOperand(1), Op.getOperand(2));
11419 // AVX2 variable shift intrinsics
11420 case Intrinsic::x86_avx2_psllv_d:
11421 case Intrinsic::x86_avx2_psllv_q:
11422 case Intrinsic::x86_avx2_psllv_d_256:
11423 case Intrinsic::x86_avx2_psllv_q_256:
11424 case Intrinsic::x86_avx2_psrlv_d:
11425 case Intrinsic::x86_avx2_psrlv_q:
11426 case Intrinsic::x86_avx2_psrlv_d_256:
11427 case Intrinsic::x86_avx2_psrlv_q_256:
11428 case Intrinsic::x86_avx2_psrav_d:
11429 case Intrinsic::x86_avx2_psrav_d_256: {
11432 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11433 case Intrinsic::x86_avx2_psllv_d:
11434 case Intrinsic::x86_avx2_psllv_q:
11435 case Intrinsic::x86_avx2_psllv_d_256:
11436 case Intrinsic::x86_avx2_psllv_q_256:
11439 case Intrinsic::x86_avx2_psrlv_d:
11440 case Intrinsic::x86_avx2_psrlv_q:
11441 case Intrinsic::x86_avx2_psrlv_d_256:
11442 case Intrinsic::x86_avx2_psrlv_q_256:
11445 case Intrinsic::x86_avx2_psrav_d:
11446 case Intrinsic::x86_avx2_psrav_d_256:
11450 return DAG.getNode(Opcode, dl, Op.getValueType(),
11451 Op.getOperand(1), Op.getOperand(2));
11454 case Intrinsic::x86_ssse3_pshuf_b_128:
11455 case Intrinsic::x86_avx2_pshuf_b:
11456 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11457 Op.getOperand(1), Op.getOperand(2));
11459 case Intrinsic::x86_ssse3_psign_b_128:
11460 case Intrinsic::x86_ssse3_psign_w_128:
11461 case Intrinsic::x86_ssse3_psign_d_128:
11462 case Intrinsic::x86_avx2_psign_b:
11463 case Intrinsic::x86_avx2_psign_w:
11464 case Intrinsic::x86_avx2_psign_d:
11465 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11466 Op.getOperand(1), Op.getOperand(2));
11468 case Intrinsic::x86_sse41_insertps:
11469 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11470 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11472 case Intrinsic::x86_avx_vperm2f128_ps_256:
11473 case Intrinsic::x86_avx_vperm2f128_pd_256:
11474 case Intrinsic::x86_avx_vperm2f128_si_256:
11475 case Intrinsic::x86_avx2_vperm2i128:
11476 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11477 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11479 case Intrinsic::x86_avx2_permd:
11480 case Intrinsic::x86_avx2_permps:
11481 // Operands intentionally swapped. Mask is last operand to intrinsic,
11482 // but second operand for node/instruction.
11483 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11484 Op.getOperand(2), Op.getOperand(1));
11486 case Intrinsic::x86_sse_sqrt_ps:
11487 case Intrinsic::x86_sse2_sqrt_pd:
11488 case Intrinsic::x86_avx_sqrt_ps_256:
11489 case Intrinsic::x86_avx_sqrt_pd_256:
11490 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11492 // ptest and testp intrinsics. The intrinsic these come from are designed to
11493 // return an integer value, not just an instruction so lower it to the ptest
11494 // or testp pattern and a setcc for the result.
11495 case Intrinsic::x86_sse41_ptestz:
11496 case Intrinsic::x86_sse41_ptestc:
11497 case Intrinsic::x86_sse41_ptestnzc:
11498 case Intrinsic::x86_avx_ptestz_256:
11499 case Intrinsic::x86_avx_ptestc_256:
11500 case Intrinsic::x86_avx_ptestnzc_256:
11501 case Intrinsic::x86_avx_vtestz_ps:
11502 case Intrinsic::x86_avx_vtestc_ps:
11503 case Intrinsic::x86_avx_vtestnzc_ps:
11504 case Intrinsic::x86_avx_vtestz_pd:
11505 case Intrinsic::x86_avx_vtestc_pd:
11506 case Intrinsic::x86_avx_vtestnzc_pd:
11507 case Intrinsic::x86_avx_vtestz_ps_256:
11508 case Intrinsic::x86_avx_vtestc_ps_256:
11509 case Intrinsic::x86_avx_vtestnzc_ps_256:
11510 case Intrinsic::x86_avx_vtestz_pd_256:
11511 case Intrinsic::x86_avx_vtestc_pd_256:
11512 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11513 bool IsTestPacked = false;
11516 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11517 case Intrinsic::x86_avx_vtestz_ps:
11518 case Intrinsic::x86_avx_vtestz_pd:
11519 case Intrinsic::x86_avx_vtestz_ps_256:
11520 case Intrinsic::x86_avx_vtestz_pd_256:
11521 IsTestPacked = true; // Fallthrough
11522 case Intrinsic::x86_sse41_ptestz:
11523 case Intrinsic::x86_avx_ptestz_256:
11525 X86CC = X86::COND_E;
11527 case Intrinsic::x86_avx_vtestc_ps:
11528 case Intrinsic::x86_avx_vtestc_pd:
11529 case Intrinsic::x86_avx_vtestc_ps_256:
11530 case Intrinsic::x86_avx_vtestc_pd_256:
11531 IsTestPacked = true; // Fallthrough
11532 case Intrinsic::x86_sse41_ptestc:
11533 case Intrinsic::x86_avx_ptestc_256:
11535 X86CC = X86::COND_B;
11537 case Intrinsic::x86_avx_vtestnzc_ps:
11538 case Intrinsic::x86_avx_vtestnzc_pd:
11539 case Intrinsic::x86_avx_vtestnzc_ps_256:
11540 case Intrinsic::x86_avx_vtestnzc_pd_256:
11541 IsTestPacked = true; // Fallthrough
11542 case Intrinsic::x86_sse41_ptestnzc:
11543 case Intrinsic::x86_avx_ptestnzc_256:
11545 X86CC = X86::COND_A;
11549 SDValue LHS = Op.getOperand(1);
11550 SDValue RHS = Op.getOperand(2);
11551 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11552 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11553 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11554 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11555 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11557 case Intrinsic::x86_avx512_kortestz_w:
11558 case Intrinsic::x86_avx512_kortestc_w: {
11559 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11560 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11561 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11562 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11563 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11564 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11565 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11568 // SSE/AVX shift intrinsics
11569 case Intrinsic::x86_sse2_psll_w:
11570 case Intrinsic::x86_sse2_psll_d:
11571 case Intrinsic::x86_sse2_psll_q:
11572 case Intrinsic::x86_avx2_psll_w:
11573 case Intrinsic::x86_avx2_psll_d:
11574 case Intrinsic::x86_avx2_psll_q:
11575 case Intrinsic::x86_sse2_psrl_w:
11576 case Intrinsic::x86_sse2_psrl_d:
11577 case Intrinsic::x86_sse2_psrl_q:
11578 case Intrinsic::x86_avx2_psrl_w:
11579 case Intrinsic::x86_avx2_psrl_d:
11580 case Intrinsic::x86_avx2_psrl_q:
11581 case Intrinsic::x86_sse2_psra_w:
11582 case Intrinsic::x86_sse2_psra_d:
11583 case Intrinsic::x86_avx2_psra_w:
11584 case Intrinsic::x86_avx2_psra_d: {
11587 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11588 case Intrinsic::x86_sse2_psll_w:
11589 case Intrinsic::x86_sse2_psll_d:
11590 case Intrinsic::x86_sse2_psll_q:
11591 case Intrinsic::x86_avx2_psll_w:
11592 case Intrinsic::x86_avx2_psll_d:
11593 case Intrinsic::x86_avx2_psll_q:
11594 Opcode = X86ISD::VSHL;
11596 case Intrinsic::x86_sse2_psrl_w:
11597 case Intrinsic::x86_sse2_psrl_d:
11598 case Intrinsic::x86_sse2_psrl_q:
11599 case Intrinsic::x86_avx2_psrl_w:
11600 case Intrinsic::x86_avx2_psrl_d:
11601 case Intrinsic::x86_avx2_psrl_q:
11602 Opcode = X86ISD::VSRL;
11604 case Intrinsic::x86_sse2_psra_w:
11605 case Intrinsic::x86_sse2_psra_d:
11606 case Intrinsic::x86_avx2_psra_w:
11607 case Intrinsic::x86_avx2_psra_d:
11608 Opcode = X86ISD::VSRA;
11611 return DAG.getNode(Opcode, dl, Op.getValueType(),
11612 Op.getOperand(1), Op.getOperand(2));
11615 // SSE/AVX immediate shift intrinsics
11616 case Intrinsic::x86_sse2_pslli_w:
11617 case Intrinsic::x86_sse2_pslli_d:
11618 case Intrinsic::x86_sse2_pslli_q:
11619 case Intrinsic::x86_avx2_pslli_w:
11620 case Intrinsic::x86_avx2_pslli_d:
11621 case Intrinsic::x86_avx2_pslli_q:
11622 case Intrinsic::x86_sse2_psrli_w:
11623 case Intrinsic::x86_sse2_psrli_d:
11624 case Intrinsic::x86_sse2_psrli_q:
11625 case Intrinsic::x86_avx2_psrli_w:
11626 case Intrinsic::x86_avx2_psrli_d:
11627 case Intrinsic::x86_avx2_psrli_q:
11628 case Intrinsic::x86_sse2_psrai_w:
11629 case Intrinsic::x86_sse2_psrai_d:
11630 case Intrinsic::x86_avx2_psrai_w:
11631 case Intrinsic::x86_avx2_psrai_d: {
11634 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11635 case Intrinsic::x86_sse2_pslli_w:
11636 case Intrinsic::x86_sse2_pslli_d:
11637 case Intrinsic::x86_sse2_pslli_q:
11638 case Intrinsic::x86_avx2_pslli_w:
11639 case Intrinsic::x86_avx2_pslli_d:
11640 case Intrinsic::x86_avx2_pslli_q:
11641 Opcode = X86ISD::VSHLI;
11643 case Intrinsic::x86_sse2_psrli_w:
11644 case Intrinsic::x86_sse2_psrli_d:
11645 case Intrinsic::x86_sse2_psrli_q:
11646 case Intrinsic::x86_avx2_psrli_w:
11647 case Intrinsic::x86_avx2_psrli_d:
11648 case Intrinsic::x86_avx2_psrli_q:
11649 Opcode = X86ISD::VSRLI;
11651 case Intrinsic::x86_sse2_psrai_w:
11652 case Intrinsic::x86_sse2_psrai_d:
11653 case Intrinsic::x86_avx2_psrai_w:
11654 case Intrinsic::x86_avx2_psrai_d:
11655 Opcode = X86ISD::VSRAI;
11658 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11659 Op.getOperand(1), Op.getOperand(2), DAG);
11662 case Intrinsic::x86_sse42_pcmpistria128:
11663 case Intrinsic::x86_sse42_pcmpestria128:
11664 case Intrinsic::x86_sse42_pcmpistric128:
11665 case Intrinsic::x86_sse42_pcmpestric128:
11666 case Intrinsic::x86_sse42_pcmpistrio128:
11667 case Intrinsic::x86_sse42_pcmpestrio128:
11668 case Intrinsic::x86_sse42_pcmpistris128:
11669 case Intrinsic::x86_sse42_pcmpestris128:
11670 case Intrinsic::x86_sse42_pcmpistriz128:
11671 case Intrinsic::x86_sse42_pcmpestriz128: {
11675 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11676 case Intrinsic::x86_sse42_pcmpistria128:
11677 Opcode = X86ISD::PCMPISTRI;
11678 X86CC = X86::COND_A;
11680 case Intrinsic::x86_sse42_pcmpestria128:
11681 Opcode = X86ISD::PCMPESTRI;
11682 X86CC = X86::COND_A;
11684 case Intrinsic::x86_sse42_pcmpistric128:
11685 Opcode = X86ISD::PCMPISTRI;
11686 X86CC = X86::COND_B;
11688 case Intrinsic::x86_sse42_pcmpestric128:
11689 Opcode = X86ISD::PCMPESTRI;
11690 X86CC = X86::COND_B;
11692 case Intrinsic::x86_sse42_pcmpistrio128:
11693 Opcode = X86ISD::PCMPISTRI;
11694 X86CC = X86::COND_O;
11696 case Intrinsic::x86_sse42_pcmpestrio128:
11697 Opcode = X86ISD::PCMPESTRI;
11698 X86CC = X86::COND_O;
11700 case Intrinsic::x86_sse42_pcmpistris128:
11701 Opcode = X86ISD::PCMPISTRI;
11702 X86CC = X86::COND_S;
11704 case Intrinsic::x86_sse42_pcmpestris128:
11705 Opcode = X86ISD::PCMPESTRI;
11706 X86CC = X86::COND_S;
11708 case Intrinsic::x86_sse42_pcmpistriz128:
11709 Opcode = X86ISD::PCMPISTRI;
11710 X86CC = X86::COND_E;
11712 case Intrinsic::x86_sse42_pcmpestriz128:
11713 Opcode = X86ISD::PCMPESTRI;
11714 X86CC = X86::COND_E;
11717 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11718 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11719 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11720 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11721 DAG.getConstant(X86CC, MVT::i8),
11722 SDValue(PCMP.getNode(), 1));
11723 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11726 case Intrinsic::x86_sse42_pcmpistri128:
11727 case Intrinsic::x86_sse42_pcmpestri128: {
11729 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11730 Opcode = X86ISD::PCMPISTRI;
11732 Opcode = X86ISD::PCMPESTRI;
11734 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11735 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11736 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11738 case Intrinsic::x86_fma_vfmadd_ps:
11739 case Intrinsic::x86_fma_vfmadd_pd:
11740 case Intrinsic::x86_fma_vfmsub_ps:
11741 case Intrinsic::x86_fma_vfmsub_pd:
11742 case Intrinsic::x86_fma_vfnmadd_ps:
11743 case Intrinsic::x86_fma_vfnmadd_pd:
11744 case Intrinsic::x86_fma_vfnmsub_ps:
11745 case Intrinsic::x86_fma_vfnmsub_pd:
11746 case Intrinsic::x86_fma_vfmaddsub_ps:
11747 case Intrinsic::x86_fma_vfmaddsub_pd:
11748 case Intrinsic::x86_fma_vfmsubadd_ps:
11749 case Intrinsic::x86_fma_vfmsubadd_pd:
11750 case Intrinsic::x86_fma_vfmadd_ps_256:
11751 case Intrinsic::x86_fma_vfmadd_pd_256:
11752 case Intrinsic::x86_fma_vfmsub_ps_256:
11753 case Intrinsic::x86_fma_vfmsub_pd_256:
11754 case Intrinsic::x86_fma_vfnmadd_ps_256:
11755 case Intrinsic::x86_fma_vfnmadd_pd_256:
11756 case Intrinsic::x86_fma_vfnmsub_ps_256:
11757 case Intrinsic::x86_fma_vfnmsub_pd_256:
11758 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11759 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11760 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11761 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11762 case Intrinsic::x86_fma_vfmadd_ps_512:
11763 case Intrinsic::x86_fma_vfmadd_pd_512:
11764 case Intrinsic::x86_fma_vfmsub_ps_512:
11765 case Intrinsic::x86_fma_vfmsub_pd_512:
11766 case Intrinsic::x86_fma_vfnmadd_ps_512:
11767 case Intrinsic::x86_fma_vfnmadd_pd_512:
11768 case Intrinsic::x86_fma_vfnmsub_ps_512:
11769 case Intrinsic::x86_fma_vfnmsub_pd_512:
11770 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11771 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11772 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11773 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11776 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11777 case Intrinsic::x86_fma_vfmadd_ps:
11778 case Intrinsic::x86_fma_vfmadd_pd:
11779 case Intrinsic::x86_fma_vfmadd_ps_256:
11780 case Intrinsic::x86_fma_vfmadd_pd_256:
11781 case Intrinsic::x86_fma_vfmadd_ps_512:
11782 case Intrinsic::x86_fma_vfmadd_pd_512:
11783 Opc = X86ISD::FMADD;
11785 case Intrinsic::x86_fma_vfmsub_ps:
11786 case Intrinsic::x86_fma_vfmsub_pd:
11787 case Intrinsic::x86_fma_vfmsub_ps_256:
11788 case Intrinsic::x86_fma_vfmsub_pd_256:
11789 case Intrinsic::x86_fma_vfmsub_ps_512:
11790 case Intrinsic::x86_fma_vfmsub_pd_512:
11791 Opc = X86ISD::FMSUB;
11793 case Intrinsic::x86_fma_vfnmadd_ps:
11794 case Intrinsic::x86_fma_vfnmadd_pd:
11795 case Intrinsic::x86_fma_vfnmadd_ps_256:
11796 case Intrinsic::x86_fma_vfnmadd_pd_256:
11797 case Intrinsic::x86_fma_vfnmadd_ps_512:
11798 case Intrinsic::x86_fma_vfnmadd_pd_512:
11799 Opc = X86ISD::FNMADD;
11801 case Intrinsic::x86_fma_vfnmsub_ps:
11802 case Intrinsic::x86_fma_vfnmsub_pd:
11803 case Intrinsic::x86_fma_vfnmsub_ps_256:
11804 case Intrinsic::x86_fma_vfnmsub_pd_256:
11805 case Intrinsic::x86_fma_vfnmsub_ps_512:
11806 case Intrinsic::x86_fma_vfnmsub_pd_512:
11807 Opc = X86ISD::FNMSUB;
11809 case Intrinsic::x86_fma_vfmaddsub_ps:
11810 case Intrinsic::x86_fma_vfmaddsub_pd:
11811 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11812 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11813 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11814 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11815 Opc = X86ISD::FMADDSUB;
11817 case Intrinsic::x86_fma_vfmsubadd_ps:
11818 case Intrinsic::x86_fma_vfmsubadd_pd:
11819 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11820 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11821 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11822 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11823 Opc = X86ISD::FMSUBADD;
11827 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11828 Op.getOperand(2), Op.getOperand(3));
11833 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11834 SDValue Base, SDValue Index,
11835 SDValue ScaleOp, SDValue Chain,
11836 const X86Subtarget * Subtarget) {
11838 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11839 assert(C && "Invalid scale type");
11840 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11841 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11842 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11843 Index.getValueType().getVectorNumElements());
11844 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11845 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11846 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11847 SDValue Segment = DAG.getRegister(0, MVT::i32);
11848 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11849 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11850 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11851 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11854 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11855 SDValue Src, SDValue Mask, SDValue Base,
11856 SDValue Index, SDValue ScaleOp, SDValue Chain,
11857 const X86Subtarget * Subtarget) {
11859 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11860 assert(C && "Invalid scale type");
11861 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11862 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11863 Index.getValueType().getVectorNumElements());
11864 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11865 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11866 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11867 SDValue Segment = DAG.getRegister(0, MVT::i32);
11868 if (Src.getOpcode() == ISD::UNDEF)
11869 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11870 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11871 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11872 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11873 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11876 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11877 SDValue Src, SDValue Base, SDValue Index,
11878 SDValue ScaleOp, SDValue Chain) {
11880 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11881 assert(C && "Invalid scale type");
11882 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11883 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11884 SDValue Segment = DAG.getRegister(0, MVT::i32);
11885 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11886 Index.getValueType().getVectorNumElements());
11887 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11888 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11889 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11890 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11891 return SDValue(Res, 1);
11894 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11895 SDValue Src, SDValue Mask, SDValue Base,
11896 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11898 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11899 assert(C && "Invalid scale type");
11900 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11901 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11902 SDValue Segment = DAG.getRegister(0, MVT::i32);
11903 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11904 Index.getValueType().getVectorNumElements());
11905 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11906 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11907 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11908 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11909 return SDValue(Res, 1);
11912 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11913 SelectionDAG &DAG) {
11915 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11917 default: return SDValue(); // Don't custom lower most intrinsics.
11919 // RDRAND/RDSEED intrinsics.
11920 case Intrinsic::x86_rdrand_16:
11921 case Intrinsic::x86_rdrand_32:
11922 case Intrinsic::x86_rdrand_64:
11923 case Intrinsic::x86_rdseed_16:
11924 case Intrinsic::x86_rdseed_32:
11925 case Intrinsic::x86_rdseed_64: {
11926 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11927 IntNo == Intrinsic::x86_rdseed_32 ||
11928 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11930 // Emit the node with the right value type.
11931 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11932 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11934 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11935 // Otherwise return the value from Rand, which is always 0, casted to i32.
11936 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11937 DAG.getConstant(1, Op->getValueType(1)),
11938 DAG.getConstant(X86::COND_B, MVT::i32),
11939 SDValue(Result.getNode(), 1) };
11940 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11941 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11942 Ops, array_lengthof(Ops));
11944 // Return { result, isValid, chain }.
11945 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11946 SDValue(Result.getNode(), 2));
11948 //int_gather(index, base, scale);
11949 case Intrinsic::x86_avx512_gather_qpd_512:
11950 case Intrinsic::x86_avx512_gather_qps_512:
11951 case Intrinsic::x86_avx512_gather_dpd_512:
11952 case Intrinsic::x86_avx512_gather_qpi_512:
11953 case Intrinsic::x86_avx512_gather_qpq_512:
11954 case Intrinsic::x86_avx512_gather_dpq_512:
11955 case Intrinsic::x86_avx512_gather_dps_512:
11956 case Intrinsic::x86_avx512_gather_dpi_512: {
11959 default: llvm_unreachable("Unexpected intrinsic!");
11960 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11961 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11962 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11963 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11964 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11965 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11966 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11967 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11969 SDValue Chain = Op.getOperand(0);
11970 SDValue Index = Op.getOperand(2);
11971 SDValue Base = Op.getOperand(3);
11972 SDValue Scale = Op.getOperand(4);
11973 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11975 //int_gather_mask(v1, mask, index, base, scale);
11976 case Intrinsic::x86_avx512_gather_qps_mask_512:
11977 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11978 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11979 case Intrinsic::x86_avx512_gather_dps_mask_512:
11980 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11981 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11982 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11983 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11986 default: llvm_unreachable("Unexpected intrinsic!");
11987 case Intrinsic::x86_avx512_gather_qps_mask_512:
11988 Opc = X86::VGATHERQPSZrm; break;
11989 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11990 Opc = X86::VGATHERQPDZrm; break;
11991 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11992 Opc = X86::VGATHERDPDZrm; break;
11993 case Intrinsic::x86_avx512_gather_dps_mask_512:
11994 Opc = X86::VGATHERDPSZrm; break;
11995 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11996 Opc = X86::VPGATHERQDZrm; break;
11997 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11998 Opc = X86::VPGATHERQQZrm; break;
11999 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12000 Opc = X86::VPGATHERDDZrm; break;
12001 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12002 Opc = X86::VPGATHERDQZrm; break;
12004 SDValue Chain = Op.getOperand(0);
12005 SDValue Src = Op.getOperand(2);
12006 SDValue Mask = Op.getOperand(3);
12007 SDValue Index = Op.getOperand(4);
12008 SDValue Base = Op.getOperand(5);
12009 SDValue Scale = Op.getOperand(6);
12010 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12013 //int_scatter(base, index, v1, scale);
12014 case Intrinsic::x86_avx512_scatter_qpd_512:
12015 case Intrinsic::x86_avx512_scatter_qps_512:
12016 case Intrinsic::x86_avx512_scatter_dpd_512:
12017 case Intrinsic::x86_avx512_scatter_qpi_512:
12018 case Intrinsic::x86_avx512_scatter_qpq_512:
12019 case Intrinsic::x86_avx512_scatter_dpq_512:
12020 case Intrinsic::x86_avx512_scatter_dps_512:
12021 case Intrinsic::x86_avx512_scatter_dpi_512: {
12024 default: llvm_unreachable("Unexpected intrinsic!");
12025 case Intrinsic::x86_avx512_scatter_qpd_512:
12026 Opc = X86::VSCATTERQPDZmr; break;
12027 case Intrinsic::x86_avx512_scatter_qps_512:
12028 Opc = X86::VSCATTERQPSZmr; break;
12029 case Intrinsic::x86_avx512_scatter_dpd_512:
12030 Opc = X86::VSCATTERDPDZmr; break;
12031 case Intrinsic::x86_avx512_scatter_dps_512:
12032 Opc = X86::VSCATTERDPSZmr; break;
12033 case Intrinsic::x86_avx512_scatter_qpi_512:
12034 Opc = X86::VPSCATTERQDZmr; break;
12035 case Intrinsic::x86_avx512_scatter_qpq_512:
12036 Opc = X86::VPSCATTERQQZmr; break;
12037 case Intrinsic::x86_avx512_scatter_dpq_512:
12038 Opc = X86::VPSCATTERDQZmr; break;
12039 case Intrinsic::x86_avx512_scatter_dpi_512:
12040 Opc = X86::VPSCATTERDDZmr; break;
12042 SDValue Chain = Op.getOperand(0);
12043 SDValue Base = Op.getOperand(2);
12044 SDValue Index = Op.getOperand(3);
12045 SDValue Src = Op.getOperand(4);
12046 SDValue Scale = Op.getOperand(5);
12047 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12049 //int_scatter_mask(base, mask, index, v1, scale);
12050 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12051 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12052 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12053 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12054 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12055 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12056 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12057 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12060 default: llvm_unreachable("Unexpected intrinsic!");
12061 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12062 Opc = X86::VSCATTERQPDZmr; break;
12063 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12064 Opc = X86::VSCATTERQPSZmr; break;
12065 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12066 Opc = X86::VSCATTERDPDZmr; break;
12067 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12068 Opc = X86::VSCATTERDPSZmr; break;
12069 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12070 Opc = X86::VPSCATTERQDZmr; break;
12071 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12072 Opc = X86::VPSCATTERQQZmr; break;
12073 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12074 Opc = X86::VPSCATTERDQZmr; break;
12075 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12076 Opc = X86::VPSCATTERDDZmr; break;
12078 SDValue Chain = Op.getOperand(0);
12079 SDValue Base = Op.getOperand(2);
12080 SDValue Mask = Op.getOperand(3);
12081 SDValue Index = Op.getOperand(4);
12082 SDValue Src = Op.getOperand(5);
12083 SDValue Scale = Op.getOperand(6);
12084 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12086 // XTEST intrinsics.
12087 case Intrinsic::x86_xtest: {
12088 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12089 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12090 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12091 DAG.getConstant(X86::COND_NE, MVT::i8),
12093 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12094 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12095 Ret, SDValue(InTrans.getNode(), 1));
12100 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12101 SelectionDAG &DAG) const {
12102 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12103 MFI->setReturnAddressIsTaken(true);
12105 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12107 EVT PtrVT = getPointerTy();
12110 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12111 const X86RegisterInfo *RegInfo =
12112 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12113 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12114 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12115 DAG.getNode(ISD::ADD, dl, PtrVT,
12116 FrameAddr, Offset),
12117 MachinePointerInfo(), false, false, false, 0);
12120 // Just load the return address.
12121 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12122 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12123 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12126 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12127 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12128 MFI->setFrameAddressIsTaken(true);
12130 EVT VT = Op.getValueType();
12131 SDLoc dl(Op); // FIXME probably not meaningful
12132 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12133 const X86RegisterInfo *RegInfo =
12134 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12135 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12136 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12137 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12138 "Invalid Frame Register!");
12139 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12141 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12142 MachinePointerInfo(),
12143 false, false, false, 0);
12147 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12148 SelectionDAG &DAG) const {
12149 const X86RegisterInfo *RegInfo =
12150 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12151 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12154 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12155 SDValue Chain = Op.getOperand(0);
12156 SDValue Offset = Op.getOperand(1);
12157 SDValue Handler = Op.getOperand(2);
12160 EVT PtrVT = getPointerTy();
12161 const X86RegisterInfo *RegInfo =
12162 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12163 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12164 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12165 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12166 "Invalid Frame Register!");
12167 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12168 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12170 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12171 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12172 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12173 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12175 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12177 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12178 DAG.getRegister(StoreAddrReg, PtrVT));
12181 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12182 SelectionDAG &DAG) const {
12184 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12185 DAG.getVTList(MVT::i32, MVT::Other),
12186 Op.getOperand(0), Op.getOperand(1));
12189 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12190 SelectionDAG &DAG) const {
12192 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12193 Op.getOperand(0), Op.getOperand(1));
12196 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12197 return Op.getOperand(0);
12200 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12201 SelectionDAG &DAG) const {
12202 SDValue Root = Op.getOperand(0);
12203 SDValue Trmp = Op.getOperand(1); // trampoline
12204 SDValue FPtr = Op.getOperand(2); // nested function
12205 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12208 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12209 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12211 if (Subtarget->is64Bit()) {
12212 SDValue OutChains[6];
12214 // Large code-model.
12215 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12216 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12218 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12219 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12221 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12223 // Load the pointer to the nested function into R11.
12224 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12225 SDValue Addr = Trmp;
12226 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12227 Addr, MachinePointerInfo(TrmpAddr),
12230 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12231 DAG.getConstant(2, MVT::i64));
12232 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12233 MachinePointerInfo(TrmpAddr, 2),
12236 // Load the 'nest' parameter value into R10.
12237 // R10 is specified in X86CallingConv.td
12238 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12239 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12240 DAG.getConstant(10, MVT::i64));
12241 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12242 Addr, MachinePointerInfo(TrmpAddr, 10),
12245 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12246 DAG.getConstant(12, MVT::i64));
12247 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12248 MachinePointerInfo(TrmpAddr, 12),
12251 // Jump to the nested function.
12252 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12253 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12254 DAG.getConstant(20, MVT::i64));
12255 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12256 Addr, MachinePointerInfo(TrmpAddr, 20),
12259 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12260 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12261 DAG.getConstant(22, MVT::i64));
12262 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12263 MachinePointerInfo(TrmpAddr, 22),
12266 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12268 const Function *Func =
12269 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12270 CallingConv::ID CC = Func->getCallingConv();
12275 llvm_unreachable("Unsupported calling convention");
12276 case CallingConv::C:
12277 case CallingConv::X86_StdCall: {
12278 // Pass 'nest' parameter in ECX.
12279 // Must be kept in sync with X86CallingConv.td
12280 NestReg = X86::ECX;
12282 // Check that ECX wasn't needed by an 'inreg' parameter.
12283 FunctionType *FTy = Func->getFunctionType();
12284 const AttributeSet &Attrs = Func->getAttributes();
12286 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12287 unsigned InRegCount = 0;
12290 for (FunctionType::param_iterator I = FTy->param_begin(),
12291 E = FTy->param_end(); I != E; ++I, ++Idx)
12292 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12293 // FIXME: should only count parameters that are lowered to integers.
12294 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12296 if (InRegCount > 2) {
12297 report_fatal_error("Nest register in use - reduce number of inreg"
12303 case CallingConv::X86_FastCall:
12304 case CallingConv::X86_ThisCall:
12305 case CallingConv::Fast:
12306 // Pass 'nest' parameter in EAX.
12307 // Must be kept in sync with X86CallingConv.td
12308 NestReg = X86::EAX;
12312 SDValue OutChains[4];
12313 SDValue Addr, Disp;
12315 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12316 DAG.getConstant(10, MVT::i32));
12317 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12319 // This is storing the opcode for MOV32ri.
12320 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12321 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12322 OutChains[0] = DAG.getStore(Root, dl,
12323 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12324 Trmp, MachinePointerInfo(TrmpAddr),
12327 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12328 DAG.getConstant(1, MVT::i32));
12329 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12330 MachinePointerInfo(TrmpAddr, 1),
12333 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12334 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12335 DAG.getConstant(5, MVT::i32));
12336 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12337 MachinePointerInfo(TrmpAddr, 5),
12340 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12341 DAG.getConstant(6, MVT::i32));
12342 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12343 MachinePointerInfo(TrmpAddr, 6),
12346 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12350 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12351 SelectionDAG &DAG) const {
12353 The rounding mode is in bits 11:10 of FPSR, and has the following
12355 00 Round to nearest
12360 FLT_ROUNDS, on the other hand, expects the following:
12367 To perform the conversion, we do:
12368 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12371 MachineFunction &MF = DAG.getMachineFunction();
12372 const TargetMachine &TM = MF.getTarget();
12373 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12374 unsigned StackAlignment = TFI.getStackAlignment();
12375 EVT VT = Op.getValueType();
12378 // Save FP Control Word to stack slot
12379 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12380 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12382 MachineMemOperand *MMO =
12383 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12384 MachineMemOperand::MOStore, 2, 2);
12386 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12387 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12388 DAG.getVTList(MVT::Other),
12389 Ops, array_lengthof(Ops), MVT::i16,
12392 // Load FP Control Word from stack slot
12393 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12394 MachinePointerInfo(), false, false, false, 0);
12396 // Transform as necessary
12398 DAG.getNode(ISD::SRL, DL, MVT::i16,
12399 DAG.getNode(ISD::AND, DL, MVT::i16,
12400 CWD, DAG.getConstant(0x800, MVT::i16)),
12401 DAG.getConstant(11, MVT::i8));
12403 DAG.getNode(ISD::SRL, DL, MVT::i16,
12404 DAG.getNode(ISD::AND, DL, MVT::i16,
12405 CWD, DAG.getConstant(0x400, MVT::i16)),
12406 DAG.getConstant(9, MVT::i8));
12409 DAG.getNode(ISD::AND, DL, MVT::i16,
12410 DAG.getNode(ISD::ADD, DL, MVT::i16,
12411 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12412 DAG.getConstant(1, MVT::i16)),
12413 DAG.getConstant(3, MVT::i16));
12415 return DAG.getNode((VT.getSizeInBits() < 16 ?
12416 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12419 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12420 EVT VT = Op.getValueType();
12422 unsigned NumBits = VT.getSizeInBits();
12425 Op = Op.getOperand(0);
12426 if (VT == MVT::i8) {
12427 // Zero extend to i32 since there is not an i8 bsr.
12429 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12432 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12433 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12434 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12436 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12439 DAG.getConstant(NumBits+NumBits-1, OpVT),
12440 DAG.getConstant(X86::COND_E, MVT::i8),
12443 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12445 // Finally xor with NumBits-1.
12446 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12449 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12453 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12454 EVT VT = Op.getValueType();
12456 unsigned NumBits = VT.getSizeInBits();
12459 Op = Op.getOperand(0);
12460 if (VT == MVT::i8) {
12461 // Zero extend to i32 since there is not an i8 bsr.
12463 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12466 // Issue a bsr (scan bits in reverse).
12467 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12468 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12470 // And xor with NumBits-1.
12471 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12474 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12478 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12479 EVT VT = Op.getValueType();
12480 unsigned NumBits = VT.getSizeInBits();
12482 Op = Op.getOperand(0);
12484 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12485 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12486 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12488 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12491 DAG.getConstant(NumBits, VT),
12492 DAG.getConstant(X86::COND_E, MVT::i8),
12495 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12498 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12499 // ones, and then concatenate the result back.
12500 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12501 EVT VT = Op.getValueType();
12503 assert(VT.is256BitVector() && VT.isInteger() &&
12504 "Unsupported value type for operation");
12506 unsigned NumElems = VT.getVectorNumElements();
12509 // Extract the LHS vectors
12510 SDValue LHS = Op.getOperand(0);
12511 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12512 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12514 // Extract the RHS vectors
12515 SDValue RHS = Op.getOperand(1);
12516 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12517 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12519 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12520 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12522 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12523 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12524 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12527 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12528 assert(Op.getValueType().is256BitVector() &&
12529 Op.getValueType().isInteger() &&
12530 "Only handle AVX 256-bit vector integer operation");
12531 return Lower256IntArith(Op, DAG);
12534 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12535 assert(Op.getValueType().is256BitVector() &&
12536 Op.getValueType().isInteger() &&
12537 "Only handle AVX 256-bit vector integer operation");
12538 return Lower256IntArith(Op, DAG);
12541 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12542 SelectionDAG &DAG) {
12544 EVT VT = Op.getValueType();
12546 // Decompose 256-bit ops into smaller 128-bit ops.
12547 if (VT.is256BitVector() && !Subtarget->hasInt256())
12548 return Lower256IntArith(Op, DAG);
12550 SDValue A = Op.getOperand(0);
12551 SDValue B = Op.getOperand(1);
12553 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12554 if (VT == MVT::v4i32) {
12555 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12556 "Should not custom lower when pmuldq is available!");
12558 // Extract the odd parts.
12559 static const int UnpackMask[] = { 1, -1, 3, -1 };
12560 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12561 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12563 // Multiply the even parts.
12564 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12565 // Now multiply odd parts.
12566 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12568 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12569 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12571 // Merge the two vectors back together with a shuffle. This expands into 2
12573 static const int ShufMask[] = { 0, 4, 2, 6 };
12574 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12577 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12578 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12580 // Ahi = psrlqi(a, 32);
12581 // Bhi = psrlqi(b, 32);
12583 // AloBlo = pmuludq(a, b);
12584 // AloBhi = pmuludq(a, Bhi);
12585 // AhiBlo = pmuludq(Ahi, b);
12587 // AloBhi = psllqi(AloBhi, 32);
12588 // AhiBlo = psllqi(AhiBlo, 32);
12589 // return AloBlo + AloBhi + AhiBlo;
12591 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12592 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12594 // Bit cast to 32-bit vectors for MULUDQ
12595 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12596 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12597 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12598 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12599 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12600 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12602 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12603 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12604 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12606 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12607 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12609 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12610 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12613 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12614 EVT VT = Op.getValueType();
12615 EVT EltTy = VT.getVectorElementType();
12616 unsigned NumElts = VT.getVectorNumElements();
12617 SDValue N0 = Op.getOperand(0);
12620 // Lower sdiv X, pow2-const.
12621 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12625 APInt SplatValue, SplatUndef;
12626 unsigned SplatBitSize;
12628 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12630 EltTy.getSizeInBits() < SplatBitSize)
12633 if ((SplatValue != 0) &&
12634 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12635 unsigned Lg2 = SplatValue.countTrailingZeros();
12636 // Splat the sign bit.
12637 SmallVector<SDValue, 16> Sz(NumElts,
12638 DAG.getConstant(EltTy.getSizeInBits() - 1,
12640 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12641 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12643 // Add (N0 < 0) ? abs2 - 1 : 0;
12644 SmallVector<SDValue, 16> Amt(NumElts,
12645 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12647 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12648 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12650 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12651 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12652 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12653 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12656 // If we're dividing by a positive value, we're done. Otherwise, we must
12657 // negate the result.
12658 if (SplatValue.isNonNegative())
12661 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12662 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12663 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12668 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12669 const X86Subtarget *Subtarget) {
12670 EVT VT = Op.getValueType();
12672 SDValue R = Op.getOperand(0);
12673 SDValue Amt = Op.getOperand(1);
12675 // Optimize shl/srl/sra with constant shift amount.
12676 if (isSplatVector(Amt.getNode())) {
12677 SDValue SclrAmt = Amt->getOperand(0);
12678 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12679 uint64_t ShiftAmt = C->getZExtValue();
12681 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12682 (Subtarget->hasInt256() &&
12683 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12684 (Subtarget->hasAVX512() &&
12685 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12686 if (Op.getOpcode() == ISD::SHL)
12687 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12689 if (Op.getOpcode() == ISD::SRL)
12690 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12692 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12693 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12697 if (VT == MVT::v16i8) {
12698 if (Op.getOpcode() == ISD::SHL) {
12699 // Make a large shift.
12700 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12701 MVT::v8i16, R, ShiftAmt,
12703 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12704 // Zero out the rightmost bits.
12705 SmallVector<SDValue, 16> V(16,
12706 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12708 return DAG.getNode(ISD::AND, dl, VT, SHL,
12709 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12711 if (Op.getOpcode() == ISD::SRL) {
12712 // Make a large shift.
12713 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12714 MVT::v8i16, R, ShiftAmt,
12716 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12717 // Zero out the leftmost bits.
12718 SmallVector<SDValue, 16> V(16,
12719 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12721 return DAG.getNode(ISD::AND, dl, VT, SRL,
12722 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12724 if (Op.getOpcode() == ISD::SRA) {
12725 if (ShiftAmt == 7) {
12726 // R s>> 7 === R s< 0
12727 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12728 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12731 // R s>> a === ((R u>> a) ^ m) - m
12732 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12733 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12735 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12736 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12737 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12740 llvm_unreachable("Unknown shift opcode.");
12743 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12744 if (Op.getOpcode() == ISD::SHL) {
12745 // Make a large shift.
12746 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12747 MVT::v16i16, R, ShiftAmt,
12749 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12750 // Zero out the rightmost bits.
12751 SmallVector<SDValue, 32> V(32,
12752 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12754 return DAG.getNode(ISD::AND, dl, VT, SHL,
12755 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12757 if (Op.getOpcode() == ISD::SRL) {
12758 // Make a large shift.
12759 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12760 MVT::v16i16, R, ShiftAmt,
12762 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12763 // Zero out the leftmost bits.
12764 SmallVector<SDValue, 32> V(32,
12765 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12767 return DAG.getNode(ISD::AND, dl, VT, SRL,
12768 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12770 if (Op.getOpcode() == ISD::SRA) {
12771 if (ShiftAmt == 7) {
12772 // R s>> 7 === R s< 0
12773 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12774 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12777 // R s>> a === ((R u>> a) ^ m) - m
12778 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12779 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12781 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12782 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12783 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12786 llvm_unreachable("Unknown shift opcode.");
12791 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12792 if (!Subtarget->is64Bit() &&
12793 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12794 Amt.getOpcode() == ISD::BITCAST &&
12795 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12796 Amt = Amt.getOperand(0);
12797 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12798 VT.getVectorNumElements();
12799 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12800 uint64_t ShiftAmt = 0;
12801 for (unsigned i = 0; i != Ratio; ++i) {
12802 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12806 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12808 // Check remaining shift amounts.
12809 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12810 uint64_t ShAmt = 0;
12811 for (unsigned j = 0; j != Ratio; ++j) {
12812 ConstantSDNode *C =
12813 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12817 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12819 if (ShAmt != ShiftAmt)
12822 switch (Op.getOpcode()) {
12824 llvm_unreachable("Unknown shift opcode!");
12826 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12829 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12832 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12840 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12841 const X86Subtarget* Subtarget) {
12842 EVT VT = Op.getValueType();
12844 SDValue R = Op.getOperand(0);
12845 SDValue Amt = Op.getOperand(1);
12847 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12848 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12849 (Subtarget->hasInt256() &&
12850 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12851 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12852 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12854 EVT EltVT = VT.getVectorElementType();
12856 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12857 unsigned NumElts = VT.getVectorNumElements();
12859 for (i = 0; i != NumElts; ++i) {
12860 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12864 for (j = i; j != NumElts; ++j) {
12865 SDValue Arg = Amt.getOperand(j);
12866 if (Arg.getOpcode() == ISD::UNDEF) continue;
12867 if (Arg != Amt.getOperand(i))
12870 if (i != NumElts && j == NumElts)
12871 BaseShAmt = Amt.getOperand(i);
12873 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12874 Amt = Amt.getOperand(0);
12875 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12876 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12877 SDValue InVec = Amt.getOperand(0);
12878 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12879 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12881 for (; i != NumElts; ++i) {
12882 SDValue Arg = InVec.getOperand(i);
12883 if (Arg.getOpcode() == ISD::UNDEF) continue;
12887 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12888 if (ConstantSDNode *C =
12889 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12890 unsigned SplatIdx =
12891 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12892 if (C->getZExtValue() == SplatIdx)
12893 BaseShAmt = InVec.getOperand(1);
12896 if (BaseShAmt.getNode() == 0)
12897 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12898 DAG.getIntPtrConstant(0));
12902 if (BaseShAmt.getNode()) {
12903 if (EltVT.bitsGT(MVT::i32))
12904 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12905 else if (EltVT.bitsLT(MVT::i32))
12906 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12908 switch (Op.getOpcode()) {
12910 llvm_unreachable("Unknown shift opcode!");
12912 switch (VT.getSimpleVT().SimpleTy) {
12913 default: return SDValue();
12922 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12925 switch (VT.getSimpleVT().SimpleTy) {
12926 default: return SDValue();
12933 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12936 switch (VT.getSimpleVT().SimpleTy) {
12937 default: return SDValue();
12946 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12952 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12953 if (!Subtarget->is64Bit() &&
12954 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12955 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12956 Amt.getOpcode() == ISD::BITCAST &&
12957 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12958 Amt = Amt.getOperand(0);
12959 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12960 VT.getVectorNumElements();
12961 std::vector<SDValue> Vals(Ratio);
12962 for (unsigned i = 0; i != Ratio; ++i)
12963 Vals[i] = Amt.getOperand(i);
12964 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12965 for (unsigned j = 0; j != Ratio; ++j)
12966 if (Vals[j] != Amt.getOperand(i + j))
12969 switch (Op.getOpcode()) {
12971 llvm_unreachable("Unknown shift opcode!");
12973 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12975 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12977 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12984 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12985 SelectionDAG &DAG) {
12987 EVT VT = Op.getValueType();
12989 SDValue R = Op.getOperand(0);
12990 SDValue Amt = Op.getOperand(1);
12993 if (!Subtarget->hasSSE2())
12996 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13000 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13004 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13006 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13007 if (Subtarget->hasInt256()) {
13008 if (Op.getOpcode() == ISD::SRL &&
13009 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13010 VT == MVT::v4i64 || VT == MVT::v8i32))
13012 if (Op.getOpcode() == ISD::SHL &&
13013 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13014 VT == MVT::v4i64 || VT == MVT::v8i32))
13016 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13020 // Lower SHL with variable shift amount.
13021 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13022 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13024 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13025 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13026 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13027 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13029 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13030 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13033 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13034 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13036 // Turn 'a' into a mask suitable for VSELECT
13037 SDValue VSelM = DAG.getConstant(0x80, VT);
13038 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13039 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13041 SDValue CM1 = DAG.getConstant(0x0f, VT);
13042 SDValue CM2 = DAG.getConstant(0x3f, VT);
13044 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13045 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13046 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13047 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13048 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13051 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13052 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13053 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13055 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13056 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13057 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13058 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13059 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13062 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13063 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13064 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13066 // return VSELECT(r, r+r, a);
13067 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13068 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13072 // Decompose 256-bit shifts into smaller 128-bit shifts.
13073 if (VT.is256BitVector()) {
13074 unsigned NumElems = VT.getVectorNumElements();
13075 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13076 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13078 // Extract the two vectors
13079 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13080 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13082 // Recreate the shift amount vectors
13083 SDValue Amt1, Amt2;
13084 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13085 // Constant shift amount
13086 SmallVector<SDValue, 4> Amt1Csts;
13087 SmallVector<SDValue, 4> Amt2Csts;
13088 for (unsigned i = 0; i != NumElems/2; ++i)
13089 Amt1Csts.push_back(Amt->getOperand(i));
13090 for (unsigned i = NumElems/2; i != NumElems; ++i)
13091 Amt2Csts.push_back(Amt->getOperand(i));
13093 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13094 &Amt1Csts[0], NumElems/2);
13095 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13096 &Amt2Csts[0], NumElems/2);
13098 // Variable shift amount
13099 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13100 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13103 // Issue new vector shifts for the smaller types
13104 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13105 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13107 // Concatenate the result back
13108 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13114 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13115 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13116 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13117 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13118 // has only one use.
13119 SDNode *N = Op.getNode();
13120 SDValue LHS = N->getOperand(0);
13121 SDValue RHS = N->getOperand(1);
13122 unsigned BaseOp = 0;
13125 switch (Op.getOpcode()) {
13126 default: llvm_unreachable("Unknown ovf instruction!");
13128 // A subtract of one will be selected as a INC. Note that INC doesn't
13129 // set CF, so we can't do this for UADDO.
13130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13132 BaseOp = X86ISD::INC;
13133 Cond = X86::COND_O;
13136 BaseOp = X86ISD::ADD;
13137 Cond = X86::COND_O;
13140 BaseOp = X86ISD::ADD;
13141 Cond = X86::COND_B;
13144 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13145 // set CF, so we can't do this for USUBO.
13146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13148 BaseOp = X86ISD::DEC;
13149 Cond = X86::COND_O;
13152 BaseOp = X86ISD::SUB;
13153 Cond = X86::COND_O;
13156 BaseOp = X86ISD::SUB;
13157 Cond = X86::COND_B;
13160 BaseOp = X86ISD::SMUL;
13161 Cond = X86::COND_O;
13163 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13164 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13166 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13169 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13170 DAG.getConstant(X86::COND_O, MVT::i32),
13171 SDValue(Sum.getNode(), 2));
13173 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13177 // Also sets EFLAGS.
13178 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13179 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13182 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13183 DAG.getConstant(Cond, MVT::i32),
13184 SDValue(Sum.getNode(), 1));
13186 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13189 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13190 SelectionDAG &DAG) const {
13192 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13193 EVT VT = Op.getValueType();
13195 if (!Subtarget->hasSSE2() || !VT.isVector())
13198 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13199 ExtraVT.getScalarType().getSizeInBits();
13201 switch (VT.getSimpleVT().SimpleTy) {
13202 default: return SDValue();
13205 if (!Subtarget->hasFp256())
13207 if (!Subtarget->hasInt256()) {
13208 // needs to be split
13209 unsigned NumElems = VT.getVectorNumElements();
13211 // Extract the LHS vectors
13212 SDValue LHS = Op.getOperand(0);
13213 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13214 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13216 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13217 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13219 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13220 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13221 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13223 SDValue Extra = DAG.getValueType(ExtraVT);
13225 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13226 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13228 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13233 SDValue Op0 = Op.getOperand(0);
13234 SDValue Op00 = Op0.getOperand(0);
13236 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13237 if (Op0.getOpcode() == ISD::BITCAST &&
13238 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13239 // (sext (vzext x)) -> (vsext x)
13240 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13241 if (Tmp1.getNode()) {
13242 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13243 // This folding is only valid when the in-reg type is a vector of i8,
13245 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13246 ExtraEltVT == MVT::i32) {
13247 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13248 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13249 "This optimization is invalid without a VZEXT.");
13250 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13256 // If the above didn't work, then just use Shift-Left + Shift-Right.
13257 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13259 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13265 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13266 SelectionDAG &DAG) {
13268 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13269 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13270 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13271 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13273 // The only fence that needs an instruction is a sequentially-consistent
13274 // cross-thread fence.
13275 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13276 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13277 // no-sse2). There isn't any reason to disable it if the target processor
13279 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13280 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13282 SDValue Chain = Op.getOperand(0);
13283 SDValue Zero = DAG.getConstant(0, MVT::i32);
13285 DAG.getRegister(X86::ESP, MVT::i32), // Base
13286 DAG.getTargetConstant(1, MVT::i8), // Scale
13287 DAG.getRegister(0, MVT::i32), // Index
13288 DAG.getTargetConstant(0, MVT::i32), // Disp
13289 DAG.getRegister(0, MVT::i32), // Segment.
13293 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13294 return SDValue(Res, 0);
13297 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13298 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13301 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13302 SelectionDAG &DAG) {
13303 EVT T = Op.getValueType();
13307 switch(T.getSimpleVT().SimpleTy) {
13308 default: llvm_unreachable("Invalid value type!");
13309 case MVT::i8: Reg = X86::AL; size = 1; break;
13310 case MVT::i16: Reg = X86::AX; size = 2; break;
13311 case MVT::i32: Reg = X86::EAX; size = 4; break;
13313 assert(Subtarget->is64Bit() && "Node not type legal!");
13314 Reg = X86::RAX; size = 8;
13317 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13318 Op.getOperand(2), SDValue());
13319 SDValue Ops[] = { cpIn.getValue(0),
13322 DAG.getTargetConstant(size, MVT::i8),
13323 cpIn.getValue(1) };
13324 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13325 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13326 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13327 Ops, array_lengthof(Ops), T, MMO);
13329 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13333 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13334 SelectionDAG &DAG) {
13335 assert(Subtarget->is64Bit() && "Result not type legalized?");
13336 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13337 SDValue TheChain = Op.getOperand(0);
13339 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13340 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13341 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13343 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13344 DAG.getConstant(32, MVT::i8));
13346 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13349 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13352 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13353 SelectionDAG &DAG) {
13354 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13355 MVT DstVT = Op.getSimpleValueType();
13356 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13357 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13358 assert((DstVT == MVT::i64 ||
13359 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13360 "Unexpected custom BITCAST");
13361 // i64 <=> MMX conversions are Legal.
13362 if (SrcVT==MVT::i64 && DstVT.isVector())
13364 if (DstVT==MVT::i64 && SrcVT.isVector())
13366 // MMX <=> MMX conversions are Legal.
13367 if (SrcVT.isVector() && DstVT.isVector())
13369 // All other conversions need to be expanded.
13373 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13374 SDNode *Node = Op.getNode();
13376 EVT T = Node->getValueType(0);
13377 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13378 DAG.getConstant(0, T), Node->getOperand(2));
13379 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13380 cast<AtomicSDNode>(Node)->getMemoryVT(),
13381 Node->getOperand(0),
13382 Node->getOperand(1), negOp,
13383 cast<AtomicSDNode>(Node)->getSrcValue(),
13384 cast<AtomicSDNode>(Node)->getAlignment(),
13385 cast<AtomicSDNode>(Node)->getOrdering(),
13386 cast<AtomicSDNode>(Node)->getSynchScope());
13389 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13390 SDNode *Node = Op.getNode();
13392 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13394 // Convert seq_cst store -> xchg
13395 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13396 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13397 // (The only way to get a 16-byte store is cmpxchg16b)
13398 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13399 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13400 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13401 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13402 cast<AtomicSDNode>(Node)->getMemoryVT(),
13403 Node->getOperand(0),
13404 Node->getOperand(1), Node->getOperand(2),
13405 cast<AtomicSDNode>(Node)->getMemOperand(),
13406 cast<AtomicSDNode>(Node)->getOrdering(),
13407 cast<AtomicSDNode>(Node)->getSynchScope());
13408 return Swap.getValue(1);
13410 // Other atomic stores have a simple pattern.
13414 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13415 EVT VT = Op.getNode()->getValueType(0);
13417 // Let legalize expand this if it isn't a legal type yet.
13418 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13421 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13424 bool ExtraOp = false;
13425 switch (Op.getOpcode()) {
13426 default: llvm_unreachable("Invalid code");
13427 case ISD::ADDC: Opc = X86ISD::ADD; break;
13428 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13429 case ISD::SUBC: Opc = X86ISD::SUB; break;
13430 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13434 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13436 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13437 Op.getOperand(1), Op.getOperand(2));
13440 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13441 SelectionDAG &DAG) {
13442 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13444 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13445 // which returns the values as { float, float } (in XMM0) or
13446 // { double, double } (which is returned in XMM0, XMM1).
13448 SDValue Arg = Op.getOperand(0);
13449 EVT ArgVT = Arg.getValueType();
13450 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13452 TargetLowering::ArgListTy Args;
13453 TargetLowering::ArgListEntry Entry;
13457 Entry.isSExt = false;
13458 Entry.isZExt = false;
13459 Args.push_back(Entry);
13461 bool isF64 = ArgVT == MVT::f64;
13462 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13463 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13464 // the results are returned via SRet in memory.
13465 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13467 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13469 Type *RetTy = isF64
13470 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13471 : (Type*)VectorType::get(ArgTy, 4);
13473 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13474 false, false, false, false, 0,
13475 CallingConv::C, /*isTaillCall=*/false,
13476 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13477 Callee, Args, DAG, dl);
13478 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13481 // Returned in xmm0 and xmm1.
13482 return CallResult.first;
13484 // Returned in bits 0:31 and 32:64 xmm0.
13485 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13486 CallResult.first, DAG.getIntPtrConstant(0));
13487 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13488 CallResult.first, DAG.getIntPtrConstant(1));
13489 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13490 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13493 /// LowerOperation - Provide custom lowering hooks for some operations.
13495 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13496 switch (Op.getOpcode()) {
13497 default: llvm_unreachable("Should not custom lower this!");
13498 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13499 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13500 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13501 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13502 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13503 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13504 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13505 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13506 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13507 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13508 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13509 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13510 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13511 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13512 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13513 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13514 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13515 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13516 case ISD::SHL_PARTS:
13517 case ISD::SRA_PARTS:
13518 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13519 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13520 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13521 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13522 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13523 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13524 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13525 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13526 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13527 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13528 case ISD::FABS: return LowerFABS(Op, DAG);
13529 case ISD::FNEG: return LowerFNEG(Op, DAG);
13530 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13531 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13532 case ISD::SETCC: return LowerSETCC(Op, DAG);
13533 case ISD::SELECT: return LowerSELECT(Op, DAG);
13534 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13535 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13536 case ISD::VASTART: return LowerVASTART(Op, DAG);
13537 case ISD::VAARG: return LowerVAARG(Op, DAG);
13538 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13539 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13540 case ISD::INTRINSIC_VOID:
13541 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13542 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13543 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13544 case ISD::FRAME_TO_ARGS_OFFSET:
13545 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13546 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13547 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13548 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13549 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13550 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13551 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13552 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13553 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13554 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13555 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13556 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13559 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13565 case ISD::UMULO: return LowerXALUO(Op, DAG);
13566 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13567 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13571 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13572 case ISD::ADD: return LowerADD(Op, DAG);
13573 case ISD::SUB: return LowerSUB(Op, DAG);
13574 case ISD::SDIV: return LowerSDIV(Op, DAG);
13575 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13579 static void ReplaceATOMIC_LOAD(SDNode *Node,
13580 SmallVectorImpl<SDValue> &Results,
13581 SelectionDAG &DAG) {
13583 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13585 // Convert wide load -> cmpxchg8b/cmpxchg16b
13586 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13587 // (The only way to get a 16-byte load is cmpxchg16b)
13588 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13589 SDValue Zero = DAG.getConstant(0, VT);
13590 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13591 Node->getOperand(0),
13592 Node->getOperand(1), Zero, Zero,
13593 cast<AtomicSDNode>(Node)->getMemOperand(),
13594 cast<AtomicSDNode>(Node)->getOrdering(),
13595 cast<AtomicSDNode>(Node)->getSynchScope());
13596 Results.push_back(Swap.getValue(0));
13597 Results.push_back(Swap.getValue(1));
13601 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13602 SelectionDAG &DAG, unsigned NewOp) {
13604 assert (Node->getValueType(0) == MVT::i64 &&
13605 "Only know how to expand i64 atomics");
13607 SDValue Chain = Node->getOperand(0);
13608 SDValue In1 = Node->getOperand(1);
13609 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13610 Node->getOperand(2), DAG.getIntPtrConstant(0));
13611 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13612 Node->getOperand(2), DAG.getIntPtrConstant(1));
13613 SDValue Ops[] = { Chain, In1, In2L, In2H };
13614 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13616 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13617 cast<MemSDNode>(Node)->getMemOperand());
13618 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13619 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13620 Results.push_back(Result.getValue(2));
13623 /// ReplaceNodeResults - Replace a node with an illegal result type
13624 /// with a new node built out of custom code.
13625 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13626 SmallVectorImpl<SDValue>&Results,
13627 SelectionDAG &DAG) const {
13629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13630 switch (N->getOpcode()) {
13632 llvm_unreachable("Do not know how to custom type legalize this operation!");
13633 case ISD::SIGN_EXTEND_INREG:
13638 // We don't want to expand or promote these.
13640 case ISD::FP_TO_SINT:
13641 case ISD::FP_TO_UINT: {
13642 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13644 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13647 std::pair<SDValue,SDValue> Vals =
13648 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13649 SDValue FIST = Vals.first, StackSlot = Vals.second;
13650 if (FIST.getNode() != 0) {
13651 EVT VT = N->getValueType(0);
13652 // Return a load from the stack slot.
13653 if (StackSlot.getNode() != 0)
13654 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13655 MachinePointerInfo(),
13656 false, false, false, 0));
13658 Results.push_back(FIST);
13662 case ISD::UINT_TO_FP: {
13663 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13664 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13665 N->getValueType(0) != MVT::v2f32)
13667 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13669 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13671 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13672 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13673 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13674 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13675 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13676 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13679 case ISD::FP_ROUND: {
13680 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13682 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13683 Results.push_back(V);
13686 case ISD::READCYCLECOUNTER: {
13687 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13688 SDValue TheChain = N->getOperand(0);
13689 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13690 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13692 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13694 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13695 SDValue Ops[] = { eax, edx };
13696 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13697 array_lengthof(Ops)));
13698 Results.push_back(edx.getValue(1));
13701 case ISD::ATOMIC_CMP_SWAP: {
13702 EVT T = N->getValueType(0);
13703 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13704 bool Regs64bit = T == MVT::i128;
13705 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13706 SDValue cpInL, cpInH;
13707 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13708 DAG.getConstant(0, HalfT));
13709 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13710 DAG.getConstant(1, HalfT));
13711 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13712 Regs64bit ? X86::RAX : X86::EAX,
13714 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13715 Regs64bit ? X86::RDX : X86::EDX,
13716 cpInH, cpInL.getValue(1));
13717 SDValue swapInL, swapInH;
13718 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13719 DAG.getConstant(0, HalfT));
13720 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13721 DAG.getConstant(1, HalfT));
13722 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13723 Regs64bit ? X86::RBX : X86::EBX,
13724 swapInL, cpInH.getValue(1));
13725 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13726 Regs64bit ? X86::RCX : X86::ECX,
13727 swapInH, swapInL.getValue(1));
13728 SDValue Ops[] = { swapInH.getValue(0),
13730 swapInH.getValue(1) };
13731 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13732 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13733 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13734 X86ISD::LCMPXCHG8_DAG;
13735 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13736 Ops, array_lengthof(Ops), T, MMO);
13737 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13738 Regs64bit ? X86::RAX : X86::EAX,
13739 HalfT, Result.getValue(1));
13740 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13741 Regs64bit ? X86::RDX : X86::EDX,
13742 HalfT, cpOutL.getValue(2));
13743 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13744 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13745 Results.push_back(cpOutH.getValue(1));
13748 case ISD::ATOMIC_LOAD_ADD:
13749 case ISD::ATOMIC_LOAD_AND:
13750 case ISD::ATOMIC_LOAD_NAND:
13751 case ISD::ATOMIC_LOAD_OR:
13752 case ISD::ATOMIC_LOAD_SUB:
13753 case ISD::ATOMIC_LOAD_XOR:
13754 case ISD::ATOMIC_LOAD_MAX:
13755 case ISD::ATOMIC_LOAD_MIN:
13756 case ISD::ATOMIC_LOAD_UMAX:
13757 case ISD::ATOMIC_LOAD_UMIN:
13758 case ISD::ATOMIC_SWAP: {
13760 switch (N->getOpcode()) {
13761 default: llvm_unreachable("Unexpected opcode");
13762 case ISD::ATOMIC_LOAD_ADD:
13763 Opc = X86ISD::ATOMADD64_DAG;
13765 case ISD::ATOMIC_LOAD_AND:
13766 Opc = X86ISD::ATOMAND64_DAG;
13768 case ISD::ATOMIC_LOAD_NAND:
13769 Opc = X86ISD::ATOMNAND64_DAG;
13771 case ISD::ATOMIC_LOAD_OR:
13772 Opc = X86ISD::ATOMOR64_DAG;
13774 case ISD::ATOMIC_LOAD_SUB:
13775 Opc = X86ISD::ATOMSUB64_DAG;
13777 case ISD::ATOMIC_LOAD_XOR:
13778 Opc = X86ISD::ATOMXOR64_DAG;
13780 case ISD::ATOMIC_LOAD_MAX:
13781 Opc = X86ISD::ATOMMAX64_DAG;
13783 case ISD::ATOMIC_LOAD_MIN:
13784 Opc = X86ISD::ATOMMIN64_DAG;
13786 case ISD::ATOMIC_LOAD_UMAX:
13787 Opc = X86ISD::ATOMUMAX64_DAG;
13789 case ISD::ATOMIC_LOAD_UMIN:
13790 Opc = X86ISD::ATOMUMIN64_DAG;
13792 case ISD::ATOMIC_SWAP:
13793 Opc = X86ISD::ATOMSWAP64_DAG;
13796 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13799 case ISD::ATOMIC_LOAD:
13800 ReplaceATOMIC_LOAD(N, Results, DAG);
13804 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13806 default: return NULL;
13807 case X86ISD::BSF: return "X86ISD::BSF";
13808 case X86ISD::BSR: return "X86ISD::BSR";
13809 case X86ISD::SHLD: return "X86ISD::SHLD";
13810 case X86ISD::SHRD: return "X86ISD::SHRD";
13811 case X86ISD::FAND: return "X86ISD::FAND";
13812 case X86ISD::FANDN: return "X86ISD::FANDN";
13813 case X86ISD::FOR: return "X86ISD::FOR";
13814 case X86ISD::FXOR: return "X86ISD::FXOR";
13815 case X86ISD::FSRL: return "X86ISD::FSRL";
13816 case X86ISD::FILD: return "X86ISD::FILD";
13817 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13818 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13819 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13820 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13821 case X86ISD::FLD: return "X86ISD::FLD";
13822 case X86ISD::FST: return "X86ISD::FST";
13823 case X86ISD::CALL: return "X86ISD::CALL";
13824 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13825 case X86ISD::BT: return "X86ISD::BT";
13826 case X86ISD::CMP: return "X86ISD::CMP";
13827 case X86ISD::COMI: return "X86ISD::COMI";
13828 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13829 case X86ISD::CMPM: return "X86ISD::CMPM";
13830 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13831 case X86ISD::SETCC: return "X86ISD::SETCC";
13832 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13833 case X86ISD::FSETCC: return "X86ISD::FSETCC";
13834 case X86ISD::CMOV: return "X86ISD::CMOV";
13835 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13836 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13837 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13838 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13839 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13840 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13841 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13842 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13843 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13844 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13845 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13846 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13847 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13848 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13849 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13850 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13851 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13852 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13853 case X86ISD::HADD: return "X86ISD::HADD";
13854 case X86ISD::HSUB: return "X86ISD::HSUB";
13855 case X86ISD::FHADD: return "X86ISD::FHADD";
13856 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13857 case X86ISD::UMAX: return "X86ISD::UMAX";
13858 case X86ISD::UMIN: return "X86ISD::UMIN";
13859 case X86ISD::SMAX: return "X86ISD::SMAX";
13860 case X86ISD::SMIN: return "X86ISD::SMIN";
13861 case X86ISD::FMAX: return "X86ISD::FMAX";
13862 case X86ISD::FMIN: return "X86ISD::FMIN";
13863 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13864 case X86ISD::FMINC: return "X86ISD::FMINC";
13865 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13866 case X86ISD::FRCP: return "X86ISD::FRCP";
13867 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13868 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13869 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13870 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13871 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13872 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13873 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13874 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13875 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13876 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13877 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13878 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13879 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13880 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13881 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13882 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13883 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13884 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13885 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13886 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13887 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13888 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13889 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13890 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13891 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13892 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13893 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13894 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13895 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13896 case X86ISD::VSHL: return "X86ISD::VSHL";
13897 case X86ISD::VSRL: return "X86ISD::VSRL";
13898 case X86ISD::VSRA: return "X86ISD::VSRA";
13899 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13900 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13901 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13902 case X86ISD::CMPP: return "X86ISD::CMPP";
13903 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13904 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13905 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13906 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13907 case X86ISD::ADD: return "X86ISD::ADD";
13908 case X86ISD::SUB: return "X86ISD::SUB";
13909 case X86ISD::ADC: return "X86ISD::ADC";
13910 case X86ISD::SBB: return "X86ISD::SBB";
13911 case X86ISD::SMUL: return "X86ISD::SMUL";
13912 case X86ISD::UMUL: return "X86ISD::UMUL";
13913 case X86ISD::INC: return "X86ISD::INC";
13914 case X86ISD::DEC: return "X86ISD::DEC";
13915 case X86ISD::OR: return "X86ISD::OR";
13916 case X86ISD::XOR: return "X86ISD::XOR";
13917 case X86ISD::AND: return "X86ISD::AND";
13918 case X86ISD::BLSI: return "X86ISD::BLSI";
13919 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13920 case X86ISD::BLSR: return "X86ISD::BLSR";
13921 case X86ISD::BZHI: return "X86ISD::BZHI";
13922 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13923 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13924 case X86ISD::PTEST: return "X86ISD::PTEST";
13925 case X86ISD::TESTP: return "X86ISD::TESTP";
13926 case X86ISD::TESTM: return "X86ISD::TESTM";
13927 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13928 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13929 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13930 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13931 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13932 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13933 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13934 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13935 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13936 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13937 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13938 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13939 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13940 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13941 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13942 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13943 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13944 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13945 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13946 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13947 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13948 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13949 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13950 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13951 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13952 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13953 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13954 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13955 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13956 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13957 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13958 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13959 case X86ISD::SAHF: return "X86ISD::SAHF";
13960 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13961 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13962 case X86ISD::FMADD: return "X86ISD::FMADD";
13963 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13964 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13965 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13966 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13967 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13968 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13969 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13970 case X86ISD::XTEST: return "X86ISD::XTEST";
13974 // isLegalAddressingMode - Return true if the addressing mode represented
13975 // by AM is legal for this target, for a load/store of the specified type.
13976 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13978 // X86 supports extremely general addressing modes.
13979 CodeModel::Model M = getTargetMachine().getCodeModel();
13980 Reloc::Model R = getTargetMachine().getRelocationModel();
13982 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13983 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13988 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13990 // If a reference to this global requires an extra load, we can't fold it.
13991 if (isGlobalStubReference(GVFlags))
13994 // If BaseGV requires a register for the PIC base, we cannot also have a
13995 // BaseReg specified.
13996 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13999 // If lower 4G is not available, then we must use rip-relative addressing.
14000 if ((M != CodeModel::Small || R != Reloc::Static) &&
14001 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14005 switch (AM.Scale) {
14011 // These scales always work.
14016 // These scales are formed with basereg+scalereg. Only accept if there is
14021 default: // Other stuff never works.
14028 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14029 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14031 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14032 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14033 return NumBits1 > NumBits2;
14036 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14037 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14040 if (!isTypeLegal(EVT::getEVT(Ty1)))
14043 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14045 // Assuming the caller doesn't have a zeroext or signext return parameter,
14046 // truncation all the way down to i1 is valid.
14050 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14051 return isInt<32>(Imm);
14054 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14055 // Can also use sub to handle negated immediates.
14056 return isInt<32>(Imm);
14059 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14060 if (!VT1.isInteger() || !VT2.isInteger())
14062 unsigned NumBits1 = VT1.getSizeInBits();
14063 unsigned NumBits2 = VT2.getSizeInBits();
14064 return NumBits1 > NumBits2;
14067 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14068 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14069 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14072 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14073 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14074 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14077 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14078 EVT VT1 = Val.getValueType();
14079 if (isZExtFree(VT1, VT2))
14082 if (Val.getOpcode() != ISD::LOAD)
14085 if (!VT1.isSimple() || !VT1.isInteger() ||
14086 !VT2.isSimple() || !VT2.isInteger())
14089 switch (VT1.getSimpleVT().SimpleTy) {
14094 // X86 has 8, 16, and 32-bit zero-extending loads.
14102 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14103 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14106 VT = VT.getScalarType();
14108 if (!VT.isSimple())
14111 switch (VT.getSimpleVT().SimpleTy) {
14122 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14123 // i16 instructions are longer (0x66 prefix) and potentially slower.
14124 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14127 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14128 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14129 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14130 /// are assumed to be legal.
14132 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14134 if (!VT.isSimple())
14137 MVT SVT = VT.getSimpleVT();
14139 // Very little shuffling can be done for 64-bit vectors right now.
14140 if (VT.getSizeInBits() == 64)
14143 // FIXME: pshufb, blends, shifts.
14144 return (SVT.getVectorNumElements() == 2 ||
14145 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14146 isMOVLMask(M, SVT) ||
14147 isSHUFPMask(M, SVT) ||
14148 isPSHUFDMask(M, SVT) ||
14149 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14150 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14151 isPALIGNRMask(M, SVT, Subtarget) ||
14152 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14153 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14154 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14155 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14159 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14161 if (!VT.isSimple())
14164 MVT SVT = VT.getSimpleVT();
14165 unsigned NumElts = SVT.getVectorNumElements();
14166 // FIXME: This collection of masks seems suspect.
14169 if (NumElts == 4 && SVT.is128BitVector()) {
14170 return (isMOVLMask(Mask, SVT) ||
14171 isCommutedMOVLMask(Mask, SVT, true) ||
14172 isSHUFPMask(Mask, SVT) ||
14173 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14178 //===----------------------------------------------------------------------===//
14179 // X86 Scheduler Hooks
14180 //===----------------------------------------------------------------------===//
14182 /// Utility function to emit xbegin specifying the start of an RTM region.
14183 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14184 const TargetInstrInfo *TII) {
14185 DebugLoc DL = MI->getDebugLoc();
14187 const BasicBlock *BB = MBB->getBasicBlock();
14188 MachineFunction::iterator I = MBB;
14191 // For the v = xbegin(), we generate
14202 MachineBasicBlock *thisMBB = MBB;
14203 MachineFunction *MF = MBB->getParent();
14204 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14205 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14206 MF->insert(I, mainMBB);
14207 MF->insert(I, sinkMBB);
14209 // Transfer the remainder of BB and its successor edges to sinkMBB.
14210 sinkMBB->splice(sinkMBB->begin(), MBB,
14211 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14212 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14216 // # fallthrough to mainMBB
14217 // # abortion to sinkMBB
14218 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14219 thisMBB->addSuccessor(mainMBB);
14220 thisMBB->addSuccessor(sinkMBB);
14224 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14225 mainMBB->addSuccessor(sinkMBB);
14228 // EAX is live into the sinkMBB
14229 sinkMBB->addLiveIn(X86::EAX);
14230 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14231 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14234 MI->eraseFromParent();
14238 // Get CMPXCHG opcode for the specified data type.
14239 static unsigned getCmpXChgOpcode(EVT VT) {
14240 switch (VT.getSimpleVT().SimpleTy) {
14241 case MVT::i8: return X86::LCMPXCHG8;
14242 case MVT::i16: return X86::LCMPXCHG16;
14243 case MVT::i32: return X86::LCMPXCHG32;
14244 case MVT::i64: return X86::LCMPXCHG64;
14248 llvm_unreachable("Invalid operand size!");
14251 // Get LOAD opcode for the specified data type.
14252 static unsigned getLoadOpcode(EVT VT) {
14253 switch (VT.getSimpleVT().SimpleTy) {
14254 case MVT::i8: return X86::MOV8rm;
14255 case MVT::i16: return X86::MOV16rm;
14256 case MVT::i32: return X86::MOV32rm;
14257 case MVT::i64: return X86::MOV64rm;
14261 llvm_unreachable("Invalid operand size!");
14264 // Get opcode of the non-atomic one from the specified atomic instruction.
14265 static unsigned getNonAtomicOpcode(unsigned Opc) {
14267 case X86::ATOMAND8: return X86::AND8rr;
14268 case X86::ATOMAND16: return X86::AND16rr;
14269 case X86::ATOMAND32: return X86::AND32rr;
14270 case X86::ATOMAND64: return X86::AND64rr;
14271 case X86::ATOMOR8: return X86::OR8rr;
14272 case X86::ATOMOR16: return X86::OR16rr;
14273 case X86::ATOMOR32: return X86::OR32rr;
14274 case X86::ATOMOR64: return X86::OR64rr;
14275 case X86::ATOMXOR8: return X86::XOR8rr;
14276 case X86::ATOMXOR16: return X86::XOR16rr;
14277 case X86::ATOMXOR32: return X86::XOR32rr;
14278 case X86::ATOMXOR64: return X86::XOR64rr;
14280 llvm_unreachable("Unhandled atomic-load-op opcode!");
14283 // Get opcode of the non-atomic one from the specified atomic instruction with
14285 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14286 unsigned &ExtraOpc) {
14288 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14289 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14290 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14291 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14292 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14293 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14294 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14295 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14296 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14297 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14298 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14299 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14300 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14301 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14302 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14303 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14304 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14305 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14306 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14307 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14309 llvm_unreachable("Unhandled atomic-load-op opcode!");
14312 // Get opcode of the non-atomic one from the specified atomic instruction for
14313 // 64-bit data type on 32-bit target.
14314 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14316 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14317 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14318 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14319 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14320 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14321 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14322 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14323 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14324 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14325 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14327 llvm_unreachable("Unhandled atomic-load-op opcode!");
14330 // Get opcode of the non-atomic one from the specified atomic instruction for
14331 // 64-bit data type on 32-bit target with extra opcode.
14332 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14334 unsigned &ExtraOpc) {
14336 case X86::ATOMNAND6432:
14337 ExtraOpc = X86::NOT32r;
14338 HiOpc = X86::AND32rr;
14339 return X86::AND32rr;
14341 llvm_unreachable("Unhandled atomic-load-op opcode!");
14344 // Get pseudo CMOV opcode from the specified data type.
14345 static unsigned getPseudoCMOVOpc(EVT VT) {
14346 switch (VT.getSimpleVT().SimpleTy) {
14347 case MVT::i8: return X86::CMOV_GR8;
14348 case MVT::i16: return X86::CMOV_GR16;
14349 case MVT::i32: return X86::CMOV_GR32;
14353 llvm_unreachable("Unknown CMOV opcode!");
14356 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14357 // They will be translated into a spin-loop or compare-exchange loop from
14360 // dst = atomic-fetch-op MI.addr, MI.val
14366 // t1 = LOAD MI.addr
14368 // t4 = phi(t1, t3 / loop)
14369 // t2 = OP MI.val, t4
14371 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14377 MachineBasicBlock *
14378 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14379 MachineBasicBlock *MBB) const {
14380 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14381 DebugLoc DL = MI->getDebugLoc();
14383 MachineFunction *MF = MBB->getParent();
14384 MachineRegisterInfo &MRI = MF->getRegInfo();
14386 const BasicBlock *BB = MBB->getBasicBlock();
14387 MachineFunction::iterator I = MBB;
14390 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14391 "Unexpected number of operands");
14393 assert(MI->hasOneMemOperand() &&
14394 "Expected atomic-load-op to have one memoperand");
14396 // Memory Reference
14397 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14398 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14400 unsigned DstReg, SrcReg;
14401 unsigned MemOpndSlot;
14403 unsigned CurOp = 0;
14405 DstReg = MI->getOperand(CurOp++).getReg();
14406 MemOpndSlot = CurOp;
14407 CurOp += X86::AddrNumOperands;
14408 SrcReg = MI->getOperand(CurOp++).getReg();
14410 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14411 MVT::SimpleValueType VT = *RC->vt_begin();
14412 unsigned t1 = MRI.createVirtualRegister(RC);
14413 unsigned t2 = MRI.createVirtualRegister(RC);
14414 unsigned t3 = MRI.createVirtualRegister(RC);
14415 unsigned t4 = MRI.createVirtualRegister(RC);
14416 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14418 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14419 unsigned LOADOpc = getLoadOpcode(VT);
14421 // For the atomic load-arith operator, we generate
14424 // t1 = LOAD [MI.addr]
14426 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14427 // t1 = OP MI.val, EAX
14429 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14435 MachineBasicBlock *thisMBB = MBB;
14436 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14437 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14438 MF->insert(I, mainMBB);
14439 MF->insert(I, sinkMBB);
14441 MachineInstrBuilder MIB;
14443 // Transfer the remainder of BB and its successor edges to sinkMBB.
14444 sinkMBB->splice(sinkMBB->begin(), MBB,
14445 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14446 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14449 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14450 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14451 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14453 NewMO.setIsKill(false);
14454 MIB.addOperand(NewMO);
14456 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14457 unsigned flags = (*MMOI)->getFlags();
14458 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14459 MachineMemOperand *MMO =
14460 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14461 (*MMOI)->getSize(),
14462 (*MMOI)->getBaseAlignment(),
14463 (*MMOI)->getTBAAInfo(),
14464 (*MMOI)->getRanges());
14465 MIB.addMemOperand(MMO);
14468 thisMBB->addSuccessor(mainMBB);
14471 MachineBasicBlock *origMainMBB = mainMBB;
14474 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14475 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14477 unsigned Opc = MI->getOpcode();
14480 llvm_unreachable("Unhandled atomic-load-op opcode!");
14481 case X86::ATOMAND8:
14482 case X86::ATOMAND16:
14483 case X86::ATOMAND32:
14484 case X86::ATOMAND64:
14486 case X86::ATOMOR16:
14487 case X86::ATOMOR32:
14488 case X86::ATOMOR64:
14489 case X86::ATOMXOR8:
14490 case X86::ATOMXOR16:
14491 case X86::ATOMXOR32:
14492 case X86::ATOMXOR64: {
14493 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14494 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14498 case X86::ATOMNAND8:
14499 case X86::ATOMNAND16:
14500 case X86::ATOMNAND32:
14501 case X86::ATOMNAND64: {
14502 unsigned Tmp = MRI.createVirtualRegister(RC);
14504 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14505 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14507 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14510 case X86::ATOMMAX8:
14511 case X86::ATOMMAX16:
14512 case X86::ATOMMAX32:
14513 case X86::ATOMMAX64:
14514 case X86::ATOMMIN8:
14515 case X86::ATOMMIN16:
14516 case X86::ATOMMIN32:
14517 case X86::ATOMMIN64:
14518 case X86::ATOMUMAX8:
14519 case X86::ATOMUMAX16:
14520 case X86::ATOMUMAX32:
14521 case X86::ATOMUMAX64:
14522 case X86::ATOMUMIN8:
14523 case X86::ATOMUMIN16:
14524 case X86::ATOMUMIN32:
14525 case X86::ATOMUMIN64: {
14527 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14529 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14533 if (Subtarget->hasCMov()) {
14534 if (VT != MVT::i8) {
14536 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14540 // Promote i8 to i32 to use CMOV32
14541 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14542 const TargetRegisterClass *RC32 =
14543 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14544 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14545 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14546 unsigned Tmp = MRI.createVirtualRegister(RC32);
14548 unsigned Undef = MRI.createVirtualRegister(RC32);
14549 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14551 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14554 .addImm(X86::sub_8bit);
14555 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14558 .addImm(X86::sub_8bit);
14560 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14564 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14565 .addReg(Tmp, 0, X86::sub_8bit);
14568 // Use pseudo select and lower them.
14569 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14570 "Invalid atomic-load-op transformation!");
14571 unsigned SelOpc = getPseudoCMOVOpc(VT);
14572 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14573 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14574 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14575 .addReg(SrcReg).addReg(t4)
14577 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14578 // Replace the original PHI node as mainMBB is changed after CMOV
14580 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14581 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14582 Phi->eraseFromParent();
14588 // Copy PhyReg back from virtual register.
14589 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14592 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14593 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14594 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14596 NewMO.setIsKill(false);
14597 MIB.addOperand(NewMO);
14600 MIB.setMemRefs(MMOBegin, MMOEnd);
14602 // Copy PhyReg back to virtual register.
14603 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14606 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14608 mainMBB->addSuccessor(origMainMBB);
14609 mainMBB->addSuccessor(sinkMBB);
14612 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14613 TII->get(TargetOpcode::COPY), DstReg)
14616 MI->eraseFromParent();
14620 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14621 // instructions. They will be translated into a spin-loop or compare-exchange
14625 // dst = atomic-fetch-op MI.addr, MI.val
14631 // t1L = LOAD [MI.addr + 0]
14632 // t1H = LOAD [MI.addr + 4]
14634 // t4L = phi(t1L, t3L / loop)
14635 // t4H = phi(t1H, t3H / loop)
14636 // t2L = OP MI.val.lo, t4L
14637 // t2H = OP MI.val.hi, t4H
14642 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14650 MachineBasicBlock *
14651 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14652 MachineBasicBlock *MBB) const {
14653 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14654 DebugLoc DL = MI->getDebugLoc();
14656 MachineFunction *MF = MBB->getParent();
14657 MachineRegisterInfo &MRI = MF->getRegInfo();
14659 const BasicBlock *BB = MBB->getBasicBlock();
14660 MachineFunction::iterator I = MBB;
14663 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14664 "Unexpected number of operands");
14666 assert(MI->hasOneMemOperand() &&
14667 "Expected atomic-load-op32 to have one memoperand");
14669 // Memory Reference
14670 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14671 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14673 unsigned DstLoReg, DstHiReg;
14674 unsigned SrcLoReg, SrcHiReg;
14675 unsigned MemOpndSlot;
14677 unsigned CurOp = 0;
14679 DstLoReg = MI->getOperand(CurOp++).getReg();
14680 DstHiReg = MI->getOperand(CurOp++).getReg();
14681 MemOpndSlot = CurOp;
14682 CurOp += X86::AddrNumOperands;
14683 SrcLoReg = MI->getOperand(CurOp++).getReg();
14684 SrcHiReg = MI->getOperand(CurOp++).getReg();
14686 const TargetRegisterClass *RC = &X86::GR32RegClass;
14687 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14689 unsigned t1L = MRI.createVirtualRegister(RC);
14690 unsigned t1H = MRI.createVirtualRegister(RC);
14691 unsigned t2L = MRI.createVirtualRegister(RC);
14692 unsigned t2H = MRI.createVirtualRegister(RC);
14693 unsigned t3L = MRI.createVirtualRegister(RC);
14694 unsigned t3H = MRI.createVirtualRegister(RC);
14695 unsigned t4L = MRI.createVirtualRegister(RC);
14696 unsigned t4H = MRI.createVirtualRegister(RC);
14698 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14699 unsigned LOADOpc = X86::MOV32rm;
14701 // For the atomic load-arith operator, we generate
14704 // t1L = LOAD [MI.addr + 0]
14705 // t1H = LOAD [MI.addr + 4]
14707 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14708 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14709 // t2L = OP MI.val.lo, t4L
14710 // t2H = OP MI.val.hi, t4H
14713 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14721 MachineBasicBlock *thisMBB = MBB;
14722 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14723 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14724 MF->insert(I, mainMBB);
14725 MF->insert(I, sinkMBB);
14727 MachineInstrBuilder MIB;
14729 // Transfer the remainder of BB and its successor edges to sinkMBB.
14730 sinkMBB->splice(sinkMBB->begin(), MBB,
14731 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14732 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14736 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14737 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14738 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14740 NewMO.setIsKill(false);
14741 MIB.addOperand(NewMO);
14743 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14744 unsigned flags = (*MMOI)->getFlags();
14745 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14746 MachineMemOperand *MMO =
14747 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14748 (*MMOI)->getSize(),
14749 (*MMOI)->getBaseAlignment(),
14750 (*MMOI)->getTBAAInfo(),
14751 (*MMOI)->getRanges());
14752 MIB.addMemOperand(MMO);
14754 MachineInstr *LowMI = MIB;
14757 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14758 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14759 if (i == X86::AddrDisp) {
14760 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14762 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14764 NewMO.setIsKill(false);
14765 MIB.addOperand(NewMO);
14768 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14770 thisMBB->addSuccessor(mainMBB);
14773 MachineBasicBlock *origMainMBB = mainMBB;
14776 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14777 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14778 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14779 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14781 unsigned Opc = MI->getOpcode();
14784 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14785 case X86::ATOMAND6432:
14786 case X86::ATOMOR6432:
14787 case X86::ATOMXOR6432:
14788 case X86::ATOMADD6432:
14789 case X86::ATOMSUB6432: {
14791 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14792 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14794 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14798 case X86::ATOMNAND6432: {
14799 unsigned HiOpc, NOTOpc;
14800 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14801 unsigned TmpL = MRI.createVirtualRegister(RC);
14802 unsigned TmpH = MRI.createVirtualRegister(RC);
14803 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14805 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14807 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14808 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14811 case X86::ATOMMAX6432:
14812 case X86::ATOMMIN6432:
14813 case X86::ATOMUMAX6432:
14814 case X86::ATOMUMIN6432: {
14816 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14817 unsigned cL = MRI.createVirtualRegister(RC8);
14818 unsigned cH = MRI.createVirtualRegister(RC8);
14819 unsigned cL32 = MRI.createVirtualRegister(RC);
14820 unsigned cH32 = MRI.createVirtualRegister(RC);
14821 unsigned cc = MRI.createVirtualRegister(RC);
14822 // cl := cmp src_lo, lo
14823 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14824 .addReg(SrcLoReg).addReg(t4L);
14825 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14826 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14827 // ch := cmp src_hi, hi
14828 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14829 .addReg(SrcHiReg).addReg(t4H);
14830 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14831 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14832 // cc := if (src_hi == hi) ? cl : ch;
14833 if (Subtarget->hasCMov()) {
14834 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14835 .addReg(cH32).addReg(cL32);
14837 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14838 .addReg(cH32).addReg(cL32)
14839 .addImm(X86::COND_E);
14840 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14842 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14843 if (Subtarget->hasCMov()) {
14844 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14845 .addReg(SrcLoReg).addReg(t4L);
14846 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14847 .addReg(SrcHiReg).addReg(t4H);
14849 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14850 .addReg(SrcLoReg).addReg(t4L)
14851 .addImm(X86::COND_NE);
14852 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14853 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14854 // 2nd CMOV lowering.
14855 mainMBB->addLiveIn(X86::EFLAGS);
14856 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14857 .addReg(SrcHiReg).addReg(t4H)
14858 .addImm(X86::COND_NE);
14859 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14860 // Replace the original PHI node as mainMBB is changed after CMOV
14862 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14863 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14864 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14865 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14866 PhiL->eraseFromParent();
14867 PhiH->eraseFromParent();
14871 case X86::ATOMSWAP6432: {
14873 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14874 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14875 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14880 // Copy EDX:EAX back from HiReg:LoReg
14881 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14882 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14883 // Copy ECX:EBX from t1H:t1L
14884 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14885 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14887 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14888 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14889 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14891 NewMO.setIsKill(false);
14892 MIB.addOperand(NewMO);
14894 MIB.setMemRefs(MMOBegin, MMOEnd);
14896 // Copy EDX:EAX back to t3H:t3L
14897 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14898 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14900 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14902 mainMBB->addSuccessor(origMainMBB);
14903 mainMBB->addSuccessor(sinkMBB);
14906 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14907 TII->get(TargetOpcode::COPY), DstLoReg)
14909 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14910 TII->get(TargetOpcode::COPY), DstHiReg)
14913 MI->eraseFromParent();
14917 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14918 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14919 // in the .td file.
14920 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14921 const TargetInstrInfo *TII) {
14923 switch (MI->getOpcode()) {
14924 default: llvm_unreachable("illegal opcode!");
14925 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14926 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14927 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14928 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14929 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14930 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14931 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14932 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14935 DebugLoc dl = MI->getDebugLoc();
14936 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14938 unsigned NumArgs = MI->getNumOperands();
14939 for (unsigned i = 1; i < NumArgs; ++i) {
14940 MachineOperand &Op = MI->getOperand(i);
14941 if (!(Op.isReg() && Op.isImplicit()))
14942 MIB.addOperand(Op);
14944 if (MI->hasOneMemOperand())
14945 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14947 BuildMI(*BB, MI, dl,
14948 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14949 .addReg(X86::XMM0);
14951 MI->eraseFromParent();
14955 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14956 // defs in an instruction pattern
14957 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14958 const TargetInstrInfo *TII) {
14960 switch (MI->getOpcode()) {
14961 default: llvm_unreachable("illegal opcode!");
14962 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14963 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14964 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14965 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14966 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14967 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14968 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14969 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14972 DebugLoc dl = MI->getDebugLoc();
14973 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14975 unsigned NumArgs = MI->getNumOperands(); // remove the results
14976 for (unsigned i = 1; i < NumArgs; ++i) {
14977 MachineOperand &Op = MI->getOperand(i);
14978 if (!(Op.isReg() && Op.isImplicit()))
14979 MIB.addOperand(Op);
14981 if (MI->hasOneMemOperand())
14982 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14984 BuildMI(*BB, MI, dl,
14985 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14988 MI->eraseFromParent();
14992 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14993 const TargetInstrInfo *TII,
14994 const X86Subtarget* Subtarget) {
14995 DebugLoc dl = MI->getDebugLoc();
14997 // Address into RAX/EAX, other two args into ECX, EDX.
14998 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14999 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15000 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15001 for (int i = 0; i < X86::AddrNumOperands; ++i)
15002 MIB.addOperand(MI->getOperand(i));
15004 unsigned ValOps = X86::AddrNumOperands;
15005 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15006 .addReg(MI->getOperand(ValOps).getReg());
15007 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15008 .addReg(MI->getOperand(ValOps+1).getReg());
15010 // The instruction doesn't actually take any operands though.
15011 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15013 MI->eraseFromParent(); // The pseudo is gone now.
15017 MachineBasicBlock *
15018 X86TargetLowering::EmitVAARG64WithCustomInserter(
15020 MachineBasicBlock *MBB) const {
15021 // Emit va_arg instruction on X86-64.
15023 // Operands to this pseudo-instruction:
15024 // 0 ) Output : destination address (reg)
15025 // 1-5) Input : va_list address (addr, i64mem)
15026 // 6 ) ArgSize : Size (in bytes) of vararg type
15027 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15028 // 8 ) Align : Alignment of type
15029 // 9 ) EFLAGS (implicit-def)
15031 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15032 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15034 unsigned DestReg = MI->getOperand(0).getReg();
15035 MachineOperand &Base = MI->getOperand(1);
15036 MachineOperand &Scale = MI->getOperand(2);
15037 MachineOperand &Index = MI->getOperand(3);
15038 MachineOperand &Disp = MI->getOperand(4);
15039 MachineOperand &Segment = MI->getOperand(5);
15040 unsigned ArgSize = MI->getOperand(6).getImm();
15041 unsigned ArgMode = MI->getOperand(7).getImm();
15042 unsigned Align = MI->getOperand(8).getImm();
15044 // Memory Reference
15045 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15046 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15047 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15049 // Machine Information
15050 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15051 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15052 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15053 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15054 DebugLoc DL = MI->getDebugLoc();
15056 // struct va_list {
15059 // i64 overflow_area (address)
15060 // i64 reg_save_area (address)
15062 // sizeof(va_list) = 24
15063 // alignment(va_list) = 8
15065 unsigned TotalNumIntRegs = 6;
15066 unsigned TotalNumXMMRegs = 8;
15067 bool UseGPOffset = (ArgMode == 1);
15068 bool UseFPOffset = (ArgMode == 2);
15069 unsigned MaxOffset = TotalNumIntRegs * 8 +
15070 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15072 /* Align ArgSize to a multiple of 8 */
15073 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15074 bool NeedsAlign = (Align > 8);
15076 MachineBasicBlock *thisMBB = MBB;
15077 MachineBasicBlock *overflowMBB;
15078 MachineBasicBlock *offsetMBB;
15079 MachineBasicBlock *endMBB;
15081 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15082 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15083 unsigned OffsetReg = 0;
15085 if (!UseGPOffset && !UseFPOffset) {
15086 // If we only pull from the overflow region, we don't create a branch.
15087 // We don't need to alter control flow.
15088 OffsetDestReg = 0; // unused
15089 OverflowDestReg = DestReg;
15092 overflowMBB = thisMBB;
15095 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15096 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15097 // If not, pull from overflow_area. (branch to overflowMBB)
15102 // offsetMBB overflowMBB
15107 // Registers for the PHI in endMBB
15108 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15109 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15111 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15112 MachineFunction *MF = MBB->getParent();
15113 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15114 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15115 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15117 MachineFunction::iterator MBBIter = MBB;
15120 // Insert the new basic blocks
15121 MF->insert(MBBIter, offsetMBB);
15122 MF->insert(MBBIter, overflowMBB);
15123 MF->insert(MBBIter, endMBB);
15125 // Transfer the remainder of MBB and its successor edges to endMBB.
15126 endMBB->splice(endMBB->begin(), thisMBB,
15127 llvm::next(MachineBasicBlock::iterator(MI)),
15129 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15131 // Make offsetMBB and overflowMBB successors of thisMBB
15132 thisMBB->addSuccessor(offsetMBB);
15133 thisMBB->addSuccessor(overflowMBB);
15135 // endMBB is a successor of both offsetMBB and overflowMBB
15136 offsetMBB->addSuccessor(endMBB);
15137 overflowMBB->addSuccessor(endMBB);
15139 // Load the offset value into a register
15140 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15141 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15145 .addDisp(Disp, UseFPOffset ? 4 : 0)
15146 .addOperand(Segment)
15147 .setMemRefs(MMOBegin, MMOEnd);
15149 // Check if there is enough room left to pull this argument.
15150 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15152 .addImm(MaxOffset + 8 - ArgSizeA8);
15154 // Branch to "overflowMBB" if offset >= max
15155 // Fall through to "offsetMBB" otherwise
15156 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15157 .addMBB(overflowMBB);
15160 // In offsetMBB, emit code to use the reg_save_area.
15162 assert(OffsetReg != 0);
15164 // Read the reg_save_area address.
15165 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15166 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15171 .addOperand(Segment)
15172 .setMemRefs(MMOBegin, MMOEnd);
15174 // Zero-extend the offset
15175 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15176 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15179 .addImm(X86::sub_32bit);
15181 // Add the offset to the reg_save_area to get the final address.
15182 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15183 .addReg(OffsetReg64)
15184 .addReg(RegSaveReg);
15186 // Compute the offset for the next argument
15187 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15188 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15190 .addImm(UseFPOffset ? 16 : 8);
15192 // Store it back into the va_list.
15193 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15197 .addDisp(Disp, UseFPOffset ? 4 : 0)
15198 .addOperand(Segment)
15199 .addReg(NextOffsetReg)
15200 .setMemRefs(MMOBegin, MMOEnd);
15203 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15208 // Emit code to use overflow area
15211 // Load the overflow_area address into a register.
15212 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15213 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15218 .addOperand(Segment)
15219 .setMemRefs(MMOBegin, MMOEnd);
15221 // If we need to align it, do so. Otherwise, just copy the address
15222 // to OverflowDestReg.
15224 // Align the overflow address
15225 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15226 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15228 // aligned_addr = (addr + (align-1)) & ~(align-1)
15229 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15230 .addReg(OverflowAddrReg)
15233 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15235 .addImm(~(uint64_t)(Align-1));
15237 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15238 .addReg(OverflowAddrReg);
15241 // Compute the next overflow address after this argument.
15242 // (the overflow address should be kept 8-byte aligned)
15243 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15244 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15245 .addReg(OverflowDestReg)
15246 .addImm(ArgSizeA8);
15248 // Store the new overflow address.
15249 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15254 .addOperand(Segment)
15255 .addReg(NextAddrReg)
15256 .setMemRefs(MMOBegin, MMOEnd);
15258 // If we branched, emit the PHI to the front of endMBB.
15260 BuildMI(*endMBB, endMBB->begin(), DL,
15261 TII->get(X86::PHI), DestReg)
15262 .addReg(OffsetDestReg).addMBB(offsetMBB)
15263 .addReg(OverflowDestReg).addMBB(overflowMBB);
15266 // Erase the pseudo instruction
15267 MI->eraseFromParent();
15272 MachineBasicBlock *
15273 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15275 MachineBasicBlock *MBB) const {
15276 // Emit code to save XMM registers to the stack. The ABI says that the
15277 // number of registers to save is given in %al, so it's theoretically
15278 // possible to do an indirect jump trick to avoid saving all of them,
15279 // however this code takes a simpler approach and just executes all
15280 // of the stores if %al is non-zero. It's less code, and it's probably
15281 // easier on the hardware branch predictor, and stores aren't all that
15282 // expensive anyway.
15284 // Create the new basic blocks. One block contains all the XMM stores,
15285 // and one block is the final destination regardless of whether any
15286 // stores were performed.
15287 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15288 MachineFunction *F = MBB->getParent();
15289 MachineFunction::iterator MBBIter = MBB;
15291 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15292 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15293 F->insert(MBBIter, XMMSaveMBB);
15294 F->insert(MBBIter, EndMBB);
15296 // Transfer the remainder of MBB and its successor edges to EndMBB.
15297 EndMBB->splice(EndMBB->begin(), MBB,
15298 llvm::next(MachineBasicBlock::iterator(MI)),
15300 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15302 // The original block will now fall through to the XMM save block.
15303 MBB->addSuccessor(XMMSaveMBB);
15304 // The XMMSaveMBB will fall through to the end block.
15305 XMMSaveMBB->addSuccessor(EndMBB);
15307 // Now add the instructions.
15308 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15309 DebugLoc DL = MI->getDebugLoc();
15311 unsigned CountReg = MI->getOperand(0).getReg();
15312 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15313 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15315 if (!Subtarget->isTargetWin64()) {
15316 // If %al is 0, branch around the XMM save block.
15317 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15318 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15319 MBB->addSuccessor(EndMBB);
15322 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15323 // In the XMM save block, save all the XMM argument registers.
15324 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15325 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15326 MachineMemOperand *MMO =
15327 F->getMachineMemOperand(
15328 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15329 MachineMemOperand::MOStore,
15330 /*Size=*/16, /*Align=*/16);
15331 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15332 .addFrameIndex(RegSaveFrameIndex)
15333 .addImm(/*Scale=*/1)
15334 .addReg(/*IndexReg=*/0)
15335 .addImm(/*Disp=*/Offset)
15336 .addReg(/*Segment=*/0)
15337 .addReg(MI->getOperand(i).getReg())
15338 .addMemOperand(MMO);
15341 MI->eraseFromParent(); // The pseudo instruction is gone now.
15346 // The EFLAGS operand of SelectItr might be missing a kill marker
15347 // because there were multiple uses of EFLAGS, and ISel didn't know
15348 // which to mark. Figure out whether SelectItr should have had a
15349 // kill marker, and set it if it should. Returns the correct kill
15351 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15352 MachineBasicBlock* BB,
15353 const TargetRegisterInfo* TRI) {
15354 // Scan forward through BB for a use/def of EFLAGS.
15355 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15356 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15357 const MachineInstr& mi = *miI;
15358 if (mi.readsRegister(X86::EFLAGS))
15360 if (mi.definesRegister(X86::EFLAGS))
15361 break; // Should have kill-flag - update below.
15364 // If we hit the end of the block, check whether EFLAGS is live into a
15366 if (miI == BB->end()) {
15367 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15368 sEnd = BB->succ_end();
15369 sItr != sEnd; ++sItr) {
15370 MachineBasicBlock* succ = *sItr;
15371 if (succ->isLiveIn(X86::EFLAGS))
15376 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15377 // out. SelectMI should have a kill flag on EFLAGS.
15378 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15382 MachineBasicBlock *
15383 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15384 MachineBasicBlock *BB) const {
15385 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15386 DebugLoc DL = MI->getDebugLoc();
15388 // To "insert" a SELECT_CC instruction, we actually have to insert the
15389 // diamond control-flow pattern. The incoming instruction knows the
15390 // destination vreg to set, the condition code register to branch on, the
15391 // true/false values to select between, and a branch opcode to use.
15392 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15393 MachineFunction::iterator It = BB;
15399 // cmpTY ccX, r1, r2
15401 // fallthrough --> copy0MBB
15402 MachineBasicBlock *thisMBB = BB;
15403 MachineFunction *F = BB->getParent();
15404 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15405 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15406 F->insert(It, copy0MBB);
15407 F->insert(It, sinkMBB);
15409 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15410 // live into the sink and copy blocks.
15411 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15412 if (!MI->killsRegister(X86::EFLAGS) &&
15413 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15414 copy0MBB->addLiveIn(X86::EFLAGS);
15415 sinkMBB->addLiveIn(X86::EFLAGS);
15418 // Transfer the remainder of BB and its successor edges to sinkMBB.
15419 sinkMBB->splice(sinkMBB->begin(), BB,
15420 llvm::next(MachineBasicBlock::iterator(MI)),
15422 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15424 // Add the true and fallthrough blocks as its successors.
15425 BB->addSuccessor(copy0MBB);
15426 BB->addSuccessor(sinkMBB);
15428 // Create the conditional branch instruction.
15430 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15431 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15434 // %FalseValue = ...
15435 // # fallthrough to sinkMBB
15436 copy0MBB->addSuccessor(sinkMBB);
15439 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15441 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15442 TII->get(X86::PHI), MI->getOperand(0).getReg())
15443 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15444 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15446 MI->eraseFromParent(); // The pseudo instruction is gone now.
15450 MachineBasicBlock *
15451 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15452 bool Is64Bit) const {
15453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15454 DebugLoc DL = MI->getDebugLoc();
15455 MachineFunction *MF = BB->getParent();
15456 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15458 assert(getTargetMachine().Options.EnableSegmentedStacks);
15460 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15461 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15464 // ... [Till the alloca]
15465 // If stacklet is not large enough, jump to mallocMBB
15468 // Allocate by subtracting from RSP
15469 // Jump to continueMBB
15472 // Allocate by call to runtime
15476 // [rest of original BB]
15479 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15480 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15481 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15483 MachineRegisterInfo &MRI = MF->getRegInfo();
15484 const TargetRegisterClass *AddrRegClass =
15485 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15487 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15488 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15489 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15490 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15491 sizeVReg = MI->getOperand(1).getReg(),
15492 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15494 MachineFunction::iterator MBBIter = BB;
15497 MF->insert(MBBIter, bumpMBB);
15498 MF->insert(MBBIter, mallocMBB);
15499 MF->insert(MBBIter, continueMBB);
15501 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15502 (MachineBasicBlock::iterator(MI)), BB->end());
15503 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15505 // Add code to the main basic block to check if the stack limit has been hit,
15506 // and if so, jump to mallocMBB otherwise to bumpMBB.
15507 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15508 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15509 .addReg(tmpSPVReg).addReg(sizeVReg);
15510 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15511 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15512 .addReg(SPLimitVReg);
15513 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15515 // bumpMBB simply decreases the stack pointer, since we know the current
15516 // stacklet has enough space.
15517 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15518 .addReg(SPLimitVReg);
15519 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15520 .addReg(SPLimitVReg);
15521 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15523 // Calls into a routine in libgcc to allocate more space from the heap.
15524 const uint32_t *RegMask =
15525 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15527 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15529 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15530 .addExternalSymbol("__morestack_allocate_stack_space")
15531 .addRegMask(RegMask)
15532 .addReg(X86::RDI, RegState::Implicit)
15533 .addReg(X86::RAX, RegState::ImplicitDefine);
15535 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15537 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15538 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15539 .addExternalSymbol("__morestack_allocate_stack_space")
15540 .addRegMask(RegMask)
15541 .addReg(X86::EAX, RegState::ImplicitDefine);
15545 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15548 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15549 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15550 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15552 // Set up the CFG correctly.
15553 BB->addSuccessor(bumpMBB);
15554 BB->addSuccessor(mallocMBB);
15555 mallocMBB->addSuccessor(continueMBB);
15556 bumpMBB->addSuccessor(continueMBB);
15558 // Take care of the PHI nodes.
15559 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15560 MI->getOperand(0).getReg())
15561 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15562 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15564 // Delete the original pseudo instruction.
15565 MI->eraseFromParent();
15568 return continueMBB;
15571 MachineBasicBlock *
15572 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15573 MachineBasicBlock *BB) const {
15574 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15575 DebugLoc DL = MI->getDebugLoc();
15577 assert(!Subtarget->isTargetMacho());
15579 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15580 // non-trivial part is impdef of ESP.
15582 if (Subtarget->isTargetWin64()) {
15583 if (Subtarget->isTargetCygMing()) {
15584 // ___chkstk(Mingw64):
15585 // Clobbers R10, R11, RAX and EFLAGS.
15587 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15588 .addExternalSymbol("___chkstk")
15589 .addReg(X86::RAX, RegState::Implicit)
15590 .addReg(X86::RSP, RegState::Implicit)
15591 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15592 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15593 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15595 // __chkstk(MSVCRT): does not update stack pointer.
15596 // Clobbers R10, R11 and EFLAGS.
15597 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15598 .addExternalSymbol("__chkstk")
15599 .addReg(X86::RAX, RegState::Implicit)
15600 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15601 // RAX has the offset to be subtracted from RSP.
15602 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15607 const char *StackProbeSymbol =
15608 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15610 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15611 .addExternalSymbol(StackProbeSymbol)
15612 .addReg(X86::EAX, RegState::Implicit)
15613 .addReg(X86::ESP, RegState::Implicit)
15614 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15615 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15616 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15619 MI->eraseFromParent(); // The pseudo instruction is gone now.
15623 MachineBasicBlock *
15624 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15625 MachineBasicBlock *BB) const {
15626 // This is pretty easy. We're taking the value that we received from
15627 // our load from the relocation, sticking it in either RDI (x86-64)
15628 // or EAX and doing an indirect call. The return value will then
15629 // be in the normal return register.
15630 const X86InstrInfo *TII
15631 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15632 DebugLoc DL = MI->getDebugLoc();
15633 MachineFunction *F = BB->getParent();
15635 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15636 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15638 // Get a register mask for the lowered call.
15639 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15640 // proper register mask.
15641 const uint32_t *RegMask =
15642 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15643 if (Subtarget->is64Bit()) {
15644 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15645 TII->get(X86::MOV64rm), X86::RDI)
15647 .addImm(0).addReg(0)
15648 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15649 MI->getOperand(3).getTargetFlags())
15651 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15652 addDirectMem(MIB, X86::RDI);
15653 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15654 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15655 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15656 TII->get(X86::MOV32rm), X86::EAX)
15658 .addImm(0).addReg(0)
15659 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15660 MI->getOperand(3).getTargetFlags())
15662 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15663 addDirectMem(MIB, X86::EAX);
15664 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15666 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15667 TII->get(X86::MOV32rm), X86::EAX)
15668 .addReg(TII->getGlobalBaseReg(F))
15669 .addImm(0).addReg(0)
15670 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15671 MI->getOperand(3).getTargetFlags())
15673 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15674 addDirectMem(MIB, X86::EAX);
15675 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15678 MI->eraseFromParent(); // The pseudo instruction is gone now.
15682 MachineBasicBlock *
15683 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15684 MachineBasicBlock *MBB) const {
15685 DebugLoc DL = MI->getDebugLoc();
15686 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15688 MachineFunction *MF = MBB->getParent();
15689 MachineRegisterInfo &MRI = MF->getRegInfo();
15691 const BasicBlock *BB = MBB->getBasicBlock();
15692 MachineFunction::iterator I = MBB;
15695 // Memory Reference
15696 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15697 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15700 unsigned MemOpndSlot = 0;
15702 unsigned CurOp = 0;
15704 DstReg = MI->getOperand(CurOp++).getReg();
15705 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15706 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15707 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15708 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15710 MemOpndSlot = CurOp;
15712 MVT PVT = getPointerTy();
15713 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15714 "Invalid Pointer Size!");
15716 // For v = setjmp(buf), we generate
15719 // buf[LabelOffset] = restoreMBB
15720 // SjLjSetup restoreMBB
15726 // v = phi(main, restore)
15731 MachineBasicBlock *thisMBB = MBB;
15732 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15733 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15734 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15735 MF->insert(I, mainMBB);
15736 MF->insert(I, sinkMBB);
15737 MF->push_back(restoreMBB);
15739 MachineInstrBuilder MIB;
15741 // Transfer the remainder of BB and its successor edges to sinkMBB.
15742 sinkMBB->splice(sinkMBB->begin(), MBB,
15743 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15744 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15747 unsigned PtrStoreOpc = 0;
15748 unsigned LabelReg = 0;
15749 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15750 Reloc::Model RM = getTargetMachine().getRelocationModel();
15751 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15752 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15754 // Prepare IP either in reg or imm.
15755 if (!UseImmLabel) {
15756 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15757 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15758 LabelReg = MRI.createVirtualRegister(PtrRC);
15759 if (Subtarget->is64Bit()) {
15760 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15764 .addMBB(restoreMBB)
15767 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15768 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15769 .addReg(XII->getGlobalBaseReg(MF))
15772 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15776 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15778 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15779 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15780 if (i == X86::AddrDisp)
15781 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15783 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15786 MIB.addReg(LabelReg);
15788 MIB.addMBB(restoreMBB);
15789 MIB.setMemRefs(MMOBegin, MMOEnd);
15791 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15792 .addMBB(restoreMBB);
15794 const X86RegisterInfo *RegInfo =
15795 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15796 MIB.addRegMask(RegInfo->getNoPreservedMask());
15797 thisMBB->addSuccessor(mainMBB);
15798 thisMBB->addSuccessor(restoreMBB);
15802 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15803 mainMBB->addSuccessor(sinkMBB);
15806 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15807 TII->get(X86::PHI), DstReg)
15808 .addReg(mainDstReg).addMBB(mainMBB)
15809 .addReg(restoreDstReg).addMBB(restoreMBB);
15812 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15813 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15814 restoreMBB->addSuccessor(sinkMBB);
15816 MI->eraseFromParent();
15820 MachineBasicBlock *
15821 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15822 MachineBasicBlock *MBB) const {
15823 DebugLoc DL = MI->getDebugLoc();
15824 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15826 MachineFunction *MF = MBB->getParent();
15827 MachineRegisterInfo &MRI = MF->getRegInfo();
15829 // Memory Reference
15830 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15831 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15833 MVT PVT = getPointerTy();
15834 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15835 "Invalid Pointer Size!");
15837 const TargetRegisterClass *RC =
15838 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15839 unsigned Tmp = MRI.createVirtualRegister(RC);
15840 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15841 const X86RegisterInfo *RegInfo =
15842 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15843 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15844 unsigned SP = RegInfo->getStackRegister();
15846 MachineInstrBuilder MIB;
15848 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15849 const int64_t SPOffset = 2 * PVT.getStoreSize();
15851 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15852 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15855 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15856 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15857 MIB.addOperand(MI->getOperand(i));
15858 MIB.setMemRefs(MMOBegin, MMOEnd);
15860 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15861 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15862 if (i == X86::AddrDisp)
15863 MIB.addDisp(MI->getOperand(i), LabelOffset);
15865 MIB.addOperand(MI->getOperand(i));
15867 MIB.setMemRefs(MMOBegin, MMOEnd);
15869 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15870 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15871 if (i == X86::AddrDisp)
15872 MIB.addDisp(MI->getOperand(i), SPOffset);
15874 MIB.addOperand(MI->getOperand(i));
15876 MIB.setMemRefs(MMOBegin, MMOEnd);
15878 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15880 MI->eraseFromParent();
15884 MachineBasicBlock *
15885 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15886 MachineBasicBlock *BB) const {
15887 switch (MI->getOpcode()) {
15888 default: llvm_unreachable("Unexpected instr type to insert");
15889 case X86::TAILJMPd64:
15890 case X86::TAILJMPr64:
15891 case X86::TAILJMPm64:
15892 llvm_unreachable("TAILJMP64 would not be touched here.");
15893 case X86::TCRETURNdi64:
15894 case X86::TCRETURNri64:
15895 case X86::TCRETURNmi64:
15897 case X86::WIN_ALLOCA:
15898 return EmitLoweredWinAlloca(MI, BB);
15899 case X86::SEG_ALLOCA_32:
15900 return EmitLoweredSegAlloca(MI, BB, false);
15901 case X86::SEG_ALLOCA_64:
15902 return EmitLoweredSegAlloca(MI, BB, true);
15903 case X86::TLSCall_32:
15904 case X86::TLSCall_64:
15905 return EmitLoweredTLSCall(MI, BB);
15906 case X86::CMOV_GR8:
15907 case X86::CMOV_FR32:
15908 case X86::CMOV_FR64:
15909 case X86::CMOV_V4F32:
15910 case X86::CMOV_V2F64:
15911 case X86::CMOV_V2I64:
15912 case X86::CMOV_V8F32:
15913 case X86::CMOV_V4F64:
15914 case X86::CMOV_V4I64:
15915 case X86::CMOV_V16F32:
15916 case X86::CMOV_V8F64:
15917 case X86::CMOV_V8I64:
15918 case X86::CMOV_GR16:
15919 case X86::CMOV_GR32:
15920 case X86::CMOV_RFP32:
15921 case X86::CMOV_RFP64:
15922 case X86::CMOV_RFP80:
15923 return EmitLoweredSelect(MI, BB);
15925 case X86::FP32_TO_INT16_IN_MEM:
15926 case X86::FP32_TO_INT32_IN_MEM:
15927 case X86::FP32_TO_INT64_IN_MEM:
15928 case X86::FP64_TO_INT16_IN_MEM:
15929 case X86::FP64_TO_INT32_IN_MEM:
15930 case X86::FP64_TO_INT64_IN_MEM:
15931 case X86::FP80_TO_INT16_IN_MEM:
15932 case X86::FP80_TO_INT32_IN_MEM:
15933 case X86::FP80_TO_INT64_IN_MEM: {
15934 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15935 DebugLoc DL = MI->getDebugLoc();
15937 // Change the floating point control register to use "round towards zero"
15938 // mode when truncating to an integer value.
15939 MachineFunction *F = BB->getParent();
15940 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15941 addFrameReference(BuildMI(*BB, MI, DL,
15942 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15944 // Load the old value of the high byte of the control word...
15946 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15947 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15950 // Set the high part to be round to zero...
15951 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15954 // Reload the modified control word now...
15955 addFrameReference(BuildMI(*BB, MI, DL,
15956 TII->get(X86::FLDCW16m)), CWFrameIdx);
15958 // Restore the memory image of control word to original value
15959 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15962 // Get the X86 opcode to use.
15964 switch (MI->getOpcode()) {
15965 default: llvm_unreachable("illegal opcode!");
15966 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15967 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15968 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15969 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15970 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15971 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15972 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15973 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15974 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15978 MachineOperand &Op = MI->getOperand(0);
15980 AM.BaseType = X86AddressMode::RegBase;
15981 AM.Base.Reg = Op.getReg();
15983 AM.BaseType = X86AddressMode::FrameIndexBase;
15984 AM.Base.FrameIndex = Op.getIndex();
15986 Op = MI->getOperand(1);
15988 AM.Scale = Op.getImm();
15989 Op = MI->getOperand(2);
15991 AM.IndexReg = Op.getImm();
15992 Op = MI->getOperand(3);
15993 if (Op.isGlobal()) {
15994 AM.GV = Op.getGlobal();
15996 AM.Disp = Op.getImm();
15998 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15999 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16001 // Reload the original control word now.
16002 addFrameReference(BuildMI(*BB, MI, DL,
16003 TII->get(X86::FLDCW16m)), CWFrameIdx);
16005 MI->eraseFromParent(); // The pseudo instruction is gone now.
16008 // String/text processing lowering.
16009 case X86::PCMPISTRM128REG:
16010 case X86::VPCMPISTRM128REG:
16011 case X86::PCMPISTRM128MEM:
16012 case X86::VPCMPISTRM128MEM:
16013 case X86::PCMPESTRM128REG:
16014 case X86::VPCMPESTRM128REG:
16015 case X86::PCMPESTRM128MEM:
16016 case X86::VPCMPESTRM128MEM:
16017 assert(Subtarget->hasSSE42() &&
16018 "Target must have SSE4.2 or AVX features enabled");
16019 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16021 // String/text processing lowering.
16022 case X86::PCMPISTRIREG:
16023 case X86::VPCMPISTRIREG:
16024 case X86::PCMPISTRIMEM:
16025 case X86::VPCMPISTRIMEM:
16026 case X86::PCMPESTRIREG:
16027 case X86::VPCMPESTRIREG:
16028 case X86::PCMPESTRIMEM:
16029 case X86::VPCMPESTRIMEM:
16030 assert(Subtarget->hasSSE42() &&
16031 "Target must have SSE4.2 or AVX features enabled");
16032 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16034 // Thread synchronization.
16036 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16040 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16042 // Atomic Lowering.
16043 case X86::ATOMAND8:
16044 case X86::ATOMAND16:
16045 case X86::ATOMAND32:
16046 case X86::ATOMAND64:
16049 case X86::ATOMOR16:
16050 case X86::ATOMOR32:
16051 case X86::ATOMOR64:
16053 case X86::ATOMXOR16:
16054 case X86::ATOMXOR8:
16055 case X86::ATOMXOR32:
16056 case X86::ATOMXOR64:
16058 case X86::ATOMNAND8:
16059 case X86::ATOMNAND16:
16060 case X86::ATOMNAND32:
16061 case X86::ATOMNAND64:
16063 case X86::ATOMMAX8:
16064 case X86::ATOMMAX16:
16065 case X86::ATOMMAX32:
16066 case X86::ATOMMAX64:
16068 case X86::ATOMMIN8:
16069 case X86::ATOMMIN16:
16070 case X86::ATOMMIN32:
16071 case X86::ATOMMIN64:
16073 case X86::ATOMUMAX8:
16074 case X86::ATOMUMAX16:
16075 case X86::ATOMUMAX32:
16076 case X86::ATOMUMAX64:
16078 case X86::ATOMUMIN8:
16079 case X86::ATOMUMIN16:
16080 case X86::ATOMUMIN32:
16081 case X86::ATOMUMIN64:
16082 return EmitAtomicLoadArith(MI, BB);
16084 // This group does 64-bit operations on a 32-bit host.
16085 case X86::ATOMAND6432:
16086 case X86::ATOMOR6432:
16087 case X86::ATOMXOR6432:
16088 case X86::ATOMNAND6432:
16089 case X86::ATOMADD6432:
16090 case X86::ATOMSUB6432:
16091 case X86::ATOMMAX6432:
16092 case X86::ATOMMIN6432:
16093 case X86::ATOMUMAX6432:
16094 case X86::ATOMUMIN6432:
16095 case X86::ATOMSWAP6432:
16096 return EmitAtomicLoadArith6432(MI, BB);
16098 case X86::VASTART_SAVE_XMM_REGS:
16099 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16101 case X86::VAARG_64:
16102 return EmitVAARG64WithCustomInserter(MI, BB);
16104 case X86::EH_SjLj_SetJmp32:
16105 case X86::EH_SjLj_SetJmp64:
16106 return emitEHSjLjSetJmp(MI, BB);
16108 case X86::EH_SjLj_LongJmp32:
16109 case X86::EH_SjLj_LongJmp64:
16110 return emitEHSjLjLongJmp(MI, BB);
16112 case TargetOpcode::STACKMAP:
16113 case TargetOpcode::PATCHPOINT:
16114 return emitPatchPoint(MI, BB);
16118 //===----------------------------------------------------------------------===//
16119 // X86 Optimization Hooks
16120 //===----------------------------------------------------------------------===//
16122 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16125 const SelectionDAG &DAG,
16126 unsigned Depth) const {
16127 unsigned BitWidth = KnownZero.getBitWidth();
16128 unsigned Opc = Op.getOpcode();
16129 assert((Opc >= ISD::BUILTIN_OP_END ||
16130 Opc == ISD::INTRINSIC_WO_CHAIN ||
16131 Opc == ISD::INTRINSIC_W_CHAIN ||
16132 Opc == ISD::INTRINSIC_VOID) &&
16133 "Should use MaskedValueIsZero if you don't know whether Op"
16134 " is a target node!");
16136 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16150 // These nodes' second result is a boolean.
16151 if (Op.getResNo() == 0)
16154 case X86ISD::SETCC:
16155 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16157 case ISD::INTRINSIC_WO_CHAIN: {
16158 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16159 unsigned NumLoBits = 0;
16162 case Intrinsic::x86_sse_movmsk_ps:
16163 case Intrinsic::x86_avx_movmsk_ps_256:
16164 case Intrinsic::x86_sse2_movmsk_pd:
16165 case Intrinsic::x86_avx_movmsk_pd_256:
16166 case Intrinsic::x86_mmx_pmovmskb:
16167 case Intrinsic::x86_sse2_pmovmskb_128:
16168 case Intrinsic::x86_avx2_pmovmskb: {
16169 // High bits of movmskp{s|d}, pmovmskb are known zero.
16171 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16172 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16173 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16174 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16175 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16176 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16177 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16178 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16180 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16189 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16190 unsigned Depth) const {
16191 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16192 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16193 return Op.getValueType().getScalarType().getSizeInBits();
16199 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16200 /// node is a GlobalAddress + offset.
16201 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16202 const GlobalValue* &GA,
16203 int64_t &Offset) const {
16204 if (N->getOpcode() == X86ISD::Wrapper) {
16205 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16206 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16207 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16211 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16214 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16215 /// same as extracting the high 128-bit part of 256-bit vector and then
16216 /// inserting the result into the low part of a new 256-bit vector
16217 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16218 EVT VT = SVOp->getValueType(0);
16219 unsigned NumElems = VT.getVectorNumElements();
16221 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16222 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16223 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16224 SVOp->getMaskElt(j) >= 0)
16230 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16231 /// same as extracting the low 128-bit part of 256-bit vector and then
16232 /// inserting the result into the high part of a new 256-bit vector
16233 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16234 EVT VT = SVOp->getValueType(0);
16235 unsigned NumElems = VT.getVectorNumElements();
16237 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16238 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16239 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16240 SVOp->getMaskElt(j) >= 0)
16246 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16247 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16248 TargetLowering::DAGCombinerInfo &DCI,
16249 const X86Subtarget* Subtarget) {
16251 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16252 SDValue V1 = SVOp->getOperand(0);
16253 SDValue V2 = SVOp->getOperand(1);
16254 EVT VT = SVOp->getValueType(0);
16255 unsigned NumElems = VT.getVectorNumElements();
16257 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16258 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16262 // V UNDEF BUILD_VECTOR UNDEF
16264 // CONCAT_VECTOR CONCAT_VECTOR
16267 // RESULT: V + zero extended
16269 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16270 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16271 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16274 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16277 // To match the shuffle mask, the first half of the mask should
16278 // be exactly the first vector, and all the rest a splat with the
16279 // first element of the second one.
16280 for (unsigned i = 0; i != NumElems/2; ++i)
16281 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16282 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16285 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16286 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16287 if (Ld->hasNUsesOfValue(1, 0)) {
16288 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16289 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16291 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16292 array_lengthof(Ops),
16294 Ld->getPointerInfo(),
16295 Ld->getAlignment(),
16296 false/*isVolatile*/, true/*ReadMem*/,
16297 false/*WriteMem*/);
16299 // Make sure the newly-created LOAD is in the same position as Ld in
16300 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16301 // and update uses of Ld's output chain to use the TokenFactor.
16302 if (Ld->hasAnyUseOfValue(1)) {
16303 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16304 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16305 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16306 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16307 SDValue(ResNode.getNode(), 1));
16310 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16314 // Emit a zeroed vector and insert the desired subvector on its
16316 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16317 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16318 return DCI.CombineTo(N, InsV);
16321 //===--------------------------------------------------------------------===//
16322 // Combine some shuffles into subvector extracts and inserts:
16325 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16326 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16327 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16328 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16329 return DCI.CombineTo(N, InsV);
16332 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16333 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16334 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16335 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16336 return DCI.CombineTo(N, InsV);
16342 /// PerformShuffleCombine - Performs several different shuffle combines.
16343 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16344 TargetLowering::DAGCombinerInfo &DCI,
16345 const X86Subtarget *Subtarget) {
16347 EVT VT = N->getValueType(0);
16349 // Don't create instructions with illegal types after legalize types has run.
16350 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16351 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16354 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16355 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16356 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16357 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16359 // Only handle 128 wide vector from here on.
16360 if (!VT.is128BitVector())
16363 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16364 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16365 // consecutive, non-overlapping, and in the right order.
16366 SmallVector<SDValue, 16> Elts;
16367 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16368 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16370 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16373 /// PerformTruncateCombine - Converts truncate operation to
16374 /// a sequence of vector shuffle operations.
16375 /// It is possible when we truncate 256-bit vector to 128-bit vector
16376 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16377 TargetLowering::DAGCombinerInfo &DCI,
16378 const X86Subtarget *Subtarget) {
16382 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16383 /// specific shuffle of a load can be folded into a single element load.
16384 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16385 /// shuffles have been customed lowered so we need to handle those here.
16386 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16387 TargetLowering::DAGCombinerInfo &DCI) {
16388 if (DCI.isBeforeLegalizeOps())
16391 SDValue InVec = N->getOperand(0);
16392 SDValue EltNo = N->getOperand(1);
16394 if (!isa<ConstantSDNode>(EltNo))
16397 EVT VT = InVec.getValueType();
16399 bool HasShuffleIntoBitcast = false;
16400 if (InVec.getOpcode() == ISD::BITCAST) {
16401 // Don't duplicate a load with other uses.
16402 if (!InVec.hasOneUse())
16404 EVT BCVT = InVec.getOperand(0).getValueType();
16405 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16407 InVec = InVec.getOperand(0);
16408 HasShuffleIntoBitcast = true;
16411 if (!isTargetShuffle(InVec.getOpcode()))
16414 // Don't duplicate a load with other uses.
16415 if (!InVec.hasOneUse())
16418 SmallVector<int, 16> ShuffleMask;
16420 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16424 // Select the input vector, guarding against out of range extract vector.
16425 unsigned NumElems = VT.getVectorNumElements();
16426 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16427 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16428 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16429 : InVec.getOperand(1);
16431 // If inputs to shuffle are the same for both ops, then allow 2 uses
16432 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16434 if (LdNode.getOpcode() == ISD::BITCAST) {
16435 // Don't duplicate a load with other uses.
16436 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16439 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16440 LdNode = LdNode.getOperand(0);
16443 if (!ISD::isNormalLoad(LdNode.getNode()))
16446 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16448 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16451 if (HasShuffleIntoBitcast) {
16452 // If there's a bitcast before the shuffle, check if the load type and
16453 // alignment is valid.
16454 unsigned Align = LN0->getAlignment();
16455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16456 unsigned NewAlign = TLI.getDataLayout()->
16457 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16459 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16463 // All checks match so transform back to vector_shuffle so that DAG combiner
16464 // can finish the job
16467 // Create shuffle node taking into account the case that its a unary shuffle
16468 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16469 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16470 InVec.getOperand(0), Shuffle,
16472 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16473 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16477 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16478 /// generation and convert it from being a bunch of shuffles and extracts
16479 /// to a simple store and scalar loads to extract the elements.
16480 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16481 TargetLowering::DAGCombinerInfo &DCI) {
16482 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16483 if (NewOp.getNode())
16486 SDValue InputVector = N->getOperand(0);
16488 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16489 // from mmx to v2i32 has a single usage.
16490 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16491 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16492 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16493 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16494 N->getValueType(0),
16495 InputVector.getNode()->getOperand(0));
16497 // Only operate on vectors of 4 elements, where the alternative shuffling
16498 // gets to be more expensive.
16499 if (InputVector.getValueType() != MVT::v4i32)
16502 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16503 // single use which is a sign-extend or zero-extend, and all elements are
16505 SmallVector<SDNode *, 4> Uses;
16506 unsigned ExtractedElements = 0;
16507 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16508 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16509 if (UI.getUse().getResNo() != InputVector.getResNo())
16512 SDNode *Extract = *UI;
16513 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16516 if (Extract->getValueType(0) != MVT::i32)
16518 if (!Extract->hasOneUse())
16520 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16521 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16523 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16526 // Record which element was extracted.
16527 ExtractedElements |=
16528 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16530 Uses.push_back(Extract);
16533 // If not all the elements were used, this may not be worthwhile.
16534 if (ExtractedElements != 15)
16537 // Ok, we've now decided to do the transformation.
16538 SDLoc dl(InputVector);
16540 // Store the value to a temporary stack slot.
16541 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16542 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16543 MachinePointerInfo(), false, false, 0);
16545 // Replace each use (extract) with a load of the appropriate element.
16546 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16547 UE = Uses.end(); UI != UE; ++UI) {
16548 SDNode *Extract = *UI;
16550 // cOMpute the element's address.
16551 SDValue Idx = Extract->getOperand(1);
16553 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16554 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16555 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16556 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16558 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16559 StackPtr, OffsetVal);
16561 // Load the scalar.
16562 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16563 ScalarAddr, MachinePointerInfo(),
16564 false, false, false, 0);
16566 // Replace the exact with the load.
16567 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16570 // The replacement was made in place; don't return anything.
16574 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16575 static std::pair<unsigned, bool>
16576 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16577 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16578 if (!VT.isVector())
16579 return std::make_pair(0, false);
16581 bool NeedSplit = false;
16582 switch (VT.getSimpleVT().SimpleTy) {
16583 default: return std::make_pair(0, false);
16587 if (!Subtarget->hasAVX2())
16589 if (!Subtarget->hasAVX())
16590 return std::make_pair(0, false);
16595 if (!Subtarget->hasSSE2())
16596 return std::make_pair(0, false);
16599 // SSE2 has only a small subset of the operations.
16600 bool hasUnsigned = Subtarget->hasSSE41() ||
16601 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16602 bool hasSigned = Subtarget->hasSSE41() ||
16603 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16605 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16608 // Check for x CC y ? x : y.
16609 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16610 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16615 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16618 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16621 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16624 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16626 // Check for x CC y ? y : x -- a min/max with reversed arms.
16627 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16628 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16633 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16636 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16639 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16642 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16646 return std::make_pair(Opc, NeedSplit);
16649 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16651 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16652 TargetLowering::DAGCombinerInfo &DCI,
16653 const X86Subtarget *Subtarget) {
16655 SDValue Cond = N->getOperand(0);
16656 // Get the LHS/RHS of the select.
16657 SDValue LHS = N->getOperand(1);
16658 SDValue RHS = N->getOperand(2);
16659 EVT VT = LHS.getValueType();
16660 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16662 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16663 // instructions match the semantics of the common C idiom x<y?x:y but not
16664 // x<=y?x:y, because of how they handle negative zero (which can be
16665 // ignored in unsafe-math mode).
16666 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16667 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16668 (Subtarget->hasSSE2() ||
16669 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16670 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16672 unsigned Opcode = 0;
16673 // Check for x CC y ? x : y.
16674 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16675 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16679 // Converting this to a min would handle NaNs incorrectly, and swapping
16680 // the operands would cause it to handle comparisons between positive
16681 // and negative zero incorrectly.
16682 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16683 if (!DAG.getTarget().Options.UnsafeFPMath &&
16684 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16686 std::swap(LHS, RHS);
16688 Opcode = X86ISD::FMIN;
16691 // Converting this to a min would handle comparisons between positive
16692 // and negative zero incorrectly.
16693 if (!DAG.getTarget().Options.UnsafeFPMath &&
16694 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16696 Opcode = X86ISD::FMIN;
16699 // Converting this to a min would handle both negative zeros and NaNs
16700 // incorrectly, but we can swap the operands to fix both.
16701 std::swap(LHS, RHS);
16705 Opcode = X86ISD::FMIN;
16709 // Converting this to a max would handle comparisons between positive
16710 // and negative zero incorrectly.
16711 if (!DAG.getTarget().Options.UnsafeFPMath &&
16712 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16714 Opcode = X86ISD::FMAX;
16717 // Converting this to a max would handle NaNs incorrectly, and swapping
16718 // the operands would cause it to handle comparisons between positive
16719 // and negative zero incorrectly.
16720 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16721 if (!DAG.getTarget().Options.UnsafeFPMath &&
16722 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16724 std::swap(LHS, RHS);
16726 Opcode = X86ISD::FMAX;
16729 // Converting this to a max would handle both negative zeros and NaNs
16730 // incorrectly, but we can swap the operands to fix both.
16731 std::swap(LHS, RHS);
16735 Opcode = X86ISD::FMAX;
16738 // Check for x CC y ? y : x -- a min/max with reversed arms.
16739 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16740 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16744 // Converting this to a min would handle comparisons between positive
16745 // and negative zero incorrectly, and swapping the operands would
16746 // cause it to handle NaNs incorrectly.
16747 if (!DAG.getTarget().Options.UnsafeFPMath &&
16748 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16749 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16751 std::swap(LHS, RHS);
16753 Opcode = X86ISD::FMIN;
16756 // Converting this to a min would handle NaNs incorrectly.
16757 if (!DAG.getTarget().Options.UnsafeFPMath &&
16758 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16760 Opcode = X86ISD::FMIN;
16763 // Converting this to a min would handle both negative zeros and NaNs
16764 // incorrectly, but we can swap the operands to fix both.
16765 std::swap(LHS, RHS);
16769 Opcode = X86ISD::FMIN;
16773 // Converting this to a max would handle NaNs incorrectly.
16774 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16776 Opcode = X86ISD::FMAX;
16779 // Converting this to a max would handle comparisons between positive
16780 // and negative zero incorrectly, and swapping the operands would
16781 // cause it to handle NaNs incorrectly.
16782 if (!DAG.getTarget().Options.UnsafeFPMath &&
16783 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16784 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16786 std::swap(LHS, RHS);
16788 Opcode = X86ISD::FMAX;
16791 // Converting this to a max would handle both negative zeros and NaNs
16792 // incorrectly, but we can swap the operands to fix both.
16793 std::swap(LHS, RHS);
16797 Opcode = X86ISD::FMAX;
16803 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16806 EVT CondVT = Cond.getValueType();
16807 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16808 CondVT.getVectorElementType() == MVT::i1) {
16809 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16810 // lowering on AVX-512. In this case we convert it to
16811 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16812 // The same situation for all 128 and 256-bit vectors of i8 and i16
16813 EVT OpVT = LHS.getValueType();
16814 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16815 (OpVT.getVectorElementType() == MVT::i8 ||
16816 OpVT.getVectorElementType() == MVT::i16)) {
16817 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16818 DCI.AddToWorklist(Cond.getNode());
16819 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16822 // If this is a select between two integer constants, try to do some
16824 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16825 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16826 // Don't do this for crazy integer types.
16827 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16828 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16829 // so that TrueC (the true value) is larger than FalseC.
16830 bool NeedsCondInvert = false;
16832 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16833 // Efficiently invertible.
16834 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16835 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16836 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16837 NeedsCondInvert = true;
16838 std::swap(TrueC, FalseC);
16841 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16842 if (FalseC->getAPIntValue() == 0 &&
16843 TrueC->getAPIntValue().isPowerOf2()) {
16844 if (NeedsCondInvert) // Invert the condition if needed.
16845 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16846 DAG.getConstant(1, Cond.getValueType()));
16848 // Zero extend the condition if needed.
16849 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16851 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16852 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16853 DAG.getConstant(ShAmt, MVT::i8));
16856 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16857 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16858 if (NeedsCondInvert) // Invert the condition if needed.
16859 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16860 DAG.getConstant(1, Cond.getValueType()));
16862 // Zero extend the condition if needed.
16863 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16864 FalseC->getValueType(0), Cond);
16865 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16866 SDValue(FalseC, 0));
16869 // Optimize cases that will turn into an LEA instruction. This requires
16870 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16871 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16872 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16873 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16875 bool isFastMultiplier = false;
16877 switch ((unsigned char)Diff) {
16879 case 1: // result = add base, cond
16880 case 2: // result = lea base( , cond*2)
16881 case 3: // result = lea base(cond, cond*2)
16882 case 4: // result = lea base( , cond*4)
16883 case 5: // result = lea base(cond, cond*4)
16884 case 8: // result = lea base( , cond*8)
16885 case 9: // result = lea base(cond, cond*8)
16886 isFastMultiplier = true;
16891 if (isFastMultiplier) {
16892 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16893 if (NeedsCondInvert) // Invert the condition if needed.
16894 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16895 DAG.getConstant(1, Cond.getValueType()));
16897 // Zero extend the condition if needed.
16898 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16900 // Scale the condition by the difference.
16902 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16903 DAG.getConstant(Diff, Cond.getValueType()));
16905 // Add the base if non-zero.
16906 if (FalseC->getAPIntValue() != 0)
16907 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16908 SDValue(FalseC, 0));
16915 // Canonicalize max and min:
16916 // (x > y) ? x : y -> (x >= y) ? x : y
16917 // (x < y) ? x : y -> (x <= y) ? x : y
16918 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16919 // the need for an extra compare
16920 // against zero. e.g.
16921 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16923 // testl %edi, %edi
16925 // cmovgl %edi, %eax
16929 // cmovsl %eax, %edi
16930 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16931 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16932 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16933 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16938 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16939 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16940 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16941 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16946 // Early exit check
16947 if (!TLI.isTypeLegal(VT))
16950 // Match VSELECTs into subs with unsigned saturation.
16951 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16952 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16953 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16954 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16955 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16957 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16958 // left side invert the predicate to simplify logic below.
16960 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16962 CC = ISD::getSetCCInverse(CC, true);
16963 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16967 if (Other.getNode() && Other->getNumOperands() == 2 &&
16968 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16969 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16970 SDValue CondRHS = Cond->getOperand(1);
16972 // Look for a general sub with unsigned saturation first.
16973 // x >= y ? x-y : 0 --> subus x, y
16974 // x > y ? x-y : 0 --> subus x, y
16975 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16976 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16977 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16979 // If the RHS is a constant we have to reverse the const canonicalization.
16980 // x > C-1 ? x+-C : 0 --> subus x, C
16981 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16982 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16983 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16984 if (CondRHS.getConstantOperandVal(0) == -A-1)
16985 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16986 DAG.getConstant(-A, VT));
16989 // Another special case: If C was a sign bit, the sub has been
16990 // canonicalized into a xor.
16991 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16992 // it's safe to decanonicalize the xor?
16993 // x s< 0 ? x^C : 0 --> subus x, C
16994 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16995 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16996 isSplatVector(OpRHS.getNode())) {
16997 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16999 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17004 // Try to match a min/max vector operation.
17005 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17006 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17007 unsigned Opc = ret.first;
17008 bool NeedSplit = ret.second;
17010 if (Opc && NeedSplit) {
17011 unsigned NumElems = VT.getVectorNumElements();
17012 // Extract the LHS vectors
17013 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17014 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17016 // Extract the RHS vectors
17017 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17018 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17020 // Create min/max for each subvector
17021 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17022 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17024 // Merge the result
17025 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17027 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17030 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17031 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17032 // Check if SETCC has already been promoted
17033 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17034 // Check that condition value type matches vselect operand type
17037 assert(Cond.getValueType().isVector() &&
17038 "vector select expects a vector selector!");
17040 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17041 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17043 if (!TValIsAllOnes && !FValIsAllZeros) {
17044 // Try invert the condition if true value is not all 1s and false value
17046 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17047 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17049 if (TValIsAllZeros || FValIsAllOnes) {
17050 SDValue CC = Cond.getOperand(2);
17051 ISD::CondCode NewCC =
17052 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17053 Cond.getOperand(0).getValueType().isInteger());
17054 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17055 std::swap(LHS, RHS);
17056 TValIsAllOnes = FValIsAllOnes;
17057 FValIsAllZeros = TValIsAllZeros;
17061 if (TValIsAllOnes || FValIsAllZeros) {
17064 if (TValIsAllOnes && FValIsAllZeros)
17066 else if (TValIsAllOnes)
17067 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17068 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17069 else if (FValIsAllZeros)
17070 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17071 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17073 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17077 // If we know that this node is legal then we know that it is going to be
17078 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17079 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17080 // to simplify previous instructions.
17081 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17082 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17083 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17085 // Don't optimize vector selects that map to mask-registers.
17089 // Check all uses of that condition operand to check whether it will be
17090 // consumed by non-BLEND instructions, which may depend on all bits are set
17092 for (SDNode::use_iterator I = Cond->use_begin(),
17093 E = Cond->use_end(); I != E; ++I)
17094 if (I->getOpcode() != ISD::VSELECT)
17095 // TODO: Add other opcodes eventually lowered into BLEND.
17098 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17099 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17101 APInt KnownZero, KnownOne;
17102 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17103 DCI.isBeforeLegalizeOps());
17104 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17105 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17106 DCI.CommitTargetLoweringOpt(TLO);
17112 // Check whether a boolean test is testing a boolean value generated by
17113 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17116 // Simplify the following patterns:
17117 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17118 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17119 // to (Op EFLAGS Cond)
17121 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17122 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17123 // to (Op EFLAGS !Cond)
17125 // where Op could be BRCOND or CMOV.
17127 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17128 // Quit if not CMP and SUB with its value result used.
17129 if (Cmp.getOpcode() != X86ISD::CMP &&
17130 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17133 // Quit if not used as a boolean value.
17134 if (CC != X86::COND_E && CC != X86::COND_NE)
17137 // Check CMP operands. One of them should be 0 or 1 and the other should be
17138 // an SetCC or extended from it.
17139 SDValue Op1 = Cmp.getOperand(0);
17140 SDValue Op2 = Cmp.getOperand(1);
17143 const ConstantSDNode* C = 0;
17144 bool needOppositeCond = (CC == X86::COND_E);
17145 bool checkAgainstTrue = false; // Is it a comparison against 1?
17147 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17149 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17151 else // Quit if all operands are not constants.
17154 if (C->getZExtValue() == 1) {
17155 needOppositeCond = !needOppositeCond;
17156 checkAgainstTrue = true;
17157 } else if (C->getZExtValue() != 0)
17158 // Quit if the constant is neither 0 or 1.
17161 bool truncatedToBoolWithAnd = false;
17162 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17163 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17164 SetCC.getOpcode() == ISD::TRUNCATE ||
17165 SetCC.getOpcode() == ISD::AND) {
17166 if (SetCC.getOpcode() == ISD::AND) {
17168 ConstantSDNode *CS;
17169 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17170 CS->getZExtValue() == 1)
17172 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17173 CS->getZExtValue() == 1)
17177 SetCC = SetCC.getOperand(OpIdx);
17178 truncatedToBoolWithAnd = true;
17180 SetCC = SetCC.getOperand(0);
17183 switch (SetCC.getOpcode()) {
17184 case X86ISD::SETCC_CARRY:
17185 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17186 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17187 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17188 // truncated to i1 using 'and'.
17189 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17191 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17192 "Invalid use of SETCC_CARRY!");
17194 case X86ISD::SETCC:
17195 // Set the condition code or opposite one if necessary.
17196 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17197 if (needOppositeCond)
17198 CC = X86::GetOppositeBranchCondition(CC);
17199 return SetCC.getOperand(1);
17200 case X86ISD::CMOV: {
17201 // Check whether false/true value has canonical one, i.e. 0 or 1.
17202 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17203 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17204 // Quit if true value is not a constant.
17207 // Quit if false value is not a constant.
17209 SDValue Op = SetCC.getOperand(0);
17210 // Skip 'zext' or 'trunc' node.
17211 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17212 Op.getOpcode() == ISD::TRUNCATE)
17213 Op = Op.getOperand(0);
17214 // A special case for rdrand/rdseed, where 0 is set if false cond is
17216 if ((Op.getOpcode() != X86ISD::RDRAND &&
17217 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17220 // Quit if false value is not the constant 0 or 1.
17221 bool FValIsFalse = true;
17222 if (FVal && FVal->getZExtValue() != 0) {
17223 if (FVal->getZExtValue() != 1)
17225 // If FVal is 1, opposite cond is needed.
17226 needOppositeCond = !needOppositeCond;
17227 FValIsFalse = false;
17229 // Quit if TVal is not the constant opposite of FVal.
17230 if (FValIsFalse && TVal->getZExtValue() != 1)
17232 if (!FValIsFalse && TVal->getZExtValue() != 0)
17234 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17235 if (needOppositeCond)
17236 CC = X86::GetOppositeBranchCondition(CC);
17237 return SetCC.getOperand(3);
17244 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17245 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17246 TargetLowering::DAGCombinerInfo &DCI,
17247 const X86Subtarget *Subtarget) {
17250 // If the flag operand isn't dead, don't touch this CMOV.
17251 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17254 SDValue FalseOp = N->getOperand(0);
17255 SDValue TrueOp = N->getOperand(1);
17256 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17257 SDValue Cond = N->getOperand(3);
17259 if (CC == X86::COND_E || CC == X86::COND_NE) {
17260 switch (Cond.getOpcode()) {
17264 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17265 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17266 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17272 Flags = checkBoolTestSetCCCombine(Cond, CC);
17273 if (Flags.getNode() &&
17274 // Extra check as FCMOV only supports a subset of X86 cond.
17275 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17276 SDValue Ops[] = { FalseOp, TrueOp,
17277 DAG.getConstant(CC, MVT::i8), Flags };
17278 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17279 Ops, array_lengthof(Ops));
17282 // If this is a select between two integer constants, try to do some
17283 // optimizations. Note that the operands are ordered the opposite of SELECT
17285 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17286 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17287 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17288 // larger than FalseC (the false value).
17289 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17290 CC = X86::GetOppositeBranchCondition(CC);
17291 std::swap(TrueC, FalseC);
17292 std::swap(TrueOp, FalseOp);
17295 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17296 // This is efficient for any integer data type (including i8/i16) and
17298 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17299 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17300 DAG.getConstant(CC, MVT::i8), Cond);
17302 // Zero extend the condition if needed.
17303 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17305 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17306 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17307 DAG.getConstant(ShAmt, MVT::i8));
17308 if (N->getNumValues() == 2) // Dead flag value?
17309 return DCI.CombineTo(N, Cond, SDValue());
17313 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17314 // for any integer data type, including i8/i16.
17315 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17316 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17317 DAG.getConstant(CC, MVT::i8), Cond);
17319 // Zero extend the condition if needed.
17320 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17321 FalseC->getValueType(0), Cond);
17322 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17323 SDValue(FalseC, 0));
17325 if (N->getNumValues() == 2) // Dead flag value?
17326 return DCI.CombineTo(N, Cond, SDValue());
17330 // Optimize cases that will turn into an LEA instruction. This requires
17331 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17332 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17333 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17334 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17336 bool isFastMultiplier = false;
17338 switch ((unsigned char)Diff) {
17340 case 1: // result = add base, cond
17341 case 2: // result = lea base( , cond*2)
17342 case 3: // result = lea base(cond, cond*2)
17343 case 4: // result = lea base( , cond*4)
17344 case 5: // result = lea base(cond, cond*4)
17345 case 8: // result = lea base( , cond*8)
17346 case 9: // result = lea base(cond, cond*8)
17347 isFastMultiplier = true;
17352 if (isFastMultiplier) {
17353 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17354 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17355 DAG.getConstant(CC, MVT::i8), Cond);
17356 // Zero extend the condition if needed.
17357 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17359 // Scale the condition by the difference.
17361 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17362 DAG.getConstant(Diff, Cond.getValueType()));
17364 // Add the base if non-zero.
17365 if (FalseC->getAPIntValue() != 0)
17366 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17367 SDValue(FalseC, 0));
17368 if (N->getNumValues() == 2) // Dead flag value?
17369 return DCI.CombineTo(N, Cond, SDValue());
17376 // Handle these cases:
17377 // (select (x != c), e, c) -> select (x != c), e, x),
17378 // (select (x == c), c, e) -> select (x == c), x, e)
17379 // where the c is an integer constant, and the "select" is the combination
17380 // of CMOV and CMP.
17382 // The rationale for this change is that the conditional-move from a constant
17383 // needs two instructions, however, conditional-move from a register needs
17384 // only one instruction.
17386 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17387 // some instruction-combining opportunities. This opt needs to be
17388 // postponed as late as possible.
17390 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17391 // the DCI.xxxx conditions are provided to postpone the optimization as
17392 // late as possible.
17394 ConstantSDNode *CmpAgainst = 0;
17395 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17396 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17397 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17399 if (CC == X86::COND_NE &&
17400 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17401 CC = X86::GetOppositeBranchCondition(CC);
17402 std::swap(TrueOp, FalseOp);
17405 if (CC == X86::COND_E &&
17406 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17407 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17408 DAG.getConstant(CC, MVT::i8), Cond };
17409 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17410 array_lengthof(Ops));
17418 /// PerformMulCombine - Optimize a single multiply with constant into two
17419 /// in order to implement it with two cheaper instructions, e.g.
17420 /// LEA + SHL, LEA + LEA.
17421 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17422 TargetLowering::DAGCombinerInfo &DCI) {
17423 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17426 EVT VT = N->getValueType(0);
17427 if (VT != MVT::i64)
17430 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17433 uint64_t MulAmt = C->getZExtValue();
17434 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17437 uint64_t MulAmt1 = 0;
17438 uint64_t MulAmt2 = 0;
17439 if ((MulAmt % 9) == 0) {
17441 MulAmt2 = MulAmt / 9;
17442 } else if ((MulAmt % 5) == 0) {
17444 MulAmt2 = MulAmt / 5;
17445 } else if ((MulAmt % 3) == 0) {
17447 MulAmt2 = MulAmt / 3;
17450 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17453 if (isPowerOf2_64(MulAmt2) &&
17454 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17455 // If second multiplifer is pow2, issue it first. We want the multiply by
17456 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17458 std::swap(MulAmt1, MulAmt2);
17461 if (isPowerOf2_64(MulAmt1))
17462 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17463 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17465 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17466 DAG.getConstant(MulAmt1, VT));
17468 if (isPowerOf2_64(MulAmt2))
17469 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17470 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17472 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17473 DAG.getConstant(MulAmt2, VT));
17475 // Do not add new nodes to DAG combiner worklist.
17476 DCI.CombineTo(N, NewMul, false);
17481 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17482 SDValue N0 = N->getOperand(0);
17483 SDValue N1 = N->getOperand(1);
17484 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17485 EVT VT = N0.getValueType();
17487 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17488 // since the result of setcc_c is all zero's or all ones.
17489 if (VT.isInteger() && !VT.isVector() &&
17490 N1C && N0.getOpcode() == ISD::AND &&
17491 N0.getOperand(1).getOpcode() == ISD::Constant) {
17492 SDValue N00 = N0.getOperand(0);
17493 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17494 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17495 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17496 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17497 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17498 APInt ShAmt = N1C->getAPIntValue();
17499 Mask = Mask.shl(ShAmt);
17501 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17502 N00, DAG.getConstant(Mask, VT));
17506 // Hardware support for vector shifts is sparse which makes us scalarize the
17507 // vector operations in many cases. Also, on sandybridge ADD is faster than
17509 // (shl V, 1) -> add V,V
17510 if (isSplatVector(N1.getNode())) {
17511 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17513 // We shift all of the values by one. In many cases we do not have
17514 // hardware support for this operation. This is better expressed as an ADD
17516 if (N1C && (1 == N1C->getZExtValue())) {
17517 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17524 /// \brief Returns a vector of 0s if the node in input is a vector logical
17525 /// shift by a constant amount which is known to be bigger than or equal
17526 /// to the vector element size in bits.
17527 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17528 const X86Subtarget *Subtarget) {
17529 EVT VT = N->getValueType(0);
17531 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17532 (!Subtarget->hasInt256() ||
17533 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17536 SDValue Amt = N->getOperand(1);
17538 if (isSplatVector(Amt.getNode())) {
17539 SDValue SclrAmt = Amt->getOperand(0);
17540 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17541 APInt ShiftAmt = C->getAPIntValue();
17542 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17544 // SSE2/AVX2 logical shifts always return a vector of 0s
17545 // if the shift amount is bigger than or equal to
17546 // the element size. The constant shift amount will be
17547 // encoded as a 8-bit immediate.
17548 if (ShiftAmt.trunc(8).uge(MaxAmount))
17549 return getZeroVector(VT, Subtarget, DAG, DL);
17556 /// PerformShiftCombine - Combine shifts.
17557 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17558 TargetLowering::DAGCombinerInfo &DCI,
17559 const X86Subtarget *Subtarget) {
17560 if (N->getOpcode() == ISD::SHL) {
17561 SDValue V = PerformSHLCombine(N, DAG);
17562 if (V.getNode()) return V;
17565 if (N->getOpcode() != ISD::SRA) {
17566 // Try to fold this logical shift into a zero vector.
17567 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17568 if (V.getNode()) return V;
17574 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17575 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17576 // and friends. Likewise for OR -> CMPNEQSS.
17577 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17578 TargetLowering::DAGCombinerInfo &DCI,
17579 const X86Subtarget *Subtarget) {
17582 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17583 // we're requiring SSE2 for both.
17584 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17585 SDValue N0 = N->getOperand(0);
17586 SDValue N1 = N->getOperand(1);
17587 SDValue CMP0 = N0->getOperand(1);
17588 SDValue CMP1 = N1->getOperand(1);
17591 // The SETCCs should both refer to the same CMP.
17592 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17595 SDValue CMP00 = CMP0->getOperand(0);
17596 SDValue CMP01 = CMP0->getOperand(1);
17597 EVT VT = CMP00.getValueType();
17599 if (VT == MVT::f32 || VT == MVT::f64) {
17600 bool ExpectingFlags = false;
17601 // Check for any users that want flags:
17602 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17603 !ExpectingFlags && UI != UE; ++UI)
17604 switch (UI->getOpcode()) {
17609 ExpectingFlags = true;
17611 case ISD::CopyToReg:
17612 case ISD::SIGN_EXTEND:
17613 case ISD::ZERO_EXTEND:
17614 case ISD::ANY_EXTEND:
17618 if (!ExpectingFlags) {
17619 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17620 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17622 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17623 X86::CondCode tmp = cc0;
17628 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17629 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17630 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17631 // FIXME: need symbolic constants for these magic numbers.
17632 // See X86ATTInstPrinter.cpp:printSSECC().
17633 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17634 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL, CMP00.getValueType(), CMP00, CMP01,
17635 DAG.getConstant(x86cc, MVT::i8));
17636 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
17637 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
17639 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17640 DAG.getConstant(1, IntVT));
17641 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17642 return OneBitOfTruth;
17650 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17651 /// so it can be folded inside ANDNP.
17652 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17653 EVT VT = N->getValueType(0);
17655 // Match direct AllOnes for 128 and 256-bit vectors
17656 if (ISD::isBuildVectorAllOnes(N))
17659 // Look through a bit convert.
17660 if (N->getOpcode() == ISD::BITCAST)
17661 N = N->getOperand(0).getNode();
17663 // Sometimes the operand may come from a insert_subvector building a 256-bit
17665 if (VT.is256BitVector() &&
17666 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17667 SDValue V1 = N->getOperand(0);
17668 SDValue V2 = N->getOperand(1);
17670 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17671 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17672 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17673 ISD::isBuildVectorAllOnes(V2.getNode()))
17680 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17681 // register. In most cases we actually compare or select YMM-sized registers
17682 // and mixing the two types creates horrible code. This method optimizes
17683 // some of the transition sequences.
17684 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17685 TargetLowering::DAGCombinerInfo &DCI,
17686 const X86Subtarget *Subtarget) {
17687 EVT VT = N->getValueType(0);
17688 if (!VT.is256BitVector())
17691 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17692 N->getOpcode() == ISD::ZERO_EXTEND ||
17693 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17695 SDValue Narrow = N->getOperand(0);
17696 EVT NarrowVT = Narrow->getValueType(0);
17697 if (!NarrowVT.is128BitVector())
17700 if (Narrow->getOpcode() != ISD::XOR &&
17701 Narrow->getOpcode() != ISD::AND &&
17702 Narrow->getOpcode() != ISD::OR)
17705 SDValue N0 = Narrow->getOperand(0);
17706 SDValue N1 = Narrow->getOperand(1);
17709 // The Left side has to be a trunc.
17710 if (N0.getOpcode() != ISD::TRUNCATE)
17713 // The type of the truncated inputs.
17714 EVT WideVT = N0->getOperand(0)->getValueType(0);
17718 // The right side has to be a 'trunc' or a constant vector.
17719 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17720 bool RHSConst = (isSplatVector(N1.getNode()) &&
17721 isa<ConstantSDNode>(N1->getOperand(0)));
17722 if (!RHSTrunc && !RHSConst)
17725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17727 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17730 // Set N0 and N1 to hold the inputs to the new wide operation.
17731 N0 = N0->getOperand(0);
17733 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17734 N1->getOperand(0));
17735 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17736 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17737 } else if (RHSTrunc) {
17738 N1 = N1->getOperand(0);
17741 // Generate the wide operation.
17742 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17743 unsigned Opcode = N->getOpcode();
17745 case ISD::ANY_EXTEND:
17747 case ISD::ZERO_EXTEND: {
17748 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17749 APInt Mask = APInt::getAllOnesValue(InBits);
17750 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17751 return DAG.getNode(ISD::AND, DL, VT,
17752 Op, DAG.getConstant(Mask, VT));
17754 case ISD::SIGN_EXTEND:
17755 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17756 Op, DAG.getValueType(NarrowVT));
17758 llvm_unreachable("Unexpected opcode");
17762 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17763 TargetLowering::DAGCombinerInfo &DCI,
17764 const X86Subtarget *Subtarget) {
17765 EVT VT = N->getValueType(0);
17766 if (DCI.isBeforeLegalizeOps())
17769 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17773 // Create BLSI, BLSR, and BZHI instructions
17774 // BLSI is X & (-X)
17775 // BLSR is X & (X-1)
17776 // BZHI is X & ((1 << Y) - 1)
17777 // BEXTR is ((X >> imm) & (2**size-1))
17778 if (VT == MVT::i32 || VT == MVT::i64) {
17779 SDValue N0 = N->getOperand(0);
17780 SDValue N1 = N->getOperand(1);
17783 if (Subtarget->hasBMI()) {
17784 // Check LHS for neg
17785 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17786 isZero(N0.getOperand(0)))
17787 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17789 // Check RHS for neg
17790 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17791 isZero(N1.getOperand(0)))
17792 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17794 // Check LHS for X-1
17795 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17796 isAllOnes(N0.getOperand(1)))
17797 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17799 // Check RHS for X-1
17800 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17801 isAllOnes(N1.getOperand(1)))
17802 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17805 if (Subtarget->hasBMI2()) {
17806 // Check for (and (add (shl 1, Y), -1), X)
17807 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17808 SDValue N00 = N0.getOperand(0);
17809 if (N00.getOpcode() == ISD::SHL) {
17810 SDValue N001 = N00.getOperand(1);
17811 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17812 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17813 if (C && C->getZExtValue() == 1)
17814 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17818 // Check for (and X, (add (shl 1, Y), -1))
17819 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17820 SDValue N10 = N1.getOperand(0);
17821 if (N10.getOpcode() == ISD::SHL) {
17822 SDValue N101 = N10.getOperand(1);
17823 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17824 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17825 if (C && C->getZExtValue() == 1)
17826 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17831 // Check for BEXTR.
17832 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17833 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17834 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17835 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17836 if (MaskNode && ShiftNode) {
17837 uint64_t Mask = MaskNode->getZExtValue();
17838 uint64_t Shift = ShiftNode->getZExtValue();
17839 if (isMask_64(Mask)) {
17840 uint64_t MaskSize = CountPopulation_64(Mask);
17841 if (Shift + MaskSize <= VT.getSizeInBits())
17842 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17843 DAG.getConstant(Shift | (MaskSize << 8), VT));
17851 // Want to form ANDNP nodes:
17852 // 1) In the hopes of then easily combining them with OR and AND nodes
17853 // to form PBLEND/PSIGN.
17854 // 2) To match ANDN packed intrinsics
17855 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17858 SDValue N0 = N->getOperand(0);
17859 SDValue N1 = N->getOperand(1);
17862 // Check LHS for vnot
17863 if (N0.getOpcode() == ISD::XOR &&
17864 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17865 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17866 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17868 // Check RHS for vnot
17869 if (N1.getOpcode() == ISD::XOR &&
17870 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17871 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17872 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17877 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17878 TargetLowering::DAGCombinerInfo &DCI,
17879 const X86Subtarget *Subtarget) {
17880 EVT VT = N->getValueType(0);
17881 if (DCI.isBeforeLegalizeOps())
17884 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17888 SDValue N0 = N->getOperand(0);
17889 SDValue N1 = N->getOperand(1);
17891 // look for psign/blend
17892 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17893 if (!Subtarget->hasSSSE3() ||
17894 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17897 // Canonicalize pandn to RHS
17898 if (N0.getOpcode() == X86ISD::ANDNP)
17900 // or (and (m, y), (pandn m, x))
17901 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17902 SDValue Mask = N1.getOperand(0);
17903 SDValue X = N1.getOperand(1);
17905 if (N0.getOperand(0) == Mask)
17906 Y = N0.getOperand(1);
17907 if (N0.getOperand(1) == Mask)
17908 Y = N0.getOperand(0);
17910 // Check to see if the mask appeared in both the AND and ANDNP and
17914 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17915 // Look through mask bitcast.
17916 if (Mask.getOpcode() == ISD::BITCAST)
17917 Mask = Mask.getOperand(0);
17918 if (X.getOpcode() == ISD::BITCAST)
17919 X = X.getOperand(0);
17920 if (Y.getOpcode() == ISD::BITCAST)
17921 Y = Y.getOperand(0);
17923 EVT MaskVT = Mask.getValueType();
17925 // Validate that the Mask operand is a vector sra node.
17926 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17927 // there is no psrai.b
17928 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17929 unsigned SraAmt = ~0;
17930 if (Mask.getOpcode() == ISD::SRA) {
17931 SDValue Amt = Mask.getOperand(1);
17932 if (isSplatVector(Amt.getNode())) {
17933 SDValue SclrAmt = Amt->getOperand(0);
17934 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17935 SraAmt = C->getZExtValue();
17937 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17938 SDValue SraC = Mask.getOperand(1);
17939 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17941 if ((SraAmt + 1) != EltBits)
17946 // Now we know we at least have a plendvb with the mask val. See if
17947 // we can form a psignb/w/d.
17948 // psign = x.type == y.type == mask.type && y = sub(0, x);
17949 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17950 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17951 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17952 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17953 "Unsupported VT for PSIGN");
17954 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17955 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17957 // PBLENDVB only available on SSE 4.1
17958 if (!Subtarget->hasSSE41())
17961 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17963 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17964 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17965 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17966 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17967 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17971 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17974 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17975 MachineFunction &MF = DAG.getMachineFunction();
17976 bool OptForSize = MF.getFunction()->getAttributes().
17977 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
17979 // SHLD/SHRD instructions have lower register pressure, but on some
17980 // platforms they have higher latency than the equivalent
17981 // series of shifts/or that would otherwise be generated.
17982 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
17983 // have higher latencies and we are not optimizing for size.
17984 if (!OptForSize && Subtarget->isSHLDSlow())
17987 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17989 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17991 if (!N0.hasOneUse() || !N1.hasOneUse())
17994 SDValue ShAmt0 = N0.getOperand(1);
17995 if (ShAmt0.getValueType() != MVT::i8)
17997 SDValue ShAmt1 = N1.getOperand(1);
17998 if (ShAmt1.getValueType() != MVT::i8)
18000 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18001 ShAmt0 = ShAmt0.getOperand(0);
18002 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18003 ShAmt1 = ShAmt1.getOperand(0);
18006 unsigned Opc = X86ISD::SHLD;
18007 SDValue Op0 = N0.getOperand(0);
18008 SDValue Op1 = N1.getOperand(0);
18009 if (ShAmt0.getOpcode() == ISD::SUB) {
18010 Opc = X86ISD::SHRD;
18011 std::swap(Op0, Op1);
18012 std::swap(ShAmt0, ShAmt1);
18015 unsigned Bits = VT.getSizeInBits();
18016 if (ShAmt1.getOpcode() == ISD::SUB) {
18017 SDValue Sum = ShAmt1.getOperand(0);
18018 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18019 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18020 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18021 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18022 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18023 return DAG.getNode(Opc, DL, VT,
18025 DAG.getNode(ISD::TRUNCATE, DL,
18028 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18029 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18031 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18032 return DAG.getNode(Opc, DL, VT,
18033 N0.getOperand(0), N1.getOperand(0),
18034 DAG.getNode(ISD::TRUNCATE, DL,
18041 // Generate NEG and CMOV for integer abs.
18042 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18043 EVT VT = N->getValueType(0);
18045 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18046 // 8-bit integer abs to NEG and CMOV.
18047 if (VT.isInteger() && VT.getSizeInBits() == 8)
18050 SDValue N0 = N->getOperand(0);
18051 SDValue N1 = N->getOperand(1);
18054 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18055 // and change it to SUB and CMOV.
18056 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18057 N0.getOpcode() == ISD::ADD &&
18058 N0.getOperand(1) == N1 &&
18059 N1.getOpcode() == ISD::SRA &&
18060 N1.getOperand(0) == N0.getOperand(0))
18061 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18062 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18063 // Generate SUB & CMOV.
18064 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18065 DAG.getConstant(0, VT), N0.getOperand(0));
18067 SDValue Ops[] = { N0.getOperand(0), Neg,
18068 DAG.getConstant(X86::COND_GE, MVT::i8),
18069 SDValue(Neg.getNode(), 1) };
18070 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18071 Ops, array_lengthof(Ops));
18076 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18077 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18078 TargetLowering::DAGCombinerInfo &DCI,
18079 const X86Subtarget *Subtarget) {
18080 EVT VT = N->getValueType(0);
18081 if (DCI.isBeforeLegalizeOps())
18084 if (Subtarget->hasCMov()) {
18085 SDValue RV = performIntegerAbsCombine(N, DAG);
18090 // Try forming BMI if it is available.
18091 if (!Subtarget->hasBMI())
18094 if (VT != MVT::i32 && VT != MVT::i64)
18097 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18099 // Create BLSMSK instructions by finding X ^ (X-1)
18100 SDValue N0 = N->getOperand(0);
18101 SDValue N1 = N->getOperand(1);
18104 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18105 isAllOnes(N0.getOperand(1)))
18106 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18108 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18109 isAllOnes(N1.getOperand(1)))
18110 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18115 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18116 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18117 TargetLowering::DAGCombinerInfo &DCI,
18118 const X86Subtarget *Subtarget) {
18119 LoadSDNode *Ld = cast<LoadSDNode>(N);
18120 EVT RegVT = Ld->getValueType(0);
18121 EVT MemVT = Ld->getMemoryVT();
18123 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18124 unsigned RegSz = RegVT.getSizeInBits();
18126 // On Sandybridge unaligned 256bit loads are inefficient.
18127 ISD::LoadExtType Ext = Ld->getExtensionType();
18128 unsigned Alignment = Ld->getAlignment();
18129 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18130 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18131 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18132 unsigned NumElems = RegVT.getVectorNumElements();
18136 SDValue Ptr = Ld->getBasePtr();
18137 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18139 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18141 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18142 Ld->getPointerInfo(), Ld->isVolatile(),
18143 Ld->isNonTemporal(), Ld->isInvariant(),
18145 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18146 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18147 Ld->getPointerInfo(), Ld->isVolatile(),
18148 Ld->isNonTemporal(), Ld->isInvariant(),
18149 std::min(16U, Alignment));
18150 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18152 Load2.getValue(1));
18154 SDValue NewVec = DAG.getUNDEF(RegVT);
18155 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18156 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18157 return DCI.CombineTo(N, NewVec, TF, true);
18160 // If this is a vector EXT Load then attempt to optimize it using a
18161 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18162 // expansion is still better than scalar code.
18163 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18164 // emit a shuffle and a arithmetic shift.
18165 // TODO: It is possible to support ZExt by zeroing the undef values
18166 // during the shuffle phase or after the shuffle.
18167 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18168 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18169 assert(MemVT != RegVT && "Cannot extend to the same type");
18170 assert(MemVT.isVector() && "Must load a vector from memory");
18172 unsigned NumElems = RegVT.getVectorNumElements();
18173 unsigned MemSz = MemVT.getSizeInBits();
18174 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18176 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18179 // All sizes must be a power of two.
18180 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18183 // Attempt to load the original value using scalar loads.
18184 // Find the largest scalar type that divides the total loaded size.
18185 MVT SclrLoadTy = MVT::i8;
18186 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18187 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18188 MVT Tp = (MVT::SimpleValueType)tp;
18189 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18194 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18195 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18197 SclrLoadTy = MVT::f64;
18199 // Calculate the number of scalar loads that we need to perform
18200 // in order to load our vector from memory.
18201 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18202 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18205 unsigned loadRegZize = RegSz;
18206 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18209 // Represent our vector as a sequence of elements which are the
18210 // largest scalar that we can load.
18211 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18212 loadRegZize/SclrLoadTy.getSizeInBits());
18214 // Represent the data using the same element type that is stored in
18215 // memory. In practice, we ''widen'' MemVT.
18217 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18218 loadRegZize/MemVT.getScalarType().getSizeInBits());
18220 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18221 "Invalid vector type");
18223 // We can't shuffle using an illegal type.
18224 if (!TLI.isTypeLegal(WideVecVT))
18227 SmallVector<SDValue, 8> Chains;
18228 SDValue Ptr = Ld->getBasePtr();
18229 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18230 TLI.getPointerTy());
18231 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18233 for (unsigned i = 0; i < NumLoads; ++i) {
18234 // Perform a single load.
18235 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18236 Ptr, Ld->getPointerInfo(),
18237 Ld->isVolatile(), Ld->isNonTemporal(),
18238 Ld->isInvariant(), Ld->getAlignment());
18239 Chains.push_back(ScalarLoad.getValue(1));
18240 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18241 // another round of DAGCombining.
18243 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18245 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18246 ScalarLoad, DAG.getIntPtrConstant(i));
18248 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18251 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18254 // Bitcast the loaded value to a vector of the original element type, in
18255 // the size of the target vector type.
18256 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18257 unsigned SizeRatio = RegSz/MemSz;
18259 if (Ext == ISD::SEXTLOAD) {
18260 // If we have SSE4.1 we can directly emit a VSEXT node.
18261 if (Subtarget->hasSSE41()) {
18262 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18263 return DCI.CombineTo(N, Sext, TF, true);
18266 // Otherwise we'll shuffle the small elements in the high bits of the
18267 // larger type and perform an arithmetic shift. If the shift is not legal
18268 // it's better to scalarize.
18269 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18272 // Redistribute the loaded elements into the different locations.
18273 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18274 for (unsigned i = 0; i != NumElems; ++i)
18275 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18277 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18278 DAG.getUNDEF(WideVecVT),
18281 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18283 // Build the arithmetic shift.
18284 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18285 MemVT.getVectorElementType().getSizeInBits();
18286 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18287 DAG.getConstant(Amt, RegVT));
18289 return DCI.CombineTo(N, Shuff, TF, true);
18292 // Redistribute the loaded elements into the different locations.
18293 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18294 for (unsigned i = 0; i != NumElems; ++i)
18295 ShuffleVec[i*SizeRatio] = i;
18297 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18298 DAG.getUNDEF(WideVecVT),
18301 // Bitcast to the requested type.
18302 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18303 // Replace the original load with the new sequence
18304 // and return the new chain.
18305 return DCI.CombineTo(N, Shuff, TF, true);
18311 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18312 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18313 const X86Subtarget *Subtarget) {
18314 StoreSDNode *St = cast<StoreSDNode>(N);
18315 EVT VT = St->getValue().getValueType();
18316 EVT StVT = St->getMemoryVT();
18318 SDValue StoredVal = St->getOperand(1);
18319 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18321 // If we are saving a concatenation of two XMM registers, perform two stores.
18322 // On Sandy Bridge, 256-bit memory operations are executed by two
18323 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18324 // memory operation.
18325 unsigned Alignment = St->getAlignment();
18326 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18327 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18328 StVT == VT && !IsAligned) {
18329 unsigned NumElems = VT.getVectorNumElements();
18333 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18334 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18336 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18337 SDValue Ptr0 = St->getBasePtr();
18338 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18340 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18341 St->getPointerInfo(), St->isVolatile(),
18342 St->isNonTemporal(), Alignment);
18343 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18344 St->getPointerInfo(), St->isVolatile(),
18345 St->isNonTemporal(),
18346 std::min(16U, Alignment));
18347 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18350 // Optimize trunc store (of multiple scalars) to shuffle and store.
18351 // First, pack all of the elements in one place. Next, store to memory
18352 // in fewer chunks.
18353 if (St->isTruncatingStore() && VT.isVector()) {
18354 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18355 unsigned NumElems = VT.getVectorNumElements();
18356 assert(StVT != VT && "Cannot truncate to the same type");
18357 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18358 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18360 // From, To sizes and ElemCount must be pow of two
18361 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18362 // We are going to use the original vector elt for storing.
18363 // Accumulated smaller vector elements must be a multiple of the store size.
18364 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18366 unsigned SizeRatio = FromSz / ToSz;
18368 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18370 // Create a type on which we perform the shuffle
18371 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18372 StVT.getScalarType(), NumElems*SizeRatio);
18374 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18376 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18377 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18378 for (unsigned i = 0; i != NumElems; ++i)
18379 ShuffleVec[i] = i * SizeRatio;
18381 // Can't shuffle using an illegal type.
18382 if (!TLI.isTypeLegal(WideVecVT))
18385 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18386 DAG.getUNDEF(WideVecVT),
18388 // At this point all of the data is stored at the bottom of the
18389 // register. We now need to save it to mem.
18391 // Find the largest store unit
18392 MVT StoreType = MVT::i8;
18393 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18394 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18395 MVT Tp = (MVT::SimpleValueType)tp;
18396 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18400 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18401 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18402 (64 <= NumElems * ToSz))
18403 StoreType = MVT::f64;
18405 // Bitcast the original vector into a vector of store-size units
18406 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18407 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18408 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18409 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18410 SmallVector<SDValue, 8> Chains;
18411 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18412 TLI.getPointerTy());
18413 SDValue Ptr = St->getBasePtr();
18415 // Perform one or more big stores into memory.
18416 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18417 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18418 StoreType, ShuffWide,
18419 DAG.getIntPtrConstant(i));
18420 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18421 St->getPointerInfo(), St->isVolatile(),
18422 St->isNonTemporal(), St->getAlignment());
18423 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18424 Chains.push_back(Ch);
18427 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18431 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18432 // the FP state in cases where an emms may be missing.
18433 // A preferable solution to the general problem is to figure out the right
18434 // places to insert EMMS. This qualifies as a quick hack.
18436 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18437 if (VT.getSizeInBits() != 64)
18440 const Function *F = DAG.getMachineFunction().getFunction();
18441 bool NoImplicitFloatOps = F->getAttributes().
18442 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18443 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18444 && Subtarget->hasSSE2();
18445 if ((VT.isVector() ||
18446 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18447 isa<LoadSDNode>(St->getValue()) &&
18448 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18449 St->getChain().hasOneUse() && !St->isVolatile()) {
18450 SDNode* LdVal = St->getValue().getNode();
18451 LoadSDNode *Ld = 0;
18452 int TokenFactorIndex = -1;
18453 SmallVector<SDValue, 8> Ops;
18454 SDNode* ChainVal = St->getChain().getNode();
18455 // Must be a store of a load. We currently handle two cases: the load
18456 // is a direct child, and it's under an intervening TokenFactor. It is
18457 // possible to dig deeper under nested TokenFactors.
18458 if (ChainVal == LdVal)
18459 Ld = cast<LoadSDNode>(St->getChain());
18460 else if (St->getValue().hasOneUse() &&
18461 ChainVal->getOpcode() == ISD::TokenFactor) {
18462 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18463 if (ChainVal->getOperand(i).getNode() == LdVal) {
18464 TokenFactorIndex = i;
18465 Ld = cast<LoadSDNode>(St->getValue());
18467 Ops.push_back(ChainVal->getOperand(i));
18471 if (!Ld || !ISD::isNormalLoad(Ld))
18474 // If this is not the MMX case, i.e. we are just turning i64 load/store
18475 // into f64 load/store, avoid the transformation if there are multiple
18476 // uses of the loaded value.
18477 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18482 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18483 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18485 if (Subtarget->is64Bit() || F64IsLegal) {
18486 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18487 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18488 Ld->getPointerInfo(), Ld->isVolatile(),
18489 Ld->isNonTemporal(), Ld->isInvariant(),
18490 Ld->getAlignment());
18491 SDValue NewChain = NewLd.getValue(1);
18492 if (TokenFactorIndex != -1) {
18493 Ops.push_back(NewChain);
18494 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18497 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18498 St->getPointerInfo(),
18499 St->isVolatile(), St->isNonTemporal(),
18500 St->getAlignment());
18503 // Otherwise, lower to two pairs of 32-bit loads / stores.
18504 SDValue LoAddr = Ld->getBasePtr();
18505 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18506 DAG.getConstant(4, MVT::i32));
18508 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18509 Ld->getPointerInfo(),
18510 Ld->isVolatile(), Ld->isNonTemporal(),
18511 Ld->isInvariant(), Ld->getAlignment());
18512 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18513 Ld->getPointerInfo().getWithOffset(4),
18514 Ld->isVolatile(), Ld->isNonTemporal(),
18516 MinAlign(Ld->getAlignment(), 4));
18518 SDValue NewChain = LoLd.getValue(1);
18519 if (TokenFactorIndex != -1) {
18520 Ops.push_back(LoLd);
18521 Ops.push_back(HiLd);
18522 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18526 LoAddr = St->getBasePtr();
18527 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18528 DAG.getConstant(4, MVT::i32));
18530 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18531 St->getPointerInfo(),
18532 St->isVolatile(), St->isNonTemporal(),
18533 St->getAlignment());
18534 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18535 St->getPointerInfo().getWithOffset(4),
18537 St->isNonTemporal(),
18538 MinAlign(St->getAlignment(), 4));
18539 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18544 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18545 /// and return the operands for the horizontal operation in LHS and RHS. A
18546 /// horizontal operation performs the binary operation on successive elements
18547 /// of its first operand, then on successive elements of its second operand,
18548 /// returning the resulting values in a vector. For example, if
18549 /// A = < float a0, float a1, float a2, float a3 >
18551 /// B = < float b0, float b1, float b2, float b3 >
18552 /// then the result of doing a horizontal operation on A and B is
18553 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18554 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18555 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18556 /// set to A, RHS to B, and the routine returns 'true'.
18557 /// Note that the binary operation should have the property that if one of the
18558 /// operands is UNDEF then the result is UNDEF.
18559 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18560 // Look for the following pattern: if
18561 // A = < float a0, float a1, float a2, float a3 >
18562 // B = < float b0, float b1, float b2, float b3 >
18564 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18565 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18566 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18567 // which is A horizontal-op B.
18569 // At least one of the operands should be a vector shuffle.
18570 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18571 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18574 MVT VT = LHS.getSimpleValueType();
18576 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18577 "Unsupported vector type for horizontal add/sub");
18579 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18580 // operate independently on 128-bit lanes.
18581 unsigned NumElts = VT.getVectorNumElements();
18582 unsigned NumLanes = VT.getSizeInBits()/128;
18583 unsigned NumLaneElts = NumElts / NumLanes;
18584 assert((NumLaneElts % 2 == 0) &&
18585 "Vector type should have an even number of elements in each lane");
18586 unsigned HalfLaneElts = NumLaneElts/2;
18588 // View LHS in the form
18589 // LHS = VECTOR_SHUFFLE A, B, LMask
18590 // If LHS is not a shuffle then pretend it is the shuffle
18591 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18592 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18595 SmallVector<int, 16> LMask(NumElts);
18596 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18597 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18598 A = LHS.getOperand(0);
18599 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18600 B = LHS.getOperand(1);
18601 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18602 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18604 if (LHS.getOpcode() != ISD::UNDEF)
18606 for (unsigned i = 0; i != NumElts; ++i)
18610 // Likewise, view RHS in the form
18611 // RHS = VECTOR_SHUFFLE C, D, RMask
18613 SmallVector<int, 16> RMask(NumElts);
18614 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18615 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18616 C = RHS.getOperand(0);
18617 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18618 D = RHS.getOperand(1);
18619 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18620 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18622 if (RHS.getOpcode() != ISD::UNDEF)
18624 for (unsigned i = 0; i != NumElts; ++i)
18628 // Check that the shuffles are both shuffling the same vectors.
18629 if (!(A == C && B == D) && !(A == D && B == C))
18632 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18633 if (!A.getNode() && !B.getNode())
18636 // If A and B occur in reverse order in RHS, then "swap" them (which means
18637 // rewriting the mask).
18639 CommuteVectorShuffleMask(RMask, NumElts);
18641 // At this point LHS and RHS are equivalent to
18642 // LHS = VECTOR_SHUFFLE A, B, LMask
18643 // RHS = VECTOR_SHUFFLE A, B, RMask
18644 // Check that the masks correspond to performing a horizontal operation.
18645 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18646 for (unsigned i = 0; i != NumLaneElts; ++i) {
18647 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18649 // Ignore any UNDEF components.
18650 if (LIdx < 0 || RIdx < 0 ||
18651 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18652 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18655 // Check that successive elements are being operated on. If not, this is
18656 // not a horizontal operation.
18657 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18658 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18659 if (!(LIdx == Index && RIdx == Index + 1) &&
18660 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18665 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18666 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18670 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18671 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18672 const X86Subtarget *Subtarget) {
18673 EVT VT = N->getValueType(0);
18674 SDValue LHS = N->getOperand(0);
18675 SDValue RHS = N->getOperand(1);
18677 // Try to synthesize horizontal adds from adds of shuffles.
18678 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18679 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18680 isHorizontalBinOp(LHS, RHS, true))
18681 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18685 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18686 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18687 const X86Subtarget *Subtarget) {
18688 EVT VT = N->getValueType(0);
18689 SDValue LHS = N->getOperand(0);
18690 SDValue RHS = N->getOperand(1);
18692 // Try to synthesize horizontal subs from subs of shuffles.
18693 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18694 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18695 isHorizontalBinOp(LHS, RHS, false))
18696 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18700 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18701 /// X86ISD::FXOR nodes.
18702 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18703 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18704 // F[X]OR(0.0, x) -> x
18705 // F[X]OR(x, 0.0) -> x
18706 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18707 if (C->getValueAPF().isPosZero())
18708 return N->getOperand(1);
18709 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18710 if (C->getValueAPF().isPosZero())
18711 return N->getOperand(0);
18715 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18716 /// X86ISD::FMAX nodes.
18717 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18718 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18720 // Only perform optimizations if UnsafeMath is used.
18721 if (!DAG.getTarget().Options.UnsafeFPMath)
18724 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18725 // into FMINC and FMAXC, which are Commutative operations.
18726 unsigned NewOp = 0;
18727 switch (N->getOpcode()) {
18728 default: llvm_unreachable("unknown opcode");
18729 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18730 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18733 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18734 N->getOperand(0), N->getOperand(1));
18737 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18738 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18739 // FAND(0.0, x) -> 0.0
18740 // FAND(x, 0.0) -> 0.0
18741 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18742 if (C->getValueAPF().isPosZero())
18743 return N->getOperand(0);
18744 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18745 if (C->getValueAPF().isPosZero())
18746 return N->getOperand(1);
18750 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18751 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18752 // FANDN(x, 0.0) -> 0.0
18753 // FANDN(0.0, x) -> x
18754 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18755 if (C->getValueAPF().isPosZero())
18756 return N->getOperand(1);
18757 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18758 if (C->getValueAPF().isPosZero())
18759 return N->getOperand(1);
18763 static SDValue PerformBTCombine(SDNode *N,
18765 TargetLowering::DAGCombinerInfo &DCI) {
18766 // BT ignores high bits in the bit index operand.
18767 SDValue Op1 = N->getOperand(1);
18768 if (Op1.hasOneUse()) {
18769 unsigned BitWidth = Op1.getValueSizeInBits();
18770 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18771 APInt KnownZero, KnownOne;
18772 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18773 !DCI.isBeforeLegalizeOps());
18774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18775 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18776 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18777 DCI.CommitTargetLoweringOpt(TLO);
18782 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18783 SDValue Op = N->getOperand(0);
18784 if (Op.getOpcode() == ISD::BITCAST)
18785 Op = Op.getOperand(0);
18786 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18787 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18788 VT.getVectorElementType().getSizeInBits() ==
18789 OpVT.getVectorElementType().getSizeInBits()) {
18790 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18795 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18796 const X86Subtarget *Subtarget) {
18797 EVT VT = N->getValueType(0);
18798 if (!VT.isVector())
18801 SDValue N0 = N->getOperand(0);
18802 SDValue N1 = N->getOperand(1);
18803 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18806 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18807 // both SSE and AVX2 since there is no sign-extended shift right
18808 // operation on a vector with 64-bit elements.
18809 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18810 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18811 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18812 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18813 SDValue N00 = N0.getOperand(0);
18815 // EXTLOAD has a better solution on AVX2,
18816 // it may be replaced with X86ISD::VSEXT node.
18817 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18818 if (!ISD::isNormalLoad(N00.getNode()))
18821 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18822 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18824 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18830 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18831 TargetLowering::DAGCombinerInfo &DCI,
18832 const X86Subtarget *Subtarget) {
18833 if (!DCI.isBeforeLegalizeOps())
18836 if (!Subtarget->hasFp256())
18839 EVT VT = N->getValueType(0);
18840 if (VT.isVector() && VT.getSizeInBits() == 256) {
18841 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18849 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18850 const X86Subtarget* Subtarget) {
18852 EVT VT = N->getValueType(0);
18854 // Let legalize expand this if it isn't a legal type yet.
18855 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18858 EVT ScalarVT = VT.getScalarType();
18859 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18860 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18863 SDValue A = N->getOperand(0);
18864 SDValue B = N->getOperand(1);
18865 SDValue C = N->getOperand(2);
18867 bool NegA = (A.getOpcode() == ISD::FNEG);
18868 bool NegB = (B.getOpcode() == ISD::FNEG);
18869 bool NegC = (C.getOpcode() == ISD::FNEG);
18871 // Negative multiplication when NegA xor NegB
18872 bool NegMul = (NegA != NegB);
18874 A = A.getOperand(0);
18876 B = B.getOperand(0);
18878 C = C.getOperand(0);
18882 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18884 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18886 return DAG.getNode(Opcode, dl, VT, A, B, C);
18889 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18890 TargetLowering::DAGCombinerInfo &DCI,
18891 const X86Subtarget *Subtarget) {
18892 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18893 // (and (i32 x86isd::setcc_carry), 1)
18894 // This eliminates the zext. This transformation is necessary because
18895 // ISD::SETCC is always legalized to i8.
18897 SDValue N0 = N->getOperand(0);
18898 EVT VT = N->getValueType(0);
18900 if (N0.getOpcode() == ISD::AND &&
18902 N0.getOperand(0).hasOneUse()) {
18903 SDValue N00 = N0.getOperand(0);
18904 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18905 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18906 if (!C || C->getZExtValue() != 1)
18908 return DAG.getNode(ISD::AND, dl, VT,
18909 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18910 N00.getOperand(0), N00.getOperand(1)),
18911 DAG.getConstant(1, VT));
18915 if (VT.is256BitVector()) {
18916 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18924 // Optimize x == -y --> x+y == 0
18925 // x != -y --> x+y != 0
18926 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18927 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18928 SDValue LHS = N->getOperand(0);
18929 SDValue RHS = N->getOperand(1);
18931 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18932 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18933 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18934 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18935 LHS.getValueType(), RHS, LHS.getOperand(1));
18936 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18937 addV, DAG.getConstant(0, addV.getValueType()), CC);
18939 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18941 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18942 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18943 RHS.getValueType(), LHS, RHS.getOperand(1));
18944 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18945 addV, DAG.getConstant(0, addV.getValueType()), CC);
18950 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18951 // as "sbb reg,reg", since it can be extended without zext and produces
18952 // an all-ones bit which is more useful than 0/1 in some cases.
18953 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18954 return DAG.getNode(ISD::AND, DL, MVT::i8,
18955 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18956 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18957 DAG.getConstant(1, MVT::i8));
18960 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18961 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18962 TargetLowering::DAGCombinerInfo &DCI,
18963 const X86Subtarget *Subtarget) {
18965 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18966 SDValue EFLAGS = N->getOperand(1);
18968 if (CC == X86::COND_A) {
18969 // Try to convert COND_A into COND_B in an attempt to facilitate
18970 // materializing "setb reg".
18972 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18973 // cannot take an immediate as its first operand.
18975 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18976 EFLAGS.getValueType().isInteger() &&
18977 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18978 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18979 EFLAGS.getNode()->getVTList(),
18980 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18981 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18982 return MaterializeSETB(DL, NewEFLAGS, DAG);
18986 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18987 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18989 if (CC == X86::COND_B)
18990 return MaterializeSETB(DL, EFLAGS, DAG);
18994 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18995 if (Flags.getNode()) {
18996 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18997 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19003 // Optimize branch condition evaluation.
19005 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19006 TargetLowering::DAGCombinerInfo &DCI,
19007 const X86Subtarget *Subtarget) {
19009 SDValue Chain = N->getOperand(0);
19010 SDValue Dest = N->getOperand(1);
19011 SDValue EFLAGS = N->getOperand(3);
19012 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19016 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19017 if (Flags.getNode()) {
19018 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19019 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19026 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19027 const X86TargetLowering *XTLI) {
19028 SDValue Op0 = N->getOperand(0);
19029 EVT InVT = Op0->getValueType(0);
19031 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19032 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19034 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19035 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19036 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19039 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19040 // a 32-bit target where SSE doesn't support i64->FP operations.
19041 if (Op0.getOpcode() == ISD::LOAD) {
19042 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19043 EVT VT = Ld->getValueType(0);
19044 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19045 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19046 !XTLI->getSubtarget()->is64Bit() &&
19048 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19049 Ld->getChain(), Op0, DAG);
19050 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19057 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19058 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19059 X86TargetLowering::DAGCombinerInfo &DCI) {
19060 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19061 // the result is either zero or one (depending on the input carry bit).
19062 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19063 if (X86::isZeroNode(N->getOperand(0)) &&
19064 X86::isZeroNode(N->getOperand(1)) &&
19065 // We don't have a good way to replace an EFLAGS use, so only do this when
19067 SDValue(N, 1).use_empty()) {
19069 EVT VT = N->getValueType(0);
19070 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19071 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19072 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19073 DAG.getConstant(X86::COND_B,MVT::i8),
19075 DAG.getConstant(1, VT));
19076 return DCI.CombineTo(N, Res1, CarryOut);
19082 // fold (add Y, (sete X, 0)) -> adc 0, Y
19083 // (add Y, (setne X, 0)) -> sbb -1, Y
19084 // (sub (sete X, 0), Y) -> sbb 0, Y
19085 // (sub (setne X, 0), Y) -> adc -1, Y
19086 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19089 // Look through ZExts.
19090 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19091 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19094 SDValue SetCC = Ext.getOperand(0);
19095 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19098 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19099 if (CC != X86::COND_E && CC != X86::COND_NE)
19102 SDValue Cmp = SetCC.getOperand(1);
19103 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19104 !X86::isZeroNode(Cmp.getOperand(1)) ||
19105 !Cmp.getOperand(0).getValueType().isInteger())
19108 SDValue CmpOp0 = Cmp.getOperand(0);
19109 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19110 DAG.getConstant(1, CmpOp0.getValueType()));
19112 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19113 if (CC == X86::COND_NE)
19114 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19115 DL, OtherVal.getValueType(), OtherVal,
19116 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19117 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19118 DL, OtherVal.getValueType(), OtherVal,
19119 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19122 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19123 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19124 const X86Subtarget *Subtarget) {
19125 EVT VT = N->getValueType(0);
19126 SDValue Op0 = N->getOperand(0);
19127 SDValue Op1 = N->getOperand(1);
19129 // Try to synthesize horizontal adds from adds of shuffles.
19130 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19131 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19132 isHorizontalBinOp(Op0, Op1, true))
19133 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19135 return OptimizeConditionalInDecrement(N, DAG);
19138 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19139 const X86Subtarget *Subtarget) {
19140 SDValue Op0 = N->getOperand(0);
19141 SDValue Op1 = N->getOperand(1);
19143 // X86 can't encode an immediate LHS of a sub. See if we can push the
19144 // negation into a preceding instruction.
19145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19146 // If the RHS of the sub is a XOR with one use and a constant, invert the
19147 // immediate. Then add one to the LHS of the sub so we can turn
19148 // X-Y -> X+~Y+1, saving one register.
19149 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19150 isa<ConstantSDNode>(Op1.getOperand(1))) {
19151 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19152 EVT VT = Op0.getValueType();
19153 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19155 DAG.getConstant(~XorC, VT));
19156 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19157 DAG.getConstant(C->getAPIntValue()+1, VT));
19161 // Try to synthesize horizontal adds from adds of shuffles.
19162 EVT VT = N->getValueType(0);
19163 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19164 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19165 isHorizontalBinOp(Op0, Op1, true))
19166 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19168 return OptimizeConditionalInDecrement(N, DAG);
19171 /// performVZEXTCombine - Performs build vector combines
19172 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19173 TargetLowering::DAGCombinerInfo &DCI,
19174 const X86Subtarget *Subtarget) {
19175 // (vzext (bitcast (vzext (x)) -> (vzext x)
19176 SDValue In = N->getOperand(0);
19177 while (In.getOpcode() == ISD::BITCAST)
19178 In = In.getOperand(0);
19180 if (In.getOpcode() != X86ISD::VZEXT)
19183 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19187 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19188 DAGCombinerInfo &DCI) const {
19189 SelectionDAG &DAG = DCI.DAG;
19190 switch (N->getOpcode()) {
19192 case ISD::EXTRACT_VECTOR_ELT:
19193 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19195 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19196 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19197 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19198 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19199 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19200 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19203 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19204 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19205 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19206 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19207 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19208 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19209 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19210 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19211 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19213 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19215 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19216 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19217 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19218 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19219 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19220 case ISD::ANY_EXTEND:
19221 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19222 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19223 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19224 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19225 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19226 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19227 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19228 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19229 case X86ISD::SHUFP: // Handle all target specific shuffles
19230 case X86ISD::PALIGNR:
19231 case X86ISD::UNPCKH:
19232 case X86ISD::UNPCKL:
19233 case X86ISD::MOVHLPS:
19234 case X86ISD::MOVLHPS:
19235 case X86ISD::PSHUFD:
19236 case X86ISD::PSHUFHW:
19237 case X86ISD::PSHUFLW:
19238 case X86ISD::MOVSS:
19239 case X86ISD::MOVSD:
19240 case X86ISD::VPERMILP:
19241 case X86ISD::VPERM2X128:
19242 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19243 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19249 /// isTypeDesirableForOp - Return true if the target has native support for
19250 /// the specified value type and it is 'desirable' to use the type for the
19251 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19252 /// instruction encodings are longer and some i16 instructions are slow.
19253 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19254 if (!isTypeLegal(VT))
19256 if (VT != MVT::i16)
19263 case ISD::SIGN_EXTEND:
19264 case ISD::ZERO_EXTEND:
19265 case ISD::ANY_EXTEND:
19278 /// IsDesirableToPromoteOp - This method query the target whether it is
19279 /// beneficial for dag combiner to promote the specified node. If true, it
19280 /// should return the desired promotion type by reference.
19281 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19282 EVT VT = Op.getValueType();
19283 if (VT != MVT::i16)
19286 bool Promote = false;
19287 bool Commute = false;
19288 switch (Op.getOpcode()) {
19291 LoadSDNode *LD = cast<LoadSDNode>(Op);
19292 // If the non-extending load has a single use and it's not live out, then it
19293 // might be folded.
19294 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19295 Op.hasOneUse()*/) {
19296 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19297 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19298 // The only case where we'd want to promote LOAD (rather then it being
19299 // promoted as an operand is when it's only use is liveout.
19300 if (UI->getOpcode() != ISD::CopyToReg)
19307 case ISD::SIGN_EXTEND:
19308 case ISD::ZERO_EXTEND:
19309 case ISD::ANY_EXTEND:
19314 SDValue N0 = Op.getOperand(0);
19315 // Look out for (store (shl (load), x)).
19316 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19329 SDValue N0 = Op.getOperand(0);
19330 SDValue N1 = Op.getOperand(1);
19331 if (!Commute && MayFoldLoad(N1))
19333 // Avoid disabling potential load folding opportunities.
19334 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19336 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19346 //===----------------------------------------------------------------------===//
19347 // X86 Inline Assembly Support
19348 //===----------------------------------------------------------------------===//
19351 // Helper to match a string separated by whitespace.
19352 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19353 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19355 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19356 StringRef piece(*args[i]);
19357 if (!s.startswith(piece)) // Check if the piece matches.
19360 s = s.substr(piece.size());
19361 StringRef::size_type pos = s.find_first_not_of(" \t");
19362 if (pos == 0) // We matched a prefix.
19370 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19373 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19375 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19376 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19377 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19378 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19380 if (AsmPieces.size() == 3)
19382 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19389 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19390 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19392 std::string AsmStr = IA->getAsmString();
19394 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19395 if (!Ty || Ty->getBitWidth() % 16 != 0)
19398 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19399 SmallVector<StringRef, 4> AsmPieces;
19400 SplitString(AsmStr, AsmPieces, ";\n");
19402 switch (AsmPieces.size()) {
19403 default: return false;
19405 // FIXME: this should verify that we are targeting a 486 or better. If not,
19406 // we will turn this bswap into something that will be lowered to logical
19407 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19408 // lower so don't worry about this.
19410 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19411 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19412 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19413 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19414 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19415 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19416 // No need to check constraints, nothing other than the equivalent of
19417 // "=r,0" would be valid here.
19418 return IntrinsicLowering::LowerToByteSwap(CI);
19421 // rorw $$8, ${0:w} --> llvm.bswap.i16
19422 if (CI->getType()->isIntegerTy(16) &&
19423 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19424 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19425 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19427 const std::string &ConstraintsStr = IA->getConstraintString();
19428 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19429 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19430 if (clobbersFlagRegisters(AsmPieces))
19431 return IntrinsicLowering::LowerToByteSwap(CI);
19435 if (CI->getType()->isIntegerTy(32) &&
19436 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19437 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19438 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19439 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19441 const std::string &ConstraintsStr = IA->getConstraintString();
19442 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19443 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19444 if (clobbersFlagRegisters(AsmPieces))
19445 return IntrinsicLowering::LowerToByteSwap(CI);
19448 if (CI->getType()->isIntegerTy(64)) {
19449 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19450 if (Constraints.size() >= 2 &&
19451 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19452 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19453 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19454 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19455 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19456 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19457 return IntrinsicLowering::LowerToByteSwap(CI);
19465 /// getConstraintType - Given a constraint letter, return the type of
19466 /// constraint it is for this target.
19467 X86TargetLowering::ConstraintType
19468 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19469 if (Constraint.size() == 1) {
19470 switch (Constraint[0]) {
19481 return C_RegisterClass;
19505 return TargetLowering::getConstraintType(Constraint);
19508 /// Examine constraint type and operand type and determine a weight value.
19509 /// This object must already have been set up with the operand type
19510 /// and the current alternative constraint selected.
19511 TargetLowering::ConstraintWeight
19512 X86TargetLowering::getSingleConstraintMatchWeight(
19513 AsmOperandInfo &info, const char *constraint) const {
19514 ConstraintWeight weight = CW_Invalid;
19515 Value *CallOperandVal = info.CallOperandVal;
19516 // If we don't have a value, we can't do a match,
19517 // but allow it at the lowest weight.
19518 if (CallOperandVal == NULL)
19520 Type *type = CallOperandVal->getType();
19521 // Look at the constraint type.
19522 switch (*constraint) {
19524 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19535 if (CallOperandVal->getType()->isIntegerTy())
19536 weight = CW_SpecificReg;
19541 if (type->isFloatingPointTy())
19542 weight = CW_SpecificReg;
19545 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19546 weight = CW_SpecificReg;
19550 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19551 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19552 weight = CW_Register;
19555 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19556 if (C->getZExtValue() <= 31)
19557 weight = CW_Constant;
19561 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19562 if (C->getZExtValue() <= 63)
19563 weight = CW_Constant;
19567 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19568 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19569 weight = CW_Constant;
19573 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19574 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19575 weight = CW_Constant;
19579 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19580 if (C->getZExtValue() <= 3)
19581 weight = CW_Constant;
19585 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19586 if (C->getZExtValue() <= 0xff)
19587 weight = CW_Constant;
19592 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19593 weight = CW_Constant;
19597 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19598 if ((C->getSExtValue() >= -0x80000000LL) &&
19599 (C->getSExtValue() <= 0x7fffffffLL))
19600 weight = CW_Constant;
19604 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19605 if (C->getZExtValue() <= 0xffffffff)
19606 weight = CW_Constant;
19613 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19614 /// with another that has more specific requirements based on the type of the
19615 /// corresponding operand.
19616 const char *X86TargetLowering::
19617 LowerXConstraint(EVT ConstraintVT) const {
19618 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19619 // 'f' like normal targets.
19620 if (ConstraintVT.isFloatingPoint()) {
19621 if (Subtarget->hasSSE2())
19623 if (Subtarget->hasSSE1())
19627 return TargetLowering::LowerXConstraint(ConstraintVT);
19630 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19631 /// vector. If it is invalid, don't add anything to Ops.
19632 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19633 std::string &Constraint,
19634 std::vector<SDValue>&Ops,
19635 SelectionDAG &DAG) const {
19636 SDValue Result(0, 0);
19638 // Only support length 1 constraints for now.
19639 if (Constraint.length() > 1) return;
19641 char ConstraintLetter = Constraint[0];
19642 switch (ConstraintLetter) {
19645 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19646 if (C->getZExtValue() <= 31) {
19647 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19653 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19654 if (C->getZExtValue() <= 63) {
19655 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19661 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19662 if (isInt<8>(C->getSExtValue())) {
19663 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19669 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19670 if (C->getZExtValue() <= 255) {
19671 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19677 // 32-bit signed value
19678 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19679 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19680 C->getSExtValue())) {
19681 // Widen to 64 bits here to get it sign extended.
19682 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19685 // FIXME gcc accepts some relocatable values here too, but only in certain
19686 // memory models; it's complicated.
19691 // 32-bit unsigned value
19692 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19693 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19694 C->getZExtValue())) {
19695 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19699 // FIXME gcc accepts some relocatable values here too, but only in certain
19700 // memory models; it's complicated.
19704 // Literal immediates are always ok.
19705 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19706 // Widen to 64 bits here to get it sign extended.
19707 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19711 // In any sort of PIC mode addresses need to be computed at runtime by
19712 // adding in a register or some sort of table lookup. These can't
19713 // be used as immediates.
19714 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19717 // If we are in non-pic codegen mode, we allow the address of a global (with
19718 // an optional displacement) to be used with 'i'.
19719 GlobalAddressSDNode *GA = 0;
19720 int64_t Offset = 0;
19722 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19724 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19725 Offset += GA->getOffset();
19727 } else if (Op.getOpcode() == ISD::ADD) {
19728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19729 Offset += C->getZExtValue();
19730 Op = Op.getOperand(0);
19733 } else if (Op.getOpcode() == ISD::SUB) {
19734 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19735 Offset += -C->getZExtValue();
19736 Op = Op.getOperand(0);
19741 // Otherwise, this isn't something we can handle, reject it.
19745 const GlobalValue *GV = GA->getGlobal();
19746 // If we require an extra load to get this address, as in PIC mode, we
19747 // can't accept it.
19748 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19749 getTargetMachine())))
19752 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19753 GA->getValueType(0), Offset);
19758 if (Result.getNode()) {
19759 Ops.push_back(Result);
19762 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19765 std::pair<unsigned, const TargetRegisterClass*>
19766 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19768 // First, see if this is a constraint that directly corresponds to an LLVM
19770 if (Constraint.size() == 1) {
19771 // GCC Constraint Letters
19772 switch (Constraint[0]) {
19774 // TODO: Slight differences here in allocation order and leaving
19775 // RIP in the class. Do they matter any more here than they do
19776 // in the normal allocation?
19777 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19778 if (Subtarget->is64Bit()) {
19779 if (VT == MVT::i32 || VT == MVT::f32)
19780 return std::make_pair(0U, &X86::GR32RegClass);
19781 if (VT == MVT::i16)
19782 return std::make_pair(0U, &X86::GR16RegClass);
19783 if (VT == MVT::i8 || VT == MVT::i1)
19784 return std::make_pair(0U, &X86::GR8RegClass);
19785 if (VT == MVT::i64 || VT == MVT::f64)
19786 return std::make_pair(0U, &X86::GR64RegClass);
19789 // 32-bit fallthrough
19790 case 'Q': // Q_REGS
19791 if (VT == MVT::i32 || VT == MVT::f32)
19792 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19793 if (VT == MVT::i16)
19794 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19795 if (VT == MVT::i8 || VT == MVT::i1)
19796 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19797 if (VT == MVT::i64)
19798 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19800 case 'r': // GENERAL_REGS
19801 case 'l': // INDEX_REGS
19802 if (VT == MVT::i8 || VT == MVT::i1)
19803 return std::make_pair(0U, &X86::GR8RegClass);
19804 if (VT == MVT::i16)
19805 return std::make_pair(0U, &X86::GR16RegClass);
19806 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19807 return std::make_pair(0U, &X86::GR32RegClass);
19808 return std::make_pair(0U, &X86::GR64RegClass);
19809 case 'R': // LEGACY_REGS
19810 if (VT == MVT::i8 || VT == MVT::i1)
19811 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19812 if (VT == MVT::i16)
19813 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19814 if (VT == MVT::i32 || !Subtarget->is64Bit())
19815 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19816 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19817 case 'f': // FP Stack registers.
19818 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19819 // value to the correct fpstack register class.
19820 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19821 return std::make_pair(0U, &X86::RFP32RegClass);
19822 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19823 return std::make_pair(0U, &X86::RFP64RegClass);
19824 return std::make_pair(0U, &X86::RFP80RegClass);
19825 case 'y': // MMX_REGS if MMX allowed.
19826 if (!Subtarget->hasMMX()) break;
19827 return std::make_pair(0U, &X86::VR64RegClass);
19828 case 'Y': // SSE_REGS if SSE2 allowed
19829 if (!Subtarget->hasSSE2()) break;
19831 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19832 if (!Subtarget->hasSSE1()) break;
19834 switch (VT.SimpleTy) {
19836 // Scalar SSE types.
19839 return std::make_pair(0U, &X86::FR32RegClass);
19842 return std::make_pair(0U, &X86::FR64RegClass);
19850 return std::make_pair(0U, &X86::VR128RegClass);
19858 return std::make_pair(0U, &X86::VR256RegClass);
19863 return std::make_pair(0U, &X86::VR512RegClass);
19869 // Use the default implementation in TargetLowering to convert the register
19870 // constraint into a member of a register class.
19871 std::pair<unsigned, const TargetRegisterClass*> Res;
19872 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19874 // Not found as a standard register?
19875 if (Res.second == 0) {
19876 // Map st(0) -> st(7) -> ST0
19877 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19878 tolower(Constraint[1]) == 's' &&
19879 tolower(Constraint[2]) == 't' &&
19880 Constraint[3] == '(' &&
19881 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19882 Constraint[5] == ')' &&
19883 Constraint[6] == '}') {
19885 Res.first = X86::ST0+Constraint[4]-'0';
19886 Res.second = &X86::RFP80RegClass;
19890 // GCC allows "st(0)" to be called just plain "st".
19891 if (StringRef("{st}").equals_lower(Constraint)) {
19892 Res.first = X86::ST0;
19893 Res.second = &X86::RFP80RegClass;
19898 if (StringRef("{flags}").equals_lower(Constraint)) {
19899 Res.first = X86::EFLAGS;
19900 Res.second = &X86::CCRRegClass;
19904 // 'A' means EAX + EDX.
19905 if (Constraint == "A") {
19906 Res.first = X86::EAX;
19907 Res.second = &X86::GR32_ADRegClass;
19913 // Otherwise, check to see if this is a register class of the wrong value
19914 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19915 // turn into {ax},{dx}.
19916 if (Res.second->hasType(VT))
19917 return Res; // Correct type already, nothing to do.
19919 // All of the single-register GCC register classes map their values onto
19920 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19921 // really want an 8-bit or 32-bit register, map to the appropriate register
19922 // class and return the appropriate register.
19923 if (Res.second == &X86::GR16RegClass) {
19924 if (VT == MVT::i8 || VT == MVT::i1) {
19925 unsigned DestReg = 0;
19926 switch (Res.first) {
19928 case X86::AX: DestReg = X86::AL; break;
19929 case X86::DX: DestReg = X86::DL; break;
19930 case X86::CX: DestReg = X86::CL; break;
19931 case X86::BX: DestReg = X86::BL; break;
19934 Res.first = DestReg;
19935 Res.second = &X86::GR8RegClass;
19937 } else if (VT == MVT::i32 || VT == MVT::f32) {
19938 unsigned DestReg = 0;
19939 switch (Res.first) {
19941 case X86::AX: DestReg = X86::EAX; break;
19942 case X86::DX: DestReg = X86::EDX; break;
19943 case X86::CX: DestReg = X86::ECX; break;
19944 case X86::BX: DestReg = X86::EBX; break;
19945 case X86::SI: DestReg = X86::ESI; break;
19946 case X86::DI: DestReg = X86::EDI; break;
19947 case X86::BP: DestReg = X86::EBP; break;
19948 case X86::SP: DestReg = X86::ESP; break;
19951 Res.first = DestReg;
19952 Res.second = &X86::GR32RegClass;
19954 } else if (VT == MVT::i64 || VT == MVT::f64) {
19955 unsigned DestReg = 0;
19956 switch (Res.first) {
19958 case X86::AX: DestReg = X86::RAX; break;
19959 case X86::DX: DestReg = X86::RDX; break;
19960 case X86::CX: DestReg = X86::RCX; break;
19961 case X86::BX: DestReg = X86::RBX; break;
19962 case X86::SI: DestReg = X86::RSI; break;
19963 case X86::DI: DestReg = X86::RDI; break;
19964 case X86::BP: DestReg = X86::RBP; break;
19965 case X86::SP: DestReg = X86::RSP; break;
19968 Res.first = DestReg;
19969 Res.second = &X86::GR64RegClass;
19972 } else if (Res.second == &X86::FR32RegClass ||
19973 Res.second == &X86::FR64RegClass ||
19974 Res.second == &X86::VR128RegClass ||
19975 Res.second == &X86::VR256RegClass ||
19976 Res.second == &X86::FR32XRegClass ||
19977 Res.second == &X86::FR64XRegClass ||
19978 Res.second == &X86::VR128XRegClass ||
19979 Res.second == &X86::VR256XRegClass ||
19980 Res.second == &X86::VR512RegClass) {
19981 // Handle references to XMM physical registers that got mapped into the
19982 // wrong class. This can happen with constraints like {xmm0} where the
19983 // target independent register mapper will just pick the first match it can
19984 // find, ignoring the required type.
19986 if (VT == MVT::f32 || VT == MVT::i32)
19987 Res.second = &X86::FR32RegClass;
19988 else if (VT == MVT::f64 || VT == MVT::i64)
19989 Res.second = &X86::FR64RegClass;
19990 else if (X86::VR128RegClass.hasType(VT))
19991 Res.second = &X86::VR128RegClass;
19992 else if (X86::VR256RegClass.hasType(VT))
19993 Res.second = &X86::VR256RegClass;
19994 else if (X86::VR512RegClass.hasType(VT))
19995 Res.second = &X86::VR512RegClass;