1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<bool> ExperimentalVectorShuffleLegality(
75 "x86-experimental-vector-shuffle-legality", cl::init(false),
76 cl::desc("Enable experimental shuffle legality based on the experimental "
77 "shuffle lowering. Should only be used with the experimental "
81 static cl::opt<int> ReciprocalEstimateRefinementSteps(
82 "x86-recip-refinement-steps", cl::init(1),
83 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
84 "result of the hardware reciprocal estimate instruction."),
87 // Forward declarations.
88 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
91 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
92 SelectionDAG &DAG, SDLoc dl,
93 unsigned vectorWidth) {
94 assert((vectorWidth == 128 || vectorWidth == 256) &&
95 "Unsupported vector width");
96 EVT VT = Vec.getValueType();
97 EVT ElVT = VT.getVectorElementType();
98 unsigned Factor = VT.getSizeInBits()/vectorWidth;
99 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
100 VT.getVectorNumElements()/Factor);
102 // Extract from UNDEF is UNDEF.
103 if (Vec.getOpcode() == ISD::UNDEF)
104 return DAG.getUNDEF(ResultVT);
106 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
107 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
109 // This is the index of the first element of the vectorWidth-bit chunk
111 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
114 // If the input is a buildvector just emit a smaller one.
115 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
116 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
117 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
120 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
121 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
124 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
125 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
126 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
127 /// instructions or a simple subregister reference. Idx is an index in the
128 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
129 /// lowering EXTRACT_VECTOR_ELT operations easier.
130 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
131 SelectionDAG &DAG, SDLoc dl) {
132 assert((Vec.getValueType().is256BitVector() ||
133 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
137 /// Generate a DAG to grab 256-bits from a 512-bit vector.
138 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
139 SelectionDAG &DAG, SDLoc dl) {
140 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
141 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
144 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
145 unsigned IdxVal, SelectionDAG &DAG,
146 SDLoc dl, unsigned vectorWidth) {
147 assert((vectorWidth == 128 || vectorWidth == 256) &&
148 "Unsupported vector width");
149 // Inserting UNDEF is Result
150 if (Vec.getOpcode() == ISD::UNDEF)
152 EVT VT = Vec.getValueType();
153 EVT ElVT = VT.getVectorElementType();
154 EVT ResultVT = Result.getValueType();
156 // Insert the relevant vectorWidth bits.
157 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
159 // This is the index of the first element of the vectorWidth-bit chunk
161 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
164 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
165 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
168 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
169 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
170 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
171 /// simple superregister reference. Idx is an index in the 128 bits
172 /// we want. It need not be aligned to a 128-bit boundary. That makes
173 /// lowering INSERT_VECTOR_ELT operations easier.
174 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
175 SelectionDAG &DAG,SDLoc dl) {
176 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
177 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
180 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
181 SelectionDAG &DAG, SDLoc dl) {
182 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
183 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
186 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
187 /// instructions. This is used because creating CONCAT_VECTOR nodes of
188 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
189 /// large BUILD_VECTORS.
190 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
197 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
198 unsigned NumElems, SelectionDAG &DAG,
200 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
201 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
204 // FIXME: This should stop caching the target machine as soon as
205 // we can remove resetOperationActions et al.
206 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
207 : TargetLowering(TM) {
208 Subtarget = &TM.getSubtarget<X86Subtarget>();
209 X86ScalarSSEf64 = Subtarget->hasSSE2();
210 X86ScalarSSEf32 = Subtarget->hasSSE1();
211 TD = getDataLayout();
213 resetOperationActions();
216 void X86TargetLowering::resetOperationActions() {
217 const TargetMachine &TM = getTargetMachine();
218 static bool FirstTimeThrough = true;
220 // If none of the target options have changed, then we don't need to reset the
221 // operation actions.
222 if (!FirstTimeThrough && TO == TM.Options) return;
224 if (!FirstTimeThrough) {
225 // Reinitialize the actions.
227 FirstTimeThrough = false;
232 // Set up the TargetLowering object.
233 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
235 // X86 is weird. It always uses i8 for shift amounts and setcc results.
236 setBooleanContents(ZeroOrOneBooleanContent);
237 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
238 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
240 // For 64-bit, since we have so many registers, use the ILP scheduler.
241 // For 32-bit, use the register pressure specific scheduling.
242 // For Atom, always use ILP scheduling.
243 if (Subtarget->isAtom())
244 setSchedulingPreference(Sched::ILP);
245 else if (Subtarget->is64Bit())
246 setSchedulingPreference(Sched::ILP);
248 setSchedulingPreference(Sched::RegPressure);
249 const X86RegisterInfo *RegInfo =
250 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
251 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
253 // Bypass expensive divides on Atom when compiling with O2.
254 if (TM.getOptLevel() >= CodeGenOpt::Default) {
255 if (Subtarget->hasSlowDivide32())
256 addBypassSlowDiv(32, 8);
257 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
258 addBypassSlowDiv(64, 16);
261 if (Subtarget->isTargetKnownWindowsMSVC()) {
262 // Setup Windows compiler runtime calls.
263 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
264 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
265 setLibcallName(RTLIB::SREM_I64, "_allrem");
266 setLibcallName(RTLIB::UREM_I64, "_aullrem");
267 setLibcallName(RTLIB::MUL_I64, "_allmul");
268 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
271 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
272 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
274 // The _ftol2 runtime function has an unusual calling conv, which
275 // is modeled by a special pseudo-instruction.
276 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
278 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
279 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
282 if (Subtarget->isTargetDarwin()) {
283 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
284 setUseUnderscoreSetJmp(false);
285 setUseUnderscoreLongJmp(false);
286 } else if (Subtarget->isTargetWindowsGNU()) {
287 // MS runtime is weird: it exports _setjmp, but longjmp!
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(false);
291 setUseUnderscoreSetJmp(true);
292 setUseUnderscoreLongJmp(true);
295 // Set up the register classes.
296 addRegisterClass(MVT::i8, &X86::GR8RegClass);
297 addRegisterClass(MVT::i16, &X86::GR16RegClass);
298 addRegisterClass(MVT::i32, &X86::GR32RegClass);
299 if (Subtarget->is64Bit())
300 addRegisterClass(MVT::i64, &X86::GR64RegClass);
302 for (MVT VT : MVT::integer_valuetypes())
303 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
305 // We don't accept any truncstore of integer registers.
306 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
307 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
308 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
309 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
310 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
311 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 // SETOEQ and SETUNE require checking two conditions.
316 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
319 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
320 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
321 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
323 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
325 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
329 if (Subtarget->is64Bit()) {
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 } else if (!TM.Options.UseSoftFloat) {
333 // We have an algorithm for SSE2->double, and we turn this into a
334 // 64-bit FILD followed by conditional FADD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 // We have an algorithm for SSE2, and we turn this into a 64-bit
337 // FILD for other targets.
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
341 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
343 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
346 if (!TM.Options.UseSoftFloat) {
347 // SSE has no i16 to fp conversion, only i32
348 if (X86ScalarSSEf32) {
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 // f32 and f64 cases are Legal, f80 case is not
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
361 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
362 // are Legal, f80 is custom lowered.
363 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
364 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
366 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
368 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
371 if (X86ScalarSSEf32) {
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
373 // f32 and f64 cases are Legal, f80 case is not
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 // Handle FP_TO_UINT by promoting the destination to a larger signed
382 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
386 if (Subtarget->is64Bit()) {
387 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
389 } else if (!TM.Options.UseSoftFloat) {
390 // Since AVX is a superset of SSE3, only check for SSE here.
391 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
392 // Expand FP_TO_UINT into a select.
393 // FIXME: We would like to use a Custom expander here eventually to do
394 // the optimal thing for SSE vs. the default expansion in the legalizer.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
397 // With SSE3 we can use fisttpll to convert to a signed i64; without
398 // SSE, we're stuck with a fistpll.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
402 if (isTargetFTOL()) {
403 // Use the _ftol2 runtime function, which has a pseudo-instruction
404 // to handle its weird calling convention.
405 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
408 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
409 if (!X86ScalarSSEf64) {
410 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
411 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
412 if (Subtarget->is64Bit()) {
413 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
414 // Without SSE, i64->f64 goes through memory.
415 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
419 // Scalar integer divide and remainder are lowered to use operations that
420 // produce two results, to match the available instructions. This exposes
421 // the two-result form to trivial CSE, which is able to combine x/y and x%y
422 // into a single instruction.
424 // Scalar integer multiply-high is also lowered to use two-result
425 // operations, to match the available instructions. However, plain multiply
426 // (low) operations are left as Legal, as there are single-result
427 // instructions for this in x86. Using the two-result multiply instructions
428 // when both high and low results are needed must be arranged by dagcombine.
429 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
431 setOperationAction(ISD::MULHS, VT, Expand);
432 setOperationAction(ISD::MULHU, VT, Expand);
433 setOperationAction(ISD::SDIV, VT, Expand);
434 setOperationAction(ISD::UDIV, VT, Expand);
435 setOperationAction(ISD::SREM, VT, Expand);
436 setOperationAction(ISD::UREM, VT, Expand);
438 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
439 setOperationAction(ISD::ADDC, VT, Custom);
440 setOperationAction(ISD::ADDE, VT, Custom);
441 setOperationAction(ISD::SUBC, VT, Custom);
442 setOperationAction(ISD::SUBE, VT, Custom);
445 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
446 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
447 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
449 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
451 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
452 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
453 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
463 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
466 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
467 setOperationAction(ISD::FREM , MVT::f32 , Expand);
468 setOperationAction(ISD::FREM , MVT::f64 , Expand);
469 setOperationAction(ISD::FREM , MVT::f80 , Expand);
470 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
472 // Promote the i8 variants and force them on up to i32 which has a shorter
474 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
478 if (Subtarget->hasBMI()) {
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
486 if (Subtarget->is64Bit())
487 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
490 if (Subtarget->hasLZCNT()) {
491 // When promoting the i8 variants, force them to i32 for a shorter
493 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
494 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
496 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
499 if (Subtarget->is64Bit())
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
502 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
508 if (Subtarget->is64Bit()) {
509 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
514 // Special handling for half-precision floating point conversions.
515 // If we don't have F16C support, then lower half float conversions
516 // into library calls.
517 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
518 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
519 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
522 // There's never any support for operations beyond MVT::f32.
523 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
524 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
525 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
526 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
528 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
529 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
530 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
531 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
532 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
535 if (Subtarget->hasPOPCNT()) {
536 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
538 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
539 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
540 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
541 if (Subtarget->is64Bit())
542 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
545 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
547 if (!Subtarget->hasMOVBE())
548 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
550 // These should be promoted to a larger select which is supported.
551 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
552 // X86 wants to expand cmov itself.
553 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
554 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
555 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
556 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
557 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
559 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
562 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
563 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
565 if (Subtarget->is64Bit()) {
566 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
569 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
570 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
571 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
572 // support continuation, user-level threading, and etc.. As a result, no
573 // other SjLj exception interfaces are implemented and please don't build
574 // your own exception handling based on them.
575 // LLVM/Clang supports zero-cost DWARF exception handling.
576 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
577 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
580 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
583 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
584 if (Subtarget->is64Bit())
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
586 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
588 if (Subtarget->is64Bit()) {
589 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
590 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
591 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
592 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
595 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
596 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
597 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
598 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
599 if (Subtarget->is64Bit()) {
600 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
601 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
602 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
605 if (Subtarget->hasSSE1())
606 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
608 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
610 // Expand certain atomics
611 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
614 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
615 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
618 if (Subtarget->hasCmpxchg16b()) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
622 // FIXME - use subtarget debug flags
623 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
624 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
625 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
628 if (Subtarget->is64Bit()) {
629 setExceptionPointerRegister(X86::RAX);
630 setExceptionSelectorRegister(X86::RDX);
632 setExceptionPointerRegister(X86::EAX);
633 setExceptionSelectorRegister(X86::EDX);
635 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
636 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
638 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
639 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::TRAP, MVT::Other, Legal);
642 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
644 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
645 setOperationAction(ISD::VASTART , MVT::Other, Custom);
646 setOperationAction(ISD::VAEND , MVT::Other, Expand);
647 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
648 // TargetInfo::X86_64ABIBuiltinVaList
649 setOperationAction(ISD::VAARG , MVT::Other, Custom);
650 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
652 // TargetInfo::CharPtrBuiltinVaList
653 setOperationAction(ISD::VAARG , MVT::Other, Expand);
654 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
657 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
658 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
660 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
662 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
663 // f32 and f64 use SSE.
664 // Set up the FP register classes.
665 addRegisterClass(MVT::f32, &X86::FR32RegClass);
666 addRegisterClass(MVT::f64, &X86::FR64RegClass);
668 // Use ANDPD to simulate FABS.
669 setOperationAction(ISD::FABS , MVT::f64, Custom);
670 setOperationAction(ISD::FABS , MVT::f32, Custom);
672 // Use XORP to simulate FNEG.
673 setOperationAction(ISD::FNEG , MVT::f64, Custom);
674 setOperationAction(ISD::FNEG , MVT::f32, Custom);
676 // Use ANDPD and ORPD to simulate FCOPYSIGN.
677 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
678 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
680 // Lower this to FGETSIGNx86 plus an AND.
681 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
682 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
684 // We don't support sin/cos/fmod
685 setOperationAction(ISD::FSIN , MVT::f64, Expand);
686 setOperationAction(ISD::FCOS , MVT::f64, Expand);
687 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
688 setOperationAction(ISD::FSIN , MVT::f32, Expand);
689 setOperationAction(ISD::FCOS , MVT::f32, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
692 // Expand FP immediates into loads from the stack, except for the special
694 addLegalFPImmediate(APFloat(+0.0)); // xorpd
695 addLegalFPImmediate(APFloat(+0.0f)); // xorps
696 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
697 // Use SSE for f32, x87 for f64.
698 // Set up the FP register classes.
699 addRegisterClass(MVT::f32, &X86::FR32RegClass);
700 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
702 // Use ANDPS to simulate FABS.
703 setOperationAction(ISD::FABS , MVT::f32, Custom);
705 // Use XORP to simulate FNEG.
706 setOperationAction(ISD::FNEG , MVT::f32, Custom);
708 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
710 // Use ANDPS and ORPS to simulate FCOPYSIGN.
711 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
712 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
714 // We don't support sin/cos/fmod
715 setOperationAction(ISD::FSIN , MVT::f32, Expand);
716 setOperationAction(ISD::FCOS , MVT::f32, Expand);
717 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
719 // Special cases we handle for FP constants.
720 addLegalFPImmediate(APFloat(+0.0f)); // xorps
721 addLegalFPImmediate(APFloat(+0.0)); // FLD0
722 addLegalFPImmediate(APFloat(+1.0)); // FLD1
723 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
724 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 } else if (!TM.Options.UseSoftFloat) {
732 // f32 and f64 in x87.
733 // Set up the FP register classes.
734 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
735 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
737 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
738 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
739 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
740 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
742 if (!TM.Options.UnsafeFPMath) {
743 setOperationAction(ISD::FSIN , MVT::f64, Expand);
744 setOperationAction(ISD::FSIN , MVT::f32, Expand);
745 setOperationAction(ISD::FCOS , MVT::f64, Expand);
746 setOperationAction(ISD::FCOS , MVT::f32, Expand);
747 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
748 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
750 addLegalFPImmediate(APFloat(+0.0)); // FLD0
751 addLegalFPImmediate(APFloat(+1.0)); // FLD1
752 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
753 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
754 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
755 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
756 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
757 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
760 // We don't support FMA.
761 setOperationAction(ISD::FMA, MVT::f64, Expand);
762 setOperationAction(ISD::FMA, MVT::f32, Expand);
764 // Long double always uses X87.
765 if (!TM.Options.UseSoftFloat) {
766 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
767 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
768 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
770 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
771 addLegalFPImmediate(TmpFlt); // FLD0
773 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
776 APFloat TmpFlt2(+1.0);
777 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
779 addLegalFPImmediate(TmpFlt2); // FLD1
780 TmpFlt2.changeSign();
781 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
784 if (!TM.Options.UnsafeFPMath) {
785 setOperationAction(ISD::FSIN , MVT::f80, Expand);
786 setOperationAction(ISD::FCOS , MVT::f80, Expand);
787 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
790 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
791 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
792 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
793 setOperationAction(ISD::FRINT, MVT::f80, Expand);
794 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
795 setOperationAction(ISD::FMA, MVT::f80, Expand);
798 // Always use a library call for pow.
799 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
800 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
801 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
803 setOperationAction(ISD::FLOG, MVT::f80, Expand);
804 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
805 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
806 setOperationAction(ISD::FEXP, MVT::f80, Expand);
807 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
808 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
809 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (MVT VT : MVT::vector_valuetypes()) {
815 setOperationAction(ISD::ADD , VT, Expand);
816 setOperationAction(ISD::SUB , VT, Expand);
817 setOperationAction(ISD::FADD, VT, Expand);
818 setOperationAction(ISD::FNEG, VT, Expand);
819 setOperationAction(ISD::FSUB, VT, Expand);
820 setOperationAction(ISD::MUL , VT, Expand);
821 setOperationAction(ISD::FMUL, VT, Expand);
822 setOperationAction(ISD::SDIV, VT, Expand);
823 setOperationAction(ISD::UDIV, VT, Expand);
824 setOperationAction(ISD::FDIV, VT, Expand);
825 setOperationAction(ISD::SREM, VT, Expand);
826 setOperationAction(ISD::UREM, VT, Expand);
827 setOperationAction(ISD::LOAD, VT, Expand);
828 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
830 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
831 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
832 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
833 setOperationAction(ISD::FABS, VT, Expand);
834 setOperationAction(ISD::FSIN, VT, Expand);
835 setOperationAction(ISD::FSINCOS, VT, Expand);
836 setOperationAction(ISD::FCOS, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FREM, VT, Expand);
839 setOperationAction(ISD::FMA, VT, Expand);
840 setOperationAction(ISD::FPOWI, VT, Expand);
841 setOperationAction(ISD::FSQRT, VT, Expand);
842 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
843 setOperationAction(ISD::FFLOOR, VT, Expand);
844 setOperationAction(ISD::FCEIL, VT, Expand);
845 setOperationAction(ISD::FTRUNC, VT, Expand);
846 setOperationAction(ISD::FRINT, VT, Expand);
847 setOperationAction(ISD::FNEARBYINT, VT, Expand);
848 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
849 setOperationAction(ISD::MULHS, VT, Expand);
850 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHU, VT, Expand);
852 setOperationAction(ISD::SDIVREM, VT, Expand);
853 setOperationAction(ISD::UDIVREM, VT, Expand);
854 setOperationAction(ISD::FPOW, VT, Expand);
855 setOperationAction(ISD::CTPOP, VT, Expand);
856 setOperationAction(ISD::CTTZ, VT, Expand);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
858 setOperationAction(ISD::CTLZ, VT, Expand);
859 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::SHL, VT, Expand);
861 setOperationAction(ISD::SRA, VT, Expand);
862 setOperationAction(ISD::SRL, VT, Expand);
863 setOperationAction(ISD::ROTL, VT, Expand);
864 setOperationAction(ISD::ROTR, VT, Expand);
865 setOperationAction(ISD::BSWAP, VT, Expand);
866 setOperationAction(ISD::SETCC, VT, Expand);
867 setOperationAction(ISD::FLOG, VT, Expand);
868 setOperationAction(ISD::FLOG2, VT, Expand);
869 setOperationAction(ISD::FLOG10, VT, Expand);
870 setOperationAction(ISD::FEXP, VT, Expand);
871 setOperationAction(ISD::FEXP2, VT, Expand);
872 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
873 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
874 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
875 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
876 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
877 setOperationAction(ISD::TRUNCATE, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
879 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
880 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
881 setOperationAction(ISD::VSELECT, VT, Expand);
882 setOperationAction(ISD::SELECT_CC, VT, Expand);
883 for (MVT InnerVT : MVT::vector_valuetypes()) {
884 setTruncStoreAction(InnerVT, VT, Expand);
886 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
887 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
889 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
890 // types, we have to deal with them whether we ask for Expansion or not.
891 // Setting Expand causes its own optimisation problems though, so leave
893 if (VT.getVectorElementType() == MVT::i1)
894 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
898 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
899 // with -msoft-float, disable use of MMX as well.
900 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
901 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
902 // No operations on x86mmx supported, everything uses intrinsics.
905 // MMX-sized vectors (other than x86mmx) are expected to be expanded
906 // into smaller operations.
907 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
908 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
909 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
910 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
911 setOperationAction(ISD::AND, MVT::v8i8, Expand);
912 setOperationAction(ISD::AND, MVT::v4i16, Expand);
913 setOperationAction(ISD::AND, MVT::v2i32, Expand);
914 setOperationAction(ISD::AND, MVT::v1i64, Expand);
915 setOperationAction(ISD::OR, MVT::v8i8, Expand);
916 setOperationAction(ISD::OR, MVT::v4i16, Expand);
917 setOperationAction(ISD::OR, MVT::v2i32, Expand);
918 setOperationAction(ISD::OR, MVT::v1i64, Expand);
919 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
927 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
928 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
929 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
930 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
931 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
932 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
937 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
938 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
940 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
941 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
942 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
943 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
944 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
945 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
946 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
947 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
948 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
949 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
951 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
952 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Only provide customized ctpop vector bit twiddling for vector types we
1000 // know to perform better than using the popcnt instructions on each vector
1001 // element. If popcnt isn't supported, always provide the custom version.
1002 if (!Subtarget->hasPOPCNT()) {
1003 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
1004 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
1007 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1008 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1009 MVT VT = (MVT::SimpleValueType)i;
1010 // Do not attempt to custom lower non-power-of-2 vectors
1011 if (!isPowerOf2_32(VT.getVectorNumElements()))
1013 // Do not attempt to custom lower non-128-bit vectors
1014 if (!VT.is128BitVector())
1016 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1017 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1021 // We support custom legalizing of sext and anyext loads for specific
1022 // memory vector types which we can load as a scalar (or sequence of
1023 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1024 // loads these must work with a single scalar load.
1025 for (MVT VT : MVT::integer_vector_valuetypes()) {
1026 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
1027 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
1028 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
1030 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1032 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1033 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1037 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1038 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1039 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1040 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1044 if (Subtarget->is64Bit()) {
1045 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1046 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1049 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1050 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1051 MVT VT = (MVT::SimpleValueType)i;
1053 // Do not attempt to promote non-128-bit vectors
1054 if (!VT.is128BitVector())
1057 setOperationAction(ISD::AND, VT, Promote);
1058 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1059 setOperationAction(ISD::OR, VT, Promote);
1060 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1061 setOperationAction(ISD::XOR, VT, Promote);
1062 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1063 setOperationAction(ISD::LOAD, VT, Promote);
1064 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1065 setOperationAction(ISD::SELECT, VT, Promote);
1066 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1069 // Custom lower v2i64 and v2f64 selects.
1070 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1071 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1072 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1073 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1075 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1076 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1078 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1079 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1080 // As there is no 64-bit GPR available, we need build a special custom
1081 // sequence to convert from v2i32 to v2f32.
1082 if (!Subtarget->is64Bit())
1083 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1085 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1086 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1088 for (MVT VT : MVT::fp_vector_valuetypes())
1089 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1091 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1092 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1093 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1096 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1097 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1100 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1102 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1103 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1104 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1105 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1106 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1108 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1109 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1110 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1111 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1112 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1113 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1114 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1115 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1116 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1119 // FIXME: Do we need to handle scalar-to-vector here?
1120 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1122 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1123 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1124 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1125 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1127 // There is no BLENDI for byte vectors. We don't need to custom lower
1128 // some vselects for now.
1129 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1131 // SSE41 brings specific instructions for doing vector sign extend even in
1132 // cases where we don't have SRA.
1133 for (MVT VT : MVT::integer_vector_valuetypes()) {
1134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1139 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
1140 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1141 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1142 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1143 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1144 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1145 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1147 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1148 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1149 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1150 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1151 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1152 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1154 // i8 and i16 vectors are custom because the source register and source
1155 // source memory operand types are not the same width. f32 vectors are
1156 // custom since the immediate controlling the insert encodes additional
1158 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1159 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1160 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1161 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1164 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1165 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1166 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1168 // FIXME: these should be Legal, but that's only for the case where
1169 // the index is constant. For now custom expand to deal with that.
1170 if (Subtarget->is64Bit()) {
1171 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1172 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1176 if (Subtarget->hasSSE2()) {
1177 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1178 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1180 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1181 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1183 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1184 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1186 // In the customized shift lowering, the legal cases in AVX2 will be
1188 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1189 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1191 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1192 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1194 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1197 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1198 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1199 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1200 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1201 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1202 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1203 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1205 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1206 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1207 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1209 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1210 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1211 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1212 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1213 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1214 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1215 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1216 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1217 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1218 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1219 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1220 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1222 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1223 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1224 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1225 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1226 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1227 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1228 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1229 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1230 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1231 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1232 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1233 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1235 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1236 // even though v8i16 is a legal type.
1237 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1238 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1239 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1241 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1242 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1243 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1245 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1246 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1248 for (MVT VT : MVT::fp_vector_valuetypes())
1249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1251 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1252 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1254 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1255 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1257 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1258 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1260 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1261 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1262 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1263 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1265 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1266 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1267 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1269 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1270 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1271 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1272 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1274 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1275 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1276 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1277 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1278 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1279 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1280 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1281 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1282 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1283 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1284 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1285 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1287 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1288 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1289 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1290 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1291 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1292 setOperationAction(ISD::FMA, MVT::f32, Legal);
1293 setOperationAction(ISD::FMA, MVT::f64, Legal);
1296 if (Subtarget->hasInt256()) {
1297 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1298 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1299 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1300 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1302 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1303 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1304 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1305 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1307 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1309 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1310 // Don't lower v32i8 because there is no 128-bit byte mul
1312 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1313 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1314 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1315 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1317 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1318 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1320 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1321 // when we have a 256bit-wide blend with immediate.
1322 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1324 // Only provide customized ctpop vector bit twiddling for vector types we
1325 // know to perform better than using the popcnt instructions on each
1326 // vector element. If popcnt isn't supported, always provide the custom
1328 if (!Subtarget->hasPOPCNT())
1329 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1331 // Custom CTPOP always performs better on natively supported v8i32
1332 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1334 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1335 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1336 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1337 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1338 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1339 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1340 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1342 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1343 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1344 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1345 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1346 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1347 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1349 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1350 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1351 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1352 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1354 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1355 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1356 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1357 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1359 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1360 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1361 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1362 // Don't lower v32i8 because there is no 128-bit byte mul
1365 // In the customized shift lowering, the legal cases in AVX2 will be
1367 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1368 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1370 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1371 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1373 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1375 // Custom lower several nodes for 256-bit types.
1376 for (MVT VT : MVT::vector_valuetypes()) {
1377 if (VT.getScalarSizeInBits() >= 32) {
1378 setOperationAction(ISD::MLOAD, VT, Legal);
1379 setOperationAction(ISD::MSTORE, VT, Legal);
1381 // Extract subvector is special because the value type
1382 // (result) is 128-bit but the source is 256-bit wide.
1383 if (VT.is128BitVector()) {
1384 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1386 // Do not attempt to custom lower other non-256-bit vectors
1387 if (!VT.is256BitVector())
1390 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1391 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1392 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1393 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1394 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1395 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1396 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1399 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1400 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1401 MVT VT = (MVT::SimpleValueType)i;
1403 // Do not attempt to promote non-256-bit vectors
1404 if (!VT.is256BitVector())
1407 setOperationAction(ISD::AND, VT, Promote);
1408 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1409 setOperationAction(ISD::OR, VT, Promote);
1410 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1411 setOperationAction(ISD::XOR, VT, Promote);
1412 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1413 setOperationAction(ISD::LOAD, VT, Promote);
1414 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1415 setOperationAction(ISD::SELECT, VT, Promote);
1416 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1420 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1421 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1422 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1423 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1424 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1426 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1427 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1428 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1430 for (MVT VT : MVT::fp_vector_valuetypes())
1431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1433 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1434 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1435 setOperationAction(ISD::XOR, MVT::i1, Legal);
1436 setOperationAction(ISD::OR, MVT::i1, Legal);
1437 setOperationAction(ISD::AND, MVT::i1, Legal);
1438 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1439 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1440 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1441 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1442 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1444 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1446 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1448 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1451 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1453 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1454 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1455 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1456 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1457 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1458 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1460 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1461 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1462 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1463 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1464 if (Subtarget->is64Bit()) {
1465 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1466 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1467 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1468 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1470 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1471 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1472 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1473 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1474 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1475 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1476 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1477 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1478 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1479 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1480 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1481 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1482 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1483 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1485 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1486 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1487 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1488 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1489 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1490 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1491 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1492 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1494 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1495 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1496 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1497 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1499 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1500 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1501 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1502 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1503 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1504 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1506 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1507 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1509 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1513 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1514 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1515 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1516 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1517 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1518 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1519 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1521 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1522 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1524 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1525 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1527 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1529 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1530 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1532 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1533 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1535 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1536 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1538 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1539 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1540 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1541 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1542 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1543 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1545 if (Subtarget->hasCDI()) {
1546 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1547 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1550 // Custom lower several nodes.
1551 for (MVT VT : MVT::vector_valuetypes()) {
1552 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1553 // Extract subvector is special because the value type
1554 // (result) is 256/128-bit but the source is 512-bit wide.
1555 if (VT.is128BitVector() || VT.is256BitVector()) {
1556 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1558 if (VT.getVectorElementType() == MVT::i1)
1559 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1561 // Do not attempt to custom lower other non-512-bit vectors
1562 if (!VT.is512BitVector())
1565 if ( EltSize >= 32) {
1566 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1567 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1568 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1569 setOperationAction(ISD::VSELECT, VT, Legal);
1570 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1571 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1572 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1573 setOperationAction(ISD::MLOAD, VT, Legal);
1574 setOperationAction(ISD::MSTORE, VT, Legal);
1577 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1578 MVT VT = (MVT::SimpleValueType)i;
1580 // Do not attempt to promote non-512-bit vectors.
1581 if (!VT.is512BitVector())
1584 setOperationAction(ISD::SELECT, VT, Promote);
1585 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1589 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1590 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1591 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1593 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1594 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1596 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1597 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1598 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1599 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1600 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1601 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1602 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1603 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1604 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1606 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1607 const MVT VT = (MVT::SimpleValueType)i;
1609 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1611 // Do not attempt to promote non-512-bit vectors.
1612 if (!VT.is512BitVector())
1616 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1617 setOperationAction(ISD::VSELECT, VT, Legal);
1622 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1623 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1624 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1626 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1627 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1628 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1630 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1631 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1632 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1633 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1634 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1635 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1638 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1639 // of this type with custom code.
1640 for (MVT VT : MVT::vector_valuetypes())
1641 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
1643 // We want to custom lower some of our intrinsics.
1644 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1645 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1646 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1647 if (!Subtarget->is64Bit())
1648 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1650 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1651 // handle type legalization for these operations here.
1653 // FIXME: We really should do custom legalization for addition and
1654 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1655 // than generic legalization for 64-bit multiplication-with-overflow, though.
1656 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1657 // Add/Sub/Mul with overflow operations are custom lowered.
1659 setOperationAction(ISD::SADDO, VT, Custom);
1660 setOperationAction(ISD::UADDO, VT, Custom);
1661 setOperationAction(ISD::SSUBO, VT, Custom);
1662 setOperationAction(ISD::USUBO, VT, Custom);
1663 setOperationAction(ISD::SMULO, VT, Custom);
1664 setOperationAction(ISD::UMULO, VT, Custom);
1668 if (!Subtarget->is64Bit()) {
1669 // These libcalls are not available in 32-bit.
1670 setLibcallName(RTLIB::SHL_I128, nullptr);
1671 setLibcallName(RTLIB::SRL_I128, nullptr);
1672 setLibcallName(RTLIB::SRA_I128, nullptr);
1675 // Combine sin / cos into one node or libcall if possible.
1676 if (Subtarget->hasSinCos()) {
1677 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1678 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1679 if (Subtarget->isTargetDarwin()) {
1680 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1681 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1682 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1683 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1687 if (Subtarget->isTargetWin64()) {
1688 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1689 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1690 setOperationAction(ISD::SREM, MVT::i128, Custom);
1691 setOperationAction(ISD::UREM, MVT::i128, Custom);
1692 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1693 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1696 // We have target-specific dag combine patterns for the following nodes:
1697 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1698 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1699 setTargetDAGCombine(ISD::VSELECT);
1700 setTargetDAGCombine(ISD::SELECT);
1701 setTargetDAGCombine(ISD::SHL);
1702 setTargetDAGCombine(ISD::SRA);
1703 setTargetDAGCombine(ISD::SRL);
1704 setTargetDAGCombine(ISD::OR);
1705 setTargetDAGCombine(ISD::AND);
1706 setTargetDAGCombine(ISD::ADD);
1707 setTargetDAGCombine(ISD::FADD);
1708 setTargetDAGCombine(ISD::FSUB);
1709 setTargetDAGCombine(ISD::FMA);
1710 setTargetDAGCombine(ISD::SUB);
1711 setTargetDAGCombine(ISD::LOAD);
1712 setTargetDAGCombine(ISD::MLOAD);
1713 setTargetDAGCombine(ISD::STORE);
1714 setTargetDAGCombine(ISD::MSTORE);
1715 setTargetDAGCombine(ISD::ZERO_EXTEND);
1716 setTargetDAGCombine(ISD::ANY_EXTEND);
1717 setTargetDAGCombine(ISD::SIGN_EXTEND);
1718 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1719 setTargetDAGCombine(ISD::TRUNCATE);
1720 setTargetDAGCombine(ISD::SINT_TO_FP);
1721 setTargetDAGCombine(ISD::SETCC);
1722 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1723 setTargetDAGCombine(ISD::BUILD_VECTOR);
1724 if (Subtarget->is64Bit())
1725 setTargetDAGCombine(ISD::MUL);
1726 setTargetDAGCombine(ISD::XOR);
1728 computeRegisterProperties();
1730 // On Darwin, -Os means optimize for size without hurting performance,
1731 // do not reduce the limit.
1732 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1733 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1734 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1735 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1736 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1737 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1738 setPrefLoopAlignment(4); // 2^4 bytes.
1740 // Predictable cmov don't hurt on atom because it's in-order.
1741 PredictableSelectIsExpensive = !Subtarget->isAtom();
1742 EnableExtLdPromotion = true;
1743 setPrefFunctionAlignment(4); // 2^4 bytes.
1745 verifyIntrinsicTables();
1748 // This has so far only been implemented for 64-bit MachO.
1749 bool X86TargetLowering::useLoadStackGuardNode() const {
1750 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1753 TargetLoweringBase::LegalizeTypeAction
1754 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1755 if (ExperimentalVectorWideningLegalization &&
1756 VT.getVectorNumElements() != 1 &&
1757 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1758 return TypeWidenVector;
1760 return TargetLoweringBase::getPreferredVectorAction(VT);
1763 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1765 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1767 const unsigned NumElts = VT.getVectorNumElements();
1768 const EVT EltVT = VT.getVectorElementType();
1769 if (VT.is512BitVector()) {
1770 if (Subtarget->hasAVX512())
1771 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1772 EltVT == MVT::f32 || EltVT == MVT::f64)
1774 case 8: return MVT::v8i1;
1775 case 16: return MVT::v16i1;
1777 if (Subtarget->hasBWI())
1778 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1780 case 32: return MVT::v32i1;
1781 case 64: return MVT::v64i1;
1785 if (VT.is256BitVector() || VT.is128BitVector()) {
1786 if (Subtarget->hasVLX())
1787 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1788 EltVT == MVT::f32 || EltVT == MVT::f64)
1790 case 2: return MVT::v2i1;
1791 case 4: return MVT::v4i1;
1792 case 8: return MVT::v8i1;
1794 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1795 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1797 case 8: return MVT::v8i1;
1798 case 16: return MVT::v16i1;
1799 case 32: return MVT::v32i1;
1803 return VT.changeVectorElementTypeToInteger();
1806 /// Helper for getByValTypeAlignment to determine
1807 /// the desired ByVal argument alignment.
1808 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1811 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1812 if (VTy->getBitWidth() == 128)
1814 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1815 unsigned EltAlign = 0;
1816 getMaxByValAlign(ATy->getElementType(), EltAlign);
1817 if (EltAlign > MaxAlign)
1818 MaxAlign = EltAlign;
1819 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1820 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1821 unsigned EltAlign = 0;
1822 getMaxByValAlign(STy->getElementType(i), EltAlign);
1823 if (EltAlign > MaxAlign)
1824 MaxAlign = EltAlign;
1831 /// Return the desired alignment for ByVal aggregate
1832 /// function arguments in the caller parameter area. For X86, aggregates
1833 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1834 /// are at 4-byte boundaries.
1835 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1836 if (Subtarget->is64Bit()) {
1837 // Max of 8 and alignment of type.
1838 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1845 if (Subtarget->hasSSE1())
1846 getMaxByValAlign(Ty, Align);
1850 /// Returns the target specific optimal type for load
1851 /// and store operations as a result of memset, memcpy, and memmove
1852 /// lowering. If DstAlign is zero that means it's safe to destination
1853 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1854 /// means there isn't a need to check it against alignment requirement,
1855 /// probably because the source does not need to be loaded. If 'IsMemset' is
1856 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1857 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1858 /// source is constant so it does not need to be loaded.
1859 /// It returns EVT::Other if the type should be determined using generic
1860 /// target-independent logic.
1862 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1863 unsigned DstAlign, unsigned SrcAlign,
1864 bool IsMemset, bool ZeroMemset,
1866 MachineFunction &MF) const {
1867 const Function *F = MF.getFunction();
1868 if ((!IsMemset || ZeroMemset) &&
1869 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1870 Attribute::NoImplicitFloat)) {
1872 (Subtarget->isUnalignedMemAccessFast() ||
1873 ((DstAlign == 0 || DstAlign >= 16) &&
1874 (SrcAlign == 0 || SrcAlign >= 16)))) {
1876 if (Subtarget->hasInt256())
1878 if (Subtarget->hasFp256())
1881 if (Subtarget->hasSSE2())
1883 if (Subtarget->hasSSE1())
1885 } else if (!MemcpyStrSrc && Size >= 8 &&
1886 !Subtarget->is64Bit() &&
1887 Subtarget->hasSSE2()) {
1888 // Do not use f64 to lower memcpy if source is string constant. It's
1889 // better to use i32 to avoid the loads.
1893 if (Subtarget->is64Bit() && Size >= 8)
1898 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1900 return X86ScalarSSEf32;
1901 else if (VT == MVT::f64)
1902 return X86ScalarSSEf64;
1907 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1912 *Fast = Subtarget->isUnalignedMemAccessFast();
1916 /// Return the entry encoding for a jump table in the
1917 /// current function. The returned value is a member of the
1918 /// MachineJumpTableInfo::JTEntryKind enum.
1919 unsigned X86TargetLowering::getJumpTableEncoding() const {
1920 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1922 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1923 Subtarget->isPICStyleGOT())
1924 return MachineJumpTableInfo::EK_Custom32;
1926 // Otherwise, use the normal jump table encoding heuristics.
1927 return TargetLowering::getJumpTableEncoding();
1931 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1932 const MachineBasicBlock *MBB,
1933 unsigned uid,MCContext &Ctx) const{
1934 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1935 Subtarget->isPICStyleGOT());
1936 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1938 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1939 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1942 /// Returns relocation base for the given PIC jumptable.
1943 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1944 SelectionDAG &DAG) const {
1945 if (!Subtarget->is64Bit())
1946 // This doesn't have SDLoc associated with it, but is not really the
1947 // same as a Register.
1948 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1952 /// This returns the relocation base for the given PIC jumptable,
1953 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1954 const MCExpr *X86TargetLowering::
1955 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1956 MCContext &Ctx) const {
1957 // X86-64 uses RIP relative addressing based on the jump table label.
1958 if (Subtarget->isPICStyleRIPRel())
1959 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1961 // Otherwise, the reference is relative to the PIC base.
1962 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1965 // FIXME: Why this routine is here? Move to RegInfo!
1966 std::pair<const TargetRegisterClass*, uint8_t>
1967 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1968 const TargetRegisterClass *RRC = nullptr;
1970 switch (VT.SimpleTy) {
1972 return TargetLowering::findRepresentativeClass(VT);
1973 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1974 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1977 RRC = &X86::VR64RegClass;
1979 case MVT::f32: case MVT::f64:
1980 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1981 case MVT::v4f32: case MVT::v2f64:
1982 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1984 RRC = &X86::VR128RegClass;
1987 return std::make_pair(RRC, Cost);
1990 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1991 unsigned &Offset) const {
1992 if (!Subtarget->isTargetLinux())
1995 if (Subtarget->is64Bit()) {
1996 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1998 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2010 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2011 unsigned DestAS) const {
2012 assert(SrcAS != DestAS && "Expected different address spaces!");
2014 return SrcAS < 256 && DestAS < 256;
2017 //===----------------------------------------------------------------------===//
2018 // Return Value Calling Convention Implementation
2019 //===----------------------------------------------------------------------===//
2021 #include "X86GenCallingConv.inc"
2024 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2025 MachineFunction &MF, bool isVarArg,
2026 const SmallVectorImpl<ISD::OutputArg> &Outs,
2027 LLVMContext &Context) const {
2028 SmallVector<CCValAssign, 16> RVLocs;
2029 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2030 return CCInfo.CheckReturn(Outs, RetCC_X86);
2033 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2034 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2039 X86TargetLowering::LowerReturn(SDValue Chain,
2040 CallingConv::ID CallConv, bool isVarArg,
2041 const SmallVectorImpl<ISD::OutputArg> &Outs,
2042 const SmallVectorImpl<SDValue> &OutVals,
2043 SDLoc dl, SelectionDAG &DAG) const {
2044 MachineFunction &MF = DAG.getMachineFunction();
2045 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2047 SmallVector<CCValAssign, 16> RVLocs;
2048 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2049 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2052 SmallVector<SDValue, 6> RetOps;
2053 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2054 // Operand #1 = Bytes To Pop
2055 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2058 // Copy the result values into the output registers.
2059 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2060 CCValAssign &VA = RVLocs[i];
2061 assert(VA.isRegLoc() && "Can only return in registers!");
2062 SDValue ValToCopy = OutVals[i];
2063 EVT ValVT = ValToCopy.getValueType();
2065 // Promote values to the appropriate types.
2066 if (VA.getLocInfo() == CCValAssign::SExt)
2067 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2068 else if (VA.getLocInfo() == CCValAssign::ZExt)
2069 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2070 else if (VA.getLocInfo() == CCValAssign::AExt)
2071 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2072 else if (VA.getLocInfo() == CCValAssign::BCvt)
2073 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2075 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2076 "Unexpected FP-extend for return value.");
2078 // If this is x86-64, and we disabled SSE, we can't return FP values,
2079 // or SSE or MMX vectors.
2080 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2081 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2082 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2083 report_fatal_error("SSE register return with SSE disabled");
2085 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2086 // llvm-gcc has never done it right and no one has noticed, so this
2087 // should be OK for now.
2088 if (ValVT == MVT::f64 &&
2089 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2090 report_fatal_error("SSE2 register return with SSE2 disabled");
2092 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2093 // the RET instruction and handled by the FP Stackifier.
2094 if (VA.getLocReg() == X86::FP0 ||
2095 VA.getLocReg() == X86::FP1) {
2096 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2097 // change the value to the FP stack register class.
2098 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2099 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2100 RetOps.push_back(ValToCopy);
2101 // Don't emit a copytoreg.
2105 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2106 // which is returned in RAX / RDX.
2107 if (Subtarget->is64Bit()) {
2108 if (ValVT == MVT::x86mmx) {
2109 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2110 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2111 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2113 // If we don't have SSE2 available, convert to v4f32 so the generated
2114 // register is legal.
2115 if (!Subtarget->hasSSE2())
2116 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2121 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2122 Flag = Chain.getValue(1);
2123 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2126 // The x86-64 ABIs require that for returning structs by value we copy
2127 // the sret argument into %rax/%eax (depending on ABI) for the return.
2128 // Win32 requires us to put the sret argument to %eax as well.
2129 // We saved the argument into a virtual register in the entry block,
2130 // so now we copy the value out and into %rax/%eax.
2131 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2132 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2133 MachineFunction &MF = DAG.getMachineFunction();
2134 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2135 unsigned Reg = FuncInfo->getSRetReturnReg();
2137 "SRetReturnReg should have been set in LowerFormalArguments().");
2138 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2141 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2142 X86::RAX : X86::EAX;
2143 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2144 Flag = Chain.getValue(1);
2146 // RAX/EAX now acts like a return value.
2147 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2150 RetOps[0] = Chain; // Update chain.
2152 // Add the flag if we have it.
2154 RetOps.push_back(Flag);
2156 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2159 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2160 if (N->getNumValues() != 1)
2162 if (!N->hasNUsesOfValue(1, 0))
2165 SDValue TCChain = Chain;
2166 SDNode *Copy = *N->use_begin();
2167 if (Copy->getOpcode() == ISD::CopyToReg) {
2168 // If the copy has a glue operand, we conservatively assume it isn't safe to
2169 // perform a tail call.
2170 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2172 TCChain = Copy->getOperand(0);
2173 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2176 bool HasRet = false;
2177 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2179 if (UI->getOpcode() != X86ISD::RET_FLAG)
2181 // If we are returning more than one value, we can definitely
2182 // not make a tail call see PR19530
2183 if (UI->getNumOperands() > 4)
2185 if (UI->getNumOperands() == 4 &&
2186 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2199 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2200 ISD::NodeType ExtendKind) const {
2202 // TODO: Is this also valid on 32-bit?
2203 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2204 ReturnMVT = MVT::i8;
2206 ReturnMVT = MVT::i32;
2208 EVT MinVT = getRegisterType(Context, ReturnMVT);
2209 return VT.bitsLT(MinVT) ? MinVT : VT;
2212 /// Lower the result values of a call into the
2213 /// appropriate copies out of appropriate physical registers.
2216 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2217 CallingConv::ID CallConv, bool isVarArg,
2218 const SmallVectorImpl<ISD::InputArg> &Ins,
2219 SDLoc dl, SelectionDAG &DAG,
2220 SmallVectorImpl<SDValue> &InVals) const {
2222 // Assign locations to each value returned by this call.
2223 SmallVector<CCValAssign, 16> RVLocs;
2224 bool Is64Bit = Subtarget->is64Bit();
2225 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2227 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2229 // Copy all of the result registers out of their specified physreg.
2230 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2231 CCValAssign &VA = RVLocs[i];
2232 EVT CopyVT = VA.getValVT();
2234 // If this is x86-64, and we disabled SSE, we can't return FP values
2235 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2236 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2237 report_fatal_error("SSE register return with SSE disabled");
2240 // If we prefer to use the value in xmm registers, copy it out as f80 and
2241 // use a truncate to move it from fp stack reg to xmm reg.
2242 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2243 isScalarFPTypeInSSEReg(VA.getValVT()))
2246 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2247 CopyVT, InFlag).getValue(1);
2248 SDValue Val = Chain.getValue(0);
2250 if (CopyVT != VA.getValVT())
2251 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2252 // This truncation won't change the value.
2253 DAG.getIntPtrConstant(1));
2255 InFlag = Chain.getValue(2);
2256 InVals.push_back(Val);
2262 //===----------------------------------------------------------------------===//
2263 // C & StdCall & Fast Calling Convention implementation
2264 //===----------------------------------------------------------------------===//
2265 // StdCall calling convention seems to be standard for many Windows' API
2266 // routines and around. It differs from C calling convention just a little:
2267 // callee should clean up the stack, not caller. Symbols should be also
2268 // decorated in some fancy way :) It doesn't support any vector arguments.
2269 // For info on fast calling convention see Fast Calling Convention (tail call)
2270 // implementation LowerX86_32FastCCCallTo.
2272 /// CallIsStructReturn - Determines whether a call uses struct return
2274 enum StructReturnType {
2279 static StructReturnType
2280 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2282 return NotStructReturn;
2284 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2285 if (!Flags.isSRet())
2286 return NotStructReturn;
2287 if (Flags.isInReg())
2288 return RegStructReturn;
2289 return StackStructReturn;
2292 /// Determines whether a function uses struct return semantics.
2293 static StructReturnType
2294 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2296 return NotStructReturn;
2298 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2299 if (!Flags.isSRet())
2300 return NotStructReturn;
2301 if (Flags.isInReg())
2302 return RegStructReturn;
2303 return StackStructReturn;
2306 /// Make a copy of an aggregate at address specified by "Src" to address
2307 /// "Dst" with size and alignment information specified by the specific
2308 /// parameter attribute. The copy will be passed as a byval function parameter.
2310 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2311 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2313 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2315 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2316 /*isVolatile*/false, /*AlwaysInline=*/true,
2317 MachinePointerInfo(), MachinePointerInfo());
2320 /// Return true if the calling convention is one that
2321 /// supports tail call optimization.
2322 static bool IsTailCallConvention(CallingConv::ID CC) {
2323 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2324 CC == CallingConv::HiPE);
2327 /// \brief Return true if the calling convention is a C calling convention.
2328 static bool IsCCallConvention(CallingConv::ID CC) {
2329 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2330 CC == CallingConv::X86_64_SysV);
2333 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2334 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2338 CallingConv::ID CalleeCC = CS.getCallingConv();
2339 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2345 /// Return true if the function is being made into
2346 /// a tailcall target by changing its ABI.
2347 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2348 bool GuaranteedTailCallOpt) {
2349 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2353 X86TargetLowering::LowerMemArgument(SDValue Chain,
2354 CallingConv::ID CallConv,
2355 const SmallVectorImpl<ISD::InputArg> &Ins,
2356 SDLoc dl, SelectionDAG &DAG,
2357 const CCValAssign &VA,
2358 MachineFrameInfo *MFI,
2360 // Create the nodes corresponding to a load from this parameter slot.
2361 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2362 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2363 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2364 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2367 // If value is passed by pointer we have address passed instead of the value
2369 if (VA.getLocInfo() == CCValAssign::Indirect)
2370 ValVT = VA.getLocVT();
2372 ValVT = VA.getValVT();
2374 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2375 // changed with more analysis.
2376 // In case of tail call optimization mark all arguments mutable. Since they
2377 // could be overwritten by lowering of arguments in case of a tail call.
2378 if (Flags.isByVal()) {
2379 unsigned Bytes = Flags.getByValSize();
2380 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2381 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2382 return DAG.getFrameIndex(FI, getPointerTy());
2384 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2385 VA.getLocMemOffset(), isImmutable);
2386 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2387 return DAG.getLoad(ValVT, dl, Chain, FIN,
2388 MachinePointerInfo::getFixedStack(FI),
2389 false, false, false, 0);
2393 // FIXME: Get this from tablegen.
2394 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2395 const X86Subtarget *Subtarget) {
2396 assert(Subtarget->is64Bit());
2398 if (Subtarget->isCallingConvWin64(CallConv)) {
2399 static const MCPhysReg GPR64ArgRegsWin64[] = {
2400 X86::RCX, X86::RDX, X86::R8, X86::R9
2402 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2405 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2406 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2408 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2411 // FIXME: Get this from tablegen.
2412 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2413 CallingConv::ID CallConv,
2414 const X86Subtarget *Subtarget) {
2415 assert(Subtarget->is64Bit());
2416 if (Subtarget->isCallingConvWin64(CallConv)) {
2417 // The XMM registers which might contain var arg parameters are shadowed
2418 // in their paired GPR. So we only need to save the GPR to their home
2420 // TODO: __vectorcall will change this.
2424 const Function *Fn = MF.getFunction();
2425 bool NoImplicitFloatOps = Fn->getAttributes().
2426 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2427 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2428 "SSE register cannot be used when SSE is disabled!");
2429 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2430 !Subtarget->hasSSE1())
2431 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2435 static const MCPhysReg XMMArgRegs64Bit[] = {
2436 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2437 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2439 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2443 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2444 CallingConv::ID CallConv,
2446 const SmallVectorImpl<ISD::InputArg> &Ins,
2449 SmallVectorImpl<SDValue> &InVals)
2451 MachineFunction &MF = DAG.getMachineFunction();
2452 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2454 const Function* Fn = MF.getFunction();
2455 if (Fn->hasExternalLinkage() &&
2456 Subtarget->isTargetCygMing() &&
2457 Fn->getName() == "main")
2458 FuncInfo->setForceFramePointer(true);
2460 MachineFrameInfo *MFI = MF.getFrameInfo();
2461 bool Is64Bit = Subtarget->is64Bit();
2462 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2464 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2465 "Var args not supported with calling convention fastcc, ghc or hipe");
2467 // Assign locations to all of the incoming arguments.
2468 SmallVector<CCValAssign, 16> ArgLocs;
2469 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2471 // Allocate shadow area for Win64
2473 CCInfo.AllocateStack(32, 8);
2475 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2477 unsigned LastVal = ~0U;
2479 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2480 CCValAssign &VA = ArgLocs[i];
2481 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2483 assert(VA.getValNo() != LastVal &&
2484 "Don't support value assigned to multiple locs yet");
2486 LastVal = VA.getValNo();
2488 if (VA.isRegLoc()) {
2489 EVT RegVT = VA.getLocVT();
2490 const TargetRegisterClass *RC;
2491 if (RegVT == MVT::i32)
2492 RC = &X86::GR32RegClass;
2493 else if (Is64Bit && RegVT == MVT::i64)
2494 RC = &X86::GR64RegClass;
2495 else if (RegVT == MVT::f32)
2496 RC = &X86::FR32RegClass;
2497 else if (RegVT == MVT::f64)
2498 RC = &X86::FR64RegClass;
2499 else if (RegVT.is512BitVector())
2500 RC = &X86::VR512RegClass;
2501 else if (RegVT.is256BitVector())
2502 RC = &X86::VR256RegClass;
2503 else if (RegVT.is128BitVector())
2504 RC = &X86::VR128RegClass;
2505 else if (RegVT == MVT::x86mmx)
2506 RC = &X86::VR64RegClass;
2507 else if (RegVT == MVT::i1)
2508 RC = &X86::VK1RegClass;
2509 else if (RegVT == MVT::v8i1)
2510 RC = &X86::VK8RegClass;
2511 else if (RegVT == MVT::v16i1)
2512 RC = &X86::VK16RegClass;
2513 else if (RegVT == MVT::v32i1)
2514 RC = &X86::VK32RegClass;
2515 else if (RegVT == MVT::v64i1)
2516 RC = &X86::VK64RegClass;
2518 llvm_unreachable("Unknown argument type!");
2520 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2521 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2523 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2524 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2526 if (VA.getLocInfo() == CCValAssign::SExt)
2527 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2528 DAG.getValueType(VA.getValVT()));
2529 else if (VA.getLocInfo() == CCValAssign::ZExt)
2530 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2531 DAG.getValueType(VA.getValVT()));
2532 else if (VA.getLocInfo() == CCValAssign::BCvt)
2533 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2535 if (VA.isExtInLoc()) {
2536 // Handle MMX values passed in XMM regs.
2537 if (RegVT.isVector())
2538 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2540 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2543 assert(VA.isMemLoc());
2544 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2547 // If value is passed via pointer - do a load.
2548 if (VA.getLocInfo() == CCValAssign::Indirect)
2549 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2550 MachinePointerInfo(), false, false, false, 0);
2552 InVals.push_back(ArgValue);
2555 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2556 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2557 // The x86-64 ABIs require that for returning structs by value we copy
2558 // the sret argument into %rax/%eax (depending on ABI) for the return.
2559 // Win32 requires us to put the sret argument to %eax as well.
2560 // Save the argument into a virtual register so that we can access it
2561 // from the return points.
2562 if (Ins[i].Flags.isSRet()) {
2563 unsigned Reg = FuncInfo->getSRetReturnReg();
2565 MVT PtrTy = getPointerTy();
2566 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2567 FuncInfo->setSRetReturnReg(Reg);
2569 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2570 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2576 unsigned StackSize = CCInfo.getNextStackOffset();
2577 // Align stack specially for tail calls.
2578 if (FuncIsMadeTailCallSafe(CallConv,
2579 MF.getTarget().Options.GuaranteedTailCallOpt))
2580 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2582 // If the function takes variable number of arguments, make a frame index for
2583 // the start of the first vararg value... for expansion of llvm.va_start. We
2584 // can skip this if there are no va_start calls.
2585 if (MFI->hasVAStart() &&
2586 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2587 CallConv != CallingConv::X86_ThisCall))) {
2588 FuncInfo->setVarArgsFrameIndex(
2589 MFI->CreateFixedObject(1, StackSize, true));
2592 // Figure out if XMM registers are in use.
2593 assert(!(MF.getTarget().Options.UseSoftFloat &&
2594 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2595 Attribute::NoImplicitFloat)) &&
2596 "SSE register cannot be used when SSE is disabled!");
2598 // 64-bit calling conventions support varargs and register parameters, so we
2599 // have to do extra work to spill them in the prologue.
2600 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2601 // Find the first unallocated argument registers.
2602 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2603 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2604 unsigned NumIntRegs =
2605 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2606 unsigned NumXMMRegs =
2607 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2608 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2609 "SSE register cannot be used when SSE is disabled!");
2611 // Gather all the live in physical registers.
2612 SmallVector<SDValue, 6> LiveGPRs;
2613 SmallVector<SDValue, 8> LiveXMMRegs;
2615 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2616 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2618 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2620 if (!ArgXMMs.empty()) {
2621 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2622 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2623 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2624 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2625 LiveXMMRegs.push_back(
2626 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2631 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2632 // Get to the caller-allocated home save location. Add 8 to account
2633 // for the return address.
2634 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2635 FuncInfo->setRegSaveFrameIndex(
2636 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2637 // Fixup to set vararg frame on shadow area (4 x i64).
2639 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2641 // For X86-64, if there are vararg parameters that are passed via
2642 // registers, then we must store them to their spots on the stack so
2643 // they may be loaded by deferencing the result of va_next.
2644 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2645 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2646 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2647 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2650 // Store the integer parameter registers.
2651 SmallVector<SDValue, 8> MemOps;
2652 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2654 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2655 for (SDValue Val : LiveGPRs) {
2656 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2657 DAG.getIntPtrConstant(Offset));
2659 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2660 MachinePointerInfo::getFixedStack(
2661 FuncInfo->getRegSaveFrameIndex(), Offset),
2663 MemOps.push_back(Store);
2667 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2668 // Now store the XMM (fp + vector) parameter registers.
2669 SmallVector<SDValue, 12> SaveXMMOps;
2670 SaveXMMOps.push_back(Chain);
2671 SaveXMMOps.push_back(ALVal);
2672 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2673 FuncInfo->getRegSaveFrameIndex()));
2674 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2675 FuncInfo->getVarArgsFPOffset()));
2676 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2678 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2679 MVT::Other, SaveXMMOps));
2682 if (!MemOps.empty())
2683 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2686 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2687 // Find the largest legal vector type.
2688 MVT VecVT = MVT::Other;
2689 // FIXME: Only some x86_32 calling conventions support AVX512.
2690 if (Subtarget->hasAVX512() &&
2691 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2692 CallConv == CallingConv::Intel_OCL_BI)))
2693 VecVT = MVT::v16f32;
2694 else if (Subtarget->hasAVX())
2696 else if (Subtarget->hasSSE2())
2699 // We forward some GPRs and some vector types.
2700 SmallVector<MVT, 2> RegParmTypes;
2701 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2702 RegParmTypes.push_back(IntVT);
2703 if (VecVT != MVT::Other)
2704 RegParmTypes.push_back(VecVT);
2706 // Compute the set of forwarded registers. The rest are scratch.
2707 SmallVectorImpl<ForwardedRegister> &Forwards =
2708 FuncInfo->getForwardedMustTailRegParms();
2709 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2711 // Conservatively forward AL on x86_64, since it might be used for varargs.
2712 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2713 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2714 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2717 // Copy all forwards from physical to virtual registers.
2718 for (ForwardedRegister &F : Forwards) {
2719 // FIXME: Can we use a less constrained schedule?
2720 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2721 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2722 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2726 // Some CCs need callee pop.
2727 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2728 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2729 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2731 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2732 // If this is an sret function, the return should pop the hidden pointer.
2733 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2734 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2735 argsAreStructReturn(Ins) == StackStructReturn)
2736 FuncInfo->setBytesToPopOnReturn(4);
2740 // RegSaveFrameIndex is X86-64 only.
2741 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2742 if (CallConv == CallingConv::X86_FastCall ||
2743 CallConv == CallingConv::X86_ThisCall)
2744 // fastcc functions can't have varargs.
2745 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2748 FuncInfo->setArgumentStackSize(StackSize);
2754 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2755 SDValue StackPtr, SDValue Arg,
2756 SDLoc dl, SelectionDAG &DAG,
2757 const CCValAssign &VA,
2758 ISD::ArgFlagsTy Flags) const {
2759 unsigned LocMemOffset = VA.getLocMemOffset();
2760 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2761 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2762 if (Flags.isByVal())
2763 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2765 return DAG.getStore(Chain, dl, Arg, PtrOff,
2766 MachinePointerInfo::getStack(LocMemOffset),
2770 /// Emit a load of return address if tail call
2771 /// optimization is performed and it is required.
2773 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2774 SDValue &OutRetAddr, SDValue Chain,
2775 bool IsTailCall, bool Is64Bit,
2776 int FPDiff, SDLoc dl) const {
2777 // Adjust the Return address stack slot.
2778 EVT VT = getPointerTy();
2779 OutRetAddr = getReturnAddressFrameIndex(DAG);
2781 // Load the "old" Return address.
2782 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2783 false, false, false, 0);
2784 return SDValue(OutRetAddr.getNode(), 1);
2787 /// Emit a store of the return address if tail call
2788 /// optimization is performed and it is required (FPDiff!=0).
2789 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2790 SDValue Chain, SDValue RetAddrFrIdx,
2791 EVT PtrVT, unsigned SlotSize,
2792 int FPDiff, SDLoc dl) {
2793 // Store the return address to the appropriate stack slot.
2794 if (!FPDiff) return Chain;
2795 // Calculate the new stack slot for the return address.
2796 int NewReturnAddrFI =
2797 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2799 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2800 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2801 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2807 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2808 SmallVectorImpl<SDValue> &InVals) const {
2809 SelectionDAG &DAG = CLI.DAG;
2811 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2812 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2813 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2814 SDValue Chain = CLI.Chain;
2815 SDValue Callee = CLI.Callee;
2816 CallingConv::ID CallConv = CLI.CallConv;
2817 bool &isTailCall = CLI.IsTailCall;
2818 bool isVarArg = CLI.IsVarArg;
2820 MachineFunction &MF = DAG.getMachineFunction();
2821 bool Is64Bit = Subtarget->is64Bit();
2822 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2823 StructReturnType SR = callIsStructReturn(Outs);
2824 bool IsSibcall = false;
2825 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2827 if (MF.getTarget().Options.DisableTailCalls)
2830 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2832 // Force this to be a tail call. The verifier rules are enough to ensure
2833 // that we can lower this successfully without moving the return address
2836 } else if (isTailCall) {
2837 // Check if it's really possible to do a tail call.
2838 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2839 isVarArg, SR != NotStructReturn,
2840 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2841 Outs, OutVals, Ins, DAG);
2843 // Sibcalls are automatically detected tailcalls which do not require
2845 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2852 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2853 "Var args not supported with calling convention fastcc, ghc or hipe");
2855 // Analyze operands of the call, assigning locations to each operand.
2856 SmallVector<CCValAssign, 16> ArgLocs;
2857 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2859 // Allocate shadow area for Win64
2861 CCInfo.AllocateStack(32, 8);
2863 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2865 // Get a count of how many bytes are to be pushed on the stack.
2866 unsigned NumBytes = CCInfo.getNextStackOffset();
2868 // This is a sibcall. The memory operands are available in caller's
2869 // own caller's stack.
2871 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2872 IsTailCallConvention(CallConv))
2873 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2876 if (isTailCall && !IsSibcall && !IsMustTail) {
2877 // Lower arguments at fp - stackoffset + fpdiff.
2878 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2880 FPDiff = NumBytesCallerPushed - NumBytes;
2882 // Set the delta of movement of the returnaddr stackslot.
2883 // But only set if delta is greater than previous delta.
2884 if (FPDiff < X86Info->getTCReturnAddrDelta())
2885 X86Info->setTCReturnAddrDelta(FPDiff);
2888 unsigned NumBytesToPush = NumBytes;
2889 unsigned NumBytesToPop = NumBytes;
2891 // If we have an inalloca argument, all stack space has already been allocated
2892 // for us and be right at the top of the stack. We don't support multiple
2893 // arguments passed in memory when using inalloca.
2894 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2896 if (!ArgLocs.back().isMemLoc())
2897 report_fatal_error("cannot use inalloca attribute on a register "
2899 if (ArgLocs.back().getLocMemOffset() != 0)
2900 report_fatal_error("any parameter with the inalloca attribute must be "
2901 "the only memory argument");
2905 Chain = DAG.getCALLSEQ_START(
2906 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2908 SDValue RetAddrFrIdx;
2909 // Load return address for tail calls.
2910 if (isTailCall && FPDiff)
2911 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2912 Is64Bit, FPDiff, dl);
2914 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2915 SmallVector<SDValue, 8> MemOpChains;
2918 // Walk the register/memloc assignments, inserting copies/loads. In the case
2919 // of tail call optimization arguments are handle later.
2920 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2921 DAG.getSubtarget().getRegisterInfo());
2922 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2923 // Skip inalloca arguments, they have already been written.
2924 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2925 if (Flags.isInAlloca())
2928 CCValAssign &VA = ArgLocs[i];
2929 EVT RegVT = VA.getLocVT();
2930 SDValue Arg = OutVals[i];
2931 bool isByVal = Flags.isByVal();
2933 // Promote the value if needed.
2934 switch (VA.getLocInfo()) {
2935 default: llvm_unreachable("Unknown loc info!");
2936 case CCValAssign::Full: break;
2937 case CCValAssign::SExt:
2938 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2940 case CCValAssign::ZExt:
2941 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2943 case CCValAssign::AExt:
2944 if (RegVT.is128BitVector()) {
2945 // Special case: passing MMX values in XMM registers.
2946 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2947 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2948 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2950 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2952 case CCValAssign::BCvt:
2953 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2955 case CCValAssign::Indirect: {
2956 // Store the argument.
2957 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2958 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2959 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2960 MachinePointerInfo::getFixedStack(FI),
2967 if (VA.isRegLoc()) {
2968 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2969 if (isVarArg && IsWin64) {
2970 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2971 // shadow reg if callee is a varargs function.
2972 unsigned ShadowReg = 0;
2973 switch (VA.getLocReg()) {
2974 case X86::XMM0: ShadowReg = X86::RCX; break;
2975 case X86::XMM1: ShadowReg = X86::RDX; break;
2976 case X86::XMM2: ShadowReg = X86::R8; break;
2977 case X86::XMM3: ShadowReg = X86::R9; break;
2980 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2982 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2983 assert(VA.isMemLoc());
2984 if (!StackPtr.getNode())
2985 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2987 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2988 dl, DAG, VA, Flags));
2992 if (!MemOpChains.empty())
2993 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2995 if (Subtarget->isPICStyleGOT()) {
2996 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2999 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
3000 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
3002 // If we are tail calling and generating PIC/GOT style code load the
3003 // address of the callee into ECX. The value in ecx is used as target of
3004 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3005 // for tail calls on PIC/GOT architectures. Normally we would just put the
3006 // address of GOT into ebx and then call target@PLT. But for tail calls
3007 // ebx would be restored (since ebx is callee saved) before jumping to the
3010 // Note: The actual moving to ECX is done further down.
3011 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3012 if (G && !G->getGlobal()->hasHiddenVisibility() &&
3013 !G->getGlobal()->hasProtectedVisibility())
3014 Callee = LowerGlobalAddress(Callee, DAG);
3015 else if (isa<ExternalSymbolSDNode>(Callee))
3016 Callee = LowerExternalSymbol(Callee, DAG);
3020 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3021 // From AMD64 ABI document:
3022 // For calls that may call functions that use varargs or stdargs
3023 // (prototype-less calls or calls to functions containing ellipsis (...) in
3024 // the declaration) %al is used as hidden argument to specify the number
3025 // of SSE registers used. The contents of %al do not need to match exactly
3026 // the number of registers, but must be an ubound on the number of SSE
3027 // registers used and is in the range 0 - 8 inclusive.
3029 // Count the number of XMM registers allocated.
3030 static const MCPhysReg XMMArgRegs[] = {
3031 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3032 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3034 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
3035 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3036 && "SSE registers cannot be used when SSE is disabled");
3038 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3039 DAG.getConstant(NumXMMRegs, MVT::i8)));
3042 if (isVarArg && IsMustTail) {
3043 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3044 for (const auto &F : Forwards) {
3045 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3046 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3050 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3051 // don't need this because the eligibility check rejects calls that require
3052 // shuffling arguments passed in memory.
3053 if (!IsSibcall && isTailCall) {
3054 // Force all the incoming stack arguments to be loaded from the stack
3055 // before any new outgoing arguments are stored to the stack, because the
3056 // outgoing stack slots may alias the incoming argument stack slots, and
3057 // the alias isn't otherwise explicit. This is slightly more conservative
3058 // than necessary, because it means that each store effectively depends
3059 // on every argument instead of just those arguments it would clobber.
3060 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3062 SmallVector<SDValue, 8> MemOpChains2;
3065 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3066 CCValAssign &VA = ArgLocs[i];
3069 assert(VA.isMemLoc());
3070 SDValue Arg = OutVals[i];
3071 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3072 // Skip inalloca arguments. They don't require any work.
3073 if (Flags.isInAlloca())
3075 // Create frame index.
3076 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3077 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3078 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3079 FIN = DAG.getFrameIndex(FI, getPointerTy());
3081 if (Flags.isByVal()) {
3082 // Copy relative to framepointer.
3083 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3084 if (!StackPtr.getNode())
3085 StackPtr = DAG.getCopyFromReg(Chain, dl,
3086 RegInfo->getStackRegister(),
3088 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3090 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3094 // Store relative to framepointer.
3095 MemOpChains2.push_back(
3096 DAG.getStore(ArgChain, dl, Arg, FIN,
3097 MachinePointerInfo::getFixedStack(FI),
3102 if (!MemOpChains2.empty())
3103 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3105 // Store the return address to the appropriate stack slot.
3106 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3107 getPointerTy(), RegInfo->getSlotSize(),
3111 // Build a sequence of copy-to-reg nodes chained together with token chain
3112 // and flag operands which copy the outgoing args into registers.
3114 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3115 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3116 RegsToPass[i].second, InFlag);
3117 InFlag = Chain.getValue(1);
3120 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3121 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3122 // In the 64-bit large code model, we have to make all calls
3123 // through a register, since the call instruction's 32-bit
3124 // pc-relative offset may not be large enough to hold the whole
3126 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3127 // If the callee is a GlobalAddress node (quite common, every direct call
3128 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3130 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3132 // We should use extra load for direct calls to dllimported functions in
3134 const GlobalValue *GV = G->getGlobal();
3135 if (!GV->hasDLLImportStorageClass()) {
3136 unsigned char OpFlags = 0;
3137 bool ExtraLoad = false;
3138 unsigned WrapperKind = ISD::DELETED_NODE;
3140 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3141 // external symbols most go through the PLT in PIC mode. If the symbol
3142 // has hidden or protected visibility, or if it is static or local, then
3143 // we don't need to use the PLT - we can directly call it.
3144 if (Subtarget->isTargetELF() &&
3145 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3146 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3147 OpFlags = X86II::MO_PLT;
3148 } else if (Subtarget->isPICStyleStubAny() &&
3149 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3150 (!Subtarget->getTargetTriple().isMacOSX() ||
3151 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3152 // PC-relative references to external symbols should go through $stub,
3153 // unless we're building with the leopard linker or later, which
3154 // automatically synthesizes these stubs.
3155 OpFlags = X86II::MO_DARWIN_STUB;
3156 } else if (Subtarget->isPICStyleRIPRel() &&
3157 isa<Function>(GV) &&
3158 cast<Function>(GV)->getAttributes().
3159 hasAttribute(AttributeSet::FunctionIndex,
3160 Attribute::NonLazyBind)) {
3161 // If the function is marked as non-lazy, generate an indirect call
3162 // which loads from the GOT directly. This avoids runtime overhead
3163 // at the cost of eager binding (and one extra byte of encoding).
3164 OpFlags = X86II::MO_GOTPCREL;
3165 WrapperKind = X86ISD::WrapperRIP;
3169 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3170 G->getOffset(), OpFlags);
3172 // Add a wrapper if needed.
3173 if (WrapperKind != ISD::DELETED_NODE)
3174 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3175 // Add extra indirection if needed.
3177 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3178 MachinePointerInfo::getGOT(),
3179 false, false, false, 0);
3181 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3182 unsigned char OpFlags = 0;
3184 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3185 // external symbols should go through the PLT.
3186 if (Subtarget->isTargetELF() &&
3187 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3188 OpFlags = X86II::MO_PLT;
3189 } else if (Subtarget->isPICStyleStubAny() &&
3190 (!Subtarget->getTargetTriple().isMacOSX() ||
3191 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3192 // PC-relative references to external symbols should go through $stub,
3193 // unless we're building with the leopard linker or later, which
3194 // automatically synthesizes these stubs.
3195 OpFlags = X86II::MO_DARWIN_STUB;
3198 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3200 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3201 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3202 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3205 // Returns a chain & a flag for retval copy to use.
3206 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3207 SmallVector<SDValue, 8> Ops;
3209 if (!IsSibcall && isTailCall) {
3210 Chain = DAG.getCALLSEQ_END(Chain,
3211 DAG.getIntPtrConstant(NumBytesToPop, true),
3212 DAG.getIntPtrConstant(0, true), InFlag, dl);
3213 InFlag = Chain.getValue(1);
3216 Ops.push_back(Chain);
3217 Ops.push_back(Callee);
3220 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3222 // Add argument registers to the end of the list so that they are known live
3224 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3225 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3226 RegsToPass[i].second.getValueType()));
3228 // Add a register mask operand representing the call-preserved registers.
3229 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3230 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3231 assert(Mask && "Missing call preserved mask for calling convention");
3232 Ops.push_back(DAG.getRegisterMask(Mask));
3234 if (InFlag.getNode())
3235 Ops.push_back(InFlag);
3239 //// If this is the first return lowered for this function, add the regs
3240 //// to the liveout set for the function.
3241 // This isn't right, although it's probably harmless on x86; liveouts
3242 // should be computed from returns not tail calls. Consider a void
3243 // function making a tail call to a function returning int.
3244 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3247 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3248 InFlag = Chain.getValue(1);
3250 // Create the CALLSEQ_END node.
3251 unsigned NumBytesForCalleeToPop;
3252 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3253 DAG.getTarget().Options.GuaranteedTailCallOpt))
3254 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3255 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3256 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3257 SR == StackStructReturn)
3258 // If this is a call to a struct-return function, the callee
3259 // pops the hidden struct pointer, so we have to push it back.
3260 // This is common for Darwin/X86, Linux & Mingw32 targets.
3261 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3262 NumBytesForCalleeToPop = 4;
3264 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3266 // Returns a flag for retval copy to use.
3268 Chain = DAG.getCALLSEQ_END(Chain,
3269 DAG.getIntPtrConstant(NumBytesToPop, true),
3270 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3273 InFlag = Chain.getValue(1);
3276 // Handle result values, copying them out of physregs into vregs that we
3278 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3279 Ins, dl, DAG, InVals);
3282 //===----------------------------------------------------------------------===//
3283 // Fast Calling Convention (tail call) implementation
3284 //===----------------------------------------------------------------------===//
3286 // Like std call, callee cleans arguments, convention except that ECX is
3287 // reserved for storing the tail called function address. Only 2 registers are
3288 // free for argument passing (inreg). Tail call optimization is performed
3290 // * tailcallopt is enabled
3291 // * caller/callee are fastcc
3292 // On X86_64 architecture with GOT-style position independent code only local
3293 // (within module) calls are supported at the moment.
3294 // To keep the stack aligned according to platform abi the function
3295 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3296 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3297 // If a tail called function callee has more arguments than the caller the
3298 // caller needs to make sure that there is room to move the RETADDR to. This is
3299 // achieved by reserving an area the size of the argument delta right after the
3300 // original RETADDR, but before the saved framepointer or the spilled registers
3301 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3313 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3314 /// for a 16 byte align requirement.
3316 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3317 SelectionDAG& DAG) const {
3318 MachineFunction &MF = DAG.getMachineFunction();
3319 const TargetMachine &TM = MF.getTarget();
3320 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3321 TM.getSubtargetImpl()->getRegisterInfo());
3322 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3323 unsigned StackAlignment = TFI.getStackAlignment();
3324 uint64_t AlignMask = StackAlignment - 1;
3325 int64_t Offset = StackSize;
3326 unsigned SlotSize = RegInfo->getSlotSize();
3327 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3328 // Number smaller than 12 so just add the difference.
3329 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3331 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3332 Offset = ((~AlignMask) & Offset) + StackAlignment +
3333 (StackAlignment-SlotSize);
3338 /// MatchingStackOffset - Return true if the given stack call argument is
3339 /// already available in the same position (relatively) of the caller's
3340 /// incoming argument stack.
3342 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3343 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3344 const X86InstrInfo *TII) {
3345 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3347 if (Arg.getOpcode() == ISD::CopyFromReg) {
3348 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3349 if (!TargetRegisterInfo::isVirtualRegister(VR))
3351 MachineInstr *Def = MRI->getVRegDef(VR);
3354 if (!Flags.isByVal()) {
3355 if (!TII->isLoadFromStackSlot(Def, FI))
3358 unsigned Opcode = Def->getOpcode();
3359 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3360 Opcode == X86::LEA64_32r) &&
3361 Def->getOperand(1).isFI()) {
3362 FI = Def->getOperand(1).getIndex();
3363 Bytes = Flags.getByValSize();
3367 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3368 if (Flags.isByVal())
3369 // ByVal argument is passed in as a pointer but it's now being
3370 // dereferenced. e.g.
3371 // define @foo(%struct.X* %A) {
3372 // tail call @bar(%struct.X* byval %A)
3375 SDValue Ptr = Ld->getBasePtr();
3376 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3379 FI = FINode->getIndex();
3380 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3381 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3382 FI = FINode->getIndex();
3383 Bytes = Flags.getByValSize();
3387 assert(FI != INT_MAX);
3388 if (!MFI->isFixedObjectIndex(FI))
3390 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3393 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3394 /// for tail call optimization. Targets which want to do tail call
3395 /// optimization should implement this function.
3397 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3398 CallingConv::ID CalleeCC,
3400 bool isCalleeStructRet,
3401 bool isCallerStructRet,
3403 const SmallVectorImpl<ISD::OutputArg> &Outs,
3404 const SmallVectorImpl<SDValue> &OutVals,
3405 const SmallVectorImpl<ISD::InputArg> &Ins,
3406 SelectionDAG &DAG) const {
3407 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3410 // If -tailcallopt is specified, make fastcc functions tail-callable.
3411 const MachineFunction &MF = DAG.getMachineFunction();
3412 const Function *CallerF = MF.getFunction();
3414 // If the function return type is x86_fp80 and the callee return type is not,
3415 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3416 // perform a tailcall optimization here.
3417 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3420 CallingConv::ID CallerCC = CallerF->getCallingConv();
3421 bool CCMatch = CallerCC == CalleeCC;
3422 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3423 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3425 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3426 if (IsTailCallConvention(CalleeCC) && CCMatch)
3431 // Look for obvious safe cases to perform tail call optimization that do not
3432 // require ABI changes. This is what gcc calls sibcall.
3434 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3435 // emit a special epilogue.
3436 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3437 DAG.getSubtarget().getRegisterInfo());
3438 if (RegInfo->needsStackRealignment(MF))
3441 // Also avoid sibcall optimization if either caller or callee uses struct
3442 // return semantics.
3443 if (isCalleeStructRet || isCallerStructRet)
3446 // An stdcall/thiscall caller is expected to clean up its arguments; the
3447 // callee isn't going to do that.
3448 // FIXME: this is more restrictive than needed. We could produce a tailcall
3449 // when the stack adjustment matches. For example, with a thiscall that takes
3450 // only one argument.
3451 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3452 CallerCC == CallingConv::X86_ThisCall))
3455 // Do not sibcall optimize vararg calls unless all arguments are passed via
3457 if (isVarArg && !Outs.empty()) {
3459 // Optimizing for varargs on Win64 is unlikely to be safe without
3460 // additional testing.
3461 if (IsCalleeWin64 || IsCallerWin64)
3464 SmallVector<CCValAssign, 16> ArgLocs;
3465 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3468 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3469 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3470 if (!ArgLocs[i].isRegLoc())
3474 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3475 // stack. Therefore, if it's not used by the call it is not safe to optimize
3476 // this into a sibcall.
3477 bool Unused = false;
3478 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3485 SmallVector<CCValAssign, 16> RVLocs;
3486 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3488 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3489 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3490 CCValAssign &VA = RVLocs[i];
3491 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3496 // If the calling conventions do not match, then we'd better make sure the
3497 // results are returned in the same way as what the caller expects.
3499 SmallVector<CCValAssign, 16> RVLocs1;
3500 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3502 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3504 SmallVector<CCValAssign, 16> RVLocs2;
3505 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3507 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3509 if (RVLocs1.size() != RVLocs2.size())
3511 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3512 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3514 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3516 if (RVLocs1[i].isRegLoc()) {
3517 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3520 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3526 // If the callee takes no arguments then go on to check the results of the
3528 if (!Outs.empty()) {
3529 // Check if stack adjustment is needed. For now, do not do this if any
3530 // argument is passed on the stack.
3531 SmallVector<CCValAssign, 16> ArgLocs;
3532 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3535 // Allocate shadow area for Win64
3537 CCInfo.AllocateStack(32, 8);
3539 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3540 if (CCInfo.getNextStackOffset()) {
3541 MachineFunction &MF = DAG.getMachineFunction();
3542 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3545 // Check if the arguments are already laid out in the right way as
3546 // the caller's fixed stack objects.
3547 MachineFrameInfo *MFI = MF.getFrameInfo();
3548 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3549 const X86InstrInfo *TII =
3550 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3551 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3552 CCValAssign &VA = ArgLocs[i];
3553 SDValue Arg = OutVals[i];
3554 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3555 if (VA.getLocInfo() == CCValAssign::Indirect)
3557 if (!VA.isRegLoc()) {
3558 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3565 // If the tailcall address may be in a register, then make sure it's
3566 // possible to register allocate for it. In 32-bit, the call address can
3567 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3568 // callee-saved registers are restored. These happen to be the same
3569 // registers used to pass 'inreg' arguments so watch out for those.
3570 if (!Subtarget->is64Bit() &&
3571 ((!isa<GlobalAddressSDNode>(Callee) &&
3572 !isa<ExternalSymbolSDNode>(Callee)) ||
3573 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3574 unsigned NumInRegs = 0;
3575 // In PIC we need an extra register to formulate the address computation
3577 unsigned MaxInRegs =
3578 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3580 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3581 CCValAssign &VA = ArgLocs[i];
3584 unsigned Reg = VA.getLocReg();
3587 case X86::EAX: case X86::EDX: case X86::ECX:
3588 if (++NumInRegs == MaxInRegs)
3600 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3601 const TargetLibraryInfo *libInfo) const {
3602 return X86::createFastISel(funcInfo, libInfo);
3605 //===----------------------------------------------------------------------===//
3606 // Other Lowering Hooks
3607 //===----------------------------------------------------------------------===//
3609 static bool MayFoldLoad(SDValue Op) {
3610 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3613 static bool MayFoldIntoStore(SDValue Op) {
3614 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3617 static bool isTargetShuffle(unsigned Opcode) {
3619 default: return false;
3620 case X86ISD::BLENDI:
3621 case X86ISD::PSHUFB:
3622 case X86ISD::PSHUFD:
3623 case X86ISD::PSHUFHW:
3624 case X86ISD::PSHUFLW:
3626 case X86ISD::PALIGNR:
3627 case X86ISD::MOVLHPS:
3628 case X86ISD::MOVLHPD:
3629 case X86ISD::MOVHLPS:
3630 case X86ISD::MOVLPS:
3631 case X86ISD::MOVLPD:
3632 case X86ISD::MOVSHDUP:
3633 case X86ISD::MOVSLDUP:
3634 case X86ISD::MOVDDUP:
3637 case X86ISD::UNPCKL:
3638 case X86ISD::UNPCKH:
3639 case X86ISD::VPERMILPI:
3640 case X86ISD::VPERM2X128:
3641 case X86ISD::VPERMI:
3646 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3647 SDValue V1, SelectionDAG &DAG) {
3649 default: llvm_unreachable("Unknown x86 shuffle node");
3650 case X86ISD::MOVSHDUP:
3651 case X86ISD::MOVSLDUP:
3652 case X86ISD::MOVDDUP:
3653 return DAG.getNode(Opc, dl, VT, V1);
3657 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3658 SDValue V1, unsigned TargetMask,
3659 SelectionDAG &DAG) {
3661 default: llvm_unreachable("Unknown x86 shuffle node");
3662 case X86ISD::PSHUFD:
3663 case X86ISD::PSHUFHW:
3664 case X86ISD::PSHUFLW:
3665 case X86ISD::VPERMILPI:
3666 case X86ISD::VPERMI:
3667 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3671 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3672 SDValue V1, SDValue V2, unsigned TargetMask,
3673 SelectionDAG &DAG) {
3675 default: llvm_unreachable("Unknown x86 shuffle node");
3676 case X86ISD::PALIGNR:
3677 case X86ISD::VALIGN:
3679 case X86ISD::VPERM2X128:
3680 return DAG.getNode(Opc, dl, VT, V1, V2,
3681 DAG.getConstant(TargetMask, MVT::i8));
3685 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3686 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3688 default: llvm_unreachable("Unknown x86 shuffle node");
3689 case X86ISD::MOVLHPS:
3690 case X86ISD::MOVLHPD:
3691 case X86ISD::MOVHLPS:
3692 case X86ISD::MOVLPS:
3693 case X86ISD::MOVLPD:
3696 case X86ISD::UNPCKL:
3697 case X86ISD::UNPCKH:
3698 return DAG.getNode(Opc, dl, VT, V1, V2);
3702 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3703 MachineFunction &MF = DAG.getMachineFunction();
3704 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3705 DAG.getSubtarget().getRegisterInfo());
3706 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3707 int ReturnAddrIndex = FuncInfo->getRAIndex();
3709 if (ReturnAddrIndex == 0) {
3710 // Set up a frame object for the return address.
3711 unsigned SlotSize = RegInfo->getSlotSize();
3712 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3715 FuncInfo->setRAIndex(ReturnAddrIndex);
3718 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3721 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3722 bool hasSymbolicDisplacement) {
3723 // Offset should fit into 32 bit immediate field.
3724 if (!isInt<32>(Offset))
3727 // If we don't have a symbolic displacement - we don't have any extra
3729 if (!hasSymbolicDisplacement)
3732 // FIXME: Some tweaks might be needed for medium code model.
3733 if (M != CodeModel::Small && M != CodeModel::Kernel)
3736 // For small code model we assume that latest object is 16MB before end of 31
3737 // bits boundary. We may also accept pretty large negative constants knowing
3738 // that all objects are in the positive half of address space.
3739 if (M == CodeModel::Small && Offset < 16*1024*1024)
3742 // For kernel code model we know that all object resist in the negative half
3743 // of 32bits address space. We may not accept negative offsets, since they may
3744 // be just off and we may accept pretty large positive ones.
3745 if (M == CodeModel::Kernel && Offset >= 0)
3751 /// isCalleePop - Determines whether the callee is required to pop its
3752 /// own arguments. Callee pop is necessary to support tail calls.
3753 bool X86::isCalleePop(CallingConv::ID CallingConv,
3754 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3755 switch (CallingConv) {
3758 case CallingConv::X86_StdCall:
3759 case CallingConv::X86_FastCall:
3760 case CallingConv::X86_ThisCall:
3762 case CallingConv::Fast:
3763 case CallingConv::GHC:
3764 case CallingConv::HiPE:
3771 /// \brief Return true if the condition is an unsigned comparison operation.
3772 static bool isX86CCUnsigned(unsigned X86CC) {
3774 default: llvm_unreachable("Invalid integer condition!");
3775 case X86::COND_E: return true;
3776 case X86::COND_G: return false;
3777 case X86::COND_GE: return false;
3778 case X86::COND_L: return false;
3779 case X86::COND_LE: return false;
3780 case X86::COND_NE: return true;
3781 case X86::COND_B: return true;
3782 case X86::COND_A: return true;
3783 case X86::COND_BE: return true;
3784 case X86::COND_AE: return true;
3786 llvm_unreachable("covered switch fell through?!");
3789 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3790 /// specific condition code, returning the condition code and the LHS/RHS of the
3791 /// comparison to make.
3792 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3793 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3795 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3796 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3797 // X > -1 -> X == 0, jump !sign.
3798 RHS = DAG.getConstant(0, RHS.getValueType());
3799 return X86::COND_NS;
3801 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3802 // X < 0 -> X == 0, jump on sign.
3805 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3807 RHS = DAG.getConstant(0, RHS.getValueType());
3808 return X86::COND_LE;
3812 switch (SetCCOpcode) {
3813 default: llvm_unreachable("Invalid integer condition!");
3814 case ISD::SETEQ: return X86::COND_E;
3815 case ISD::SETGT: return X86::COND_G;
3816 case ISD::SETGE: return X86::COND_GE;
3817 case ISD::SETLT: return X86::COND_L;
3818 case ISD::SETLE: return X86::COND_LE;
3819 case ISD::SETNE: return X86::COND_NE;
3820 case ISD::SETULT: return X86::COND_B;
3821 case ISD::SETUGT: return X86::COND_A;
3822 case ISD::SETULE: return X86::COND_BE;
3823 case ISD::SETUGE: return X86::COND_AE;
3827 // First determine if it is required or is profitable to flip the operands.
3829 // If LHS is a foldable load, but RHS is not, flip the condition.
3830 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3831 !ISD::isNON_EXTLoad(RHS.getNode())) {
3832 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3833 std::swap(LHS, RHS);
3836 switch (SetCCOpcode) {
3842 std::swap(LHS, RHS);
3846 // On a floating point condition, the flags are set as follows:
3848 // 0 | 0 | 0 | X > Y
3849 // 0 | 0 | 1 | X < Y
3850 // 1 | 0 | 0 | X == Y
3851 // 1 | 1 | 1 | unordered
3852 switch (SetCCOpcode) {
3853 default: llvm_unreachable("Condcode should be pre-legalized away");
3855 case ISD::SETEQ: return X86::COND_E;
3856 case ISD::SETOLT: // flipped
3858 case ISD::SETGT: return X86::COND_A;
3859 case ISD::SETOLE: // flipped
3861 case ISD::SETGE: return X86::COND_AE;
3862 case ISD::SETUGT: // flipped
3864 case ISD::SETLT: return X86::COND_B;
3865 case ISD::SETUGE: // flipped
3867 case ISD::SETLE: return X86::COND_BE;
3869 case ISD::SETNE: return X86::COND_NE;
3870 case ISD::SETUO: return X86::COND_P;
3871 case ISD::SETO: return X86::COND_NP;
3873 case ISD::SETUNE: return X86::COND_INVALID;
3877 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3878 /// code. Current x86 isa includes the following FP cmov instructions:
3879 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3880 static bool hasFPCMov(unsigned X86CC) {
3896 /// isFPImmLegal - Returns true if the target can instruction select the
3897 /// specified FP immediate natively. If false, the legalizer will
3898 /// materialize the FP immediate as a load from a constant pool.
3899 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3900 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3901 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3907 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3908 ISD::LoadExtType ExtTy,
3910 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3911 // relocation target a movq or addq instruction: don't let the load shrink.
3912 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3913 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3914 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3915 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3919 /// \brief Returns true if it is beneficial to convert a load of a constant
3920 /// to just the constant itself.
3921 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3923 assert(Ty->isIntegerTy());
3925 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3926 if (BitSize == 0 || BitSize > 64)
3931 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3932 unsigned Index) const {
3933 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3936 return (Index == 0 || Index == ResVT.getVectorNumElements());
3939 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3940 // Speculate cttz only if we can directly use TZCNT.
3941 return Subtarget->hasBMI();
3944 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3945 // Speculate ctlz only if we can directly use LZCNT.
3946 return Subtarget->hasLZCNT();
3949 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3950 /// the specified range (L, H].
3951 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3952 return (Val < 0) || (Val >= Low && Val < Hi);
3955 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3956 /// specified value.
3957 static bool isUndefOrEqual(int Val, int CmpVal) {
3958 return (Val < 0 || Val == CmpVal);
3961 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3962 /// from position Pos and ending in Pos+Size, falls within the specified
3963 /// sequential range (Low, Low+Size]. or is undef.
3964 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3965 unsigned Pos, unsigned Size, int Low) {
3966 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3967 if (!isUndefOrEqual(Mask[i], Low))
3972 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3973 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3974 /// operand - by default will match for first operand.
3975 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3976 bool TestSecondOperand = false) {
3977 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3978 VT != MVT::v2f64 && VT != MVT::v2i64)
3981 unsigned NumElems = VT.getVectorNumElements();
3982 unsigned Lo = TestSecondOperand ? NumElems : 0;
3983 unsigned Hi = Lo + NumElems;
3985 for (unsigned i = 0; i < NumElems; ++i)
3986 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3992 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3993 /// is suitable for input to PSHUFHW.
3994 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3995 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3998 // Lower quadword copied in order or undef.
3999 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
4002 // Upper quadword shuffled.
4003 for (unsigned i = 4; i != 8; ++i)
4004 if (!isUndefOrInRange(Mask[i], 4, 8))
4007 if (VT == MVT::v16i16) {
4008 // Lower quadword copied in order or undef.
4009 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
4012 // Upper quadword shuffled.
4013 for (unsigned i = 12; i != 16; ++i)
4014 if (!isUndefOrInRange(Mask[i], 12, 16))
4021 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
4022 /// is suitable for input to PSHUFLW.
4023 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4024 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
4027 // Upper quadword copied in order.
4028 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
4031 // Lower quadword shuffled.
4032 for (unsigned i = 0; i != 4; ++i)
4033 if (!isUndefOrInRange(Mask[i], 0, 4))
4036 if (VT == MVT::v16i16) {
4037 // Upper quadword copied in order.
4038 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
4041 // Lower quadword shuffled.
4042 for (unsigned i = 8; i != 12; ++i)
4043 if (!isUndefOrInRange(Mask[i], 8, 12))
4050 /// \brief Return true if the mask specifies a shuffle of elements that is
4051 /// suitable for input to intralane (palignr) or interlane (valign) vector
4053 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4054 unsigned NumElts = VT.getVectorNumElements();
4055 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4056 unsigned NumLaneElts = NumElts/NumLanes;
4058 // Do not handle 64-bit element shuffles with palignr.
4059 if (NumLaneElts == 2)
4062 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4064 for (i = 0; i != NumLaneElts; ++i) {
4069 // Lane is all undef, go to next lane
4070 if (i == NumLaneElts)
4073 int Start = Mask[i+l];
4075 // Make sure its in this lane in one of the sources
4076 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4077 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4080 // If not lane 0, then we must match lane 0
4081 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4084 // Correct second source to be contiguous with first source
4085 if (Start >= (int)NumElts)
4086 Start -= NumElts - NumLaneElts;
4088 // Make sure we're shifting in the right direction.
4089 if (Start <= (int)(i+l))
4094 // Check the rest of the elements to see if they are consecutive.
4095 for (++i; i != NumLaneElts; ++i) {
4096 int Idx = Mask[i+l];
4098 // Make sure its in this lane
4099 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4100 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4103 // If not lane 0, then we must match lane 0
4104 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4107 if (Idx >= (int)NumElts)
4108 Idx -= NumElts - NumLaneElts;
4110 if (!isUndefOrEqual(Idx, Start+i))
4119 /// \brief Return true if the node specifies a shuffle of elements that is
4120 /// suitable for input to PALIGNR.
4121 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4122 const X86Subtarget *Subtarget) {
4123 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4124 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4125 VT.is512BitVector())
4126 // FIXME: Add AVX512BW.
4129 return isAlignrMask(Mask, VT, false);
4132 /// \brief Return true if the node specifies a shuffle of elements that is
4133 /// suitable for input to VALIGN.
4134 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4135 const X86Subtarget *Subtarget) {
4136 // FIXME: Add AVX512VL.
4137 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4139 return isAlignrMask(Mask, VT, true);
4142 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4143 /// the two vector operands have swapped position.
4144 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4145 unsigned NumElems) {
4146 for (unsigned i = 0; i != NumElems; ++i) {
4150 else if (idx < (int)NumElems)
4151 Mask[i] = idx + NumElems;
4153 Mask[i] = idx - NumElems;
4157 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4158 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4159 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4160 /// reverse of what x86 shuffles want.
4161 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4163 unsigned NumElems = VT.getVectorNumElements();
4164 unsigned NumLanes = VT.getSizeInBits()/128;
4165 unsigned NumLaneElems = NumElems/NumLanes;
4167 if (NumLaneElems != 2 && NumLaneElems != 4)
4170 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4171 bool symetricMaskRequired =
4172 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4174 // VSHUFPSY divides the resulting vector into 4 chunks.
4175 // The sources are also splitted into 4 chunks, and each destination
4176 // chunk must come from a different source chunk.
4178 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4179 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4181 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4182 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4184 // VSHUFPDY divides the resulting vector into 4 chunks.
4185 // The sources are also splitted into 4 chunks, and each destination
4186 // chunk must come from a different source chunk.
4188 // SRC1 => X3 X2 X1 X0
4189 // SRC2 => Y3 Y2 Y1 Y0
4191 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4193 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4194 unsigned HalfLaneElems = NumLaneElems/2;
4195 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4196 for (unsigned i = 0; i != NumLaneElems; ++i) {
4197 int Idx = Mask[i+l];
4198 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4199 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4201 // For VSHUFPSY, the mask of the second half must be the same as the
4202 // first but with the appropriate offsets. This works in the same way as
4203 // VPERMILPS works with masks.
4204 if (!symetricMaskRequired || Idx < 0)
4206 if (MaskVal[i] < 0) {
4207 MaskVal[i] = Idx - l;
4210 if ((signed)(Idx - l) != MaskVal[i])
4218 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4219 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4220 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4221 if (!VT.is128BitVector())
4224 unsigned NumElems = VT.getVectorNumElements();
4229 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4230 return isUndefOrEqual(Mask[0], 6) &&
4231 isUndefOrEqual(Mask[1], 7) &&
4232 isUndefOrEqual(Mask[2], 2) &&
4233 isUndefOrEqual(Mask[3], 3);
4236 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4237 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4239 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4240 if (!VT.is128BitVector())
4243 unsigned NumElems = VT.getVectorNumElements();
4248 return isUndefOrEqual(Mask[0], 2) &&
4249 isUndefOrEqual(Mask[1], 3) &&
4250 isUndefOrEqual(Mask[2], 2) &&
4251 isUndefOrEqual(Mask[3], 3);
4254 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4255 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4256 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4257 if (!VT.is128BitVector())
4260 unsigned NumElems = VT.getVectorNumElements();
4262 if (NumElems != 2 && NumElems != 4)
4265 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4266 if (!isUndefOrEqual(Mask[i], i + NumElems))
4269 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4270 if (!isUndefOrEqual(Mask[i], i))
4276 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4277 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4278 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4279 if (!VT.is128BitVector())
4282 unsigned NumElems = VT.getVectorNumElements();
4284 if (NumElems != 2 && NumElems != 4)
4287 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4288 if (!isUndefOrEqual(Mask[i], i))
4291 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4292 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4298 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4300 /// i. e: If all but one element come from the same vector.
4301 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4302 // TODO: Deal with AVX's VINSERTPS
4303 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4306 unsigned CorrectPosV1 = 0;
4307 unsigned CorrectPosV2 = 0;
4308 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4309 if (Mask[i] == -1) {
4317 else if (Mask[i] == i + 4)
4321 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4322 // We have 3 elements (undefs count as elements from any vector) from one
4323 // vector, and one from another.
4330 // Some special combinations that can be optimized.
4333 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4334 SelectionDAG &DAG) {
4335 MVT VT = SVOp->getSimpleValueType(0);
4338 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4341 ArrayRef<int> Mask = SVOp->getMask();
4343 // These are the special masks that may be optimized.
4344 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4345 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4346 bool MatchEvenMask = true;
4347 bool MatchOddMask = true;
4348 for (int i=0; i<8; ++i) {
4349 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4350 MatchEvenMask = false;
4351 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4352 MatchOddMask = false;
4355 if (!MatchEvenMask && !MatchOddMask)
4358 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4360 SDValue Op0 = SVOp->getOperand(0);
4361 SDValue Op1 = SVOp->getOperand(1);
4363 if (MatchEvenMask) {
4364 // Shift the second operand right to 32 bits.
4365 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4366 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4368 // Shift the first operand left to 32 bits.
4369 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4370 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4372 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4373 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4376 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4377 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4378 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4379 bool HasInt256, bool V2IsSplat = false) {
4381 assert(VT.getSizeInBits() >= 128 &&
4382 "Unsupported vector type for unpckl");
4384 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4386 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4389 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4390 "Unsupported vector type for unpckh");
4392 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4393 unsigned NumLanes = VT.getSizeInBits()/128;
4394 unsigned NumLaneElts = NumElts/NumLanes;
4396 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4397 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4398 int BitI = Mask[l+i];
4399 int BitI1 = Mask[l+i+1];
4400 if (!isUndefOrEqual(BitI, j))
4403 if (!isUndefOrEqual(BitI1, NumElts))
4406 if (!isUndefOrEqual(BitI1, j + NumElts))
4415 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4416 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4417 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4418 bool HasInt256, bool V2IsSplat = false) {
4419 assert(VT.getSizeInBits() >= 128 &&
4420 "Unsupported vector type for unpckh");
4422 unsigned NumElts = VT.getVectorNumElements();
4423 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4424 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4427 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4428 "Unsupported vector type for unpckh");
4430 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4431 unsigned NumLanes = VT.getSizeInBits()/128;
4432 unsigned NumLaneElts = NumElts/NumLanes;
4434 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4435 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4436 int BitI = Mask[l+i];
4437 int BitI1 = Mask[l+i+1];
4438 if (!isUndefOrEqual(BitI, j))
4441 if (isUndefOrEqual(BitI1, NumElts))
4444 if (!isUndefOrEqual(BitI1, j+NumElts))
4452 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4453 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4455 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4456 unsigned NumElts = VT.getVectorNumElements();
4457 bool Is256BitVec = VT.is256BitVector();
4459 if (VT.is512BitVector())
4461 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4462 "Unsupported vector type for unpckh");
4464 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4465 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4468 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4469 // FIXME: Need a better way to get rid of this, there's no latency difference
4470 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4471 // the former later. We should also remove the "_undef" special mask.
4472 if (NumElts == 4 && Is256BitVec)
4475 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4476 // independently on 128-bit lanes.
4477 unsigned NumLanes = VT.getSizeInBits()/128;
4478 unsigned NumLaneElts = NumElts/NumLanes;
4480 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4481 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4482 int BitI = Mask[l+i];
4483 int BitI1 = Mask[l+i+1];
4485 if (!isUndefOrEqual(BitI, j))
4487 if (!isUndefOrEqual(BitI1, j))
4495 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4496 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4498 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4499 unsigned NumElts = VT.getVectorNumElements();
4501 if (VT.is512BitVector())
4504 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4505 "Unsupported vector type for unpckh");
4507 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4508 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4511 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4512 // independently on 128-bit lanes.
4513 unsigned NumLanes = VT.getSizeInBits()/128;
4514 unsigned NumLaneElts = NumElts/NumLanes;
4516 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4517 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4518 int BitI = Mask[l+i];
4519 int BitI1 = Mask[l+i+1];
4520 if (!isUndefOrEqual(BitI, j))
4522 if (!isUndefOrEqual(BitI1, j))
4529 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4530 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4531 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4532 if (!VT.is512BitVector())
4535 unsigned NumElts = VT.getVectorNumElements();
4536 unsigned HalfSize = NumElts/2;
4537 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4538 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4543 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4544 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4552 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4554 /// MOVSD, and MOVD, i.e. setting the lowest element.
4555 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4556 if (VT.getVectorElementType().getSizeInBits() < 32)
4558 if (!VT.is128BitVector())
4561 unsigned NumElts = VT.getVectorNumElements();
4563 if (!isUndefOrEqual(Mask[0], NumElts))
4566 for (unsigned i = 1; i != NumElts; ++i)
4567 if (!isUndefOrEqual(Mask[i], i))
4573 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4574 /// as permutations between 128-bit chunks or halves. As an example: this
4576 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4577 /// The first half comes from the second half of V1 and the second half from the
4578 /// the second half of V2.
4579 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4580 if (!HasFp256 || !VT.is256BitVector())
4583 // The shuffle result is divided into half A and half B. In total the two
4584 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4585 // B must come from C, D, E or F.
4586 unsigned HalfSize = VT.getVectorNumElements()/2;
4587 bool MatchA = false, MatchB = false;
4589 // Check if A comes from one of C, D, E, F.
4590 for (unsigned Half = 0; Half != 4; ++Half) {
4591 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4597 // Check if B comes from one of C, D, E, F.
4598 for (unsigned Half = 0; Half != 4; ++Half) {
4599 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4605 return MatchA && MatchB;
4608 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4609 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4610 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4611 MVT VT = SVOp->getSimpleValueType(0);
4613 unsigned HalfSize = VT.getVectorNumElements()/2;
4615 unsigned FstHalf = 0, SndHalf = 0;
4616 for (unsigned i = 0; i < HalfSize; ++i) {
4617 if (SVOp->getMaskElt(i) > 0) {
4618 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4622 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4623 if (SVOp->getMaskElt(i) > 0) {
4624 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4629 return (FstHalf | (SndHalf << 4));
4632 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4633 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4634 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4638 unsigned NumElts = VT.getVectorNumElements();
4640 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4641 for (unsigned i = 0; i != NumElts; ++i) {
4644 Imm8 |= Mask[i] << (i*2);
4649 unsigned LaneSize = 4;
4650 SmallVector<int, 4> MaskVal(LaneSize, -1);
4652 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4653 for (unsigned i = 0; i != LaneSize; ++i) {
4654 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4658 if (MaskVal[i] < 0) {
4659 MaskVal[i] = Mask[i+l] - l;
4660 Imm8 |= MaskVal[i] << (i*2);
4663 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4670 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4671 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4672 /// Note that VPERMIL mask matching is different depending whether theunderlying
4673 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4674 /// to the same elements of the low, but to the higher half of the source.
4675 /// In VPERMILPD the two lanes could be shuffled independently of each other
4676 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4677 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4678 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4679 if (VT.getSizeInBits() < 256 || EltSize < 32)
4681 bool symetricMaskRequired = (EltSize == 32);
4682 unsigned NumElts = VT.getVectorNumElements();
4684 unsigned NumLanes = VT.getSizeInBits()/128;
4685 unsigned LaneSize = NumElts/NumLanes;
4686 // 2 or 4 elements in one lane
4688 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4689 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4690 for (unsigned i = 0; i != LaneSize; ++i) {
4691 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4693 if (symetricMaskRequired) {
4694 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4695 ExpectedMaskVal[i] = Mask[i+l] - l;
4698 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4706 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4707 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4708 /// element of vector 2 and the other elements to come from vector 1 in order.
4709 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4710 bool V2IsSplat = false, bool V2IsUndef = false) {
4711 if (!VT.is128BitVector())
4714 unsigned NumOps = VT.getVectorNumElements();
4715 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4718 if (!isUndefOrEqual(Mask[0], 0))
4721 for (unsigned i = 1; i != NumOps; ++i)
4722 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4723 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4724 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4730 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4731 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4732 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4733 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4734 const X86Subtarget *Subtarget) {
4735 if (!Subtarget->hasSSE3())
4738 unsigned NumElems = VT.getVectorNumElements();
4740 if ((VT.is128BitVector() && NumElems != 4) ||
4741 (VT.is256BitVector() && NumElems != 8) ||
4742 (VT.is512BitVector() && NumElems != 16))
4745 // "i+1" is the value the indexed mask element must have
4746 for (unsigned i = 0; i != NumElems; i += 2)
4747 if (!isUndefOrEqual(Mask[i], i+1) ||
4748 !isUndefOrEqual(Mask[i+1], i+1))
4754 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4755 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4756 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4757 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4758 const X86Subtarget *Subtarget) {
4759 if (!Subtarget->hasSSE3())
4762 unsigned NumElems = VT.getVectorNumElements();
4764 if ((VT.is128BitVector() && NumElems != 4) ||
4765 (VT.is256BitVector() && NumElems != 8) ||
4766 (VT.is512BitVector() && NumElems != 16))
4769 // "i" is the value the indexed mask element must have
4770 for (unsigned i = 0; i != NumElems; i += 2)
4771 if (!isUndefOrEqual(Mask[i], i) ||
4772 !isUndefOrEqual(Mask[i+1], i))
4778 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4779 /// specifies a shuffle of elements that is suitable for input to 256-bit
4780 /// version of MOVDDUP.
4781 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4782 if (!HasFp256 || !VT.is256BitVector())
4785 unsigned NumElts = VT.getVectorNumElements();
4789 for (unsigned i = 0; i != NumElts/2; ++i)
4790 if (!isUndefOrEqual(Mask[i], 0))
4792 for (unsigned i = NumElts/2; i != NumElts; ++i)
4793 if (!isUndefOrEqual(Mask[i], NumElts/2))
4798 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4799 /// specifies a shuffle of elements that is suitable for input to 128-bit
4800 /// version of MOVDDUP.
4801 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4802 if (!VT.is128BitVector())
4805 unsigned e = VT.getVectorNumElements() / 2;
4806 for (unsigned i = 0; i != e; ++i)
4807 if (!isUndefOrEqual(Mask[i], i))
4809 for (unsigned i = 0; i != e; ++i)
4810 if (!isUndefOrEqual(Mask[e+i], i))
4815 /// isVEXTRACTIndex - Return true if the specified
4816 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4817 /// suitable for instruction that extract 128 or 256 bit vectors
4818 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4819 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4820 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4823 // The index should be aligned on a vecWidth-bit boundary.
4825 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4827 MVT VT = N->getSimpleValueType(0);
4828 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4829 bool Result = (Index * ElSize) % vecWidth == 0;
4834 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4835 /// operand specifies a subvector insert that is suitable for input to
4836 /// insertion of 128 or 256-bit subvectors
4837 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4838 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4839 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4841 // The index should be aligned on a vecWidth-bit boundary.
4843 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4845 MVT VT = N->getSimpleValueType(0);
4846 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4847 bool Result = (Index * ElSize) % vecWidth == 0;
4852 bool X86::isVINSERT128Index(SDNode *N) {
4853 return isVINSERTIndex(N, 128);
4856 bool X86::isVINSERT256Index(SDNode *N) {
4857 return isVINSERTIndex(N, 256);
4860 bool X86::isVEXTRACT128Index(SDNode *N) {
4861 return isVEXTRACTIndex(N, 128);
4864 bool X86::isVEXTRACT256Index(SDNode *N) {
4865 return isVEXTRACTIndex(N, 256);
4868 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4869 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4870 /// Handles 128-bit and 256-bit.
4871 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4872 MVT VT = N->getSimpleValueType(0);
4874 assert((VT.getSizeInBits() >= 128) &&
4875 "Unsupported vector type for PSHUF/SHUFP");
4877 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4878 // independently on 128-bit lanes.
4879 unsigned NumElts = VT.getVectorNumElements();
4880 unsigned NumLanes = VT.getSizeInBits()/128;
4881 unsigned NumLaneElts = NumElts/NumLanes;
4883 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4884 "Only supports 2, 4 or 8 elements per lane");
4886 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4888 for (unsigned i = 0; i != NumElts; ++i) {
4889 int Elt = N->getMaskElt(i);
4890 if (Elt < 0) continue;
4891 Elt &= NumLaneElts - 1;
4892 unsigned ShAmt = (i << Shift) % 8;
4893 Mask |= Elt << ShAmt;
4899 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4900 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4901 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4902 MVT VT = N->getSimpleValueType(0);
4904 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4905 "Unsupported vector type for PSHUFHW");
4907 unsigned NumElts = VT.getVectorNumElements();
4910 for (unsigned l = 0; l != NumElts; l += 8) {
4911 // 8 nodes per lane, but we only care about the last 4.
4912 for (unsigned i = 0; i < 4; ++i) {
4913 int Elt = N->getMaskElt(l+i+4);
4914 if (Elt < 0) continue;
4915 Elt &= 0x3; // only 2-bits.
4916 Mask |= Elt << (i * 2);
4923 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4924 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4925 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4926 MVT VT = N->getSimpleValueType(0);
4928 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4929 "Unsupported vector type for PSHUFHW");
4931 unsigned NumElts = VT.getVectorNumElements();
4934 for (unsigned l = 0; l != NumElts; l += 8) {
4935 // 8 nodes per lane, but we only care about the first 4.
4936 for (unsigned i = 0; i < 4; ++i) {
4937 int Elt = N->getMaskElt(l+i);
4938 if (Elt < 0) continue;
4939 Elt &= 0x3; // only 2-bits
4940 Mask |= Elt << (i * 2);
4947 /// \brief Return the appropriate immediate to shuffle the specified
4948 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4949 /// VALIGN (if Interlane is true) instructions.
4950 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4952 MVT VT = SVOp->getSimpleValueType(0);
4953 unsigned EltSize = InterLane ? 1 :
4954 VT.getVectorElementType().getSizeInBits() >> 3;
4956 unsigned NumElts = VT.getVectorNumElements();
4957 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4958 unsigned NumLaneElts = NumElts/NumLanes;
4962 for (i = 0; i != NumElts; ++i) {
4963 Val = SVOp->getMaskElt(i);
4967 if (Val >= (int)NumElts)
4968 Val -= NumElts - NumLaneElts;
4970 assert(Val - i > 0 && "PALIGNR imm should be positive");
4971 return (Val - i) * EltSize;
4974 /// \brief Return the appropriate immediate to shuffle the specified
4975 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4976 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4977 return getShuffleAlignrImmediate(SVOp, false);
4980 /// \brief Return the appropriate immediate to shuffle the specified
4981 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4982 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4983 return getShuffleAlignrImmediate(SVOp, true);
4987 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4988 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4989 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4990 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4993 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4995 MVT VecVT = N->getOperand(0).getSimpleValueType();
4996 MVT ElVT = VecVT.getVectorElementType();
4998 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4999 return Index / NumElemsPerChunk;
5002 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
5003 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
5004 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
5005 llvm_unreachable("Illegal insert subvector for VINSERT");
5008 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
5010 MVT VecVT = N->getSimpleValueType(0);
5011 MVT ElVT = VecVT.getVectorElementType();
5013 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
5014 return Index / NumElemsPerChunk;
5017 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
5018 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
5019 /// and VINSERTI128 instructions.
5020 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
5021 return getExtractVEXTRACTImmediate(N, 128);
5024 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
5025 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
5026 /// and VINSERTI64x4 instructions.
5027 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
5028 return getExtractVEXTRACTImmediate(N, 256);
5031 /// getInsertVINSERT128Immediate - Return the appropriate immediate
5032 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
5033 /// and VINSERTI128 instructions.
5034 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
5035 return getInsertVINSERTImmediate(N, 128);
5038 /// getInsertVINSERT256Immediate - Return the appropriate immediate
5039 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
5040 /// and VINSERTI64x4 instructions.
5041 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
5042 return getInsertVINSERTImmediate(N, 256);
5045 /// isZero - Returns true if Elt is a constant integer zero
5046 static bool isZero(SDValue V) {
5047 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
5048 return C && C->isNullValue();
5051 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
5053 bool X86::isZeroNode(SDValue Elt) {
5056 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5057 return CFP->getValueAPF().isPosZero();
5061 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5062 /// match movhlps. The lower half elements should come from upper half of
5063 /// V1 (and in order), and the upper half elements should come from the upper
5064 /// half of V2 (and in order).
5065 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5066 if (!VT.is128BitVector())
5068 if (VT.getVectorNumElements() != 4)
5070 for (unsigned i = 0, e = 2; i != e; ++i)
5071 if (!isUndefOrEqual(Mask[i], i+2))
5073 for (unsigned i = 2; i != 4; ++i)
5074 if (!isUndefOrEqual(Mask[i], i+4))
5079 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5080 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5082 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5083 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5085 N = N->getOperand(0).getNode();
5086 if (!ISD::isNON_EXTLoad(N))
5089 *LD = cast<LoadSDNode>(N);
5093 // Test whether the given value is a vector value which will be legalized
5095 static bool WillBeConstantPoolLoad(SDNode *N) {
5096 if (N->getOpcode() != ISD::BUILD_VECTOR)
5099 // Check for any non-constant elements.
5100 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5101 switch (N->getOperand(i).getNode()->getOpcode()) {
5103 case ISD::ConstantFP:
5110 // Vectors of all-zeros and all-ones are materialized with special
5111 // instructions rather than being loaded.
5112 return !ISD::isBuildVectorAllZeros(N) &&
5113 !ISD::isBuildVectorAllOnes(N);
5116 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5117 /// match movlp{s|d}. The lower half elements should come from lower half of
5118 /// V1 (and in order), and the upper half elements should come from the upper
5119 /// half of V2 (and in order). And since V1 will become the source of the
5120 /// MOVLP, it must be either a vector load or a scalar load to vector.
5121 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5122 ArrayRef<int> Mask, MVT VT) {
5123 if (!VT.is128BitVector())
5126 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5128 // Is V2 is a vector load, don't do this transformation. We will try to use
5129 // load folding shufps op.
5130 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5133 unsigned NumElems = VT.getVectorNumElements();
5135 if (NumElems != 2 && NumElems != 4)
5137 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5138 if (!isUndefOrEqual(Mask[i], i))
5140 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5141 if (!isUndefOrEqual(Mask[i], i+NumElems))
5146 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5147 /// to an zero vector.
5148 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5149 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5150 SDValue V1 = N->getOperand(0);
5151 SDValue V2 = N->getOperand(1);
5152 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5153 for (unsigned i = 0; i != NumElems; ++i) {
5154 int Idx = N->getMaskElt(i);
5155 if (Idx >= (int)NumElems) {
5156 unsigned Opc = V2.getOpcode();
5157 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5159 if (Opc != ISD::BUILD_VECTOR ||
5160 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5162 } else if (Idx >= 0) {
5163 unsigned Opc = V1.getOpcode();
5164 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5166 if (Opc != ISD::BUILD_VECTOR ||
5167 !X86::isZeroNode(V1.getOperand(Idx)))
5174 /// getZeroVector - Returns a vector of specified type with all zero elements.
5176 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5177 SelectionDAG &DAG, SDLoc dl) {
5178 assert(VT.isVector() && "Expected a vector type");
5180 // Always build SSE zero vectors as <4 x i32> bitcasted
5181 // to their dest type. This ensures they get CSE'd.
5183 if (VT.is128BitVector()) { // SSE
5184 if (Subtarget->hasSSE2()) { // SSE2
5185 SDValue Cst = DAG.getConstant(0, MVT::i32);
5186 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5188 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5189 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5191 } else if (VT.is256BitVector()) { // AVX
5192 if (Subtarget->hasInt256()) { // AVX2
5193 SDValue Cst = DAG.getConstant(0, MVT::i32);
5194 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5195 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5197 // 256-bit logic and arithmetic instructions in AVX are all
5198 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5199 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5200 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5201 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5203 } else if (VT.is512BitVector()) { // AVX-512
5204 SDValue Cst = DAG.getConstant(0, MVT::i32);
5205 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5206 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5207 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5208 } else if (VT.getScalarType() == MVT::i1) {
5209 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5210 SDValue Cst = DAG.getConstant(0, MVT::i1);
5211 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5212 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5214 llvm_unreachable("Unexpected vector type");
5216 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5219 /// getOnesVector - Returns a vector of specified type with all bits set.
5220 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5221 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5222 /// Then bitcast to their original type, ensuring they get CSE'd.
5223 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5225 assert(VT.isVector() && "Expected a vector type");
5227 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5229 if (VT.is256BitVector()) {
5230 if (HasInt256) { // AVX2
5231 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5232 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5234 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5235 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5237 } else if (VT.is128BitVector()) {
5238 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5240 llvm_unreachable("Unexpected vector type");
5242 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5245 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5246 /// that point to V2 points to its first element.
5247 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5248 for (unsigned i = 0; i != NumElems; ++i) {
5249 if (Mask[i] > (int)NumElems) {
5255 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5256 /// operation of specified width.
5257 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5259 unsigned NumElems = VT.getVectorNumElements();
5260 SmallVector<int, 8> Mask;
5261 Mask.push_back(NumElems);
5262 for (unsigned i = 1; i != NumElems; ++i)
5264 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5267 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5268 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 8> Mask;
5272 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5274 Mask.push_back(i + NumElems);
5276 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5279 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5280 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5282 unsigned NumElems = VT.getVectorNumElements();
5283 SmallVector<int, 8> Mask;
5284 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5285 Mask.push_back(i + Half);
5286 Mask.push_back(i + NumElems + Half);
5288 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5291 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5292 // a generic shuffle instruction because the target has no such instructions.
5293 // Generate shuffles which repeat i16 and i8 several times until they can be
5294 // represented by v4f32 and then be manipulated by target suported shuffles.
5295 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5296 MVT VT = V.getSimpleValueType();
5297 int NumElems = VT.getVectorNumElements();
5300 while (NumElems > 4) {
5301 if (EltNo < NumElems/2) {
5302 V = getUnpackl(DAG, dl, VT, V, V);
5304 V = getUnpackh(DAG, dl, VT, V, V);
5305 EltNo -= NumElems/2;
5312 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5313 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5314 MVT VT = V.getSimpleValueType();
5317 if (VT.is128BitVector()) {
5318 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5319 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5320 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5322 } else if (VT.is256BitVector()) {
5323 // To use VPERMILPS to splat scalars, the second half of indicies must
5324 // refer to the higher part, which is a duplication of the lower one,
5325 // because VPERMILPS can only handle in-lane permutations.
5326 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5327 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5329 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5330 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5333 llvm_unreachable("Vector size not supported");
5335 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5338 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5339 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5340 MVT SrcVT = SV->getSimpleValueType(0);
5341 SDValue V1 = SV->getOperand(0);
5344 int EltNo = SV->getSplatIndex();
5345 int NumElems = SrcVT.getVectorNumElements();
5346 bool Is256BitVec = SrcVT.is256BitVector();
5348 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5349 "Unknown how to promote splat for type");
5351 // Extract the 128-bit part containing the splat element and update
5352 // the splat element index when it refers to the higher register.
5354 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5355 if (EltNo >= NumElems/2)
5356 EltNo -= NumElems/2;
5359 // All i16 and i8 vector types can't be used directly by a generic shuffle
5360 // instruction because the target has no such instruction. Generate shuffles
5361 // which repeat i16 and i8 several times until they fit in i32, and then can
5362 // be manipulated by target suported shuffles.
5363 MVT EltVT = SrcVT.getVectorElementType();
5364 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5365 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5367 // Recreate the 256-bit vector and place the same 128-bit vector
5368 // into the low and high part. This is necessary because we want
5369 // to use VPERM* to shuffle the vectors
5371 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5374 return getLegalSplat(DAG, V1, EltNo);
5377 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5378 /// vector of zero or undef vector. This produces a shuffle where the low
5379 /// element of V2 is swizzled into the zero/undef vector, landing at element
5380 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5381 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5383 const X86Subtarget *Subtarget,
5384 SelectionDAG &DAG) {
5385 MVT VT = V2.getSimpleValueType();
5387 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5388 unsigned NumElems = VT.getVectorNumElements();
5389 SmallVector<int, 16> MaskVec;
5390 for (unsigned i = 0; i != NumElems; ++i)
5391 // If this is the insertion idx, put the low elt of V2 here.
5392 MaskVec.push_back(i == Idx ? NumElems : i);
5393 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5396 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5397 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5398 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5399 /// shuffles which use a single input multiple times, and in those cases it will
5400 /// adjust the mask to only have indices within that single input.
5401 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5402 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5403 unsigned NumElems = VT.getVectorNumElements();
5407 bool IsFakeUnary = false;
5408 switch(N->getOpcode()) {
5409 case X86ISD::BLENDI:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5414 ImmN = N->getOperand(N->getNumOperands()-1);
5415 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5416 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5418 case X86ISD::UNPCKH:
5419 DecodeUNPCKHMask(VT, Mask);
5420 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5422 case X86ISD::UNPCKL:
5423 DecodeUNPCKLMask(VT, Mask);
5424 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5426 case X86ISD::MOVHLPS:
5427 DecodeMOVHLPSMask(NumElems, Mask);
5428 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5430 case X86ISD::MOVLHPS:
5431 DecodeMOVLHPSMask(NumElems, Mask);
5432 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5434 case X86ISD::PALIGNR:
5435 ImmN = N->getOperand(N->getNumOperands()-1);
5436 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5438 case X86ISD::PSHUFD:
5439 case X86ISD::VPERMILPI:
5440 ImmN = N->getOperand(N->getNumOperands()-1);
5441 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5444 case X86ISD::PSHUFHW:
5445 ImmN = N->getOperand(N->getNumOperands()-1);
5446 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5449 case X86ISD::PSHUFLW:
5450 ImmN = N->getOperand(N->getNumOperands()-1);
5451 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5454 case X86ISD::PSHUFB: {
5456 SDValue MaskNode = N->getOperand(1);
5457 while (MaskNode->getOpcode() == ISD::BITCAST)
5458 MaskNode = MaskNode->getOperand(0);
5460 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5461 // If we have a build-vector, then things are easy.
5462 EVT VT = MaskNode.getValueType();
5463 assert(VT.isVector() &&
5464 "Can't produce a non-vector with a build_vector!");
5465 if (!VT.isInteger())
5468 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5470 SmallVector<uint64_t, 32> RawMask;
5471 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5472 SDValue Op = MaskNode->getOperand(i);
5473 if (Op->getOpcode() == ISD::UNDEF) {
5474 RawMask.push_back((uint64_t)SM_SentinelUndef);
5477 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5480 APInt MaskElement = CN->getAPIntValue();
5482 // We now have to decode the element which could be any integer size and
5483 // extract each byte of it.
5484 for (int j = 0; j < NumBytesPerElement; ++j) {
5485 // Note that this is x86 and so always little endian: the low byte is
5486 // the first byte of the mask.
5487 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5488 MaskElement = MaskElement.lshr(8);
5491 DecodePSHUFBMask(RawMask, Mask);
5495 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5499 SDValue Ptr = MaskLoad->getBasePtr();
5500 if (Ptr->getOpcode() == X86ISD::Wrapper)
5501 Ptr = Ptr->getOperand(0);
5503 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5504 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5507 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5508 DecodePSHUFBMask(C, Mask);
5514 case X86ISD::VPERMI:
5515 ImmN = N->getOperand(N->getNumOperands()-1);
5516 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5520 case X86ISD::MOVSD: {
5521 // The index 0 always comes from the first element of the second source,
5522 // this is why MOVSS and MOVSD are used in the first place. The other
5523 // elements come from the other positions of the first source vector
5524 Mask.push_back(NumElems);
5525 for (unsigned i = 1; i != NumElems; ++i) {
5530 case X86ISD::VPERM2X128:
5531 ImmN = N->getOperand(N->getNumOperands()-1);
5532 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5533 if (Mask.empty()) return false;
5535 case X86ISD::MOVSLDUP:
5536 DecodeMOVSLDUPMask(VT, Mask);
5539 case X86ISD::MOVSHDUP:
5540 DecodeMOVSHDUPMask(VT, Mask);
5543 case X86ISD::MOVDDUP:
5544 DecodeMOVDDUPMask(VT, Mask);
5547 case X86ISD::MOVLHPD:
5548 case X86ISD::MOVLPD:
5549 case X86ISD::MOVLPS:
5550 // Not yet implemented
5552 default: llvm_unreachable("unknown target shuffle node");
5555 // If we have a fake unary shuffle, the shuffle mask is spread across two
5556 // inputs that are actually the same node. Re-map the mask to always point
5557 // into the first input.
5560 if (M >= (int)Mask.size())
5566 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5567 /// element of the result of the vector shuffle.
5568 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5571 return SDValue(); // Limit search depth.
5573 SDValue V = SDValue(N, 0);
5574 EVT VT = V.getValueType();
5575 unsigned Opcode = V.getOpcode();
5577 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5578 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5579 int Elt = SV->getMaskElt(Index);
5582 return DAG.getUNDEF(VT.getVectorElementType());
5584 unsigned NumElems = VT.getVectorNumElements();
5585 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5586 : SV->getOperand(1);
5587 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5590 // Recurse into target specific vector shuffles to find scalars.
5591 if (isTargetShuffle(Opcode)) {
5592 MVT ShufVT = V.getSimpleValueType();
5593 unsigned NumElems = ShufVT.getVectorNumElements();
5594 SmallVector<int, 16> ShuffleMask;
5597 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5600 int Elt = ShuffleMask[Index];
5602 return DAG.getUNDEF(ShufVT.getVectorElementType());
5604 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5606 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5610 // Actual nodes that may contain scalar elements
5611 if (Opcode == ISD::BITCAST) {
5612 V = V.getOperand(0);
5613 EVT SrcVT = V.getValueType();
5614 unsigned NumElems = VT.getVectorNumElements();
5616 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5620 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5621 return (Index == 0) ? V.getOperand(0)
5622 : DAG.getUNDEF(VT.getVectorElementType());
5624 if (V.getOpcode() == ISD::BUILD_VECTOR)
5625 return V.getOperand(Index);
5630 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5631 /// shuffle operation which come from a consecutively from a zero. The
5632 /// search can start in two different directions, from left or right.
5633 /// We count undefs as zeros until PreferredNum is reached.
5634 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5635 unsigned NumElems, bool ZerosFromLeft,
5637 unsigned PreferredNum = -1U) {
5638 unsigned NumZeros = 0;
5639 for (unsigned i = 0; i != NumElems; ++i) {
5640 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5641 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5645 if (X86::isZeroNode(Elt))
5647 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5648 NumZeros = std::min(NumZeros + 1, PreferredNum);
5656 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5657 /// correspond consecutively to elements from one of the vector operands,
5658 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5660 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5661 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5662 unsigned NumElems, unsigned &OpNum) {
5663 bool SeenV1 = false;
5664 bool SeenV2 = false;
5666 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5667 int Idx = SVOp->getMaskElt(i);
5668 // Ignore undef indicies
5672 if (Idx < (int)NumElems)
5677 // Only accept consecutive elements from the same vector
5678 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5682 OpNum = SeenV1 ? 0 : 1;
5686 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5687 /// logical left shift of a vector.
5688 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5689 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5691 SVOp->getSimpleValueType(0).getVectorNumElements();
5692 unsigned NumZeros = getNumOfConsecutiveZeros(
5693 SVOp, NumElems, false /* check zeros from right */, DAG,
5694 SVOp->getMaskElt(0));
5700 // Considering the elements in the mask that are not consecutive zeros,
5701 // check if they consecutively come from only one of the source vectors.
5703 // V1 = {X, A, B, C} 0
5705 // vector_shuffle V1, V2 <1, 2, 3, X>
5707 if (!isShuffleMaskConsecutive(SVOp,
5708 0, // Mask Start Index
5709 NumElems-NumZeros, // Mask End Index(exclusive)
5710 NumZeros, // Where to start looking in the src vector
5711 NumElems, // Number of elements in vector
5712 OpSrc)) // Which source operand ?
5717 ShVal = SVOp->getOperand(OpSrc);
5721 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5722 /// logical left shift of a vector.
5723 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5724 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5726 SVOp->getSimpleValueType(0).getVectorNumElements();
5727 unsigned NumZeros = getNumOfConsecutiveZeros(
5728 SVOp, NumElems, true /* check zeros from left */, DAG,
5729 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5735 // Considering the elements in the mask that are not consecutive zeros,
5736 // check if they consecutively come from only one of the source vectors.
5738 // 0 { A, B, X, X } = V2
5740 // vector_shuffle V1, V2 <X, X, 4, 5>
5742 if (!isShuffleMaskConsecutive(SVOp,
5743 NumZeros, // Mask Start Index
5744 NumElems, // Mask End Index(exclusive)
5745 0, // Where to start looking in the src vector
5746 NumElems, // Number of elements in vector
5747 OpSrc)) // Which source operand ?
5752 ShVal = SVOp->getOperand(OpSrc);
5756 /// isVectorShift - Returns true if the shuffle can be implemented as a
5757 /// logical left or right shift of a vector.
5758 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5759 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5760 // Although the logic below support any bitwidth size, there are no
5761 // shift instructions which handle more than 128-bit vectors.
5762 if (!SVOp->getSimpleValueType(0).is128BitVector())
5765 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5766 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5772 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5774 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5775 unsigned NumNonZero, unsigned NumZero,
5777 const X86Subtarget* Subtarget,
5778 const TargetLowering &TLI) {
5785 for (unsigned i = 0; i < 16; ++i) {
5786 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5787 if (ThisIsNonZero && First) {
5789 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5791 V = DAG.getUNDEF(MVT::v8i16);
5796 SDValue ThisElt, LastElt;
5797 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5798 if (LastIsNonZero) {
5799 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5800 MVT::i16, Op.getOperand(i-1));
5802 if (ThisIsNonZero) {
5803 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5804 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5805 ThisElt, DAG.getConstant(8, MVT::i8));
5807 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5811 if (ThisElt.getNode())
5812 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5813 DAG.getIntPtrConstant(i/2));
5817 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5820 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5822 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5823 unsigned NumNonZero, unsigned NumZero,
5825 const X86Subtarget* Subtarget,
5826 const TargetLowering &TLI) {
5833 for (unsigned i = 0; i < 8; ++i) {
5834 bool isNonZero = (NonZeros & (1 << i)) != 0;
5838 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5840 V = DAG.getUNDEF(MVT::v8i16);
5843 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5844 MVT::v8i16, V, Op.getOperand(i),
5845 DAG.getIntPtrConstant(i));
5852 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5853 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5854 const X86Subtarget *Subtarget,
5855 const TargetLowering &TLI) {
5856 // Find all zeroable elements.
5858 for (int i=0; i < 4; ++i) {
5859 SDValue Elt = Op->getOperand(i);
5860 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5862 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5863 [](bool M) { return !M; }) > 1 &&
5864 "We expect at least two non-zero elements!");
5866 // We only know how to deal with build_vector nodes where elements are either
5867 // zeroable or extract_vector_elt with constant index.
5868 SDValue FirstNonZero;
5869 unsigned FirstNonZeroIdx;
5870 for (unsigned i=0; i < 4; ++i) {
5873 SDValue Elt = Op->getOperand(i);
5874 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5875 !isa<ConstantSDNode>(Elt.getOperand(1)))
5877 // Make sure that this node is extracting from a 128-bit vector.
5878 MVT VT = Elt.getOperand(0).getSimpleValueType();
5879 if (!VT.is128BitVector())
5881 if (!FirstNonZero.getNode()) {
5883 FirstNonZeroIdx = i;
5887 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5888 SDValue V1 = FirstNonZero.getOperand(0);
5889 MVT VT = V1.getSimpleValueType();
5891 // See if this build_vector can be lowered as a blend with zero.
5893 unsigned EltMaskIdx, EltIdx;
5895 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5896 if (Zeroable[EltIdx]) {
5897 // The zero vector will be on the right hand side.
5898 Mask[EltIdx] = EltIdx+4;
5902 Elt = Op->getOperand(EltIdx);
5903 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5904 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5905 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5907 Mask[EltIdx] = EltIdx;
5911 // Let the shuffle legalizer deal with blend operations.
5912 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5913 if (V1.getSimpleValueType() != VT)
5914 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5915 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5918 // See if we can lower this build_vector to a INSERTPS.
5919 if (!Subtarget->hasSSE41())
5922 SDValue V2 = Elt.getOperand(0);
5923 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5926 bool CanFold = true;
5927 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5931 SDValue Current = Op->getOperand(i);
5932 SDValue SrcVector = Current->getOperand(0);
5935 CanFold = SrcVector == V1 &&
5936 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5942 assert(V1.getNode() && "Expected at least two non-zero elements!");
5943 if (V1.getSimpleValueType() != MVT::v4f32)
5944 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5945 if (V2.getSimpleValueType() != MVT::v4f32)
5946 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5948 // Ok, we can emit an INSERTPS instruction.
5950 for (int i = 0; i < 4; ++i)
5954 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5955 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5956 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5957 DAG.getIntPtrConstant(InsertPSMask));
5958 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5961 /// getVShift - Return a vector logical shift node.
5963 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5964 unsigned NumBits, SelectionDAG &DAG,
5965 const TargetLowering &TLI, SDLoc dl) {
5966 assert(VT.is128BitVector() && "Unknown type for VShift");
5967 EVT ShVT = MVT::v2i64;
5968 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5969 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5970 return DAG.getNode(ISD::BITCAST, dl, VT,
5971 DAG.getNode(Opc, dl, ShVT, SrcOp,
5972 DAG.getConstant(NumBits,
5973 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5977 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5979 // Check if the scalar load can be widened into a vector load. And if
5980 // the address is "base + cst" see if the cst can be "absorbed" into
5981 // the shuffle mask.
5982 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5983 SDValue Ptr = LD->getBasePtr();
5984 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5986 EVT PVT = LD->getValueType(0);
5987 if (PVT != MVT::i32 && PVT != MVT::f32)
5992 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5993 FI = FINode->getIndex();
5995 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5996 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5997 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5998 Offset = Ptr.getConstantOperandVal(1);
5999 Ptr = Ptr.getOperand(0);
6004 // FIXME: 256-bit vector instructions don't require a strict alignment,
6005 // improve this code to support it better.
6006 unsigned RequiredAlign = VT.getSizeInBits()/8;
6007 SDValue Chain = LD->getChain();
6008 // Make sure the stack object alignment is at least 16 or 32.
6009 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6010 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
6011 if (MFI->isFixedObjectIndex(FI)) {
6012 // Can't change the alignment. FIXME: It's possible to compute
6013 // the exact stack offset and reference FI + adjust offset instead.
6014 // If someone *really* cares about this. That's the way to implement it.
6017 MFI->setObjectAlignment(FI, RequiredAlign);
6021 // (Offset % 16 or 32) must be multiple of 4. Then address is then
6022 // Ptr + (Offset & ~15).
6025 if ((Offset % RequiredAlign) & 3)
6027 int64_t StartOffset = Offset & ~(RequiredAlign-1);
6029 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
6030 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
6032 int EltNo = (Offset - StartOffset) >> 2;
6033 unsigned NumElems = VT.getVectorNumElements();
6035 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
6036 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
6037 LD->getPointerInfo().getWithOffset(StartOffset),
6038 false, false, false, 0);
6040 SmallVector<int, 8> Mask;
6041 for (unsigned i = 0; i != NumElems; ++i)
6042 Mask.push_back(EltNo);
6044 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
6050 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
6051 /// vector of type 'VT', see if the elements can be replaced by a single large
6052 /// load which has the same value as a build_vector whose operands are 'elts'.
6054 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6056 /// FIXME: we'd also like to handle the case where the last elements are zero
6057 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6058 /// There's even a handy isZeroNode for that purpose.
6059 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6060 SDLoc &DL, SelectionDAG &DAG,
6061 bool isAfterLegalize) {
6062 EVT EltVT = VT.getVectorElementType();
6063 unsigned NumElems = Elts.size();
6065 LoadSDNode *LDBase = nullptr;
6066 unsigned LastLoadedElt = -1U;
6068 // For each element in the initializer, see if we've found a load or an undef.
6069 // If we don't find an initial load element, or later load elements are
6070 // non-consecutive, bail out.
6071 for (unsigned i = 0; i < NumElems; ++i) {
6072 SDValue Elt = Elts[i];
6074 if (!Elt.getNode() ||
6075 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6078 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6080 LDBase = cast<LoadSDNode>(Elt.getNode());
6084 if (Elt.getOpcode() == ISD::UNDEF)
6087 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6088 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6093 // If we have found an entire vector of loads and undefs, then return a large
6094 // load of the entire vector width starting at the base pointer. If we found
6095 // consecutive loads for the low half, generate a vzext_load node.
6096 if (LastLoadedElt == NumElems - 1) {
6098 if (isAfterLegalize &&
6099 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6102 SDValue NewLd = SDValue();
6104 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6105 LDBase->getPointerInfo(), LDBase->isVolatile(),
6106 LDBase->isNonTemporal(), LDBase->isInvariant(),
6107 LDBase->getAlignment());
6109 if (LDBase->hasAnyUseOfValue(1)) {
6110 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6112 SDValue(NewLd.getNode(), 1));
6113 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6114 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6115 SDValue(NewLd.getNode(), 1));
6121 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6122 //of a v4i32 / v4f32. It's probably worth generalizing.
6123 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6124 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6125 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6126 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6128 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6129 LDBase->getPointerInfo(),
6130 LDBase->getAlignment(),
6131 false/*isVolatile*/, true/*ReadMem*/,
6134 // Make sure the newly-created LOAD is in the same position as LDBase in
6135 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6136 // update uses of LDBase's output chain to use the TokenFactor.
6137 if (LDBase->hasAnyUseOfValue(1)) {
6138 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6139 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6140 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6141 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6142 SDValue(ResNode.getNode(), 1));
6145 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6150 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6151 /// to generate a splat value for the following cases:
6152 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6153 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6154 /// a scalar load, or a constant.
6155 /// The VBROADCAST node is returned when a pattern is found,
6156 /// or SDValue() otherwise.
6157 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6158 SelectionDAG &DAG) {
6159 // VBROADCAST requires AVX.
6160 // TODO: Splats could be generated for non-AVX CPUs using SSE
6161 // instructions, but there's less potential gain for only 128-bit vectors.
6162 if (!Subtarget->hasAVX())
6165 MVT VT = Op.getSimpleValueType();
6168 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6169 "Unsupported vector type for broadcast.");
6174 switch (Op.getOpcode()) {
6176 // Unknown pattern found.
6179 case ISD::BUILD_VECTOR: {
6180 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6181 BitVector UndefElements;
6182 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6184 // We need a splat of a single value to use broadcast, and it doesn't
6185 // make any sense if the value is only in one element of the vector.
6186 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6190 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6191 Ld.getOpcode() == ISD::ConstantFP);
6193 // Make sure that all of the users of a non-constant load are from the
6194 // BUILD_VECTOR node.
6195 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6200 case ISD::VECTOR_SHUFFLE: {
6201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6203 // Shuffles must have a splat mask where the first element is
6205 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6208 SDValue Sc = Op.getOperand(0);
6209 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6210 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6212 if (!Subtarget->hasInt256())
6215 // Use the register form of the broadcast instruction available on AVX2.
6216 if (VT.getSizeInBits() >= 256)
6217 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6218 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6221 Ld = Sc.getOperand(0);
6222 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6223 Ld.getOpcode() == ISD::ConstantFP);
6225 // The scalar_to_vector node and the suspected
6226 // load node must have exactly one user.
6227 // Constants may have multiple users.
6229 // AVX-512 has register version of the broadcast
6230 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6231 Ld.getValueType().getSizeInBits() >= 32;
6232 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6239 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6240 bool IsGE256 = (VT.getSizeInBits() >= 256);
6242 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6243 // instruction to save 8 or more bytes of constant pool data.
6244 // TODO: If multiple splats are generated to load the same constant,
6245 // it may be detrimental to overall size. There needs to be a way to detect
6246 // that condition to know if this is truly a size win.
6247 const Function *F = DAG.getMachineFunction().getFunction();
6248 bool OptForSize = F->getAttributes().
6249 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6251 // Handle broadcasting a single constant scalar from the constant pool
6253 // On Sandybridge (no AVX2), it is still better to load a constant vector
6254 // from the constant pool and not to broadcast it from a scalar.
6255 // But override that restriction when optimizing for size.
6256 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6257 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6258 EVT CVT = Ld.getValueType();
6259 assert(!CVT.isVector() && "Must not broadcast a vector type");
6261 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6262 // For size optimization, also splat v2f64 and v2i64, and for size opt
6263 // with AVX2, also splat i8 and i16.
6264 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6265 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6266 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6267 const Constant *C = nullptr;
6268 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6269 C = CI->getConstantIntValue();
6270 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6271 C = CF->getConstantFPValue();
6273 assert(C && "Invalid constant type");
6275 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6276 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6277 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6278 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6279 MachinePointerInfo::getConstantPool(),
6280 false, false, false, Alignment);
6282 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6286 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6288 // Handle AVX2 in-register broadcasts.
6289 if (!IsLoad && Subtarget->hasInt256() &&
6290 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6291 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6293 // The scalar source must be a normal load.
6297 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6298 (Subtarget->hasVLX() && ScalarSize == 64))
6299 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6301 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6302 // double since there is no vbroadcastsd xmm
6303 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6304 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6305 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6308 // Unsupported broadcast.
6312 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6313 /// underlying vector and index.
6315 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6317 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6319 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6320 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6323 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6325 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6327 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6328 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6331 // In this case the vector is the extract_subvector expression and the index
6332 // is 2, as specified by the shuffle.
6333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6334 SDValue ShuffleVec = SVOp->getOperand(0);
6335 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6336 assert(ShuffleVecVT.getVectorElementType() ==
6337 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6339 int ShuffleIdx = SVOp->getMaskElt(Idx);
6340 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6341 ExtractedFromVec = ShuffleVec;
6347 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6348 MVT VT = Op.getSimpleValueType();
6350 // Skip if insert_vec_elt is not supported.
6351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6352 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6356 unsigned NumElems = Op.getNumOperands();
6360 SmallVector<unsigned, 4> InsertIndices;
6361 SmallVector<int, 8> Mask(NumElems, -1);
6363 for (unsigned i = 0; i != NumElems; ++i) {
6364 unsigned Opc = Op.getOperand(i).getOpcode();
6366 if (Opc == ISD::UNDEF)
6369 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6370 // Quit if more than 1 elements need inserting.
6371 if (InsertIndices.size() > 1)
6374 InsertIndices.push_back(i);
6378 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6379 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6380 // Quit if non-constant index.
6381 if (!isa<ConstantSDNode>(ExtIdx))
6383 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6385 // Quit if extracted from vector of different type.
6386 if (ExtractedFromVec.getValueType() != VT)
6389 if (!VecIn1.getNode())
6390 VecIn1 = ExtractedFromVec;
6391 else if (VecIn1 != ExtractedFromVec) {
6392 if (!VecIn2.getNode())
6393 VecIn2 = ExtractedFromVec;
6394 else if (VecIn2 != ExtractedFromVec)
6395 // Quit if more than 2 vectors to shuffle
6399 if (ExtractedFromVec == VecIn1)
6401 else if (ExtractedFromVec == VecIn2)
6402 Mask[i] = Idx + NumElems;
6405 if (!VecIn1.getNode())
6408 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6409 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6410 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6411 unsigned Idx = InsertIndices[i];
6412 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6413 DAG.getIntPtrConstant(Idx));
6419 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6421 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6423 MVT VT = Op.getSimpleValueType();
6424 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6425 "Unexpected type in LowerBUILD_VECTORvXi1!");
6428 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6429 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6430 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6431 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6434 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6435 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6436 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6437 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6440 bool AllContants = true;
6441 uint64_t Immediate = 0;
6442 int NonConstIdx = -1;
6443 bool IsSplat = true;
6444 unsigned NumNonConsts = 0;
6445 unsigned NumConsts = 0;
6446 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6447 SDValue In = Op.getOperand(idx);
6448 if (In.getOpcode() == ISD::UNDEF)
6450 if (!isa<ConstantSDNode>(In)) {
6451 AllContants = false;
6456 if (cast<ConstantSDNode>(In)->getZExtValue())
6457 Immediate |= (1ULL << idx);
6459 if (In != Op.getOperand(0))
6464 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6465 DAG.getConstant(Immediate, MVT::i16));
6466 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6467 DAG.getIntPtrConstant(0));
6470 if (NumNonConsts == 1 && NonConstIdx != 0) {
6473 SDValue VecAsImm = DAG.getConstant(Immediate,
6474 MVT::getIntegerVT(VT.getSizeInBits()));
6475 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6478 DstVec = DAG.getUNDEF(VT);
6479 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6480 Op.getOperand(NonConstIdx),
6481 DAG.getIntPtrConstant(NonConstIdx));
6483 if (!IsSplat && (NonConstIdx != 0))
6484 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6485 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6488 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6489 DAG.getConstant(-1, SelectVT),
6490 DAG.getConstant(0, SelectVT));
6492 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6493 DAG.getConstant((Immediate | 1), SelectVT),
6494 DAG.getConstant(Immediate, SelectVT));
6495 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6498 /// \brief Return true if \p N implements a horizontal binop and return the
6499 /// operands for the horizontal binop into V0 and V1.
6501 /// This is a helper function of PerformBUILD_VECTORCombine.
6502 /// This function checks that the build_vector \p N in input implements a
6503 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6504 /// operation to match.
6505 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6506 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6507 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6510 /// This function only analyzes elements of \p N whose indices are
6511 /// in range [BaseIdx, LastIdx).
6512 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6514 unsigned BaseIdx, unsigned LastIdx,
6515 SDValue &V0, SDValue &V1) {
6516 EVT VT = N->getValueType(0);
6518 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6519 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6520 "Invalid Vector in input!");
6522 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6523 bool CanFold = true;
6524 unsigned ExpectedVExtractIdx = BaseIdx;
6525 unsigned NumElts = LastIdx - BaseIdx;
6526 V0 = DAG.getUNDEF(VT);
6527 V1 = DAG.getUNDEF(VT);
6529 // Check if N implements a horizontal binop.
6530 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6531 SDValue Op = N->getOperand(i + BaseIdx);
6534 if (Op->getOpcode() == ISD::UNDEF) {
6535 // Update the expected vector extract index.
6536 if (i * 2 == NumElts)
6537 ExpectedVExtractIdx = BaseIdx;
6538 ExpectedVExtractIdx += 2;
6542 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6547 SDValue Op0 = Op.getOperand(0);
6548 SDValue Op1 = Op.getOperand(1);
6550 // Try to match the following pattern:
6551 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6552 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6553 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6554 Op0.getOperand(0) == Op1.getOperand(0) &&
6555 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6556 isa<ConstantSDNode>(Op1.getOperand(1)));
6560 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6563 if (i * 2 < NumElts) {
6564 if (V0.getOpcode() == ISD::UNDEF)
6565 V0 = Op0.getOperand(0);
6567 if (V1.getOpcode() == ISD::UNDEF)
6568 V1 = Op0.getOperand(0);
6569 if (i * 2 == NumElts)
6570 ExpectedVExtractIdx = BaseIdx;
6573 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6574 if (I0 == ExpectedVExtractIdx)
6575 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6576 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6577 // Try to match the following dag sequence:
6578 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6579 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6583 ExpectedVExtractIdx += 2;
6589 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6590 /// a concat_vector.
6592 /// This is a helper function of PerformBUILD_VECTORCombine.
6593 /// This function expects two 256-bit vectors called V0 and V1.
6594 /// At first, each vector is split into two separate 128-bit vectors.
6595 /// Then, the resulting 128-bit vectors are used to implement two
6596 /// horizontal binary operations.
6598 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6600 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6601 /// the two new horizontal binop.
6602 /// When Mode is set, the first horizontal binop dag node would take as input
6603 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6604 /// horizontal binop dag node would take as input the lower 128-bit of V1
6605 /// and the upper 128-bit of V1.
6607 /// HADD V0_LO, V0_HI
6608 /// HADD V1_LO, V1_HI
6610 /// Otherwise, the first horizontal binop dag node takes as input the lower
6611 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6612 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6614 /// HADD V0_LO, V1_LO
6615 /// HADD V0_HI, V1_HI
6617 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6618 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6619 /// the upper 128-bits of the result.
6620 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6621 SDLoc DL, SelectionDAG &DAG,
6622 unsigned X86Opcode, bool Mode,
6623 bool isUndefLO, bool isUndefHI) {
6624 EVT VT = V0.getValueType();
6625 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6626 "Invalid nodes in input!");
6628 unsigned NumElts = VT.getVectorNumElements();
6629 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6630 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6631 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6632 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6633 EVT NewVT = V0_LO.getValueType();
6635 SDValue LO = DAG.getUNDEF(NewVT);
6636 SDValue HI = DAG.getUNDEF(NewVT);
6639 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6640 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6641 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6642 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6643 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6645 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6646 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6647 V1_LO->getOpcode() != ISD::UNDEF))
6648 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6650 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6651 V1_HI->getOpcode() != ISD::UNDEF))
6652 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6655 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6658 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6659 /// sequence of 'vadd + vsub + blendi'.
6660 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6661 const X86Subtarget *Subtarget) {
6663 EVT VT = BV->getValueType(0);
6664 unsigned NumElts = VT.getVectorNumElements();
6665 SDValue InVec0 = DAG.getUNDEF(VT);
6666 SDValue InVec1 = DAG.getUNDEF(VT);
6668 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6669 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6671 // Odd-numbered elements in the input build vector are obtained from
6672 // adding two integer/float elements.
6673 // Even-numbered elements in the input build vector are obtained from
6674 // subtracting two integer/float elements.
6675 unsigned ExpectedOpcode = ISD::FSUB;
6676 unsigned NextExpectedOpcode = ISD::FADD;
6677 bool AddFound = false;
6678 bool SubFound = false;
6680 for (unsigned i = 0, e = NumElts; i != e; i++) {
6681 SDValue Op = BV->getOperand(i);
6683 // Skip 'undef' values.
6684 unsigned Opcode = Op.getOpcode();
6685 if (Opcode == ISD::UNDEF) {
6686 std::swap(ExpectedOpcode, NextExpectedOpcode);
6690 // Early exit if we found an unexpected opcode.
6691 if (Opcode != ExpectedOpcode)
6694 SDValue Op0 = Op.getOperand(0);
6695 SDValue Op1 = Op.getOperand(1);
6697 // Try to match the following pattern:
6698 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6699 // Early exit if we cannot match that sequence.
6700 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6701 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6702 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6703 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6704 Op0.getOperand(1) != Op1.getOperand(1))
6707 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6711 // We found a valid add/sub node. Update the information accordingly.
6717 // Update InVec0 and InVec1.
6718 if (InVec0.getOpcode() == ISD::UNDEF)
6719 InVec0 = Op0.getOperand(0);
6720 if (InVec1.getOpcode() == ISD::UNDEF)
6721 InVec1 = Op1.getOperand(0);
6723 // Make sure that operands in input to each add/sub node always
6724 // come from a same pair of vectors.
6725 if (InVec0 != Op0.getOperand(0)) {
6726 if (ExpectedOpcode == ISD::FSUB)
6729 // FADD is commutable. Try to commute the operands
6730 // and then test again.
6731 std::swap(Op0, Op1);
6732 if (InVec0 != Op0.getOperand(0))
6736 if (InVec1 != Op1.getOperand(0))
6739 // Update the pair of expected opcodes.
6740 std::swap(ExpectedOpcode, NextExpectedOpcode);
6743 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6744 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6745 InVec1.getOpcode() != ISD::UNDEF)
6746 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6751 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6752 const X86Subtarget *Subtarget) {
6754 EVT VT = N->getValueType(0);
6755 unsigned NumElts = VT.getVectorNumElements();
6756 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6757 SDValue InVec0, InVec1;
6759 // Try to match an ADDSUB.
6760 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6761 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6762 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6763 if (Value.getNode())
6767 // Try to match horizontal ADD/SUB.
6768 unsigned NumUndefsLO = 0;
6769 unsigned NumUndefsHI = 0;
6770 unsigned Half = NumElts/2;
6772 // Count the number of UNDEF operands in the build_vector in input.
6773 for (unsigned i = 0, e = Half; i != e; ++i)
6774 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6777 for (unsigned i = Half, e = NumElts; i != e; ++i)
6778 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6781 // Early exit if this is either a build_vector of all UNDEFs or all the
6782 // operands but one are UNDEF.
6783 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6786 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6787 // Try to match an SSE3 float HADD/HSUB.
6788 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6789 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6791 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6792 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6793 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6794 // Try to match an SSSE3 integer HADD/HSUB.
6795 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6796 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6798 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6799 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6802 if (!Subtarget->hasAVX())
6805 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6806 // Try to match an AVX horizontal add/sub of packed single/double
6807 // precision floating point values from 256-bit vectors.
6808 SDValue InVec2, InVec3;
6809 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6810 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6811 ((InVec0.getOpcode() == ISD::UNDEF ||
6812 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6813 ((InVec1.getOpcode() == ISD::UNDEF ||
6814 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6815 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6817 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6818 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6819 ((InVec0.getOpcode() == ISD::UNDEF ||
6820 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6821 ((InVec1.getOpcode() == ISD::UNDEF ||
6822 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6823 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6824 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6825 // Try to match an AVX2 horizontal add/sub of signed integers.
6826 SDValue InVec2, InVec3;
6828 bool CanFold = true;
6830 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6831 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6832 ((InVec0.getOpcode() == ISD::UNDEF ||
6833 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6834 ((InVec1.getOpcode() == ISD::UNDEF ||
6835 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6836 X86Opcode = X86ISD::HADD;
6837 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6838 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6839 ((InVec0.getOpcode() == ISD::UNDEF ||
6840 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6841 ((InVec1.getOpcode() == ISD::UNDEF ||
6842 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6843 X86Opcode = X86ISD::HSUB;
6848 // Fold this build_vector into a single horizontal add/sub.
6849 // Do this only if the target has AVX2.
6850 if (Subtarget->hasAVX2())
6851 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6853 // Do not try to expand this build_vector into a pair of horizontal
6854 // add/sub if we can emit a pair of scalar add/sub.
6855 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6858 // Convert this build_vector into a pair of horizontal binop followed by
6860 bool isUndefLO = NumUndefsLO == Half;
6861 bool isUndefHI = NumUndefsHI == Half;
6862 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6863 isUndefLO, isUndefHI);
6867 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6868 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6870 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6871 X86Opcode = X86ISD::HADD;
6872 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6873 X86Opcode = X86ISD::HSUB;
6874 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6875 X86Opcode = X86ISD::FHADD;
6876 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6877 X86Opcode = X86ISD::FHSUB;
6881 // Don't try to expand this build_vector into a pair of horizontal add/sub
6882 // if we can simply emit a pair of scalar add/sub.
6883 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6886 // Convert this build_vector into two horizontal add/sub followed by
6888 bool isUndefLO = NumUndefsLO == Half;
6889 bool isUndefHI = NumUndefsHI == Half;
6890 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6891 isUndefLO, isUndefHI);
6898 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6901 MVT VT = Op.getSimpleValueType();
6902 MVT ExtVT = VT.getVectorElementType();
6903 unsigned NumElems = Op.getNumOperands();
6905 // Generate vectors for predicate vectors.
6906 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6907 return LowerBUILD_VECTORvXi1(Op, DAG);
6909 // Vectors containing all zeros can be matched by pxor and xorps later
6910 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6911 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6912 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6913 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6916 return getZeroVector(VT, Subtarget, DAG, dl);
6919 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6920 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6921 // vpcmpeqd on 256-bit vectors.
6922 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6923 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6926 if (!VT.is512BitVector())
6927 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6930 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6931 if (Broadcast.getNode())
6934 unsigned EVTBits = ExtVT.getSizeInBits();
6936 unsigned NumZero = 0;
6937 unsigned NumNonZero = 0;
6938 unsigned NonZeros = 0;
6939 bool IsAllConstants = true;
6940 SmallSet<SDValue, 8> Values;
6941 for (unsigned i = 0; i < NumElems; ++i) {
6942 SDValue Elt = Op.getOperand(i);
6943 if (Elt.getOpcode() == ISD::UNDEF)
6946 if (Elt.getOpcode() != ISD::Constant &&
6947 Elt.getOpcode() != ISD::ConstantFP)
6948 IsAllConstants = false;
6949 if (X86::isZeroNode(Elt))
6952 NonZeros |= (1 << i);
6957 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6958 if (NumNonZero == 0)
6959 return DAG.getUNDEF(VT);
6961 // Special case for single non-zero, non-undef, element.
6962 if (NumNonZero == 1) {
6963 unsigned Idx = countTrailingZeros(NonZeros);
6964 SDValue Item = Op.getOperand(Idx);
6966 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6967 // the value are obviously zero, truncate the value to i32 and do the
6968 // insertion that way. Only do this if the value is non-constant or if the
6969 // value is a constant being inserted into element 0. It is cheaper to do
6970 // a constant pool load than it is to do a movd + shuffle.
6971 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6972 (!IsAllConstants || Idx == 0)) {
6973 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6975 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6976 EVT VecVT = MVT::v4i32;
6977 unsigned VecElts = 4;
6979 // Truncate the value (which may itself be a constant) to i32, and
6980 // convert it to a vector with movd (S2V+shuffle to zero extend).
6981 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6982 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6984 // If using the new shuffle lowering, just directly insert this.
6985 if (ExperimentalVectorShuffleLowering)
6987 ISD::BITCAST, dl, VT,
6988 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6990 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6992 // Now we have our 32-bit value zero extended in the low element of
6993 // a vector. If Idx != 0, swizzle it into place.
6995 SmallVector<int, 4> Mask;
6996 Mask.push_back(Idx);
6997 for (unsigned i = 1; i != VecElts; ++i)
6999 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
7002 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
7006 // If we have a constant or non-constant insertion into the low element of
7007 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
7008 // the rest of the elements. This will be matched as movd/movq/movss/movsd
7009 // depending on what the source datatype is.
7012 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7014 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
7015 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
7016 if (VT.is256BitVector() || VT.is512BitVector()) {
7017 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
7018 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
7019 Item, DAG.getIntPtrConstant(0));
7021 assert(VT.is128BitVector() && "Expected an SSE value type!");
7022 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7023 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
7024 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
7027 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
7028 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
7029 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
7030 if (VT.is256BitVector()) {
7031 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
7032 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
7034 assert(VT.is128BitVector() && "Expected an SSE value type!");
7035 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
7037 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
7041 // Is it a vector logical left shift?
7042 if (NumElems == 2 && Idx == 1 &&
7043 X86::isZeroNode(Op.getOperand(0)) &&
7044 !X86::isZeroNode(Op.getOperand(1))) {
7045 unsigned NumBits = VT.getSizeInBits();
7046 return getVShift(true, VT,
7047 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7048 VT, Op.getOperand(1)),
7049 NumBits/2, DAG, *this, dl);
7052 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7055 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7056 // is a non-constant being inserted into an element other than the low one,
7057 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7058 // movd/movss) to move this into the low element, then shuffle it into
7060 if (EVTBits == 32) {
7061 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7063 // If using the new shuffle lowering, just directly insert this.
7064 if (ExperimentalVectorShuffleLowering)
7065 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7067 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7068 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7069 SmallVector<int, 8> MaskVec;
7070 for (unsigned i = 0; i != NumElems; ++i)
7071 MaskVec.push_back(i == Idx ? 0 : 1);
7072 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7076 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7077 if (Values.size() == 1) {
7078 if (EVTBits == 32) {
7079 // Instead of a shuffle like this:
7080 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7081 // Check if it's possible to issue this instead.
7082 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7083 unsigned Idx = countTrailingZeros(NonZeros);
7084 SDValue Item = Op.getOperand(Idx);
7085 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7086 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7091 // A vector full of immediates; various special cases are already
7092 // handled, so this is best done with a single constant-pool load.
7096 // For AVX-length vectors, see if we can use a vector load to get all of the
7097 // elements, otherwise build the individual 128-bit pieces and use
7098 // shuffles to put them in place.
7099 if (VT.is256BitVector() || VT.is512BitVector()) {
7100 SmallVector<SDValue, 64> V;
7101 for (unsigned i = 0; i != NumElems; ++i)
7102 V.push_back(Op.getOperand(i));
7104 // Check for a build vector of consecutive loads.
7105 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7108 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7110 // Build both the lower and upper subvector.
7111 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7112 makeArrayRef(&V[0], NumElems/2));
7113 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7114 makeArrayRef(&V[NumElems / 2], NumElems/2));
7116 // Recreate the wider vector with the lower and upper part.
7117 if (VT.is256BitVector())
7118 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7119 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7122 // Let legalizer expand 2-wide build_vectors.
7123 if (EVTBits == 64) {
7124 if (NumNonZero == 1) {
7125 // One half is zero or undef.
7126 unsigned Idx = countTrailingZeros(NonZeros);
7127 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7128 Op.getOperand(Idx));
7129 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7134 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7135 if (EVTBits == 8 && NumElems == 16) {
7136 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7138 if (V.getNode()) return V;
7141 if (EVTBits == 16 && NumElems == 8) {
7142 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7144 if (V.getNode()) return V;
7147 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7148 if (EVTBits == 32 && NumElems == 4) {
7149 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7154 // If element VT is == 32 bits, turn it into a number of shuffles.
7155 SmallVector<SDValue, 8> V(NumElems);
7156 if (NumElems == 4 && NumZero > 0) {
7157 for (unsigned i = 0; i < 4; ++i) {
7158 bool isZero = !(NonZeros & (1 << i));
7160 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7162 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7165 for (unsigned i = 0; i < 2; ++i) {
7166 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7169 V[i] = V[i*2]; // Must be a zero vector.
7172 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7175 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7178 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7183 bool Reverse1 = (NonZeros & 0x3) == 2;
7184 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7188 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7189 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7191 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7194 if (Values.size() > 1 && VT.is128BitVector()) {
7195 // Check for a build vector of consecutive loads.
7196 for (unsigned i = 0; i < NumElems; ++i)
7197 V[i] = Op.getOperand(i);
7199 // Check for elements which are consecutive loads.
7200 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7204 // Check for a build vector from mostly shuffle plus few inserting.
7205 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7209 // For SSE 4.1, use insertps to put the high elements into the low element.
7210 if (getSubtarget()->hasSSE41()) {
7212 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7213 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7215 Result = DAG.getUNDEF(VT);
7217 for (unsigned i = 1; i < NumElems; ++i) {
7218 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7219 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7220 Op.getOperand(i), DAG.getIntPtrConstant(i));
7225 // Otherwise, expand into a number of unpckl*, start by extending each of
7226 // our (non-undef) elements to the full vector width with the element in the
7227 // bottom slot of the vector (which generates no code for SSE).
7228 for (unsigned i = 0; i < NumElems; ++i) {
7229 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7230 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7232 V[i] = DAG.getUNDEF(VT);
7235 // Next, we iteratively mix elements, e.g. for v4f32:
7236 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7237 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7238 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7239 unsigned EltStride = NumElems >> 1;
7240 while (EltStride != 0) {
7241 for (unsigned i = 0; i < EltStride; ++i) {
7242 // If V[i+EltStride] is undef and this is the first round of mixing,
7243 // then it is safe to just drop this shuffle: V[i] is already in the
7244 // right place, the one element (since it's the first round) being
7245 // inserted as undef can be dropped. This isn't safe for successive
7246 // rounds because they will permute elements within both vectors.
7247 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7248 EltStride == NumElems/2)
7251 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7260 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7261 // to create 256-bit vectors from two other 128-bit ones.
7262 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7264 MVT ResVT = Op.getSimpleValueType();
7266 assert((ResVT.is256BitVector() ||
7267 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7269 SDValue V1 = Op.getOperand(0);
7270 SDValue V2 = Op.getOperand(1);
7271 unsigned NumElems = ResVT.getVectorNumElements();
7272 if(ResVT.is256BitVector())
7273 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7275 if (Op.getNumOperands() == 4) {
7276 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7277 ResVT.getVectorNumElements()/2);
7278 SDValue V3 = Op.getOperand(2);
7279 SDValue V4 = Op.getOperand(3);
7280 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7281 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7283 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7286 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7287 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7288 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7289 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7290 Op.getNumOperands() == 4)));
7292 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7293 // from two other 128-bit ones.
7295 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7296 return LowerAVXCONCAT_VECTORS(Op, DAG);
7300 //===----------------------------------------------------------------------===//
7301 // Vector shuffle lowering
7303 // This is an experimental code path for lowering vector shuffles on x86. It is
7304 // designed to handle arbitrary vector shuffles and blends, gracefully
7305 // degrading performance as necessary. It works hard to recognize idiomatic
7306 // shuffles and lower them to optimal instruction patterns without leaving
7307 // a framework that allows reasonably efficient handling of all vector shuffle
7309 //===----------------------------------------------------------------------===//
7311 /// \brief Tiny helper function to identify a no-op mask.
7313 /// This is a somewhat boring predicate function. It checks whether the mask
7314 /// array input, which is assumed to be a single-input shuffle mask of the kind
7315 /// used by the X86 shuffle instructions (not a fully general
7316 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7317 /// in-place shuffle are 'no-op's.
7318 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7319 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7320 if (Mask[i] != -1 && Mask[i] != i)
7325 /// \brief Helper function to classify a mask as a single-input mask.
7327 /// This isn't a generic single-input test because in the vector shuffle
7328 /// lowering we canonicalize single inputs to be the first input operand. This
7329 /// means we can more quickly test for a single input by only checking whether
7330 /// an input from the second operand exists. We also assume that the size of
7331 /// mask corresponds to the size of the input vectors which isn't true in the
7332 /// fully general case.
7333 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7335 if (M >= (int)Mask.size())
7340 /// \brief Test whether there are elements crossing 128-bit lanes in this
7343 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7344 /// and we routinely test for these.
7345 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7346 int LaneSize = 128 / VT.getScalarSizeInBits();
7347 int Size = Mask.size();
7348 for (int i = 0; i < Size; ++i)
7349 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7354 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7356 /// This checks a shuffle mask to see if it is performing the same
7357 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7358 /// that it is also not lane-crossing. It may however involve a blend from the
7359 /// same lane of a second vector.
7361 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7362 /// non-trivial to compute in the face of undef lanes. The representation is
7363 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7364 /// entries from both V1 and V2 inputs to the wider mask.
7366 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7367 SmallVectorImpl<int> &RepeatedMask) {
7368 int LaneSize = 128 / VT.getScalarSizeInBits();
7369 RepeatedMask.resize(LaneSize, -1);
7370 int Size = Mask.size();
7371 for (int i = 0; i < Size; ++i) {
7374 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7375 // This entry crosses lanes, so there is no way to model this shuffle.
7378 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7379 if (RepeatedMask[i % LaneSize] == -1)
7380 // This is the first non-undef entry in this slot of a 128-bit lane.
7381 RepeatedMask[i % LaneSize] =
7382 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7383 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7384 // Found a mismatch with the repeated mask.
7390 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7391 // 2013 will allow us to use it as a non-type template parameter.
7394 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7396 /// See its documentation for details.
7397 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7398 if (Mask.size() != Args.size())
7400 for (int i = 0, e = Mask.size(); i < e; ++i) {
7401 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7402 if (Mask[i] != -1 && Mask[i] != *Args[i])
7410 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7413 /// This is a fast way to test a shuffle mask against a fixed pattern:
7415 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7417 /// It returns true if the mask is exactly as wide as the argument list, and
7418 /// each element of the mask is either -1 (signifying undef) or the value given
7419 /// in the argument.
7420 static const VariadicFunction1<
7421 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7423 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7425 /// This helper function produces an 8-bit shuffle immediate corresponding to
7426 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7427 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7430 /// NB: We rely heavily on "undef" masks preserving the input lane.
7431 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7432 SelectionDAG &DAG) {
7433 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7434 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7435 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7436 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7437 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7440 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7441 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7442 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7443 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7444 return DAG.getConstant(Imm, MVT::i8);
7447 /// \brief Try to emit a blend instruction for a shuffle.
7449 /// This doesn't do any checks for the availability of instructions for blending
7450 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7451 /// be matched in the backend with the type given. What it does check for is
7452 /// that the shuffle mask is in fact a blend.
7453 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7454 SDValue V2, ArrayRef<int> Mask,
7455 const X86Subtarget *Subtarget,
7456 SelectionDAG &DAG) {
7458 unsigned BlendMask = 0;
7459 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7460 if (Mask[i] >= Size) {
7461 if (Mask[i] != i + Size)
7462 return SDValue(); // Shuffled V2 input!
7463 BlendMask |= 1u << i;
7466 if (Mask[i] >= 0 && Mask[i] != i)
7467 return SDValue(); // Shuffled V1 input!
7469 switch (VT.SimpleTy) {
7474 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7475 DAG.getConstant(BlendMask, MVT::i8));
7479 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7483 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7484 // that instruction.
7485 if (Subtarget->hasAVX2()) {
7486 // Scale the blend by the number of 32-bit dwords per element.
7487 int Scale = VT.getScalarSizeInBits() / 32;
7489 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7490 if (Mask[i] >= Size)
7491 for (int j = 0; j < Scale; ++j)
7492 BlendMask |= 1u << (i * Scale + j);
7494 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7495 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7496 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7497 return DAG.getNode(ISD::BITCAST, DL, VT,
7498 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7499 DAG.getConstant(BlendMask, MVT::i8)));
7503 // For integer shuffles we need to expand the mask and cast the inputs to
7504 // v8i16s prior to blending.
7505 int Scale = 8 / VT.getVectorNumElements();
7507 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7508 if (Mask[i] >= Size)
7509 for (int j = 0; j < Scale; ++j)
7510 BlendMask |= 1u << (i * Scale + j);
7512 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7513 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7514 return DAG.getNode(ISD::BITCAST, DL, VT,
7515 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7516 DAG.getConstant(BlendMask, MVT::i8)));
7520 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7521 SmallVector<int, 8> RepeatedMask;
7522 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7523 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7524 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7526 for (int i = 0; i < 8; ++i)
7527 if (RepeatedMask[i] >= 16)
7528 BlendMask |= 1u << i;
7529 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7530 DAG.getConstant(BlendMask, MVT::i8));
7535 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7536 // Scale the blend by the number of bytes per element.
7537 int Scale = VT.getScalarSizeInBits() / 8;
7538 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7540 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7541 // mix of LLVM's code generator and the x86 backend. We tell the code
7542 // generator that boolean values in the elements of an x86 vector register
7543 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7544 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7545 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7546 // of the element (the remaining are ignored) and 0 in that high bit would
7547 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7548 // the LLVM model for boolean values in vector elements gets the relevant
7549 // bit set, it is set backwards and over constrained relative to x86's
7551 SDValue VSELECTMask[32];
7552 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7553 for (int j = 0; j < Scale; ++j)
7554 VSELECTMask[Scale * i + j] =
7555 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7556 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7558 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7559 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7561 ISD::BITCAST, DL, VT,
7562 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7563 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7568 llvm_unreachable("Not a supported integer vector type!");
7572 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7573 /// unblended shuffles followed by an unshuffled blend.
7575 /// This matches the extremely common pattern for handling combined
7576 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7578 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7582 SelectionDAG &DAG) {
7583 // Shuffle the input elements into the desired positions in V1 and V2 and
7584 // blend them together.
7585 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7586 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7587 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7588 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7589 if (Mask[i] >= 0 && Mask[i] < Size) {
7590 V1Mask[i] = Mask[i];
7592 } else if (Mask[i] >= Size) {
7593 V2Mask[i] = Mask[i] - Size;
7594 BlendMask[i] = i + Size;
7597 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7598 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7599 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7602 /// \brief Try to lower a vector shuffle as a byte rotation.
7604 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7605 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7606 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7607 /// try to generically lower a vector shuffle through such an pattern. It
7608 /// does not check for the profitability of lowering either as PALIGNR or
7609 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7610 /// This matches shuffle vectors that look like:
7612 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7614 /// Essentially it concatenates V1 and V2, shifts right by some number of
7615 /// elements, and takes the low elements as the result. Note that while this is
7616 /// specified as a *right shift* because x86 is little-endian, it is a *left
7617 /// rotate* of the vector lanes.
7619 /// Note that this only handles 128-bit vector widths currently.
7620 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7623 const X86Subtarget *Subtarget,
7624 SelectionDAG &DAG) {
7625 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7627 // We need to detect various ways of spelling a rotation:
7628 // [11, 12, 13, 14, 15, 0, 1, 2]
7629 // [-1, 12, 13, 14, -1, -1, 1, -1]
7630 // [-1, -1, -1, -1, -1, -1, 1, 2]
7631 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7632 // [-1, 4, 5, 6, -1, -1, 9, -1]
7633 // [-1, 4, 5, 6, -1, -1, -1, -1]
7636 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7639 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7641 // Based on the mod-Size value of this mask element determine where
7642 // a rotated vector would have started.
7643 int StartIdx = i - (Mask[i] % Size);
7645 // The identity rotation isn't interesting, stop.
7648 // If we found the tail of a vector the rotation must be the missing
7649 // front. If we found the head of a vector, it must be how much of the head.
7650 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7653 Rotation = CandidateRotation;
7654 else if (Rotation != CandidateRotation)
7655 // The rotations don't match, so we can't match this mask.
7658 // Compute which value this mask is pointing at.
7659 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7661 // Compute which of the two target values this index should be assigned to.
7662 // This reflects whether the high elements are remaining or the low elements
7664 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7666 // Either set up this value if we've not encountered it before, or check
7667 // that it remains consistent.
7670 else if (TargetV != MaskV)
7671 // This may be a rotation, but it pulls from the inputs in some
7672 // unsupported interleaving.
7676 // Check that we successfully analyzed the mask, and normalize the results.
7677 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7678 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7684 assert(VT.getSizeInBits() == 128 &&
7685 "Rotate-based lowering only supports 128-bit lowering!");
7686 assert(Mask.size() <= 16 &&
7687 "Can shuffle at most 16 bytes in a 128-bit vector!");
7689 // The actual rotate instruction rotates bytes, so we need to scale the
7690 // rotation based on how many bytes are in the vector.
7691 int Scale = 16 / Mask.size();
7693 // SSSE3 targets can use the palignr instruction
7694 if (Subtarget->hasSSSE3()) {
7695 // Cast the inputs to v16i8 to match PALIGNR.
7696 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7697 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7699 return DAG.getNode(ISD::BITCAST, DL, VT,
7700 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7701 DAG.getConstant(Rotation * Scale, MVT::i8)));
7704 // Default SSE2 implementation
7705 int LoByteShift = 16 - Rotation * Scale;
7706 int HiByteShift = Rotation * Scale;
7708 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7709 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7710 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7712 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7713 DAG.getConstant(8 * LoByteShift, MVT::i8));
7714 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7715 DAG.getConstant(8 * HiByteShift, MVT::i8));
7716 return DAG.getNode(ISD::BITCAST, DL, VT,
7717 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7720 /// \brief Compute whether each element of a shuffle is zeroable.
7722 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7723 /// Either it is an undef element in the shuffle mask, the element of the input
7724 /// referenced is undef, or the element of the input referenced is known to be
7725 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7726 /// as many lanes with this technique as possible to simplify the remaining
7728 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7729 SDValue V1, SDValue V2) {
7730 SmallBitVector Zeroable(Mask.size(), false);
7732 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7733 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7735 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7737 // Handle the easy cases.
7738 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7743 // If this is an index into a build_vector node, dig out the input value and
7745 SDValue V = M < Size ? V1 : V2;
7746 if (V.getOpcode() != ISD::BUILD_VECTOR)
7749 SDValue Input = V.getOperand(M % Size);
7750 // The UNDEF opcode check really should be dead code here, but not quite
7751 // worth asserting on (it isn't invalid, just unexpected).
7752 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7759 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7761 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7762 /// byte-shift instructions. The mask must consist of a shifted sequential
7763 /// shuffle from one of the input vectors and zeroable elements for the
7764 /// remaining 'shifted in' elements.
7766 /// Note that this only handles 128-bit vector widths currently.
7767 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7768 SDValue V2, ArrayRef<int> Mask,
7769 SelectionDAG &DAG) {
7770 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7772 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7774 int Size = Mask.size();
7775 int Scale = 16 / Size;
7777 for (int Shift = 1; Shift < Size; Shift++) {
7778 int ByteShift = Shift * Scale;
7780 // PSRLDQ : (little-endian) right byte shift
7781 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7782 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7783 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7784 bool ZeroableRight = true;
7785 for (int i = Size - Shift; i < Size; i++) {
7786 ZeroableRight &= Zeroable[i];
7789 if (ZeroableRight) {
7790 bool ValidShiftRight1 =
7791 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Shift);
7792 bool ValidShiftRight2 =
7793 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Size + Shift);
7795 if (ValidShiftRight1 || ValidShiftRight2) {
7796 // Cast the inputs to v2i64 to match PSRLDQ.
7797 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7798 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7799 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7800 DAG.getConstant(ByteShift * 8, MVT::i8));
7801 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7805 // PSLLDQ : (little-endian) left byte shift
7806 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7807 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7808 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7809 bool ZeroableLeft = true;
7810 for (int i = 0; i < Shift; i++) {
7811 ZeroableLeft &= Zeroable[i];
7815 bool ValidShiftLeft1 =
7816 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, 0);
7817 bool ValidShiftLeft2 =
7818 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, Size);
7820 if (ValidShiftLeft1 || ValidShiftLeft2) {
7821 // Cast the inputs to v2i64 to match PSLLDQ.
7822 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7823 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7824 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7825 DAG.getConstant(ByteShift * 8, MVT::i8));
7826 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7834 /// \brief Lower a vector shuffle as a zero or any extension.
7836 /// Given a specific number of elements, element bit width, and extension
7837 /// stride, produce either a zero or any extension based on the available
7838 /// features of the subtarget.
7839 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7840 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7841 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7842 assert(Scale > 1 && "Need a scale to extend.");
7843 int EltBits = VT.getSizeInBits() / NumElements;
7844 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7845 "Only 8, 16, and 32 bit elements can be extended.");
7846 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7848 // Found a valid zext mask! Try various lowering strategies based on the
7849 // input type and available ISA extensions.
7850 if (Subtarget->hasSSE41()) {
7851 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7852 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7853 NumElements / Scale);
7854 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7855 return DAG.getNode(ISD::BITCAST, DL, VT,
7856 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7859 // For any extends we can cheat for larger element sizes and use shuffle
7860 // instructions that can fold with a load and/or copy.
7861 if (AnyExt && EltBits == 32) {
7862 int PSHUFDMask[4] = {0, -1, 1, -1};
7864 ISD::BITCAST, DL, VT,
7865 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7866 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7867 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7869 if (AnyExt && EltBits == 16 && Scale > 2) {
7870 int PSHUFDMask[4] = {0, -1, 0, -1};
7871 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7872 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7873 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7874 int PSHUFHWMask[4] = {1, -1, -1, -1};
7876 ISD::BITCAST, DL, VT,
7877 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7878 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7879 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7882 // If this would require more than 2 unpack instructions to expand, use
7883 // pshufb when available. We can only use more than 2 unpack instructions
7884 // when zero extending i8 elements which also makes it easier to use pshufb.
7885 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7886 assert(NumElements == 16 && "Unexpected byte vector width!");
7887 SDValue PSHUFBMask[16];
7888 for (int i = 0; i < 16; ++i)
7890 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7891 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7892 return DAG.getNode(ISD::BITCAST, DL, VT,
7893 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7894 DAG.getNode(ISD::BUILD_VECTOR, DL,
7895 MVT::v16i8, PSHUFBMask)));
7898 // Otherwise emit a sequence of unpacks.
7900 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7901 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7902 : getZeroVector(InputVT, Subtarget, DAG, DL);
7903 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7904 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7908 } while (Scale > 1);
7909 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7912 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7914 /// This routine will try to do everything in its power to cleverly lower
7915 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7916 /// check for the profitability of this lowering, it tries to aggressively
7917 /// match this pattern. It will use all of the micro-architectural details it
7918 /// can to emit an efficient lowering. It handles both blends with all-zero
7919 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7920 /// masking out later).
7922 /// The reason we have dedicated lowering for zext-style shuffles is that they
7923 /// are both incredibly common and often quite performance sensitive.
7924 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7925 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7926 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7927 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7929 int Bits = VT.getSizeInBits();
7930 int NumElements = Mask.size();
7932 // Define a helper function to check a particular ext-scale and lower to it if
7934 auto Lower = [&](int Scale) -> SDValue {
7937 for (int i = 0; i < NumElements; ++i) {
7939 continue; // Valid anywhere but doesn't tell us anything.
7940 if (i % Scale != 0) {
7941 // Each of the extend elements needs to be zeroable.
7945 // We no lorger are in the anyext case.
7950 // Each of the base elements needs to be consecutive indices into the
7951 // same input vector.
7952 SDValue V = Mask[i] < NumElements ? V1 : V2;
7955 else if (InputV != V)
7956 return SDValue(); // Flip-flopping inputs.
7958 if (Mask[i] % NumElements != i / Scale)
7959 return SDValue(); // Non-consecutive strided elemenst.
7962 // If we fail to find an input, we have a zero-shuffle which should always
7963 // have already been handled.
7964 // FIXME: Maybe handle this here in case during blending we end up with one?
7968 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7969 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7972 // The widest scale possible for extending is to a 64-bit integer.
7973 assert(Bits % 64 == 0 &&
7974 "The number of bits in a vector must be divisible by 64 on x86!");
7975 int NumExtElements = Bits / 64;
7977 // Each iteration, try extending the elements half as much, but into twice as
7979 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7980 assert(NumElements % NumExtElements == 0 &&
7981 "The input vector size must be divisble by the extended size.");
7982 if (SDValue V = Lower(NumElements / NumExtElements))
7986 // No viable ext lowering found.
7990 /// \brief Try to get a scalar value for a specific element of a vector.
7992 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7993 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7994 SelectionDAG &DAG) {
7995 MVT VT = V.getSimpleValueType();
7996 MVT EltVT = VT.getVectorElementType();
7997 while (V.getOpcode() == ISD::BITCAST)
7998 V = V.getOperand(0);
7999 // If the bitcasts shift the element size, we can't extract an equivalent
8001 MVT NewVT = V.getSimpleValueType();
8002 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
8005 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8006 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
8007 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
8012 /// \brief Helper to test for a load that can be folded with x86 shuffles.
8014 /// This is particularly important because the set of instructions varies
8015 /// significantly based on whether the operand is a load or not.
8016 static bool isShuffleFoldableLoad(SDValue V) {
8017 while (V.getOpcode() == ISD::BITCAST)
8018 V = V.getOperand(0);
8020 return ISD::isNON_EXTLoad(V.getNode());
8023 /// \brief Try to lower insertion of a single element into a zero vector.
8025 /// This is a common pattern that we have especially efficient patterns to lower
8026 /// across all subtarget feature sets.
8027 static SDValue lowerVectorShuffleAsElementInsertion(
8028 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
8029 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8030 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8032 MVT EltVT = VT.getVectorElementType();
8034 int V2Index = std::find_if(Mask.begin(), Mask.end(),
8035 [&Mask](int M) { return M >= (int)Mask.size(); }) -
8037 bool IsV1Zeroable = true;
8038 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8039 if (i != V2Index && !Zeroable[i]) {
8040 IsV1Zeroable = false;
8044 // Check for a single input from a SCALAR_TO_VECTOR node.
8045 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
8046 // all the smarts here sunk into that routine. However, the current
8047 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8048 // vector shuffle lowering is dead.
8049 if (SDValue V2S = getScalarValueForVectorElement(
8050 V2, Mask[V2Index] - Mask.size(), DAG)) {
8051 // We need to zext the scalar if it is smaller than an i32.
8052 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8053 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8054 // Using zext to expand a narrow element won't work for non-zero
8059 // Zero-extend directly to i32.
8061 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8063 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8064 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8065 EltVT == MVT::i16) {
8066 // Either not inserting from the low element of the input or the input
8067 // element size is too small to use VZEXT_MOVL to clear the high bits.
8071 if (!IsV1Zeroable) {
8072 // If V1 can't be treated as a zero vector we have fewer options to lower
8073 // this. We can't support integer vectors or non-zero targets cheaply, and
8074 // the V1 elements can't be permuted in any way.
8075 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8076 if (!VT.isFloatingPoint() || V2Index != 0)
8078 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8079 V1Mask[V2Index] = -1;
8080 if (!isNoopShuffleMask(V1Mask))
8082 // This is essentially a special case blend operation, but if we have
8083 // general purpose blend operations, they are always faster. Bail and let
8084 // the rest of the lowering handle these as blends.
8085 if (Subtarget->hasSSE41())
8088 // Otherwise, use MOVSD or MOVSS.
8089 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8090 "Only two types of floating point element types to handle!");
8091 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8095 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8097 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8100 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8101 // the desired position. Otherwise it is more efficient to do a vector
8102 // shift left. We know that we can do a vector shift left because all
8103 // the inputs are zero.
8104 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8105 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8106 V2Shuffle[V2Index] = 0;
8107 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8109 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8111 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8113 V2Index * EltVT.getSizeInBits(),
8114 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8115 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8121 /// \brief Try to lower broadcast of a single element.
8123 /// For convenience, this code also bundles all of the subtarget feature set
8124 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8125 /// a convenient way to factor it out.
8126 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8128 const X86Subtarget *Subtarget,
8129 SelectionDAG &DAG) {
8130 if (!Subtarget->hasAVX())
8132 if (VT.isInteger() && !Subtarget->hasAVX2())
8135 // Check that the mask is a broadcast.
8136 int BroadcastIdx = -1;
8138 if (M >= 0 && BroadcastIdx == -1)
8140 else if (M >= 0 && M != BroadcastIdx)
8143 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8144 "a sorted mask where the broadcast "
8147 // Go up the chain of (vector) values to try and find a scalar load that
8148 // we can combine with the broadcast.
8150 switch (V.getOpcode()) {
8151 case ISD::CONCAT_VECTORS: {
8152 int OperandSize = Mask.size() / V.getNumOperands();
8153 V = V.getOperand(BroadcastIdx / OperandSize);
8154 BroadcastIdx %= OperandSize;
8158 case ISD::INSERT_SUBVECTOR: {
8159 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8160 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8164 int BeginIdx = (int)ConstantIdx->getZExtValue();
8166 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8167 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8168 BroadcastIdx -= BeginIdx;
8179 // Check if this is a broadcast of a scalar. We special case lowering
8180 // for scalars so that we can more effectively fold with loads.
8181 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8182 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8183 V = V.getOperand(BroadcastIdx);
8185 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8187 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8189 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8190 // We can't broadcast from a vector register w/o AVX2, and we can only
8191 // broadcast from the zero-element of a vector register.
8195 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8198 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8199 // INSERTPS when the V1 elements are already in the correct locations
8200 // because otherwise we can just always use two SHUFPS instructions which
8201 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8202 // perform INSERTPS if a single V1 element is out of place and all V2
8203 // elements are zeroable.
8204 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8206 SelectionDAG &DAG) {
8207 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8208 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8209 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8210 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8212 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8215 int V1DstIndex = -1;
8216 int V2DstIndex = -1;
8217 bool V1UsedInPlace = false;
8219 for (int i = 0; i < 4; i++) {
8220 // Synthesize a zero mask from the zeroable elements (includes undefs).
8226 // Flag if we use any V1 inputs in place.
8228 V1UsedInPlace = true;
8232 // We can only insert a single non-zeroable element.
8233 if (V1DstIndex != -1 || V2DstIndex != -1)
8237 // V1 input out of place for insertion.
8240 // V2 input for insertion.
8245 // Don't bother if we have no (non-zeroable) element for insertion.
8246 if (V1DstIndex == -1 && V2DstIndex == -1)
8249 // Determine element insertion src/dst indices. The src index is from the
8250 // start of the inserted vector, not the start of the concatenated vector.
8251 unsigned V2SrcIndex = 0;
8252 if (V1DstIndex != -1) {
8253 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8254 // and don't use the original V2 at all.
8255 V2SrcIndex = Mask[V1DstIndex];
8256 V2DstIndex = V1DstIndex;
8259 V2SrcIndex = Mask[V2DstIndex] - 4;
8262 // If no V1 inputs are used in place, then the result is created only from
8263 // the zero mask and the V2 insertion - so remove V1 dependency.
8265 V1 = DAG.getUNDEF(MVT::v4f32);
8267 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8268 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8270 // Insert the V2 element into the desired position.
8272 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8273 DAG.getConstant(InsertPSMask, MVT::i8));
8276 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8278 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8279 /// support for floating point shuffles but not integer shuffles. These
8280 /// instructions will incur a domain crossing penalty on some chips though so
8281 /// it is better to avoid lowering through this for integer vectors where
8283 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8284 const X86Subtarget *Subtarget,
8285 SelectionDAG &DAG) {
8287 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8288 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8289 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8290 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8291 ArrayRef<int> Mask = SVOp->getMask();
8292 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8294 if (isSingleInputShuffleMask(Mask)) {
8295 // Use low duplicate instructions for masks that match their pattern.
8296 if (Subtarget->hasSSE3())
8297 if (isShuffleEquivalent(Mask, 0, 0))
8298 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8300 // Straight shuffle of a single input vector. Simulate this by using the
8301 // single input as both of the "inputs" to this instruction..
8302 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8304 if (Subtarget->hasAVX()) {
8305 // If we have AVX, we can use VPERMILPS which will allow folding a load
8306 // into the shuffle.
8307 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8308 DAG.getConstant(SHUFPDMask, MVT::i8));
8311 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8312 DAG.getConstant(SHUFPDMask, MVT::i8));
8314 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8315 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8317 // Use dedicated unpack instructions for masks that match their pattern.
8318 if (isShuffleEquivalent(Mask, 0, 2))
8319 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8320 if (isShuffleEquivalent(Mask, 1, 3))
8321 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8323 // If we have a single input, insert that into V1 if we can do so cheaply.
8324 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8325 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8326 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8328 // Try inverting the insertion since for v2 masks it is easy to do and we
8329 // can't reliably sort the mask one way or the other.
8330 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8331 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8332 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8333 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8337 // Try to use one of the special instruction patterns to handle two common
8338 // blend patterns if a zero-blend above didn't work.
8339 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8340 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8341 // We can either use a special instruction to load over the low double or
8342 // to move just the low double.
8344 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8346 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8348 if (Subtarget->hasSSE41())
8349 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8353 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8354 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8355 DAG.getConstant(SHUFPDMask, MVT::i8));
8358 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8360 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8361 /// the integer unit to minimize domain crossing penalties. However, for blends
8362 /// it falls back to the floating point shuffle operation with appropriate bit
8364 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8365 const X86Subtarget *Subtarget,
8366 SelectionDAG &DAG) {
8368 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8369 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8370 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8371 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8372 ArrayRef<int> Mask = SVOp->getMask();
8373 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8375 if (isSingleInputShuffleMask(Mask)) {
8376 // Check for being able to broadcast a single element.
8377 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8378 Mask, Subtarget, DAG))
8381 // Straight shuffle of a single input vector. For everything from SSE2
8382 // onward this has a single fast instruction with no scary immediates.
8383 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8384 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8385 int WidenedMask[4] = {
8386 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8387 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8389 ISD::BITCAST, DL, MVT::v2i64,
8390 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8391 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8394 // Try to use byte shift instructions.
8395 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8396 DL, MVT::v2i64, V1, V2, Mask, DAG))
8399 // If we have a single input from V2 insert that into V1 if we can do so
8401 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8402 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8403 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8405 // Try inverting the insertion since for v2 masks it is easy to do and we
8406 // can't reliably sort the mask one way or the other.
8407 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8408 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8409 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8410 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8414 // Use dedicated unpack instructions for masks that match their pattern.
8415 if (isShuffleEquivalent(Mask, 0, 2))
8416 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8417 if (isShuffleEquivalent(Mask, 1, 3))
8418 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8420 if (Subtarget->hasSSE41())
8421 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8425 // Try to use byte rotation instructions.
8426 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8427 if (Subtarget->hasSSSE3())
8428 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8429 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8432 // We implement this with SHUFPD which is pretty lame because it will likely
8433 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8434 // However, all the alternatives are still more cycles and newer chips don't
8435 // have this problem. It would be really nice if x86 had better shuffles here.
8436 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8437 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8438 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8439 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8442 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8444 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8445 /// It makes no assumptions about whether this is the *best* lowering, it simply
8447 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8448 ArrayRef<int> Mask, SDValue V1,
8449 SDValue V2, SelectionDAG &DAG) {
8450 SDValue LowV = V1, HighV = V2;
8451 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8454 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8456 if (NumV2Elements == 1) {
8458 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8461 // Compute the index adjacent to V2Index and in the same half by toggling
8463 int V2AdjIndex = V2Index ^ 1;
8465 if (Mask[V2AdjIndex] == -1) {
8466 // Handles all the cases where we have a single V2 element and an undef.
8467 // This will only ever happen in the high lanes because we commute the
8468 // vector otherwise.
8470 std::swap(LowV, HighV);
8471 NewMask[V2Index] -= 4;
8473 // Handle the case where the V2 element ends up adjacent to a V1 element.
8474 // To make this work, blend them together as the first step.
8475 int V1Index = V2AdjIndex;
8476 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8477 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8478 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8480 // Now proceed to reconstruct the final blend as we have the necessary
8481 // high or low half formed.
8488 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8489 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8491 } else if (NumV2Elements == 2) {
8492 if (Mask[0] < 4 && Mask[1] < 4) {
8493 // Handle the easy case where we have V1 in the low lanes and V2 in the
8497 } else if (Mask[2] < 4 && Mask[3] < 4) {
8498 // We also handle the reversed case because this utility may get called
8499 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8500 // arrange things in the right direction.
8506 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8507 // trying to place elements directly, just blend them and set up the final
8508 // shuffle to place them.
8510 // The first two blend mask elements are for V1, the second two are for
8512 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8513 Mask[2] < 4 ? Mask[2] : Mask[3],
8514 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8515 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8516 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8517 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8519 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8522 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8523 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8524 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8525 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8528 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8529 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8532 /// \brief Lower 4-lane 32-bit floating point shuffles.
8534 /// Uses instructions exclusively from the floating point unit to minimize
8535 /// domain crossing penalties, as these are sufficient to implement all v4f32
8537 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8538 const X86Subtarget *Subtarget,
8539 SelectionDAG &DAG) {
8541 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8542 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8543 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8544 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8545 ArrayRef<int> Mask = SVOp->getMask();
8546 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8549 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8551 if (NumV2Elements == 0) {
8552 // Check for being able to broadcast a single element.
8553 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8554 Mask, Subtarget, DAG))
8557 // Use even/odd duplicate instructions for masks that match their pattern.
8558 if (Subtarget->hasSSE3()) {
8559 if (isShuffleEquivalent(Mask, 0, 0, 2, 2))
8560 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8561 if (isShuffleEquivalent(Mask, 1, 1, 3, 3))
8562 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8565 if (Subtarget->hasAVX()) {
8566 // If we have AVX, we can use VPERMILPS which will allow folding a load
8567 // into the shuffle.
8568 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8569 getV4X86ShuffleImm8ForMask(Mask, DAG));
8572 // Otherwise, use a straight shuffle of a single input vector. We pass the
8573 // input vector to both operands to simulate this with a SHUFPS.
8574 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8575 getV4X86ShuffleImm8ForMask(Mask, DAG));
8578 // Use dedicated unpack instructions for masks that match their pattern.
8579 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8580 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8581 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8582 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8584 // There are special ways we can lower some single-element blends. However, we
8585 // have custom ways we can lower more complex single-element blends below that
8586 // we defer to if both this and BLENDPS fail to match, so restrict this to
8587 // when the V2 input is targeting element 0 of the mask -- that is the fast
8589 if (NumV2Elements == 1 && Mask[0] >= 4)
8590 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8591 Mask, Subtarget, DAG))
8594 if (Subtarget->hasSSE41()) {
8595 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8599 // Use INSERTPS if we can complete the shuffle efficiently.
8600 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8604 // Otherwise fall back to a SHUFPS lowering strategy.
8605 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8608 /// \brief Lower 4-lane i32 vector shuffles.
8610 /// We try to handle these with integer-domain shuffles where we can, but for
8611 /// blends we use the floating point domain blend instructions.
8612 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8613 const X86Subtarget *Subtarget,
8614 SelectionDAG &DAG) {
8616 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8617 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8618 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8619 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8620 ArrayRef<int> Mask = SVOp->getMask();
8621 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8623 // Whenever we can lower this as a zext, that instruction is strictly faster
8624 // than any alternative. It also allows us to fold memory operands into the
8625 // shuffle in many cases.
8626 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8627 Mask, Subtarget, DAG))
8631 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8633 if (NumV2Elements == 0) {
8634 // Check for being able to broadcast a single element.
8635 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8636 Mask, Subtarget, DAG))
8639 // Straight shuffle of a single input vector. For everything from SSE2
8640 // onward this has a single fast instruction with no scary immediates.
8641 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8642 // but we aren't actually going to use the UNPCK instruction because doing
8643 // so prevents folding a load into this instruction or making a copy.
8644 const int UnpackLoMask[] = {0, 0, 1, 1};
8645 const int UnpackHiMask[] = {2, 2, 3, 3};
8646 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8647 Mask = UnpackLoMask;
8648 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8649 Mask = UnpackHiMask;
8651 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8652 getV4X86ShuffleImm8ForMask(Mask, DAG));
8655 // Try to use byte shift instructions.
8656 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8657 DL, MVT::v4i32, V1, V2, Mask, DAG))
8660 // There are special ways we can lower some single-element blends.
8661 if (NumV2Elements == 1)
8662 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8663 Mask, Subtarget, DAG))
8666 // Use dedicated unpack instructions for masks that match their pattern.
8667 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8668 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8669 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8670 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8672 if (Subtarget->hasSSE41())
8673 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8677 // Try to use byte rotation instructions.
8678 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8679 if (Subtarget->hasSSSE3())
8680 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8681 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8684 // We implement this with SHUFPS because it can blend from two vectors.
8685 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8686 // up the inputs, bypassing domain shift penalties that we would encur if we
8687 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8689 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8690 DAG.getVectorShuffle(
8692 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8693 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8696 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8697 /// shuffle lowering, and the most complex part.
8699 /// The lowering strategy is to try to form pairs of input lanes which are
8700 /// targeted at the same half of the final vector, and then use a dword shuffle
8701 /// to place them onto the right half, and finally unpack the paired lanes into
8702 /// their final position.
8704 /// The exact breakdown of how to form these dword pairs and align them on the
8705 /// correct sides is really tricky. See the comments within the function for
8706 /// more of the details.
8707 static SDValue lowerV8I16SingleInputVectorShuffle(
8708 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8709 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8710 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8711 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8712 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8714 SmallVector<int, 4> LoInputs;
8715 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8716 [](int M) { return M >= 0; });
8717 std::sort(LoInputs.begin(), LoInputs.end());
8718 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8719 SmallVector<int, 4> HiInputs;
8720 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8721 [](int M) { return M >= 0; });
8722 std::sort(HiInputs.begin(), HiInputs.end());
8723 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8725 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8726 int NumHToL = LoInputs.size() - NumLToL;
8728 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8729 int NumHToH = HiInputs.size() - NumLToH;
8730 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8731 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8732 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8733 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8735 // Check for being able to broadcast a single element.
8736 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8737 Mask, Subtarget, DAG))
8740 // Try to use byte shift instructions.
8741 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8742 DL, MVT::v8i16, V, V, Mask, DAG))
8745 // Use dedicated unpack instructions for masks that match their pattern.
8746 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8747 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8748 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8749 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8751 // Try to use byte rotation instructions.
8752 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8753 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8756 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8757 // such inputs we can swap two of the dwords across the half mark and end up
8758 // with <=2 inputs to each half in each half. Once there, we can fall through
8759 // to the generic code below. For example:
8761 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8762 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8764 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8765 // and an existing 2-into-2 on the other half. In this case we may have to
8766 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8767 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8768 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8769 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8770 // half than the one we target for fixing) will be fixed when we re-enter this
8771 // path. We will also combine away any sequence of PSHUFD instructions that
8772 // result into a single instruction. Here is an example of the tricky case:
8774 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8775 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8777 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8779 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8780 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8782 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8783 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8785 // The result is fine to be handled by the generic logic.
8786 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8787 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8788 int AOffset, int BOffset) {
8789 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8790 "Must call this with A having 3 or 1 inputs from the A half.");
8791 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8792 "Must call this with B having 1 or 3 inputs from the B half.");
8793 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8794 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8796 // Compute the index of dword with only one word among the three inputs in
8797 // a half by taking the sum of the half with three inputs and subtracting
8798 // the sum of the actual three inputs. The difference is the remaining
8801 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8802 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8803 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8804 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8805 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8806 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8807 int TripleNonInputIdx =
8808 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8809 TripleDWord = TripleNonInputIdx / 2;
8811 // We use xor with one to compute the adjacent DWord to whichever one the
8813 OneInputDWord = (OneInput / 2) ^ 1;
8815 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8816 // and BToA inputs. If there is also such a problem with the BToB and AToB
8817 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8818 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8819 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8820 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8821 // Compute how many inputs will be flipped by swapping these DWords. We
8823 // to balance this to ensure we don't form a 3-1 shuffle in the other
8825 int NumFlippedAToBInputs =
8826 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8827 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8828 int NumFlippedBToBInputs =
8829 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8830 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8831 if ((NumFlippedAToBInputs == 1 &&
8832 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8833 (NumFlippedBToBInputs == 1 &&
8834 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8835 // We choose whether to fix the A half or B half based on whether that
8836 // half has zero flipped inputs. At zero, we may not be able to fix it
8837 // with that half. We also bias towards fixing the B half because that
8838 // will more commonly be the high half, and we have to bias one way.
8839 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8840 ArrayRef<int> Inputs) {
8841 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8842 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8843 PinnedIdx ^ 1) != Inputs.end();
8844 // Determine whether the free index is in the flipped dword or the
8845 // unflipped dword based on where the pinned index is. We use this bit
8846 // in an xor to conditionally select the adjacent dword.
8847 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8848 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8849 FixFreeIdx) != Inputs.end();
8850 if (IsFixIdxInput == IsFixFreeIdxInput)
8852 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8853 FixFreeIdx) != Inputs.end();
8854 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8855 "We need to be changing the number of flipped inputs!");
8856 int PSHUFHalfMask[] = {0, 1, 2, 3};
8857 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8858 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8860 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8863 if (M != -1 && M == FixIdx)
8865 else if (M != -1 && M == FixFreeIdx)
8868 if (NumFlippedBToBInputs != 0) {
8870 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8871 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8873 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8875 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8876 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8881 int PSHUFDMask[] = {0, 1, 2, 3};
8882 PSHUFDMask[ADWord] = BDWord;
8883 PSHUFDMask[BDWord] = ADWord;
8884 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8885 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8886 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8887 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8889 // Adjust the mask to match the new locations of A and B.
8891 if (M != -1 && M/2 == ADWord)
8892 M = 2 * BDWord + M % 2;
8893 else if (M != -1 && M/2 == BDWord)
8894 M = 2 * ADWord + M % 2;
8896 // Recurse back into this routine to re-compute state now that this isn't
8897 // a 3 and 1 problem.
8898 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8901 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8902 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8903 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8904 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8906 // At this point there are at most two inputs to the low and high halves from
8907 // each half. That means the inputs can always be grouped into dwords and
8908 // those dwords can then be moved to the correct half with a dword shuffle.
8909 // We use at most one low and one high word shuffle to collect these paired
8910 // inputs into dwords, and finally a dword shuffle to place them.
8911 int PSHUFLMask[4] = {-1, -1, -1, -1};
8912 int PSHUFHMask[4] = {-1, -1, -1, -1};
8913 int PSHUFDMask[4] = {-1, -1, -1, -1};
8915 // First fix the masks for all the inputs that are staying in their
8916 // original halves. This will then dictate the targets of the cross-half
8918 auto fixInPlaceInputs =
8919 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8920 MutableArrayRef<int> SourceHalfMask,
8921 MutableArrayRef<int> HalfMask, int HalfOffset) {
8922 if (InPlaceInputs.empty())
8924 if (InPlaceInputs.size() == 1) {
8925 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8926 InPlaceInputs[0] - HalfOffset;
8927 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8930 if (IncomingInputs.empty()) {
8931 // Just fix all of the in place inputs.
8932 for (int Input : InPlaceInputs) {
8933 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8934 PSHUFDMask[Input / 2] = Input / 2;
8939 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8940 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8941 InPlaceInputs[0] - HalfOffset;
8942 // Put the second input next to the first so that they are packed into
8943 // a dword. We find the adjacent index by toggling the low bit.
8944 int AdjIndex = InPlaceInputs[0] ^ 1;
8945 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8946 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8947 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8949 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8950 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8952 // Now gather the cross-half inputs and place them into a free dword of
8953 // their target half.
8954 // FIXME: This operation could almost certainly be simplified dramatically to
8955 // look more like the 3-1 fixing operation.
8956 auto moveInputsToRightHalf = [&PSHUFDMask](
8957 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8958 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8959 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8961 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8962 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8964 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8966 int LowWord = Word & ~1;
8967 int HighWord = Word | 1;
8968 return isWordClobbered(SourceHalfMask, LowWord) ||
8969 isWordClobbered(SourceHalfMask, HighWord);
8972 if (IncomingInputs.empty())
8975 if (ExistingInputs.empty()) {
8976 // Map any dwords with inputs from them into the right half.
8977 for (int Input : IncomingInputs) {
8978 // If the source half mask maps over the inputs, turn those into
8979 // swaps and use the swapped lane.
8980 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8981 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8982 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8983 Input - SourceOffset;
8984 // We have to swap the uses in our half mask in one sweep.
8985 for (int &M : HalfMask)
8986 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8988 else if (M == Input)
8989 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8991 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8992 Input - SourceOffset &&
8993 "Previous placement doesn't match!");
8995 // Note that this correctly re-maps both when we do a swap and when
8996 // we observe the other side of the swap above. We rely on that to
8997 // avoid swapping the members of the input list directly.
8998 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9001 // Map the input's dword into the correct half.
9002 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9003 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9005 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9007 "Previous placement doesn't match!");
9010 // And just directly shift any other-half mask elements to be same-half
9011 // as we will have mirrored the dword containing the element into the
9012 // same position within that half.
9013 for (int &M : HalfMask)
9014 if (M >= SourceOffset && M < SourceOffset + 4) {
9015 M = M - SourceOffset + DestOffset;
9016 assert(M >= 0 && "This should never wrap below zero!");
9021 // Ensure we have the input in a viable dword of its current half. This
9022 // is particularly tricky because the original position may be clobbered
9023 // by inputs being moved and *staying* in that half.
9024 if (IncomingInputs.size() == 1) {
9025 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9026 int InputFixed = std::find(std::begin(SourceHalfMask),
9027 std::end(SourceHalfMask), -1) -
9028 std::begin(SourceHalfMask) + SourceOffset;
9029 SourceHalfMask[InputFixed - SourceOffset] =
9030 IncomingInputs[0] - SourceOffset;
9031 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9033 IncomingInputs[0] = InputFixed;
9035 } else if (IncomingInputs.size() == 2) {
9036 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9037 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9038 // We have two non-adjacent or clobbered inputs we need to extract from
9039 // the source half. To do this, we need to map them into some adjacent
9040 // dword slot in the source mask.
9041 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9042 IncomingInputs[1] - SourceOffset};
9044 // If there is a free slot in the source half mask adjacent to one of
9045 // the inputs, place the other input in it. We use (Index XOR 1) to
9046 // compute an adjacent index.
9047 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9048 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9049 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9050 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9051 InputsFixed[1] = InputsFixed[0] ^ 1;
9052 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9053 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9054 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9055 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9056 InputsFixed[0] = InputsFixed[1] ^ 1;
9057 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9058 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9059 // The two inputs are in the same DWord but it is clobbered and the
9060 // adjacent DWord isn't used at all. Move both inputs to the free
9062 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9063 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9064 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9065 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9067 // The only way we hit this point is if there is no clobbering
9068 // (because there are no off-half inputs to this half) and there is no
9069 // free slot adjacent to one of the inputs. In this case, we have to
9070 // swap an input with a non-input.
9071 for (int i = 0; i < 4; ++i)
9072 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9073 "We can't handle any clobbers here!");
9074 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9075 "Cannot have adjacent inputs here!");
9077 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9078 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9080 // We also have to update the final source mask in this case because
9081 // it may need to undo the above swap.
9082 for (int &M : FinalSourceHalfMask)
9083 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9084 M = InputsFixed[1] + SourceOffset;
9085 else if (M == InputsFixed[1] + SourceOffset)
9086 M = (InputsFixed[0] ^ 1) + SourceOffset;
9088 InputsFixed[1] = InputsFixed[0] ^ 1;
9091 // Point everything at the fixed inputs.
9092 for (int &M : HalfMask)
9093 if (M == IncomingInputs[0])
9094 M = InputsFixed[0] + SourceOffset;
9095 else if (M == IncomingInputs[1])
9096 M = InputsFixed[1] + SourceOffset;
9098 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9099 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9102 llvm_unreachable("Unhandled input size!");
9105 // Now hoist the DWord down to the right half.
9106 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9107 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9108 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9109 for (int &M : HalfMask)
9110 for (int Input : IncomingInputs)
9112 M = FreeDWord * 2 + Input % 2;
9114 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9115 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9116 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9117 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9119 // Now enact all the shuffles we've computed to move the inputs into their
9121 if (!isNoopShuffleMask(PSHUFLMask))
9122 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9123 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9124 if (!isNoopShuffleMask(PSHUFHMask))
9125 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9126 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9127 if (!isNoopShuffleMask(PSHUFDMask))
9128 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9129 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9130 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9131 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9133 // At this point, each half should contain all its inputs, and we can then
9134 // just shuffle them into their final position.
9135 assert(std::count_if(LoMask.begin(), LoMask.end(),
9136 [](int M) { return M >= 4; }) == 0 &&
9137 "Failed to lift all the high half inputs to the low mask!");
9138 assert(std::count_if(HiMask.begin(), HiMask.end(),
9139 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9140 "Failed to lift all the low half inputs to the high mask!");
9142 // Do a half shuffle for the low mask.
9143 if (!isNoopShuffleMask(LoMask))
9144 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9145 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9147 // Do a half shuffle with the high mask after shifting its values down.
9148 for (int &M : HiMask)
9151 if (!isNoopShuffleMask(HiMask))
9152 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9153 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9158 /// \brief Detect whether the mask pattern should be lowered through
9161 /// This essentially tests whether viewing the mask as an interleaving of two
9162 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9163 /// lowering it through interleaving is a significantly better strategy.
9164 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9165 int NumEvenInputs[2] = {0, 0};
9166 int NumOddInputs[2] = {0, 0};
9167 int NumLoInputs[2] = {0, 0};
9168 int NumHiInputs[2] = {0, 0};
9169 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9173 int InputIdx = Mask[i] >= Size;
9176 ++NumLoInputs[InputIdx];
9178 ++NumHiInputs[InputIdx];
9181 ++NumEvenInputs[InputIdx];
9183 ++NumOddInputs[InputIdx];
9186 // The minimum number of cross-input results for both the interleaved and
9187 // split cases. If interleaving results in fewer cross-input results, return
9189 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9190 NumEvenInputs[0] + NumOddInputs[1]);
9191 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9192 NumLoInputs[0] + NumHiInputs[1]);
9193 return InterleavedCrosses < SplitCrosses;
9196 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9198 /// This strategy only works when the inputs from each vector fit into a single
9199 /// half of that vector, and generally there are not so many inputs as to leave
9200 /// the in-place shuffles required highly constrained (and thus expensive). It
9201 /// shifts all the inputs into a single side of both input vectors and then
9202 /// uses an unpack to interleave these inputs in a single vector. At that
9203 /// point, we will fall back on the generic single input shuffle lowering.
9204 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9206 MutableArrayRef<int> Mask,
9207 const X86Subtarget *Subtarget,
9208 SelectionDAG &DAG) {
9209 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9210 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9211 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9212 for (int i = 0; i < 8; ++i)
9213 if (Mask[i] >= 0 && Mask[i] < 4)
9214 LoV1Inputs.push_back(i);
9215 else if (Mask[i] >= 4 && Mask[i] < 8)
9216 HiV1Inputs.push_back(i);
9217 else if (Mask[i] >= 8 && Mask[i] < 12)
9218 LoV2Inputs.push_back(i);
9219 else if (Mask[i] >= 12)
9220 HiV2Inputs.push_back(i);
9222 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9223 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9226 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9227 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9228 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9230 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9231 HiV1Inputs.size() + HiV2Inputs.size();
9233 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9234 ArrayRef<int> HiInputs, bool MoveToLo,
9236 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9237 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9238 if (BadInputs.empty())
9241 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9242 int MoveOffset = MoveToLo ? 0 : 4;
9244 if (GoodInputs.empty()) {
9245 for (int BadInput : BadInputs) {
9246 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9247 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9250 if (GoodInputs.size() == 2) {
9251 // If the low inputs are spread across two dwords, pack them into
9253 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9254 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9255 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9256 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9258 // Otherwise pin the good inputs.
9259 for (int GoodInput : GoodInputs)
9260 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9263 if (BadInputs.size() == 2) {
9264 // If we have two bad inputs then there may be either one or two good
9265 // inputs fixed in place. Find a fixed input, and then find the *other*
9266 // two adjacent indices by using modular arithmetic.
9268 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9269 [](int M) { return M >= 0; }) -
9270 std::begin(MoveMask);
9272 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9273 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9274 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9275 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9276 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9277 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9278 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9280 assert(BadInputs.size() == 1 && "All sizes handled");
9281 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9282 std::end(MoveMask), -1) -
9283 std::begin(MoveMask);
9284 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9285 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9289 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9292 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9294 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9297 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9298 // cross-half traffic in the final shuffle.
9300 // Munge the mask to be a single-input mask after the unpack merges the
9304 M = 2 * (M % 4) + (M / 8);
9306 return DAG.getVectorShuffle(
9307 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9308 DL, MVT::v8i16, V1, V2),
9309 DAG.getUNDEF(MVT::v8i16), Mask);
9312 /// \brief Generic lowering of 8-lane i16 shuffles.
9314 /// This handles both single-input shuffles and combined shuffle/blends with
9315 /// two inputs. The single input shuffles are immediately delegated to
9316 /// a dedicated lowering routine.
9318 /// The blends are lowered in one of three fundamental ways. If there are few
9319 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9320 /// of the input is significantly cheaper when lowered as an interleaving of
9321 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9322 /// halves of the inputs separately (making them have relatively few inputs)
9323 /// and then concatenate them.
9324 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9325 const X86Subtarget *Subtarget,
9326 SelectionDAG &DAG) {
9328 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9329 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9330 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9331 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9332 ArrayRef<int> OrigMask = SVOp->getMask();
9333 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9334 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9335 MutableArrayRef<int> Mask(MaskStorage);
9337 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9339 // Whenever we can lower this as a zext, that instruction is strictly faster
9340 // than any alternative.
9341 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9342 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9345 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9346 auto isV2 = [](int M) { return M >= 8; };
9348 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9349 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9351 if (NumV2Inputs == 0)
9352 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9354 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9355 "to be V1-input shuffles.");
9357 // Try to use byte shift instructions.
9358 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9359 DL, MVT::v8i16, V1, V2, Mask, DAG))
9362 // There are special ways we can lower some single-element blends.
9363 if (NumV2Inputs == 1)
9364 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9365 Mask, Subtarget, DAG))
9368 // Use dedicated unpack instructions for masks that match their pattern.
9369 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9370 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9371 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9372 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9374 if (Subtarget->hasSSE41())
9375 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9379 // Try to use byte rotation instructions.
9380 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9381 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9384 if (NumV1Inputs + NumV2Inputs <= 4)
9385 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9387 // Check whether an interleaving lowering is likely to be more efficient.
9388 // This isn't perfect but it is a strong heuristic that tends to work well on
9389 // the kinds of shuffles that show up in practice.
9391 // FIXME: Handle 1x, 2x, and 4x interleaving.
9392 if (shouldLowerAsInterleaving(Mask)) {
9393 // FIXME: Figure out whether we should pack these into the low or high
9396 int EMask[8], OMask[8];
9397 for (int i = 0; i < 4; ++i) {
9398 EMask[i] = Mask[2*i];
9399 OMask[i] = Mask[2*i + 1];
9404 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9405 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9407 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9410 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9411 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9413 for (int i = 0; i < 4; ++i) {
9414 LoBlendMask[i] = Mask[i];
9415 HiBlendMask[i] = Mask[i + 4];
9418 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9419 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9420 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9421 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9423 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9424 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9427 /// \brief Check whether a compaction lowering can be done by dropping even
9428 /// elements and compute how many times even elements must be dropped.
9430 /// This handles shuffles which take every Nth element where N is a power of
9431 /// two. Example shuffle masks:
9433 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9434 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9435 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9436 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9437 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9438 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9440 /// Any of these lanes can of course be undef.
9442 /// This routine only supports N <= 3.
9443 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9446 /// \returns N above, or the number of times even elements must be dropped if
9447 /// there is such a number. Otherwise returns zero.
9448 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9449 // Figure out whether we're looping over two inputs or just one.
9450 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9452 // The modulus for the shuffle vector entries is based on whether this is
9453 // a single input or not.
9454 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9455 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9456 "We should only be called with masks with a power-of-2 size!");
9458 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9460 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9461 // and 2^3 simultaneously. This is because we may have ambiguity with
9462 // partially undef inputs.
9463 bool ViableForN[3] = {true, true, true};
9465 for (int i = 0, e = Mask.size(); i < e; ++i) {
9466 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9471 bool IsAnyViable = false;
9472 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9473 if (ViableForN[j]) {
9476 // The shuffle mask must be equal to (i * 2^N) % M.
9477 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9480 ViableForN[j] = false;
9482 // Early exit if we exhaust the possible powers of two.
9487 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9491 // Return 0 as there is no viable power of two.
9495 /// \brief Generic lowering of v16i8 shuffles.
9497 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9498 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9499 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9500 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9502 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9503 const X86Subtarget *Subtarget,
9504 SelectionDAG &DAG) {
9506 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9507 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9508 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9509 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9510 ArrayRef<int> OrigMask = SVOp->getMask();
9511 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9513 // Try to use byte shift instructions.
9514 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9515 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9518 // Try to use byte rotation instructions.
9519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9520 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9523 // Try to use a zext lowering.
9524 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9525 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9528 int MaskStorage[16] = {
9529 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9530 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9531 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9532 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9533 MutableArrayRef<int> Mask(MaskStorage);
9534 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9535 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9538 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9540 // For single-input shuffles, there are some nicer lowering tricks we can use.
9541 if (NumV2Elements == 0) {
9542 // Check for being able to broadcast a single element.
9543 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9544 Mask, Subtarget, DAG))
9547 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9548 // Notably, this handles splat and partial-splat shuffles more efficiently.
9549 // However, it only makes sense if the pre-duplication shuffle simplifies
9550 // things significantly. Currently, this means we need to be able to
9551 // express the pre-duplication shuffle as an i16 shuffle.
9553 // FIXME: We should check for other patterns which can be widened into an
9554 // i16 shuffle as well.
9555 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9556 for (int i = 0; i < 16; i += 2)
9557 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9562 auto tryToWidenViaDuplication = [&]() -> SDValue {
9563 if (!canWidenViaDuplication(Mask))
9565 SmallVector<int, 4> LoInputs;
9566 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9567 [](int M) { return M >= 0 && M < 8; });
9568 std::sort(LoInputs.begin(), LoInputs.end());
9569 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9571 SmallVector<int, 4> HiInputs;
9572 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9573 [](int M) { return M >= 8; });
9574 std::sort(HiInputs.begin(), HiInputs.end());
9575 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9578 bool TargetLo = LoInputs.size() >= HiInputs.size();
9579 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9580 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9582 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9583 SmallDenseMap<int, int, 8> LaneMap;
9584 for (int I : InPlaceInputs) {
9585 PreDupI16Shuffle[I/2] = I/2;
9588 int j = TargetLo ? 0 : 4, je = j + 4;
9589 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9590 // Check if j is already a shuffle of this input. This happens when
9591 // there are two adjacent bytes after we move the low one.
9592 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9593 // If we haven't yet mapped the input, search for a slot into which
9595 while (j < je && PreDupI16Shuffle[j] != -1)
9599 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9602 // Map this input with the i16 shuffle.
9603 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9606 // Update the lane map based on the mapping we ended up with.
9607 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9610 ISD::BITCAST, DL, MVT::v16i8,
9611 DAG.getVectorShuffle(MVT::v8i16, DL,
9612 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9613 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9615 // Unpack the bytes to form the i16s that will be shuffled into place.
9616 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9617 MVT::v16i8, V1, V1);
9619 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9620 for (int i = 0; i < 16; ++i)
9621 if (Mask[i] != -1) {
9622 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9623 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9624 if (PostDupI16Shuffle[i / 2] == -1)
9625 PostDupI16Shuffle[i / 2] = MappedMask;
9627 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9628 "Conflicting entrties in the original shuffle!");
9631 ISD::BITCAST, DL, MVT::v16i8,
9632 DAG.getVectorShuffle(MVT::v8i16, DL,
9633 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9634 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9636 if (SDValue V = tryToWidenViaDuplication())
9640 // Check whether an interleaving lowering is likely to be more efficient.
9641 // This isn't perfect but it is a strong heuristic that tends to work well on
9642 // the kinds of shuffles that show up in practice.
9644 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9645 if (shouldLowerAsInterleaving(Mask)) {
9646 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9647 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9649 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9650 return (M >= 8 && M < 16) || M >= 24;
9652 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9653 -1, -1, -1, -1, -1, -1, -1, -1};
9654 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9655 -1, -1, -1, -1, -1, -1, -1, -1};
9656 bool UnpackLo = NumLoHalf >= NumHiHalf;
9657 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9658 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9659 for (int i = 0; i < 8; ++i) {
9660 TargetEMask[i] = Mask[2 * i];
9661 TargetOMask[i] = Mask[2 * i + 1];
9664 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9665 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9667 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9668 MVT::v16i8, Evens, Odds);
9671 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9672 // with PSHUFB. It is important to do this before we attempt to generate any
9673 // blends but after all of the single-input lowerings. If the single input
9674 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9675 // want to preserve that and we can DAG combine any longer sequences into
9676 // a PSHUFB in the end. But once we start blending from multiple inputs,
9677 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9678 // and there are *very* few patterns that would actually be faster than the
9679 // PSHUFB approach because of its ability to zero lanes.
9681 // FIXME: The only exceptions to the above are blends which are exact
9682 // interleavings with direct instructions supporting them. We currently don't
9683 // handle those well here.
9684 if (Subtarget->hasSSSE3()) {
9687 bool V1InUse = false;
9688 bool V2InUse = false;
9689 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9691 for (int i = 0; i < 16; ++i) {
9692 if (Mask[i] == -1) {
9693 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9695 const int ZeroMask = 0x80;
9696 int V1Idx = (Mask[i] < 16 ? Mask[i] : ZeroMask);
9697 int V2Idx = (Mask[i] < 16 ? ZeroMask : Mask[i] - 16);
9699 V1Idx = V2Idx = ZeroMask;
9700 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
9701 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
9702 V1InUse |= (ZeroMask != V1Idx);
9703 V2InUse |= (ZeroMask != V2Idx);
9708 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9709 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9711 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9712 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9714 // If we need shuffled inputs from both, blend the two.
9715 if (V1InUse && V2InUse)
9716 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9718 return V1; // Single inputs are easy.
9720 return V2; // Single inputs are easy.
9721 // Shuffling to a zeroable vector.
9722 return getZeroVector(MVT::v16i8, Subtarget, DAG, DL);
9725 // There are special ways we can lower some single-element blends.
9726 if (NumV2Elements == 1)
9727 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9728 Mask, Subtarget, DAG))
9731 // Check whether a compaction lowering can be done. This handles shuffles
9732 // which take every Nth element for some even N. See the helper function for
9735 // We special case these as they can be particularly efficiently handled with
9736 // the PACKUSB instruction on x86 and they show up in common patterns of
9737 // rearranging bytes to truncate wide elements.
9738 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9739 // NumEvenDrops is the power of two stride of the elements. Another way of
9740 // thinking about it is that we need to drop the even elements this many
9741 // times to get the original input.
9742 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9744 // First we need to zero all the dropped bytes.
9745 assert(NumEvenDrops <= 3 &&
9746 "No support for dropping even elements more than 3 times.");
9747 // We use the mask type to pick which bytes are preserved based on how many
9748 // elements are dropped.
9749 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9750 SDValue ByteClearMask =
9751 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9752 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9753 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9755 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9757 // Now pack things back together.
9758 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9759 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9760 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9761 for (int i = 1; i < NumEvenDrops; ++i) {
9762 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9763 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9769 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9770 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9771 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9772 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9774 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9775 MutableArrayRef<int> V1HalfBlendMask,
9776 MutableArrayRef<int> V2HalfBlendMask) {
9777 for (int i = 0; i < 8; ++i)
9778 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9779 V1HalfBlendMask[i] = HalfMask[i];
9781 } else if (HalfMask[i] >= 16) {
9782 V2HalfBlendMask[i] = HalfMask[i] - 16;
9783 HalfMask[i] = i + 8;
9786 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9787 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9789 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9791 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9792 MutableArrayRef<int> HiBlendMask) {
9794 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9795 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9797 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9798 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9799 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9800 [](int M) { return M >= 0 && M % 2 == 1; })) {
9801 // Use a mask to drop the high bytes.
9802 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9803 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9804 DAG.getConstant(0x00FF, MVT::v8i16));
9806 // This will be a single vector shuffle instead of a blend so nuke V2.
9807 V2 = DAG.getUNDEF(MVT::v8i16);
9809 // Squash the masks to point directly into V1.
9810 for (int &M : LoBlendMask)
9813 for (int &M : HiBlendMask)
9817 // Otherwise just unpack the low half of V into V1 and the high half into
9818 // V2 so that we can blend them as i16s.
9819 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9820 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9821 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9822 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9825 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9826 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9827 return std::make_pair(BlendedLo, BlendedHi);
9829 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9830 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9831 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9833 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9834 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9836 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9839 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9841 /// This routine breaks down the specific type of 128-bit shuffle and
9842 /// dispatches to the lowering routines accordingly.
9843 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9844 MVT VT, const X86Subtarget *Subtarget,
9845 SelectionDAG &DAG) {
9846 switch (VT.SimpleTy) {
9848 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9850 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9852 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9854 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9856 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9858 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9861 llvm_unreachable("Unimplemented!");
9865 /// \brief Helper function to test whether a shuffle mask could be
9866 /// simplified by widening the elements being shuffled.
9868 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9869 /// leaves it in an unspecified state.
9871 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9872 /// shuffle masks. The latter have the special property of a '-2' representing
9873 /// a zero-ed lane of a vector.
9874 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9875 SmallVectorImpl<int> &WidenedMask) {
9876 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9877 // If both elements are undef, its trivial.
9878 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9879 WidenedMask.push_back(SM_SentinelUndef);
9883 // Check for an undef mask and a mask value properly aligned to fit with
9884 // a pair of values. If we find such a case, use the non-undef mask's value.
9885 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9886 WidenedMask.push_back(Mask[i + 1] / 2);
9889 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9890 WidenedMask.push_back(Mask[i] / 2);
9894 // When zeroing, we need to spread the zeroing across both lanes to widen.
9895 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9896 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9897 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9898 WidenedMask.push_back(SM_SentinelZero);
9904 // Finally check if the two mask values are adjacent and aligned with
9906 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9907 WidenedMask.push_back(Mask[i] / 2);
9911 // Otherwise we can't safely widen the elements used in this shuffle.
9914 assert(WidenedMask.size() == Mask.size() / 2 &&
9915 "Incorrect size of mask after widening the elements!");
9920 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9922 /// This routine just extracts two subvectors, shuffles them independently, and
9923 /// then concatenates them back together. This should work effectively with all
9924 /// AVX vector shuffle types.
9925 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9926 SDValue V2, ArrayRef<int> Mask,
9927 SelectionDAG &DAG) {
9928 assert(VT.getSizeInBits() >= 256 &&
9929 "Only for 256-bit or wider vector shuffles!");
9930 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9931 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9933 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9934 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9936 int NumElements = VT.getVectorNumElements();
9937 int SplitNumElements = NumElements / 2;
9938 MVT ScalarVT = VT.getScalarType();
9939 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9941 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9942 DAG.getIntPtrConstant(0));
9943 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9944 DAG.getIntPtrConstant(SplitNumElements));
9945 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9946 DAG.getIntPtrConstant(0));
9947 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9948 DAG.getIntPtrConstant(SplitNumElements));
9950 // Now create two 4-way blends of these half-width vectors.
9951 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9952 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9953 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9954 for (int i = 0; i < SplitNumElements; ++i) {
9955 int M = HalfMask[i];
9956 if (M >= NumElements) {
9957 if (M >= NumElements + SplitNumElements)
9961 V2BlendMask.push_back(M - NumElements);
9962 V1BlendMask.push_back(-1);
9963 BlendMask.push_back(SplitNumElements + i);
9964 } else if (M >= 0) {
9965 if (M >= SplitNumElements)
9969 V2BlendMask.push_back(-1);
9970 V1BlendMask.push_back(M);
9971 BlendMask.push_back(i);
9973 V2BlendMask.push_back(-1);
9974 V1BlendMask.push_back(-1);
9975 BlendMask.push_back(-1);
9979 // Because the lowering happens after all combining takes place, we need to
9980 // manually combine these blend masks as much as possible so that we create
9981 // a minimal number of high-level vector shuffle nodes.
9983 // First try just blending the halves of V1 or V2.
9984 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9985 return DAG.getUNDEF(SplitVT);
9986 if (!UseLoV2 && !UseHiV2)
9987 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9988 if (!UseLoV1 && !UseHiV1)
9989 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9991 SDValue V1Blend, V2Blend;
9992 if (UseLoV1 && UseHiV1) {
9994 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9996 // We only use half of V1 so map the usage down into the final blend mask.
9997 V1Blend = UseLoV1 ? LoV1 : HiV1;
9998 for (int i = 0; i < SplitNumElements; ++i)
9999 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
10000 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
10002 if (UseLoV2 && UseHiV2) {
10004 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10006 // We only use half of V2 so map the usage down into the final blend mask.
10007 V2Blend = UseLoV2 ? LoV2 : HiV2;
10008 for (int i = 0; i < SplitNumElements; ++i)
10009 if (BlendMask[i] >= SplitNumElements)
10010 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
10012 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
10014 SDValue Lo = HalfBlend(LoMask);
10015 SDValue Hi = HalfBlend(HiMask);
10016 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
10019 /// \brief Either split a vector in halves or decompose the shuffles and the
10022 /// This is provided as a good fallback for many lowerings of non-single-input
10023 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10024 /// between splitting the shuffle into 128-bit components and stitching those
10025 /// back together vs. extracting the single-input shuffles and blending those
10027 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10028 SDValue V2, ArrayRef<int> Mask,
10029 SelectionDAG &DAG) {
10030 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10031 "lower single-input shuffles as it "
10032 "could then recurse on itself.");
10033 int Size = Mask.size();
10035 // If this can be modeled as a broadcast of two elements followed by a blend,
10036 // prefer that lowering. This is especially important because broadcasts can
10037 // often fold with memory operands.
10038 auto DoBothBroadcast = [&] {
10039 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10042 if (V2BroadcastIdx == -1)
10043 V2BroadcastIdx = M - Size;
10044 else if (M - Size != V2BroadcastIdx)
10046 } else if (M >= 0) {
10047 if (V1BroadcastIdx == -1)
10048 V1BroadcastIdx = M;
10049 else if (M != V1BroadcastIdx)
10054 if (DoBothBroadcast())
10055 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10058 // If the inputs all stem from a single 128-bit lane of each input, then we
10059 // split them rather than blending because the split will decompose to
10060 // unusually few instructions.
10061 int LaneCount = VT.getSizeInBits() / 128;
10062 int LaneSize = Size / LaneCount;
10063 SmallBitVector LaneInputs[2];
10064 LaneInputs[0].resize(LaneCount, false);
10065 LaneInputs[1].resize(LaneCount, false);
10066 for (int i = 0; i < Size; ++i)
10068 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10069 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10070 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10072 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10073 // that the decomposed single-input shuffles don't end up here.
10074 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10077 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10078 /// a permutation and blend of those lanes.
10080 /// This essentially blends the out-of-lane inputs to each lane into the lane
10081 /// from a permuted copy of the vector. This lowering strategy results in four
10082 /// instructions in the worst case for a single-input cross lane shuffle which
10083 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10084 /// of. Special cases for each particular shuffle pattern should be handled
10085 /// prior to trying this lowering.
10086 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10087 SDValue V1, SDValue V2,
10088 ArrayRef<int> Mask,
10089 SelectionDAG &DAG) {
10090 // FIXME: This should probably be generalized for 512-bit vectors as well.
10091 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
10092 int LaneSize = Mask.size() / 2;
10094 // If there are only inputs from one 128-bit lane, splitting will in fact be
10095 // less expensive. The flags track wether the given lane contains an element
10096 // that crosses to another lane.
10097 bool LaneCrossing[2] = {false, false};
10098 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10099 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10100 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10101 if (!LaneCrossing[0] || !LaneCrossing[1])
10102 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10104 if (isSingleInputShuffleMask(Mask)) {
10105 SmallVector<int, 32> FlippedBlendMask;
10106 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10107 FlippedBlendMask.push_back(
10108 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10110 : Mask[i] % LaneSize +
10111 (i / LaneSize) * LaneSize + Size));
10113 // Flip the vector, and blend the results which should now be in-lane. The
10114 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10115 // 5 for the high source. The value 3 selects the high half of source 2 and
10116 // the value 2 selects the low half of source 2. We only use source 2 to
10117 // allow folding it into a memory operand.
10118 unsigned PERMMask = 3 | 2 << 4;
10119 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10120 V1, DAG.getConstant(PERMMask, MVT::i8));
10121 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10124 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10125 // will be handled by the above logic and a blend of the results, much like
10126 // other patterns in AVX.
10127 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10130 /// \brief Handle lowering 2-lane 128-bit shuffles.
10131 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10132 SDValue V2, ArrayRef<int> Mask,
10133 const X86Subtarget *Subtarget,
10134 SelectionDAG &DAG) {
10135 // Blends are faster and handle all the non-lane-crossing cases.
10136 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10140 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10141 VT.getVectorNumElements() / 2);
10142 // Check for patterns which can be matched with a single insert of a 128-bit
10144 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10145 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10146 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10147 DAG.getIntPtrConstant(0));
10148 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10149 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10150 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10152 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10153 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10154 DAG.getIntPtrConstant(0));
10155 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10156 DAG.getIntPtrConstant(2));
10157 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10160 // Otherwise form a 128-bit permutation.
10161 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10162 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10163 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10164 DAG.getConstant(PermMask, MVT::i8));
10167 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10168 /// shuffling each lane.
10170 /// This will only succeed when the result of fixing the 128-bit lanes results
10171 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10172 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10173 /// the lane crosses early and then use simpler shuffles within each lane.
10175 /// FIXME: It might be worthwhile at some point to support this without
10176 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10177 /// in x86 only floating point has interesting non-repeating shuffles, and even
10178 /// those are still *marginally* more expensive.
10179 static SDValue lowerVectorShuffleByMerging128BitLanes(
10180 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10181 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10182 assert(!isSingleInputShuffleMask(Mask) &&
10183 "This is only useful with multiple inputs.");
10185 int Size = Mask.size();
10186 int LaneSize = 128 / VT.getScalarSizeInBits();
10187 int NumLanes = Size / LaneSize;
10188 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10190 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10191 // check whether the in-128-bit lane shuffles share a repeating pattern.
10192 SmallVector<int, 4> Lanes;
10193 Lanes.resize(NumLanes, -1);
10194 SmallVector<int, 4> InLaneMask;
10195 InLaneMask.resize(LaneSize, -1);
10196 for (int i = 0; i < Size; ++i) {
10200 int j = i / LaneSize;
10202 if (Lanes[j] < 0) {
10203 // First entry we've seen for this lane.
10204 Lanes[j] = Mask[i] / LaneSize;
10205 } else if (Lanes[j] != Mask[i] / LaneSize) {
10206 // This doesn't match the lane selected previously!
10210 // Check that within each lane we have a consistent shuffle mask.
10211 int k = i % LaneSize;
10212 if (InLaneMask[k] < 0) {
10213 InLaneMask[k] = Mask[i] % LaneSize;
10214 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10215 // This doesn't fit a repeating in-lane mask.
10220 // First shuffle the lanes into place.
10221 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10222 VT.getSizeInBits() / 64);
10223 SmallVector<int, 8> LaneMask;
10224 LaneMask.resize(NumLanes * 2, -1);
10225 for (int i = 0; i < NumLanes; ++i)
10226 if (Lanes[i] >= 0) {
10227 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10228 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10231 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10232 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10233 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10235 // Cast it back to the type we actually want.
10236 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10238 // Now do a simple shuffle that isn't lane crossing.
10239 SmallVector<int, 8> NewMask;
10240 NewMask.resize(Size, -1);
10241 for (int i = 0; i < Size; ++i)
10243 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10244 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10245 "Must not introduce lane crosses at this point!");
10247 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10250 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10253 /// This returns true if the elements from a particular input are already in the
10254 /// slot required by the given mask and require no permutation.
10255 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10256 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10257 int Size = Mask.size();
10258 for (int i = 0; i < Size; ++i)
10259 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10265 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10267 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10268 /// isn't available.
10269 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10270 const X86Subtarget *Subtarget,
10271 SelectionDAG &DAG) {
10273 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10274 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10275 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10276 ArrayRef<int> Mask = SVOp->getMask();
10277 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10279 SmallVector<int, 4> WidenedMask;
10280 if (canWidenShuffleElements(Mask, WidenedMask))
10281 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10284 if (isSingleInputShuffleMask(Mask)) {
10285 // Check for being able to broadcast a single element.
10286 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10287 Mask, Subtarget, DAG))
10290 // Use low duplicate instructions for masks that match their pattern.
10291 if (isShuffleEquivalent(Mask, 0, 0, 2, 2))
10292 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10294 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10295 // Non-half-crossing single input shuffles can be lowerid with an
10296 // interleaved permutation.
10297 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10298 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10299 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10300 DAG.getConstant(VPERMILPMask, MVT::i8));
10303 // With AVX2 we have direct support for this permutation.
10304 if (Subtarget->hasAVX2())
10305 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10306 getV4X86ShuffleImm8ForMask(Mask, DAG));
10308 // Otherwise, fall back.
10309 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10313 // X86 has dedicated unpack instructions that can handle specific blend
10314 // operations: UNPCKH and UNPCKL.
10315 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10316 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10317 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10318 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10320 // If we have a single input to the zero element, insert that into V1 if we
10321 // can do so cheaply.
10322 int NumV2Elements =
10323 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10324 if (NumV2Elements == 1 && Mask[0] >= 4)
10325 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10326 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10329 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10333 // Check if the blend happens to exactly fit that of SHUFPD.
10334 if ((Mask[0] == -1 || Mask[0] < 2) &&
10335 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10336 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10337 (Mask[3] == -1 || Mask[3] >= 6)) {
10338 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10339 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10340 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10341 DAG.getConstant(SHUFPDMask, MVT::i8));
10343 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10344 (Mask[1] == -1 || Mask[1] < 2) &&
10345 (Mask[2] == -1 || Mask[2] >= 6) &&
10346 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10347 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10348 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10349 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10350 DAG.getConstant(SHUFPDMask, MVT::i8));
10353 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10354 // shuffle. However, if we have AVX2 and either inputs are already in place,
10355 // we will be able to shuffle even across lanes the other input in a single
10356 // instruction so skip this pattern.
10357 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10358 isShuffleMaskInputInPlace(1, Mask))))
10359 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10360 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10363 // If we have AVX2 then we always want to lower with a blend because an v4 we
10364 // can fully permute the elements.
10365 if (Subtarget->hasAVX2())
10366 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10369 // Otherwise fall back on generic lowering.
10370 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10373 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10375 /// This routine is only called when we have AVX2 and thus a reasonable
10376 /// instruction set for v4i64 shuffling..
10377 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10378 const X86Subtarget *Subtarget,
10379 SelectionDAG &DAG) {
10381 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10382 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10383 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10384 ArrayRef<int> Mask = SVOp->getMask();
10385 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10386 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10388 SmallVector<int, 4> WidenedMask;
10389 if (canWidenShuffleElements(Mask, WidenedMask))
10390 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10393 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10397 // Check for being able to broadcast a single element.
10398 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10399 Mask, Subtarget, DAG))
10402 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10403 // use lower latency instructions that will operate on both 128-bit lanes.
10404 SmallVector<int, 2> RepeatedMask;
10405 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10406 if (isSingleInputShuffleMask(Mask)) {
10407 int PSHUFDMask[] = {-1, -1, -1, -1};
10408 for (int i = 0; i < 2; ++i)
10409 if (RepeatedMask[i] >= 0) {
10410 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10411 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10413 return DAG.getNode(
10414 ISD::BITCAST, DL, MVT::v4i64,
10415 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10416 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10417 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10420 // Use dedicated unpack instructions for masks that match their pattern.
10421 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10422 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10423 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10424 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10427 // AVX2 provides a direct instruction for permuting a single input across
10429 if (isSingleInputShuffleMask(Mask))
10430 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10431 getV4X86ShuffleImm8ForMask(Mask, DAG));
10433 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10434 // shuffle. However, if we have AVX2 and either inputs are already in place,
10435 // we will be able to shuffle even across lanes the other input in a single
10436 // instruction so skip this pattern.
10437 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10438 isShuffleMaskInputInPlace(1, Mask))))
10439 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10440 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10443 // Otherwise fall back on generic blend lowering.
10444 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10448 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10450 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10451 /// isn't available.
10452 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10453 const X86Subtarget *Subtarget,
10454 SelectionDAG &DAG) {
10456 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10457 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10459 ArrayRef<int> Mask = SVOp->getMask();
10460 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10462 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10466 // Check for being able to broadcast a single element.
10467 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10468 Mask, Subtarget, DAG))
10471 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10472 // options to efficiently lower the shuffle.
10473 SmallVector<int, 4> RepeatedMask;
10474 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10475 assert(RepeatedMask.size() == 4 &&
10476 "Repeated masks must be half the mask width!");
10478 // Use even/odd duplicate instructions for masks that match their pattern.
10479 if (isShuffleEquivalent(Mask, 0, 0, 2, 2, 4, 4, 6, 6))
10480 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10481 if (isShuffleEquivalent(Mask, 1, 1, 3, 3, 5, 5, 7, 7))
10482 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10484 if (isSingleInputShuffleMask(Mask))
10485 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10486 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10488 // Use dedicated unpack instructions for masks that match their pattern.
10489 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10490 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10491 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10492 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10494 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10495 // have already handled any direct blends. We also need to squash the
10496 // repeated mask into a simulated v4f32 mask.
10497 for (int i = 0; i < 4; ++i)
10498 if (RepeatedMask[i] >= 8)
10499 RepeatedMask[i] -= 4;
10500 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10503 // If we have a single input shuffle with different shuffle patterns in the
10504 // two 128-bit lanes use the variable mask to VPERMILPS.
10505 if (isSingleInputShuffleMask(Mask)) {
10506 SDValue VPermMask[8];
10507 for (int i = 0; i < 8; ++i)
10508 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10509 : DAG.getConstant(Mask[i], MVT::i32);
10510 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10511 return DAG.getNode(
10512 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10513 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10515 if (Subtarget->hasAVX2())
10516 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10517 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10518 DAG.getNode(ISD::BUILD_VECTOR, DL,
10519 MVT::v8i32, VPermMask)),
10522 // Otherwise, fall back.
10523 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10527 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10529 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10530 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10533 // If we have AVX2 then we always want to lower with a blend because at v8 we
10534 // can fully permute the elements.
10535 if (Subtarget->hasAVX2())
10536 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10539 // Otherwise fall back on generic lowering.
10540 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10543 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10545 /// This routine is only called when we have AVX2 and thus a reasonable
10546 /// instruction set for v8i32 shuffling..
10547 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10548 const X86Subtarget *Subtarget,
10549 SelectionDAG &DAG) {
10551 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10552 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10553 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10554 ArrayRef<int> Mask = SVOp->getMask();
10555 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10556 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10558 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10562 // Check for being able to broadcast a single element.
10563 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10564 Mask, Subtarget, DAG))
10567 // If the shuffle mask is repeated in each 128-bit lane we can use more
10568 // efficient instructions that mirror the shuffles across the two 128-bit
10570 SmallVector<int, 4> RepeatedMask;
10571 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10572 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10573 if (isSingleInputShuffleMask(Mask))
10574 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10575 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10577 // Use dedicated unpack instructions for masks that match their pattern.
10578 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10579 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10580 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10581 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10584 // If the shuffle patterns aren't repeated but it is a single input, directly
10585 // generate a cross-lane VPERMD instruction.
10586 if (isSingleInputShuffleMask(Mask)) {
10587 SDValue VPermMask[8];
10588 for (int i = 0; i < 8; ++i)
10589 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10590 : DAG.getConstant(Mask[i], MVT::i32);
10591 return DAG.getNode(
10592 X86ISD::VPERMV, DL, MVT::v8i32,
10593 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10596 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10598 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10599 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10602 // Otherwise fall back on generic blend lowering.
10603 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10607 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10609 /// This routine is only called when we have AVX2 and thus a reasonable
10610 /// instruction set for v16i16 shuffling..
10611 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10612 const X86Subtarget *Subtarget,
10613 SelectionDAG &DAG) {
10615 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10616 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10617 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10618 ArrayRef<int> Mask = SVOp->getMask();
10619 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10620 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10622 // Check for being able to broadcast a single element.
10623 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10624 Mask, Subtarget, DAG))
10627 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10631 // Use dedicated unpack instructions for masks that match their pattern.
10632 if (isShuffleEquivalent(Mask,
10633 // First 128-bit lane:
10634 0, 16, 1, 17, 2, 18, 3, 19,
10635 // Second 128-bit lane:
10636 8, 24, 9, 25, 10, 26, 11, 27))
10637 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10638 if (isShuffleEquivalent(Mask,
10639 // First 128-bit lane:
10640 4, 20, 5, 21, 6, 22, 7, 23,
10641 // Second 128-bit lane:
10642 12, 28, 13, 29, 14, 30, 15, 31))
10643 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10645 if (isSingleInputShuffleMask(Mask)) {
10646 // There are no generalized cross-lane shuffle operations available on i16
10648 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10649 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10652 SDValue PSHUFBMask[32];
10653 for (int i = 0; i < 16; ++i) {
10654 if (Mask[i] == -1) {
10655 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10659 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10660 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10661 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10662 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10664 return DAG.getNode(
10665 ISD::BITCAST, DL, MVT::v16i16,
10667 X86ISD::PSHUFB, DL, MVT::v32i8,
10668 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10669 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10672 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10674 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10675 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10678 // Otherwise fall back on generic lowering.
10679 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10682 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10684 /// This routine is only called when we have AVX2 and thus a reasonable
10685 /// instruction set for v32i8 shuffling..
10686 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10687 const X86Subtarget *Subtarget,
10688 SelectionDAG &DAG) {
10690 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10691 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10692 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10693 ArrayRef<int> Mask = SVOp->getMask();
10694 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10695 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10697 // Check for being able to broadcast a single element.
10698 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10699 Mask, Subtarget, DAG))
10702 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10706 // Use dedicated unpack instructions for masks that match their pattern.
10707 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10709 if (isShuffleEquivalent(
10711 // First 128-bit lane:
10712 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10713 // Second 128-bit lane:
10714 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10715 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10716 if (isShuffleEquivalent(
10718 // First 128-bit lane:
10719 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10720 // Second 128-bit lane:
10721 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10722 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10724 if (isSingleInputShuffleMask(Mask)) {
10725 // There are no generalized cross-lane shuffle operations available on i8
10727 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10728 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10731 SDValue PSHUFBMask[32];
10732 for (int i = 0; i < 32; ++i)
10735 ? DAG.getUNDEF(MVT::i8)
10736 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10738 return DAG.getNode(
10739 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10740 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10743 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10745 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10746 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10749 // Otherwise fall back on generic lowering.
10750 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10753 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10755 /// This routine either breaks down the specific type of a 256-bit x86 vector
10756 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10757 /// together based on the available instructions.
10758 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10759 MVT VT, const X86Subtarget *Subtarget,
10760 SelectionDAG &DAG) {
10762 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10763 ArrayRef<int> Mask = SVOp->getMask();
10765 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10766 // check for those subtargets here and avoid much of the subtarget querying in
10767 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10768 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10769 // floating point types there eventually, just immediately cast everything to
10770 // a float and operate entirely in that domain.
10771 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10772 int ElementBits = VT.getScalarSizeInBits();
10773 if (ElementBits < 32)
10774 // No floating point type available, decompose into 128-bit vectors.
10775 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10777 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10778 VT.getVectorNumElements());
10779 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10780 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10781 return DAG.getNode(ISD::BITCAST, DL, VT,
10782 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10785 switch (VT.SimpleTy) {
10787 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10789 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10791 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10793 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10795 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10797 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10800 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10804 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10805 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10806 const X86Subtarget *Subtarget,
10807 SelectionDAG &DAG) {
10809 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10810 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10811 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10812 ArrayRef<int> Mask = SVOp->getMask();
10813 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10815 // X86 has dedicated unpack instructions that can handle specific blend
10816 // operations: UNPCKH and UNPCKL.
10817 if (isShuffleEquivalent(Mask, 0, 8, 2, 10, 4, 12, 6, 14))
10818 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10819 if (isShuffleEquivalent(Mask, 1, 9, 3, 11, 5, 13, 7, 15))
10820 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10822 // FIXME: Implement direct support for this type!
10823 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10826 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10827 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10828 const X86Subtarget *Subtarget,
10829 SelectionDAG &DAG) {
10831 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10832 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10833 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10834 ArrayRef<int> Mask = SVOp->getMask();
10835 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10837 // Use dedicated unpack instructions for masks that match their pattern.
10838 if (isShuffleEquivalent(Mask,
10839 0, 16, 1, 17, 4, 20, 5, 21,
10840 8, 24, 9, 25, 12, 28, 13, 29))
10841 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10842 if (isShuffleEquivalent(Mask,
10843 2, 18, 3, 19, 6, 22, 7, 23,
10844 10, 26, 11, 27, 14, 30, 15, 31))
10845 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10847 // FIXME: Implement direct support for this type!
10848 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10851 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10852 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10853 const X86Subtarget *Subtarget,
10854 SelectionDAG &DAG) {
10856 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10857 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10858 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10859 ArrayRef<int> Mask = SVOp->getMask();
10860 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10862 // X86 has dedicated unpack instructions that can handle specific blend
10863 // operations: UNPCKH and UNPCKL.
10864 if (isShuffleEquivalent(Mask, 0, 8, 2, 10, 4, 12, 6, 14))
10865 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10866 if (isShuffleEquivalent(Mask, 1, 9, 3, 11, 5, 13, 7, 15))
10867 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10869 // FIXME: Implement direct support for this type!
10870 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10873 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10874 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10875 const X86Subtarget *Subtarget,
10876 SelectionDAG &DAG) {
10878 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10879 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10881 ArrayRef<int> Mask = SVOp->getMask();
10882 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10884 // Use dedicated unpack instructions for masks that match their pattern.
10885 if (isShuffleEquivalent(Mask,
10886 0, 16, 1, 17, 4, 20, 5, 21,
10887 8, 24, 9, 25, 12, 28, 13, 29))
10888 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10889 if (isShuffleEquivalent(Mask,
10890 2, 18, 3, 19, 6, 22, 7, 23,
10891 10, 26, 11, 27, 14, 30, 15, 31))
10892 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10894 // FIXME: Implement direct support for this type!
10895 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10898 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10899 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10900 const X86Subtarget *Subtarget,
10901 SelectionDAG &DAG) {
10903 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10904 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10905 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10906 ArrayRef<int> Mask = SVOp->getMask();
10907 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10908 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10910 // FIXME: Implement direct support for this type!
10911 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10914 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10915 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10916 const X86Subtarget *Subtarget,
10917 SelectionDAG &DAG) {
10919 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10920 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10921 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10922 ArrayRef<int> Mask = SVOp->getMask();
10923 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10924 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10926 // FIXME: Implement direct support for this type!
10927 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10930 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10932 /// This routine either breaks down the specific type of a 512-bit x86 vector
10933 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10934 /// together based on the available instructions.
10935 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10936 MVT VT, const X86Subtarget *Subtarget,
10937 SelectionDAG &DAG) {
10939 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10940 ArrayRef<int> Mask = SVOp->getMask();
10941 assert(Subtarget->hasAVX512() &&
10942 "Cannot lower 512-bit vectors w/ basic ISA!");
10944 // Check for being able to broadcast a single element.
10945 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10946 Mask, Subtarget, DAG))
10949 // Dispatch to each element type for lowering. If we don't have supprot for
10950 // specific element type shuffles at 512 bits, immediately split them and
10951 // lower them. Each lowering routine of a given type is allowed to assume that
10952 // the requisite ISA extensions for that element type are available.
10953 switch (VT.SimpleTy) {
10955 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10957 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10959 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10961 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10963 if (Subtarget->hasBWI())
10964 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10967 if (Subtarget->hasBWI())
10968 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10972 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10975 // Otherwise fall back on splitting.
10976 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10979 /// \brief Top-level lowering for x86 vector shuffles.
10981 /// This handles decomposition, canonicalization, and lowering of all x86
10982 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10983 /// above in helper routines. The canonicalization attempts to widen shuffles
10984 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10985 /// s.t. only one of the two inputs needs to be tested, etc.
10986 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10987 SelectionDAG &DAG) {
10988 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10989 ArrayRef<int> Mask = SVOp->getMask();
10990 SDValue V1 = Op.getOperand(0);
10991 SDValue V2 = Op.getOperand(1);
10992 MVT VT = Op.getSimpleValueType();
10993 int NumElements = VT.getVectorNumElements();
10996 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10998 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10999 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11000 if (V1IsUndef && V2IsUndef)
11001 return DAG.getUNDEF(VT);
11003 // When we create a shuffle node we put the UNDEF node to second operand,
11004 // but in some cases the first operand may be transformed to UNDEF.
11005 // In this case we should just commute the node.
11007 return DAG.getCommutedVectorShuffle(*SVOp);
11009 // Check for non-undef masks pointing at an undef vector and make the masks
11010 // undef as well. This makes it easier to match the shuffle based solely on
11014 if (M >= NumElements) {
11015 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11016 for (int &M : NewMask)
11017 if (M >= NumElements)
11019 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11022 // Try to collapse shuffles into using a vector type with fewer elements but
11023 // wider element types. We cap this to not form integers or floating point
11024 // elements wider than 64 bits, but it might be interesting to form i128
11025 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11026 SmallVector<int, 16> WidenedMask;
11027 if (VT.getScalarSizeInBits() < 64 &&
11028 canWidenShuffleElements(Mask, WidenedMask)) {
11029 MVT NewEltVT = VT.isFloatingPoint()
11030 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11031 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11032 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11033 // Make sure that the new vector type is legal. For example, v2f64 isn't
11035 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11036 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
11037 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
11038 return DAG.getNode(ISD::BITCAST, dl, VT,
11039 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11043 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11044 for (int M : SVOp->getMask())
11046 ++NumUndefElements;
11047 else if (M < NumElements)
11052 // Commute the shuffle as needed such that more elements come from V1 than
11053 // V2. This allows us to match the shuffle pattern strictly on how many
11054 // elements come from V1 without handling the symmetric cases.
11055 if (NumV2Elements > NumV1Elements)
11056 return DAG.getCommutedVectorShuffle(*SVOp);
11058 // When the number of V1 and V2 elements are the same, try to minimize the
11059 // number of uses of V2 in the low half of the vector. When that is tied,
11060 // ensure that the sum of indices for V1 is equal to or lower than the sum
11061 // indices for V2. When those are equal, try to ensure that the number of odd
11062 // indices for V1 is lower than the number of odd indices for V2.
11063 if (NumV1Elements == NumV2Elements) {
11064 int LowV1Elements = 0, LowV2Elements = 0;
11065 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11066 if (M >= NumElements)
11070 if (LowV2Elements > LowV1Elements) {
11071 return DAG.getCommutedVectorShuffle(*SVOp);
11072 } else if (LowV2Elements == LowV1Elements) {
11073 int SumV1Indices = 0, SumV2Indices = 0;
11074 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11075 if (SVOp->getMask()[i] >= NumElements)
11077 else if (SVOp->getMask()[i] >= 0)
11079 if (SumV2Indices < SumV1Indices) {
11080 return DAG.getCommutedVectorShuffle(*SVOp);
11081 } else if (SumV2Indices == SumV1Indices) {
11082 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11083 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11084 if (SVOp->getMask()[i] >= NumElements)
11085 NumV2OddIndices += i % 2;
11086 else if (SVOp->getMask()[i] >= 0)
11087 NumV1OddIndices += i % 2;
11088 if (NumV2OddIndices < NumV1OddIndices)
11089 return DAG.getCommutedVectorShuffle(*SVOp);
11094 // For each vector width, delegate to a specialized lowering routine.
11095 if (VT.getSizeInBits() == 128)
11096 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11098 if (VT.getSizeInBits() == 256)
11099 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11101 // Force AVX-512 vectors to be scalarized for now.
11102 // FIXME: Implement AVX-512 support!
11103 if (VT.getSizeInBits() == 512)
11104 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11106 llvm_unreachable("Unimplemented!");
11110 //===----------------------------------------------------------------------===//
11111 // Legacy vector shuffle lowering
11113 // This code is the legacy code handling vector shuffles until the above
11114 // replaces its functionality and performance.
11115 //===----------------------------------------------------------------------===//
11117 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
11118 bool hasInt256, unsigned *MaskOut = nullptr) {
11119 MVT EltVT = VT.getVectorElementType();
11121 // There is no blend with immediate in AVX-512.
11122 if (VT.is512BitVector())
11125 if (!hasSSE41 || EltVT == MVT::i8)
11127 if (!hasInt256 && VT == MVT::v16i16)
11130 unsigned MaskValue = 0;
11131 unsigned NumElems = VT.getVectorNumElements();
11132 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11133 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11134 unsigned NumElemsInLane = NumElems / NumLanes;
11136 // Blend for v16i16 should be symetric for the both lanes.
11137 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11139 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
11140 int EltIdx = MaskVals[i];
11142 if ((EltIdx < 0 || EltIdx == (int)i) &&
11143 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
11146 if (((unsigned)EltIdx == (i + NumElems)) &&
11147 (SndLaneEltIdx < 0 ||
11148 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
11149 MaskValue |= (1 << i);
11155 *MaskOut = MaskValue;
11159 // Try to lower a shuffle node into a simple blend instruction.
11160 // This function assumes isBlendMask returns true for this
11161 // SuffleVectorSDNode
11162 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
11163 unsigned MaskValue,
11164 const X86Subtarget *Subtarget,
11165 SelectionDAG &DAG) {
11166 MVT VT = SVOp->getSimpleValueType(0);
11167 MVT EltVT = VT.getVectorElementType();
11168 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11169 Subtarget->hasInt256() && "Trying to lower a "
11170 "VECTOR_SHUFFLE to a Blend but "
11171 "with the wrong mask"));
11172 SDValue V1 = SVOp->getOperand(0);
11173 SDValue V2 = SVOp->getOperand(1);
11175 unsigned NumElems = VT.getVectorNumElements();
11177 // Convert i32 vectors to floating point if it is not AVX2.
11178 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11180 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11181 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11183 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11184 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11187 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11188 DAG.getConstant(MaskValue, MVT::i32));
11189 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11192 /// In vector type \p VT, return true if the element at index \p InputIdx
11193 /// falls on a different 128-bit lane than \p OutputIdx.
11194 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11195 unsigned OutputIdx) {
11196 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11197 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11200 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11201 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11202 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11203 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11205 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11206 SelectionDAG &DAG) {
11207 MVT VT = V1.getSimpleValueType();
11208 assert(VT.is128BitVector() || VT.is256BitVector());
11210 MVT EltVT = VT.getVectorElementType();
11211 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11212 unsigned NumElts = VT.getVectorNumElements();
11214 SmallVector<SDValue, 32> PshufbMask;
11215 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11216 int InputIdx = MaskVals[OutputIdx];
11217 unsigned InputByteIdx;
11219 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11220 InputByteIdx = 0x80;
11222 // Cross lane is not allowed.
11223 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11225 InputByteIdx = InputIdx * EltSizeInBytes;
11226 // Index is an byte offset within the 128-bit lane.
11227 InputByteIdx &= 0xf;
11230 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11231 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11232 if (InputByteIdx != 0x80)
11237 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11239 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11240 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11241 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11244 // v8i16 shuffles - Prefer shuffles in the following order:
11245 // 1. [all] pshuflw, pshufhw, optional move
11246 // 2. [ssse3] 1 x pshufb
11247 // 3. [ssse3] 2 x pshufb + 1 x por
11248 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11250 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11251 SelectionDAG &DAG) {
11252 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11253 SDValue V1 = SVOp->getOperand(0);
11254 SDValue V2 = SVOp->getOperand(1);
11256 SmallVector<int, 8> MaskVals;
11258 // Determine if more than 1 of the words in each of the low and high quadwords
11259 // of the result come from the same quadword of one of the two inputs. Undef
11260 // mask values count as coming from any quadword, for better codegen.
11262 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11263 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11264 unsigned LoQuad[] = { 0, 0, 0, 0 };
11265 unsigned HiQuad[] = { 0, 0, 0, 0 };
11266 // Indices of quads used.
11267 std::bitset<4> InputQuads;
11268 for (unsigned i = 0; i < 8; ++i) {
11269 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11270 int EltIdx = SVOp->getMaskElt(i);
11271 MaskVals.push_back(EltIdx);
11279 ++Quad[EltIdx / 4];
11280 InputQuads.set(EltIdx / 4);
11283 int BestLoQuad = -1;
11284 unsigned MaxQuad = 1;
11285 for (unsigned i = 0; i < 4; ++i) {
11286 if (LoQuad[i] > MaxQuad) {
11288 MaxQuad = LoQuad[i];
11292 int BestHiQuad = -1;
11294 for (unsigned i = 0; i < 4; ++i) {
11295 if (HiQuad[i] > MaxQuad) {
11297 MaxQuad = HiQuad[i];
11301 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11302 // of the two input vectors, shuffle them into one input vector so only a
11303 // single pshufb instruction is necessary. If there are more than 2 input
11304 // quads, disable the next transformation since it does not help SSSE3.
11305 bool V1Used = InputQuads[0] || InputQuads[1];
11306 bool V2Used = InputQuads[2] || InputQuads[3];
11307 if (Subtarget->hasSSSE3()) {
11308 if (InputQuads.count() == 2 && V1Used && V2Used) {
11309 BestLoQuad = InputQuads[0] ? 0 : 1;
11310 BestHiQuad = InputQuads[2] ? 2 : 3;
11312 if (InputQuads.count() > 2) {
11318 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11319 // the shuffle mask. If a quad is scored as -1, that means that it contains
11320 // words from all 4 input quadwords.
11322 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11324 BestLoQuad < 0 ? 0 : BestLoQuad,
11325 BestHiQuad < 0 ? 1 : BestHiQuad
11327 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11328 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11329 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11330 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11332 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11333 // source words for the shuffle, to aid later transformations.
11334 bool AllWordsInNewV = true;
11335 bool InOrder[2] = { true, true };
11336 for (unsigned i = 0; i != 8; ++i) {
11337 int idx = MaskVals[i];
11339 InOrder[i/4] = false;
11340 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11342 AllWordsInNewV = false;
11346 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11347 if (AllWordsInNewV) {
11348 for (int i = 0; i != 8; ++i) {
11349 int idx = MaskVals[i];
11352 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11353 if ((idx != i) && idx < 4)
11355 if ((idx != i) && idx > 3)
11364 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11365 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11366 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11367 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11368 unsigned TargetMask = 0;
11369 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11370 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11371 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11372 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11373 getShufflePSHUFLWImmediate(SVOp);
11374 V1 = NewV.getOperand(0);
11375 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11379 // Promote splats to a larger type which usually leads to more efficient code.
11380 // FIXME: Is this true if pshufb is available?
11381 if (SVOp->isSplat())
11382 return PromoteSplat(SVOp, DAG);
11384 // If we have SSSE3, and all words of the result are from 1 input vector,
11385 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11386 // is present, fall back to case 4.
11387 if (Subtarget->hasSSSE3()) {
11388 SmallVector<SDValue,16> pshufbMask;
11390 // If we have elements from both input vectors, set the high bit of the
11391 // shuffle mask element to zero out elements that come from V2 in the V1
11392 // mask, and elements that come from V1 in the V2 mask, so that the two
11393 // results can be OR'd together.
11394 bool TwoInputs = V1Used && V2Used;
11395 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11397 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11399 // Calculate the shuffle mask for the second input, shuffle it, and
11400 // OR it with the first shuffled input.
11401 CommuteVectorShuffleMask(MaskVals, 8);
11402 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11403 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11404 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11407 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11408 // and update MaskVals with new element order.
11409 std::bitset<8> InOrder;
11410 if (BestLoQuad >= 0) {
11411 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11412 for (int i = 0; i != 4; ++i) {
11413 int idx = MaskVals[i];
11416 } else if ((idx / 4) == BestLoQuad) {
11417 MaskV[i] = idx & 3;
11421 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11424 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11426 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11427 NewV.getOperand(0),
11428 getShufflePSHUFLWImmediate(SVOp), DAG);
11432 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11433 // and update MaskVals with the new element order.
11434 if (BestHiQuad >= 0) {
11435 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11436 for (unsigned i = 4; i != 8; ++i) {
11437 int idx = MaskVals[i];
11440 } else if ((idx / 4) == BestHiQuad) {
11441 MaskV[i] = (idx & 3) + 4;
11445 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11448 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11449 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11450 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11451 NewV.getOperand(0),
11452 getShufflePSHUFHWImmediate(SVOp), DAG);
11456 // In case BestHi & BestLo were both -1, which means each quadword has a word
11457 // from each of the four input quadwords, calculate the InOrder bitvector now
11458 // before falling through to the insert/extract cleanup.
11459 if (BestLoQuad == -1 && BestHiQuad == -1) {
11461 for (int i = 0; i != 8; ++i)
11462 if (MaskVals[i] < 0 || MaskVals[i] == i)
11466 // The other elements are put in the right place using pextrw and pinsrw.
11467 for (unsigned i = 0; i != 8; ++i) {
11470 int EltIdx = MaskVals[i];
11473 SDValue ExtOp = (EltIdx < 8) ?
11474 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11475 DAG.getIntPtrConstant(EltIdx)) :
11476 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11477 DAG.getIntPtrConstant(EltIdx - 8));
11478 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11479 DAG.getIntPtrConstant(i));
11484 /// \brief v16i16 shuffles
11486 /// FIXME: We only support generation of a single pshufb currently. We can
11487 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11488 /// well (e.g 2 x pshufb + 1 x por).
11490 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11491 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11492 SDValue V1 = SVOp->getOperand(0);
11493 SDValue V2 = SVOp->getOperand(1);
11496 if (V2.getOpcode() != ISD::UNDEF)
11499 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11500 return getPSHUFB(MaskVals, V1, dl, DAG);
11503 // v16i8 shuffles - Prefer shuffles in the following order:
11504 // 1. [ssse3] 1 x pshufb
11505 // 2. [ssse3] 2 x pshufb + 1 x por
11506 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11507 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11508 const X86Subtarget* Subtarget,
11509 SelectionDAG &DAG) {
11510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11511 SDValue V1 = SVOp->getOperand(0);
11512 SDValue V2 = SVOp->getOperand(1);
11514 ArrayRef<int> MaskVals = SVOp->getMask();
11516 // Promote splats to a larger type which usually leads to more efficient code.
11517 // FIXME: Is this true if pshufb is available?
11518 if (SVOp->isSplat())
11519 return PromoteSplat(SVOp, DAG);
11521 // If we have SSSE3, case 1 is generated when all result bytes come from
11522 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11523 // present, fall back to case 3.
11525 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11526 if (Subtarget->hasSSSE3()) {
11527 SmallVector<SDValue,16> pshufbMask;
11529 // If all result elements are from one input vector, then only translate
11530 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11532 // Otherwise, we have elements from both input vectors, and must zero out
11533 // elements that come from V2 in the first mask, and V1 in the second mask
11534 // so that we can OR them together.
11535 for (unsigned i = 0; i != 16; ++i) {
11536 int EltIdx = MaskVals[i];
11537 if (EltIdx < 0 || EltIdx >= 16)
11539 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11541 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11542 DAG.getNode(ISD::BUILD_VECTOR, dl,
11543 MVT::v16i8, pshufbMask));
11545 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11546 // the 2nd operand if it's undefined or zero.
11547 if (V2.getOpcode() == ISD::UNDEF ||
11548 ISD::isBuildVectorAllZeros(V2.getNode()))
11551 // Calculate the shuffle mask for the second input, shuffle it, and
11552 // OR it with the first shuffled input.
11553 pshufbMask.clear();
11554 for (unsigned i = 0; i != 16; ++i) {
11555 int EltIdx = MaskVals[i];
11556 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11557 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11559 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11560 DAG.getNode(ISD::BUILD_VECTOR, dl,
11561 MVT::v16i8, pshufbMask));
11562 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11565 // No SSSE3 - Calculate in place words and then fix all out of place words
11566 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11567 // the 16 different words that comprise the two doublequadword input vectors.
11568 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11569 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11571 for (int i = 0; i != 8; ++i) {
11572 int Elt0 = MaskVals[i*2];
11573 int Elt1 = MaskVals[i*2+1];
11575 // This word of the result is all undef, skip it.
11576 if (Elt0 < 0 && Elt1 < 0)
11579 // This word of the result is already in the correct place, skip it.
11580 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11583 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11584 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11587 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11588 // using a single extract together, load it and store it.
11589 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11590 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11591 DAG.getIntPtrConstant(Elt1 / 2));
11592 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11593 DAG.getIntPtrConstant(i));
11597 // If Elt1 is defined, extract it from the appropriate source. If the
11598 // source byte is not also odd, shift the extracted word left 8 bits
11599 // otherwise clear the bottom 8 bits if we need to do an or.
11601 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11602 DAG.getIntPtrConstant(Elt1 / 2));
11603 if ((Elt1 & 1) == 0)
11604 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11606 TLI.getShiftAmountTy(InsElt.getValueType())));
11607 else if (Elt0 >= 0)
11608 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11609 DAG.getConstant(0xFF00, MVT::i16));
11611 // If Elt0 is defined, extract it from the appropriate source. If the
11612 // source byte is not also even, shift the extracted word right 8 bits. If
11613 // Elt1 was also defined, OR the extracted values together before
11614 // inserting them in the result.
11616 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11617 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11618 if ((Elt0 & 1) != 0)
11619 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11621 TLI.getShiftAmountTy(InsElt0.getValueType())));
11622 else if (Elt1 >= 0)
11623 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11624 DAG.getConstant(0x00FF, MVT::i16));
11625 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11628 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11629 DAG.getIntPtrConstant(i));
11631 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11634 // v32i8 shuffles - Translate to VPSHUFB if possible.
11636 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11637 const X86Subtarget *Subtarget,
11638 SelectionDAG &DAG) {
11639 MVT VT = SVOp->getSimpleValueType(0);
11640 SDValue V1 = SVOp->getOperand(0);
11641 SDValue V2 = SVOp->getOperand(1);
11643 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11645 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11646 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11647 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11649 // VPSHUFB may be generated if
11650 // (1) one of input vector is undefined or zeroinitializer.
11651 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11652 // And (2) the mask indexes don't cross the 128-bit lane.
11653 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11654 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11657 if (V1IsAllZero && !V2IsAllZero) {
11658 CommuteVectorShuffleMask(MaskVals, 32);
11661 return getPSHUFB(MaskVals, V1, dl, DAG);
11664 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11665 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11666 /// done when every pair / quad of shuffle mask elements point to elements in
11667 /// the right sequence. e.g.
11668 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11670 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11671 SelectionDAG &DAG) {
11672 MVT VT = SVOp->getSimpleValueType(0);
11674 unsigned NumElems = VT.getVectorNumElements();
11677 switch (VT.SimpleTy) {
11678 default: llvm_unreachable("Unexpected!");
11681 return SDValue(SVOp, 0);
11682 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11683 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11684 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11685 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11686 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11687 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11690 SmallVector<int, 8> MaskVec;
11691 for (unsigned i = 0; i != NumElems; i += Scale) {
11693 for (unsigned j = 0; j != Scale; ++j) {
11694 int EltIdx = SVOp->getMaskElt(i+j);
11698 StartIdx = (EltIdx / Scale);
11699 if (EltIdx != (int)(StartIdx*Scale + j))
11702 MaskVec.push_back(StartIdx);
11705 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11706 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11707 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11710 /// getVZextMovL - Return a zero-extending vector move low node.
11712 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11713 SDValue SrcOp, SelectionDAG &DAG,
11714 const X86Subtarget *Subtarget, SDLoc dl) {
11715 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11716 LoadSDNode *LD = nullptr;
11717 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11718 LD = dyn_cast<LoadSDNode>(SrcOp);
11720 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11722 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11723 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11724 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11725 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11726 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11728 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11729 return DAG.getNode(ISD::BITCAST, dl, VT,
11730 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11731 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11733 SrcOp.getOperand(0)
11739 return DAG.getNode(ISD::BITCAST, dl, VT,
11740 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11741 DAG.getNode(ISD::BITCAST, dl,
11745 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11746 /// which could not be matched by any known target speficic shuffle
11748 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11750 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11751 if (NewOp.getNode())
11754 MVT VT = SVOp->getSimpleValueType(0);
11756 unsigned NumElems = VT.getVectorNumElements();
11757 unsigned NumLaneElems = NumElems / 2;
11760 MVT EltVT = VT.getVectorElementType();
11761 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11764 SmallVector<int, 16> Mask;
11765 for (unsigned l = 0; l < 2; ++l) {
11766 // Build a shuffle mask for the output, discovering on the fly which
11767 // input vectors to use as shuffle operands (recorded in InputUsed).
11768 // If building a suitable shuffle vector proves too hard, then bail
11769 // out with UseBuildVector set.
11770 bool UseBuildVector = false;
11771 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11772 unsigned LaneStart = l * NumLaneElems;
11773 for (unsigned i = 0; i != NumLaneElems; ++i) {
11774 // The mask element. This indexes into the input.
11775 int Idx = SVOp->getMaskElt(i+LaneStart);
11777 // the mask element does not index into any input vector.
11778 Mask.push_back(-1);
11782 // The input vector this mask element indexes into.
11783 int Input = Idx / NumLaneElems;
11785 // Turn the index into an offset from the start of the input vector.
11786 Idx -= Input * NumLaneElems;
11788 // Find or create a shuffle vector operand to hold this input.
11790 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11791 if (InputUsed[OpNo] == Input)
11792 // This input vector is already an operand.
11794 if (InputUsed[OpNo] < 0) {
11795 // Create a new operand for this input vector.
11796 InputUsed[OpNo] = Input;
11801 if (OpNo >= array_lengthof(InputUsed)) {
11802 // More than two input vectors used! Give up on trying to create a
11803 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11804 UseBuildVector = true;
11808 // Add the mask index for the new shuffle vector.
11809 Mask.push_back(Idx + OpNo * NumLaneElems);
11812 if (UseBuildVector) {
11813 SmallVector<SDValue, 16> SVOps;
11814 for (unsigned i = 0; i != NumLaneElems; ++i) {
11815 // The mask element. This indexes into the input.
11816 int Idx = SVOp->getMaskElt(i+LaneStart);
11818 SVOps.push_back(DAG.getUNDEF(EltVT));
11822 // The input vector this mask element indexes into.
11823 int Input = Idx / NumElems;
11825 // Turn the index into an offset from the start of the input vector.
11826 Idx -= Input * NumElems;
11828 // Extract the vector element by hand.
11829 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11830 SVOp->getOperand(Input),
11831 DAG.getIntPtrConstant(Idx)));
11834 // Construct the output using a BUILD_VECTOR.
11835 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11836 } else if (InputUsed[0] < 0) {
11837 // No input vectors were used! The result is undefined.
11838 Output[l] = DAG.getUNDEF(NVT);
11840 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11841 (InputUsed[0] % 2) * NumLaneElems,
11843 // If only one input was used, use an undefined vector for the other.
11844 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11845 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11846 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11847 // At least one input vector was used. Create a new shuffle vector.
11848 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11854 // Concatenate the result back
11855 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11858 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11859 /// 4 elements, and match them with several different shuffle types.
11861 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11862 SDValue V1 = SVOp->getOperand(0);
11863 SDValue V2 = SVOp->getOperand(1);
11865 MVT VT = SVOp->getSimpleValueType(0);
11867 assert(VT.is128BitVector() && "Unsupported vector size");
11869 std::pair<int, int> Locs[4];
11870 int Mask1[] = { -1, -1, -1, -1 };
11871 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11873 unsigned NumHi = 0;
11874 unsigned NumLo = 0;
11875 for (unsigned i = 0; i != 4; ++i) {
11876 int Idx = PermMask[i];
11878 Locs[i] = std::make_pair(-1, -1);
11880 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11882 Locs[i] = std::make_pair(0, NumLo);
11883 Mask1[NumLo] = Idx;
11886 Locs[i] = std::make_pair(1, NumHi);
11888 Mask1[2+NumHi] = Idx;
11894 if (NumLo <= 2 && NumHi <= 2) {
11895 // If no more than two elements come from either vector. This can be
11896 // implemented with two shuffles. First shuffle gather the elements.
11897 // The second shuffle, which takes the first shuffle as both of its
11898 // vector operands, put the elements into the right order.
11899 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11901 int Mask2[] = { -1, -1, -1, -1 };
11903 for (unsigned i = 0; i != 4; ++i)
11904 if (Locs[i].first != -1) {
11905 unsigned Idx = (i < 2) ? 0 : 4;
11906 Idx += Locs[i].first * 2 + Locs[i].second;
11910 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11913 if (NumLo == 3 || NumHi == 3) {
11914 // Otherwise, we must have three elements from one vector, call it X, and
11915 // one element from the other, call it Y. First, use a shufps to build an
11916 // intermediate vector with the one element from Y and the element from X
11917 // that will be in the same half in the final destination (the indexes don't
11918 // matter). Then, use a shufps to build the final vector, taking the half
11919 // containing the element from Y from the intermediate, and the other half
11922 // Normalize it so the 3 elements come from V1.
11923 CommuteVectorShuffleMask(PermMask, 4);
11927 // Find the element from V2.
11929 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11930 int Val = PermMask[HiIndex];
11937 Mask1[0] = PermMask[HiIndex];
11939 Mask1[2] = PermMask[HiIndex^1];
11941 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11943 if (HiIndex >= 2) {
11944 Mask1[0] = PermMask[0];
11945 Mask1[1] = PermMask[1];
11946 Mask1[2] = HiIndex & 1 ? 6 : 4;
11947 Mask1[3] = HiIndex & 1 ? 4 : 6;
11948 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11951 Mask1[0] = HiIndex & 1 ? 2 : 0;
11952 Mask1[1] = HiIndex & 1 ? 0 : 2;
11953 Mask1[2] = PermMask[2];
11954 Mask1[3] = PermMask[3];
11959 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11962 // Break it into (shuffle shuffle_hi, shuffle_lo).
11963 int LoMask[] = { -1, -1, -1, -1 };
11964 int HiMask[] = { -1, -1, -1, -1 };
11966 int *MaskPtr = LoMask;
11967 unsigned MaskIdx = 0;
11968 unsigned LoIdx = 0;
11969 unsigned HiIdx = 2;
11970 for (unsigned i = 0; i != 4; ++i) {
11977 int Idx = PermMask[i];
11979 Locs[i] = std::make_pair(-1, -1);
11980 } else if (Idx < 4) {
11981 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11982 MaskPtr[LoIdx] = Idx;
11985 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11986 MaskPtr[HiIdx] = Idx;
11991 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11992 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11993 int MaskOps[] = { -1, -1, -1, -1 };
11994 for (unsigned i = 0; i != 4; ++i)
11995 if (Locs[i].first != -1)
11996 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11997 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
12000 static bool MayFoldVectorLoad(SDValue V) {
12001 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
12002 V = V.getOperand(0);
12004 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
12005 V = V.getOperand(0);
12006 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
12007 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
12008 // BUILD_VECTOR (load), undef
12009 V = V.getOperand(0);
12011 return MayFoldLoad(V);
12015 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
12016 MVT VT = Op.getSimpleValueType();
12018 // Canonizalize to v2f64.
12019 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
12020 return DAG.getNode(ISD::BITCAST, dl, VT,
12021 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
12026 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
12028 SDValue V1 = Op.getOperand(0);
12029 SDValue V2 = Op.getOperand(1);
12030 MVT VT = Op.getSimpleValueType();
12032 assert(VT != MVT::v2i64 && "unsupported shuffle type");
12034 if (HasSSE2 && VT == MVT::v2f64)
12035 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
12037 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
12038 return DAG.getNode(ISD::BITCAST, dl, VT,
12039 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
12040 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
12041 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
12045 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
12046 SDValue V1 = Op.getOperand(0);
12047 SDValue V2 = Op.getOperand(1);
12048 MVT VT = Op.getSimpleValueType();
12050 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
12051 "unsupported shuffle type");
12053 if (V2.getOpcode() == ISD::UNDEF)
12057 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
12061 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
12062 SDValue V1 = Op.getOperand(0);
12063 SDValue V2 = Op.getOperand(1);
12064 MVT VT = Op.getSimpleValueType();
12065 unsigned NumElems = VT.getVectorNumElements();
12067 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
12068 // operand of these instructions is only memory, so check if there's a
12069 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
12071 bool CanFoldLoad = false;
12073 // Trivial case, when V2 comes from a load.
12074 if (MayFoldVectorLoad(V2))
12075 CanFoldLoad = true;
12077 // When V1 is a load, it can be folded later into a store in isel, example:
12078 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
12080 // (MOVLPSmr addr:$src1, VR128:$src2)
12081 // So, recognize this potential and also use MOVLPS or MOVLPD
12082 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
12083 CanFoldLoad = true;
12085 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12087 if (HasSSE2 && NumElems == 2)
12088 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
12091 // If we don't care about the second element, proceed to use movss.
12092 if (SVOp->getMaskElt(1) != -1)
12093 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
12096 // movl and movlp will both match v2i64, but v2i64 is never matched by
12097 // movl earlier because we make it strict to avoid messing with the movlp load
12098 // folding logic (see the code above getMOVLP call). Match it here then,
12099 // this is horrible, but will stay like this until we move all shuffle
12100 // matching to x86 specific nodes. Note that for the 1st condition all
12101 // types are matched with movsd.
12103 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
12104 // as to remove this logic from here, as much as possible
12105 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
12106 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12107 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12110 assert(VT != MVT::v4i32 && "unsupported shuffle type");
12112 // Invert the operand order and use SHUFPS to match it.
12113 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
12114 getShuffleSHUFImmediate(SVOp), DAG);
12117 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
12118 SelectionDAG &DAG) {
12120 MVT VT = Load->getSimpleValueType(0);
12121 MVT EVT = VT.getVectorElementType();
12122 SDValue Addr = Load->getOperand(1);
12123 SDValue NewAddr = DAG.getNode(
12124 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
12125 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
12128 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
12129 DAG.getMachineFunction().getMachineMemOperand(
12130 Load->getMemOperand(), 0, EVT.getStoreSize()));
12134 // It is only safe to call this function if isINSERTPSMask is true for
12135 // this shufflevector mask.
12136 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
12137 SelectionDAG &DAG) {
12138 // Generate an insertps instruction when inserting an f32 from memory onto a
12139 // v4f32 or when copying a member from one v4f32 to another.
12140 // We also use it for transferring i32 from one register to another,
12141 // since it simply copies the same bits.
12142 // If we're transferring an i32 from memory to a specific element in a
12143 // register, we output a generic DAG that will match the PINSRD
12145 MVT VT = SVOp->getSimpleValueType(0);
12146 MVT EVT = VT.getVectorElementType();
12147 SDValue V1 = SVOp->getOperand(0);
12148 SDValue V2 = SVOp->getOperand(1);
12149 auto Mask = SVOp->getMask();
12150 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
12151 "unsupported vector type for insertps/pinsrd");
12153 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
12154 auto FromV2Predicate = [](const int &i) { return i >= 4; };
12155 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
12159 unsigned DestIndex;
12163 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12166 // If we have 1 element from each vector, we have to check if we're
12167 // changing V1's element's place. If so, we're done. Otherwise, we
12168 // should assume we're changing V2's element's place and behave
12170 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12171 assert(DestIndex <= INT32_MAX && "truncated destination index");
12172 if (FromV1 == FromV2 &&
12173 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12177 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12180 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12181 "More than one element from V1 and from V2, or no elements from one "
12182 "of the vectors. This case should not have returned true from "
12187 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12190 // Get an index into the source vector in the range [0,4) (the mask is
12191 // in the range [0,8) because it can address V1 and V2)
12192 unsigned SrcIndex = Mask[DestIndex] % 4;
12193 if (MayFoldLoad(From)) {
12194 // Trivial case, when From comes from a load and is only used by the
12195 // shuffle. Make it use insertps from the vector that we need from that
12198 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12199 if (!NewLoad.getNode())
12202 if (EVT == MVT::f32) {
12203 // Create this as a scalar to vector to match the instruction pattern.
12204 SDValue LoadScalarToVector =
12205 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12206 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12207 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12209 } else { // EVT == MVT::i32
12210 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12211 // instruction, to match the PINSRD instruction, which loads an i32 to a
12212 // certain vector element.
12213 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12214 DAG.getConstant(DestIndex, MVT::i32));
12218 // Vector-element-to-vector
12219 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12220 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12223 // Reduce a vector shuffle to zext.
12224 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12225 SelectionDAG &DAG) {
12226 // PMOVZX is only available from SSE41.
12227 if (!Subtarget->hasSSE41())
12230 MVT VT = Op.getSimpleValueType();
12232 // Only AVX2 support 256-bit vector integer extending.
12233 if (!Subtarget->hasInt256() && VT.is256BitVector())
12236 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12238 SDValue V1 = Op.getOperand(0);
12239 SDValue V2 = Op.getOperand(1);
12240 unsigned NumElems = VT.getVectorNumElements();
12242 // Extending is an unary operation and the element type of the source vector
12243 // won't be equal to or larger than i64.
12244 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12245 VT.getVectorElementType() == MVT::i64)
12248 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12249 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12250 while ((1U << Shift) < NumElems) {
12251 if (SVOp->getMaskElt(1U << Shift) == 1)
12254 // The maximal ratio is 8, i.e. from i8 to i64.
12259 // Check the shuffle mask.
12260 unsigned Mask = (1U << Shift) - 1;
12261 for (unsigned i = 0; i != NumElems; ++i) {
12262 int EltIdx = SVOp->getMaskElt(i);
12263 if ((i & Mask) != 0 && EltIdx != -1)
12265 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12269 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12270 MVT NeVT = MVT::getIntegerVT(NBits);
12271 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12273 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12276 return DAG.getNode(ISD::BITCAST, DL, VT,
12277 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12280 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12281 SelectionDAG &DAG) {
12282 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12283 MVT VT = Op.getSimpleValueType();
12285 SDValue V1 = Op.getOperand(0);
12286 SDValue V2 = Op.getOperand(1);
12288 if (isZeroShuffle(SVOp))
12289 return getZeroVector(VT, Subtarget, DAG, dl);
12291 // Handle splat operations
12292 if (SVOp->isSplat()) {
12293 // Use vbroadcast whenever the splat comes from a foldable load
12294 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12295 if (Broadcast.getNode())
12299 // Check integer expanding shuffles.
12300 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12301 if (NewOp.getNode())
12304 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12306 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12307 VT == MVT::v32i8) {
12308 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12309 if (NewOp.getNode())
12310 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12311 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12312 // FIXME: Figure out a cleaner way to do this.
12313 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12314 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12315 if (NewOp.getNode()) {
12316 MVT NewVT = NewOp.getSimpleValueType();
12317 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12318 NewVT, true, false))
12319 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12322 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12323 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12324 if (NewOp.getNode()) {
12325 MVT NewVT = NewOp.getSimpleValueType();
12326 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12327 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12336 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12337 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12338 SDValue V1 = Op.getOperand(0);
12339 SDValue V2 = Op.getOperand(1);
12340 MVT VT = Op.getSimpleValueType();
12342 unsigned NumElems = VT.getVectorNumElements();
12343 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12344 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12345 bool V1IsSplat = false;
12346 bool V2IsSplat = false;
12347 bool HasSSE2 = Subtarget->hasSSE2();
12348 bool HasFp256 = Subtarget->hasFp256();
12349 bool HasInt256 = Subtarget->hasInt256();
12350 MachineFunction &MF = DAG.getMachineFunction();
12351 bool OptForSize = MF.getFunction()->getAttributes().
12352 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12354 // Check if we should use the experimental vector shuffle lowering. If so,
12355 // delegate completely to that code path.
12356 if (ExperimentalVectorShuffleLowering)
12357 return lowerVectorShuffle(Op, Subtarget, DAG);
12359 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12361 if (V1IsUndef && V2IsUndef)
12362 return DAG.getUNDEF(VT);
12364 // When we create a shuffle node we put the UNDEF node to second operand,
12365 // but in some cases the first operand may be transformed to UNDEF.
12366 // In this case we should just commute the node.
12368 return DAG.getCommutedVectorShuffle(*SVOp);
12370 // Vector shuffle lowering takes 3 steps:
12372 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12373 // narrowing and commutation of operands should be handled.
12374 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12376 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12377 // so the shuffle can be broken into other shuffles and the legalizer can
12378 // try the lowering again.
12380 // The general idea is that no vector_shuffle operation should be left to
12381 // be matched during isel, all of them must be converted to a target specific
12384 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12385 // narrowing and commutation of operands should be handled. The actual code
12386 // doesn't include all of those, work in progress...
12387 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12388 if (NewOp.getNode())
12391 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12393 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12394 // unpckh_undef). Only use pshufd if speed is more important than size.
12395 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12396 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12397 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12398 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12400 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12401 V2IsUndef && MayFoldVectorLoad(V1))
12402 return getMOVDDup(Op, dl, V1, DAG);
12404 if (isMOVHLPS_v_undef_Mask(M, VT))
12405 return getMOVHighToLow(Op, dl, DAG);
12407 // Use to match splats
12408 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12409 (VT == MVT::v2f64 || VT == MVT::v2i64))
12410 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12412 if (isPSHUFDMask(M, VT)) {
12413 // The actual implementation will match the mask in the if above and then
12414 // during isel it can match several different instructions, not only pshufd
12415 // as its name says, sad but true, emulate the behavior for now...
12416 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12417 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12419 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12421 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12422 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12424 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12425 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12428 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12432 if (isPALIGNRMask(M, VT, Subtarget))
12433 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12434 getShufflePALIGNRImmediate(SVOp),
12437 if (isVALIGNMask(M, VT, Subtarget))
12438 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12439 getShuffleVALIGNImmediate(SVOp),
12442 // Check if this can be converted into a logical shift.
12443 bool isLeft = false;
12444 unsigned ShAmt = 0;
12446 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12447 if (isShift && ShVal.hasOneUse()) {
12448 // If the shifted value has multiple uses, it may be cheaper to use
12449 // v_set0 + movlhps or movhlps, etc.
12450 MVT EltVT = VT.getVectorElementType();
12451 ShAmt *= EltVT.getSizeInBits();
12452 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12455 if (isMOVLMask(M, VT)) {
12456 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12457 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12458 if (!isMOVLPMask(M, VT)) {
12459 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12460 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12462 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12463 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12467 // FIXME: fold these into legal mask.
12468 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12469 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12471 if (isMOVHLPSMask(M, VT))
12472 return getMOVHighToLow(Op, dl, DAG);
12474 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12475 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12477 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12478 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12480 if (isMOVLPMask(M, VT))
12481 return getMOVLP(Op, dl, DAG, HasSSE2);
12483 if (ShouldXformToMOVHLPS(M, VT) ||
12484 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12485 return DAG.getCommutedVectorShuffle(*SVOp);
12488 // No better options. Use a vshldq / vsrldq.
12489 MVT EltVT = VT.getVectorElementType();
12490 ShAmt *= EltVT.getSizeInBits();
12491 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12494 bool Commuted = false;
12495 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12496 // 1,1,1,1 -> v8i16 though.
12497 BitVector UndefElements;
12498 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12499 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12501 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12502 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12505 // Canonicalize the splat or undef, if present, to be on the RHS.
12506 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12507 CommuteVectorShuffleMask(M, NumElems);
12509 std::swap(V1IsSplat, V2IsSplat);
12513 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12514 // Shuffling low element of v1 into undef, just return v1.
12517 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12518 // the instruction selector will not match, so get a canonical MOVL with
12519 // swapped operands to undo the commute.
12520 return getMOVL(DAG, dl, VT, V2, V1);
12523 if (isUNPCKLMask(M, VT, HasInt256))
12524 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12526 if (isUNPCKHMask(M, VT, HasInt256))
12527 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12530 // Normalize mask so all entries that point to V2 points to its first
12531 // element then try to match unpck{h|l} again. If match, return a
12532 // new vector_shuffle with the corrected mask.p
12533 SmallVector<int, 8> NewMask(M.begin(), M.end());
12534 NormalizeMask(NewMask, NumElems);
12535 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12536 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12537 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12538 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12542 // Commute is back and try unpck* again.
12543 // FIXME: this seems wrong.
12544 CommuteVectorShuffleMask(M, NumElems);
12546 std::swap(V1IsSplat, V2IsSplat);
12548 if (isUNPCKLMask(M, VT, HasInt256))
12549 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12551 if (isUNPCKHMask(M, VT, HasInt256))
12552 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12555 // Normalize the node to match x86 shuffle ops if needed
12556 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12557 return DAG.getCommutedVectorShuffle(*SVOp);
12559 // The checks below are all present in isShuffleMaskLegal, but they are
12560 // inlined here right now to enable us to directly emit target specific
12561 // nodes, and remove one by one until they don't return Op anymore.
12563 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12564 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12565 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12566 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12569 if (isPSHUFHWMask(M, VT, HasInt256))
12570 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12571 getShufflePSHUFHWImmediate(SVOp),
12574 if (isPSHUFLWMask(M, VT, HasInt256))
12575 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12576 getShufflePSHUFLWImmediate(SVOp),
12579 unsigned MaskValue;
12580 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12582 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12584 if (isSHUFPMask(M, VT))
12585 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12586 getShuffleSHUFImmediate(SVOp), DAG);
12588 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12589 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12590 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12591 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12593 //===--------------------------------------------------------------------===//
12594 // Generate target specific nodes for 128 or 256-bit shuffles only
12595 // supported in the AVX instruction set.
12598 // Handle VMOVDDUPY permutations
12599 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12600 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12602 // Handle VPERMILPS/D* permutations
12603 if (isVPERMILPMask(M, VT)) {
12604 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12605 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12606 getShuffleSHUFImmediate(SVOp), DAG);
12607 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12608 getShuffleSHUFImmediate(SVOp), DAG);
12612 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12613 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12614 Idx*(NumElems/2), DAG, dl);
12616 // Handle VPERM2F128/VPERM2I128 permutations
12617 if (isVPERM2X128Mask(M, VT, HasFp256))
12618 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12619 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12621 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12622 return getINSERTPS(SVOp, dl, DAG);
12625 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12626 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12628 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12629 VT.is512BitVector()) {
12630 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12631 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12632 SmallVector<SDValue, 16> permclMask;
12633 for (unsigned i = 0; i != NumElems; ++i) {
12634 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12637 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12639 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12640 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12641 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12642 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12643 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12646 //===--------------------------------------------------------------------===//
12647 // Since no target specific shuffle was selected for this generic one,
12648 // lower it into other known shuffles. FIXME: this isn't true yet, but
12649 // this is the plan.
12652 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12653 if (VT == MVT::v8i16) {
12654 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12655 if (NewOp.getNode())
12659 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12660 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12661 if (NewOp.getNode())
12665 if (VT == MVT::v16i8) {
12666 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12667 if (NewOp.getNode())
12671 if (VT == MVT::v32i8) {
12672 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12673 if (NewOp.getNode())
12677 // Handle all 128-bit wide vectors with 4 elements, and match them with
12678 // several different shuffle types.
12679 if (NumElems == 4 && VT.is128BitVector())
12680 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12682 // Handle general 256-bit shuffles
12683 if (VT.is256BitVector())
12684 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12689 // This function assumes its argument is a BUILD_VECTOR of constants or
12690 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12692 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12693 unsigned &MaskValue) {
12695 unsigned NumElems = BuildVector->getNumOperands();
12696 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12697 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12698 unsigned NumElemsInLane = NumElems / NumLanes;
12700 // Blend for v16i16 should be symetric for the both lanes.
12701 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12702 SDValue EltCond = BuildVector->getOperand(i);
12703 SDValue SndLaneEltCond =
12704 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12706 int Lane1Cond = -1, Lane2Cond = -1;
12707 if (isa<ConstantSDNode>(EltCond))
12708 Lane1Cond = !isZero(EltCond);
12709 if (isa<ConstantSDNode>(SndLaneEltCond))
12710 Lane2Cond = !isZero(SndLaneEltCond);
12712 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12713 // Lane1Cond != 0, means we want the first argument.
12714 // Lane1Cond == 0, means we want the second argument.
12715 // The encoding of this argument is 0 for the first argument, 1
12716 // for the second. Therefore, invert the condition.
12717 MaskValue |= !Lane1Cond << i;
12718 else if (Lane1Cond < 0)
12719 MaskValue |= !Lane2Cond << i;
12726 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12728 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12729 SelectionDAG &DAG) {
12730 SDValue Cond = Op.getOperand(0);
12731 SDValue LHS = Op.getOperand(1);
12732 SDValue RHS = Op.getOperand(2);
12734 MVT VT = Op.getSimpleValueType();
12735 MVT EltVT = VT.getVectorElementType();
12736 unsigned NumElems = VT.getVectorNumElements();
12738 // There is no blend with immediate in AVX-512.
12739 if (VT.is512BitVector())
12742 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12744 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12747 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12750 // Check the mask for BLEND and build the value.
12751 unsigned MaskValue = 0;
12752 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12755 // Convert i32 vectors to floating point if it is not AVX2.
12756 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12758 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12759 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12761 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12762 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12765 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12766 DAG.getConstant(MaskValue, MVT::i32));
12767 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12770 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12771 // A vselect where all conditions and data are constants can be optimized into
12772 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12773 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12774 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12775 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12778 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12779 if (BlendOp.getNode())
12782 // Some types for vselect were previously set to Expand, not Legal or
12783 // Custom. Return an empty SDValue so we fall-through to Expand, after
12784 // the Custom lowering phase.
12785 MVT VT = Op.getSimpleValueType();
12786 switch (VT.SimpleTy) {
12791 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12796 // We couldn't create a "Blend with immediate" node.
12797 // This node should still be legal, but we'll have to emit a blendv*
12802 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12803 MVT VT = Op.getSimpleValueType();
12806 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12809 if (VT.getSizeInBits() == 8) {
12810 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12811 Op.getOperand(0), Op.getOperand(1));
12812 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12813 DAG.getValueType(VT));
12814 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12817 if (VT.getSizeInBits() == 16) {
12818 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12819 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12821 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12822 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12823 DAG.getNode(ISD::BITCAST, dl,
12826 Op.getOperand(1)));
12827 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12828 Op.getOperand(0), Op.getOperand(1));
12829 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12830 DAG.getValueType(VT));
12831 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12834 if (VT == MVT::f32) {
12835 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12836 // the result back to FR32 register. It's only worth matching if the
12837 // result has a single use which is a store or a bitcast to i32. And in
12838 // the case of a store, it's not worth it if the index is a constant 0,
12839 // because a MOVSSmr can be used instead, which is smaller and faster.
12840 if (!Op.hasOneUse())
12842 SDNode *User = *Op.getNode()->use_begin();
12843 if ((User->getOpcode() != ISD::STORE ||
12844 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12845 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12846 (User->getOpcode() != ISD::BITCAST ||
12847 User->getValueType(0) != MVT::i32))
12849 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12850 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12853 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12856 if (VT == MVT::i32 || VT == MVT::i64) {
12857 // ExtractPS/pextrq works with constant index.
12858 if (isa<ConstantSDNode>(Op.getOperand(1)))
12864 /// Extract one bit from mask vector, like v16i1 or v8i1.
12865 /// AVX-512 feature.
12867 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12868 SDValue Vec = Op.getOperand(0);
12870 MVT VecVT = Vec.getSimpleValueType();
12871 SDValue Idx = Op.getOperand(1);
12872 MVT EltVT = Op.getSimpleValueType();
12874 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12875 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
12876 "Unexpected vector type in ExtractBitFromMaskVector");
12878 // variable index can't be handled in mask registers,
12879 // extend vector to VR512
12880 if (!isa<ConstantSDNode>(Idx)) {
12881 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12882 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12883 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12884 ExtVT.getVectorElementType(), Ext, Idx);
12885 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12888 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12889 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12890 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
12891 rc = getRegClassFor(MVT::v16i1);
12892 unsigned MaxSift = rc->getSize()*8 - 1;
12893 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12894 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12895 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12896 DAG.getConstant(MaxSift, MVT::i8));
12897 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12898 DAG.getIntPtrConstant(0));
12902 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12903 SelectionDAG &DAG) const {
12905 SDValue Vec = Op.getOperand(0);
12906 MVT VecVT = Vec.getSimpleValueType();
12907 SDValue Idx = Op.getOperand(1);
12909 if (Op.getSimpleValueType() == MVT::i1)
12910 return ExtractBitFromMaskVector(Op, DAG);
12912 if (!isa<ConstantSDNode>(Idx)) {
12913 if (VecVT.is512BitVector() ||
12914 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12915 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12918 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12919 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12920 MaskEltVT.getSizeInBits());
12922 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12923 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12924 getZeroVector(MaskVT, Subtarget, DAG, dl),
12925 Idx, DAG.getConstant(0, getPointerTy()));
12926 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12927 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12928 Perm, DAG.getConstant(0, getPointerTy()));
12933 // If this is a 256-bit vector result, first extract the 128-bit vector and
12934 // then extract the element from the 128-bit vector.
12935 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12937 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12938 // Get the 128-bit vector.
12939 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12940 MVT EltVT = VecVT.getVectorElementType();
12942 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12944 //if (IdxVal >= NumElems/2)
12945 // IdxVal -= NumElems/2;
12946 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12947 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12948 DAG.getConstant(IdxVal, MVT::i32));
12951 assert(VecVT.is128BitVector() && "Unexpected vector length");
12953 if (Subtarget->hasSSE41()) {
12954 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12959 MVT VT = Op.getSimpleValueType();
12960 // TODO: handle v16i8.
12961 if (VT.getSizeInBits() == 16) {
12962 SDValue Vec = Op.getOperand(0);
12963 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12965 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12966 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12967 DAG.getNode(ISD::BITCAST, dl,
12969 Op.getOperand(1)));
12970 // Transform it so it match pextrw which produces a 32-bit result.
12971 MVT EltVT = MVT::i32;
12972 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12973 Op.getOperand(0), Op.getOperand(1));
12974 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12975 DAG.getValueType(VT));
12976 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12979 if (VT.getSizeInBits() == 32) {
12980 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12984 // SHUFPS the element to the lowest double word, then movss.
12985 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12986 MVT VVT = Op.getOperand(0).getSimpleValueType();
12987 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12988 DAG.getUNDEF(VVT), Mask);
12989 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12990 DAG.getIntPtrConstant(0));
12993 if (VT.getSizeInBits() == 64) {
12994 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12995 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12996 // to match extract_elt for f64.
12997 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
13001 // UNPCKHPD the element to the lowest double word, then movsd.
13002 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
13003 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
13004 int Mask[2] = { 1, -1 };
13005 MVT VVT = Op.getOperand(0).getSimpleValueType();
13006 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
13007 DAG.getUNDEF(VVT), Mask);
13008 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
13009 DAG.getIntPtrConstant(0));
13015 /// Insert one bit to mask vector, like v16i1 or v8i1.
13016 /// AVX-512 feature.
13018 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
13020 SDValue Vec = Op.getOperand(0);
13021 SDValue Elt = Op.getOperand(1);
13022 SDValue Idx = Op.getOperand(2);
13023 MVT VecVT = Vec.getSimpleValueType();
13025 if (!isa<ConstantSDNode>(Idx)) {
13026 // Non constant index. Extend source and destination,
13027 // insert element and then truncate the result.
13028 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
13029 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
13030 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
13031 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
13032 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
13033 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
13036 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13037 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
13038 if (Vec.getOpcode() == ISD::UNDEF)
13039 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
13040 DAG.getConstant(IdxVal, MVT::i8));
13041 const TargetRegisterClass* rc = getRegClassFor(VecVT);
13042 unsigned MaxSift = rc->getSize()*8 - 1;
13043 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
13044 DAG.getConstant(MaxSift, MVT::i8));
13045 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
13046 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
13047 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
13050 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
13051 SelectionDAG &DAG) const {
13052 MVT VT = Op.getSimpleValueType();
13053 MVT EltVT = VT.getVectorElementType();
13055 if (EltVT == MVT::i1)
13056 return InsertBitToMaskVector(Op, DAG);
13059 SDValue N0 = Op.getOperand(0);
13060 SDValue N1 = Op.getOperand(1);
13061 SDValue N2 = Op.getOperand(2);
13062 if (!isa<ConstantSDNode>(N2))
13064 auto *N2C = cast<ConstantSDNode>(N2);
13065 unsigned IdxVal = N2C->getZExtValue();
13067 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
13068 // into that, and then insert the subvector back into the result.
13069 if (VT.is256BitVector() || VT.is512BitVector()) {
13070 // Get the desired 128-bit vector half.
13071 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
13073 // Insert the element into the desired half.
13074 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
13075 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
13077 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
13078 DAG.getConstant(IdxIn128, MVT::i32));
13080 // Insert the changed part back to the 256-bit vector
13081 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
13083 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
13085 if (Subtarget->hasSSE41()) {
13086 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
13088 if (VT == MVT::v8i16) {
13089 Opc = X86ISD::PINSRW;
13091 assert(VT == MVT::v16i8);
13092 Opc = X86ISD::PINSRB;
13095 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
13097 if (N1.getValueType() != MVT::i32)
13098 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
13099 if (N2.getValueType() != MVT::i32)
13100 N2 = DAG.getIntPtrConstant(IdxVal);
13101 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
13104 if (EltVT == MVT::f32) {
13105 // Bits [7:6] of the constant are the source select. This will always be
13106 // zero here. The DAG Combiner may combine an extract_elt index into
13108 // bits. For example (insert (extract, 3), 2) could be matched by
13110 // the '3' into bits [7:6] of X86ISD::INSERTPS.
13111 // Bits [5:4] of the constant are the destination select. This is the
13112 // value of the incoming immediate.
13113 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
13114 // combine either bitwise AND or insert of float 0.0 to set these bits.
13115 N2 = DAG.getIntPtrConstant(IdxVal << 4);
13116 // Create this as a scalar to vector..
13117 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
13118 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
13121 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
13122 // PINSR* works with constant index.
13127 if (EltVT == MVT::i8)
13130 if (EltVT.getSizeInBits() == 16) {
13131 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
13132 // as its second argument.
13133 if (N1.getValueType() != MVT::i32)
13134 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
13135 if (N2.getValueType() != MVT::i32)
13136 N2 = DAG.getIntPtrConstant(IdxVal);
13137 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
13142 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
13144 MVT OpVT = Op.getSimpleValueType();
13146 // If this is a 256-bit vector result, first insert into a 128-bit
13147 // vector and then insert into the 256-bit vector.
13148 if (!OpVT.is128BitVector()) {
13149 // Insert into a 128-bit vector.
13150 unsigned SizeFactor = OpVT.getSizeInBits()/128;
13151 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
13152 OpVT.getVectorNumElements() / SizeFactor);
13154 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
13156 // Insert the 128-bit vector.
13157 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
13160 if (OpVT == MVT::v1i64 &&
13161 Op.getOperand(0).getValueType() == MVT::i64)
13162 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
13164 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
13165 assert(OpVT.is128BitVector() && "Expected an SSE type!");
13166 return DAG.getNode(ISD::BITCAST, dl, OpVT,
13167 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13170 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13171 // a simple subregister reference or explicit instructions to grab
13172 // upper bits of a vector.
13173 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13174 SelectionDAG &DAG) {
13176 SDValue In = Op.getOperand(0);
13177 SDValue Idx = Op.getOperand(1);
13178 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13179 MVT ResVT = Op.getSimpleValueType();
13180 MVT InVT = In.getSimpleValueType();
13182 if (Subtarget->hasFp256()) {
13183 if (ResVT.is128BitVector() &&
13184 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13185 isa<ConstantSDNode>(Idx)) {
13186 return Extract128BitVector(In, IdxVal, DAG, dl);
13188 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13189 isa<ConstantSDNode>(Idx)) {
13190 return Extract256BitVector(In, IdxVal, DAG, dl);
13196 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13197 // simple superregister reference or explicit instructions to insert
13198 // the upper bits of a vector.
13199 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13200 SelectionDAG &DAG) {
13201 if (Subtarget->hasFp256()) {
13202 SDLoc dl(Op.getNode());
13203 SDValue Vec = Op.getNode()->getOperand(0);
13204 SDValue SubVec = Op.getNode()->getOperand(1);
13205 SDValue Idx = Op.getNode()->getOperand(2);
13207 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13208 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13209 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13210 isa<ConstantSDNode>(Idx)) {
13211 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13212 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13215 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13216 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13217 isa<ConstantSDNode>(Idx)) {
13218 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13219 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13225 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13226 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13227 // one of the above mentioned nodes. It has to be wrapped because otherwise
13228 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13229 // be used to form addressing mode. These wrapped nodes will be selected
13232 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13233 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13235 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13236 // global base reg.
13237 unsigned char OpFlag = 0;
13238 unsigned WrapperKind = X86ISD::Wrapper;
13239 CodeModel::Model M = DAG.getTarget().getCodeModel();
13241 if (Subtarget->isPICStyleRIPRel() &&
13242 (M == CodeModel::Small || M == CodeModel::Kernel))
13243 WrapperKind = X86ISD::WrapperRIP;
13244 else if (Subtarget->isPICStyleGOT())
13245 OpFlag = X86II::MO_GOTOFF;
13246 else if (Subtarget->isPICStyleStubPIC())
13247 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13249 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13250 CP->getAlignment(),
13251 CP->getOffset(), OpFlag);
13253 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13254 // With PIC, the address is actually $g + Offset.
13256 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13257 DAG.getNode(X86ISD::GlobalBaseReg,
13258 SDLoc(), getPointerTy()),
13265 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13266 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13268 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13269 // global base reg.
13270 unsigned char OpFlag = 0;
13271 unsigned WrapperKind = X86ISD::Wrapper;
13272 CodeModel::Model M = DAG.getTarget().getCodeModel();
13274 if (Subtarget->isPICStyleRIPRel() &&
13275 (M == CodeModel::Small || M == CodeModel::Kernel))
13276 WrapperKind = X86ISD::WrapperRIP;
13277 else if (Subtarget->isPICStyleGOT())
13278 OpFlag = X86II::MO_GOTOFF;
13279 else if (Subtarget->isPICStyleStubPIC())
13280 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13282 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13285 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13287 // With PIC, the address is actually $g + Offset.
13289 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13290 DAG.getNode(X86ISD::GlobalBaseReg,
13291 SDLoc(), getPointerTy()),
13298 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13299 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13301 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13302 // global base reg.
13303 unsigned char OpFlag = 0;
13304 unsigned WrapperKind = X86ISD::Wrapper;
13305 CodeModel::Model M = DAG.getTarget().getCodeModel();
13307 if (Subtarget->isPICStyleRIPRel() &&
13308 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13309 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13310 OpFlag = X86II::MO_GOTPCREL;
13311 WrapperKind = X86ISD::WrapperRIP;
13312 } else if (Subtarget->isPICStyleGOT()) {
13313 OpFlag = X86II::MO_GOT;
13314 } else if (Subtarget->isPICStyleStubPIC()) {
13315 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13316 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13317 OpFlag = X86II::MO_DARWIN_NONLAZY;
13320 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13323 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13325 // With PIC, the address is actually $g + Offset.
13326 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13327 !Subtarget->is64Bit()) {
13328 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13329 DAG.getNode(X86ISD::GlobalBaseReg,
13330 SDLoc(), getPointerTy()),
13334 // For symbols that require a load from a stub to get the address, emit the
13336 if (isGlobalStubReference(OpFlag))
13337 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13338 MachinePointerInfo::getGOT(), false, false, false, 0);
13344 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13345 // Create the TargetBlockAddressAddress node.
13346 unsigned char OpFlags =
13347 Subtarget->ClassifyBlockAddressReference();
13348 CodeModel::Model M = DAG.getTarget().getCodeModel();
13349 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13350 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13352 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13355 if (Subtarget->isPICStyleRIPRel() &&
13356 (M == CodeModel::Small || M == CodeModel::Kernel))
13357 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13359 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13361 // With PIC, the address is actually $g + Offset.
13362 if (isGlobalRelativeToPICBase(OpFlags)) {
13363 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13364 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13372 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13373 int64_t Offset, SelectionDAG &DAG) const {
13374 // Create the TargetGlobalAddress node, folding in the constant
13375 // offset if it is legal.
13376 unsigned char OpFlags =
13377 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13378 CodeModel::Model M = DAG.getTarget().getCodeModel();
13380 if (OpFlags == X86II::MO_NO_FLAG &&
13381 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13382 // A direct static reference to a global.
13383 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13386 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13389 if (Subtarget->isPICStyleRIPRel() &&
13390 (M == CodeModel::Small || M == CodeModel::Kernel))
13391 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13393 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13395 // With PIC, the address is actually $g + Offset.
13396 if (isGlobalRelativeToPICBase(OpFlags)) {
13397 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13398 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13402 // For globals that require a load from a stub to get the address, emit the
13404 if (isGlobalStubReference(OpFlags))
13405 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13406 MachinePointerInfo::getGOT(), false, false, false, 0);
13408 // If there was a non-zero offset that we didn't fold, create an explicit
13409 // addition for it.
13411 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13412 DAG.getConstant(Offset, getPointerTy()));
13418 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13419 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13420 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13421 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13425 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13426 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13427 unsigned char OperandFlags, bool LocalDynamic = false) {
13428 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13429 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13431 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13432 GA->getValueType(0),
13436 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13440 SDValue Ops[] = { Chain, TGA, *InFlag };
13441 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13443 SDValue Ops[] = { Chain, TGA };
13444 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13447 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13448 MFI->setAdjustsStack(true);
13449 MFI->setHasCalls(true);
13451 SDValue Flag = Chain.getValue(1);
13452 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13455 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13457 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13460 SDLoc dl(GA); // ? function entry point might be better
13461 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13462 DAG.getNode(X86ISD::GlobalBaseReg,
13463 SDLoc(), PtrVT), InFlag);
13464 InFlag = Chain.getValue(1);
13466 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13469 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13471 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13473 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13474 X86::RAX, X86II::MO_TLSGD);
13477 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13483 // Get the start address of the TLS block for this module.
13484 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13485 .getInfo<X86MachineFunctionInfo>();
13486 MFI->incNumLocalDynamicTLSAccesses();
13490 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13491 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13494 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13495 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13496 InFlag = Chain.getValue(1);
13497 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13498 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13501 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13505 unsigned char OperandFlags = X86II::MO_DTPOFF;
13506 unsigned WrapperKind = X86ISD::Wrapper;
13507 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13508 GA->getValueType(0),
13509 GA->getOffset(), OperandFlags);
13510 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13512 // Add x@dtpoff with the base.
13513 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13516 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13517 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13518 const EVT PtrVT, TLSModel::Model model,
13519 bool is64Bit, bool isPIC) {
13522 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13523 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13524 is64Bit ? 257 : 256));
13526 SDValue ThreadPointer =
13527 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13528 MachinePointerInfo(Ptr), false, false, false, 0);
13530 unsigned char OperandFlags = 0;
13531 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13533 unsigned WrapperKind = X86ISD::Wrapper;
13534 if (model == TLSModel::LocalExec) {
13535 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13536 } else if (model == TLSModel::InitialExec) {
13538 OperandFlags = X86II::MO_GOTTPOFF;
13539 WrapperKind = X86ISD::WrapperRIP;
13541 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13544 llvm_unreachable("Unexpected model");
13547 // emit "addl x@ntpoff,%eax" (local exec)
13548 // or "addl x@indntpoff,%eax" (initial exec)
13549 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13551 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13552 GA->getOffset(), OperandFlags);
13553 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13555 if (model == TLSModel::InitialExec) {
13556 if (isPIC && !is64Bit) {
13557 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13558 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13562 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13563 MachinePointerInfo::getGOT(), false, false, false, 0);
13566 // The address of the thread local variable is the add of the thread
13567 // pointer with the offset of the variable.
13568 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13572 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13574 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13575 const GlobalValue *GV = GA->getGlobal();
13577 if (Subtarget->isTargetELF()) {
13578 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13581 case TLSModel::GeneralDynamic:
13582 if (Subtarget->is64Bit())
13583 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13584 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13585 case TLSModel::LocalDynamic:
13586 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13587 Subtarget->is64Bit());
13588 case TLSModel::InitialExec:
13589 case TLSModel::LocalExec:
13590 return LowerToTLSExecModel(
13591 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13592 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13594 llvm_unreachable("Unknown TLS model.");
13597 if (Subtarget->isTargetDarwin()) {
13598 // Darwin only has one model of TLS. Lower to that.
13599 unsigned char OpFlag = 0;
13600 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13601 X86ISD::WrapperRIP : X86ISD::Wrapper;
13603 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13604 // global base reg.
13605 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13606 !Subtarget->is64Bit();
13608 OpFlag = X86II::MO_TLVP_PIC_BASE;
13610 OpFlag = X86II::MO_TLVP;
13612 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13613 GA->getValueType(0),
13614 GA->getOffset(), OpFlag);
13615 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13617 // With PIC32, the address is actually $g + Offset.
13619 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13620 DAG.getNode(X86ISD::GlobalBaseReg,
13621 SDLoc(), getPointerTy()),
13624 // Lowering the machine isd will make sure everything is in the right
13626 SDValue Chain = DAG.getEntryNode();
13627 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13628 SDValue Args[] = { Chain, Offset };
13629 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13631 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13632 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13633 MFI->setAdjustsStack(true);
13635 // And our return value (tls address) is in the standard call return value
13637 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13638 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13639 Chain.getValue(1));
13642 if (Subtarget->isTargetKnownWindowsMSVC() ||
13643 Subtarget->isTargetWindowsGNU()) {
13644 // Just use the implicit TLS architecture
13645 // Need to generate someting similar to:
13646 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13648 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13649 // mov rcx, qword [rdx+rcx*8]
13650 // mov eax, .tls$:tlsvar
13651 // [rax+rcx] contains the address
13652 // Windows 64bit: gs:0x58
13653 // Windows 32bit: fs:__tls_array
13656 SDValue Chain = DAG.getEntryNode();
13658 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13659 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13660 // use its literal value of 0x2C.
13661 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13662 ? Type::getInt8PtrTy(*DAG.getContext(),
13664 : Type::getInt32PtrTy(*DAG.getContext(),
13668 Subtarget->is64Bit()
13669 ? DAG.getIntPtrConstant(0x58)
13670 : (Subtarget->isTargetWindowsGNU()
13671 ? DAG.getIntPtrConstant(0x2C)
13672 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13674 SDValue ThreadPointer =
13675 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13676 MachinePointerInfo(Ptr), false, false, false, 0);
13678 // Load the _tls_index variable
13679 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13680 if (Subtarget->is64Bit())
13681 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13682 IDX, MachinePointerInfo(), MVT::i32,
13683 false, false, false, 0);
13685 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13686 false, false, false, 0);
13688 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13690 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13692 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13693 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13694 false, false, false, 0);
13696 // Get the offset of start of .tls section
13697 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13698 GA->getValueType(0),
13699 GA->getOffset(), X86II::MO_SECREL);
13700 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13702 // The address of the thread local variable is the add of the thread
13703 // pointer with the offset of the variable.
13704 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13707 llvm_unreachable("TLS not implemented for this target.");
13710 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13711 /// and take a 2 x i32 value to shift plus a shift amount.
13712 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13713 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13714 MVT VT = Op.getSimpleValueType();
13715 unsigned VTBits = VT.getSizeInBits();
13717 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13718 SDValue ShOpLo = Op.getOperand(0);
13719 SDValue ShOpHi = Op.getOperand(1);
13720 SDValue ShAmt = Op.getOperand(2);
13721 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13722 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13724 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13725 DAG.getConstant(VTBits - 1, MVT::i8));
13726 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13727 DAG.getConstant(VTBits - 1, MVT::i8))
13728 : DAG.getConstant(0, VT);
13730 SDValue Tmp2, Tmp3;
13731 if (Op.getOpcode() == ISD::SHL_PARTS) {
13732 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13733 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13735 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13736 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13739 // If the shift amount is larger or equal than the width of a part we can't
13740 // rely on the results of shld/shrd. Insert a test and select the appropriate
13741 // values for large shift amounts.
13742 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13743 DAG.getConstant(VTBits, MVT::i8));
13744 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13745 AndNode, DAG.getConstant(0, MVT::i8));
13748 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13749 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13750 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13752 if (Op.getOpcode() == ISD::SHL_PARTS) {
13753 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13754 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13756 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13757 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13760 SDValue Ops[2] = { Lo, Hi };
13761 return DAG.getMergeValues(Ops, dl);
13764 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13765 SelectionDAG &DAG) const {
13766 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13769 if (SrcVT.isVector()) {
13770 if (SrcVT.getVectorElementType() == MVT::i1) {
13771 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13772 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13773 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13774 Op.getOperand(0)));
13779 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13780 "Unknown SINT_TO_FP to lower!");
13782 // These are really Legal; return the operand so the caller accepts it as
13784 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13786 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13787 Subtarget->is64Bit()) {
13791 unsigned Size = SrcVT.getSizeInBits()/8;
13792 MachineFunction &MF = DAG.getMachineFunction();
13793 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13794 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13795 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13797 MachinePointerInfo::getFixedStack(SSFI),
13799 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13802 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13804 SelectionDAG &DAG) const {
13808 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13810 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13812 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13814 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13816 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13817 MachineMemOperand *MMO;
13819 int SSFI = FI->getIndex();
13821 DAG.getMachineFunction()
13822 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13823 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13825 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13826 StackSlot = StackSlot.getOperand(1);
13828 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13829 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13831 Tys, Ops, SrcVT, MMO);
13834 Chain = Result.getValue(1);
13835 SDValue InFlag = Result.getValue(2);
13837 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13838 // shouldn't be necessary except that RFP cannot be live across
13839 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13840 MachineFunction &MF = DAG.getMachineFunction();
13841 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13842 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13843 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13844 Tys = DAG.getVTList(MVT::Other);
13846 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13848 MachineMemOperand *MMO =
13849 DAG.getMachineFunction()
13850 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13851 MachineMemOperand::MOStore, SSFISize, SSFISize);
13853 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13854 Ops, Op.getValueType(), MMO);
13855 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13856 MachinePointerInfo::getFixedStack(SSFI),
13857 false, false, false, 0);
13863 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13864 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13865 SelectionDAG &DAG) const {
13866 // This algorithm is not obvious. Here it is what we're trying to output:
13869 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13870 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13872 haddpd %xmm0, %xmm0
13874 pshufd $0x4e, %xmm0, %xmm1
13880 LLVMContext *Context = DAG.getContext();
13882 // Build some magic constants.
13883 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13884 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13885 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13887 SmallVector<Constant*,2> CV1;
13889 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13890 APInt(64, 0x4330000000000000ULL))));
13892 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13893 APInt(64, 0x4530000000000000ULL))));
13894 Constant *C1 = ConstantVector::get(CV1);
13895 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13897 // Load the 64-bit value into an XMM register.
13898 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13900 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13901 MachinePointerInfo::getConstantPool(),
13902 false, false, false, 16);
13903 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13904 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13907 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13908 MachinePointerInfo::getConstantPool(),
13909 false, false, false, 16);
13910 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13911 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13914 if (Subtarget->hasSSE3()) {
13915 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13916 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13918 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13919 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13921 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13922 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13926 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13927 DAG.getIntPtrConstant(0));
13930 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13931 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13932 SelectionDAG &DAG) const {
13934 // FP constant to bias correct the final result.
13935 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13938 // Load the 32-bit value into an XMM register.
13939 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13942 // Zero out the upper parts of the register.
13943 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13945 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13946 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13947 DAG.getIntPtrConstant(0));
13949 // Or the load with the bias.
13950 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13951 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13952 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13953 MVT::v2f64, Load)),
13954 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13955 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13956 MVT::v2f64, Bias)));
13957 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13958 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13959 DAG.getIntPtrConstant(0));
13961 // Subtract the bias.
13962 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13964 // Handle final rounding.
13965 EVT DestVT = Op.getValueType();
13967 if (DestVT.bitsLT(MVT::f64))
13968 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13969 DAG.getIntPtrConstant(0));
13970 if (DestVT.bitsGT(MVT::f64))
13971 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13973 // Handle final rounding.
13977 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13978 const X86Subtarget &Subtarget) {
13979 // The algorithm is the following:
13980 // #ifdef __SSE4_1__
13981 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13982 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13983 // (uint4) 0x53000000, 0xaa);
13985 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13986 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13988 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13989 // return (float4) lo + fhi;
13992 SDValue V = Op->getOperand(0);
13993 EVT VecIntVT = V.getValueType();
13994 bool Is128 = VecIntVT == MVT::v4i32;
13995 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13996 // If we convert to something else than the supported type, e.g., to v4f64,
13998 if (VecFloatVT != Op->getValueType(0))
14001 unsigned NumElts = VecIntVT.getVectorNumElements();
14002 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
14003 "Unsupported custom type");
14004 assert(NumElts <= 8 && "The size of the constant array must be fixed");
14006 // In the #idef/#else code, we have in common:
14007 // - The vector of constants:
14013 // Create the splat vector for 0x4b000000.
14014 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
14015 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
14016 CstLow, CstLow, CstLow, CstLow};
14017 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
14018 makeArrayRef(&CstLowArray[0], NumElts));
14019 // Create the splat vector for 0x53000000.
14020 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
14021 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
14022 CstHigh, CstHigh, CstHigh, CstHigh};
14023 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
14024 makeArrayRef(&CstHighArray[0], NumElts));
14026 // Create the right shift.
14027 SDValue CstShift = DAG.getConstant(16, MVT::i32);
14028 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
14029 CstShift, CstShift, CstShift, CstShift};
14030 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
14031 makeArrayRef(&CstShiftArray[0], NumElts));
14032 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
14035 if (Subtarget.hasSSE41()) {
14036 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
14037 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
14038 SDValue VecCstLowBitcast =
14039 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
14040 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
14041 // Low will be bitcasted right away, so do not bother bitcasting back to its
14043 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
14044 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
14045 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
14046 // (uint4) 0x53000000, 0xaa);
14047 SDValue VecCstHighBitcast =
14048 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
14049 SDValue VecShiftBitcast =
14050 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
14051 // High will be bitcasted right away, so do not bother bitcasting back to
14052 // its original type.
14053 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
14054 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
14056 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
14057 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
14058 CstMask, CstMask, CstMask);
14059 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
14060 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
14061 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
14063 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
14064 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
14067 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
14068 SDValue CstFAdd = DAG.getConstantFP(
14069 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
14070 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
14071 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
14072 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
14073 makeArrayRef(&CstFAddArray[0], NumElts));
14075 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
14076 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
14078 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
14079 // return (float4) lo + fhi;
14080 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
14081 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
14084 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
14085 SelectionDAG &DAG) const {
14086 SDValue N0 = Op.getOperand(0);
14087 MVT SVT = N0.getSimpleValueType();
14090 switch (SVT.SimpleTy) {
14092 llvm_unreachable("Custom UINT_TO_FP is not supported!");
14097 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
14098 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
14099 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
14103 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
14105 llvm_unreachable(nullptr);
14108 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
14109 SelectionDAG &DAG) const {
14110 SDValue N0 = Op.getOperand(0);
14113 if (Op.getValueType().isVector())
14114 return lowerUINT_TO_FP_vec(Op, DAG);
14116 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
14117 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
14118 // the optimization here.
14119 if (DAG.SignBitIsZero(N0))
14120 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
14122 MVT SrcVT = N0.getSimpleValueType();
14123 MVT DstVT = Op.getSimpleValueType();
14124 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
14125 return LowerUINT_TO_FP_i64(Op, DAG);
14126 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
14127 return LowerUINT_TO_FP_i32(Op, DAG);
14128 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
14131 // Make a 64-bit buffer, and use it to build an FILD.
14132 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
14133 if (SrcVT == MVT::i32) {
14134 SDValue WordOff = DAG.getConstant(4, getPointerTy());
14135 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
14136 getPointerTy(), StackSlot, WordOff);
14137 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
14138 StackSlot, MachinePointerInfo(),
14140 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
14141 OffsetSlot, MachinePointerInfo(),
14143 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
14147 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
14148 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
14149 StackSlot, MachinePointerInfo(),
14151 // For i64 source, we need to add the appropriate power of 2 if the input
14152 // was negative. This is the same as the optimization in
14153 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
14154 // we must be careful to do the computation in x87 extended precision, not
14155 // in SSE. (The generic code can't know it's OK to do this, or how to.)
14156 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
14157 MachineMemOperand *MMO =
14158 DAG.getMachineFunction()
14159 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14160 MachineMemOperand::MOLoad, 8, 8);
14162 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
14163 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
14164 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
14167 APInt FF(32, 0x5F800000ULL);
14169 // Check whether the sign bit is set.
14170 SDValue SignSet = DAG.getSetCC(dl,
14171 getSetCCResultType(*DAG.getContext(), MVT::i64),
14172 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14175 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14176 SDValue FudgePtr = DAG.getConstantPool(
14177 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14180 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14181 SDValue Zero = DAG.getIntPtrConstant(0);
14182 SDValue Four = DAG.getIntPtrConstant(4);
14183 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14185 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14187 // Load the value out, extending it from f32 to f80.
14188 // FIXME: Avoid the extend by constructing the right constant pool?
14189 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14190 FudgePtr, MachinePointerInfo::getConstantPool(),
14191 MVT::f32, false, false, false, 4);
14192 // Extend everything to 80 bits to force it to be done on x87.
14193 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14194 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14197 std::pair<SDValue,SDValue>
14198 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14199 bool IsSigned, bool IsReplace) const {
14202 EVT DstTy = Op.getValueType();
14204 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14205 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14209 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14210 DstTy.getSimpleVT() >= MVT::i16 &&
14211 "Unknown FP_TO_INT to lower!");
14213 // These are really Legal.
14214 if (DstTy == MVT::i32 &&
14215 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14216 return std::make_pair(SDValue(), SDValue());
14217 if (Subtarget->is64Bit() &&
14218 DstTy == MVT::i64 &&
14219 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14220 return std::make_pair(SDValue(), SDValue());
14222 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14223 // stack slot, or into the FTOL runtime function.
14224 MachineFunction &MF = DAG.getMachineFunction();
14225 unsigned MemSize = DstTy.getSizeInBits()/8;
14226 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14227 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14230 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14231 Opc = X86ISD::WIN_FTOL;
14233 switch (DstTy.getSimpleVT().SimpleTy) {
14234 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14235 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14236 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14237 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14240 SDValue Chain = DAG.getEntryNode();
14241 SDValue Value = Op.getOperand(0);
14242 EVT TheVT = Op.getOperand(0).getValueType();
14243 // FIXME This causes a redundant load/store if the SSE-class value is already
14244 // in memory, such as if it is on the callstack.
14245 if (isScalarFPTypeInSSEReg(TheVT)) {
14246 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14247 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14248 MachinePointerInfo::getFixedStack(SSFI),
14250 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14252 Chain, StackSlot, DAG.getValueType(TheVT)
14255 MachineMemOperand *MMO =
14256 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14257 MachineMemOperand::MOLoad, MemSize, MemSize);
14258 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14259 Chain = Value.getValue(1);
14260 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14261 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14264 MachineMemOperand *MMO =
14265 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14266 MachineMemOperand::MOStore, MemSize, MemSize);
14268 if (Opc != X86ISD::WIN_FTOL) {
14269 // Build the FP_TO_INT*_IN_MEM
14270 SDValue Ops[] = { Chain, Value, StackSlot };
14271 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14273 return std::make_pair(FIST, StackSlot);
14275 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14276 DAG.getVTList(MVT::Other, MVT::Glue),
14278 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14279 MVT::i32, ftol.getValue(1));
14280 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14281 MVT::i32, eax.getValue(2));
14282 SDValue Ops[] = { eax, edx };
14283 SDValue pair = IsReplace
14284 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14285 : DAG.getMergeValues(Ops, DL);
14286 return std::make_pair(pair, SDValue());
14290 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14291 const X86Subtarget *Subtarget) {
14292 MVT VT = Op->getSimpleValueType(0);
14293 SDValue In = Op->getOperand(0);
14294 MVT InVT = In.getSimpleValueType();
14297 // Optimize vectors in AVX mode:
14300 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14301 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14302 // Concat upper and lower parts.
14305 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14306 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14307 // Concat upper and lower parts.
14310 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14311 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14312 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14315 if (Subtarget->hasInt256())
14316 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14318 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14319 SDValue Undef = DAG.getUNDEF(InVT);
14320 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14321 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14322 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14324 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14325 VT.getVectorNumElements()/2);
14327 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14328 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14330 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14333 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14334 SelectionDAG &DAG) {
14335 MVT VT = Op->getSimpleValueType(0);
14336 SDValue In = Op->getOperand(0);
14337 MVT InVT = In.getSimpleValueType();
14339 unsigned int NumElts = VT.getVectorNumElements();
14340 if (NumElts != 8 && NumElts != 16)
14343 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14344 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14346 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14348 // Now we have only mask extension
14349 assert(InVT.getVectorElementType() == MVT::i1);
14350 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14351 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14352 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14353 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14354 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14355 MachinePointerInfo::getConstantPool(),
14356 false, false, false, Alignment);
14358 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14359 if (VT.is512BitVector())
14361 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14364 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14365 SelectionDAG &DAG) {
14366 if (Subtarget->hasFp256()) {
14367 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14375 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14376 SelectionDAG &DAG) {
14378 MVT VT = Op.getSimpleValueType();
14379 SDValue In = Op.getOperand(0);
14380 MVT SVT = In.getSimpleValueType();
14382 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14383 return LowerZERO_EXTEND_AVX512(Op, DAG);
14385 if (Subtarget->hasFp256()) {
14386 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14391 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14392 VT.getVectorNumElements() != SVT.getVectorNumElements());
14396 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14398 MVT VT = Op.getSimpleValueType();
14399 SDValue In = Op.getOperand(0);
14400 MVT InVT = In.getSimpleValueType();
14402 if (VT == MVT::i1) {
14403 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14404 "Invalid scalar TRUNCATE operation");
14405 if (InVT.getSizeInBits() >= 32)
14407 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14408 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14410 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14411 "Invalid TRUNCATE operation");
14413 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14414 if (VT.getVectorElementType().getSizeInBits() >=8)
14415 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14417 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14418 unsigned NumElts = InVT.getVectorNumElements();
14419 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14420 if (InVT.getSizeInBits() < 512) {
14421 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14422 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14426 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14427 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14428 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14429 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14430 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14431 MachinePointerInfo::getConstantPool(),
14432 false, false, false, Alignment);
14433 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14434 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14435 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14438 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14439 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14440 if (Subtarget->hasInt256()) {
14441 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14442 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14443 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14445 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14446 DAG.getIntPtrConstant(0));
14449 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14450 DAG.getIntPtrConstant(0));
14451 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14452 DAG.getIntPtrConstant(2));
14453 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14454 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14455 static const int ShufMask[] = {0, 2, 4, 6};
14456 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14459 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14460 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14461 if (Subtarget->hasInt256()) {
14462 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14464 SmallVector<SDValue,32> pshufbMask;
14465 for (unsigned i = 0; i < 2; ++i) {
14466 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14467 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14468 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14469 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14470 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14471 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14472 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14473 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14474 for (unsigned j = 0; j < 8; ++j)
14475 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14477 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14478 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14479 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14481 static const int ShufMask[] = {0, 2, -1, -1};
14482 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14484 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14485 DAG.getIntPtrConstant(0));
14486 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14489 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14490 DAG.getIntPtrConstant(0));
14492 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14493 DAG.getIntPtrConstant(4));
14495 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14496 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14498 // The PSHUFB mask:
14499 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14500 -1, -1, -1, -1, -1, -1, -1, -1};
14502 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14503 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14504 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14506 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14507 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14509 // The MOVLHPS Mask:
14510 static const int ShufMask2[] = {0, 1, 4, 5};
14511 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14512 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14515 // Handle truncation of V256 to V128 using shuffles.
14516 if (!VT.is128BitVector() || !InVT.is256BitVector())
14519 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14521 unsigned NumElems = VT.getVectorNumElements();
14522 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14524 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14525 // Prepare truncation shuffle mask
14526 for (unsigned i = 0; i != NumElems; ++i)
14527 MaskVec[i] = i * 2;
14528 SDValue V = DAG.getVectorShuffle(NVT, DL,
14529 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14530 DAG.getUNDEF(NVT), &MaskVec[0]);
14531 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14532 DAG.getIntPtrConstant(0));
14535 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14536 SelectionDAG &DAG) const {
14537 assert(!Op.getSimpleValueType().isVector());
14539 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14540 /*IsSigned=*/ true, /*IsReplace=*/ false);
14541 SDValue FIST = Vals.first, StackSlot = Vals.second;
14542 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14543 if (!FIST.getNode()) return Op;
14545 if (StackSlot.getNode())
14546 // Load the result.
14547 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14548 FIST, StackSlot, MachinePointerInfo(),
14549 false, false, false, 0);
14551 // The node is the result.
14555 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14556 SelectionDAG &DAG) const {
14557 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14558 /*IsSigned=*/ false, /*IsReplace=*/ false);
14559 SDValue FIST = Vals.first, StackSlot = Vals.second;
14560 assert(FIST.getNode() && "Unexpected failure");
14562 if (StackSlot.getNode())
14563 // Load the result.
14564 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14565 FIST, StackSlot, MachinePointerInfo(),
14566 false, false, false, 0);
14568 // The node is the result.
14572 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14574 MVT VT = Op.getSimpleValueType();
14575 SDValue In = Op.getOperand(0);
14576 MVT SVT = In.getSimpleValueType();
14578 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14580 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14581 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14582 In, DAG.getUNDEF(SVT)));
14585 /// The only differences between FABS and FNEG are the mask and the logic op.
14586 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14587 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14588 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14589 "Wrong opcode for lowering FABS or FNEG.");
14591 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14593 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14594 // into an FNABS. We'll lower the FABS after that if it is still in use.
14596 for (SDNode *User : Op->uses())
14597 if (User->getOpcode() == ISD::FNEG)
14600 SDValue Op0 = Op.getOperand(0);
14601 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14604 MVT VT = Op.getSimpleValueType();
14605 // Assume scalar op for initialization; update for vector if needed.
14606 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14607 // generate a 16-byte vector constant and logic op even for the scalar case.
14608 // Using a 16-byte mask allows folding the load of the mask with
14609 // the logic op, so it can save (~4 bytes) on code size.
14611 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14612 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14613 // decide if we should generate a 16-byte constant mask when we only need 4 or
14614 // 8 bytes for the scalar case.
14615 if (VT.isVector()) {
14616 EltVT = VT.getVectorElementType();
14617 NumElts = VT.getVectorNumElements();
14620 unsigned EltBits = EltVT.getSizeInBits();
14621 LLVMContext *Context = DAG.getContext();
14622 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14624 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14625 Constant *C = ConstantInt::get(*Context, MaskElt);
14626 C = ConstantVector::getSplat(NumElts, C);
14627 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14628 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14629 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14630 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14631 MachinePointerInfo::getConstantPool(),
14632 false, false, false, Alignment);
14634 if (VT.isVector()) {
14635 // For a vector, cast operands to a vector type, perform the logic op,
14636 // and cast the result back to the original value type.
14637 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14638 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14639 SDValue Operand = IsFNABS ?
14640 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14641 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14642 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14643 return DAG.getNode(ISD::BITCAST, dl, VT,
14644 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14647 // If not vector, then scalar.
14648 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14649 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14650 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14653 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14654 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14655 LLVMContext *Context = DAG.getContext();
14656 SDValue Op0 = Op.getOperand(0);
14657 SDValue Op1 = Op.getOperand(1);
14659 MVT VT = Op.getSimpleValueType();
14660 MVT SrcVT = Op1.getSimpleValueType();
14662 // If second operand is smaller, extend it first.
14663 if (SrcVT.bitsLT(VT)) {
14664 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14667 // And if it is bigger, shrink it first.
14668 if (SrcVT.bitsGT(VT)) {
14669 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14673 // At this point the operands and the result should have the same
14674 // type, and that won't be f80 since that is not custom lowered.
14676 const fltSemantics &Sem =
14677 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14678 const unsigned SizeInBits = VT.getSizeInBits();
14680 SmallVector<Constant *, 4> CV(
14681 VT == MVT::f64 ? 2 : 4,
14682 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14684 // First, clear all bits but the sign bit from the second operand (sign).
14685 CV[0] = ConstantFP::get(*Context,
14686 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14687 Constant *C = ConstantVector::get(CV);
14688 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14689 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14690 MachinePointerInfo::getConstantPool(),
14691 false, false, false, 16);
14692 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14694 // Next, clear the sign bit from the first operand (magnitude).
14695 // If it's a constant, we can clear it here.
14696 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
14697 APFloat APF = Op0CN->getValueAPF();
14698 // If the magnitude is a positive zero, the sign bit alone is enough.
14699 if (APF.isPosZero())
14702 CV[0] = ConstantFP::get(*Context, APF);
14704 CV[0] = ConstantFP::get(
14706 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14708 C = ConstantVector::get(CV);
14709 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14710 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14711 MachinePointerInfo::getConstantPool(),
14712 false, false, false, 16);
14713 // If the magnitude operand wasn't a constant, we need to AND out the sign.
14714 if (!isa<ConstantFPSDNode>(Op0))
14715 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
14717 // OR the magnitude value with the sign bit.
14718 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14721 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14722 SDValue N0 = Op.getOperand(0);
14724 MVT VT = Op.getSimpleValueType();
14726 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14727 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14728 DAG.getConstant(1, VT));
14729 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14732 // Check whether an OR'd tree is PTEST-able.
14733 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14734 SelectionDAG &DAG) {
14735 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14737 if (!Subtarget->hasSSE41())
14740 if (!Op->hasOneUse())
14743 SDNode *N = Op.getNode();
14746 SmallVector<SDValue, 8> Opnds;
14747 DenseMap<SDValue, unsigned> VecInMap;
14748 SmallVector<SDValue, 8> VecIns;
14749 EVT VT = MVT::Other;
14751 // Recognize a special case where a vector is casted into wide integer to
14753 Opnds.push_back(N->getOperand(0));
14754 Opnds.push_back(N->getOperand(1));
14756 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14757 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14758 // BFS traverse all OR'd operands.
14759 if (I->getOpcode() == ISD::OR) {
14760 Opnds.push_back(I->getOperand(0));
14761 Opnds.push_back(I->getOperand(1));
14762 // Re-evaluate the number of nodes to be traversed.
14763 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14767 // Quit if a non-EXTRACT_VECTOR_ELT
14768 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14771 // Quit if without a constant index.
14772 SDValue Idx = I->getOperand(1);
14773 if (!isa<ConstantSDNode>(Idx))
14776 SDValue ExtractedFromVec = I->getOperand(0);
14777 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14778 if (M == VecInMap.end()) {
14779 VT = ExtractedFromVec.getValueType();
14780 // Quit if not 128/256-bit vector.
14781 if (!VT.is128BitVector() && !VT.is256BitVector())
14783 // Quit if not the same type.
14784 if (VecInMap.begin() != VecInMap.end() &&
14785 VT != VecInMap.begin()->first.getValueType())
14787 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14788 VecIns.push_back(ExtractedFromVec);
14790 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14793 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14794 "Not extracted from 128-/256-bit vector.");
14796 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14798 for (DenseMap<SDValue, unsigned>::const_iterator
14799 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14800 // Quit if not all elements are used.
14801 if (I->second != FullMask)
14805 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14807 // Cast all vectors into TestVT for PTEST.
14808 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14809 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14811 // If more than one full vectors are evaluated, OR them first before PTEST.
14812 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14813 // Each iteration will OR 2 nodes and append the result until there is only
14814 // 1 node left, i.e. the final OR'd value of all vectors.
14815 SDValue LHS = VecIns[Slot];
14816 SDValue RHS = VecIns[Slot + 1];
14817 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14820 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14821 VecIns.back(), VecIns.back());
14824 /// \brief return true if \c Op has a use that doesn't just read flags.
14825 static bool hasNonFlagsUse(SDValue Op) {
14826 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14828 SDNode *User = *UI;
14829 unsigned UOpNo = UI.getOperandNo();
14830 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14831 // Look pass truncate.
14832 UOpNo = User->use_begin().getOperandNo();
14833 User = *User->use_begin();
14836 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14837 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14843 /// Emit nodes that will be selected as "test Op0,Op0", or something
14845 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14846 SelectionDAG &DAG) const {
14847 if (Op.getValueType() == MVT::i1)
14848 // KORTEST instruction should be selected
14849 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14850 DAG.getConstant(0, Op.getValueType()));
14852 // CF and OF aren't always set the way we want. Determine which
14853 // of these we need.
14854 bool NeedCF = false;
14855 bool NeedOF = false;
14858 case X86::COND_A: case X86::COND_AE:
14859 case X86::COND_B: case X86::COND_BE:
14862 case X86::COND_G: case X86::COND_GE:
14863 case X86::COND_L: case X86::COND_LE:
14864 case X86::COND_O: case X86::COND_NO: {
14865 // Check if we really need to set the
14866 // Overflow flag. If NoSignedWrap is present
14867 // that is not actually needed.
14868 switch (Op->getOpcode()) {
14873 const BinaryWithFlagsSDNode *BinNode =
14874 cast<BinaryWithFlagsSDNode>(Op.getNode());
14875 if (BinNode->hasNoSignedWrap())
14885 // See if we can use the EFLAGS value from the operand instead of
14886 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14887 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14888 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14889 // Emit a CMP with 0, which is the TEST pattern.
14890 //if (Op.getValueType() == MVT::i1)
14891 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14892 // DAG.getConstant(0, MVT::i1));
14893 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14894 DAG.getConstant(0, Op.getValueType()));
14896 unsigned Opcode = 0;
14897 unsigned NumOperands = 0;
14899 // Truncate operations may prevent the merge of the SETCC instruction
14900 // and the arithmetic instruction before it. Attempt to truncate the operands
14901 // of the arithmetic instruction and use a reduced bit-width instruction.
14902 bool NeedTruncation = false;
14903 SDValue ArithOp = Op;
14904 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14905 SDValue Arith = Op->getOperand(0);
14906 // Both the trunc and the arithmetic op need to have one user each.
14907 if (Arith->hasOneUse())
14908 switch (Arith.getOpcode()) {
14915 NeedTruncation = true;
14921 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14922 // which may be the result of a CAST. We use the variable 'Op', which is the
14923 // non-casted variable when we check for possible users.
14924 switch (ArithOp.getOpcode()) {
14926 // Due to an isel shortcoming, be conservative if this add is likely to be
14927 // selected as part of a load-modify-store instruction. When the root node
14928 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14929 // uses of other nodes in the match, such as the ADD in this case. This
14930 // leads to the ADD being left around and reselected, with the result being
14931 // two adds in the output. Alas, even if none our users are stores, that
14932 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14933 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14934 // climbing the DAG back to the root, and it doesn't seem to be worth the
14936 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14937 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14938 if (UI->getOpcode() != ISD::CopyToReg &&
14939 UI->getOpcode() != ISD::SETCC &&
14940 UI->getOpcode() != ISD::STORE)
14943 if (ConstantSDNode *C =
14944 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14945 // An add of one will be selected as an INC.
14946 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14947 Opcode = X86ISD::INC;
14952 // An add of negative one (subtract of one) will be selected as a DEC.
14953 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14954 Opcode = X86ISD::DEC;
14960 // Otherwise use a regular EFLAGS-setting add.
14961 Opcode = X86ISD::ADD;
14966 // If we have a constant logical shift that's only used in a comparison
14967 // against zero turn it into an equivalent AND. This allows turning it into
14968 // a TEST instruction later.
14969 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14970 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14971 EVT VT = Op.getValueType();
14972 unsigned BitWidth = VT.getSizeInBits();
14973 unsigned ShAmt = Op->getConstantOperandVal(1);
14974 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14976 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14977 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14978 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14979 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14981 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14982 DAG.getConstant(Mask, VT));
14983 DAG.ReplaceAllUsesWith(Op, New);
14989 // If the primary and result isn't used, don't bother using X86ISD::AND,
14990 // because a TEST instruction will be better.
14991 if (!hasNonFlagsUse(Op))
14997 // Due to the ISEL shortcoming noted above, be conservative if this op is
14998 // likely to be selected as part of a load-modify-store instruction.
14999 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15000 UE = Op.getNode()->use_end(); UI != UE; ++UI)
15001 if (UI->getOpcode() == ISD::STORE)
15004 // Otherwise use a regular EFLAGS-setting instruction.
15005 switch (ArithOp.getOpcode()) {
15006 default: llvm_unreachable("unexpected operator!");
15007 case ISD::SUB: Opcode = X86ISD::SUB; break;
15008 case ISD::XOR: Opcode = X86ISD::XOR; break;
15009 case ISD::AND: Opcode = X86ISD::AND; break;
15011 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
15012 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
15013 if (EFLAGS.getNode())
15016 Opcode = X86ISD::OR;
15030 return SDValue(Op.getNode(), 1);
15036 // If we found that truncation is beneficial, perform the truncation and
15038 if (NeedTruncation) {
15039 EVT VT = Op.getValueType();
15040 SDValue WideVal = Op->getOperand(0);
15041 EVT WideVT = WideVal.getValueType();
15042 unsigned ConvertedOp = 0;
15043 // Use a target machine opcode to prevent further DAGCombine
15044 // optimizations that may separate the arithmetic operations
15045 // from the setcc node.
15046 switch (WideVal.getOpcode()) {
15048 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
15049 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
15050 case ISD::AND: ConvertedOp = X86ISD::AND; break;
15051 case ISD::OR: ConvertedOp = X86ISD::OR; break;
15052 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
15056 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15057 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
15058 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
15059 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
15060 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
15066 // Emit a CMP with 0, which is the TEST pattern.
15067 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
15068 DAG.getConstant(0, Op.getValueType()));
15070 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15071 SmallVector<SDValue, 4> Ops;
15072 for (unsigned i = 0; i != NumOperands; ++i)
15073 Ops.push_back(Op.getOperand(i));
15075 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
15076 DAG.ReplaceAllUsesWith(Op, New);
15077 return SDValue(New.getNode(), 1);
15080 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
15082 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
15083 SDLoc dl, SelectionDAG &DAG) const {
15084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
15085 if (C->getAPIntValue() == 0)
15086 return EmitTest(Op0, X86CC, dl, DAG);
15088 if (Op0.getValueType() == MVT::i1)
15089 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
15092 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
15093 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
15094 // Do the comparison at i32 if it's smaller, besides the Atom case.
15095 // This avoids subregister aliasing issues. Keep the smaller reference
15096 // if we're optimizing for size, however, as that'll allow better folding
15097 // of memory operations.
15098 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
15099 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
15100 AttributeSet::FunctionIndex, Attribute::MinSize) &&
15101 !Subtarget->isAtom()) {
15102 unsigned ExtendOp =
15103 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
15104 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
15105 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
15107 // Use SUB instead of CMP to enable CSE between SUB and CMP.
15108 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
15109 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
15111 return SDValue(Sub.getNode(), 1);
15113 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
15116 /// Convert a comparison if required by the subtarget.
15117 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
15118 SelectionDAG &DAG) const {
15119 // If the subtarget does not support the FUCOMI instruction, floating-point
15120 // comparisons have to be converted.
15121 if (Subtarget->hasCMov() ||
15122 Cmp.getOpcode() != X86ISD::CMP ||
15123 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
15124 !Cmp.getOperand(1).getValueType().isFloatingPoint())
15127 // The instruction selector will select an FUCOM instruction instead of
15128 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
15129 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
15130 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
15132 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
15133 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
15134 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
15135 DAG.getConstant(8, MVT::i8));
15136 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
15137 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
15140 /// The minimum architected relative accuracy is 2^-12. We need one
15141 /// Newton-Raphson step to have a good float result (24 bits of precision).
15142 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
15143 DAGCombinerInfo &DCI,
15144 unsigned &RefinementSteps,
15145 bool &UseOneConstNR) const {
15146 // FIXME: We should use instruction latency models to calculate the cost of
15147 // each potential sequence, but this is very hard to do reliably because
15148 // at least Intel's Core* chips have variable timing based on the number of
15149 // significant digits in the divisor and/or sqrt operand.
15150 if (!Subtarget->useSqrtEst())
15153 EVT VT = Op.getValueType();
15155 // SSE1 has rsqrtss and rsqrtps.
15156 // TODO: Add support for AVX512 (v16f32).
15157 // It is likely not profitable to do this for f64 because a double-precision
15158 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
15159 // instructions: convert to single, rsqrtss, convert back to double, refine
15160 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
15161 // along with FMA, this could be a throughput win.
15162 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15163 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15164 RefinementSteps = 1;
15165 UseOneConstNR = false;
15166 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
15171 /// The minimum architected relative accuracy is 2^-12. We need one
15172 /// Newton-Raphson step to have a good float result (24 bits of precision).
15173 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
15174 DAGCombinerInfo &DCI,
15175 unsigned &RefinementSteps) const {
15176 // FIXME: We should use instruction latency models to calculate the cost of
15177 // each potential sequence, but this is very hard to do reliably because
15178 // at least Intel's Core* chips have variable timing based on the number of
15179 // significant digits in the divisor.
15180 if (!Subtarget->useReciprocalEst())
15183 EVT VT = Op.getValueType();
15185 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15186 // TODO: Add support for AVX512 (v16f32).
15187 // It is likely not profitable to do this for f64 because a double-precision
15188 // reciprocal estimate with refinement on x86 prior to FMA requires
15189 // 15 instructions: convert to single, rcpss, convert back to double, refine
15190 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15191 // along with FMA, this could be a throughput win.
15192 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15193 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15194 RefinementSteps = ReciprocalEstimateRefinementSteps;
15195 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15200 static bool isAllOnes(SDValue V) {
15201 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15202 return C && C->isAllOnesValue();
15205 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15206 /// if it's possible.
15207 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15208 SDLoc dl, SelectionDAG &DAG) const {
15209 SDValue Op0 = And.getOperand(0);
15210 SDValue Op1 = And.getOperand(1);
15211 if (Op0.getOpcode() == ISD::TRUNCATE)
15212 Op0 = Op0.getOperand(0);
15213 if (Op1.getOpcode() == ISD::TRUNCATE)
15214 Op1 = Op1.getOperand(0);
15217 if (Op1.getOpcode() == ISD::SHL)
15218 std::swap(Op0, Op1);
15219 if (Op0.getOpcode() == ISD::SHL) {
15220 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15221 if (And00C->getZExtValue() == 1) {
15222 // If we looked past a truncate, check that it's only truncating away
15224 unsigned BitWidth = Op0.getValueSizeInBits();
15225 unsigned AndBitWidth = And.getValueSizeInBits();
15226 if (BitWidth > AndBitWidth) {
15228 DAG.computeKnownBits(Op0, Zeros, Ones);
15229 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15233 RHS = Op0.getOperand(1);
15235 } else if (Op1.getOpcode() == ISD::Constant) {
15236 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15237 uint64_t AndRHSVal = AndRHS->getZExtValue();
15238 SDValue AndLHS = Op0;
15240 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15241 LHS = AndLHS.getOperand(0);
15242 RHS = AndLHS.getOperand(1);
15245 // Use BT if the immediate can't be encoded in a TEST instruction.
15246 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15248 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15252 if (LHS.getNode()) {
15253 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15254 // instruction. Since the shift amount is in-range-or-undefined, we know
15255 // that doing a bittest on the i32 value is ok. We extend to i32 because
15256 // the encoding for the i16 version is larger than the i32 version.
15257 // Also promote i16 to i32 for performance / code size reason.
15258 if (LHS.getValueType() == MVT::i8 ||
15259 LHS.getValueType() == MVT::i16)
15260 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15262 // If the operand types disagree, extend the shift amount to match. Since
15263 // BT ignores high bits (like shifts) we can use anyextend.
15264 if (LHS.getValueType() != RHS.getValueType())
15265 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15267 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15268 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15269 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15270 DAG.getConstant(Cond, MVT::i8), BT);
15276 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15278 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15283 // SSE Condition code mapping:
15292 switch (SetCCOpcode) {
15293 default: llvm_unreachable("Unexpected SETCC condition");
15295 case ISD::SETEQ: SSECC = 0; break;
15297 case ISD::SETGT: Swap = true; // Fallthrough
15299 case ISD::SETOLT: SSECC = 1; break;
15301 case ISD::SETGE: Swap = true; // Fallthrough
15303 case ISD::SETOLE: SSECC = 2; break;
15304 case ISD::SETUO: SSECC = 3; break;
15306 case ISD::SETNE: SSECC = 4; break;
15307 case ISD::SETULE: Swap = true; // Fallthrough
15308 case ISD::SETUGE: SSECC = 5; break;
15309 case ISD::SETULT: Swap = true; // Fallthrough
15310 case ISD::SETUGT: SSECC = 6; break;
15311 case ISD::SETO: SSECC = 7; break;
15313 case ISD::SETONE: SSECC = 8; break;
15316 std::swap(Op0, Op1);
15321 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15322 // ones, and then concatenate the result back.
15323 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15324 MVT VT = Op.getSimpleValueType();
15326 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15327 "Unsupported value type for operation");
15329 unsigned NumElems = VT.getVectorNumElements();
15331 SDValue CC = Op.getOperand(2);
15333 // Extract the LHS vectors
15334 SDValue LHS = Op.getOperand(0);
15335 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15336 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15338 // Extract the RHS vectors
15339 SDValue RHS = Op.getOperand(1);
15340 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15341 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15343 // Issue the operation on the smaller types and concatenate the result back
15344 MVT EltVT = VT.getVectorElementType();
15345 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15346 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15347 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15348 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15351 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15352 const X86Subtarget *Subtarget) {
15353 SDValue Op0 = Op.getOperand(0);
15354 SDValue Op1 = Op.getOperand(1);
15355 SDValue CC = Op.getOperand(2);
15356 MVT VT = Op.getSimpleValueType();
15359 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15360 Op.getValueType().getScalarType() == MVT::i1 &&
15361 "Cannot set masked compare for this operation");
15363 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15365 bool Unsigned = false;
15368 switch (SetCCOpcode) {
15369 default: llvm_unreachable("Unexpected SETCC condition");
15370 case ISD::SETNE: SSECC = 4; break;
15371 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15372 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15373 case ISD::SETLT: Swap = true; //fall-through
15374 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15375 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15376 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15377 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15378 case ISD::SETULE: Unsigned = true; //fall-through
15379 case ISD::SETLE: SSECC = 2; break;
15383 std::swap(Op0, Op1);
15385 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15386 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15387 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15388 DAG.getConstant(SSECC, MVT::i8));
15391 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15392 /// operand \p Op1. If non-trivial (for example because it's not constant)
15393 /// return an empty value.
15394 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15396 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15400 MVT VT = Op1.getSimpleValueType();
15401 MVT EVT = VT.getVectorElementType();
15402 unsigned n = VT.getVectorNumElements();
15403 SmallVector<SDValue, 8> ULTOp1;
15405 for (unsigned i = 0; i < n; ++i) {
15406 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15407 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15410 // Avoid underflow.
15411 APInt Val = Elt->getAPIntValue();
15415 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15418 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15421 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15422 SelectionDAG &DAG) {
15423 SDValue Op0 = Op.getOperand(0);
15424 SDValue Op1 = Op.getOperand(1);
15425 SDValue CC = Op.getOperand(2);
15426 MVT VT = Op.getSimpleValueType();
15427 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15428 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15433 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15434 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15437 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15438 unsigned Opc = X86ISD::CMPP;
15439 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15440 assert(VT.getVectorNumElements() <= 16);
15441 Opc = X86ISD::CMPM;
15443 // In the two special cases we can't handle, emit two comparisons.
15446 unsigned CombineOpc;
15447 if (SetCCOpcode == ISD::SETUEQ) {
15448 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15450 assert(SetCCOpcode == ISD::SETONE);
15451 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15454 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15455 DAG.getConstant(CC0, MVT::i8));
15456 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15457 DAG.getConstant(CC1, MVT::i8));
15458 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15460 // Handle all other FP comparisons here.
15461 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15462 DAG.getConstant(SSECC, MVT::i8));
15465 // Break 256-bit integer vector compare into smaller ones.
15466 if (VT.is256BitVector() && !Subtarget->hasInt256())
15467 return Lower256IntVSETCC(Op, DAG);
15469 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15470 EVT OpVT = Op1.getValueType();
15471 if (Subtarget->hasAVX512()) {
15472 if (Op1.getValueType().is512BitVector() ||
15473 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15474 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15475 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15477 // In AVX-512 architecture setcc returns mask with i1 elements,
15478 // But there is no compare instruction for i8 and i16 elements in KNL.
15479 // We are not talking about 512-bit operands in this case, these
15480 // types are illegal.
15482 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15483 OpVT.getVectorElementType().getSizeInBits() >= 8))
15484 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15485 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15488 // We are handling one of the integer comparisons here. Since SSE only has
15489 // GT and EQ comparisons for integer, swapping operands and multiple
15490 // operations may be required for some comparisons.
15492 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15493 bool Subus = false;
15495 switch (SetCCOpcode) {
15496 default: llvm_unreachable("Unexpected SETCC condition");
15497 case ISD::SETNE: Invert = true;
15498 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15499 case ISD::SETLT: Swap = true;
15500 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15501 case ISD::SETGE: Swap = true;
15502 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15503 Invert = true; break;
15504 case ISD::SETULT: Swap = true;
15505 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15506 FlipSigns = true; break;
15507 case ISD::SETUGE: Swap = true;
15508 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15509 FlipSigns = true; Invert = true; break;
15512 // Special case: Use min/max operations for SETULE/SETUGE
15513 MVT VET = VT.getVectorElementType();
15515 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15516 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15519 switch (SetCCOpcode) {
15521 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15522 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15525 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15528 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15529 if (!MinMax && hasSubus) {
15530 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15532 // t = psubus Op0, Op1
15533 // pcmpeq t, <0..0>
15534 switch (SetCCOpcode) {
15536 case ISD::SETULT: {
15537 // If the comparison is against a constant we can turn this into a
15538 // setule. With psubus, setule does not require a swap. This is
15539 // beneficial because the constant in the register is no longer
15540 // destructed as the destination so it can be hoisted out of a loop.
15541 // Only do this pre-AVX since vpcmp* is no longer destructive.
15542 if (Subtarget->hasAVX())
15544 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15545 if (ULEOp1.getNode()) {
15547 Subus = true; Invert = false; Swap = false;
15551 // Psubus is better than flip-sign because it requires no inversion.
15552 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15553 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15557 Opc = X86ISD::SUBUS;
15563 std::swap(Op0, Op1);
15565 // Check that the operation in question is available (most are plain SSE2,
15566 // but PCMPGTQ and PCMPEQQ have different requirements).
15567 if (VT == MVT::v2i64) {
15568 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15569 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15571 // First cast everything to the right type.
15572 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15573 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15575 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15576 // bits of the inputs before performing those operations. The lower
15577 // compare is always unsigned.
15580 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15582 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15583 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15584 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15585 Sign, Zero, Sign, Zero);
15587 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15588 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15590 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15591 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15592 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15594 // Create masks for only the low parts/high parts of the 64 bit integers.
15595 static const int MaskHi[] = { 1, 1, 3, 3 };
15596 static const int MaskLo[] = { 0, 0, 2, 2 };
15597 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15598 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15599 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15601 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15602 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15605 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15607 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15610 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15611 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15612 // pcmpeqd + pshufd + pand.
15613 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15615 // First cast everything to the right type.
15616 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15617 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15620 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15622 // Make sure the lower and upper halves are both all-ones.
15623 static const int Mask[] = { 1, 0, 3, 2 };
15624 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15625 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15628 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15630 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15634 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15635 // bits of the inputs before performing those operations.
15637 EVT EltVT = VT.getVectorElementType();
15638 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15639 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15640 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15643 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15645 // If the logical-not of the result is required, perform that now.
15647 Result = DAG.getNOT(dl, Result, VT);
15650 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15653 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15654 getZeroVector(VT, Subtarget, DAG, dl));
15659 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15661 MVT VT = Op.getSimpleValueType();
15663 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15665 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15666 && "SetCC type must be 8-bit or 1-bit integer");
15667 SDValue Op0 = Op.getOperand(0);
15668 SDValue Op1 = Op.getOperand(1);
15670 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15672 // Optimize to BT if possible.
15673 // Lower (X & (1 << N)) == 0 to BT(X, N).
15674 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15675 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15676 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15677 Op1.getOpcode() == ISD::Constant &&
15678 cast<ConstantSDNode>(Op1)->isNullValue() &&
15679 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15680 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15681 if (NewSetCC.getNode()) {
15683 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15688 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15690 if (Op1.getOpcode() == ISD::Constant &&
15691 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15692 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15693 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15695 // If the input is a setcc, then reuse the input setcc or use a new one with
15696 // the inverted condition.
15697 if (Op0.getOpcode() == X86ISD::SETCC) {
15698 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15699 bool Invert = (CC == ISD::SETNE) ^
15700 cast<ConstantSDNode>(Op1)->isNullValue();
15704 CCode = X86::GetOppositeBranchCondition(CCode);
15705 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15706 DAG.getConstant(CCode, MVT::i8),
15707 Op0.getOperand(1));
15709 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15713 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15714 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15715 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15717 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15718 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15721 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15722 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15723 if (X86CC == X86::COND_INVALID)
15726 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15727 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15728 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15729 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15731 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15735 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15736 static bool isX86LogicalCmp(SDValue Op) {
15737 unsigned Opc = Op.getNode()->getOpcode();
15738 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15739 Opc == X86ISD::SAHF)
15741 if (Op.getResNo() == 1 &&
15742 (Opc == X86ISD::ADD ||
15743 Opc == X86ISD::SUB ||
15744 Opc == X86ISD::ADC ||
15745 Opc == X86ISD::SBB ||
15746 Opc == X86ISD::SMUL ||
15747 Opc == X86ISD::UMUL ||
15748 Opc == X86ISD::INC ||
15749 Opc == X86ISD::DEC ||
15750 Opc == X86ISD::OR ||
15751 Opc == X86ISD::XOR ||
15752 Opc == X86ISD::AND))
15755 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15761 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15762 if (V.getOpcode() != ISD::TRUNCATE)
15765 SDValue VOp0 = V.getOperand(0);
15766 unsigned InBits = VOp0.getValueSizeInBits();
15767 unsigned Bits = V.getValueSizeInBits();
15768 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15771 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15772 bool addTest = true;
15773 SDValue Cond = Op.getOperand(0);
15774 SDValue Op1 = Op.getOperand(1);
15775 SDValue Op2 = Op.getOperand(2);
15777 EVT VT = Op1.getValueType();
15780 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15781 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15782 // sequence later on.
15783 if (Cond.getOpcode() == ISD::SETCC &&
15784 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15785 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15786 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15787 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15788 int SSECC = translateX86FSETCC(
15789 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15792 if (Subtarget->hasAVX512()) {
15793 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15794 DAG.getConstant(SSECC, MVT::i8));
15795 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15797 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15798 DAG.getConstant(SSECC, MVT::i8));
15799 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15800 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15801 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15805 if (Cond.getOpcode() == ISD::SETCC) {
15806 SDValue NewCond = LowerSETCC(Cond, DAG);
15807 if (NewCond.getNode())
15811 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15812 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15813 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15814 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15815 if (Cond.getOpcode() == X86ISD::SETCC &&
15816 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15817 isZero(Cond.getOperand(1).getOperand(1))) {
15818 SDValue Cmp = Cond.getOperand(1);
15820 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15822 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15823 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15824 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15826 SDValue CmpOp0 = Cmp.getOperand(0);
15827 // Apply further optimizations for special cases
15828 // (select (x != 0), -1, 0) -> neg & sbb
15829 // (select (x == 0), 0, -1) -> neg & sbb
15830 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15831 if (YC->isNullValue() &&
15832 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15833 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15834 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15835 DAG.getConstant(0, CmpOp0.getValueType()),
15837 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15838 DAG.getConstant(X86::COND_B, MVT::i8),
15839 SDValue(Neg.getNode(), 1));
15843 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15844 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15845 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15847 SDValue Res = // Res = 0 or -1.
15848 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15849 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15851 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15852 Res = DAG.getNOT(DL, Res, Res.getValueType());
15854 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15855 if (!N2C || !N2C->isNullValue())
15856 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15861 // Look past (and (setcc_carry (cmp ...)), 1).
15862 if (Cond.getOpcode() == ISD::AND &&
15863 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15864 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15865 if (C && C->getAPIntValue() == 1)
15866 Cond = Cond.getOperand(0);
15869 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15870 // setting operand in place of the X86ISD::SETCC.
15871 unsigned CondOpcode = Cond.getOpcode();
15872 if (CondOpcode == X86ISD::SETCC ||
15873 CondOpcode == X86ISD::SETCC_CARRY) {
15874 CC = Cond.getOperand(0);
15876 SDValue Cmp = Cond.getOperand(1);
15877 unsigned Opc = Cmp.getOpcode();
15878 MVT VT = Op.getSimpleValueType();
15880 bool IllegalFPCMov = false;
15881 if (VT.isFloatingPoint() && !VT.isVector() &&
15882 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15883 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15885 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15886 Opc == X86ISD::BT) { // FIXME
15890 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15891 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15892 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15893 Cond.getOperand(0).getValueType() != MVT::i8)) {
15894 SDValue LHS = Cond.getOperand(0);
15895 SDValue RHS = Cond.getOperand(1);
15896 unsigned X86Opcode;
15899 switch (CondOpcode) {
15900 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15901 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15902 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15903 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15904 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15905 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15906 default: llvm_unreachable("unexpected overflowing operator");
15908 if (CondOpcode == ISD::UMULO)
15909 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15912 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15914 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15916 if (CondOpcode == ISD::UMULO)
15917 Cond = X86Op.getValue(2);
15919 Cond = X86Op.getValue(1);
15921 CC = DAG.getConstant(X86Cond, MVT::i8);
15926 // Look pass the truncate if the high bits are known zero.
15927 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15928 Cond = Cond.getOperand(0);
15930 // We know the result of AND is compared against zero. Try to match
15932 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15933 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15934 if (NewSetCC.getNode()) {
15935 CC = NewSetCC.getOperand(0);
15936 Cond = NewSetCC.getOperand(1);
15943 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15944 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15947 // a < b ? -1 : 0 -> RES = ~setcc_carry
15948 // a < b ? 0 : -1 -> RES = setcc_carry
15949 // a >= b ? -1 : 0 -> RES = setcc_carry
15950 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15951 if (Cond.getOpcode() == X86ISD::SUB) {
15952 Cond = ConvertCmpIfNecessary(Cond, DAG);
15953 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15955 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15956 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15957 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15958 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15959 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15960 return DAG.getNOT(DL, Res, Res.getValueType());
15965 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15966 // widen the cmov and push the truncate through. This avoids introducing a new
15967 // branch during isel and doesn't add any extensions.
15968 if (Op.getValueType() == MVT::i8 &&
15969 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15970 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15971 if (T1.getValueType() == T2.getValueType() &&
15972 // Blacklist CopyFromReg to avoid partial register stalls.
15973 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15974 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15975 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15976 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15980 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15981 // condition is true.
15982 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15983 SDValue Ops[] = { Op2, Op1, CC, Cond };
15984 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15987 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15988 SelectionDAG &DAG) {
15989 MVT VT = Op->getSimpleValueType(0);
15990 SDValue In = Op->getOperand(0);
15991 MVT InVT = In.getSimpleValueType();
15992 MVT VTElt = VT.getVectorElementType();
15993 MVT InVTElt = InVT.getVectorElementType();
15997 if ((InVTElt == MVT::i1) &&
15998 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15999 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
16001 ((Subtarget->hasBWI() && VT.is512BitVector() &&
16002 VTElt.getSizeInBits() <= 16)) ||
16004 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
16005 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
16007 ((Subtarget->hasDQI() && VT.is512BitVector() &&
16008 VTElt.getSizeInBits() >= 32))))
16009 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
16011 unsigned int NumElts = VT.getVectorNumElements();
16013 if (NumElts != 8 && NumElts != 16)
16016 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
16017 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
16018 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
16019 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
16022 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16023 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
16025 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
16026 Constant *C = ConstantInt::get(*DAG.getContext(),
16027 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
16029 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
16030 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
16031 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
16032 MachinePointerInfo::getConstantPool(),
16033 false, false, false, Alignment);
16034 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
16035 if (VT.is512BitVector())
16037 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
16040 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
16041 SelectionDAG &DAG) {
16042 MVT VT = Op->getSimpleValueType(0);
16043 SDValue In = Op->getOperand(0);
16044 MVT InVT = In.getSimpleValueType();
16047 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
16048 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
16050 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
16051 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
16052 (VT != MVT::v16i16 || InVT != MVT::v16i8))
16055 if (Subtarget->hasInt256())
16056 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
16058 // Optimize vectors in AVX mode
16059 // Sign extend v8i16 to v8i32 and
16062 // Divide input vector into two parts
16063 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
16064 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
16065 // concat the vectors to original VT
16067 unsigned NumElems = InVT.getVectorNumElements();
16068 SDValue Undef = DAG.getUNDEF(InVT);
16070 SmallVector<int,8> ShufMask1(NumElems, -1);
16071 for (unsigned i = 0; i != NumElems/2; ++i)
16074 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
16076 SmallVector<int,8> ShufMask2(NumElems, -1);
16077 for (unsigned i = 0; i != NumElems/2; ++i)
16078 ShufMask2[i] = i + NumElems/2;
16080 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
16082 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
16083 VT.getVectorNumElements()/2);
16085 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
16086 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
16088 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
16091 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
16092 // may emit an illegal shuffle but the expansion is still better than scalar
16093 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
16094 // we'll emit a shuffle and a arithmetic shift.
16095 // TODO: It is possible to support ZExt by zeroing the undef values during
16096 // the shuffle phase or after the shuffle.
16097 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
16098 SelectionDAG &DAG) {
16099 MVT RegVT = Op.getSimpleValueType();
16100 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
16101 assert(RegVT.isInteger() &&
16102 "We only custom lower integer vector sext loads.");
16104 // Nothing useful we can do without SSE2 shuffles.
16105 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
16107 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
16109 EVT MemVT = Ld->getMemoryVT();
16110 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16111 unsigned RegSz = RegVT.getSizeInBits();
16113 ISD::LoadExtType Ext = Ld->getExtensionType();
16115 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
16116 && "Only anyext and sext are currently implemented.");
16117 assert(MemVT != RegVT && "Cannot extend to the same type");
16118 assert(MemVT.isVector() && "Must load a vector from memory");
16120 unsigned NumElems = RegVT.getVectorNumElements();
16121 unsigned MemSz = MemVT.getSizeInBits();
16122 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16124 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
16125 // The only way in which we have a legal 256-bit vector result but not the
16126 // integer 256-bit operations needed to directly lower a sextload is if we
16127 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
16128 // a 128-bit vector and a normal sign_extend to 256-bits that should get
16129 // correctly legalized. We do this late to allow the canonical form of
16130 // sextload to persist throughout the rest of the DAG combiner -- it wants
16131 // to fold together any extensions it can, and so will fuse a sign_extend
16132 // of an sextload into a sextload targeting a wider value.
16134 if (MemSz == 128) {
16135 // Just switch this to a normal load.
16136 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
16137 "it must be a legal 128-bit vector "
16139 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
16140 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
16141 Ld->isInvariant(), Ld->getAlignment());
16143 assert(MemSz < 128 &&
16144 "Can't extend a type wider than 128 bits to a 256 bit vector!");
16145 // Do an sext load to a 128-bit vector type. We want to use the same
16146 // number of elements, but elements half as wide. This will end up being
16147 // recursively lowered by this routine, but will succeed as we definitely
16148 // have all the necessary features if we're using AVX1.
16150 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
16151 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
16153 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
16154 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
16155 Ld->isNonTemporal(), Ld->isInvariant(),
16156 Ld->getAlignment());
16159 // Replace chain users with the new chain.
16160 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
16161 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
16163 // Finally, do a normal sign-extend to the desired register.
16164 return DAG.getSExtOrTrunc(Load, dl, RegVT);
16167 // All sizes must be a power of two.
16168 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
16169 "Non-power-of-two elements are not custom lowered!");
16171 // Attempt to load the original value using scalar loads.
16172 // Find the largest scalar type that divides the total loaded size.
16173 MVT SclrLoadTy = MVT::i8;
16174 for (MVT Tp : MVT::integer_valuetypes()) {
16175 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16180 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16181 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16183 SclrLoadTy = MVT::f64;
16185 // Calculate the number of scalar loads that we need to perform
16186 // in order to load our vector from memory.
16187 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16189 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16190 "Can only lower sext loads with a single scalar load!");
16192 unsigned loadRegZize = RegSz;
16193 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16196 // Represent our vector as a sequence of elements which are the
16197 // largest scalar that we can load.
16198 EVT LoadUnitVecVT = EVT::getVectorVT(
16199 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16201 // Represent the data using the same element type that is stored in
16202 // memory. In practice, we ''widen'' MemVT.
16204 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16205 loadRegZize / MemVT.getScalarType().getSizeInBits());
16207 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16208 "Invalid vector type");
16210 // We can't shuffle using an illegal type.
16211 assert(TLI.isTypeLegal(WideVecVT) &&
16212 "We only lower types that form legal widened vector types");
16214 SmallVector<SDValue, 8> Chains;
16215 SDValue Ptr = Ld->getBasePtr();
16216 SDValue Increment =
16217 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16218 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16220 for (unsigned i = 0; i < NumLoads; ++i) {
16221 // Perform a single load.
16222 SDValue ScalarLoad =
16223 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16224 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16225 Ld->getAlignment());
16226 Chains.push_back(ScalarLoad.getValue(1));
16227 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16228 // another round of DAGCombining.
16230 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16232 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16233 ScalarLoad, DAG.getIntPtrConstant(i));
16235 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16238 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16240 // Bitcast the loaded value to a vector of the original element type, in
16241 // the size of the target vector type.
16242 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16243 unsigned SizeRatio = RegSz / MemSz;
16245 if (Ext == ISD::SEXTLOAD) {
16246 // If we have SSE4.1, we can directly emit a VSEXT node.
16247 if (Subtarget->hasSSE41()) {
16248 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16249 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16253 // Otherwise we'll shuffle the small elements in the high bits of the
16254 // larger type and perform an arithmetic shift. If the shift is not legal
16255 // it's better to scalarize.
16256 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16257 "We can't implement a sext load without an arithmetic right shift!");
16259 // Redistribute the loaded elements into the different locations.
16260 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16261 for (unsigned i = 0; i != NumElems; ++i)
16262 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16264 SDValue Shuff = DAG.getVectorShuffle(
16265 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16267 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16269 // Build the arithmetic shift.
16270 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16271 MemVT.getVectorElementType().getSizeInBits();
16273 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16275 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16279 // Redistribute the loaded elements into the different locations.
16280 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16281 for (unsigned i = 0; i != NumElems; ++i)
16282 ShuffleVec[i * SizeRatio] = i;
16284 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16285 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16287 // Bitcast to the requested type.
16288 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16289 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16293 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16294 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16295 // from the AND / OR.
16296 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16297 Opc = Op.getOpcode();
16298 if (Opc != ISD::OR && Opc != ISD::AND)
16300 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16301 Op.getOperand(0).hasOneUse() &&
16302 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16303 Op.getOperand(1).hasOneUse());
16306 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16307 // 1 and that the SETCC node has a single use.
16308 static bool isXor1OfSetCC(SDValue Op) {
16309 if (Op.getOpcode() != ISD::XOR)
16311 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16312 if (N1C && N1C->getAPIntValue() == 1) {
16313 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16314 Op.getOperand(0).hasOneUse();
16319 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16320 bool addTest = true;
16321 SDValue Chain = Op.getOperand(0);
16322 SDValue Cond = Op.getOperand(1);
16323 SDValue Dest = Op.getOperand(2);
16326 bool Inverted = false;
16328 if (Cond.getOpcode() == ISD::SETCC) {
16329 // Check for setcc([su]{add,sub,mul}o == 0).
16330 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16331 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16332 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16333 Cond.getOperand(0).getResNo() == 1 &&
16334 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16335 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16336 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16337 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16338 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16339 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16341 Cond = Cond.getOperand(0);
16343 SDValue NewCond = LowerSETCC(Cond, DAG);
16344 if (NewCond.getNode())
16349 // FIXME: LowerXALUO doesn't handle these!!
16350 else if (Cond.getOpcode() == X86ISD::ADD ||
16351 Cond.getOpcode() == X86ISD::SUB ||
16352 Cond.getOpcode() == X86ISD::SMUL ||
16353 Cond.getOpcode() == X86ISD::UMUL)
16354 Cond = LowerXALUO(Cond, DAG);
16357 // Look pass (and (setcc_carry (cmp ...)), 1).
16358 if (Cond.getOpcode() == ISD::AND &&
16359 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16360 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16361 if (C && C->getAPIntValue() == 1)
16362 Cond = Cond.getOperand(0);
16365 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16366 // setting operand in place of the X86ISD::SETCC.
16367 unsigned CondOpcode = Cond.getOpcode();
16368 if (CondOpcode == X86ISD::SETCC ||
16369 CondOpcode == X86ISD::SETCC_CARRY) {
16370 CC = Cond.getOperand(0);
16372 SDValue Cmp = Cond.getOperand(1);
16373 unsigned Opc = Cmp.getOpcode();
16374 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16375 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16379 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16383 // These can only come from an arithmetic instruction with overflow,
16384 // e.g. SADDO, UADDO.
16385 Cond = Cond.getNode()->getOperand(1);
16391 CondOpcode = Cond.getOpcode();
16392 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16393 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16394 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16395 Cond.getOperand(0).getValueType() != MVT::i8)) {
16396 SDValue LHS = Cond.getOperand(0);
16397 SDValue RHS = Cond.getOperand(1);
16398 unsigned X86Opcode;
16401 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16402 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16404 switch (CondOpcode) {
16405 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16409 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16412 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16413 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16415 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16417 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16420 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16421 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16422 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16423 default: llvm_unreachable("unexpected overflowing operator");
16426 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16427 if (CondOpcode == ISD::UMULO)
16428 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16431 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16433 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16435 if (CondOpcode == ISD::UMULO)
16436 Cond = X86Op.getValue(2);
16438 Cond = X86Op.getValue(1);
16440 CC = DAG.getConstant(X86Cond, MVT::i8);
16444 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16445 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16446 if (CondOpc == ISD::OR) {
16447 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16448 // two branches instead of an explicit OR instruction with a
16450 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16451 isX86LogicalCmp(Cmp)) {
16452 CC = Cond.getOperand(0).getOperand(0);
16453 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16454 Chain, Dest, CC, Cmp);
16455 CC = Cond.getOperand(1).getOperand(0);
16459 } else { // ISD::AND
16460 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16461 // two branches instead of an explicit AND instruction with a
16462 // separate test. However, we only do this if this block doesn't
16463 // have a fall-through edge, because this requires an explicit
16464 // jmp when the condition is false.
16465 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16466 isX86LogicalCmp(Cmp) &&
16467 Op.getNode()->hasOneUse()) {
16468 X86::CondCode CCode =
16469 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16470 CCode = X86::GetOppositeBranchCondition(CCode);
16471 CC = DAG.getConstant(CCode, MVT::i8);
16472 SDNode *User = *Op.getNode()->use_begin();
16473 // Look for an unconditional branch following this conditional branch.
16474 // We need this because we need to reverse the successors in order
16475 // to implement FCMP_OEQ.
16476 if (User->getOpcode() == ISD::BR) {
16477 SDValue FalseBB = User->getOperand(1);
16479 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16480 assert(NewBR == User);
16484 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16485 Chain, Dest, CC, Cmp);
16486 X86::CondCode CCode =
16487 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16488 CCode = X86::GetOppositeBranchCondition(CCode);
16489 CC = DAG.getConstant(CCode, MVT::i8);
16495 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16496 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16497 // It should be transformed during dag combiner except when the condition
16498 // is set by a arithmetics with overflow node.
16499 X86::CondCode CCode =
16500 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16501 CCode = X86::GetOppositeBranchCondition(CCode);
16502 CC = DAG.getConstant(CCode, MVT::i8);
16503 Cond = Cond.getOperand(0).getOperand(1);
16505 } else if (Cond.getOpcode() == ISD::SETCC &&
16506 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16507 // For FCMP_OEQ, we can emit
16508 // two branches instead of an explicit AND instruction with a
16509 // separate test. However, we only do this if this block doesn't
16510 // have a fall-through edge, because this requires an explicit
16511 // jmp when the condition is false.
16512 if (Op.getNode()->hasOneUse()) {
16513 SDNode *User = *Op.getNode()->use_begin();
16514 // Look for an unconditional branch following this conditional branch.
16515 // We need this because we need to reverse the successors in order
16516 // to implement FCMP_OEQ.
16517 if (User->getOpcode() == ISD::BR) {
16518 SDValue FalseBB = User->getOperand(1);
16520 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16521 assert(NewBR == User);
16525 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16526 Cond.getOperand(0), Cond.getOperand(1));
16527 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16528 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16529 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16530 Chain, Dest, CC, Cmp);
16531 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16536 } else if (Cond.getOpcode() == ISD::SETCC &&
16537 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16538 // For FCMP_UNE, we can emit
16539 // two branches instead of an explicit AND instruction with a
16540 // separate test. However, we only do this if this block doesn't
16541 // have a fall-through edge, because this requires an explicit
16542 // jmp when the condition is false.
16543 if (Op.getNode()->hasOneUse()) {
16544 SDNode *User = *Op.getNode()->use_begin();
16545 // Look for an unconditional branch following this conditional branch.
16546 // We need this because we need to reverse the successors in order
16547 // to implement FCMP_UNE.
16548 if (User->getOpcode() == ISD::BR) {
16549 SDValue FalseBB = User->getOperand(1);
16551 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16552 assert(NewBR == User);
16555 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16556 Cond.getOperand(0), Cond.getOperand(1));
16557 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16558 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16559 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16560 Chain, Dest, CC, Cmp);
16561 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16571 // Look pass the truncate if the high bits are known zero.
16572 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16573 Cond = Cond.getOperand(0);
16575 // We know the result of AND is compared against zero. Try to match
16577 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16578 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16579 if (NewSetCC.getNode()) {
16580 CC = NewSetCC.getOperand(0);
16581 Cond = NewSetCC.getOperand(1);
16588 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16589 CC = DAG.getConstant(X86Cond, MVT::i8);
16590 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16592 Cond = ConvertCmpIfNecessary(Cond, DAG);
16593 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16594 Chain, Dest, CC, Cond);
16597 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16598 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16599 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16600 // that the guard pages used by the OS virtual memory manager are allocated in
16601 // correct sequence.
16603 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16604 SelectionDAG &DAG) const {
16605 MachineFunction &MF = DAG.getMachineFunction();
16606 bool SplitStack = MF.shouldSplitStack();
16607 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16613 SDNode* Node = Op.getNode();
16615 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16616 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16617 " not tell us which reg is the stack pointer!");
16618 EVT VT = Node->getValueType(0);
16619 SDValue Tmp1 = SDValue(Node, 0);
16620 SDValue Tmp2 = SDValue(Node, 1);
16621 SDValue Tmp3 = Node->getOperand(2);
16622 SDValue Chain = Tmp1.getOperand(0);
16624 // Chain the dynamic stack allocation so that it doesn't modify the stack
16625 // pointer when other instructions are using the stack.
16626 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16629 SDValue Size = Tmp2.getOperand(1);
16630 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16631 Chain = SP.getValue(1);
16632 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16633 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16634 unsigned StackAlign = TFI.getStackAlignment();
16635 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16636 if (Align > StackAlign)
16637 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16638 DAG.getConstant(-(uint64_t)Align, VT));
16639 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16641 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16642 DAG.getIntPtrConstant(0, true), SDValue(),
16645 SDValue Ops[2] = { Tmp1, Tmp2 };
16646 return DAG.getMergeValues(Ops, dl);
16650 SDValue Chain = Op.getOperand(0);
16651 SDValue Size = Op.getOperand(1);
16652 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16653 EVT VT = Op.getNode()->getValueType(0);
16655 bool Is64Bit = Subtarget->is64Bit();
16656 EVT SPTy = getPointerTy();
16659 MachineRegisterInfo &MRI = MF.getRegInfo();
16662 // The 64 bit implementation of segmented stacks needs to clobber both r10
16663 // r11. This makes it impossible to use it along with nested parameters.
16664 const Function *F = MF.getFunction();
16666 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16668 if (I->hasNestAttr())
16669 report_fatal_error("Cannot use segmented stacks with functions that "
16670 "have nested arguments.");
16673 const TargetRegisterClass *AddrRegClass =
16674 getRegClassFor(getPointerTy());
16675 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16676 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16677 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16678 DAG.getRegister(Vreg, SPTy));
16679 SDValue Ops1[2] = { Value, Chain };
16680 return DAG.getMergeValues(Ops1, dl);
16683 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16685 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16686 Flag = Chain.getValue(1);
16687 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16689 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16691 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16692 DAG.getSubtarget().getRegisterInfo());
16693 unsigned SPReg = RegInfo->getStackRegister();
16694 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16695 Chain = SP.getValue(1);
16698 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16699 DAG.getConstant(-(uint64_t)Align, VT));
16700 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16703 SDValue Ops1[2] = { SP, Chain };
16704 return DAG.getMergeValues(Ops1, dl);
16708 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16709 MachineFunction &MF = DAG.getMachineFunction();
16710 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16712 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16715 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16716 // vastart just stores the address of the VarArgsFrameIndex slot into the
16717 // memory location argument.
16718 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16720 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16721 MachinePointerInfo(SV), false, false, 0);
16725 // gp_offset (0 - 6 * 8)
16726 // fp_offset (48 - 48 + 8 * 16)
16727 // overflow_arg_area (point to parameters coming in memory).
16729 SmallVector<SDValue, 8> MemOps;
16730 SDValue FIN = Op.getOperand(1);
16732 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16733 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16735 FIN, MachinePointerInfo(SV), false, false, 0);
16736 MemOps.push_back(Store);
16739 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16740 FIN, DAG.getIntPtrConstant(4));
16741 Store = DAG.getStore(Op.getOperand(0), DL,
16742 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16744 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16745 MemOps.push_back(Store);
16747 // Store ptr to overflow_arg_area
16748 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16749 FIN, DAG.getIntPtrConstant(4));
16750 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16752 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16753 MachinePointerInfo(SV, 8),
16755 MemOps.push_back(Store);
16757 // Store ptr to reg_save_area.
16758 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16759 FIN, DAG.getIntPtrConstant(8));
16760 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16762 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16763 MachinePointerInfo(SV, 16), false, false, 0);
16764 MemOps.push_back(Store);
16765 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16768 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16769 assert(Subtarget->is64Bit() &&
16770 "LowerVAARG only handles 64-bit va_arg!");
16771 assert((Subtarget->isTargetLinux() ||
16772 Subtarget->isTargetDarwin()) &&
16773 "Unhandled target in LowerVAARG");
16774 assert(Op.getNode()->getNumOperands() == 4);
16775 SDValue Chain = Op.getOperand(0);
16776 SDValue SrcPtr = Op.getOperand(1);
16777 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16778 unsigned Align = Op.getConstantOperandVal(3);
16781 EVT ArgVT = Op.getNode()->getValueType(0);
16782 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16783 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16786 // Decide which area this value should be read from.
16787 // TODO: Implement the AMD64 ABI in its entirety. This simple
16788 // selection mechanism works only for the basic types.
16789 if (ArgVT == MVT::f80) {
16790 llvm_unreachable("va_arg for f80 not yet implemented");
16791 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16792 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16793 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16794 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16796 llvm_unreachable("Unhandled argument type in LowerVAARG");
16799 if (ArgMode == 2) {
16800 // Sanity Check: Make sure using fp_offset makes sense.
16801 assert(!DAG.getTarget().Options.UseSoftFloat &&
16802 !(DAG.getMachineFunction()
16803 .getFunction()->getAttributes()
16804 .hasAttribute(AttributeSet::FunctionIndex,
16805 Attribute::NoImplicitFloat)) &&
16806 Subtarget->hasSSE1());
16809 // Insert VAARG_64 node into the DAG
16810 // VAARG_64 returns two values: Variable Argument Address, Chain
16811 SmallVector<SDValue, 11> InstOps;
16812 InstOps.push_back(Chain);
16813 InstOps.push_back(SrcPtr);
16814 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16815 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16816 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16817 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16818 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16819 VTs, InstOps, MVT::i64,
16820 MachinePointerInfo(SV),
16822 /*Volatile=*/false,
16824 /*WriteMem=*/true);
16825 Chain = VAARG.getValue(1);
16827 // Load the next argument and return it
16828 return DAG.getLoad(ArgVT, dl,
16831 MachinePointerInfo(),
16832 false, false, false, 0);
16835 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16836 SelectionDAG &DAG) {
16837 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16838 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16839 SDValue Chain = Op.getOperand(0);
16840 SDValue DstPtr = Op.getOperand(1);
16841 SDValue SrcPtr = Op.getOperand(2);
16842 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16843 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16846 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16847 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16849 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16852 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16853 // amount is a constant. Takes immediate version of shift as input.
16854 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16855 SDValue SrcOp, uint64_t ShiftAmt,
16856 SelectionDAG &DAG) {
16857 MVT ElementType = VT.getVectorElementType();
16859 // Fold this packed shift into its first operand if ShiftAmt is 0.
16863 // Check for ShiftAmt >= element width
16864 if (ShiftAmt >= ElementType.getSizeInBits()) {
16865 if (Opc == X86ISD::VSRAI)
16866 ShiftAmt = ElementType.getSizeInBits() - 1;
16868 return DAG.getConstant(0, VT);
16871 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16872 && "Unknown target vector shift-by-constant node");
16874 // Fold this packed vector shift into a build vector if SrcOp is a
16875 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16876 if (VT == SrcOp.getSimpleValueType() &&
16877 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16878 SmallVector<SDValue, 8> Elts;
16879 unsigned NumElts = SrcOp->getNumOperands();
16880 ConstantSDNode *ND;
16883 default: llvm_unreachable(nullptr);
16884 case X86ISD::VSHLI:
16885 for (unsigned i=0; i!=NumElts; ++i) {
16886 SDValue CurrentOp = SrcOp->getOperand(i);
16887 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16888 Elts.push_back(CurrentOp);
16891 ND = cast<ConstantSDNode>(CurrentOp);
16892 const APInt &C = ND->getAPIntValue();
16893 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16896 case X86ISD::VSRLI:
16897 for (unsigned i=0; i!=NumElts; ++i) {
16898 SDValue CurrentOp = SrcOp->getOperand(i);
16899 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16900 Elts.push_back(CurrentOp);
16903 ND = cast<ConstantSDNode>(CurrentOp);
16904 const APInt &C = ND->getAPIntValue();
16905 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16908 case X86ISD::VSRAI:
16909 for (unsigned i=0; i!=NumElts; ++i) {
16910 SDValue CurrentOp = SrcOp->getOperand(i);
16911 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16912 Elts.push_back(CurrentOp);
16915 ND = cast<ConstantSDNode>(CurrentOp);
16916 const APInt &C = ND->getAPIntValue();
16917 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16922 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16925 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16928 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16929 // may or may not be a constant. Takes immediate version of shift as input.
16930 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16931 SDValue SrcOp, SDValue ShAmt,
16932 SelectionDAG &DAG) {
16933 MVT SVT = ShAmt.getSimpleValueType();
16934 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16936 // Catch shift-by-constant.
16937 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16938 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16939 CShAmt->getZExtValue(), DAG);
16941 // Change opcode to non-immediate version
16943 default: llvm_unreachable("Unknown target vector shift node");
16944 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16945 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16946 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16949 const X86Subtarget &Subtarget =
16950 DAG.getTarget().getSubtarget<X86Subtarget>();
16951 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16952 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16953 // Let the shuffle legalizer expand this shift amount node.
16954 SDValue Op0 = ShAmt.getOperand(0);
16955 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16956 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16958 // Need to build a vector containing shift amount.
16959 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16960 SmallVector<SDValue, 4> ShOps;
16961 ShOps.push_back(ShAmt);
16962 if (SVT == MVT::i32) {
16963 ShOps.push_back(DAG.getConstant(0, SVT));
16964 ShOps.push_back(DAG.getUNDEF(SVT));
16966 ShOps.push_back(DAG.getUNDEF(SVT));
16968 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16969 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16972 // The return type has to be a 128-bit type with the same element
16973 // type as the input type.
16974 MVT EltVT = VT.getVectorElementType();
16975 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16977 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16978 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16981 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16982 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16983 /// necessary casting for \p Mask when lowering masking intrinsics.
16984 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16985 SDValue PreservedSrc,
16986 const X86Subtarget *Subtarget,
16987 SelectionDAG &DAG) {
16988 EVT VT = Op.getValueType();
16989 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16990 MVT::i1, VT.getVectorNumElements());
16991 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16992 Mask.getValueType().getSizeInBits());
16995 assert(MaskVT.isSimple() && "invalid mask type");
16997 if (isAllOnes(Mask))
17000 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17001 // are extracted by EXTRACT_SUBVECTOR.
17002 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17003 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17004 DAG.getIntPtrConstant(0));
17006 switch (Op.getOpcode()) {
17008 case X86ISD::PCMPEQM:
17009 case X86ISD::PCMPGTM:
17011 case X86ISD::CMPMU:
17012 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
17014 if (PreservedSrc.getOpcode() == ISD::UNDEF)
17015 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
17016 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
17019 /// \brief Creates an SDNode for a predicated scalar operation.
17020 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
17021 /// The mask is comming as MVT::i8 and it should be truncated
17022 /// to MVT::i1 while lowering masking intrinsics.
17023 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
17024 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
17025 /// a scalar instruction.
17026 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
17027 SDValue PreservedSrc,
17028 const X86Subtarget *Subtarget,
17029 SelectionDAG &DAG) {
17030 if (isAllOnes(Mask))
17033 EVT VT = Op.getValueType();
17035 // The mask should be of type MVT::i1
17036 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
17038 if (PreservedSrc.getOpcode() == ISD::UNDEF)
17039 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
17040 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
17043 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17044 SelectionDAG &DAG) {
17046 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17047 EVT VT = Op.getValueType();
17048 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
17050 switch(IntrData->Type) {
17051 case INTR_TYPE_1OP:
17052 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
17053 case INTR_TYPE_2OP:
17054 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
17056 case INTR_TYPE_3OP:
17057 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
17058 Op.getOperand(2), Op.getOperand(3));
17059 case INTR_TYPE_1OP_MASK_RM: {
17060 SDValue Src = Op.getOperand(1);
17061 SDValue Src0 = Op.getOperand(2);
17062 SDValue Mask = Op.getOperand(3);
17063 SDValue RoundingMode = Op.getOperand(4);
17064 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
17066 Mask, Src0, Subtarget, DAG);
17068 case INTR_TYPE_SCALAR_MASK_RM: {
17069 SDValue Src1 = Op.getOperand(1);
17070 SDValue Src2 = Op.getOperand(2);
17071 SDValue Src0 = Op.getOperand(3);
17072 SDValue Mask = Op.getOperand(4);
17073 SDValue RoundingMode = Op.getOperand(5);
17074 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
17076 Mask, Src0, Subtarget, DAG);
17078 case INTR_TYPE_2OP_MASK: {
17079 SDValue Mask = Op.getOperand(4);
17080 SDValue PassThru = Op.getOperand(3);
17081 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
17082 if (IntrWithRoundingModeOpcode != 0) {
17083 unsigned Round = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
17084 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
17085 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
17086 dl, Op.getValueType(),
17087 Op.getOperand(1), Op.getOperand(2),
17088 Op.getOperand(3), Op.getOperand(5)),
17089 Mask, PassThru, Subtarget, DAG);
17092 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
17095 Mask, PassThru, Subtarget, DAG);
17097 case FMA_OP_MASK: {
17098 SDValue Src1 = Op.getOperand(1);
17099 SDValue Src2 = Op.getOperand(2);
17100 SDValue Src3 = Op.getOperand(3);
17101 SDValue Mask = Op.getOperand(4);
17102 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
17103 if (IntrWithRoundingModeOpcode != 0) {
17104 SDValue Rnd = Op.getOperand(5);
17105 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
17106 X86::STATIC_ROUNDING::CUR_DIRECTION)
17107 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
17108 dl, Op.getValueType(),
17109 Src1, Src2, Src3, Rnd),
17110 Mask, Src1, Subtarget, DAG);
17112 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17113 dl, Op.getValueType(),
17115 Mask, Src1, Subtarget, DAG);
17118 case CMP_MASK_CC: {
17119 // Comparison intrinsics with masks.
17120 // Example of transformation:
17121 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
17122 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
17124 // (v8i1 (insert_subvector undef,
17125 // (v2i1 (and (PCMPEQM %a, %b),
17126 // (extract_subvector
17127 // (v8i1 (bitcast %mask)), 0))), 0))))
17128 EVT VT = Op.getOperand(1).getValueType();
17129 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17130 VT.getVectorNumElements());
17131 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
17132 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17133 Mask.getValueType().getSizeInBits());
17135 if (IntrData->Type == CMP_MASK_CC) {
17136 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
17137 Op.getOperand(2), Op.getOperand(3));
17139 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
17140 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
17143 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
17144 DAG.getTargetConstant(0, MaskVT),
17146 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
17147 DAG.getUNDEF(BitcastVT), CmpMask,
17148 DAG.getIntPtrConstant(0));
17149 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
17151 case COMI: { // Comparison intrinsics
17152 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
17153 SDValue LHS = Op.getOperand(1);
17154 SDValue RHS = Op.getOperand(2);
17155 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
17156 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
17157 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
17158 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17159 DAG.getConstant(X86CC, MVT::i8), Cond);
17160 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17163 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
17164 Op.getOperand(1), Op.getOperand(2), DAG);
17166 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17167 Op.getSimpleValueType(),
17169 Op.getOperand(2), DAG),
17170 Op.getOperand(4), Op.getOperand(3), Subtarget,
17172 case COMPRESS_EXPAND_IN_REG: {
17173 SDValue Mask = Op.getOperand(3);
17174 SDValue DataToCompress = Op.getOperand(1);
17175 SDValue PassThru = Op.getOperand(2);
17176 if (isAllOnes(Mask)) // return data as is
17177 return Op.getOperand(1);
17178 EVT VT = Op.getValueType();
17179 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17180 VT.getVectorNumElements());
17181 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17182 Mask.getValueType().getSizeInBits());
17184 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17185 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17186 DAG.getIntPtrConstant(0));
17188 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17192 SDValue Mask = Op.getOperand(3);
17193 EVT VT = Op.getValueType();
17194 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17195 VT.getVectorNumElements());
17196 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17197 Mask.getValueType().getSizeInBits());
17199 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17200 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17201 DAG.getIntPtrConstant(0));
17202 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17211 default: return SDValue(); // Don't custom lower most intrinsics.
17213 case Intrinsic::x86_avx512_mask_valign_q_512:
17214 case Intrinsic::x86_avx512_mask_valign_d_512:
17215 // Vector source operands are swapped.
17216 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17217 Op.getValueType(), Op.getOperand(2),
17220 Op.getOperand(5), Op.getOperand(4),
17223 // ptest and testp intrinsics. The intrinsic these come from are designed to
17224 // return an integer value, not just an instruction so lower it to the ptest
17225 // or testp pattern and a setcc for the result.
17226 case Intrinsic::x86_sse41_ptestz:
17227 case Intrinsic::x86_sse41_ptestc:
17228 case Intrinsic::x86_sse41_ptestnzc:
17229 case Intrinsic::x86_avx_ptestz_256:
17230 case Intrinsic::x86_avx_ptestc_256:
17231 case Intrinsic::x86_avx_ptestnzc_256:
17232 case Intrinsic::x86_avx_vtestz_ps:
17233 case Intrinsic::x86_avx_vtestc_ps:
17234 case Intrinsic::x86_avx_vtestnzc_ps:
17235 case Intrinsic::x86_avx_vtestz_pd:
17236 case Intrinsic::x86_avx_vtestc_pd:
17237 case Intrinsic::x86_avx_vtestnzc_pd:
17238 case Intrinsic::x86_avx_vtestz_ps_256:
17239 case Intrinsic::x86_avx_vtestc_ps_256:
17240 case Intrinsic::x86_avx_vtestnzc_ps_256:
17241 case Intrinsic::x86_avx_vtestz_pd_256:
17242 case Intrinsic::x86_avx_vtestc_pd_256:
17243 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17244 bool IsTestPacked = false;
17247 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17248 case Intrinsic::x86_avx_vtestz_ps:
17249 case Intrinsic::x86_avx_vtestz_pd:
17250 case Intrinsic::x86_avx_vtestz_ps_256:
17251 case Intrinsic::x86_avx_vtestz_pd_256:
17252 IsTestPacked = true; // Fallthrough
17253 case Intrinsic::x86_sse41_ptestz:
17254 case Intrinsic::x86_avx_ptestz_256:
17256 X86CC = X86::COND_E;
17258 case Intrinsic::x86_avx_vtestc_ps:
17259 case Intrinsic::x86_avx_vtestc_pd:
17260 case Intrinsic::x86_avx_vtestc_ps_256:
17261 case Intrinsic::x86_avx_vtestc_pd_256:
17262 IsTestPacked = true; // Fallthrough
17263 case Intrinsic::x86_sse41_ptestc:
17264 case Intrinsic::x86_avx_ptestc_256:
17266 X86CC = X86::COND_B;
17268 case Intrinsic::x86_avx_vtestnzc_ps:
17269 case Intrinsic::x86_avx_vtestnzc_pd:
17270 case Intrinsic::x86_avx_vtestnzc_ps_256:
17271 case Intrinsic::x86_avx_vtestnzc_pd_256:
17272 IsTestPacked = true; // Fallthrough
17273 case Intrinsic::x86_sse41_ptestnzc:
17274 case Intrinsic::x86_avx_ptestnzc_256:
17276 X86CC = X86::COND_A;
17280 SDValue LHS = Op.getOperand(1);
17281 SDValue RHS = Op.getOperand(2);
17282 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17283 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17284 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17285 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17286 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17288 case Intrinsic::x86_avx512_kortestz_w:
17289 case Intrinsic::x86_avx512_kortestc_w: {
17290 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17291 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17292 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17293 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17294 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17295 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17296 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17299 case Intrinsic::x86_sse42_pcmpistria128:
17300 case Intrinsic::x86_sse42_pcmpestria128:
17301 case Intrinsic::x86_sse42_pcmpistric128:
17302 case Intrinsic::x86_sse42_pcmpestric128:
17303 case Intrinsic::x86_sse42_pcmpistrio128:
17304 case Intrinsic::x86_sse42_pcmpestrio128:
17305 case Intrinsic::x86_sse42_pcmpistris128:
17306 case Intrinsic::x86_sse42_pcmpestris128:
17307 case Intrinsic::x86_sse42_pcmpistriz128:
17308 case Intrinsic::x86_sse42_pcmpestriz128: {
17312 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17313 case Intrinsic::x86_sse42_pcmpistria128:
17314 Opcode = X86ISD::PCMPISTRI;
17315 X86CC = X86::COND_A;
17317 case Intrinsic::x86_sse42_pcmpestria128:
17318 Opcode = X86ISD::PCMPESTRI;
17319 X86CC = X86::COND_A;
17321 case Intrinsic::x86_sse42_pcmpistric128:
17322 Opcode = X86ISD::PCMPISTRI;
17323 X86CC = X86::COND_B;
17325 case Intrinsic::x86_sse42_pcmpestric128:
17326 Opcode = X86ISD::PCMPESTRI;
17327 X86CC = X86::COND_B;
17329 case Intrinsic::x86_sse42_pcmpistrio128:
17330 Opcode = X86ISD::PCMPISTRI;
17331 X86CC = X86::COND_O;
17333 case Intrinsic::x86_sse42_pcmpestrio128:
17334 Opcode = X86ISD::PCMPESTRI;
17335 X86CC = X86::COND_O;
17337 case Intrinsic::x86_sse42_pcmpistris128:
17338 Opcode = X86ISD::PCMPISTRI;
17339 X86CC = X86::COND_S;
17341 case Intrinsic::x86_sse42_pcmpestris128:
17342 Opcode = X86ISD::PCMPESTRI;
17343 X86CC = X86::COND_S;
17345 case Intrinsic::x86_sse42_pcmpistriz128:
17346 Opcode = X86ISD::PCMPISTRI;
17347 X86CC = X86::COND_E;
17349 case Intrinsic::x86_sse42_pcmpestriz128:
17350 Opcode = X86ISD::PCMPESTRI;
17351 X86CC = X86::COND_E;
17354 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17355 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17356 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17357 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17358 DAG.getConstant(X86CC, MVT::i8),
17359 SDValue(PCMP.getNode(), 1));
17360 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17363 case Intrinsic::x86_sse42_pcmpistri128:
17364 case Intrinsic::x86_sse42_pcmpestri128: {
17366 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17367 Opcode = X86ISD::PCMPISTRI;
17369 Opcode = X86ISD::PCMPESTRI;
17371 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17372 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17373 return DAG.getNode(Opcode, dl, VTs, NewOps);
17378 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17379 SDValue Src, SDValue Mask, SDValue Base,
17380 SDValue Index, SDValue ScaleOp, SDValue Chain,
17381 const X86Subtarget * Subtarget) {
17383 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17384 assert(C && "Invalid scale type");
17385 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17386 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17387 Index.getSimpleValueType().getVectorNumElements());
17389 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17391 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17393 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17394 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17395 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17396 SDValue Segment = DAG.getRegister(0, MVT::i32);
17397 if (Src.getOpcode() == ISD::UNDEF)
17398 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17399 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17400 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17401 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17402 return DAG.getMergeValues(RetOps, dl);
17405 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17406 SDValue Src, SDValue Mask, SDValue Base,
17407 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17409 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17410 assert(C && "Invalid scale type");
17411 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17412 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17413 SDValue Segment = DAG.getRegister(0, MVT::i32);
17414 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17415 Index.getSimpleValueType().getVectorNumElements());
17417 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17419 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17421 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17422 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17423 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17424 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17425 return SDValue(Res, 1);
17428 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17429 SDValue Mask, SDValue Base, SDValue Index,
17430 SDValue ScaleOp, SDValue Chain) {
17432 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17433 assert(C && "Invalid scale type");
17434 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17435 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17436 SDValue Segment = DAG.getRegister(0, MVT::i32);
17438 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17440 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17442 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17444 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17445 //SDVTList VTs = DAG.getVTList(MVT::Other);
17446 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17447 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17448 return SDValue(Res, 0);
17451 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17452 // read performance monitor counters (x86_rdpmc).
17453 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17454 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17455 SmallVectorImpl<SDValue> &Results) {
17456 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17457 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17460 // The ECX register is used to select the index of the performance counter
17462 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17464 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17466 // Reads the content of a 64-bit performance counter and returns it in the
17467 // registers EDX:EAX.
17468 if (Subtarget->is64Bit()) {
17469 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17470 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17473 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17474 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17477 Chain = HI.getValue(1);
17479 if (Subtarget->is64Bit()) {
17480 // The EAX register is loaded with the low-order 32 bits. The EDX register
17481 // is loaded with the supported high-order bits of the counter.
17482 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17483 DAG.getConstant(32, MVT::i8));
17484 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17485 Results.push_back(Chain);
17489 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17490 SDValue Ops[] = { LO, HI };
17491 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17492 Results.push_back(Pair);
17493 Results.push_back(Chain);
17496 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17497 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17498 // also used to custom lower READCYCLECOUNTER nodes.
17499 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17500 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17501 SmallVectorImpl<SDValue> &Results) {
17502 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17503 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17506 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17507 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17508 // and the EAX register is loaded with the low-order 32 bits.
17509 if (Subtarget->is64Bit()) {
17510 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17511 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17514 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17515 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17518 SDValue Chain = HI.getValue(1);
17520 if (Opcode == X86ISD::RDTSCP_DAG) {
17521 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17523 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17524 // the ECX register. Add 'ecx' explicitly to the chain.
17525 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17527 // Explicitly store the content of ECX at the location passed in input
17528 // to the 'rdtscp' intrinsic.
17529 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17530 MachinePointerInfo(), false, false, 0);
17533 if (Subtarget->is64Bit()) {
17534 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17535 // the EAX register is loaded with the low-order 32 bits.
17536 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17537 DAG.getConstant(32, MVT::i8));
17538 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17539 Results.push_back(Chain);
17543 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17544 SDValue Ops[] = { LO, HI };
17545 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17546 Results.push_back(Pair);
17547 Results.push_back(Chain);
17550 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17551 SelectionDAG &DAG) {
17552 SmallVector<SDValue, 2> Results;
17554 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17556 return DAG.getMergeValues(Results, DL);
17560 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17561 SelectionDAG &DAG) {
17562 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17564 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17569 switch(IntrData->Type) {
17571 llvm_unreachable("Unknown Intrinsic Type");
17575 // Emit the node with the right value type.
17576 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17577 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17579 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17580 // Otherwise return the value from Rand, which is always 0, casted to i32.
17581 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17582 DAG.getConstant(1, Op->getValueType(1)),
17583 DAG.getConstant(X86::COND_B, MVT::i32),
17584 SDValue(Result.getNode(), 1) };
17585 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17586 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17589 // Return { result, isValid, chain }.
17590 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17591 SDValue(Result.getNode(), 2));
17594 //gather(v1, mask, index, base, scale);
17595 SDValue Chain = Op.getOperand(0);
17596 SDValue Src = Op.getOperand(2);
17597 SDValue Base = Op.getOperand(3);
17598 SDValue Index = Op.getOperand(4);
17599 SDValue Mask = Op.getOperand(5);
17600 SDValue Scale = Op.getOperand(6);
17601 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17605 //scatter(base, mask, index, v1, scale);
17606 SDValue Chain = Op.getOperand(0);
17607 SDValue Base = Op.getOperand(2);
17608 SDValue Mask = Op.getOperand(3);
17609 SDValue Index = Op.getOperand(4);
17610 SDValue Src = Op.getOperand(5);
17611 SDValue Scale = Op.getOperand(6);
17612 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17615 SDValue Hint = Op.getOperand(6);
17617 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17618 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17619 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17620 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17621 SDValue Chain = Op.getOperand(0);
17622 SDValue Mask = Op.getOperand(2);
17623 SDValue Index = Op.getOperand(3);
17624 SDValue Base = Op.getOperand(4);
17625 SDValue Scale = Op.getOperand(5);
17626 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17628 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17630 SmallVector<SDValue, 2> Results;
17631 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17632 return DAG.getMergeValues(Results, dl);
17634 // Read Performance Monitoring Counters.
17636 SmallVector<SDValue, 2> Results;
17637 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17638 return DAG.getMergeValues(Results, dl);
17640 // XTEST intrinsics.
17642 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17643 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17644 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17645 DAG.getConstant(X86::COND_NE, MVT::i8),
17647 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17648 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17649 Ret, SDValue(InTrans.getNode(), 1));
17653 SmallVector<SDValue, 2> Results;
17654 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17655 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17656 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17657 DAG.getConstant(-1, MVT::i8));
17658 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17659 Op.getOperand(4), GenCF.getValue(1));
17660 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17661 Op.getOperand(5), MachinePointerInfo(),
17663 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17664 DAG.getConstant(X86::COND_B, MVT::i8),
17666 Results.push_back(SetCC);
17667 Results.push_back(Store);
17668 return DAG.getMergeValues(Results, dl);
17670 case COMPRESS_TO_MEM: {
17672 SDValue Mask = Op.getOperand(4);
17673 SDValue DataToCompress = Op.getOperand(3);
17674 SDValue Addr = Op.getOperand(2);
17675 SDValue Chain = Op.getOperand(0);
17677 if (isAllOnes(Mask)) // return just a store
17678 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17679 MachinePointerInfo(), false, false, 0);
17681 EVT VT = DataToCompress.getValueType();
17682 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17683 VT.getVectorNumElements());
17684 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17685 Mask.getValueType().getSizeInBits());
17686 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17687 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17688 DAG.getIntPtrConstant(0));
17690 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17691 DataToCompress, DAG.getUNDEF(VT));
17692 return DAG.getStore(Chain, dl, Compressed, Addr,
17693 MachinePointerInfo(), false, false, 0);
17695 case EXPAND_FROM_MEM: {
17697 SDValue Mask = Op.getOperand(4);
17698 SDValue PathThru = Op.getOperand(3);
17699 SDValue Addr = Op.getOperand(2);
17700 SDValue Chain = Op.getOperand(0);
17701 EVT VT = Op.getValueType();
17703 if (isAllOnes(Mask)) // return just a load
17704 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17706 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17707 VT.getVectorNumElements());
17708 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17709 Mask.getValueType().getSizeInBits());
17710 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17711 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17712 DAG.getIntPtrConstant(0));
17714 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17715 false, false, false, 0);
17717 SmallVector<SDValue, 2> Results;
17718 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17720 Results.push_back(Chain);
17721 return DAG.getMergeValues(Results, dl);
17726 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17727 SelectionDAG &DAG) const {
17728 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17729 MFI->setReturnAddressIsTaken(true);
17731 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17734 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17736 EVT PtrVT = getPointerTy();
17739 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17740 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17741 DAG.getSubtarget().getRegisterInfo());
17742 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17743 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17744 DAG.getNode(ISD::ADD, dl, PtrVT,
17745 FrameAddr, Offset),
17746 MachinePointerInfo(), false, false, false, 0);
17749 // Just load the return address.
17750 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17751 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17752 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17755 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17756 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17757 MFI->setFrameAddressIsTaken(true);
17759 EVT VT = Op.getValueType();
17760 SDLoc dl(Op); // FIXME probably not meaningful
17761 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17762 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17763 DAG.getSubtarget().getRegisterInfo());
17764 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17765 DAG.getMachineFunction());
17766 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17767 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17768 "Invalid Frame Register!");
17769 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17771 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17772 MachinePointerInfo(),
17773 false, false, false, 0);
17777 // FIXME? Maybe this could be a TableGen attribute on some registers and
17778 // this table could be generated automatically from RegInfo.
17779 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17781 unsigned Reg = StringSwitch<unsigned>(RegName)
17782 .Case("esp", X86::ESP)
17783 .Case("rsp", X86::RSP)
17787 report_fatal_error("Invalid register name global variable");
17790 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17791 SelectionDAG &DAG) const {
17792 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17793 DAG.getSubtarget().getRegisterInfo());
17794 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17797 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17798 SDValue Chain = Op.getOperand(0);
17799 SDValue Offset = Op.getOperand(1);
17800 SDValue Handler = Op.getOperand(2);
17803 EVT PtrVT = getPointerTy();
17804 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17805 DAG.getSubtarget().getRegisterInfo());
17806 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17807 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17808 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17809 "Invalid Frame Register!");
17810 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17811 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17813 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17814 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17815 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17816 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17818 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17820 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17821 DAG.getRegister(StoreAddrReg, PtrVT));
17824 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17825 SelectionDAG &DAG) const {
17827 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17828 DAG.getVTList(MVT::i32, MVT::Other),
17829 Op.getOperand(0), Op.getOperand(1));
17832 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17833 SelectionDAG &DAG) const {
17835 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17836 Op.getOperand(0), Op.getOperand(1));
17839 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17840 return Op.getOperand(0);
17843 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17844 SelectionDAG &DAG) const {
17845 SDValue Root = Op.getOperand(0);
17846 SDValue Trmp = Op.getOperand(1); // trampoline
17847 SDValue FPtr = Op.getOperand(2); // nested function
17848 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17851 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17852 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17854 if (Subtarget->is64Bit()) {
17855 SDValue OutChains[6];
17857 // Large code-model.
17858 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17859 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17861 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17862 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17864 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17866 // Load the pointer to the nested function into R11.
17867 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17868 SDValue Addr = Trmp;
17869 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17870 Addr, MachinePointerInfo(TrmpAddr),
17873 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17874 DAG.getConstant(2, MVT::i64));
17875 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17876 MachinePointerInfo(TrmpAddr, 2),
17879 // Load the 'nest' parameter value into R10.
17880 // R10 is specified in X86CallingConv.td
17881 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17882 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17883 DAG.getConstant(10, MVT::i64));
17884 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17885 Addr, MachinePointerInfo(TrmpAddr, 10),
17888 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17889 DAG.getConstant(12, MVT::i64));
17890 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17891 MachinePointerInfo(TrmpAddr, 12),
17894 // Jump to the nested function.
17895 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17896 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17897 DAG.getConstant(20, MVT::i64));
17898 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17899 Addr, MachinePointerInfo(TrmpAddr, 20),
17902 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17903 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17904 DAG.getConstant(22, MVT::i64));
17905 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17906 MachinePointerInfo(TrmpAddr, 22),
17909 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17911 const Function *Func =
17912 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17913 CallingConv::ID CC = Func->getCallingConv();
17918 llvm_unreachable("Unsupported calling convention");
17919 case CallingConv::C:
17920 case CallingConv::X86_StdCall: {
17921 // Pass 'nest' parameter in ECX.
17922 // Must be kept in sync with X86CallingConv.td
17923 NestReg = X86::ECX;
17925 // Check that ECX wasn't needed by an 'inreg' parameter.
17926 FunctionType *FTy = Func->getFunctionType();
17927 const AttributeSet &Attrs = Func->getAttributes();
17929 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17930 unsigned InRegCount = 0;
17933 for (FunctionType::param_iterator I = FTy->param_begin(),
17934 E = FTy->param_end(); I != E; ++I, ++Idx)
17935 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17936 // FIXME: should only count parameters that are lowered to integers.
17937 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17939 if (InRegCount > 2) {
17940 report_fatal_error("Nest register in use - reduce number of inreg"
17946 case CallingConv::X86_FastCall:
17947 case CallingConv::X86_ThisCall:
17948 case CallingConv::Fast:
17949 // Pass 'nest' parameter in EAX.
17950 // Must be kept in sync with X86CallingConv.td
17951 NestReg = X86::EAX;
17955 SDValue OutChains[4];
17956 SDValue Addr, Disp;
17958 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17959 DAG.getConstant(10, MVT::i32));
17960 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17962 // This is storing the opcode for MOV32ri.
17963 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17964 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17965 OutChains[0] = DAG.getStore(Root, dl,
17966 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17967 Trmp, MachinePointerInfo(TrmpAddr),
17970 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17971 DAG.getConstant(1, MVT::i32));
17972 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17973 MachinePointerInfo(TrmpAddr, 1),
17976 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17977 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17978 DAG.getConstant(5, MVT::i32));
17979 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17980 MachinePointerInfo(TrmpAddr, 5),
17983 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17984 DAG.getConstant(6, MVT::i32));
17985 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17986 MachinePointerInfo(TrmpAddr, 6),
17989 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17993 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17994 SelectionDAG &DAG) const {
17996 The rounding mode is in bits 11:10 of FPSR, and has the following
17998 00 Round to nearest
18003 FLT_ROUNDS, on the other hand, expects the following:
18010 To perform the conversion, we do:
18011 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
18014 MachineFunction &MF = DAG.getMachineFunction();
18015 const TargetMachine &TM = MF.getTarget();
18016 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
18017 unsigned StackAlignment = TFI.getStackAlignment();
18018 MVT VT = Op.getSimpleValueType();
18021 // Save FP Control Word to stack slot
18022 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
18023 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
18025 MachineMemOperand *MMO =
18026 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
18027 MachineMemOperand::MOStore, 2, 2);
18029 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
18030 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
18031 DAG.getVTList(MVT::Other),
18032 Ops, MVT::i16, MMO);
18034 // Load FP Control Word from stack slot
18035 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
18036 MachinePointerInfo(), false, false, false, 0);
18038 // Transform as necessary
18040 DAG.getNode(ISD::SRL, DL, MVT::i16,
18041 DAG.getNode(ISD::AND, DL, MVT::i16,
18042 CWD, DAG.getConstant(0x800, MVT::i16)),
18043 DAG.getConstant(11, MVT::i8));
18045 DAG.getNode(ISD::SRL, DL, MVT::i16,
18046 DAG.getNode(ISD::AND, DL, MVT::i16,
18047 CWD, DAG.getConstant(0x400, MVT::i16)),
18048 DAG.getConstant(9, MVT::i8));
18051 DAG.getNode(ISD::AND, DL, MVT::i16,
18052 DAG.getNode(ISD::ADD, DL, MVT::i16,
18053 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
18054 DAG.getConstant(1, MVT::i16)),
18055 DAG.getConstant(3, MVT::i16));
18057 return DAG.getNode((VT.getSizeInBits() < 16 ?
18058 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
18061 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
18062 MVT VT = Op.getSimpleValueType();
18064 unsigned NumBits = VT.getSizeInBits();
18067 Op = Op.getOperand(0);
18068 if (VT == MVT::i8) {
18069 // Zero extend to i32 since there is not an i8 bsr.
18071 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18074 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
18075 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18076 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18078 // If src is zero (i.e. bsr sets ZF), returns NumBits.
18081 DAG.getConstant(NumBits+NumBits-1, OpVT),
18082 DAG.getConstant(X86::COND_E, MVT::i8),
18085 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18087 // Finally xor with NumBits-1.
18088 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18091 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18095 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
18096 MVT VT = Op.getSimpleValueType();
18098 unsigned NumBits = VT.getSizeInBits();
18101 Op = Op.getOperand(0);
18102 if (VT == MVT::i8) {
18103 // Zero extend to i32 since there is not an i8 bsr.
18105 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18108 // Issue a bsr (scan bits in reverse).
18109 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18110 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18112 // And xor with NumBits-1.
18113 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18116 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18120 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18121 MVT VT = Op.getSimpleValueType();
18122 unsigned NumBits = VT.getSizeInBits();
18124 Op = Op.getOperand(0);
18126 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18127 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18128 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18130 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18133 DAG.getConstant(NumBits, VT),
18134 DAG.getConstant(X86::COND_E, MVT::i8),
18137 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18140 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18141 // ones, and then concatenate the result back.
18142 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18143 MVT VT = Op.getSimpleValueType();
18145 assert(VT.is256BitVector() && VT.isInteger() &&
18146 "Unsupported value type for operation");
18148 unsigned NumElems = VT.getVectorNumElements();
18151 // Extract the LHS vectors
18152 SDValue LHS = Op.getOperand(0);
18153 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18154 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18156 // Extract the RHS vectors
18157 SDValue RHS = Op.getOperand(1);
18158 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18159 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18161 MVT EltVT = VT.getVectorElementType();
18162 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18164 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18165 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18166 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18169 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18170 assert(Op.getSimpleValueType().is256BitVector() &&
18171 Op.getSimpleValueType().isInteger() &&
18172 "Only handle AVX 256-bit vector integer operation");
18173 return Lower256IntArith(Op, DAG);
18176 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18177 assert(Op.getSimpleValueType().is256BitVector() &&
18178 Op.getSimpleValueType().isInteger() &&
18179 "Only handle AVX 256-bit vector integer operation");
18180 return Lower256IntArith(Op, DAG);
18183 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18184 SelectionDAG &DAG) {
18186 MVT VT = Op.getSimpleValueType();
18188 // Decompose 256-bit ops into smaller 128-bit ops.
18189 if (VT.is256BitVector() && !Subtarget->hasInt256())
18190 return Lower256IntArith(Op, DAG);
18192 SDValue A = Op.getOperand(0);
18193 SDValue B = Op.getOperand(1);
18195 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18196 if (VT == MVT::v4i32) {
18197 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18198 "Should not custom lower when pmuldq is available!");
18200 // Extract the odd parts.
18201 static const int UnpackMask[] = { 1, -1, 3, -1 };
18202 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18203 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18205 // Multiply the even parts.
18206 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18207 // Now multiply odd parts.
18208 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18210 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18211 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18213 // Merge the two vectors back together with a shuffle. This expands into 2
18215 static const int ShufMask[] = { 0, 4, 2, 6 };
18216 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18219 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18220 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18222 // Ahi = psrlqi(a, 32);
18223 // Bhi = psrlqi(b, 32);
18225 // AloBlo = pmuludq(a, b);
18226 // AloBhi = pmuludq(a, Bhi);
18227 // AhiBlo = pmuludq(Ahi, b);
18229 // AloBhi = psllqi(AloBhi, 32);
18230 // AhiBlo = psllqi(AhiBlo, 32);
18231 // return AloBlo + AloBhi + AhiBlo;
18233 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18234 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18236 // Bit cast to 32-bit vectors for MULUDQ
18237 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18238 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18239 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18240 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18241 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18242 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18244 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18245 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18246 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18248 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18249 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18251 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18252 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18255 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18256 assert(Subtarget->isTargetWin64() && "Unexpected target");
18257 EVT VT = Op.getValueType();
18258 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18259 "Unexpected return type for lowering");
18263 switch (Op->getOpcode()) {
18264 default: llvm_unreachable("Unexpected request for libcall!");
18265 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18266 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18267 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18268 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18269 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18270 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18274 SDValue InChain = DAG.getEntryNode();
18276 TargetLowering::ArgListTy Args;
18277 TargetLowering::ArgListEntry Entry;
18278 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18279 EVT ArgVT = Op->getOperand(i).getValueType();
18280 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18281 "Unexpected argument type for lowering");
18282 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18283 Entry.Node = StackPtr;
18284 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18286 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18287 Entry.Ty = PointerType::get(ArgTy,0);
18288 Entry.isSExt = false;
18289 Entry.isZExt = false;
18290 Args.push_back(Entry);
18293 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18296 TargetLowering::CallLoweringInfo CLI(DAG);
18297 CLI.setDebugLoc(dl).setChain(InChain)
18298 .setCallee(getLibcallCallingConv(LC),
18299 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18300 Callee, std::move(Args), 0)
18301 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18303 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18304 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18307 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18308 SelectionDAG &DAG) {
18309 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18310 EVT VT = Op0.getValueType();
18313 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18314 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18316 // PMULxD operations multiply each even value (starting at 0) of LHS with
18317 // the related value of RHS and produce a widen result.
18318 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18319 // => <2 x i64> <ae|cg>
18321 // In other word, to have all the results, we need to perform two PMULxD:
18322 // 1. one with the even values.
18323 // 2. one with the odd values.
18324 // To achieve #2, with need to place the odd values at an even position.
18326 // Place the odd value at an even position (basically, shift all values 1
18327 // step to the left):
18328 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18329 // <a|b|c|d> => <b|undef|d|undef>
18330 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18331 // <e|f|g|h> => <f|undef|h|undef>
18332 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18334 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18336 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18337 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18339 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18340 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18341 // => <2 x i64> <ae|cg>
18342 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18343 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18344 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18345 // => <2 x i64> <bf|dh>
18346 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18347 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18349 // Shuffle it back into the right order.
18350 SDValue Highs, Lows;
18351 if (VT == MVT::v8i32) {
18352 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18353 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18354 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18355 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18357 const int HighMask[] = {1, 5, 3, 7};
18358 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18359 const int LowMask[] = {0, 4, 2, 6};
18360 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18363 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18364 // unsigned multiply.
18365 if (IsSigned && !Subtarget->hasSSE41()) {
18367 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18368 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18369 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18370 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18371 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18373 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18374 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18377 // The first result of MUL_LOHI is actually the low value, followed by the
18379 SDValue Ops[] = {Lows, Highs};
18380 return DAG.getMergeValues(Ops, dl);
18383 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18384 const X86Subtarget *Subtarget) {
18385 MVT VT = Op.getSimpleValueType();
18387 SDValue R = Op.getOperand(0);
18388 SDValue Amt = Op.getOperand(1);
18390 // Optimize shl/srl/sra with constant shift amount.
18391 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18392 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18393 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18395 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18396 (Subtarget->hasInt256() &&
18397 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18398 (Subtarget->hasAVX512() &&
18399 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18400 if (Op.getOpcode() == ISD::SHL)
18401 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18403 if (Op.getOpcode() == ISD::SRL)
18404 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18406 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18407 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18411 if (VT == MVT::v16i8) {
18412 if (Op.getOpcode() == ISD::SHL) {
18413 // Make a large shift.
18414 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18415 MVT::v8i16, R, ShiftAmt,
18417 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18418 // Zero out the rightmost bits.
18419 SmallVector<SDValue, 16> V(16,
18420 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18422 return DAG.getNode(ISD::AND, dl, VT, SHL,
18423 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18425 if (Op.getOpcode() == ISD::SRL) {
18426 // Make a large shift.
18427 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18428 MVT::v8i16, R, ShiftAmt,
18430 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18431 // Zero out the leftmost bits.
18432 SmallVector<SDValue, 16> V(16,
18433 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18435 return DAG.getNode(ISD::AND, dl, VT, SRL,
18436 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18438 if (Op.getOpcode() == ISD::SRA) {
18439 if (ShiftAmt == 7) {
18440 // R s>> 7 === R s< 0
18441 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18442 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18445 // R s>> a === ((R u>> a) ^ m) - m
18446 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18447 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18449 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18450 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18451 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18454 llvm_unreachable("Unknown shift opcode.");
18457 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18458 if (Op.getOpcode() == ISD::SHL) {
18459 // Make a large shift.
18460 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18461 MVT::v16i16, R, ShiftAmt,
18463 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18464 // Zero out the rightmost bits.
18465 SmallVector<SDValue, 32> V(32,
18466 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18468 return DAG.getNode(ISD::AND, dl, VT, SHL,
18469 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18471 if (Op.getOpcode() == ISD::SRL) {
18472 // Make a large shift.
18473 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18474 MVT::v16i16, R, ShiftAmt,
18476 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18477 // Zero out the leftmost bits.
18478 SmallVector<SDValue, 32> V(32,
18479 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18481 return DAG.getNode(ISD::AND, dl, VT, SRL,
18482 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18484 if (Op.getOpcode() == ISD::SRA) {
18485 if (ShiftAmt == 7) {
18486 // R s>> 7 === R s< 0
18487 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18488 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18491 // R s>> a === ((R u>> a) ^ m) - m
18492 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18493 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18495 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18496 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18497 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18500 llvm_unreachable("Unknown shift opcode.");
18505 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18506 if (!Subtarget->is64Bit() &&
18507 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18508 Amt.getOpcode() == ISD::BITCAST &&
18509 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18510 Amt = Amt.getOperand(0);
18511 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18512 VT.getVectorNumElements();
18513 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18514 uint64_t ShiftAmt = 0;
18515 for (unsigned i = 0; i != Ratio; ++i) {
18516 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18520 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18522 // Check remaining shift amounts.
18523 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18524 uint64_t ShAmt = 0;
18525 for (unsigned j = 0; j != Ratio; ++j) {
18526 ConstantSDNode *C =
18527 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18531 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18533 if (ShAmt != ShiftAmt)
18536 switch (Op.getOpcode()) {
18538 llvm_unreachable("Unknown shift opcode!");
18540 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18543 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18546 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18554 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18555 const X86Subtarget* Subtarget) {
18556 MVT VT = Op.getSimpleValueType();
18558 SDValue R = Op.getOperand(0);
18559 SDValue Amt = Op.getOperand(1);
18561 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18562 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18563 (Subtarget->hasInt256() &&
18564 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18565 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18566 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18568 EVT EltVT = VT.getVectorElementType();
18570 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18571 // Check if this build_vector node is doing a splat.
18572 // If so, then set BaseShAmt equal to the splat value.
18573 BaseShAmt = BV->getSplatValue();
18574 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18575 BaseShAmt = SDValue();
18577 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18578 Amt = Amt.getOperand(0);
18580 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18581 if (SVN && SVN->isSplat()) {
18582 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18583 SDValue InVec = Amt.getOperand(0);
18584 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18585 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18586 "Unexpected shuffle index found!");
18587 BaseShAmt = InVec.getOperand(SplatIdx);
18588 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18589 if (ConstantSDNode *C =
18590 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18591 if (C->getZExtValue() == SplatIdx)
18592 BaseShAmt = InVec.getOperand(1);
18597 // Avoid introducing an extract element from a shuffle.
18598 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18599 DAG.getIntPtrConstant(SplatIdx));
18603 if (BaseShAmt.getNode()) {
18604 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18605 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18606 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18607 else if (EltVT.bitsLT(MVT::i32))
18608 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18610 switch (Op.getOpcode()) {
18612 llvm_unreachable("Unknown shift opcode!");
18614 switch (VT.SimpleTy) {
18615 default: return SDValue();
18624 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18627 switch (VT.SimpleTy) {
18628 default: return SDValue();
18635 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18638 switch (VT.SimpleTy) {
18639 default: return SDValue();
18648 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18654 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18655 if (!Subtarget->is64Bit() &&
18656 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18657 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18658 Amt.getOpcode() == ISD::BITCAST &&
18659 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18660 Amt = Amt.getOperand(0);
18661 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18662 VT.getVectorNumElements();
18663 std::vector<SDValue> Vals(Ratio);
18664 for (unsigned i = 0; i != Ratio; ++i)
18665 Vals[i] = Amt.getOperand(i);
18666 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18667 for (unsigned j = 0; j != Ratio; ++j)
18668 if (Vals[j] != Amt.getOperand(i + j))
18671 switch (Op.getOpcode()) {
18673 llvm_unreachable("Unknown shift opcode!");
18675 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18677 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18679 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18686 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18687 SelectionDAG &DAG) {
18688 MVT VT = Op.getSimpleValueType();
18690 SDValue R = Op.getOperand(0);
18691 SDValue Amt = Op.getOperand(1);
18694 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18695 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18697 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18701 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18705 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18707 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18708 if (Subtarget->hasInt256()) {
18709 if (Op.getOpcode() == ISD::SRL &&
18710 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18711 VT == MVT::v4i64 || VT == MVT::v8i32))
18713 if (Op.getOpcode() == ISD::SHL &&
18714 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18715 VT == MVT::v4i64 || VT == MVT::v8i32))
18717 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18721 // If possible, lower this packed shift into a vector multiply instead of
18722 // expanding it into a sequence of scalar shifts.
18723 // Do this only if the vector shift count is a constant build_vector.
18724 if (Op.getOpcode() == ISD::SHL &&
18725 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18726 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18727 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18728 SmallVector<SDValue, 8> Elts;
18729 EVT SVT = VT.getScalarType();
18730 unsigned SVTBits = SVT.getSizeInBits();
18731 const APInt &One = APInt(SVTBits, 1);
18732 unsigned NumElems = VT.getVectorNumElements();
18734 for (unsigned i=0; i !=NumElems; ++i) {
18735 SDValue Op = Amt->getOperand(i);
18736 if (Op->getOpcode() == ISD::UNDEF) {
18737 Elts.push_back(Op);
18741 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18742 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18743 uint64_t ShAmt = C.getZExtValue();
18744 if (ShAmt >= SVTBits) {
18745 Elts.push_back(DAG.getUNDEF(SVT));
18748 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18750 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18751 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18754 // Lower SHL with variable shift amount.
18755 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18756 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18758 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18759 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18760 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18761 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18764 // If possible, lower this shift as a sequence of two shifts by
18765 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18767 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18769 // Could be rewritten as:
18770 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18772 // The advantage is that the two shifts from the example would be
18773 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18774 // the vector shift into four scalar shifts plus four pairs of vector
18776 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18777 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18778 unsigned TargetOpcode = X86ISD::MOVSS;
18779 bool CanBeSimplified;
18780 // The splat value for the first packed shift (the 'X' from the example).
18781 SDValue Amt1 = Amt->getOperand(0);
18782 // The splat value for the second packed shift (the 'Y' from the example).
18783 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18784 Amt->getOperand(2);
18786 // See if it is possible to replace this node with a sequence of
18787 // two shifts followed by a MOVSS/MOVSD
18788 if (VT == MVT::v4i32) {
18789 // Check if it is legal to use a MOVSS.
18790 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18791 Amt2 == Amt->getOperand(3);
18792 if (!CanBeSimplified) {
18793 // Otherwise, check if we can still simplify this node using a MOVSD.
18794 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18795 Amt->getOperand(2) == Amt->getOperand(3);
18796 TargetOpcode = X86ISD::MOVSD;
18797 Amt2 = Amt->getOperand(2);
18800 // Do similar checks for the case where the machine value type
18802 CanBeSimplified = Amt1 == Amt->getOperand(1);
18803 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18804 CanBeSimplified = Amt2 == Amt->getOperand(i);
18806 if (!CanBeSimplified) {
18807 TargetOpcode = X86ISD::MOVSD;
18808 CanBeSimplified = true;
18809 Amt2 = Amt->getOperand(4);
18810 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18811 CanBeSimplified = Amt1 == Amt->getOperand(i);
18812 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18813 CanBeSimplified = Amt2 == Amt->getOperand(j);
18817 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18818 isa<ConstantSDNode>(Amt2)) {
18819 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18820 EVT CastVT = MVT::v4i32;
18822 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18823 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18825 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18826 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18827 if (TargetOpcode == X86ISD::MOVSD)
18828 CastVT = MVT::v2i64;
18829 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18830 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18831 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18833 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18837 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18838 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18841 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18842 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18844 // Turn 'a' into a mask suitable for VSELECT
18845 SDValue VSelM = DAG.getConstant(0x80, VT);
18846 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18847 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18849 SDValue CM1 = DAG.getConstant(0x0f, VT);
18850 SDValue CM2 = DAG.getConstant(0x3f, VT);
18852 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18853 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18854 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18855 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18856 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18859 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18860 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18861 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18863 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18864 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18865 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18866 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18867 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18870 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18871 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18872 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18874 // return VSELECT(r, r+r, a);
18875 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18876 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18880 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18881 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18882 // solution better.
18883 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18884 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18886 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18887 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18888 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18889 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18890 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18893 // Decompose 256-bit shifts into smaller 128-bit shifts.
18894 if (VT.is256BitVector()) {
18895 unsigned NumElems = VT.getVectorNumElements();
18896 MVT EltVT = VT.getVectorElementType();
18897 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18899 // Extract the two vectors
18900 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18901 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18903 // Recreate the shift amount vectors
18904 SDValue Amt1, Amt2;
18905 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18906 // Constant shift amount
18907 SmallVector<SDValue, 4> Amt1Csts;
18908 SmallVector<SDValue, 4> Amt2Csts;
18909 for (unsigned i = 0; i != NumElems/2; ++i)
18910 Amt1Csts.push_back(Amt->getOperand(i));
18911 for (unsigned i = NumElems/2; i != NumElems; ++i)
18912 Amt2Csts.push_back(Amt->getOperand(i));
18914 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18915 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18917 // Variable shift amount
18918 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18919 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18922 // Issue new vector shifts for the smaller types
18923 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18924 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18926 // Concatenate the result back
18927 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18933 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18934 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18935 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18936 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18937 // has only one use.
18938 SDNode *N = Op.getNode();
18939 SDValue LHS = N->getOperand(0);
18940 SDValue RHS = N->getOperand(1);
18941 unsigned BaseOp = 0;
18944 switch (Op.getOpcode()) {
18945 default: llvm_unreachable("Unknown ovf instruction!");
18947 // A subtract of one will be selected as a INC. Note that INC doesn't
18948 // set CF, so we can't do this for UADDO.
18949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18951 BaseOp = X86ISD::INC;
18952 Cond = X86::COND_O;
18955 BaseOp = X86ISD::ADD;
18956 Cond = X86::COND_O;
18959 BaseOp = X86ISD::ADD;
18960 Cond = X86::COND_B;
18963 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18964 // set CF, so we can't do this for USUBO.
18965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18967 BaseOp = X86ISD::DEC;
18968 Cond = X86::COND_O;
18971 BaseOp = X86ISD::SUB;
18972 Cond = X86::COND_O;
18975 BaseOp = X86ISD::SUB;
18976 Cond = X86::COND_B;
18979 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18980 Cond = X86::COND_O;
18982 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18983 if (N->getValueType(0) == MVT::i8) {
18984 BaseOp = X86ISD::UMUL8;
18985 Cond = X86::COND_O;
18988 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18990 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18993 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18994 DAG.getConstant(X86::COND_O, MVT::i32),
18995 SDValue(Sum.getNode(), 2));
18997 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19001 // Also sets EFLAGS.
19002 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19003 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19006 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19007 DAG.getConstant(Cond, MVT::i32),
19008 SDValue(Sum.getNode(), 1));
19010 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19013 // Sign extension of the low part of vector elements. This may be used either
19014 // when sign extend instructions are not available or if the vector element
19015 // sizes already match the sign-extended size. If the vector elements are in
19016 // their pre-extended size and sign extend instructions are available, that will
19017 // be handled by LowerSIGN_EXTEND.
19018 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
19019 SelectionDAG &DAG) const {
19021 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
19022 MVT VT = Op.getSimpleValueType();
19024 if (!Subtarget->hasSSE2() || !VT.isVector())
19027 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
19028 ExtraVT.getScalarType().getSizeInBits();
19030 switch (VT.SimpleTy) {
19031 default: return SDValue();
19034 if (!Subtarget->hasFp256())
19036 if (!Subtarget->hasInt256()) {
19037 // needs to be split
19038 unsigned NumElems = VT.getVectorNumElements();
19040 // Extract the LHS vectors
19041 SDValue LHS = Op.getOperand(0);
19042 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
19043 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
19045 MVT EltVT = VT.getVectorElementType();
19046 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
19048 EVT ExtraEltVT = ExtraVT.getVectorElementType();
19049 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
19050 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
19052 SDValue Extra = DAG.getValueType(ExtraVT);
19054 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
19055 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
19057 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
19062 SDValue Op0 = Op.getOperand(0);
19064 // This is a sign extension of some low part of vector elements without
19065 // changing the size of the vector elements themselves:
19066 // Shift-Left + Shift-Right-Algebraic.
19067 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
19069 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
19075 /// Returns true if the operand type is exactly twice the native width, and
19076 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19077 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19078 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19079 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
19080 const X86Subtarget &Subtarget =
19081 getTargetMachine().getSubtarget<X86Subtarget>();
19082 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19085 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19086 else if (OpWidth == 128)
19087 return Subtarget.hasCmpxchg16b();
19092 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19093 return needsCmpXchgNb(SI->getValueOperand()->getType());
19096 // Note: this turns large loads into lock cmpxchg8b/16b.
19097 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19098 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19099 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19100 return needsCmpXchgNb(PTy->getElementType());
19103 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19104 const X86Subtarget &Subtarget =
19105 getTargetMachine().getSubtarget<X86Subtarget>();
19106 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19107 const Type *MemType = AI->getType();
19109 // If the operand is too big, we must see if cmpxchg8/16b is available
19110 // and default to library calls otherwise.
19111 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19112 return needsCmpXchgNb(MemType);
19114 AtomicRMWInst::BinOp Op = AI->getOperation();
19117 llvm_unreachable("Unknown atomic operation");
19118 case AtomicRMWInst::Xchg:
19119 case AtomicRMWInst::Add:
19120 case AtomicRMWInst::Sub:
19121 // It's better to use xadd, xsub or xchg for these in all cases.
19123 case AtomicRMWInst::Or:
19124 case AtomicRMWInst::And:
19125 case AtomicRMWInst::Xor:
19126 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19127 // prefix to a normal instruction for these operations.
19128 return !AI->use_empty();
19129 case AtomicRMWInst::Nand:
19130 case AtomicRMWInst::Max:
19131 case AtomicRMWInst::Min:
19132 case AtomicRMWInst::UMax:
19133 case AtomicRMWInst::UMin:
19134 // These always require a non-trivial set of data operations on x86. We must
19135 // use a cmpxchg loop.
19140 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19141 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19142 // no-sse2). There isn't any reason to disable it if the target processor
19144 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19148 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19149 const X86Subtarget &Subtarget =
19150 getTargetMachine().getSubtarget<X86Subtarget>();
19151 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19152 const Type *MemType = AI->getType();
19153 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19154 // there is no benefit in turning such RMWs into loads, and it is actually
19155 // harmful as it introduces a mfence.
19156 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19159 auto Builder = IRBuilder<>(AI);
19160 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19161 auto SynchScope = AI->getSynchScope();
19162 // We must restrict the ordering to avoid generating loads with Release or
19163 // ReleaseAcquire orderings.
19164 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19165 auto Ptr = AI->getPointerOperand();
19167 // Before the load we need a fence. Here is an example lifted from
19168 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19171 // x.store(1, relaxed);
19172 // r1 = y.fetch_add(0, release);
19174 // y.fetch_add(42, acquire);
19175 // r2 = x.load(relaxed);
19176 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19177 // lowered to just a load without a fence. A mfence flushes the store buffer,
19178 // making the optimization clearly correct.
19179 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19180 // otherwise, we might be able to be more agressive on relaxed idempotent
19181 // rmw. In practice, they do not look useful, so we don't try to be
19182 // especially clever.
19183 if (SynchScope == SingleThread) {
19184 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19185 // the IR level, so we must wrap it in an intrinsic.
19187 } else if (hasMFENCE(Subtarget)) {
19188 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19189 Intrinsic::x86_sse2_mfence);
19190 Builder.CreateCall(MFence);
19192 // FIXME: it might make sense to use a locked operation here but on a
19193 // different cache-line to prevent cache-line bouncing. In practice it
19194 // is probably a small win, and x86 processors without mfence are rare
19195 // enough that we do not bother.
19199 // Finally we can emit the atomic load.
19200 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19201 AI->getType()->getPrimitiveSizeInBits());
19202 Loaded->setAtomic(Order, SynchScope);
19203 AI->replaceAllUsesWith(Loaded);
19204 AI->eraseFromParent();
19208 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19209 SelectionDAG &DAG) {
19211 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19212 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19213 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19214 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19216 // The only fence that needs an instruction is a sequentially-consistent
19217 // cross-thread fence.
19218 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19219 if (hasMFENCE(*Subtarget))
19220 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19222 SDValue Chain = Op.getOperand(0);
19223 SDValue Zero = DAG.getConstant(0, MVT::i32);
19225 DAG.getRegister(X86::ESP, MVT::i32), // Base
19226 DAG.getTargetConstant(1, MVT::i8), // Scale
19227 DAG.getRegister(0, MVT::i32), // Index
19228 DAG.getTargetConstant(0, MVT::i32), // Disp
19229 DAG.getRegister(0, MVT::i32), // Segment.
19233 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19234 return SDValue(Res, 0);
19237 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19238 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19241 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19242 SelectionDAG &DAG) {
19243 MVT T = Op.getSimpleValueType();
19247 switch(T.SimpleTy) {
19248 default: llvm_unreachable("Invalid value type!");
19249 case MVT::i8: Reg = X86::AL; size = 1; break;
19250 case MVT::i16: Reg = X86::AX; size = 2; break;
19251 case MVT::i32: Reg = X86::EAX; size = 4; break;
19253 assert(Subtarget->is64Bit() && "Node not type legal!");
19254 Reg = X86::RAX; size = 8;
19257 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19258 Op.getOperand(2), SDValue());
19259 SDValue Ops[] = { cpIn.getValue(0),
19262 DAG.getTargetConstant(size, MVT::i8),
19263 cpIn.getValue(1) };
19264 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19265 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19266 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19270 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19271 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19272 MVT::i32, cpOut.getValue(2));
19273 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19274 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19276 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19277 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19278 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19282 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19283 SelectionDAG &DAG) {
19284 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19285 MVT DstVT = Op.getSimpleValueType();
19287 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19288 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19289 if (DstVT != MVT::f64)
19290 // This conversion needs to be expanded.
19293 SDValue InVec = Op->getOperand(0);
19295 unsigned NumElts = SrcVT.getVectorNumElements();
19296 EVT SVT = SrcVT.getVectorElementType();
19298 // Widen the vector in input in the case of MVT::v2i32.
19299 // Example: from MVT::v2i32 to MVT::v4i32.
19300 SmallVector<SDValue, 16> Elts;
19301 for (unsigned i = 0, e = NumElts; i != e; ++i)
19302 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19303 DAG.getIntPtrConstant(i)));
19305 // Explicitly mark the extra elements as Undef.
19306 SDValue Undef = DAG.getUNDEF(SVT);
19307 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19308 Elts.push_back(Undef);
19310 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19311 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19312 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19314 DAG.getIntPtrConstant(0));
19317 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19318 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19319 assert((DstVT == MVT::i64 ||
19320 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19321 "Unexpected custom BITCAST");
19322 // i64 <=> MMX conversions are Legal.
19323 if (SrcVT==MVT::i64 && DstVT.isVector())
19325 if (DstVT==MVT::i64 && SrcVT.isVector())
19327 // MMX <=> MMX conversions are Legal.
19328 if (SrcVT.isVector() && DstVT.isVector())
19330 // All other conversions need to be expanded.
19334 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19335 SelectionDAG &DAG) {
19336 SDNode *Node = Op.getNode();
19339 Op = Op.getOperand(0);
19340 EVT VT = Op.getValueType();
19341 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19342 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19344 unsigned NumElts = VT.getVectorNumElements();
19345 EVT EltVT = VT.getVectorElementType();
19346 unsigned Len = EltVT.getSizeInBits();
19348 // This is the vectorized version of the "best" algorithm from
19349 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19350 // with a minor tweak to use a series of adds + shifts instead of vector
19351 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19353 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19354 // v8i32 => Always profitable
19356 // FIXME: There a couple of possible improvements:
19358 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19359 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19361 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19362 "CTPOP not implemented for this vector element type.");
19364 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19365 // extra legalization.
19366 bool NeedsBitcast = EltVT == MVT::i32;
19367 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19369 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19370 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19371 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19373 // v = v - ((v >> 1) & 0x55555555...)
19374 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19375 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19376 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19378 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19380 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19381 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19383 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19385 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19386 if (VT != And.getValueType())
19387 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19388 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19390 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19391 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19392 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19393 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19394 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19396 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19397 if (NeedsBitcast) {
19398 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19399 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19400 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19403 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19404 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19405 if (VT != AndRHS.getValueType()) {
19406 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19407 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19409 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19411 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19412 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19413 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19414 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19415 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19417 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19418 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19419 if (NeedsBitcast) {
19420 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19421 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19423 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19424 if (VT != And.getValueType())
19425 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19427 // The algorithm mentioned above uses:
19428 // v = (v * 0x01010101...) >> (Len - 8)
19430 // Change it to use vector adds + vector shifts which yield faster results on
19431 // Haswell than using vector integer multiplication.
19433 // For i32 elements:
19434 // v = v + (v >> 8)
19435 // v = v + (v >> 16)
19437 // For i64 elements:
19438 // v = v + (v >> 8)
19439 // v = v + (v >> 16)
19440 // v = v + (v >> 32)
19443 SmallVector<SDValue, 8> Csts;
19444 for (unsigned i = 8; i <= Len/2; i *= 2) {
19445 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19446 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19447 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19448 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19452 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19453 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19454 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19455 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19456 if (NeedsBitcast) {
19457 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19458 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19460 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19461 if (VT != And.getValueType())
19462 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19467 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19468 SDNode *Node = Op.getNode();
19470 EVT T = Node->getValueType(0);
19471 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19472 DAG.getConstant(0, T), Node->getOperand(2));
19473 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19474 cast<AtomicSDNode>(Node)->getMemoryVT(),
19475 Node->getOperand(0),
19476 Node->getOperand(1), negOp,
19477 cast<AtomicSDNode>(Node)->getMemOperand(),
19478 cast<AtomicSDNode>(Node)->getOrdering(),
19479 cast<AtomicSDNode>(Node)->getSynchScope());
19482 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19483 SDNode *Node = Op.getNode();
19485 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19487 // Convert seq_cst store -> xchg
19488 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19489 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19490 // (The only way to get a 16-byte store is cmpxchg16b)
19491 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19492 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19493 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19494 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19495 cast<AtomicSDNode>(Node)->getMemoryVT(),
19496 Node->getOperand(0),
19497 Node->getOperand(1), Node->getOperand(2),
19498 cast<AtomicSDNode>(Node)->getMemOperand(),
19499 cast<AtomicSDNode>(Node)->getOrdering(),
19500 cast<AtomicSDNode>(Node)->getSynchScope());
19501 return Swap.getValue(1);
19503 // Other atomic stores have a simple pattern.
19507 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19508 EVT VT = Op.getNode()->getSimpleValueType(0);
19510 // Let legalize expand this if it isn't a legal type yet.
19511 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19514 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19517 bool ExtraOp = false;
19518 switch (Op.getOpcode()) {
19519 default: llvm_unreachable("Invalid code");
19520 case ISD::ADDC: Opc = X86ISD::ADD; break;
19521 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19522 case ISD::SUBC: Opc = X86ISD::SUB; break;
19523 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19527 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19529 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19530 Op.getOperand(1), Op.getOperand(2));
19533 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19534 SelectionDAG &DAG) {
19535 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19537 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19538 // which returns the values as { float, float } (in XMM0) or
19539 // { double, double } (which is returned in XMM0, XMM1).
19541 SDValue Arg = Op.getOperand(0);
19542 EVT ArgVT = Arg.getValueType();
19543 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19545 TargetLowering::ArgListTy Args;
19546 TargetLowering::ArgListEntry Entry;
19550 Entry.isSExt = false;
19551 Entry.isZExt = false;
19552 Args.push_back(Entry);
19554 bool isF64 = ArgVT == MVT::f64;
19555 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19556 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19557 // the results are returned via SRet in memory.
19558 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19560 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19562 Type *RetTy = isF64
19563 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19564 : (Type*)VectorType::get(ArgTy, 4);
19566 TargetLowering::CallLoweringInfo CLI(DAG);
19567 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19568 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19570 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19573 // Returned in xmm0 and xmm1.
19574 return CallResult.first;
19576 // Returned in bits 0:31 and 32:64 xmm0.
19577 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19578 CallResult.first, DAG.getIntPtrConstant(0));
19579 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19580 CallResult.first, DAG.getIntPtrConstant(1));
19581 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19582 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19585 /// LowerOperation - Provide custom lowering hooks for some operations.
19587 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19588 switch (Op.getOpcode()) {
19589 default: llvm_unreachable("Should not custom lower this!");
19590 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19591 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19592 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19593 return LowerCMP_SWAP(Op, Subtarget, DAG);
19594 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19595 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19596 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19597 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19598 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19599 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19600 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19601 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19602 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19603 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19604 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19605 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19606 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19607 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19608 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19609 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19610 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19611 case ISD::SHL_PARTS:
19612 case ISD::SRA_PARTS:
19613 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19614 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19615 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19616 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19617 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19618 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19619 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19620 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19621 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19622 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19623 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19625 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19626 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19627 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19628 case ISD::SETCC: return LowerSETCC(Op, DAG);
19629 case ISD::SELECT: return LowerSELECT(Op, DAG);
19630 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19631 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19632 case ISD::VASTART: return LowerVASTART(Op, DAG);
19633 case ISD::VAARG: return LowerVAARG(Op, DAG);
19634 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19635 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19636 case ISD::INTRINSIC_VOID:
19637 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19638 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19639 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19640 case ISD::FRAME_TO_ARGS_OFFSET:
19641 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19642 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19643 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19644 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19645 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19646 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19647 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19648 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19649 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19650 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19651 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19652 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19653 case ISD::UMUL_LOHI:
19654 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19657 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19663 case ISD::UMULO: return LowerXALUO(Op, DAG);
19664 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19665 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19669 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19670 case ISD::ADD: return LowerADD(Op, DAG);
19671 case ISD::SUB: return LowerSUB(Op, DAG);
19672 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19676 /// ReplaceNodeResults - Replace a node with an illegal result type
19677 /// with a new node built out of custom code.
19678 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19679 SmallVectorImpl<SDValue>&Results,
19680 SelectionDAG &DAG) const {
19682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19683 switch (N->getOpcode()) {
19685 llvm_unreachable("Do not know how to custom type legalize this operation!");
19686 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19687 case X86ISD::FMINC:
19689 case X86ISD::FMAXC:
19690 case X86ISD::FMAX: {
19691 EVT VT = N->getValueType(0);
19692 if (VT != MVT::v2f32)
19693 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19694 SDValue UNDEF = DAG.getUNDEF(VT);
19695 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19696 N->getOperand(0), UNDEF);
19697 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19698 N->getOperand(1), UNDEF);
19699 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19702 case ISD::SIGN_EXTEND_INREG:
19707 // We don't want to expand or promote these.
19714 case ISD::UDIVREM: {
19715 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19716 Results.push_back(V);
19719 case ISD::FP_TO_SINT:
19720 case ISD::FP_TO_UINT: {
19721 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19723 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19726 std::pair<SDValue,SDValue> Vals =
19727 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19728 SDValue FIST = Vals.first, StackSlot = Vals.second;
19729 if (FIST.getNode()) {
19730 EVT VT = N->getValueType(0);
19731 // Return a load from the stack slot.
19732 if (StackSlot.getNode())
19733 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19734 MachinePointerInfo(),
19735 false, false, false, 0));
19737 Results.push_back(FIST);
19741 case ISD::UINT_TO_FP: {
19742 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19743 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19744 N->getValueType(0) != MVT::v2f32)
19746 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19748 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19750 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19751 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19752 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19753 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19754 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19755 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19758 case ISD::FP_ROUND: {
19759 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19761 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19762 Results.push_back(V);
19765 case ISD::INTRINSIC_W_CHAIN: {
19766 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19768 default : llvm_unreachable("Do not know how to custom type "
19769 "legalize this intrinsic operation!");
19770 case Intrinsic::x86_rdtsc:
19771 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19773 case Intrinsic::x86_rdtscp:
19774 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19776 case Intrinsic::x86_rdpmc:
19777 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19780 case ISD::READCYCLECOUNTER: {
19781 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19784 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19785 EVT T = N->getValueType(0);
19786 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19787 bool Regs64bit = T == MVT::i128;
19788 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19789 SDValue cpInL, cpInH;
19790 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19791 DAG.getConstant(0, HalfT));
19792 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19793 DAG.getConstant(1, HalfT));
19794 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19795 Regs64bit ? X86::RAX : X86::EAX,
19797 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19798 Regs64bit ? X86::RDX : X86::EDX,
19799 cpInH, cpInL.getValue(1));
19800 SDValue swapInL, swapInH;
19801 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19802 DAG.getConstant(0, HalfT));
19803 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19804 DAG.getConstant(1, HalfT));
19805 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19806 Regs64bit ? X86::RBX : X86::EBX,
19807 swapInL, cpInH.getValue(1));
19808 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19809 Regs64bit ? X86::RCX : X86::ECX,
19810 swapInH, swapInL.getValue(1));
19811 SDValue Ops[] = { swapInH.getValue(0),
19813 swapInH.getValue(1) };
19814 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19815 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19816 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19817 X86ISD::LCMPXCHG8_DAG;
19818 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19819 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19820 Regs64bit ? X86::RAX : X86::EAX,
19821 HalfT, Result.getValue(1));
19822 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19823 Regs64bit ? X86::RDX : X86::EDX,
19824 HalfT, cpOutL.getValue(2));
19825 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19827 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19828 MVT::i32, cpOutH.getValue(2));
19830 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19831 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19832 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19834 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19835 Results.push_back(Success);
19836 Results.push_back(EFLAGS.getValue(1));
19839 case ISD::ATOMIC_SWAP:
19840 case ISD::ATOMIC_LOAD_ADD:
19841 case ISD::ATOMIC_LOAD_SUB:
19842 case ISD::ATOMIC_LOAD_AND:
19843 case ISD::ATOMIC_LOAD_OR:
19844 case ISD::ATOMIC_LOAD_XOR:
19845 case ISD::ATOMIC_LOAD_NAND:
19846 case ISD::ATOMIC_LOAD_MIN:
19847 case ISD::ATOMIC_LOAD_MAX:
19848 case ISD::ATOMIC_LOAD_UMIN:
19849 case ISD::ATOMIC_LOAD_UMAX:
19850 case ISD::ATOMIC_LOAD: {
19851 // Delegate to generic TypeLegalization. Situations we can really handle
19852 // should have already been dealt with by AtomicExpandPass.cpp.
19855 case ISD::BITCAST: {
19856 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19857 EVT DstVT = N->getValueType(0);
19858 EVT SrcVT = N->getOperand(0)->getValueType(0);
19860 if (SrcVT != MVT::f64 ||
19861 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19864 unsigned NumElts = DstVT.getVectorNumElements();
19865 EVT SVT = DstVT.getVectorElementType();
19866 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19867 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19868 MVT::v2f64, N->getOperand(0));
19869 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19871 if (ExperimentalVectorWideningLegalization) {
19872 // If we are legalizing vectors by widening, we already have the desired
19873 // legal vector type, just return it.
19874 Results.push_back(ToVecInt);
19878 SmallVector<SDValue, 8> Elts;
19879 for (unsigned i = 0, e = NumElts; i != e; ++i)
19880 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19881 ToVecInt, DAG.getIntPtrConstant(i)));
19883 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19888 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19890 default: return nullptr;
19891 case X86ISD::BSF: return "X86ISD::BSF";
19892 case X86ISD::BSR: return "X86ISD::BSR";
19893 case X86ISD::SHLD: return "X86ISD::SHLD";
19894 case X86ISD::SHRD: return "X86ISD::SHRD";
19895 case X86ISD::FAND: return "X86ISD::FAND";
19896 case X86ISD::FANDN: return "X86ISD::FANDN";
19897 case X86ISD::FOR: return "X86ISD::FOR";
19898 case X86ISD::FXOR: return "X86ISD::FXOR";
19899 case X86ISD::FSRL: return "X86ISD::FSRL";
19900 case X86ISD::FILD: return "X86ISD::FILD";
19901 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19902 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19903 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19904 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19905 case X86ISD::FLD: return "X86ISD::FLD";
19906 case X86ISD::FST: return "X86ISD::FST";
19907 case X86ISD::CALL: return "X86ISD::CALL";
19908 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19909 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19910 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19911 case X86ISD::BT: return "X86ISD::BT";
19912 case X86ISD::CMP: return "X86ISD::CMP";
19913 case X86ISD::COMI: return "X86ISD::COMI";
19914 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19915 case X86ISD::CMPM: return "X86ISD::CMPM";
19916 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19917 case X86ISD::SETCC: return "X86ISD::SETCC";
19918 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19919 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19920 case X86ISD::CMOV: return "X86ISD::CMOV";
19921 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19922 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19923 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19924 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19925 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19926 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19927 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19928 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19929 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19930 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19931 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19932 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19933 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19934 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19935 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19936 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19937 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19938 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19939 case X86ISD::HADD: return "X86ISD::HADD";
19940 case X86ISD::HSUB: return "X86ISD::HSUB";
19941 case X86ISD::FHADD: return "X86ISD::FHADD";
19942 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19943 case X86ISD::UMAX: return "X86ISD::UMAX";
19944 case X86ISD::UMIN: return "X86ISD::UMIN";
19945 case X86ISD::SMAX: return "X86ISD::SMAX";
19946 case X86ISD::SMIN: return "X86ISD::SMIN";
19947 case X86ISD::FMAX: return "X86ISD::FMAX";
19948 case X86ISD::FMIN: return "X86ISD::FMIN";
19949 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19950 case X86ISD::FMINC: return "X86ISD::FMINC";
19951 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19952 case X86ISD::FRCP: return "X86ISD::FRCP";
19953 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19954 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19955 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19956 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19957 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19958 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19959 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19960 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19961 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19962 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19963 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19964 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19965 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19966 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19967 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19968 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19969 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19970 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19971 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19972 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19973 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19974 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19975 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19976 case X86ISD::VSHL: return "X86ISD::VSHL";
19977 case X86ISD::VSRL: return "X86ISD::VSRL";
19978 case X86ISD::VSRA: return "X86ISD::VSRA";
19979 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19980 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19981 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19982 case X86ISD::CMPP: return "X86ISD::CMPP";
19983 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19984 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19985 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19986 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19987 case X86ISD::ADD: return "X86ISD::ADD";
19988 case X86ISD::SUB: return "X86ISD::SUB";
19989 case X86ISD::ADC: return "X86ISD::ADC";
19990 case X86ISD::SBB: return "X86ISD::SBB";
19991 case X86ISD::SMUL: return "X86ISD::SMUL";
19992 case X86ISD::UMUL: return "X86ISD::UMUL";
19993 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19994 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19995 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19996 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19997 case X86ISD::INC: return "X86ISD::INC";
19998 case X86ISD::DEC: return "X86ISD::DEC";
19999 case X86ISD::OR: return "X86ISD::OR";
20000 case X86ISD::XOR: return "X86ISD::XOR";
20001 case X86ISD::AND: return "X86ISD::AND";
20002 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20003 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20004 case X86ISD::PTEST: return "X86ISD::PTEST";
20005 case X86ISD::TESTP: return "X86ISD::TESTP";
20006 case X86ISD::TESTM: return "X86ISD::TESTM";
20007 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20008 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20009 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20010 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20011 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20012 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20013 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20014 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20015 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20016 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20017 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20018 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20019 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20020 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20021 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20022 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20023 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20024 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20025 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20026 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20027 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20028 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20029 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20030 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20031 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20032 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20033 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20034 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20035 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20036 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20037 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20038 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20039 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20040 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20041 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20042 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20043 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20044 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20045 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
20046 case X86ISD::SAHF: return "X86ISD::SAHF";
20047 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20048 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20049 case X86ISD::FMADD: return "X86ISD::FMADD";
20050 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20051 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20052 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20053 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20054 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20055 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20056 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20057 case X86ISD::XTEST: return "X86ISD::XTEST";
20058 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20059 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20060 case X86ISD::SELECT: return "X86ISD::SELECT";
20064 // isLegalAddressingMode - Return true if the addressing mode represented
20065 // by AM is legal for this target, for a load/store of the specified type.
20066 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
20068 // X86 supports extremely general addressing modes.
20069 CodeModel::Model M = getTargetMachine().getCodeModel();
20070 Reloc::Model R = getTargetMachine().getRelocationModel();
20072 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20073 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20078 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20080 // If a reference to this global requires an extra load, we can't fold it.
20081 if (isGlobalStubReference(GVFlags))
20084 // If BaseGV requires a register for the PIC base, we cannot also have a
20085 // BaseReg specified.
20086 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20089 // If lower 4G is not available, then we must use rip-relative addressing.
20090 if ((M != CodeModel::Small || R != Reloc::Static) &&
20091 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20095 switch (AM.Scale) {
20101 // These scales always work.
20106 // These scales are formed with basereg+scalereg. Only accept if there is
20111 default: // Other stuff never works.
20118 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20119 unsigned Bits = Ty->getScalarSizeInBits();
20121 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20122 // particularly cheaper than those without.
20126 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20127 // variable shifts just as cheap as scalar ones.
20128 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20131 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20132 // fully general vector.
20136 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20137 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20139 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20140 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20141 return NumBits1 > NumBits2;
20144 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20145 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20148 if (!isTypeLegal(EVT::getEVT(Ty1)))
20151 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20153 // Assuming the caller doesn't have a zeroext or signext return parameter,
20154 // truncation all the way down to i1 is valid.
20158 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20159 return isInt<32>(Imm);
20162 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20163 // Can also use sub to handle negated immediates.
20164 return isInt<32>(Imm);
20167 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20168 if (!VT1.isInteger() || !VT2.isInteger())
20170 unsigned NumBits1 = VT1.getSizeInBits();
20171 unsigned NumBits2 = VT2.getSizeInBits();
20172 return NumBits1 > NumBits2;
20175 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20176 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20177 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20180 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20181 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20182 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20185 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20186 EVT VT1 = Val.getValueType();
20187 if (isZExtFree(VT1, VT2))
20190 if (Val.getOpcode() != ISD::LOAD)
20193 if (!VT1.isSimple() || !VT1.isInteger() ||
20194 !VT2.isSimple() || !VT2.isInteger())
20197 switch (VT1.getSimpleVT().SimpleTy) {
20202 // X86 has 8, 16, and 32-bit zero-extending loads.
20210 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20211 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20214 VT = VT.getScalarType();
20216 if (!VT.isSimple())
20219 switch (VT.getSimpleVT().SimpleTy) {
20230 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20231 // i16 instructions are longer (0x66 prefix) and potentially slower.
20232 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20235 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20236 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20237 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20238 /// are assumed to be legal.
20240 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20242 if (!VT.isSimple())
20245 MVT SVT = VT.getSimpleVT();
20247 // Very little shuffling can be done for 64-bit vectors right now.
20248 if (VT.getSizeInBits() == 64)
20251 // This is an experimental legality test that is tailored to match the
20252 // legality test of the experimental lowering more closely. They are gated
20253 // separately to ease testing of performance differences.
20254 if (ExperimentalVectorShuffleLegality)
20255 // We only care that the types being shuffled are legal. The lowering can
20256 // handle any possible shuffle mask that results.
20257 return isTypeLegal(SVT);
20259 // If this is a single-input shuffle with no 128 bit lane crossings we can
20260 // lower it into pshufb.
20261 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20262 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20263 bool isLegal = true;
20264 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20265 if (M[I] >= (int)SVT.getVectorNumElements() ||
20266 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20275 // FIXME: blends, shifts.
20276 return (SVT.getVectorNumElements() == 2 ||
20277 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20278 isMOVLMask(M, SVT) ||
20279 isCommutedMOVLMask(M, SVT) ||
20280 isMOVHLPSMask(M, SVT) ||
20281 isSHUFPMask(M, SVT) ||
20282 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20283 isPSHUFDMask(M, SVT) ||
20284 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20285 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20286 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20287 isPALIGNRMask(M, SVT, Subtarget) ||
20288 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20289 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20290 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20291 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20292 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20293 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20297 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20299 if (!VT.isSimple())
20302 MVT SVT = VT.getSimpleVT();
20304 // This is an experimental legality test that is tailored to match the
20305 // legality test of the experimental lowering more closely. They are gated
20306 // separately to ease testing of performance differences.
20307 if (ExperimentalVectorShuffleLegality)
20308 // The new vector shuffle lowering is very good at managing zero-inputs.
20309 return isShuffleMaskLegal(Mask, VT);
20311 unsigned NumElts = SVT.getVectorNumElements();
20312 // FIXME: This collection of masks seems suspect.
20315 if (NumElts == 4 && SVT.is128BitVector()) {
20316 return (isMOVLMask(Mask, SVT) ||
20317 isCommutedMOVLMask(Mask, SVT, true) ||
20318 isSHUFPMask(Mask, SVT) ||
20319 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20320 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20321 Subtarget->hasInt256()));
20326 //===----------------------------------------------------------------------===//
20327 // X86 Scheduler Hooks
20328 //===----------------------------------------------------------------------===//
20330 /// Utility function to emit xbegin specifying the start of an RTM region.
20331 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20332 const TargetInstrInfo *TII) {
20333 DebugLoc DL = MI->getDebugLoc();
20335 const BasicBlock *BB = MBB->getBasicBlock();
20336 MachineFunction::iterator I = MBB;
20339 // For the v = xbegin(), we generate
20350 MachineBasicBlock *thisMBB = MBB;
20351 MachineFunction *MF = MBB->getParent();
20352 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20353 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20354 MF->insert(I, mainMBB);
20355 MF->insert(I, sinkMBB);
20357 // Transfer the remainder of BB and its successor edges to sinkMBB.
20358 sinkMBB->splice(sinkMBB->begin(), MBB,
20359 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20360 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20364 // # fallthrough to mainMBB
20365 // # abortion to sinkMBB
20366 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20367 thisMBB->addSuccessor(mainMBB);
20368 thisMBB->addSuccessor(sinkMBB);
20372 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20373 mainMBB->addSuccessor(sinkMBB);
20376 // EAX is live into the sinkMBB
20377 sinkMBB->addLiveIn(X86::EAX);
20378 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20379 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20382 MI->eraseFromParent();
20386 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20387 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20388 // in the .td file.
20389 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20390 const TargetInstrInfo *TII) {
20392 switch (MI->getOpcode()) {
20393 default: llvm_unreachable("illegal opcode!");
20394 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20395 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20396 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20397 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20398 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20399 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20400 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20401 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20404 DebugLoc dl = MI->getDebugLoc();
20405 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20407 unsigned NumArgs = MI->getNumOperands();
20408 for (unsigned i = 1; i < NumArgs; ++i) {
20409 MachineOperand &Op = MI->getOperand(i);
20410 if (!(Op.isReg() && Op.isImplicit()))
20411 MIB.addOperand(Op);
20413 if (MI->hasOneMemOperand())
20414 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20416 BuildMI(*BB, MI, dl,
20417 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20418 .addReg(X86::XMM0);
20420 MI->eraseFromParent();
20424 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20425 // defs in an instruction pattern
20426 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20427 const TargetInstrInfo *TII) {
20429 switch (MI->getOpcode()) {
20430 default: llvm_unreachable("illegal opcode!");
20431 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20432 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20433 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20434 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20435 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20436 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20437 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20438 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20441 DebugLoc dl = MI->getDebugLoc();
20442 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20444 unsigned NumArgs = MI->getNumOperands(); // remove the results
20445 for (unsigned i = 1; i < NumArgs; ++i) {
20446 MachineOperand &Op = MI->getOperand(i);
20447 if (!(Op.isReg() && Op.isImplicit()))
20448 MIB.addOperand(Op);
20450 if (MI->hasOneMemOperand())
20451 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20453 BuildMI(*BB, MI, dl,
20454 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20457 MI->eraseFromParent();
20461 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20462 const TargetInstrInfo *TII,
20463 const X86Subtarget* Subtarget) {
20464 DebugLoc dl = MI->getDebugLoc();
20466 // Address into RAX/EAX, other two args into ECX, EDX.
20467 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20468 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20469 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20470 for (int i = 0; i < X86::AddrNumOperands; ++i)
20471 MIB.addOperand(MI->getOperand(i));
20473 unsigned ValOps = X86::AddrNumOperands;
20474 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20475 .addReg(MI->getOperand(ValOps).getReg());
20476 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20477 .addReg(MI->getOperand(ValOps+1).getReg());
20479 // The instruction doesn't actually take any operands though.
20480 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20482 MI->eraseFromParent(); // The pseudo is gone now.
20486 MachineBasicBlock *
20487 X86TargetLowering::EmitVAARG64WithCustomInserter(
20489 MachineBasicBlock *MBB) const {
20490 // Emit va_arg instruction on X86-64.
20492 // Operands to this pseudo-instruction:
20493 // 0 ) Output : destination address (reg)
20494 // 1-5) Input : va_list address (addr, i64mem)
20495 // 6 ) ArgSize : Size (in bytes) of vararg type
20496 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20497 // 8 ) Align : Alignment of type
20498 // 9 ) EFLAGS (implicit-def)
20500 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20501 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20503 unsigned DestReg = MI->getOperand(0).getReg();
20504 MachineOperand &Base = MI->getOperand(1);
20505 MachineOperand &Scale = MI->getOperand(2);
20506 MachineOperand &Index = MI->getOperand(3);
20507 MachineOperand &Disp = MI->getOperand(4);
20508 MachineOperand &Segment = MI->getOperand(5);
20509 unsigned ArgSize = MI->getOperand(6).getImm();
20510 unsigned ArgMode = MI->getOperand(7).getImm();
20511 unsigned Align = MI->getOperand(8).getImm();
20513 // Memory Reference
20514 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20515 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20516 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20518 // Machine Information
20519 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20520 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20521 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20522 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20523 DebugLoc DL = MI->getDebugLoc();
20525 // struct va_list {
20528 // i64 overflow_area (address)
20529 // i64 reg_save_area (address)
20531 // sizeof(va_list) = 24
20532 // alignment(va_list) = 8
20534 unsigned TotalNumIntRegs = 6;
20535 unsigned TotalNumXMMRegs = 8;
20536 bool UseGPOffset = (ArgMode == 1);
20537 bool UseFPOffset = (ArgMode == 2);
20538 unsigned MaxOffset = TotalNumIntRegs * 8 +
20539 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20541 /* Align ArgSize to a multiple of 8 */
20542 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20543 bool NeedsAlign = (Align > 8);
20545 MachineBasicBlock *thisMBB = MBB;
20546 MachineBasicBlock *overflowMBB;
20547 MachineBasicBlock *offsetMBB;
20548 MachineBasicBlock *endMBB;
20550 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20551 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20552 unsigned OffsetReg = 0;
20554 if (!UseGPOffset && !UseFPOffset) {
20555 // If we only pull from the overflow region, we don't create a branch.
20556 // We don't need to alter control flow.
20557 OffsetDestReg = 0; // unused
20558 OverflowDestReg = DestReg;
20560 offsetMBB = nullptr;
20561 overflowMBB = thisMBB;
20564 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20565 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20566 // If not, pull from overflow_area. (branch to overflowMBB)
20571 // offsetMBB overflowMBB
20576 // Registers for the PHI in endMBB
20577 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20578 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20580 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20581 MachineFunction *MF = MBB->getParent();
20582 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20583 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20584 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20586 MachineFunction::iterator MBBIter = MBB;
20589 // Insert the new basic blocks
20590 MF->insert(MBBIter, offsetMBB);
20591 MF->insert(MBBIter, overflowMBB);
20592 MF->insert(MBBIter, endMBB);
20594 // Transfer the remainder of MBB and its successor edges to endMBB.
20595 endMBB->splice(endMBB->begin(), thisMBB,
20596 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20597 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20599 // Make offsetMBB and overflowMBB successors of thisMBB
20600 thisMBB->addSuccessor(offsetMBB);
20601 thisMBB->addSuccessor(overflowMBB);
20603 // endMBB is a successor of both offsetMBB and overflowMBB
20604 offsetMBB->addSuccessor(endMBB);
20605 overflowMBB->addSuccessor(endMBB);
20607 // Load the offset value into a register
20608 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20609 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20613 .addDisp(Disp, UseFPOffset ? 4 : 0)
20614 .addOperand(Segment)
20615 .setMemRefs(MMOBegin, MMOEnd);
20617 // Check if there is enough room left to pull this argument.
20618 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20620 .addImm(MaxOffset + 8 - ArgSizeA8);
20622 // Branch to "overflowMBB" if offset >= max
20623 // Fall through to "offsetMBB" otherwise
20624 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20625 .addMBB(overflowMBB);
20628 // In offsetMBB, emit code to use the reg_save_area.
20630 assert(OffsetReg != 0);
20632 // Read the reg_save_area address.
20633 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20634 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20639 .addOperand(Segment)
20640 .setMemRefs(MMOBegin, MMOEnd);
20642 // Zero-extend the offset
20643 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20644 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20647 .addImm(X86::sub_32bit);
20649 // Add the offset to the reg_save_area to get the final address.
20650 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20651 .addReg(OffsetReg64)
20652 .addReg(RegSaveReg);
20654 // Compute the offset for the next argument
20655 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20656 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20658 .addImm(UseFPOffset ? 16 : 8);
20660 // Store it back into the va_list.
20661 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20665 .addDisp(Disp, UseFPOffset ? 4 : 0)
20666 .addOperand(Segment)
20667 .addReg(NextOffsetReg)
20668 .setMemRefs(MMOBegin, MMOEnd);
20671 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20676 // Emit code to use overflow area
20679 // Load the overflow_area address into a register.
20680 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20681 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20686 .addOperand(Segment)
20687 .setMemRefs(MMOBegin, MMOEnd);
20689 // If we need to align it, do so. Otherwise, just copy the address
20690 // to OverflowDestReg.
20692 // Align the overflow address
20693 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20694 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20696 // aligned_addr = (addr + (align-1)) & ~(align-1)
20697 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20698 .addReg(OverflowAddrReg)
20701 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20703 .addImm(~(uint64_t)(Align-1));
20705 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20706 .addReg(OverflowAddrReg);
20709 // Compute the next overflow address after this argument.
20710 // (the overflow address should be kept 8-byte aligned)
20711 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20712 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20713 .addReg(OverflowDestReg)
20714 .addImm(ArgSizeA8);
20716 // Store the new overflow address.
20717 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20722 .addOperand(Segment)
20723 .addReg(NextAddrReg)
20724 .setMemRefs(MMOBegin, MMOEnd);
20726 // If we branched, emit the PHI to the front of endMBB.
20728 BuildMI(*endMBB, endMBB->begin(), DL,
20729 TII->get(X86::PHI), DestReg)
20730 .addReg(OffsetDestReg).addMBB(offsetMBB)
20731 .addReg(OverflowDestReg).addMBB(overflowMBB);
20734 // Erase the pseudo instruction
20735 MI->eraseFromParent();
20740 MachineBasicBlock *
20741 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20743 MachineBasicBlock *MBB) const {
20744 // Emit code to save XMM registers to the stack. The ABI says that the
20745 // number of registers to save is given in %al, so it's theoretically
20746 // possible to do an indirect jump trick to avoid saving all of them,
20747 // however this code takes a simpler approach and just executes all
20748 // of the stores if %al is non-zero. It's less code, and it's probably
20749 // easier on the hardware branch predictor, and stores aren't all that
20750 // expensive anyway.
20752 // Create the new basic blocks. One block contains all the XMM stores,
20753 // and one block is the final destination regardless of whether any
20754 // stores were performed.
20755 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20756 MachineFunction *F = MBB->getParent();
20757 MachineFunction::iterator MBBIter = MBB;
20759 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20760 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20761 F->insert(MBBIter, XMMSaveMBB);
20762 F->insert(MBBIter, EndMBB);
20764 // Transfer the remainder of MBB and its successor edges to EndMBB.
20765 EndMBB->splice(EndMBB->begin(), MBB,
20766 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20767 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20769 // The original block will now fall through to the XMM save block.
20770 MBB->addSuccessor(XMMSaveMBB);
20771 // The XMMSaveMBB will fall through to the end block.
20772 XMMSaveMBB->addSuccessor(EndMBB);
20774 // Now add the instructions.
20775 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20776 DebugLoc DL = MI->getDebugLoc();
20778 unsigned CountReg = MI->getOperand(0).getReg();
20779 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20780 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20782 if (!Subtarget->isTargetWin64()) {
20783 // If %al is 0, branch around the XMM save block.
20784 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20785 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20786 MBB->addSuccessor(EndMBB);
20789 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20790 // that was just emitted, but clearly shouldn't be "saved".
20791 assert((MI->getNumOperands() <= 3 ||
20792 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20793 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20794 && "Expected last argument to be EFLAGS");
20795 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20796 // In the XMM save block, save all the XMM argument registers.
20797 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20798 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20799 MachineMemOperand *MMO =
20800 F->getMachineMemOperand(
20801 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20802 MachineMemOperand::MOStore,
20803 /*Size=*/16, /*Align=*/16);
20804 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20805 .addFrameIndex(RegSaveFrameIndex)
20806 .addImm(/*Scale=*/1)
20807 .addReg(/*IndexReg=*/0)
20808 .addImm(/*Disp=*/Offset)
20809 .addReg(/*Segment=*/0)
20810 .addReg(MI->getOperand(i).getReg())
20811 .addMemOperand(MMO);
20814 MI->eraseFromParent(); // The pseudo instruction is gone now.
20819 // The EFLAGS operand of SelectItr might be missing a kill marker
20820 // because there were multiple uses of EFLAGS, and ISel didn't know
20821 // which to mark. Figure out whether SelectItr should have had a
20822 // kill marker, and set it if it should. Returns the correct kill
20824 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20825 MachineBasicBlock* BB,
20826 const TargetRegisterInfo* TRI) {
20827 // Scan forward through BB for a use/def of EFLAGS.
20828 MachineBasicBlock::iterator miI(std::next(SelectItr));
20829 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20830 const MachineInstr& mi = *miI;
20831 if (mi.readsRegister(X86::EFLAGS))
20833 if (mi.definesRegister(X86::EFLAGS))
20834 break; // Should have kill-flag - update below.
20837 // If we hit the end of the block, check whether EFLAGS is live into a
20839 if (miI == BB->end()) {
20840 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20841 sEnd = BB->succ_end();
20842 sItr != sEnd; ++sItr) {
20843 MachineBasicBlock* succ = *sItr;
20844 if (succ->isLiveIn(X86::EFLAGS))
20849 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20850 // out. SelectMI should have a kill flag on EFLAGS.
20851 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20855 MachineBasicBlock *
20856 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20857 MachineBasicBlock *BB) const {
20858 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20859 DebugLoc DL = MI->getDebugLoc();
20861 // To "insert" a SELECT_CC instruction, we actually have to insert the
20862 // diamond control-flow pattern. The incoming instruction knows the
20863 // destination vreg to set, the condition code register to branch on, the
20864 // true/false values to select between, and a branch opcode to use.
20865 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20866 MachineFunction::iterator It = BB;
20872 // cmpTY ccX, r1, r2
20874 // fallthrough --> copy0MBB
20875 MachineBasicBlock *thisMBB = BB;
20876 MachineFunction *F = BB->getParent();
20877 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20878 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20879 F->insert(It, copy0MBB);
20880 F->insert(It, sinkMBB);
20882 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20883 // live into the sink and copy blocks.
20884 const TargetRegisterInfo *TRI =
20885 BB->getParent()->getSubtarget().getRegisterInfo();
20886 if (!MI->killsRegister(X86::EFLAGS) &&
20887 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20888 copy0MBB->addLiveIn(X86::EFLAGS);
20889 sinkMBB->addLiveIn(X86::EFLAGS);
20892 // Transfer the remainder of BB and its successor edges to sinkMBB.
20893 sinkMBB->splice(sinkMBB->begin(), BB,
20894 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20895 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20897 // Add the true and fallthrough blocks as its successors.
20898 BB->addSuccessor(copy0MBB);
20899 BB->addSuccessor(sinkMBB);
20901 // Create the conditional branch instruction.
20903 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20904 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20907 // %FalseValue = ...
20908 // # fallthrough to sinkMBB
20909 copy0MBB->addSuccessor(sinkMBB);
20912 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20914 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20915 TII->get(X86::PHI), MI->getOperand(0).getReg())
20916 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20917 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20919 MI->eraseFromParent(); // The pseudo instruction is gone now.
20923 MachineBasicBlock *
20924 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20925 MachineBasicBlock *BB) const {
20926 MachineFunction *MF = BB->getParent();
20927 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20928 DebugLoc DL = MI->getDebugLoc();
20929 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20931 assert(MF->shouldSplitStack());
20933 const bool Is64Bit = Subtarget->is64Bit();
20934 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20936 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20937 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20940 // ... [Till the alloca]
20941 // If stacklet is not large enough, jump to mallocMBB
20944 // Allocate by subtracting from RSP
20945 // Jump to continueMBB
20948 // Allocate by call to runtime
20952 // [rest of original BB]
20955 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20956 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20957 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20959 MachineRegisterInfo &MRI = MF->getRegInfo();
20960 const TargetRegisterClass *AddrRegClass =
20961 getRegClassFor(getPointerTy());
20963 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20964 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20965 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20966 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20967 sizeVReg = MI->getOperand(1).getReg(),
20968 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20970 MachineFunction::iterator MBBIter = BB;
20973 MF->insert(MBBIter, bumpMBB);
20974 MF->insert(MBBIter, mallocMBB);
20975 MF->insert(MBBIter, continueMBB);
20977 continueMBB->splice(continueMBB->begin(), BB,
20978 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20979 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20981 // Add code to the main basic block to check if the stack limit has been hit,
20982 // and if so, jump to mallocMBB otherwise to bumpMBB.
20983 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20984 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20985 .addReg(tmpSPVReg).addReg(sizeVReg);
20986 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20987 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20988 .addReg(SPLimitVReg);
20989 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20991 // bumpMBB simply decreases the stack pointer, since we know the current
20992 // stacklet has enough space.
20993 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20994 .addReg(SPLimitVReg);
20995 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20996 .addReg(SPLimitVReg);
20997 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20999 // Calls into a routine in libgcc to allocate more space from the heap.
21000 const uint32_t *RegMask = MF->getTarget()
21001 .getSubtargetImpl()
21002 ->getRegisterInfo()
21003 ->getCallPreservedMask(CallingConv::C);
21005 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21007 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21008 .addExternalSymbol("__morestack_allocate_stack_space")
21009 .addRegMask(RegMask)
21010 .addReg(X86::RDI, RegState::Implicit)
21011 .addReg(X86::RAX, RegState::ImplicitDefine);
21012 } else if (Is64Bit) {
21013 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21015 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21016 .addExternalSymbol("__morestack_allocate_stack_space")
21017 .addRegMask(RegMask)
21018 .addReg(X86::EDI, RegState::Implicit)
21019 .addReg(X86::EAX, RegState::ImplicitDefine);
21021 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21023 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21024 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21025 .addExternalSymbol("__morestack_allocate_stack_space")
21026 .addRegMask(RegMask)
21027 .addReg(X86::EAX, RegState::ImplicitDefine);
21031 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21034 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21035 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21036 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21038 // Set up the CFG correctly.
21039 BB->addSuccessor(bumpMBB);
21040 BB->addSuccessor(mallocMBB);
21041 mallocMBB->addSuccessor(continueMBB);
21042 bumpMBB->addSuccessor(continueMBB);
21044 // Take care of the PHI nodes.
21045 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21046 MI->getOperand(0).getReg())
21047 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21048 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21050 // Delete the original pseudo instruction.
21051 MI->eraseFromParent();
21054 return continueMBB;
21057 MachineBasicBlock *
21058 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21059 MachineBasicBlock *BB) const {
21060 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
21061 DebugLoc DL = MI->getDebugLoc();
21063 assert(!Subtarget->isTargetMachO());
21065 // The lowering is pretty easy: we're just emitting the call to _alloca. The
21066 // non-trivial part is impdef of ESP.
21068 if (Subtarget->isTargetWin64()) {
21069 if (Subtarget->isTargetCygMing()) {
21070 // ___chkstk(Mingw64):
21071 // Clobbers R10, R11, RAX and EFLAGS.
21073 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
21074 .addExternalSymbol("___chkstk")
21075 .addReg(X86::RAX, RegState::Implicit)
21076 .addReg(X86::RSP, RegState::Implicit)
21077 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
21078 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
21079 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21081 // __chkstk(MSVCRT): does not update stack pointer.
21082 // Clobbers R10, R11 and EFLAGS.
21083 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
21084 .addExternalSymbol("__chkstk")
21085 .addReg(X86::RAX, RegState::Implicit)
21086 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21087 // RAX has the offset to be subtracted from RSP.
21088 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
21093 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
21094 Subtarget->isTargetWindowsItanium())
21098 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
21099 .addExternalSymbol(StackProbeSymbol)
21100 .addReg(X86::EAX, RegState::Implicit)
21101 .addReg(X86::ESP, RegState::Implicit)
21102 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
21103 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
21104 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21107 MI->eraseFromParent(); // The pseudo instruction is gone now.
21111 MachineBasicBlock *
21112 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21113 MachineBasicBlock *BB) const {
21114 // This is pretty easy. We're taking the value that we received from
21115 // our load from the relocation, sticking it in either RDI (x86-64)
21116 // or EAX and doing an indirect call. The return value will then
21117 // be in the normal return register.
21118 MachineFunction *F = BB->getParent();
21119 const X86InstrInfo *TII =
21120 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
21121 DebugLoc DL = MI->getDebugLoc();
21123 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21124 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21126 // Get a register mask for the lowered call.
21127 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21128 // proper register mask.
21129 const uint32_t *RegMask = F->getTarget()
21130 .getSubtargetImpl()
21131 ->getRegisterInfo()
21132 ->getCallPreservedMask(CallingConv::C);
21133 if (Subtarget->is64Bit()) {
21134 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21135 TII->get(X86::MOV64rm), X86::RDI)
21137 .addImm(0).addReg(0)
21138 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21139 MI->getOperand(3).getTargetFlags())
21141 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21142 addDirectMem(MIB, X86::RDI);
21143 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21144 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21145 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21146 TII->get(X86::MOV32rm), X86::EAX)
21148 .addImm(0).addReg(0)
21149 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21150 MI->getOperand(3).getTargetFlags())
21152 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21153 addDirectMem(MIB, X86::EAX);
21154 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21156 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21157 TII->get(X86::MOV32rm), X86::EAX)
21158 .addReg(TII->getGlobalBaseReg(F))
21159 .addImm(0).addReg(0)
21160 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21161 MI->getOperand(3).getTargetFlags())
21163 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21164 addDirectMem(MIB, X86::EAX);
21165 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21168 MI->eraseFromParent(); // The pseudo instruction is gone now.
21172 MachineBasicBlock *
21173 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21174 MachineBasicBlock *MBB) const {
21175 DebugLoc DL = MI->getDebugLoc();
21176 MachineFunction *MF = MBB->getParent();
21177 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21178 MachineRegisterInfo &MRI = MF->getRegInfo();
21180 const BasicBlock *BB = MBB->getBasicBlock();
21181 MachineFunction::iterator I = MBB;
21184 // Memory Reference
21185 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21186 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21189 unsigned MemOpndSlot = 0;
21191 unsigned CurOp = 0;
21193 DstReg = MI->getOperand(CurOp++).getReg();
21194 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21195 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21196 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21197 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21199 MemOpndSlot = CurOp;
21201 MVT PVT = getPointerTy();
21202 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21203 "Invalid Pointer Size!");
21205 // For v = setjmp(buf), we generate
21208 // buf[LabelOffset] = restoreMBB
21209 // SjLjSetup restoreMBB
21215 // v = phi(main, restore)
21218 // if base pointer being used, load it from frame
21221 MachineBasicBlock *thisMBB = MBB;
21222 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21223 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21224 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21225 MF->insert(I, mainMBB);
21226 MF->insert(I, sinkMBB);
21227 MF->push_back(restoreMBB);
21229 MachineInstrBuilder MIB;
21231 // Transfer the remainder of BB and its successor edges to sinkMBB.
21232 sinkMBB->splice(sinkMBB->begin(), MBB,
21233 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21234 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21237 unsigned PtrStoreOpc = 0;
21238 unsigned LabelReg = 0;
21239 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21240 Reloc::Model RM = MF->getTarget().getRelocationModel();
21241 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21242 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21244 // Prepare IP either in reg or imm.
21245 if (!UseImmLabel) {
21246 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21247 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21248 LabelReg = MRI.createVirtualRegister(PtrRC);
21249 if (Subtarget->is64Bit()) {
21250 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21254 .addMBB(restoreMBB)
21257 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21258 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21259 .addReg(XII->getGlobalBaseReg(MF))
21262 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21266 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21268 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21269 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21270 if (i == X86::AddrDisp)
21271 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21273 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21276 MIB.addReg(LabelReg);
21278 MIB.addMBB(restoreMBB);
21279 MIB.setMemRefs(MMOBegin, MMOEnd);
21281 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21282 .addMBB(restoreMBB);
21284 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21285 MF->getSubtarget().getRegisterInfo());
21286 MIB.addRegMask(RegInfo->getNoPreservedMask());
21287 thisMBB->addSuccessor(mainMBB);
21288 thisMBB->addSuccessor(restoreMBB);
21292 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21293 mainMBB->addSuccessor(sinkMBB);
21296 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21297 TII->get(X86::PHI), DstReg)
21298 .addReg(mainDstReg).addMBB(mainMBB)
21299 .addReg(restoreDstReg).addMBB(restoreMBB);
21302 if (RegInfo->hasBasePointer(*MF)) {
21303 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21304 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21305 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21306 X86FI->setRestoreBasePointer(MF);
21307 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21308 unsigned BasePtr = RegInfo->getBaseRegister();
21309 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21310 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21311 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21312 .setMIFlag(MachineInstr::FrameSetup);
21314 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21315 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21316 restoreMBB->addSuccessor(sinkMBB);
21318 MI->eraseFromParent();
21322 MachineBasicBlock *
21323 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21324 MachineBasicBlock *MBB) const {
21325 DebugLoc DL = MI->getDebugLoc();
21326 MachineFunction *MF = MBB->getParent();
21327 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21328 MachineRegisterInfo &MRI = MF->getRegInfo();
21330 // Memory Reference
21331 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21332 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21334 MVT PVT = getPointerTy();
21335 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21336 "Invalid Pointer Size!");
21338 const TargetRegisterClass *RC =
21339 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21340 unsigned Tmp = MRI.createVirtualRegister(RC);
21341 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21342 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21343 MF->getSubtarget().getRegisterInfo());
21344 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21345 unsigned SP = RegInfo->getStackRegister();
21347 MachineInstrBuilder MIB;
21349 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21350 const int64_t SPOffset = 2 * PVT.getStoreSize();
21352 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21353 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21356 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21357 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21358 MIB.addOperand(MI->getOperand(i));
21359 MIB.setMemRefs(MMOBegin, MMOEnd);
21361 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21362 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21363 if (i == X86::AddrDisp)
21364 MIB.addDisp(MI->getOperand(i), LabelOffset);
21366 MIB.addOperand(MI->getOperand(i));
21368 MIB.setMemRefs(MMOBegin, MMOEnd);
21370 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21371 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21372 if (i == X86::AddrDisp)
21373 MIB.addDisp(MI->getOperand(i), SPOffset);
21375 MIB.addOperand(MI->getOperand(i));
21377 MIB.setMemRefs(MMOBegin, MMOEnd);
21379 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21381 MI->eraseFromParent();
21385 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21386 // accumulator loops. Writing back to the accumulator allows the coalescer
21387 // to remove extra copies in the loop.
21388 MachineBasicBlock *
21389 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21390 MachineBasicBlock *MBB) const {
21391 MachineOperand &AddendOp = MI->getOperand(3);
21393 // Bail out early if the addend isn't a register - we can't switch these.
21394 if (!AddendOp.isReg())
21397 MachineFunction &MF = *MBB->getParent();
21398 MachineRegisterInfo &MRI = MF.getRegInfo();
21400 // Check whether the addend is defined by a PHI:
21401 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21402 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21403 if (!AddendDef.isPHI())
21406 // Look for the following pattern:
21408 // %addend = phi [%entry, 0], [%loop, %result]
21410 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21414 // %addend = phi [%entry, 0], [%loop, %result]
21416 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21418 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21419 assert(AddendDef.getOperand(i).isReg());
21420 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21421 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21422 if (&PHISrcInst == MI) {
21423 // Found a matching instruction.
21424 unsigned NewFMAOpc = 0;
21425 switch (MI->getOpcode()) {
21426 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21427 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21428 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21429 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21430 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21431 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21432 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21433 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21434 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21435 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21436 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21437 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21438 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21439 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21440 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21441 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21442 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21443 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21444 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21445 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21447 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21448 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21449 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21450 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21451 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21452 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21453 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21454 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21455 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21456 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21457 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21458 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21459 default: llvm_unreachable("Unrecognized FMA variant.");
21462 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21463 MachineInstrBuilder MIB =
21464 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21465 .addOperand(MI->getOperand(0))
21466 .addOperand(MI->getOperand(3))
21467 .addOperand(MI->getOperand(2))
21468 .addOperand(MI->getOperand(1));
21469 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21470 MI->eraseFromParent();
21477 MachineBasicBlock *
21478 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21479 MachineBasicBlock *BB) const {
21480 switch (MI->getOpcode()) {
21481 default: llvm_unreachable("Unexpected instr type to insert");
21482 case X86::TAILJMPd64:
21483 case X86::TAILJMPr64:
21484 case X86::TAILJMPm64:
21485 llvm_unreachable("TAILJMP64 would not be touched here.");
21486 case X86::TCRETURNdi64:
21487 case X86::TCRETURNri64:
21488 case X86::TCRETURNmi64:
21490 case X86::WIN_ALLOCA:
21491 return EmitLoweredWinAlloca(MI, BB);
21492 case X86::SEG_ALLOCA_32:
21493 case X86::SEG_ALLOCA_64:
21494 return EmitLoweredSegAlloca(MI, BB);
21495 case X86::TLSCall_32:
21496 case X86::TLSCall_64:
21497 return EmitLoweredTLSCall(MI, BB);
21498 case X86::CMOV_GR8:
21499 case X86::CMOV_FR32:
21500 case X86::CMOV_FR64:
21501 case X86::CMOV_V4F32:
21502 case X86::CMOV_V2F64:
21503 case X86::CMOV_V2I64:
21504 case X86::CMOV_V8F32:
21505 case X86::CMOV_V4F64:
21506 case X86::CMOV_V4I64:
21507 case X86::CMOV_V16F32:
21508 case X86::CMOV_V8F64:
21509 case X86::CMOV_V8I64:
21510 case X86::CMOV_GR16:
21511 case X86::CMOV_GR32:
21512 case X86::CMOV_RFP32:
21513 case X86::CMOV_RFP64:
21514 case X86::CMOV_RFP80:
21515 return EmitLoweredSelect(MI, BB);
21517 case X86::FP32_TO_INT16_IN_MEM:
21518 case X86::FP32_TO_INT32_IN_MEM:
21519 case X86::FP32_TO_INT64_IN_MEM:
21520 case X86::FP64_TO_INT16_IN_MEM:
21521 case X86::FP64_TO_INT32_IN_MEM:
21522 case X86::FP64_TO_INT64_IN_MEM:
21523 case X86::FP80_TO_INT16_IN_MEM:
21524 case X86::FP80_TO_INT32_IN_MEM:
21525 case X86::FP80_TO_INT64_IN_MEM: {
21526 MachineFunction *F = BB->getParent();
21527 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21528 DebugLoc DL = MI->getDebugLoc();
21530 // Change the floating point control register to use "round towards zero"
21531 // mode when truncating to an integer value.
21532 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21533 addFrameReference(BuildMI(*BB, MI, DL,
21534 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21536 // Load the old value of the high byte of the control word...
21538 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21539 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21542 // Set the high part to be round to zero...
21543 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21546 // Reload the modified control word now...
21547 addFrameReference(BuildMI(*BB, MI, DL,
21548 TII->get(X86::FLDCW16m)), CWFrameIdx);
21550 // Restore the memory image of control word to original value
21551 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21554 // Get the X86 opcode to use.
21556 switch (MI->getOpcode()) {
21557 default: llvm_unreachable("illegal opcode!");
21558 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21559 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21560 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21561 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21562 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21563 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21564 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21565 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21566 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21570 MachineOperand &Op = MI->getOperand(0);
21572 AM.BaseType = X86AddressMode::RegBase;
21573 AM.Base.Reg = Op.getReg();
21575 AM.BaseType = X86AddressMode::FrameIndexBase;
21576 AM.Base.FrameIndex = Op.getIndex();
21578 Op = MI->getOperand(1);
21580 AM.Scale = Op.getImm();
21581 Op = MI->getOperand(2);
21583 AM.IndexReg = Op.getImm();
21584 Op = MI->getOperand(3);
21585 if (Op.isGlobal()) {
21586 AM.GV = Op.getGlobal();
21588 AM.Disp = Op.getImm();
21590 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21591 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21593 // Reload the original control word now.
21594 addFrameReference(BuildMI(*BB, MI, DL,
21595 TII->get(X86::FLDCW16m)), CWFrameIdx);
21597 MI->eraseFromParent(); // The pseudo instruction is gone now.
21600 // String/text processing lowering.
21601 case X86::PCMPISTRM128REG:
21602 case X86::VPCMPISTRM128REG:
21603 case X86::PCMPISTRM128MEM:
21604 case X86::VPCMPISTRM128MEM:
21605 case X86::PCMPESTRM128REG:
21606 case X86::VPCMPESTRM128REG:
21607 case X86::PCMPESTRM128MEM:
21608 case X86::VPCMPESTRM128MEM:
21609 assert(Subtarget->hasSSE42() &&
21610 "Target must have SSE4.2 or AVX features enabled");
21611 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21613 // String/text processing lowering.
21614 case X86::PCMPISTRIREG:
21615 case X86::VPCMPISTRIREG:
21616 case X86::PCMPISTRIMEM:
21617 case X86::VPCMPISTRIMEM:
21618 case X86::PCMPESTRIREG:
21619 case X86::VPCMPESTRIREG:
21620 case X86::PCMPESTRIMEM:
21621 case X86::VPCMPESTRIMEM:
21622 assert(Subtarget->hasSSE42() &&
21623 "Target must have SSE4.2 or AVX features enabled");
21624 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21626 // Thread synchronization.
21628 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21633 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21635 case X86::VASTART_SAVE_XMM_REGS:
21636 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21638 case X86::VAARG_64:
21639 return EmitVAARG64WithCustomInserter(MI, BB);
21641 case X86::EH_SjLj_SetJmp32:
21642 case X86::EH_SjLj_SetJmp64:
21643 return emitEHSjLjSetJmp(MI, BB);
21645 case X86::EH_SjLj_LongJmp32:
21646 case X86::EH_SjLj_LongJmp64:
21647 return emitEHSjLjLongJmp(MI, BB);
21649 case TargetOpcode::STATEPOINT:
21650 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21651 // this point in the process. We diverge later.
21652 return emitPatchPoint(MI, BB);
21654 case TargetOpcode::STACKMAP:
21655 case TargetOpcode::PATCHPOINT:
21656 return emitPatchPoint(MI, BB);
21658 case X86::VFMADDPDr213r:
21659 case X86::VFMADDPSr213r:
21660 case X86::VFMADDSDr213r:
21661 case X86::VFMADDSSr213r:
21662 case X86::VFMSUBPDr213r:
21663 case X86::VFMSUBPSr213r:
21664 case X86::VFMSUBSDr213r:
21665 case X86::VFMSUBSSr213r:
21666 case X86::VFNMADDPDr213r:
21667 case X86::VFNMADDPSr213r:
21668 case X86::VFNMADDSDr213r:
21669 case X86::VFNMADDSSr213r:
21670 case X86::VFNMSUBPDr213r:
21671 case X86::VFNMSUBPSr213r:
21672 case X86::VFNMSUBSDr213r:
21673 case X86::VFNMSUBSSr213r:
21674 case X86::VFMADDSUBPDr213r:
21675 case X86::VFMADDSUBPSr213r:
21676 case X86::VFMSUBADDPDr213r:
21677 case X86::VFMSUBADDPSr213r:
21678 case X86::VFMADDPDr213rY:
21679 case X86::VFMADDPSr213rY:
21680 case X86::VFMSUBPDr213rY:
21681 case X86::VFMSUBPSr213rY:
21682 case X86::VFNMADDPDr213rY:
21683 case X86::VFNMADDPSr213rY:
21684 case X86::VFNMSUBPDr213rY:
21685 case X86::VFNMSUBPSr213rY:
21686 case X86::VFMADDSUBPDr213rY:
21687 case X86::VFMADDSUBPSr213rY:
21688 case X86::VFMSUBADDPDr213rY:
21689 case X86::VFMSUBADDPSr213rY:
21690 return emitFMA3Instr(MI, BB);
21694 //===----------------------------------------------------------------------===//
21695 // X86 Optimization Hooks
21696 //===----------------------------------------------------------------------===//
21698 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21701 const SelectionDAG &DAG,
21702 unsigned Depth) const {
21703 unsigned BitWidth = KnownZero.getBitWidth();
21704 unsigned Opc = Op.getOpcode();
21705 assert((Opc >= ISD::BUILTIN_OP_END ||
21706 Opc == ISD::INTRINSIC_WO_CHAIN ||
21707 Opc == ISD::INTRINSIC_W_CHAIN ||
21708 Opc == ISD::INTRINSIC_VOID) &&
21709 "Should use MaskedValueIsZero if you don't know whether Op"
21710 " is a target node!");
21712 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21726 // These nodes' second result is a boolean.
21727 if (Op.getResNo() == 0)
21730 case X86ISD::SETCC:
21731 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21733 case ISD::INTRINSIC_WO_CHAIN: {
21734 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21735 unsigned NumLoBits = 0;
21738 case Intrinsic::x86_sse_movmsk_ps:
21739 case Intrinsic::x86_avx_movmsk_ps_256:
21740 case Intrinsic::x86_sse2_movmsk_pd:
21741 case Intrinsic::x86_avx_movmsk_pd_256:
21742 case Intrinsic::x86_mmx_pmovmskb:
21743 case Intrinsic::x86_sse2_pmovmskb_128:
21744 case Intrinsic::x86_avx2_pmovmskb: {
21745 // High bits of movmskp{s|d}, pmovmskb are known zero.
21747 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21748 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21749 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21750 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21751 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21752 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21753 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21754 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21756 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21765 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21767 const SelectionDAG &,
21768 unsigned Depth) const {
21769 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21770 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21771 return Op.getValueType().getScalarType().getSizeInBits();
21777 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21778 /// node is a GlobalAddress + offset.
21779 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21780 const GlobalValue* &GA,
21781 int64_t &Offset) const {
21782 if (N->getOpcode() == X86ISD::Wrapper) {
21783 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21784 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21785 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21789 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21792 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21793 /// same as extracting the high 128-bit part of 256-bit vector and then
21794 /// inserting the result into the low part of a new 256-bit vector
21795 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21796 EVT VT = SVOp->getValueType(0);
21797 unsigned NumElems = VT.getVectorNumElements();
21799 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21800 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21801 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21802 SVOp->getMaskElt(j) >= 0)
21808 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21809 /// same as extracting the low 128-bit part of 256-bit vector and then
21810 /// inserting the result into the high part of a new 256-bit vector
21811 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21812 EVT VT = SVOp->getValueType(0);
21813 unsigned NumElems = VT.getVectorNumElements();
21815 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21816 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21817 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21818 SVOp->getMaskElt(j) >= 0)
21824 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21825 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21826 TargetLowering::DAGCombinerInfo &DCI,
21827 const X86Subtarget* Subtarget) {
21829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21830 SDValue V1 = SVOp->getOperand(0);
21831 SDValue V2 = SVOp->getOperand(1);
21832 EVT VT = SVOp->getValueType(0);
21833 unsigned NumElems = VT.getVectorNumElements();
21835 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21836 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21840 // V UNDEF BUILD_VECTOR UNDEF
21842 // CONCAT_VECTOR CONCAT_VECTOR
21845 // RESULT: V + zero extended
21847 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21848 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21849 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21852 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21855 // To match the shuffle mask, the first half of the mask should
21856 // be exactly the first vector, and all the rest a splat with the
21857 // first element of the second one.
21858 for (unsigned i = 0; i != NumElems/2; ++i)
21859 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21860 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21863 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21864 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21865 if (Ld->hasNUsesOfValue(1, 0)) {
21866 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21867 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21869 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21871 Ld->getPointerInfo(),
21872 Ld->getAlignment(),
21873 false/*isVolatile*/, true/*ReadMem*/,
21874 false/*WriteMem*/);
21876 // Make sure the newly-created LOAD is in the same position as Ld in
21877 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21878 // and update uses of Ld's output chain to use the TokenFactor.
21879 if (Ld->hasAnyUseOfValue(1)) {
21880 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21881 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21882 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21883 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21884 SDValue(ResNode.getNode(), 1));
21887 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21891 // Emit a zeroed vector and insert the desired subvector on its
21893 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21894 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21895 return DCI.CombineTo(N, InsV);
21898 //===--------------------------------------------------------------------===//
21899 // Combine some shuffles into subvector extracts and inserts:
21902 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21903 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21904 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21905 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21906 return DCI.CombineTo(N, InsV);
21909 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21910 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21911 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21912 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21913 return DCI.CombineTo(N, InsV);
21919 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21922 /// This is the leaf of the recursive combinine below. When we have found some
21923 /// chain of single-use x86 shuffle instructions and accumulated the combined
21924 /// shuffle mask represented by them, this will try to pattern match that mask
21925 /// into either a single instruction if there is a special purpose instruction
21926 /// for this operation, or into a PSHUFB instruction which is a fully general
21927 /// instruction but should only be used to replace chains over a certain depth.
21928 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21929 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21930 TargetLowering::DAGCombinerInfo &DCI,
21931 const X86Subtarget *Subtarget) {
21932 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21934 // Find the operand that enters the chain. Note that multiple uses are OK
21935 // here, we're not going to remove the operand we find.
21936 SDValue Input = Op.getOperand(0);
21937 while (Input.getOpcode() == ISD::BITCAST)
21938 Input = Input.getOperand(0);
21940 MVT VT = Input.getSimpleValueType();
21941 MVT RootVT = Root.getSimpleValueType();
21944 // Just remove no-op shuffle masks.
21945 if (Mask.size() == 1) {
21946 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21951 // Use the float domain if the operand type is a floating point type.
21952 bool FloatDomain = VT.isFloatingPoint();
21954 // For floating point shuffles, we don't have free copies in the shuffle
21955 // instructions or the ability to load as part of the instruction, so
21956 // canonicalize their shuffles to UNPCK or MOV variants.
21958 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21959 // vectors because it can have a load folded into it that UNPCK cannot. This
21960 // doesn't preclude something switching to the shorter encoding post-RA.
21962 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21963 bool Lo = Mask.equals(0, 0);
21966 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21967 // is no slower than UNPCKLPD but has the option to fold the input operand
21968 // into even an unaligned memory load.
21969 if (Lo && Subtarget->hasSSE3()) {
21970 Shuffle = X86ISD::MOVDDUP;
21971 ShuffleVT = MVT::v2f64;
21973 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21974 // than the UNPCK variants.
21975 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21976 ShuffleVT = MVT::v4f32;
21978 if (Depth == 1 && Root->getOpcode() == Shuffle)
21979 return false; // Nothing to do!
21980 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21981 DCI.AddToWorklist(Op.getNode());
21982 if (Shuffle == X86ISD::MOVDDUP)
21983 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21985 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21986 DCI.AddToWorklist(Op.getNode());
21987 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21991 if (Subtarget->hasSSE3() &&
21992 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21993 bool Lo = Mask.equals(0, 0, 2, 2);
21994 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21995 MVT ShuffleVT = MVT::v4f32;
21996 if (Depth == 1 && Root->getOpcode() == Shuffle)
21997 return false; // Nothing to do!
21998 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21999 DCI.AddToWorklist(Op.getNode());
22000 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22001 DCI.AddToWorklist(Op.getNode());
22002 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
22006 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
22007 bool Lo = Mask.equals(0, 0, 1, 1);
22008 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22009 MVT ShuffleVT = MVT::v4f32;
22010 if (Depth == 1 && Root->getOpcode() == Shuffle)
22011 return false; // Nothing to do!
22012 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
22013 DCI.AddToWorklist(Op.getNode());
22014 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22015 DCI.AddToWorklist(Op.getNode());
22016 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
22022 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22023 // variants as none of these have single-instruction variants that are
22024 // superior to the UNPCK formulation.
22025 if (!FloatDomain &&
22026 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
22027 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
22028 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
22029 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
22031 bool Lo = Mask[0] == 0;
22032 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22033 if (Depth == 1 && Root->getOpcode() == Shuffle)
22034 return false; // Nothing to do!
22036 switch (Mask.size()) {
22038 ShuffleVT = MVT::v8i16;
22041 ShuffleVT = MVT::v16i8;
22044 llvm_unreachable("Impossible mask size!");
22046 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
22047 DCI.AddToWorklist(Op.getNode());
22048 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22049 DCI.AddToWorklist(Op.getNode());
22050 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
22055 // Don't try to re-form single instruction chains under any circumstances now
22056 // that we've done encoding canonicalization for them.
22060 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22061 // can replace them with a single PSHUFB instruction profitably. Intel's
22062 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22063 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22064 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22065 SmallVector<SDValue, 16> PSHUFBMask;
22066 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
22067 int Ratio = 16 / Mask.size();
22068 for (unsigned i = 0; i < 16; ++i) {
22069 if (Mask[i / Ratio] == SM_SentinelUndef) {
22070 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22073 int M = Mask[i / Ratio] != SM_SentinelZero
22074 ? Ratio * Mask[i / Ratio] + i % Ratio
22076 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
22078 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
22079 DCI.AddToWorklist(Op.getNode());
22080 SDValue PSHUFBMaskOp =
22081 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
22082 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22083 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
22084 DCI.AddToWorklist(Op.getNode());
22085 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
22090 // Failed to find any combines.
22094 /// \brief Fully generic combining of x86 shuffle instructions.
22096 /// This should be the last combine run over the x86 shuffle instructions. Once
22097 /// they have been fully optimized, this will recursively consider all chains
22098 /// of single-use shuffle instructions, build a generic model of the cumulative
22099 /// shuffle operation, and check for simpler instructions which implement this
22100 /// operation. We use this primarily for two purposes:
22102 /// 1) Collapse generic shuffles to specialized single instructions when
22103 /// equivalent. In most cases, this is just an encoding size win, but
22104 /// sometimes we will collapse multiple generic shuffles into a single
22105 /// special-purpose shuffle.
22106 /// 2) Look for sequences of shuffle instructions with 3 or more total
22107 /// instructions, and replace them with the slightly more expensive SSSE3
22108 /// PSHUFB instruction if available. We do this as the last combining step
22109 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22110 /// a suitable short sequence of other instructions. The PHUFB will either
22111 /// use a register or have to read from memory and so is slightly (but only
22112 /// slightly) more expensive than the other shuffle instructions.
22114 /// Because this is inherently a quadratic operation (for each shuffle in
22115 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22116 /// This should never be an issue in practice as the shuffle lowering doesn't
22117 /// produce sequences of more than 8 instructions.
22119 /// FIXME: We will currently miss some cases where the redundant shuffling
22120 /// would simplify under the threshold for PSHUFB formation because of
22121 /// combine-ordering. To fix this, we should do the redundant instruction
22122 /// combining in this recursive walk.
22123 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22124 ArrayRef<int> RootMask,
22125 int Depth, bool HasPSHUFB,
22127 TargetLowering::DAGCombinerInfo &DCI,
22128 const X86Subtarget *Subtarget) {
22129 // Bound the depth of our recursive combine because this is ultimately
22130 // quadratic in nature.
22134 // Directly rip through bitcasts to find the underlying operand.
22135 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22136 Op = Op.getOperand(0);
22138 MVT VT = Op.getSimpleValueType();
22139 if (!VT.isVector())
22140 return false; // Bail if we hit a non-vector.
22141 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22142 // version should be added.
22143 if (VT.getSizeInBits() != 128)
22146 assert(Root.getSimpleValueType().isVector() &&
22147 "Shuffles operate on vector types!");
22148 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22149 "Can only combine shuffles of the same vector register size.");
22151 if (!isTargetShuffle(Op.getOpcode()))
22153 SmallVector<int, 16> OpMask;
22155 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22156 // We only can combine unary shuffles which we can decode the mask for.
22157 if (!HaveMask || !IsUnary)
22160 assert(VT.getVectorNumElements() == OpMask.size() &&
22161 "Different mask size from vector size!");
22162 assert(((RootMask.size() > OpMask.size() &&
22163 RootMask.size() % OpMask.size() == 0) ||
22164 (OpMask.size() > RootMask.size() &&
22165 OpMask.size() % RootMask.size() == 0) ||
22166 OpMask.size() == RootMask.size()) &&
22167 "The smaller number of elements must divide the larger.");
22168 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22169 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22170 assert(((RootRatio == 1 && OpRatio == 1) ||
22171 (RootRatio == 1) != (OpRatio == 1)) &&
22172 "Must not have a ratio for both incoming and op masks!");
22174 SmallVector<int, 16> Mask;
22175 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22177 // Merge this shuffle operation's mask into our accumulated mask. Note that
22178 // this shuffle's mask will be the first applied to the input, followed by the
22179 // root mask to get us all the way to the root value arrangement. The reason
22180 // for this order is that we are recursing up the operation chain.
22181 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22182 int RootIdx = i / RootRatio;
22183 if (RootMask[RootIdx] < 0) {
22184 // This is a zero or undef lane, we're done.
22185 Mask.push_back(RootMask[RootIdx]);
22189 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22190 int OpIdx = RootMaskedIdx / OpRatio;
22191 if (OpMask[OpIdx] < 0) {
22192 // The incoming lanes are zero or undef, it doesn't matter which ones we
22194 Mask.push_back(OpMask[OpIdx]);
22198 // Ok, we have non-zero lanes, map them through.
22199 Mask.push_back(OpMask[OpIdx] * OpRatio +
22200 RootMaskedIdx % OpRatio);
22203 // See if we can recurse into the operand to combine more things.
22204 switch (Op.getOpcode()) {
22205 case X86ISD::PSHUFB:
22207 case X86ISD::PSHUFD:
22208 case X86ISD::PSHUFHW:
22209 case X86ISD::PSHUFLW:
22210 if (Op.getOperand(0).hasOneUse() &&
22211 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22212 HasPSHUFB, DAG, DCI, Subtarget))
22216 case X86ISD::UNPCKL:
22217 case X86ISD::UNPCKH:
22218 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22219 // We can't check for single use, we have to check that this shuffle is the only user.
22220 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22221 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22222 HasPSHUFB, DAG, DCI, Subtarget))
22227 // Minor canonicalization of the accumulated shuffle mask to make it easier
22228 // to match below. All this does is detect masks with squential pairs of
22229 // elements, and shrink them to the half-width mask. It does this in a loop
22230 // so it will reduce the size of the mask to the minimal width mask which
22231 // performs an equivalent shuffle.
22232 SmallVector<int, 16> WidenedMask;
22233 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22234 Mask = std::move(WidenedMask);
22235 WidenedMask.clear();
22238 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22242 /// \brief Get the PSHUF-style mask from PSHUF node.
22244 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22245 /// PSHUF-style masks that can be reused with such instructions.
22246 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22247 SmallVector<int, 4> Mask;
22249 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22253 switch (N.getOpcode()) {
22254 case X86ISD::PSHUFD:
22256 case X86ISD::PSHUFLW:
22259 case X86ISD::PSHUFHW:
22260 Mask.erase(Mask.begin(), Mask.begin() + 4);
22261 for (int &M : Mask)
22265 llvm_unreachable("No valid shuffle instruction found!");
22269 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22271 /// We walk up the chain and look for a combinable shuffle, skipping over
22272 /// shuffles that we could hoist this shuffle's transformation past without
22273 /// altering anything.
22275 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22277 TargetLowering::DAGCombinerInfo &DCI) {
22278 assert(N.getOpcode() == X86ISD::PSHUFD &&
22279 "Called with something other than an x86 128-bit half shuffle!");
22282 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22283 // of the shuffles in the chain so that we can form a fresh chain to replace
22285 SmallVector<SDValue, 8> Chain;
22286 SDValue V = N.getOperand(0);
22287 for (; V.hasOneUse(); V = V.getOperand(0)) {
22288 switch (V.getOpcode()) {
22290 return SDValue(); // Nothing combined!
22293 // Skip bitcasts as we always know the type for the target specific
22297 case X86ISD::PSHUFD:
22298 // Found another dword shuffle.
22301 case X86ISD::PSHUFLW:
22302 // Check that the low words (being shuffled) are the identity in the
22303 // dword shuffle, and the high words are self-contained.
22304 if (Mask[0] != 0 || Mask[1] != 1 ||
22305 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22308 Chain.push_back(V);
22311 case X86ISD::PSHUFHW:
22312 // Check that the high words (being shuffled) are the identity in the
22313 // dword shuffle, and the low words are self-contained.
22314 if (Mask[2] != 2 || Mask[3] != 3 ||
22315 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22318 Chain.push_back(V);
22321 case X86ISD::UNPCKL:
22322 case X86ISD::UNPCKH:
22323 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22324 // shuffle into a preceding word shuffle.
22325 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22328 // Search for a half-shuffle which we can combine with.
22329 unsigned CombineOp =
22330 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22331 if (V.getOperand(0) != V.getOperand(1) ||
22332 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22334 Chain.push_back(V);
22335 V = V.getOperand(0);
22337 switch (V.getOpcode()) {
22339 return SDValue(); // Nothing to combine.
22341 case X86ISD::PSHUFLW:
22342 case X86ISD::PSHUFHW:
22343 if (V.getOpcode() == CombineOp)
22346 Chain.push_back(V);
22350 V = V.getOperand(0);
22354 } while (V.hasOneUse());
22357 // Break out of the loop if we break out of the switch.
22361 if (!V.hasOneUse())
22362 // We fell out of the loop without finding a viable combining instruction.
22365 // Merge this node's mask and our incoming mask.
22366 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22367 for (int &M : Mask)
22369 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22370 getV4X86ShuffleImm8ForMask(Mask, DAG));
22372 // Rebuild the chain around this new shuffle.
22373 while (!Chain.empty()) {
22374 SDValue W = Chain.pop_back_val();
22376 if (V.getValueType() != W.getOperand(0).getValueType())
22377 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22379 switch (W.getOpcode()) {
22381 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22383 case X86ISD::UNPCKL:
22384 case X86ISD::UNPCKH:
22385 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22388 case X86ISD::PSHUFD:
22389 case X86ISD::PSHUFLW:
22390 case X86ISD::PSHUFHW:
22391 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22395 if (V.getValueType() != N.getValueType())
22396 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22398 // Return the new chain to replace N.
22402 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22404 /// We walk up the chain, skipping shuffles of the other half and looking
22405 /// through shuffles which switch halves trying to find a shuffle of the same
22406 /// pair of dwords.
22407 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22409 TargetLowering::DAGCombinerInfo &DCI) {
22411 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22412 "Called with something other than an x86 128-bit half shuffle!");
22414 unsigned CombineOpcode = N.getOpcode();
22416 // Walk up a single-use chain looking for a combinable shuffle.
22417 SDValue V = N.getOperand(0);
22418 for (; V.hasOneUse(); V = V.getOperand(0)) {
22419 switch (V.getOpcode()) {
22421 return false; // Nothing combined!
22424 // Skip bitcasts as we always know the type for the target specific
22428 case X86ISD::PSHUFLW:
22429 case X86ISD::PSHUFHW:
22430 if (V.getOpcode() == CombineOpcode)
22433 // Other-half shuffles are no-ops.
22436 // Break out of the loop if we break out of the switch.
22440 if (!V.hasOneUse())
22441 // We fell out of the loop without finding a viable combining instruction.
22444 // Combine away the bottom node as its shuffle will be accumulated into
22445 // a preceding shuffle.
22446 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22448 // Record the old value.
22451 // Merge this node's mask and our incoming mask (adjusted to account for all
22452 // the pshufd instructions encountered).
22453 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22454 for (int &M : Mask)
22456 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22457 getV4X86ShuffleImm8ForMask(Mask, DAG));
22459 // Check that the shuffles didn't cancel each other out. If not, we need to
22460 // combine to the new one.
22462 // Replace the combinable shuffle with the combined one, updating all users
22463 // so that we re-evaluate the chain here.
22464 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22469 /// \brief Try to combine x86 target specific shuffles.
22470 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22471 TargetLowering::DAGCombinerInfo &DCI,
22472 const X86Subtarget *Subtarget) {
22474 MVT VT = N.getSimpleValueType();
22475 SmallVector<int, 4> Mask;
22477 switch (N.getOpcode()) {
22478 case X86ISD::PSHUFD:
22479 case X86ISD::PSHUFLW:
22480 case X86ISD::PSHUFHW:
22481 Mask = getPSHUFShuffleMask(N);
22482 assert(Mask.size() == 4);
22488 // Nuke no-op shuffles that show up after combining.
22489 if (isNoopShuffleMask(Mask))
22490 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22492 // Look for simplifications involving one or two shuffle instructions.
22493 SDValue V = N.getOperand(0);
22494 switch (N.getOpcode()) {
22497 case X86ISD::PSHUFLW:
22498 case X86ISD::PSHUFHW:
22499 assert(VT == MVT::v8i16);
22502 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22503 return SDValue(); // We combined away this shuffle, so we're done.
22505 // See if this reduces to a PSHUFD which is no more expensive and can
22506 // combine with more operations. Note that it has to at least flip the
22507 // dwords as otherwise it would have been removed as a no-op.
22508 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22509 int DMask[] = {0, 1, 2, 3};
22510 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22511 DMask[DOffset + 0] = DOffset + 1;
22512 DMask[DOffset + 1] = DOffset + 0;
22513 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22514 DCI.AddToWorklist(V.getNode());
22515 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22516 getV4X86ShuffleImm8ForMask(DMask, DAG));
22517 DCI.AddToWorklist(V.getNode());
22518 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22521 // Look for shuffle patterns which can be implemented as a single unpack.
22522 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22523 // only works when we have a PSHUFD followed by two half-shuffles.
22524 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22525 (V.getOpcode() == X86ISD::PSHUFLW ||
22526 V.getOpcode() == X86ISD::PSHUFHW) &&
22527 V.getOpcode() != N.getOpcode() &&
22529 SDValue D = V.getOperand(0);
22530 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22531 D = D.getOperand(0);
22532 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22533 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22534 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22535 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22536 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22538 for (int i = 0; i < 4; ++i) {
22539 WordMask[i + NOffset] = Mask[i] + NOffset;
22540 WordMask[i + VOffset] = VMask[i] + VOffset;
22542 // Map the word mask through the DWord mask.
22544 for (int i = 0; i < 8; ++i)
22545 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22546 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22547 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22548 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22549 std::begin(UnpackLoMask)) ||
22550 std::equal(std::begin(MappedMask), std::end(MappedMask),
22551 std::begin(UnpackHiMask))) {
22552 // We can replace all three shuffles with an unpack.
22553 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22554 DCI.AddToWorklist(V.getNode());
22555 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22557 DL, MVT::v8i16, V, V);
22564 case X86ISD::PSHUFD:
22565 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22574 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22576 /// We combine this directly on the abstract vector shuffle nodes so it is
22577 /// easier to generically match. We also insert dummy vector shuffle nodes for
22578 /// the operands which explicitly discard the lanes which are unused by this
22579 /// operation to try to flow through the rest of the combiner the fact that
22580 /// they're unused.
22581 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22583 EVT VT = N->getValueType(0);
22585 // We only handle target-independent shuffles.
22586 // FIXME: It would be easy and harmless to use the target shuffle mask
22587 // extraction tool to support more.
22588 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22591 auto *SVN = cast<ShuffleVectorSDNode>(N);
22592 ArrayRef<int> Mask = SVN->getMask();
22593 SDValue V1 = N->getOperand(0);
22594 SDValue V2 = N->getOperand(1);
22596 // We require the first shuffle operand to be the SUB node, and the second to
22597 // be the ADD node.
22598 // FIXME: We should support the commuted patterns.
22599 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22602 // If there are other uses of these operations we can't fold them.
22603 if (!V1->hasOneUse() || !V2->hasOneUse())
22606 // Ensure that both operations have the same operands. Note that we can
22607 // commute the FADD operands.
22608 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22609 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22610 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22613 // We're looking for blends between FADD and FSUB nodes. We insist on these
22614 // nodes being lined up in a specific expected pattern.
22615 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22616 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22617 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22620 // Only specific types are legal at this point, assert so we notice if and
22621 // when these change.
22622 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22623 VT == MVT::v4f64) &&
22624 "Unknown vector type encountered!");
22626 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22629 /// PerformShuffleCombine - Performs several different shuffle combines.
22630 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22631 TargetLowering::DAGCombinerInfo &DCI,
22632 const X86Subtarget *Subtarget) {
22634 SDValue N0 = N->getOperand(0);
22635 SDValue N1 = N->getOperand(1);
22636 EVT VT = N->getValueType(0);
22638 // Don't create instructions with illegal types after legalize types has run.
22639 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22640 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22643 // If we have legalized the vector types, look for blends of FADD and FSUB
22644 // nodes that we can fuse into an ADDSUB node.
22645 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22646 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22649 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22650 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22651 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22652 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22654 // During Type Legalization, when promoting illegal vector types,
22655 // the backend might introduce new shuffle dag nodes and bitcasts.
22657 // This code performs the following transformation:
22658 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22659 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22661 // We do this only if both the bitcast and the BINOP dag nodes have
22662 // one use. Also, perform this transformation only if the new binary
22663 // operation is legal. This is to avoid introducing dag nodes that
22664 // potentially need to be further expanded (or custom lowered) into a
22665 // less optimal sequence of dag nodes.
22666 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22667 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22668 N0.getOpcode() == ISD::BITCAST) {
22669 SDValue BC0 = N0.getOperand(0);
22670 EVT SVT = BC0.getValueType();
22671 unsigned Opcode = BC0.getOpcode();
22672 unsigned NumElts = VT.getVectorNumElements();
22674 if (BC0.hasOneUse() && SVT.isVector() &&
22675 SVT.getVectorNumElements() * 2 == NumElts &&
22676 TLI.isOperationLegal(Opcode, VT)) {
22677 bool CanFold = false;
22689 unsigned SVTNumElts = SVT.getVectorNumElements();
22690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22691 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22692 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22693 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22694 CanFold = SVOp->getMaskElt(i) < 0;
22697 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22698 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22699 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22700 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22705 // Only handle 128 wide vector from here on.
22706 if (!VT.is128BitVector())
22709 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22710 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22711 // consecutive, non-overlapping, and in the right order.
22712 SmallVector<SDValue, 16> Elts;
22713 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22714 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22716 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22720 if (isTargetShuffle(N->getOpcode())) {
22722 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22723 if (Shuffle.getNode())
22726 // Try recursively combining arbitrary sequences of x86 shuffle
22727 // instructions into higher-order shuffles. We do this after combining
22728 // specific PSHUF instruction sequences into their minimal form so that we
22729 // can evaluate how many specialized shuffle instructions are involved in
22730 // a particular chain.
22731 SmallVector<int, 1> NonceMask; // Just a placeholder.
22732 NonceMask.push_back(0);
22733 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22734 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22736 return SDValue(); // This routine will use CombineTo to replace N.
22742 /// PerformTruncateCombine - Converts truncate operation to
22743 /// a sequence of vector shuffle operations.
22744 /// It is possible when we truncate 256-bit vector to 128-bit vector
22745 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22746 TargetLowering::DAGCombinerInfo &DCI,
22747 const X86Subtarget *Subtarget) {
22751 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22752 /// specific shuffle of a load can be folded into a single element load.
22753 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22754 /// shuffles have been custom lowered so we need to handle those here.
22755 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22756 TargetLowering::DAGCombinerInfo &DCI) {
22757 if (DCI.isBeforeLegalizeOps())
22760 SDValue InVec = N->getOperand(0);
22761 SDValue EltNo = N->getOperand(1);
22763 if (!isa<ConstantSDNode>(EltNo))
22766 EVT OriginalVT = InVec.getValueType();
22768 if (InVec.getOpcode() == ISD::BITCAST) {
22769 // Don't duplicate a load with other uses.
22770 if (!InVec.hasOneUse())
22772 EVT BCVT = InVec.getOperand(0).getValueType();
22773 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22775 InVec = InVec.getOperand(0);
22778 EVT CurrentVT = InVec.getValueType();
22780 if (!isTargetShuffle(InVec.getOpcode()))
22783 // Don't duplicate a load with other uses.
22784 if (!InVec.hasOneUse())
22787 SmallVector<int, 16> ShuffleMask;
22789 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22790 ShuffleMask, UnaryShuffle))
22793 // Select the input vector, guarding against out of range extract vector.
22794 unsigned NumElems = CurrentVT.getVectorNumElements();
22795 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22796 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22797 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22798 : InVec.getOperand(1);
22800 // If inputs to shuffle are the same for both ops, then allow 2 uses
22801 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22802 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22804 if (LdNode.getOpcode() == ISD::BITCAST) {
22805 // Don't duplicate a load with other uses.
22806 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22809 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22810 LdNode = LdNode.getOperand(0);
22813 if (!ISD::isNormalLoad(LdNode.getNode()))
22816 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22818 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22821 EVT EltVT = N->getValueType(0);
22822 // If there's a bitcast before the shuffle, check if the load type and
22823 // alignment is valid.
22824 unsigned Align = LN0->getAlignment();
22825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22826 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22827 EltVT.getTypeForEVT(*DAG.getContext()));
22829 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22832 // All checks match so transform back to vector_shuffle so that DAG combiner
22833 // can finish the job
22836 // Create shuffle node taking into account the case that its a unary shuffle
22837 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22838 : InVec.getOperand(1);
22839 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22840 InVec.getOperand(0), Shuffle,
22842 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22843 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22847 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22848 /// generation and convert it from being a bunch of shuffles and extracts
22849 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22850 /// storing the value and loading scalars back, while for x64 we should
22851 /// use 64-bit extracts and shifts.
22852 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22853 TargetLowering::DAGCombinerInfo &DCI) {
22854 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22855 if (NewOp.getNode())
22858 SDValue InputVector = N->getOperand(0);
22860 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22861 // from mmx to v2i32 has a single usage.
22862 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22863 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22864 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22865 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22866 N->getValueType(0),
22867 InputVector.getNode()->getOperand(0));
22869 // Only operate on vectors of 4 elements, where the alternative shuffling
22870 // gets to be more expensive.
22871 if (InputVector.getValueType() != MVT::v4i32)
22874 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22875 // single use which is a sign-extend or zero-extend, and all elements are
22877 SmallVector<SDNode *, 4> Uses;
22878 unsigned ExtractedElements = 0;
22879 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22880 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22881 if (UI.getUse().getResNo() != InputVector.getResNo())
22884 SDNode *Extract = *UI;
22885 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22888 if (Extract->getValueType(0) != MVT::i32)
22890 if (!Extract->hasOneUse())
22892 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22893 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22895 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22898 // Record which element was extracted.
22899 ExtractedElements |=
22900 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22902 Uses.push_back(Extract);
22905 // If not all the elements were used, this may not be worthwhile.
22906 if (ExtractedElements != 15)
22909 // Ok, we've now decided to do the transformation.
22910 // If 64-bit shifts are legal, use the extract-shift sequence,
22911 // otherwise bounce the vector off the cache.
22912 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22914 SDLoc dl(InputVector);
22916 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22917 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22918 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22919 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22920 DAG.getConstant(0, VecIdxTy));
22921 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22922 DAG.getConstant(1, VecIdxTy));
22924 SDValue ShAmt = DAG.getConstant(32,
22925 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22926 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22927 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22928 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22929 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22930 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22931 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22933 // Store the value to a temporary stack slot.
22934 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22935 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22936 MachinePointerInfo(), false, false, 0);
22938 EVT ElementType = InputVector.getValueType().getVectorElementType();
22939 unsigned EltSize = ElementType.getSizeInBits() / 8;
22941 // Replace each use (extract) with a load of the appropriate element.
22942 for (unsigned i = 0; i < 4; ++i) {
22943 uint64_t Offset = EltSize * i;
22944 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22946 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22947 StackPtr, OffsetVal);
22949 // Load the scalar.
22950 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22951 ScalarAddr, MachinePointerInfo(),
22952 false, false, false, 0);
22957 // Replace the extracts
22958 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22959 UE = Uses.end(); UI != UE; ++UI) {
22960 SDNode *Extract = *UI;
22962 SDValue Idx = Extract->getOperand(1);
22963 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22964 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22967 // The replacement was made in place; don't return anything.
22971 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22972 static std::pair<unsigned, bool>
22973 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22974 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22975 if (!VT.isVector())
22976 return std::make_pair(0, false);
22978 bool NeedSplit = false;
22979 switch (VT.getSimpleVT().SimpleTy) {
22980 default: return std::make_pair(0, false);
22983 if (!Subtarget->hasVLX())
22984 return std::make_pair(0, false);
22988 if (!Subtarget->hasBWI())
22989 return std::make_pair(0, false);
22993 if (!Subtarget->hasAVX512())
22994 return std::make_pair(0, false);
22999 if (!Subtarget->hasAVX2())
23001 if (!Subtarget->hasAVX())
23002 return std::make_pair(0, false);
23007 if (!Subtarget->hasSSE2())
23008 return std::make_pair(0, false);
23011 // SSE2 has only a small subset of the operations.
23012 bool hasUnsigned = Subtarget->hasSSE41() ||
23013 (Subtarget->hasSSE2() && VT == MVT::v16i8);
23014 bool hasSigned = Subtarget->hasSSE41() ||
23015 (Subtarget->hasSSE2() && VT == MVT::v8i16);
23017 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23020 // Check for x CC y ? x : y.
23021 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23022 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23027 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
23030 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
23033 Opc = hasSigned ? X86ISD::SMIN : 0; break;
23036 Opc = hasSigned ? X86ISD::SMAX : 0; break;
23038 // Check for x CC y ? y : x -- a min/max with reversed arms.
23039 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23040 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23045 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
23048 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
23051 Opc = hasSigned ? X86ISD::SMAX : 0; break;
23054 Opc = hasSigned ? X86ISD::SMIN : 0; break;
23058 return std::make_pair(Opc, NeedSplit);
23062 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23063 const X86Subtarget *Subtarget) {
23065 SDValue Cond = N->getOperand(0);
23066 SDValue LHS = N->getOperand(1);
23067 SDValue RHS = N->getOperand(2);
23069 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23070 SDValue CondSrc = Cond->getOperand(0);
23071 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23072 Cond = CondSrc->getOperand(0);
23075 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23078 // A vselect where all conditions and data are constants can be optimized into
23079 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23080 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23081 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23084 unsigned MaskValue = 0;
23085 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23088 MVT VT = N->getSimpleValueType(0);
23089 unsigned NumElems = VT.getVectorNumElements();
23090 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23091 for (unsigned i = 0; i < NumElems; ++i) {
23092 // Be sure we emit undef where we can.
23093 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23094 ShuffleMask[i] = -1;
23096 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23100 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23102 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23105 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23107 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23108 TargetLowering::DAGCombinerInfo &DCI,
23109 const X86Subtarget *Subtarget) {
23111 SDValue Cond = N->getOperand(0);
23112 // Get the LHS/RHS of the select.
23113 SDValue LHS = N->getOperand(1);
23114 SDValue RHS = N->getOperand(2);
23115 EVT VT = LHS.getValueType();
23116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23118 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23119 // instructions match the semantics of the common C idiom x<y?x:y but not
23120 // x<=y?x:y, because of how they handle negative zero (which can be
23121 // ignored in unsafe-math mode).
23122 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23123 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23124 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23125 (Subtarget->hasSSE2() ||
23126 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23127 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23129 unsigned Opcode = 0;
23130 // Check for x CC y ? x : y.
23131 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23132 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23136 // Converting this to a min would handle NaNs incorrectly, and swapping
23137 // the operands would cause it to handle comparisons between positive
23138 // and negative zero incorrectly.
23139 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23140 if (!DAG.getTarget().Options.UnsafeFPMath &&
23141 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23143 std::swap(LHS, RHS);
23145 Opcode = X86ISD::FMIN;
23148 // Converting this to a min would handle comparisons between positive
23149 // and negative zero incorrectly.
23150 if (!DAG.getTarget().Options.UnsafeFPMath &&
23151 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23153 Opcode = X86ISD::FMIN;
23156 // Converting this to a min would handle both negative zeros and NaNs
23157 // incorrectly, but we can swap the operands to fix both.
23158 std::swap(LHS, RHS);
23162 Opcode = X86ISD::FMIN;
23166 // Converting this to a max would handle comparisons between positive
23167 // and negative zero incorrectly.
23168 if (!DAG.getTarget().Options.UnsafeFPMath &&
23169 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23171 Opcode = X86ISD::FMAX;
23174 // Converting this to a max would handle NaNs incorrectly, and swapping
23175 // the operands would cause it to handle comparisons between positive
23176 // and negative zero incorrectly.
23177 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23178 if (!DAG.getTarget().Options.UnsafeFPMath &&
23179 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23181 std::swap(LHS, RHS);
23183 Opcode = X86ISD::FMAX;
23186 // Converting this to a max would handle both negative zeros and NaNs
23187 // incorrectly, but we can swap the operands to fix both.
23188 std::swap(LHS, RHS);
23192 Opcode = X86ISD::FMAX;
23195 // Check for x CC y ? y : x -- a min/max with reversed arms.
23196 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23197 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23201 // Converting this to a min would handle comparisons between positive
23202 // and negative zero incorrectly, and swapping the operands would
23203 // cause it to handle NaNs incorrectly.
23204 if (!DAG.getTarget().Options.UnsafeFPMath &&
23205 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23206 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23208 std::swap(LHS, RHS);
23210 Opcode = X86ISD::FMIN;
23213 // Converting this to a min would handle NaNs incorrectly.
23214 if (!DAG.getTarget().Options.UnsafeFPMath &&
23215 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23217 Opcode = X86ISD::FMIN;
23220 // Converting this to a min would handle both negative zeros and NaNs
23221 // incorrectly, but we can swap the operands to fix both.
23222 std::swap(LHS, RHS);
23226 Opcode = X86ISD::FMIN;
23230 // Converting this to a max would handle NaNs incorrectly.
23231 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23233 Opcode = X86ISD::FMAX;
23236 // Converting this to a max would handle comparisons between positive
23237 // and negative zero incorrectly, and swapping the operands would
23238 // cause it to handle NaNs incorrectly.
23239 if (!DAG.getTarget().Options.UnsafeFPMath &&
23240 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23241 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23243 std::swap(LHS, RHS);
23245 Opcode = X86ISD::FMAX;
23248 // Converting this to a max would handle both negative zeros and NaNs
23249 // incorrectly, but we can swap the operands to fix both.
23250 std::swap(LHS, RHS);
23254 Opcode = X86ISD::FMAX;
23260 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23263 EVT CondVT = Cond.getValueType();
23264 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23265 CondVT.getVectorElementType() == MVT::i1) {
23266 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23267 // lowering on KNL. In this case we convert it to
23268 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23269 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23270 // Since SKX these selects have a proper lowering.
23271 EVT OpVT = LHS.getValueType();
23272 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23273 (OpVT.getVectorElementType() == MVT::i8 ||
23274 OpVT.getVectorElementType() == MVT::i16) &&
23275 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23276 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23277 DCI.AddToWorklist(Cond.getNode());
23278 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23281 // If this is a select between two integer constants, try to do some
23283 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23284 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23285 // Don't do this for crazy integer types.
23286 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23287 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23288 // so that TrueC (the true value) is larger than FalseC.
23289 bool NeedsCondInvert = false;
23291 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23292 // Efficiently invertible.
23293 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23294 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23295 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23296 NeedsCondInvert = true;
23297 std::swap(TrueC, FalseC);
23300 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23301 if (FalseC->getAPIntValue() == 0 &&
23302 TrueC->getAPIntValue().isPowerOf2()) {
23303 if (NeedsCondInvert) // Invert the condition if needed.
23304 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23305 DAG.getConstant(1, Cond.getValueType()));
23307 // Zero extend the condition if needed.
23308 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23310 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23311 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23312 DAG.getConstant(ShAmt, MVT::i8));
23315 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23316 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23317 if (NeedsCondInvert) // Invert the condition if needed.
23318 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23319 DAG.getConstant(1, Cond.getValueType()));
23321 // Zero extend the condition if needed.
23322 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23323 FalseC->getValueType(0), Cond);
23324 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23325 SDValue(FalseC, 0));
23328 // Optimize cases that will turn into an LEA instruction. This requires
23329 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23330 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23331 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23332 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23334 bool isFastMultiplier = false;
23336 switch ((unsigned char)Diff) {
23338 case 1: // result = add base, cond
23339 case 2: // result = lea base( , cond*2)
23340 case 3: // result = lea base(cond, cond*2)
23341 case 4: // result = lea base( , cond*4)
23342 case 5: // result = lea base(cond, cond*4)
23343 case 8: // result = lea base( , cond*8)
23344 case 9: // result = lea base(cond, cond*8)
23345 isFastMultiplier = true;
23350 if (isFastMultiplier) {
23351 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23352 if (NeedsCondInvert) // Invert the condition if needed.
23353 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23354 DAG.getConstant(1, Cond.getValueType()));
23356 // Zero extend the condition if needed.
23357 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23359 // Scale the condition by the difference.
23361 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23362 DAG.getConstant(Diff, Cond.getValueType()));
23364 // Add the base if non-zero.
23365 if (FalseC->getAPIntValue() != 0)
23366 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23367 SDValue(FalseC, 0));
23374 // Canonicalize max and min:
23375 // (x > y) ? x : y -> (x >= y) ? x : y
23376 // (x < y) ? x : y -> (x <= y) ? x : y
23377 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23378 // the need for an extra compare
23379 // against zero. e.g.
23380 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23382 // testl %edi, %edi
23384 // cmovgl %edi, %eax
23388 // cmovsl %eax, %edi
23389 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23390 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23391 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23392 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23397 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23398 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23399 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23400 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23405 // Early exit check
23406 if (!TLI.isTypeLegal(VT))
23409 // Match VSELECTs into subs with unsigned saturation.
23410 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23411 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23412 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23413 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23414 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23416 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23417 // left side invert the predicate to simplify logic below.
23419 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23421 CC = ISD::getSetCCInverse(CC, true);
23422 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23426 if (Other.getNode() && Other->getNumOperands() == 2 &&
23427 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23428 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23429 SDValue CondRHS = Cond->getOperand(1);
23431 // Look for a general sub with unsigned saturation first.
23432 // x >= y ? x-y : 0 --> subus x, y
23433 // x > y ? x-y : 0 --> subus x, y
23434 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23435 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23436 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23438 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23439 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23440 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23441 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23442 // If the RHS is a constant we have to reverse the const
23443 // canonicalization.
23444 // x > C-1 ? x+-C : 0 --> subus x, C
23445 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23446 CondRHSConst->getAPIntValue() ==
23447 (-OpRHSConst->getAPIntValue() - 1))
23448 return DAG.getNode(
23449 X86ISD::SUBUS, DL, VT, OpLHS,
23450 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23452 // Another special case: If C was a sign bit, the sub has been
23453 // canonicalized into a xor.
23454 // FIXME: Would it be better to use computeKnownBits to determine
23455 // whether it's safe to decanonicalize the xor?
23456 // x s< 0 ? x^C : 0 --> subus x, C
23457 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23458 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23459 OpRHSConst->getAPIntValue().isSignBit())
23460 // Note that we have to rebuild the RHS constant here to ensure we
23461 // don't rely on particular values of undef lanes.
23462 return DAG.getNode(
23463 X86ISD::SUBUS, DL, VT, OpLHS,
23464 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23469 // Try to match a min/max vector operation.
23470 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23471 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23472 unsigned Opc = ret.first;
23473 bool NeedSplit = ret.second;
23475 if (Opc && NeedSplit) {
23476 unsigned NumElems = VT.getVectorNumElements();
23477 // Extract the LHS vectors
23478 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23479 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23481 // Extract the RHS vectors
23482 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23483 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23485 // Create min/max for each subvector
23486 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23487 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23489 // Merge the result
23490 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23492 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23495 // Simplify vector selection if condition value type matches vselect
23497 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23498 assert(Cond.getValueType().isVector() &&
23499 "vector select expects a vector selector!");
23501 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23502 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23504 // Try invert the condition if true value is not all 1s and false value
23506 if (!TValIsAllOnes && !FValIsAllZeros &&
23507 // Check if the selector will be produced by CMPP*/PCMP*
23508 Cond.getOpcode() == ISD::SETCC &&
23509 // Check if SETCC has already been promoted
23510 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23511 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23512 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23514 if (TValIsAllZeros || FValIsAllOnes) {
23515 SDValue CC = Cond.getOperand(2);
23516 ISD::CondCode NewCC =
23517 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23518 Cond.getOperand(0).getValueType().isInteger());
23519 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23520 std::swap(LHS, RHS);
23521 TValIsAllOnes = FValIsAllOnes;
23522 FValIsAllZeros = TValIsAllZeros;
23526 if (TValIsAllOnes || FValIsAllZeros) {
23529 if (TValIsAllOnes && FValIsAllZeros)
23531 else if (TValIsAllOnes)
23532 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23533 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23534 else if (FValIsAllZeros)
23535 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23536 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23538 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23542 // If we know that this node is legal then we know that it is going to be
23543 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23544 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23545 // to simplify previous instructions.
23546 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23547 !DCI.isBeforeLegalize() &&
23548 // We explicitly check against v8i16 and v16i16 because, although
23549 // they're marked as Custom, they might only be legal when Cond is a
23550 // build_vector of constants. This will be taken care in a later
23552 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23553 VT != MVT::v8i16) &&
23554 // Don't optimize vector of constants. Those are handled by
23555 // the generic code and all the bits must be properly set for
23556 // the generic optimizer.
23557 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23558 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23560 // Don't optimize vector selects that map to mask-registers.
23564 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23565 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23567 APInt KnownZero, KnownOne;
23568 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23569 DCI.isBeforeLegalizeOps());
23570 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23571 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23573 // If we changed the computation somewhere in the DAG, this change
23574 // will affect all users of Cond.
23575 // Make sure it is fine and update all the nodes so that we do not
23576 // use the generic VSELECT anymore. Otherwise, we may perform
23577 // wrong optimizations as we messed up with the actual expectation
23578 // for the vector boolean values.
23579 if (Cond != TLO.Old) {
23580 // Check all uses of that condition operand to check whether it will be
23581 // consumed by non-BLEND instructions, which may depend on all bits are
23583 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23585 if (I->getOpcode() != ISD::VSELECT)
23586 // TODO: Add other opcodes eventually lowered into BLEND.
23589 // Update all the users of the condition, before committing the change,
23590 // so that the VSELECT optimizations that expect the correct vector
23591 // boolean value will not be triggered.
23592 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23594 DAG.ReplaceAllUsesOfValueWith(
23596 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23597 Cond, I->getOperand(1), I->getOperand(2)));
23598 DCI.CommitTargetLoweringOpt(TLO);
23601 // At this point, only Cond is changed. Change the condition
23602 // just for N to keep the opportunity to optimize all other
23603 // users their own way.
23604 DAG.ReplaceAllUsesOfValueWith(
23606 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23607 TLO.New, N->getOperand(1), N->getOperand(2)));
23612 // We should generate an X86ISD::BLENDI from a vselect if its argument
23613 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23614 // constants. This specific pattern gets generated when we split a
23615 // selector for a 512 bit vector in a machine without AVX512 (but with
23616 // 256-bit vectors), during legalization:
23618 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23620 // Iff we find this pattern and the build_vectors are built from
23621 // constants, we translate the vselect into a shuffle_vector that we
23622 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23623 if ((N->getOpcode() == ISD::VSELECT ||
23624 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23625 !DCI.isBeforeLegalize()) {
23626 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23627 if (Shuffle.getNode())
23634 // Check whether a boolean test is testing a boolean value generated by
23635 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23638 // Simplify the following patterns:
23639 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23640 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23641 // to (Op EFLAGS Cond)
23643 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23644 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23645 // to (Op EFLAGS !Cond)
23647 // where Op could be BRCOND or CMOV.
23649 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23650 // Quit if not CMP and SUB with its value result used.
23651 if (Cmp.getOpcode() != X86ISD::CMP &&
23652 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23655 // Quit if not used as a boolean value.
23656 if (CC != X86::COND_E && CC != X86::COND_NE)
23659 // Check CMP operands. One of them should be 0 or 1 and the other should be
23660 // an SetCC or extended from it.
23661 SDValue Op1 = Cmp.getOperand(0);
23662 SDValue Op2 = Cmp.getOperand(1);
23665 const ConstantSDNode* C = nullptr;
23666 bool needOppositeCond = (CC == X86::COND_E);
23667 bool checkAgainstTrue = false; // Is it a comparison against 1?
23669 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23671 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23673 else // Quit if all operands are not constants.
23676 if (C->getZExtValue() == 1) {
23677 needOppositeCond = !needOppositeCond;
23678 checkAgainstTrue = true;
23679 } else if (C->getZExtValue() != 0)
23680 // Quit if the constant is neither 0 or 1.
23683 bool truncatedToBoolWithAnd = false;
23684 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23685 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23686 SetCC.getOpcode() == ISD::TRUNCATE ||
23687 SetCC.getOpcode() == ISD::AND) {
23688 if (SetCC.getOpcode() == ISD::AND) {
23690 ConstantSDNode *CS;
23691 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23692 CS->getZExtValue() == 1)
23694 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23695 CS->getZExtValue() == 1)
23699 SetCC = SetCC.getOperand(OpIdx);
23700 truncatedToBoolWithAnd = true;
23702 SetCC = SetCC.getOperand(0);
23705 switch (SetCC.getOpcode()) {
23706 case X86ISD::SETCC_CARRY:
23707 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23708 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23709 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23710 // truncated to i1 using 'and'.
23711 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23713 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23714 "Invalid use of SETCC_CARRY!");
23716 case X86ISD::SETCC:
23717 // Set the condition code or opposite one if necessary.
23718 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23719 if (needOppositeCond)
23720 CC = X86::GetOppositeBranchCondition(CC);
23721 return SetCC.getOperand(1);
23722 case X86ISD::CMOV: {
23723 // Check whether false/true value has canonical one, i.e. 0 or 1.
23724 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23725 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23726 // Quit if true value is not a constant.
23729 // Quit if false value is not a constant.
23731 SDValue Op = SetCC.getOperand(0);
23732 // Skip 'zext' or 'trunc' node.
23733 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23734 Op.getOpcode() == ISD::TRUNCATE)
23735 Op = Op.getOperand(0);
23736 // A special case for rdrand/rdseed, where 0 is set if false cond is
23738 if ((Op.getOpcode() != X86ISD::RDRAND &&
23739 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23742 // Quit if false value is not the constant 0 or 1.
23743 bool FValIsFalse = true;
23744 if (FVal && FVal->getZExtValue() != 0) {
23745 if (FVal->getZExtValue() != 1)
23747 // If FVal is 1, opposite cond is needed.
23748 needOppositeCond = !needOppositeCond;
23749 FValIsFalse = false;
23751 // Quit if TVal is not the constant opposite of FVal.
23752 if (FValIsFalse && TVal->getZExtValue() != 1)
23754 if (!FValIsFalse && TVal->getZExtValue() != 0)
23756 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23757 if (needOppositeCond)
23758 CC = X86::GetOppositeBranchCondition(CC);
23759 return SetCC.getOperand(3);
23766 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23767 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23768 TargetLowering::DAGCombinerInfo &DCI,
23769 const X86Subtarget *Subtarget) {
23772 // If the flag operand isn't dead, don't touch this CMOV.
23773 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23776 SDValue FalseOp = N->getOperand(0);
23777 SDValue TrueOp = N->getOperand(1);
23778 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23779 SDValue Cond = N->getOperand(3);
23781 if (CC == X86::COND_E || CC == X86::COND_NE) {
23782 switch (Cond.getOpcode()) {
23786 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23787 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23788 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23794 Flags = checkBoolTestSetCCCombine(Cond, CC);
23795 if (Flags.getNode() &&
23796 // Extra check as FCMOV only supports a subset of X86 cond.
23797 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23798 SDValue Ops[] = { FalseOp, TrueOp,
23799 DAG.getConstant(CC, MVT::i8), Flags };
23800 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23803 // If this is a select between two integer constants, try to do some
23804 // optimizations. Note that the operands are ordered the opposite of SELECT
23806 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23807 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23808 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23809 // larger than FalseC (the false value).
23810 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23811 CC = X86::GetOppositeBranchCondition(CC);
23812 std::swap(TrueC, FalseC);
23813 std::swap(TrueOp, FalseOp);
23816 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23817 // This is efficient for any integer data type (including i8/i16) and
23819 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23820 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23821 DAG.getConstant(CC, MVT::i8), Cond);
23823 // Zero extend the condition if needed.
23824 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23826 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23827 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23828 DAG.getConstant(ShAmt, MVT::i8));
23829 if (N->getNumValues() == 2) // Dead flag value?
23830 return DCI.CombineTo(N, Cond, SDValue());
23834 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23835 // for any integer data type, including i8/i16.
23836 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23837 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23838 DAG.getConstant(CC, MVT::i8), Cond);
23840 // Zero extend the condition if needed.
23841 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23842 FalseC->getValueType(0), Cond);
23843 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23844 SDValue(FalseC, 0));
23846 if (N->getNumValues() == 2) // Dead flag value?
23847 return DCI.CombineTo(N, Cond, SDValue());
23851 // Optimize cases that will turn into an LEA instruction. This requires
23852 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23853 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23854 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23855 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23857 bool isFastMultiplier = false;
23859 switch ((unsigned char)Diff) {
23861 case 1: // result = add base, cond
23862 case 2: // result = lea base( , cond*2)
23863 case 3: // result = lea base(cond, cond*2)
23864 case 4: // result = lea base( , cond*4)
23865 case 5: // result = lea base(cond, cond*4)
23866 case 8: // result = lea base( , cond*8)
23867 case 9: // result = lea base(cond, cond*8)
23868 isFastMultiplier = true;
23873 if (isFastMultiplier) {
23874 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23875 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23876 DAG.getConstant(CC, MVT::i8), Cond);
23877 // Zero extend the condition if needed.
23878 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23880 // Scale the condition by the difference.
23882 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23883 DAG.getConstant(Diff, Cond.getValueType()));
23885 // Add the base if non-zero.
23886 if (FalseC->getAPIntValue() != 0)
23887 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23888 SDValue(FalseC, 0));
23889 if (N->getNumValues() == 2) // Dead flag value?
23890 return DCI.CombineTo(N, Cond, SDValue());
23897 // Handle these cases:
23898 // (select (x != c), e, c) -> select (x != c), e, x),
23899 // (select (x == c), c, e) -> select (x == c), x, e)
23900 // where the c is an integer constant, and the "select" is the combination
23901 // of CMOV and CMP.
23903 // The rationale for this change is that the conditional-move from a constant
23904 // needs two instructions, however, conditional-move from a register needs
23905 // only one instruction.
23907 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23908 // some instruction-combining opportunities. This opt needs to be
23909 // postponed as late as possible.
23911 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23912 // the DCI.xxxx conditions are provided to postpone the optimization as
23913 // late as possible.
23915 ConstantSDNode *CmpAgainst = nullptr;
23916 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23917 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23918 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23920 if (CC == X86::COND_NE &&
23921 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23922 CC = X86::GetOppositeBranchCondition(CC);
23923 std::swap(TrueOp, FalseOp);
23926 if (CC == X86::COND_E &&
23927 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23928 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23929 DAG.getConstant(CC, MVT::i8), Cond };
23930 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23938 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23939 const X86Subtarget *Subtarget) {
23940 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23942 default: return SDValue();
23943 // SSE/AVX/AVX2 blend intrinsics.
23944 case Intrinsic::x86_avx2_pblendvb:
23945 case Intrinsic::x86_avx2_pblendw:
23946 case Intrinsic::x86_avx2_pblendd_128:
23947 case Intrinsic::x86_avx2_pblendd_256:
23948 // Don't try to simplify this intrinsic if we don't have AVX2.
23949 if (!Subtarget->hasAVX2())
23952 case Intrinsic::x86_avx_blend_pd_256:
23953 case Intrinsic::x86_avx_blend_ps_256:
23954 case Intrinsic::x86_avx_blendv_pd_256:
23955 case Intrinsic::x86_avx_blendv_ps_256:
23956 // Don't try to simplify this intrinsic if we don't have AVX.
23957 if (!Subtarget->hasAVX())
23960 case Intrinsic::x86_sse41_pblendw:
23961 case Intrinsic::x86_sse41_blendpd:
23962 case Intrinsic::x86_sse41_blendps:
23963 case Intrinsic::x86_sse41_blendvps:
23964 case Intrinsic::x86_sse41_blendvpd:
23965 case Intrinsic::x86_sse41_pblendvb: {
23966 SDValue Op0 = N->getOperand(1);
23967 SDValue Op1 = N->getOperand(2);
23968 SDValue Mask = N->getOperand(3);
23970 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23971 if (!Subtarget->hasSSE41())
23974 // fold (blend A, A, Mask) -> A
23977 // fold (blend A, B, allZeros) -> A
23978 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23980 // fold (blend A, B, allOnes) -> B
23981 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23984 // Simplify the case where the mask is a constant i32 value.
23985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23986 if (C->isNullValue())
23988 if (C->isAllOnesValue())
23995 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23996 case Intrinsic::x86_sse2_psrai_w:
23997 case Intrinsic::x86_sse2_psrai_d:
23998 case Intrinsic::x86_avx2_psrai_w:
23999 case Intrinsic::x86_avx2_psrai_d:
24000 case Intrinsic::x86_sse2_psra_w:
24001 case Intrinsic::x86_sse2_psra_d:
24002 case Intrinsic::x86_avx2_psra_w:
24003 case Intrinsic::x86_avx2_psra_d: {
24004 SDValue Op0 = N->getOperand(1);
24005 SDValue Op1 = N->getOperand(2);
24006 EVT VT = Op0.getValueType();
24007 assert(VT.isVector() && "Expected a vector type!");
24009 if (isa<BuildVectorSDNode>(Op1))
24010 Op1 = Op1.getOperand(0);
24012 if (!isa<ConstantSDNode>(Op1))
24015 EVT SVT = VT.getVectorElementType();
24016 unsigned SVTBits = SVT.getSizeInBits();
24018 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
24019 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
24020 uint64_t ShAmt = C.getZExtValue();
24022 // Don't try to convert this shift into a ISD::SRA if the shift
24023 // count is bigger than or equal to the element size.
24024 if (ShAmt >= SVTBits)
24027 // Trivial case: if the shift count is zero, then fold this
24028 // into the first operand.
24032 // Replace this packed shift intrinsic with a target independent
24034 SDValue Splat = DAG.getConstant(C, VT);
24035 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
24040 /// PerformMulCombine - Optimize a single multiply with constant into two
24041 /// in order to implement it with two cheaper instructions, e.g.
24042 /// LEA + SHL, LEA + LEA.
24043 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24044 TargetLowering::DAGCombinerInfo &DCI) {
24045 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24048 EVT VT = N->getValueType(0);
24049 if (VT != MVT::i64)
24052 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24055 uint64_t MulAmt = C->getZExtValue();
24056 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24059 uint64_t MulAmt1 = 0;
24060 uint64_t MulAmt2 = 0;
24061 if ((MulAmt % 9) == 0) {
24063 MulAmt2 = MulAmt / 9;
24064 } else if ((MulAmt % 5) == 0) {
24066 MulAmt2 = MulAmt / 5;
24067 } else if ((MulAmt % 3) == 0) {
24069 MulAmt2 = MulAmt / 3;
24072 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24075 if (isPowerOf2_64(MulAmt2) &&
24076 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24077 // If second multiplifer is pow2, issue it first. We want the multiply by
24078 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24080 std::swap(MulAmt1, MulAmt2);
24083 if (isPowerOf2_64(MulAmt1))
24084 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24085 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
24087 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24088 DAG.getConstant(MulAmt1, VT));
24090 if (isPowerOf2_64(MulAmt2))
24091 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24092 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
24094 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24095 DAG.getConstant(MulAmt2, VT));
24097 // Do not add new nodes to DAG combiner worklist.
24098 DCI.CombineTo(N, NewMul, false);
24103 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24104 SDValue N0 = N->getOperand(0);
24105 SDValue N1 = N->getOperand(1);
24106 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24107 EVT VT = N0.getValueType();
24109 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24110 // since the result of setcc_c is all zero's or all ones.
24111 if (VT.isInteger() && !VT.isVector() &&
24112 N1C && N0.getOpcode() == ISD::AND &&
24113 N0.getOperand(1).getOpcode() == ISD::Constant) {
24114 SDValue N00 = N0.getOperand(0);
24115 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
24116 ((N00.getOpcode() == ISD::ANY_EXTEND ||
24117 N00.getOpcode() == ISD::ZERO_EXTEND) &&
24118 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
24119 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24120 APInt ShAmt = N1C->getAPIntValue();
24121 Mask = Mask.shl(ShAmt);
24123 return DAG.getNode(ISD::AND, SDLoc(N), VT,
24124 N00, DAG.getConstant(Mask, VT));
24128 // Hardware support for vector shifts is sparse which makes us scalarize the
24129 // vector operations in many cases. Also, on sandybridge ADD is faster than
24131 // (shl V, 1) -> add V,V
24132 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24133 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24134 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24135 // We shift all of the values by one. In many cases we do not have
24136 // hardware support for this operation. This is better expressed as an ADD
24138 if (N1SplatC->getZExtValue() == 1)
24139 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24145 /// \brief Returns a vector of 0s if the node in input is a vector logical
24146 /// shift by a constant amount which is known to be bigger than or equal
24147 /// to the vector element size in bits.
24148 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24149 const X86Subtarget *Subtarget) {
24150 EVT VT = N->getValueType(0);
24152 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24153 (!Subtarget->hasInt256() ||
24154 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24157 SDValue Amt = N->getOperand(1);
24159 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24160 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24161 APInt ShiftAmt = AmtSplat->getAPIntValue();
24162 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24164 // SSE2/AVX2 logical shifts always return a vector of 0s
24165 // if the shift amount is bigger than or equal to
24166 // the element size. The constant shift amount will be
24167 // encoded as a 8-bit immediate.
24168 if (ShiftAmt.trunc(8).uge(MaxAmount))
24169 return getZeroVector(VT, Subtarget, DAG, DL);
24175 /// PerformShiftCombine - Combine shifts.
24176 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24177 TargetLowering::DAGCombinerInfo &DCI,
24178 const X86Subtarget *Subtarget) {
24179 if (N->getOpcode() == ISD::SHL) {
24180 SDValue V = PerformSHLCombine(N, DAG);
24181 if (V.getNode()) return V;
24184 if (N->getOpcode() != ISD::SRA) {
24185 // Try to fold this logical shift into a zero vector.
24186 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24187 if (V.getNode()) return V;
24193 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24194 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24195 // and friends. Likewise for OR -> CMPNEQSS.
24196 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24197 TargetLowering::DAGCombinerInfo &DCI,
24198 const X86Subtarget *Subtarget) {
24201 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24202 // we're requiring SSE2 for both.
24203 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24204 SDValue N0 = N->getOperand(0);
24205 SDValue N1 = N->getOperand(1);
24206 SDValue CMP0 = N0->getOperand(1);
24207 SDValue CMP1 = N1->getOperand(1);
24210 // The SETCCs should both refer to the same CMP.
24211 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24214 SDValue CMP00 = CMP0->getOperand(0);
24215 SDValue CMP01 = CMP0->getOperand(1);
24216 EVT VT = CMP00.getValueType();
24218 if (VT == MVT::f32 || VT == MVT::f64) {
24219 bool ExpectingFlags = false;
24220 // Check for any users that want flags:
24221 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24222 !ExpectingFlags && UI != UE; ++UI)
24223 switch (UI->getOpcode()) {
24228 ExpectingFlags = true;
24230 case ISD::CopyToReg:
24231 case ISD::SIGN_EXTEND:
24232 case ISD::ZERO_EXTEND:
24233 case ISD::ANY_EXTEND:
24237 if (!ExpectingFlags) {
24238 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24239 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24241 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24242 X86::CondCode tmp = cc0;
24247 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24248 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24249 // FIXME: need symbolic constants for these magic numbers.
24250 // See X86ATTInstPrinter.cpp:printSSECC().
24251 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24252 if (Subtarget->hasAVX512()) {
24253 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24254 CMP01, DAG.getConstant(x86cc, MVT::i8));
24255 if (N->getValueType(0) != MVT::i1)
24256 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24260 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24261 CMP00.getValueType(), CMP00, CMP01,
24262 DAG.getConstant(x86cc, MVT::i8));
24264 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24265 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24267 if (is64BitFP && !Subtarget->is64Bit()) {
24268 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24269 // 64-bit integer, since that's not a legal type. Since
24270 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24271 // bits, but can do this little dance to extract the lowest 32 bits
24272 // and work with those going forward.
24273 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24275 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24277 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24278 Vector32, DAG.getIntPtrConstant(0));
24282 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24283 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24284 DAG.getConstant(1, IntVT));
24285 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24286 return OneBitOfTruth;
24294 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24295 /// so it can be folded inside ANDNP.
24296 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24297 EVT VT = N->getValueType(0);
24299 // Match direct AllOnes for 128 and 256-bit vectors
24300 if (ISD::isBuildVectorAllOnes(N))
24303 // Look through a bit convert.
24304 if (N->getOpcode() == ISD::BITCAST)
24305 N = N->getOperand(0).getNode();
24307 // Sometimes the operand may come from a insert_subvector building a 256-bit
24309 if (VT.is256BitVector() &&
24310 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24311 SDValue V1 = N->getOperand(0);
24312 SDValue V2 = N->getOperand(1);
24314 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24315 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24316 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24317 ISD::isBuildVectorAllOnes(V2.getNode()))
24324 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24325 // register. In most cases we actually compare or select YMM-sized registers
24326 // and mixing the two types creates horrible code. This method optimizes
24327 // some of the transition sequences.
24328 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24329 TargetLowering::DAGCombinerInfo &DCI,
24330 const X86Subtarget *Subtarget) {
24331 EVT VT = N->getValueType(0);
24332 if (!VT.is256BitVector())
24335 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24336 N->getOpcode() == ISD::ZERO_EXTEND ||
24337 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24339 SDValue Narrow = N->getOperand(0);
24340 EVT NarrowVT = Narrow->getValueType(0);
24341 if (!NarrowVT.is128BitVector())
24344 if (Narrow->getOpcode() != ISD::XOR &&
24345 Narrow->getOpcode() != ISD::AND &&
24346 Narrow->getOpcode() != ISD::OR)
24349 SDValue N0 = Narrow->getOperand(0);
24350 SDValue N1 = Narrow->getOperand(1);
24353 // The Left side has to be a trunc.
24354 if (N0.getOpcode() != ISD::TRUNCATE)
24357 // The type of the truncated inputs.
24358 EVT WideVT = N0->getOperand(0)->getValueType(0);
24362 // The right side has to be a 'trunc' or a constant vector.
24363 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24364 ConstantSDNode *RHSConstSplat = nullptr;
24365 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24366 RHSConstSplat = RHSBV->getConstantSplatNode();
24367 if (!RHSTrunc && !RHSConstSplat)
24370 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24372 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24375 // Set N0 and N1 to hold the inputs to the new wide operation.
24376 N0 = N0->getOperand(0);
24377 if (RHSConstSplat) {
24378 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24379 SDValue(RHSConstSplat, 0));
24380 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24381 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24382 } else if (RHSTrunc) {
24383 N1 = N1->getOperand(0);
24386 // Generate the wide operation.
24387 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24388 unsigned Opcode = N->getOpcode();
24390 case ISD::ANY_EXTEND:
24392 case ISD::ZERO_EXTEND: {
24393 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24394 APInt Mask = APInt::getAllOnesValue(InBits);
24395 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24396 return DAG.getNode(ISD::AND, DL, VT,
24397 Op, DAG.getConstant(Mask, VT));
24399 case ISD::SIGN_EXTEND:
24400 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24401 Op, DAG.getValueType(NarrowVT));
24403 llvm_unreachable("Unexpected opcode");
24407 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24408 TargetLowering::DAGCombinerInfo &DCI,
24409 const X86Subtarget *Subtarget) {
24410 EVT VT = N->getValueType(0);
24411 if (DCI.isBeforeLegalizeOps())
24414 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24418 // Create BEXTR instructions
24419 // BEXTR is ((X >> imm) & (2**size-1))
24420 if (VT == MVT::i32 || VT == MVT::i64) {
24421 SDValue N0 = N->getOperand(0);
24422 SDValue N1 = N->getOperand(1);
24425 // Check for BEXTR.
24426 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24427 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24428 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24429 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24430 if (MaskNode && ShiftNode) {
24431 uint64_t Mask = MaskNode->getZExtValue();
24432 uint64_t Shift = ShiftNode->getZExtValue();
24433 if (isMask_64(Mask)) {
24434 uint64_t MaskSize = CountPopulation_64(Mask);
24435 if (Shift + MaskSize <= VT.getSizeInBits())
24436 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24437 DAG.getConstant(Shift | (MaskSize << 8), VT));
24445 // Want to form ANDNP nodes:
24446 // 1) In the hopes of then easily combining them with OR and AND nodes
24447 // to form PBLEND/PSIGN.
24448 // 2) To match ANDN packed intrinsics
24449 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24452 SDValue N0 = N->getOperand(0);
24453 SDValue N1 = N->getOperand(1);
24456 // Check LHS for vnot
24457 if (N0.getOpcode() == ISD::XOR &&
24458 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24459 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24460 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24462 // Check RHS for vnot
24463 if (N1.getOpcode() == ISD::XOR &&
24464 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24465 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24466 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24471 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24472 TargetLowering::DAGCombinerInfo &DCI,
24473 const X86Subtarget *Subtarget) {
24474 if (DCI.isBeforeLegalizeOps())
24477 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24481 SDValue N0 = N->getOperand(0);
24482 SDValue N1 = N->getOperand(1);
24483 EVT VT = N->getValueType(0);
24485 // look for psign/blend
24486 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24487 if (!Subtarget->hasSSSE3() ||
24488 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24491 // Canonicalize pandn to RHS
24492 if (N0.getOpcode() == X86ISD::ANDNP)
24494 // or (and (m, y), (pandn m, x))
24495 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24496 SDValue Mask = N1.getOperand(0);
24497 SDValue X = N1.getOperand(1);
24499 if (N0.getOperand(0) == Mask)
24500 Y = N0.getOperand(1);
24501 if (N0.getOperand(1) == Mask)
24502 Y = N0.getOperand(0);
24504 // Check to see if the mask appeared in both the AND and ANDNP and
24508 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24509 // Look through mask bitcast.
24510 if (Mask.getOpcode() == ISD::BITCAST)
24511 Mask = Mask.getOperand(0);
24512 if (X.getOpcode() == ISD::BITCAST)
24513 X = X.getOperand(0);
24514 if (Y.getOpcode() == ISD::BITCAST)
24515 Y = Y.getOperand(0);
24517 EVT MaskVT = Mask.getValueType();
24519 // Validate that the Mask operand is a vector sra node.
24520 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24521 // there is no psrai.b
24522 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24523 unsigned SraAmt = ~0;
24524 if (Mask.getOpcode() == ISD::SRA) {
24525 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24526 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24527 SraAmt = AmtConst->getZExtValue();
24528 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24529 SDValue SraC = Mask.getOperand(1);
24530 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24532 if ((SraAmt + 1) != EltBits)
24537 // Now we know we at least have a plendvb with the mask val. See if
24538 // we can form a psignb/w/d.
24539 // psign = x.type == y.type == mask.type && y = sub(0, x);
24540 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24541 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24542 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24543 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24544 "Unsupported VT for PSIGN");
24545 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24546 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24548 // PBLENDVB only available on SSE 4.1
24549 if (!Subtarget->hasSSE41())
24552 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24554 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24555 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24556 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24557 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24558 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24562 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24565 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24566 MachineFunction &MF = DAG.getMachineFunction();
24567 bool OptForSize = MF.getFunction()->getAttributes().
24568 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24570 // SHLD/SHRD instructions have lower register pressure, but on some
24571 // platforms they have higher latency than the equivalent
24572 // series of shifts/or that would otherwise be generated.
24573 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24574 // have higher latencies and we are not optimizing for size.
24575 if (!OptForSize && Subtarget->isSHLDSlow())
24578 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24580 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24582 if (!N0.hasOneUse() || !N1.hasOneUse())
24585 SDValue ShAmt0 = N0.getOperand(1);
24586 if (ShAmt0.getValueType() != MVT::i8)
24588 SDValue ShAmt1 = N1.getOperand(1);
24589 if (ShAmt1.getValueType() != MVT::i8)
24591 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24592 ShAmt0 = ShAmt0.getOperand(0);
24593 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24594 ShAmt1 = ShAmt1.getOperand(0);
24597 unsigned Opc = X86ISD::SHLD;
24598 SDValue Op0 = N0.getOperand(0);
24599 SDValue Op1 = N1.getOperand(0);
24600 if (ShAmt0.getOpcode() == ISD::SUB) {
24601 Opc = X86ISD::SHRD;
24602 std::swap(Op0, Op1);
24603 std::swap(ShAmt0, ShAmt1);
24606 unsigned Bits = VT.getSizeInBits();
24607 if (ShAmt1.getOpcode() == ISD::SUB) {
24608 SDValue Sum = ShAmt1.getOperand(0);
24609 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24610 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24611 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24612 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24613 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24614 return DAG.getNode(Opc, DL, VT,
24616 DAG.getNode(ISD::TRUNCATE, DL,
24619 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24620 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24622 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24623 return DAG.getNode(Opc, DL, VT,
24624 N0.getOperand(0), N1.getOperand(0),
24625 DAG.getNode(ISD::TRUNCATE, DL,
24632 // Generate NEG and CMOV for integer abs.
24633 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24634 EVT VT = N->getValueType(0);
24636 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24637 // 8-bit integer abs to NEG and CMOV.
24638 if (VT.isInteger() && VT.getSizeInBits() == 8)
24641 SDValue N0 = N->getOperand(0);
24642 SDValue N1 = N->getOperand(1);
24645 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24646 // and change it to SUB and CMOV.
24647 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24648 N0.getOpcode() == ISD::ADD &&
24649 N0.getOperand(1) == N1 &&
24650 N1.getOpcode() == ISD::SRA &&
24651 N1.getOperand(0) == N0.getOperand(0))
24652 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24653 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24654 // Generate SUB & CMOV.
24655 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24656 DAG.getConstant(0, VT), N0.getOperand(0));
24658 SDValue Ops[] = { N0.getOperand(0), Neg,
24659 DAG.getConstant(X86::COND_GE, MVT::i8),
24660 SDValue(Neg.getNode(), 1) };
24661 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24666 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24667 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24668 TargetLowering::DAGCombinerInfo &DCI,
24669 const X86Subtarget *Subtarget) {
24670 if (DCI.isBeforeLegalizeOps())
24673 if (Subtarget->hasCMov()) {
24674 SDValue RV = performIntegerAbsCombine(N, DAG);
24682 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24683 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24684 TargetLowering::DAGCombinerInfo &DCI,
24685 const X86Subtarget *Subtarget) {
24686 LoadSDNode *Ld = cast<LoadSDNode>(N);
24687 EVT RegVT = Ld->getValueType(0);
24688 EVT MemVT = Ld->getMemoryVT();
24690 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24692 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24693 // into two 16-byte operations.
24694 ISD::LoadExtType Ext = Ld->getExtensionType();
24695 unsigned Alignment = Ld->getAlignment();
24696 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24697 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24698 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24699 unsigned NumElems = RegVT.getVectorNumElements();
24703 SDValue Ptr = Ld->getBasePtr();
24704 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24706 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24708 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24709 Ld->getPointerInfo(), Ld->isVolatile(),
24710 Ld->isNonTemporal(), Ld->isInvariant(),
24712 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24713 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24714 Ld->getPointerInfo(), Ld->isVolatile(),
24715 Ld->isNonTemporal(), Ld->isInvariant(),
24716 std::min(16U, Alignment));
24717 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24719 Load2.getValue(1));
24721 SDValue NewVec = DAG.getUNDEF(RegVT);
24722 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24723 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24724 return DCI.CombineTo(N, NewVec, TF, true);
24730 /// PerformMLOADCombine - Resolve extending loads
24731 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24732 TargetLowering::DAGCombinerInfo &DCI,
24733 const X86Subtarget *Subtarget) {
24734 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24735 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24738 EVT VT = Mld->getValueType(0);
24739 unsigned NumElems = VT.getVectorNumElements();
24740 EVT LdVT = Mld->getMemoryVT();
24743 assert(LdVT != VT && "Cannot extend to the same type");
24744 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24745 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24746 // From, To sizes and ElemCount must be pow of two
24747 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24748 "Unexpected size for extending masked load");
24750 unsigned SizeRatio = ToSz / FromSz;
24751 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24753 // Create a type on which we perform the shuffle
24754 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24755 LdVT.getScalarType(), NumElems*SizeRatio);
24756 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24758 // Convert Src0 value
24759 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
24760 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24761 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24762 for (unsigned i = 0; i != NumElems; ++i)
24763 ShuffleVec[i] = i * SizeRatio;
24765 // Can't shuffle using an illegal type.
24766 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24767 && "WideVecVT should be legal");
24768 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24769 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24771 // Prepare the new mask
24773 SDValue Mask = Mld->getMask();
24774 if (Mask.getValueType() == VT) {
24775 // Mask and original value have the same type
24776 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
24777 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24778 for (unsigned i = 0; i != NumElems; ++i)
24779 ShuffleVec[i] = i * SizeRatio;
24780 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24781 ShuffleVec[i] = NumElems*SizeRatio;
24782 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24783 DAG.getConstant(0, WideVecVT),
24787 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24788 unsigned WidenNumElts = NumElems*SizeRatio;
24789 unsigned MaskNumElts = VT.getVectorNumElements();
24790 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24793 unsigned NumConcat = WidenNumElts / MaskNumElts;
24794 SmallVector<SDValue, 16> Ops(NumConcat);
24795 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
24797 for (unsigned i = 1; i != NumConcat; ++i)
24800 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24803 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24804 Mld->getBasePtr(), NewMask, WideSrc0,
24805 Mld->getMemoryVT(), Mld->getMemOperand(),
24807 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24808 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24811 /// PerformMSTORECombine - Resolve truncating stores
24812 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24813 const X86Subtarget *Subtarget) {
24814 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24815 if (!Mst->isTruncatingStore())
24818 EVT VT = Mst->getValue().getValueType();
24819 unsigned NumElems = VT.getVectorNumElements();
24820 EVT StVT = Mst->getMemoryVT();
24823 assert(StVT != VT && "Cannot truncate to the same type");
24824 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24825 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24827 // From, To sizes and ElemCount must be pow of two
24828 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24829 "Unexpected size for truncating masked store");
24830 // We are going to use the original vector elt for storing.
24831 // Accumulated smaller vector elements must be a multiple of the store size.
24832 assert (((NumElems * FromSz) % ToSz) == 0 &&
24833 "Unexpected ratio for truncating masked store");
24835 unsigned SizeRatio = FromSz / ToSz;
24836 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24838 // Create a type on which we perform the shuffle
24839 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24840 StVT.getScalarType(), NumElems*SizeRatio);
24842 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24844 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
24845 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24846 for (unsigned i = 0; i != NumElems; ++i)
24847 ShuffleVec[i] = i * SizeRatio;
24849 // Can't shuffle using an illegal type.
24850 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24851 && "WideVecVT should be legal");
24853 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24854 DAG.getUNDEF(WideVecVT),
24858 SDValue Mask = Mst->getMask();
24859 if (Mask.getValueType() == VT) {
24860 // Mask and original value have the same type
24861 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
24862 for (unsigned i = 0; i != NumElems; ++i)
24863 ShuffleVec[i] = i * SizeRatio;
24864 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24865 ShuffleVec[i] = NumElems*SizeRatio;
24866 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24867 DAG.getConstant(0, WideVecVT),
24871 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24872 unsigned WidenNumElts = NumElems*SizeRatio;
24873 unsigned MaskNumElts = VT.getVectorNumElements();
24874 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24877 unsigned NumConcat = WidenNumElts / MaskNumElts;
24878 SmallVector<SDValue, 16> Ops(NumConcat);
24879 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
24881 for (unsigned i = 1; i != NumConcat; ++i)
24884 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24887 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24888 NewMask, StVT, Mst->getMemOperand(), false);
24890 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24891 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24892 const X86Subtarget *Subtarget) {
24893 StoreSDNode *St = cast<StoreSDNode>(N);
24894 EVT VT = St->getValue().getValueType();
24895 EVT StVT = St->getMemoryVT();
24897 SDValue StoredVal = St->getOperand(1);
24898 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24900 // If we are saving a concatenation of two XMM registers and 32-byte stores
24901 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24902 unsigned Alignment = St->getAlignment();
24903 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24904 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24905 StVT == VT && !IsAligned) {
24906 unsigned NumElems = VT.getVectorNumElements();
24910 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24911 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24913 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24914 SDValue Ptr0 = St->getBasePtr();
24915 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24917 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24918 St->getPointerInfo(), St->isVolatile(),
24919 St->isNonTemporal(), Alignment);
24920 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24921 St->getPointerInfo(), St->isVolatile(),
24922 St->isNonTemporal(),
24923 std::min(16U, Alignment));
24924 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24927 // Optimize trunc store (of multiple scalars) to shuffle and store.
24928 // First, pack all of the elements in one place. Next, store to memory
24929 // in fewer chunks.
24930 if (St->isTruncatingStore() && VT.isVector()) {
24931 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24932 unsigned NumElems = VT.getVectorNumElements();
24933 assert(StVT != VT && "Cannot truncate to the same type");
24934 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24935 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24937 // From, To sizes and ElemCount must be pow of two
24938 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24939 // We are going to use the original vector elt for storing.
24940 // Accumulated smaller vector elements must be a multiple of the store size.
24941 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24943 unsigned SizeRatio = FromSz / ToSz;
24945 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24947 // Create a type on which we perform the shuffle
24948 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24949 StVT.getScalarType(), NumElems*SizeRatio);
24951 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24953 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24954 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24955 for (unsigned i = 0; i != NumElems; ++i)
24956 ShuffleVec[i] = i * SizeRatio;
24958 // Can't shuffle using an illegal type.
24959 if (!TLI.isTypeLegal(WideVecVT))
24962 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24963 DAG.getUNDEF(WideVecVT),
24965 // At this point all of the data is stored at the bottom of the
24966 // register. We now need to save it to mem.
24968 // Find the largest store unit
24969 MVT StoreType = MVT::i8;
24970 for (MVT Tp : MVT::integer_valuetypes()) {
24971 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24975 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24976 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24977 (64 <= NumElems * ToSz))
24978 StoreType = MVT::f64;
24980 // Bitcast the original vector into a vector of store-size units
24981 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24982 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24983 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24984 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24985 SmallVector<SDValue, 8> Chains;
24986 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24987 TLI.getPointerTy());
24988 SDValue Ptr = St->getBasePtr();
24990 // Perform one or more big stores into memory.
24991 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24992 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24993 StoreType, ShuffWide,
24994 DAG.getIntPtrConstant(i));
24995 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24996 St->getPointerInfo(), St->isVolatile(),
24997 St->isNonTemporal(), St->getAlignment());
24998 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24999 Chains.push_back(Ch);
25002 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25005 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25006 // the FP state in cases where an emms may be missing.
25007 // A preferable solution to the general problem is to figure out the right
25008 // places to insert EMMS. This qualifies as a quick hack.
25010 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25011 if (VT.getSizeInBits() != 64)
25014 const Function *F = DAG.getMachineFunction().getFunction();
25015 bool NoImplicitFloatOps = F->getAttributes().
25016 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
25017 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
25018 && Subtarget->hasSSE2();
25019 if ((VT.isVector() ||
25020 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25021 isa<LoadSDNode>(St->getValue()) &&
25022 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25023 St->getChain().hasOneUse() && !St->isVolatile()) {
25024 SDNode* LdVal = St->getValue().getNode();
25025 LoadSDNode *Ld = nullptr;
25026 int TokenFactorIndex = -1;
25027 SmallVector<SDValue, 8> Ops;
25028 SDNode* ChainVal = St->getChain().getNode();
25029 // Must be a store of a load. We currently handle two cases: the load
25030 // is a direct child, and it's under an intervening TokenFactor. It is
25031 // possible to dig deeper under nested TokenFactors.
25032 if (ChainVal == LdVal)
25033 Ld = cast<LoadSDNode>(St->getChain());
25034 else if (St->getValue().hasOneUse() &&
25035 ChainVal->getOpcode() == ISD::TokenFactor) {
25036 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25037 if (ChainVal->getOperand(i).getNode() == LdVal) {
25038 TokenFactorIndex = i;
25039 Ld = cast<LoadSDNode>(St->getValue());
25041 Ops.push_back(ChainVal->getOperand(i));
25045 if (!Ld || !ISD::isNormalLoad(Ld))
25048 // If this is not the MMX case, i.e. we are just turning i64 load/store
25049 // into f64 load/store, avoid the transformation if there are multiple
25050 // uses of the loaded value.
25051 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25056 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25057 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25059 if (Subtarget->is64Bit() || F64IsLegal) {
25060 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25061 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25062 Ld->getPointerInfo(), Ld->isVolatile(),
25063 Ld->isNonTemporal(), Ld->isInvariant(),
25064 Ld->getAlignment());
25065 SDValue NewChain = NewLd.getValue(1);
25066 if (TokenFactorIndex != -1) {
25067 Ops.push_back(NewChain);
25068 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25070 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25071 St->getPointerInfo(),
25072 St->isVolatile(), St->isNonTemporal(),
25073 St->getAlignment());
25076 // Otherwise, lower to two pairs of 32-bit loads / stores.
25077 SDValue LoAddr = Ld->getBasePtr();
25078 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25079 DAG.getConstant(4, MVT::i32));
25081 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25082 Ld->getPointerInfo(),
25083 Ld->isVolatile(), Ld->isNonTemporal(),
25084 Ld->isInvariant(), Ld->getAlignment());
25085 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25086 Ld->getPointerInfo().getWithOffset(4),
25087 Ld->isVolatile(), Ld->isNonTemporal(),
25089 MinAlign(Ld->getAlignment(), 4));
25091 SDValue NewChain = LoLd.getValue(1);
25092 if (TokenFactorIndex != -1) {
25093 Ops.push_back(LoLd);
25094 Ops.push_back(HiLd);
25095 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25098 LoAddr = St->getBasePtr();
25099 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25100 DAG.getConstant(4, MVT::i32));
25102 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25103 St->getPointerInfo(),
25104 St->isVolatile(), St->isNonTemporal(),
25105 St->getAlignment());
25106 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25107 St->getPointerInfo().getWithOffset(4),
25109 St->isNonTemporal(),
25110 MinAlign(St->getAlignment(), 4));
25111 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25116 /// Return 'true' if this vector operation is "horizontal"
25117 /// and return the operands for the horizontal operation in LHS and RHS. A
25118 /// horizontal operation performs the binary operation on successive elements
25119 /// of its first operand, then on successive elements of its second operand,
25120 /// returning the resulting values in a vector. For example, if
25121 /// A = < float a0, float a1, float a2, float a3 >
25123 /// B = < float b0, float b1, float b2, float b3 >
25124 /// then the result of doing a horizontal operation on A and B is
25125 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25126 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25127 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25128 /// set to A, RHS to B, and the routine returns 'true'.
25129 /// Note that the binary operation should have the property that if one of the
25130 /// operands is UNDEF then the result is UNDEF.
25131 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25132 // Look for the following pattern: if
25133 // A = < float a0, float a1, float a2, float a3 >
25134 // B = < float b0, float b1, float b2, float b3 >
25136 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25137 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25138 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25139 // which is A horizontal-op B.
25141 // At least one of the operands should be a vector shuffle.
25142 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25143 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25146 MVT VT = LHS.getSimpleValueType();
25148 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25149 "Unsupported vector type for horizontal add/sub");
25151 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25152 // operate independently on 128-bit lanes.
25153 unsigned NumElts = VT.getVectorNumElements();
25154 unsigned NumLanes = VT.getSizeInBits()/128;
25155 unsigned NumLaneElts = NumElts / NumLanes;
25156 assert((NumLaneElts % 2 == 0) &&
25157 "Vector type should have an even number of elements in each lane");
25158 unsigned HalfLaneElts = NumLaneElts/2;
25160 // View LHS in the form
25161 // LHS = VECTOR_SHUFFLE A, B, LMask
25162 // If LHS is not a shuffle then pretend it is the shuffle
25163 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25164 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25167 SmallVector<int, 16> LMask(NumElts);
25168 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25169 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25170 A = LHS.getOperand(0);
25171 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25172 B = LHS.getOperand(1);
25173 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25174 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25176 if (LHS.getOpcode() != ISD::UNDEF)
25178 for (unsigned i = 0; i != NumElts; ++i)
25182 // Likewise, view RHS in the form
25183 // RHS = VECTOR_SHUFFLE C, D, RMask
25185 SmallVector<int, 16> RMask(NumElts);
25186 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25187 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25188 C = RHS.getOperand(0);
25189 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25190 D = RHS.getOperand(1);
25191 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25192 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25194 if (RHS.getOpcode() != ISD::UNDEF)
25196 for (unsigned i = 0; i != NumElts; ++i)
25200 // Check that the shuffles are both shuffling the same vectors.
25201 if (!(A == C && B == D) && !(A == D && B == C))
25204 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25205 if (!A.getNode() && !B.getNode())
25208 // If A and B occur in reverse order in RHS, then "swap" them (which means
25209 // rewriting the mask).
25211 CommuteVectorShuffleMask(RMask, NumElts);
25213 // At this point LHS and RHS are equivalent to
25214 // LHS = VECTOR_SHUFFLE A, B, LMask
25215 // RHS = VECTOR_SHUFFLE A, B, RMask
25216 // Check that the masks correspond to performing a horizontal operation.
25217 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25218 for (unsigned i = 0; i != NumLaneElts; ++i) {
25219 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25221 // Ignore any UNDEF components.
25222 if (LIdx < 0 || RIdx < 0 ||
25223 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25224 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25227 // Check that successive elements are being operated on. If not, this is
25228 // not a horizontal operation.
25229 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25230 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25231 if (!(LIdx == Index && RIdx == Index + 1) &&
25232 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25237 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25238 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25242 /// Do target-specific dag combines on floating point adds.
25243 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25244 const X86Subtarget *Subtarget) {
25245 EVT VT = N->getValueType(0);
25246 SDValue LHS = N->getOperand(0);
25247 SDValue RHS = N->getOperand(1);
25249 // Try to synthesize horizontal adds from adds of shuffles.
25250 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25251 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25252 isHorizontalBinOp(LHS, RHS, true))
25253 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25257 /// Do target-specific dag combines on floating point subs.
25258 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25259 const X86Subtarget *Subtarget) {
25260 EVT VT = N->getValueType(0);
25261 SDValue LHS = N->getOperand(0);
25262 SDValue RHS = N->getOperand(1);
25264 // Try to synthesize horizontal subs from subs of shuffles.
25265 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25266 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25267 isHorizontalBinOp(LHS, RHS, false))
25268 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25272 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25273 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
25274 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25275 // F[X]OR(0.0, x) -> x
25276 // F[X]OR(x, 0.0) -> x
25277 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25278 if (C->getValueAPF().isPosZero())
25279 return N->getOperand(1);
25280 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25281 if (C->getValueAPF().isPosZero())
25282 return N->getOperand(0);
25286 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25287 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25288 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25290 // Only perform optimizations if UnsafeMath is used.
25291 if (!DAG.getTarget().Options.UnsafeFPMath)
25294 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25295 // into FMINC and FMAXC, which are Commutative operations.
25296 unsigned NewOp = 0;
25297 switch (N->getOpcode()) {
25298 default: llvm_unreachable("unknown opcode");
25299 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25300 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25303 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25304 N->getOperand(0), N->getOperand(1));
25307 /// Do target-specific dag combines on X86ISD::FAND nodes.
25308 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25309 // FAND(0.0, x) -> 0.0
25310 // FAND(x, 0.0) -> 0.0
25311 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25312 if (C->getValueAPF().isPosZero())
25313 return N->getOperand(0);
25314 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25315 if (C->getValueAPF().isPosZero())
25316 return N->getOperand(1);
25320 /// Do target-specific dag combines on X86ISD::FANDN nodes
25321 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25322 // FANDN(x, 0.0) -> 0.0
25323 // FANDN(0.0, x) -> x
25324 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25325 if (C->getValueAPF().isPosZero())
25326 return N->getOperand(1);
25327 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25328 if (C->getValueAPF().isPosZero())
25329 return N->getOperand(1);
25333 static SDValue PerformBTCombine(SDNode *N,
25335 TargetLowering::DAGCombinerInfo &DCI) {
25336 // BT ignores high bits in the bit index operand.
25337 SDValue Op1 = N->getOperand(1);
25338 if (Op1.hasOneUse()) {
25339 unsigned BitWidth = Op1.getValueSizeInBits();
25340 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25341 APInt KnownZero, KnownOne;
25342 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25343 !DCI.isBeforeLegalizeOps());
25344 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25345 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25346 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25347 DCI.CommitTargetLoweringOpt(TLO);
25352 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25353 SDValue Op = N->getOperand(0);
25354 if (Op.getOpcode() == ISD::BITCAST)
25355 Op = Op.getOperand(0);
25356 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25357 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25358 VT.getVectorElementType().getSizeInBits() ==
25359 OpVT.getVectorElementType().getSizeInBits()) {
25360 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25365 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25366 const X86Subtarget *Subtarget) {
25367 EVT VT = N->getValueType(0);
25368 if (!VT.isVector())
25371 SDValue N0 = N->getOperand(0);
25372 SDValue N1 = N->getOperand(1);
25373 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25376 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25377 // both SSE and AVX2 since there is no sign-extended shift right
25378 // operation on a vector with 64-bit elements.
25379 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25380 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25381 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25382 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25383 SDValue N00 = N0.getOperand(0);
25385 // EXTLOAD has a better solution on AVX2,
25386 // it may be replaced with X86ISD::VSEXT node.
25387 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25388 if (!ISD::isNormalLoad(N00.getNode()))
25391 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25392 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25394 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25400 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25401 TargetLowering::DAGCombinerInfo &DCI,
25402 const X86Subtarget *Subtarget) {
25403 SDValue N0 = N->getOperand(0);
25404 EVT VT = N->getValueType(0);
25406 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25407 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25408 // This exposes the sext to the sdivrem lowering, so that it directly extends
25409 // from AH (which we otherwise need to do contortions to access).
25410 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25411 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25413 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25414 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25415 N0.getOperand(0), N0.getOperand(1));
25416 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25417 return R.getValue(1);
25420 if (!DCI.isBeforeLegalizeOps())
25423 if (!Subtarget->hasFp256())
25426 if (VT.isVector() && VT.getSizeInBits() == 256) {
25427 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25435 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25436 const X86Subtarget* Subtarget) {
25438 EVT VT = N->getValueType(0);
25440 // Let legalize expand this if it isn't a legal type yet.
25441 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25444 EVT ScalarVT = VT.getScalarType();
25445 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25446 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25449 SDValue A = N->getOperand(0);
25450 SDValue B = N->getOperand(1);
25451 SDValue C = N->getOperand(2);
25453 bool NegA = (A.getOpcode() == ISD::FNEG);
25454 bool NegB = (B.getOpcode() == ISD::FNEG);
25455 bool NegC = (C.getOpcode() == ISD::FNEG);
25457 // Negative multiplication when NegA xor NegB
25458 bool NegMul = (NegA != NegB);
25460 A = A.getOperand(0);
25462 B = B.getOperand(0);
25464 C = C.getOperand(0);
25468 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25470 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25472 return DAG.getNode(Opcode, dl, VT, A, B, C);
25475 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25476 TargetLowering::DAGCombinerInfo &DCI,
25477 const X86Subtarget *Subtarget) {
25478 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25479 // (and (i32 x86isd::setcc_carry), 1)
25480 // This eliminates the zext. This transformation is necessary because
25481 // ISD::SETCC is always legalized to i8.
25483 SDValue N0 = N->getOperand(0);
25484 EVT VT = N->getValueType(0);
25486 if (N0.getOpcode() == ISD::AND &&
25488 N0.getOperand(0).hasOneUse()) {
25489 SDValue N00 = N0.getOperand(0);
25490 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25491 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25492 if (!C || C->getZExtValue() != 1)
25494 return DAG.getNode(ISD::AND, dl, VT,
25495 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25496 N00.getOperand(0), N00.getOperand(1)),
25497 DAG.getConstant(1, VT));
25501 if (N0.getOpcode() == ISD::TRUNCATE &&
25503 N0.getOperand(0).hasOneUse()) {
25504 SDValue N00 = N0.getOperand(0);
25505 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25506 return DAG.getNode(ISD::AND, dl, VT,
25507 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25508 N00.getOperand(0), N00.getOperand(1)),
25509 DAG.getConstant(1, VT));
25512 if (VT.is256BitVector()) {
25513 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25518 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25519 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25520 // This exposes the zext to the udivrem lowering, so that it directly extends
25521 // from AH (which we otherwise need to do contortions to access).
25522 if (N0.getOpcode() == ISD::UDIVREM &&
25523 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25524 (VT == MVT::i32 || VT == MVT::i64)) {
25525 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25526 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25527 N0.getOperand(0), N0.getOperand(1));
25528 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25529 return R.getValue(1);
25535 // Optimize x == -y --> x+y == 0
25536 // x != -y --> x+y != 0
25537 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25538 const X86Subtarget* Subtarget) {
25539 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25540 SDValue LHS = N->getOperand(0);
25541 SDValue RHS = N->getOperand(1);
25542 EVT VT = N->getValueType(0);
25545 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25547 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25548 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25549 LHS.getValueType(), RHS, LHS.getOperand(1));
25550 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25551 addV, DAG.getConstant(0, addV.getValueType()), CC);
25553 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25554 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25555 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25556 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25557 RHS.getValueType(), LHS, RHS.getOperand(1));
25558 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25559 addV, DAG.getConstant(0, addV.getValueType()), CC);
25562 if (VT.getScalarType() == MVT::i1) {
25563 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25564 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25565 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25566 if (!IsSEXT0 && !IsVZero0)
25568 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25569 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25570 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25572 if (!IsSEXT1 && !IsVZero1)
25575 if (IsSEXT0 && IsVZero1) {
25576 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25577 if (CC == ISD::SETEQ)
25578 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25579 return LHS.getOperand(0);
25581 if (IsSEXT1 && IsVZero0) {
25582 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25583 if (CC == ISD::SETEQ)
25584 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25585 return RHS.getOperand(0);
25592 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25593 const X86Subtarget *Subtarget) {
25595 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25596 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25597 "X86insertps is only defined for v4x32");
25599 SDValue Ld = N->getOperand(1);
25600 if (MayFoldLoad(Ld)) {
25601 // Extract the countS bits from the immediate so we can get the proper
25602 // address when narrowing the vector load to a specific element.
25603 // When the second source op is a memory address, interps doesn't use
25604 // countS and just gets an f32 from that address.
25605 unsigned DestIndex =
25606 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25607 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25611 // Create this as a scalar to vector to match the instruction pattern.
25612 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25613 // countS bits are ignored when loading from memory on insertps, which
25614 // means we don't need to explicitly set them to 0.
25615 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25616 LoadScalarToVector, N->getOperand(2));
25619 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25620 // as "sbb reg,reg", since it can be extended without zext and produces
25621 // an all-ones bit which is more useful than 0/1 in some cases.
25622 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25625 return DAG.getNode(ISD::AND, DL, VT,
25626 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25627 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25628 DAG.getConstant(1, VT));
25629 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25630 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25631 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25632 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25635 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25636 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25637 TargetLowering::DAGCombinerInfo &DCI,
25638 const X86Subtarget *Subtarget) {
25640 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25641 SDValue EFLAGS = N->getOperand(1);
25643 if (CC == X86::COND_A) {
25644 // Try to convert COND_A into COND_B in an attempt to facilitate
25645 // materializing "setb reg".
25647 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25648 // cannot take an immediate as its first operand.
25650 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25651 EFLAGS.getValueType().isInteger() &&
25652 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25653 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25654 EFLAGS.getNode()->getVTList(),
25655 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25656 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25657 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25661 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25662 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25664 if (CC == X86::COND_B)
25665 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25669 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25670 if (Flags.getNode()) {
25671 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25672 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25678 // Optimize branch condition evaluation.
25680 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25681 TargetLowering::DAGCombinerInfo &DCI,
25682 const X86Subtarget *Subtarget) {
25684 SDValue Chain = N->getOperand(0);
25685 SDValue Dest = N->getOperand(1);
25686 SDValue EFLAGS = N->getOperand(3);
25687 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25691 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25692 if (Flags.getNode()) {
25693 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25694 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25701 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25702 SelectionDAG &DAG) {
25703 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25704 // optimize away operation when it's from a constant.
25706 // The general transformation is:
25707 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25708 // AND(VECTOR_CMP(x,y), constant2)
25709 // constant2 = UNARYOP(constant)
25711 // Early exit if this isn't a vector operation, the operand of the
25712 // unary operation isn't a bitwise AND, or if the sizes of the operations
25713 // aren't the same.
25714 EVT VT = N->getValueType(0);
25715 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25716 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25717 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25720 // Now check that the other operand of the AND is a constant. We could
25721 // make the transformation for non-constant splats as well, but it's unclear
25722 // that would be a benefit as it would not eliminate any operations, just
25723 // perform one more step in scalar code before moving to the vector unit.
25724 if (BuildVectorSDNode *BV =
25725 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25726 // Bail out if the vector isn't a constant.
25727 if (!BV->isConstant())
25730 // Everything checks out. Build up the new and improved node.
25732 EVT IntVT = BV->getValueType(0);
25733 // Create a new constant of the appropriate type for the transformed
25735 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25736 // The AND node needs bitcasts to/from an integer vector type around it.
25737 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25738 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25739 N->getOperand(0)->getOperand(0), MaskConst);
25740 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25747 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25748 const X86TargetLowering *XTLI) {
25749 // First try to optimize away the conversion entirely when it's
25750 // conditionally from a constant. Vectors only.
25751 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25752 if (Res != SDValue())
25755 // Now move on to more general possibilities.
25756 SDValue Op0 = N->getOperand(0);
25757 EVT InVT = Op0->getValueType(0);
25759 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25760 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25762 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25763 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25764 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25767 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25768 // a 32-bit target where SSE doesn't support i64->FP operations.
25769 if (Op0.getOpcode() == ISD::LOAD) {
25770 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25771 EVT VT = Ld->getValueType(0);
25772 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25773 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25774 !XTLI->getSubtarget()->is64Bit() &&
25776 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25777 Ld->getChain(), Op0, DAG);
25778 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25785 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25786 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25787 X86TargetLowering::DAGCombinerInfo &DCI) {
25788 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25789 // the result is either zero or one (depending on the input carry bit).
25790 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25791 if (X86::isZeroNode(N->getOperand(0)) &&
25792 X86::isZeroNode(N->getOperand(1)) &&
25793 // We don't have a good way to replace an EFLAGS use, so only do this when
25795 SDValue(N, 1).use_empty()) {
25797 EVT VT = N->getValueType(0);
25798 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25799 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25800 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25801 DAG.getConstant(X86::COND_B,MVT::i8),
25803 DAG.getConstant(1, VT));
25804 return DCI.CombineTo(N, Res1, CarryOut);
25810 // fold (add Y, (sete X, 0)) -> adc 0, Y
25811 // (add Y, (setne X, 0)) -> sbb -1, Y
25812 // (sub (sete X, 0), Y) -> sbb 0, Y
25813 // (sub (setne X, 0), Y) -> adc -1, Y
25814 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25817 // Look through ZExts.
25818 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25819 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25822 SDValue SetCC = Ext.getOperand(0);
25823 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25826 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25827 if (CC != X86::COND_E && CC != X86::COND_NE)
25830 SDValue Cmp = SetCC.getOperand(1);
25831 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25832 !X86::isZeroNode(Cmp.getOperand(1)) ||
25833 !Cmp.getOperand(0).getValueType().isInteger())
25836 SDValue CmpOp0 = Cmp.getOperand(0);
25837 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25838 DAG.getConstant(1, CmpOp0.getValueType()));
25840 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25841 if (CC == X86::COND_NE)
25842 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25843 DL, OtherVal.getValueType(), OtherVal,
25844 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25845 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25846 DL, OtherVal.getValueType(), OtherVal,
25847 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25850 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25851 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25852 const X86Subtarget *Subtarget) {
25853 EVT VT = N->getValueType(0);
25854 SDValue Op0 = N->getOperand(0);
25855 SDValue Op1 = N->getOperand(1);
25857 // Try to synthesize horizontal adds from adds of shuffles.
25858 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25859 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25860 isHorizontalBinOp(Op0, Op1, true))
25861 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25863 return OptimizeConditionalInDecrement(N, DAG);
25866 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25867 const X86Subtarget *Subtarget) {
25868 SDValue Op0 = N->getOperand(0);
25869 SDValue Op1 = N->getOperand(1);
25871 // X86 can't encode an immediate LHS of a sub. See if we can push the
25872 // negation into a preceding instruction.
25873 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25874 // If the RHS of the sub is a XOR with one use and a constant, invert the
25875 // immediate. Then add one to the LHS of the sub so we can turn
25876 // X-Y -> X+~Y+1, saving one register.
25877 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25878 isa<ConstantSDNode>(Op1.getOperand(1))) {
25879 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25880 EVT VT = Op0.getValueType();
25881 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25883 DAG.getConstant(~XorC, VT));
25884 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25885 DAG.getConstant(C->getAPIntValue()+1, VT));
25889 // Try to synthesize horizontal adds from adds of shuffles.
25890 EVT VT = N->getValueType(0);
25891 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25892 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25893 isHorizontalBinOp(Op0, Op1, true))
25894 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25896 return OptimizeConditionalInDecrement(N, DAG);
25899 /// performVZEXTCombine - Performs build vector combines
25900 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25901 TargetLowering::DAGCombinerInfo &DCI,
25902 const X86Subtarget *Subtarget) {
25904 MVT VT = N->getSimpleValueType(0);
25905 SDValue Op = N->getOperand(0);
25906 MVT OpVT = Op.getSimpleValueType();
25907 MVT OpEltVT = OpVT.getVectorElementType();
25908 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25910 // (vzext (bitcast (vzext (x)) -> (vzext x)
25912 while (V.getOpcode() == ISD::BITCAST)
25913 V = V.getOperand(0);
25915 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25916 MVT InnerVT = V.getSimpleValueType();
25917 MVT InnerEltVT = InnerVT.getVectorElementType();
25919 // If the element sizes match exactly, we can just do one larger vzext. This
25920 // is always an exact type match as vzext operates on integer types.
25921 if (OpEltVT == InnerEltVT) {
25922 assert(OpVT == InnerVT && "Types must match for vzext!");
25923 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25926 // The only other way we can combine them is if only a single element of the
25927 // inner vzext is used in the input to the outer vzext.
25928 if (InnerEltVT.getSizeInBits() < InputBits)
25931 // In this case, the inner vzext is completely dead because we're going to
25932 // only look at bits inside of the low element. Just do the outer vzext on
25933 // a bitcast of the input to the inner.
25934 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25935 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25938 // Check if we can bypass extracting and re-inserting an element of an input
25939 // vector. Essentialy:
25940 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25941 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25942 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25943 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25944 SDValue ExtractedV = V.getOperand(0);
25945 SDValue OrigV = ExtractedV.getOperand(0);
25946 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25947 if (ExtractIdx->getZExtValue() == 0) {
25948 MVT OrigVT = OrigV.getSimpleValueType();
25949 // Extract a subvector if necessary...
25950 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25951 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25952 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25953 OrigVT.getVectorNumElements() / Ratio);
25954 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25955 DAG.getIntPtrConstant(0));
25957 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25958 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25965 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25966 DAGCombinerInfo &DCI) const {
25967 SelectionDAG &DAG = DCI.DAG;
25968 switch (N->getOpcode()) {
25970 case ISD::EXTRACT_VECTOR_ELT:
25971 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25974 case X86ISD::SHRUNKBLEND:
25975 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25976 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25977 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25978 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25979 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25980 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25983 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25984 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25985 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25986 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25987 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25988 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
25989 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25990 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
25991 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25992 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25993 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25995 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25997 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25998 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25999 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26000 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26001 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26002 case ISD::ANY_EXTEND:
26003 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26004 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26005 case ISD::SIGN_EXTEND_INREG:
26006 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26007 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
26008 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26009 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26010 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26011 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26012 case X86ISD::SHUFP: // Handle all target specific shuffles
26013 case X86ISD::PALIGNR:
26014 case X86ISD::UNPCKH:
26015 case X86ISD::UNPCKL:
26016 case X86ISD::MOVHLPS:
26017 case X86ISD::MOVLHPS:
26018 case X86ISD::PSHUFB:
26019 case X86ISD::PSHUFD:
26020 case X86ISD::PSHUFHW:
26021 case X86ISD::PSHUFLW:
26022 case X86ISD::MOVSS:
26023 case X86ISD::MOVSD:
26024 case X86ISD::VPERMILPI:
26025 case X86ISD::VPERM2X128:
26026 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26027 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26028 case ISD::INTRINSIC_WO_CHAIN:
26029 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
26030 case X86ISD::INSERTPS: {
26031 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26032 return PerformINSERTPSCombine(N, DAG, Subtarget);
26035 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
26041 /// isTypeDesirableForOp - Return true if the target has native support for
26042 /// the specified value type and it is 'desirable' to use the type for the
26043 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26044 /// instruction encodings are longer and some i16 instructions are slow.
26045 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26046 if (!isTypeLegal(VT))
26048 if (VT != MVT::i16)
26055 case ISD::SIGN_EXTEND:
26056 case ISD::ZERO_EXTEND:
26057 case ISD::ANY_EXTEND:
26070 /// IsDesirableToPromoteOp - This method query the target whether it is
26071 /// beneficial for dag combiner to promote the specified node. If true, it
26072 /// should return the desired promotion type by reference.
26073 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26074 EVT VT = Op.getValueType();
26075 if (VT != MVT::i16)
26078 bool Promote = false;
26079 bool Commute = false;
26080 switch (Op.getOpcode()) {
26083 LoadSDNode *LD = cast<LoadSDNode>(Op);
26084 // If the non-extending load has a single use and it's not live out, then it
26085 // might be folded.
26086 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26087 Op.hasOneUse()*/) {
26088 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26089 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26090 // The only case where we'd want to promote LOAD (rather then it being
26091 // promoted as an operand is when it's only use is liveout.
26092 if (UI->getOpcode() != ISD::CopyToReg)
26099 case ISD::SIGN_EXTEND:
26100 case ISD::ZERO_EXTEND:
26101 case ISD::ANY_EXTEND:
26106 SDValue N0 = Op.getOperand(0);
26107 // Look out for (store (shl (load), x)).
26108 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26121 SDValue N0 = Op.getOperand(0);
26122 SDValue N1 = Op.getOperand(1);
26123 if (!Commute && MayFoldLoad(N1))
26125 // Avoid disabling potential load folding opportunities.
26126 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26128 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26138 //===----------------------------------------------------------------------===//
26139 // X86 Inline Assembly Support
26140 //===----------------------------------------------------------------------===//
26143 // Helper to match a string separated by whitespace.
26144 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
26145 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
26147 for (unsigned i = 0, e = args.size(); i != e; ++i) {
26148 StringRef piece(*args[i]);
26149 if (!s.startswith(piece)) // Check if the piece matches.
26152 s = s.substr(piece.size());
26153 StringRef::size_type pos = s.find_first_not_of(" \t");
26154 if (pos == 0) // We matched a prefix.
26162 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
26165 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26167 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26168 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26169 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26170 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26172 if (AsmPieces.size() == 3)
26174 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26181 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26182 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26184 std::string AsmStr = IA->getAsmString();
26186 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26187 if (!Ty || Ty->getBitWidth() % 16 != 0)
26190 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26191 SmallVector<StringRef, 4> AsmPieces;
26192 SplitString(AsmStr, AsmPieces, ";\n");
26194 switch (AsmPieces.size()) {
26195 default: return false;
26197 // FIXME: this should verify that we are targeting a 486 or better. If not,
26198 // we will turn this bswap into something that will be lowered to logical
26199 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26200 // lower so don't worry about this.
26202 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
26203 matchAsm(AsmPieces[0], "bswapl", "$0") ||
26204 matchAsm(AsmPieces[0], "bswapq", "$0") ||
26205 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
26206 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
26207 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
26208 // No need to check constraints, nothing other than the equivalent of
26209 // "=r,0" would be valid here.
26210 return IntrinsicLowering::LowerToByteSwap(CI);
26213 // rorw $$8, ${0:w} --> llvm.bswap.i16
26214 if (CI->getType()->isIntegerTy(16) &&
26215 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26216 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
26217 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
26219 const std::string &ConstraintsStr = IA->getConstraintString();
26220 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26221 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26222 if (clobbersFlagRegisters(AsmPieces))
26223 return IntrinsicLowering::LowerToByteSwap(CI);
26227 if (CI->getType()->isIntegerTy(32) &&
26228 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26229 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
26230 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
26231 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
26233 const std::string &ConstraintsStr = IA->getConstraintString();
26234 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26235 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26236 if (clobbersFlagRegisters(AsmPieces))
26237 return IntrinsicLowering::LowerToByteSwap(CI);
26240 if (CI->getType()->isIntegerTy(64)) {
26241 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26242 if (Constraints.size() >= 2 &&
26243 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26244 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26245 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26246 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
26247 matchAsm(AsmPieces[1], "bswap", "%edx") &&
26248 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
26249 return IntrinsicLowering::LowerToByteSwap(CI);
26257 /// getConstraintType - Given a constraint letter, return the type of
26258 /// constraint it is for this target.
26259 X86TargetLowering::ConstraintType
26260 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
26261 if (Constraint.size() == 1) {
26262 switch (Constraint[0]) {
26273 return C_RegisterClass;
26297 return TargetLowering::getConstraintType(Constraint);
26300 /// Examine constraint type and operand type and determine a weight value.
26301 /// This object must already have been set up with the operand type
26302 /// and the current alternative constraint selected.
26303 TargetLowering::ConstraintWeight
26304 X86TargetLowering::getSingleConstraintMatchWeight(
26305 AsmOperandInfo &info, const char *constraint) const {
26306 ConstraintWeight weight = CW_Invalid;
26307 Value *CallOperandVal = info.CallOperandVal;
26308 // If we don't have a value, we can't do a match,
26309 // but allow it at the lowest weight.
26310 if (!CallOperandVal)
26312 Type *type = CallOperandVal->getType();
26313 // Look at the constraint type.
26314 switch (*constraint) {
26316 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26327 if (CallOperandVal->getType()->isIntegerTy())
26328 weight = CW_SpecificReg;
26333 if (type->isFloatingPointTy())
26334 weight = CW_SpecificReg;
26337 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26338 weight = CW_SpecificReg;
26342 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26343 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26344 weight = CW_Register;
26347 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26348 if (C->getZExtValue() <= 31)
26349 weight = CW_Constant;
26353 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26354 if (C->getZExtValue() <= 63)
26355 weight = CW_Constant;
26359 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26360 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26361 weight = CW_Constant;
26365 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26366 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26367 weight = CW_Constant;
26371 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26372 if (C->getZExtValue() <= 3)
26373 weight = CW_Constant;
26377 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26378 if (C->getZExtValue() <= 0xff)
26379 weight = CW_Constant;
26384 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26385 weight = CW_Constant;
26389 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26390 if ((C->getSExtValue() >= -0x80000000LL) &&
26391 (C->getSExtValue() <= 0x7fffffffLL))
26392 weight = CW_Constant;
26396 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26397 if (C->getZExtValue() <= 0xffffffff)
26398 weight = CW_Constant;
26405 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26406 /// with another that has more specific requirements based on the type of the
26407 /// corresponding operand.
26408 const char *X86TargetLowering::
26409 LowerXConstraint(EVT ConstraintVT) const {
26410 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26411 // 'f' like normal targets.
26412 if (ConstraintVT.isFloatingPoint()) {
26413 if (Subtarget->hasSSE2())
26415 if (Subtarget->hasSSE1())
26419 return TargetLowering::LowerXConstraint(ConstraintVT);
26422 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26423 /// vector. If it is invalid, don't add anything to Ops.
26424 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26425 std::string &Constraint,
26426 std::vector<SDValue>&Ops,
26427 SelectionDAG &DAG) const {
26430 // Only support length 1 constraints for now.
26431 if (Constraint.length() > 1) return;
26433 char ConstraintLetter = Constraint[0];
26434 switch (ConstraintLetter) {
26437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26438 if (C->getZExtValue() <= 31) {
26439 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26445 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26446 if (C->getZExtValue() <= 63) {
26447 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26454 if (isInt<8>(C->getSExtValue())) {
26455 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26461 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26462 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26463 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26464 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
26470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26471 if (C->getZExtValue() <= 3) {
26472 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26479 if (C->getZExtValue() <= 255) {
26480 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26487 if (C->getZExtValue() <= 127) {
26488 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26494 // 32-bit signed value
26495 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26496 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26497 C->getSExtValue())) {
26498 // Widen to 64 bits here to get it sign extended.
26499 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26502 // FIXME gcc accepts some relocatable values here too, but only in certain
26503 // memory models; it's complicated.
26508 // 32-bit unsigned value
26509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26510 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26511 C->getZExtValue())) {
26512 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26516 // FIXME gcc accepts some relocatable values here too, but only in certain
26517 // memory models; it's complicated.
26521 // Literal immediates are always ok.
26522 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26523 // Widen to 64 bits here to get it sign extended.
26524 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26528 // In any sort of PIC mode addresses need to be computed at runtime by
26529 // adding in a register or some sort of table lookup. These can't
26530 // be used as immediates.
26531 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26534 // If we are in non-pic codegen mode, we allow the address of a global (with
26535 // an optional displacement) to be used with 'i'.
26536 GlobalAddressSDNode *GA = nullptr;
26537 int64_t Offset = 0;
26539 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26541 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26542 Offset += GA->getOffset();
26544 } else if (Op.getOpcode() == ISD::ADD) {
26545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26546 Offset += C->getZExtValue();
26547 Op = Op.getOperand(0);
26550 } else if (Op.getOpcode() == ISD::SUB) {
26551 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26552 Offset += -C->getZExtValue();
26553 Op = Op.getOperand(0);
26558 // Otherwise, this isn't something we can handle, reject it.
26562 const GlobalValue *GV = GA->getGlobal();
26563 // If we require an extra load to get this address, as in PIC mode, we
26564 // can't accept it.
26565 if (isGlobalStubReference(
26566 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26569 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26570 GA->getValueType(0), Offset);
26575 if (Result.getNode()) {
26576 Ops.push_back(Result);
26579 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26582 std::pair<unsigned, const TargetRegisterClass*>
26583 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26585 // First, see if this is a constraint that directly corresponds to an LLVM
26587 if (Constraint.size() == 1) {
26588 // GCC Constraint Letters
26589 switch (Constraint[0]) {
26591 // TODO: Slight differences here in allocation order and leaving
26592 // RIP in the class. Do they matter any more here than they do
26593 // in the normal allocation?
26594 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26595 if (Subtarget->is64Bit()) {
26596 if (VT == MVT::i32 || VT == MVT::f32)
26597 return std::make_pair(0U, &X86::GR32RegClass);
26598 if (VT == MVT::i16)
26599 return std::make_pair(0U, &X86::GR16RegClass);
26600 if (VT == MVT::i8 || VT == MVT::i1)
26601 return std::make_pair(0U, &X86::GR8RegClass);
26602 if (VT == MVT::i64 || VT == MVT::f64)
26603 return std::make_pair(0U, &X86::GR64RegClass);
26606 // 32-bit fallthrough
26607 case 'Q': // Q_REGS
26608 if (VT == MVT::i32 || VT == MVT::f32)
26609 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26610 if (VT == MVT::i16)
26611 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26612 if (VT == MVT::i8 || VT == MVT::i1)
26613 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26614 if (VT == MVT::i64)
26615 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26617 case 'r': // GENERAL_REGS
26618 case 'l': // INDEX_REGS
26619 if (VT == MVT::i8 || VT == MVT::i1)
26620 return std::make_pair(0U, &X86::GR8RegClass);
26621 if (VT == MVT::i16)
26622 return std::make_pair(0U, &X86::GR16RegClass);
26623 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26624 return std::make_pair(0U, &X86::GR32RegClass);
26625 return std::make_pair(0U, &X86::GR64RegClass);
26626 case 'R': // LEGACY_REGS
26627 if (VT == MVT::i8 || VT == MVT::i1)
26628 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26629 if (VT == MVT::i16)
26630 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26631 if (VT == MVT::i32 || !Subtarget->is64Bit())
26632 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26633 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26634 case 'f': // FP Stack registers.
26635 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26636 // value to the correct fpstack register class.
26637 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26638 return std::make_pair(0U, &X86::RFP32RegClass);
26639 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26640 return std::make_pair(0U, &X86::RFP64RegClass);
26641 return std::make_pair(0U, &X86::RFP80RegClass);
26642 case 'y': // MMX_REGS if MMX allowed.
26643 if (!Subtarget->hasMMX()) break;
26644 return std::make_pair(0U, &X86::VR64RegClass);
26645 case 'Y': // SSE_REGS if SSE2 allowed
26646 if (!Subtarget->hasSSE2()) break;
26648 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26649 if (!Subtarget->hasSSE1()) break;
26651 switch (VT.SimpleTy) {
26653 // Scalar SSE types.
26656 return std::make_pair(0U, &X86::FR32RegClass);
26659 return std::make_pair(0U, &X86::FR64RegClass);
26667 return std::make_pair(0U, &X86::VR128RegClass);
26675 return std::make_pair(0U, &X86::VR256RegClass);
26680 return std::make_pair(0U, &X86::VR512RegClass);
26686 // Use the default implementation in TargetLowering to convert the register
26687 // constraint into a member of a register class.
26688 std::pair<unsigned, const TargetRegisterClass*> Res;
26689 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26691 // Not found as a standard register?
26693 // Map st(0) -> st(7) -> ST0
26694 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26695 tolower(Constraint[1]) == 's' &&
26696 tolower(Constraint[2]) == 't' &&
26697 Constraint[3] == '(' &&
26698 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26699 Constraint[5] == ')' &&
26700 Constraint[6] == '}') {
26702 Res.first = X86::FP0+Constraint[4]-'0';
26703 Res.second = &X86::RFP80RegClass;
26707 // GCC allows "st(0)" to be called just plain "st".
26708 if (StringRef("{st}").equals_lower(Constraint)) {
26709 Res.first = X86::FP0;
26710 Res.second = &X86::RFP80RegClass;
26715 if (StringRef("{flags}").equals_lower(Constraint)) {
26716 Res.first = X86::EFLAGS;
26717 Res.second = &X86::CCRRegClass;
26721 // 'A' means EAX + EDX.
26722 if (Constraint == "A") {
26723 Res.first = X86::EAX;
26724 Res.second = &X86::GR32_ADRegClass;
26730 // Otherwise, check to see if this is a register class of the wrong value
26731 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26732 // turn into {ax},{dx}.
26733 if (Res.second->hasType(VT))
26734 return Res; // Correct type already, nothing to do.
26736 // All of the single-register GCC register classes map their values onto
26737 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26738 // really want an 8-bit or 32-bit register, map to the appropriate register
26739 // class and return the appropriate register.
26740 if (Res.second == &X86::GR16RegClass) {
26741 if (VT == MVT::i8 || VT == MVT::i1) {
26742 unsigned DestReg = 0;
26743 switch (Res.first) {
26745 case X86::AX: DestReg = X86::AL; break;
26746 case X86::DX: DestReg = X86::DL; break;
26747 case X86::CX: DestReg = X86::CL; break;
26748 case X86::BX: DestReg = X86::BL; break;
26751 Res.first = DestReg;
26752 Res.second = &X86::GR8RegClass;
26754 } else if (VT == MVT::i32 || VT == MVT::f32) {
26755 unsigned DestReg = 0;
26756 switch (Res.first) {
26758 case X86::AX: DestReg = X86::EAX; break;
26759 case X86::DX: DestReg = X86::EDX; break;
26760 case X86::CX: DestReg = X86::ECX; break;
26761 case X86::BX: DestReg = X86::EBX; break;
26762 case X86::SI: DestReg = X86::ESI; break;
26763 case X86::DI: DestReg = X86::EDI; break;
26764 case X86::BP: DestReg = X86::EBP; break;
26765 case X86::SP: DestReg = X86::ESP; break;
26768 Res.first = DestReg;
26769 Res.second = &X86::GR32RegClass;
26771 } else if (VT == MVT::i64 || VT == MVT::f64) {
26772 unsigned DestReg = 0;
26773 switch (Res.first) {
26775 case X86::AX: DestReg = X86::RAX; break;
26776 case X86::DX: DestReg = X86::RDX; break;
26777 case X86::CX: DestReg = X86::RCX; break;
26778 case X86::BX: DestReg = X86::RBX; break;
26779 case X86::SI: DestReg = X86::RSI; break;
26780 case X86::DI: DestReg = X86::RDI; break;
26781 case X86::BP: DestReg = X86::RBP; break;
26782 case X86::SP: DestReg = X86::RSP; break;
26785 Res.first = DestReg;
26786 Res.second = &X86::GR64RegClass;
26789 } else if (Res.second == &X86::FR32RegClass ||
26790 Res.second == &X86::FR64RegClass ||
26791 Res.second == &X86::VR128RegClass ||
26792 Res.second == &X86::VR256RegClass ||
26793 Res.second == &X86::FR32XRegClass ||
26794 Res.second == &X86::FR64XRegClass ||
26795 Res.second == &X86::VR128XRegClass ||
26796 Res.second == &X86::VR256XRegClass ||
26797 Res.second == &X86::VR512RegClass) {
26798 // Handle references to XMM physical registers that got mapped into the
26799 // wrong class. This can happen with constraints like {xmm0} where the
26800 // target independent register mapper will just pick the first match it can
26801 // find, ignoring the required type.
26803 if (VT == MVT::f32 || VT == MVT::i32)
26804 Res.second = &X86::FR32RegClass;
26805 else if (VT == MVT::f64 || VT == MVT::i64)
26806 Res.second = &X86::FR64RegClass;
26807 else if (X86::VR128RegClass.hasType(VT))
26808 Res.second = &X86::VR128RegClass;
26809 else if (X86::VR256RegClass.hasType(VT))
26810 Res.second = &X86::VR256RegClass;
26811 else if (X86::VR512RegClass.hasType(VT))
26812 Res.second = &X86::VR512RegClass;
26818 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26820 // Scaling factors are not free at all.
26821 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26822 // will take 2 allocations in the out of order engine instead of 1
26823 // for plain addressing mode, i.e. inst (reg1).
26825 // vaddps (%rsi,%drx), %ymm0, %ymm1
26826 // Requires two allocations (one for the load, one for the computation)
26828 // vaddps (%rsi), %ymm0, %ymm1
26829 // Requires just 1 allocation, i.e., freeing allocations for other operations
26830 // and having less micro operations to execute.
26832 // For some X86 architectures, this is even worse because for instance for
26833 // stores, the complex addressing mode forces the instruction to use the
26834 // "load" ports instead of the dedicated "store" port.
26835 // E.g., on Haswell:
26836 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26837 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26838 if (isLegalAddressingMode(AM, Ty))
26839 // Scale represents reg2 * scale, thus account for 1
26840 // as soon as we use a second register.
26841 return AM.Scale != 0;
26845 bool X86TargetLowering::isTargetFTOL() const {
26846 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();