1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
829 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
830 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
831 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
833 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
834 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
839 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
841 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
842 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
844 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
845 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
846 MVT VT = (MVT::SimpleValueType)i;
847 // Do not attempt to custom lower non-power-of-2 vectors
848 if (!isPowerOf2_32(VT.getVectorNumElements()))
850 // Do not attempt to custom lower non-128-bit vectors
851 if (!VT.is128BitVector())
853 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
855 setOperationAction(ISD::VSELECT, VT, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
859 // We support custom legalizing of sext and anyext loads for specific
860 // memory vector types which we can load as a scalar (or sequence of
861 // scalars) and extend in-register to a legal 128-bit vector type. For sext
862 // loads these must work with a single scalar load.
863 for (MVT VT : MVT::integer_vector_valuetypes()) {
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
866 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
884 if (Subtarget->is64Bit()) {
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
889 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
890 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
891 MVT VT = (MVT::SimpleValueType)i;
893 // Do not attempt to promote non-128-bit vectors
894 if (!VT.is128BitVector())
897 setOperationAction(ISD::AND, VT, Promote);
898 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
899 setOperationAction(ISD::OR, VT, Promote);
900 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
901 setOperationAction(ISD::XOR, VT, Promote);
902 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
903 setOperationAction(ISD::LOAD, VT, Promote);
904 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
905 setOperationAction(ISD::SELECT, VT, Promote);
906 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
909 // Custom lower v2i64 and v2f64 selects.
910 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
911 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
912 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
913 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
915 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
916 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
918 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
920 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
921 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
922 // As there is no 64-bit GPR available, we need build a special custom
923 // sequence to convert from v2i32 to v2f32.
924 if (!Subtarget->is64Bit())
925 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
927 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
928 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
930 for (MVT VT : MVT::fp_vector_valuetypes())
931 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
933 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
934 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
935 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
938 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
939 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
940 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
941 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
942 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
943 setOperationAction(ISD::FRINT, RoundedTy, Legal);
944 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
947 // FIXME: Do we need to handle scalar-to-vector here?
948 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
950 // We directly match byte blends in the backend as they match the VSELECT
952 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
954 // SSE41 brings specific instructions for doing vector sign extend even in
955 // cases where we don't have SRA.
956 for (MVT VT : MVT::integer_vector_valuetypes()) {
957 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
958 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
959 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
962 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
967 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
968 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
973 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
974 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
975 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
977 // i8 and i16 vectors are custom because the source register and source
978 // source memory operand types are not the same width. f32 vectors are
979 // custom since the immediate controlling the insert encodes additional
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
983 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
984 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
989 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
991 // FIXME: these should be Legal, but that's only for the case where
992 // the index is constant. For now custom expand to deal with that.
993 if (Subtarget->is64Bit()) {
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
999 if (Subtarget->hasSSE2()) {
1000 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1004 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1005 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1007 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1008 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1010 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1011 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1013 // In the customized shift lowering, the legal cases in AVX2 will be
1015 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1016 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1019 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1021 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1024 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1025 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1026 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1027 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1028 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1029 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1032 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1033 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1036 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1047 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1049 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1060 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1062 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1063 // even though v8i16 is a legal type.
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1065 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1066 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1068 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1069 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1070 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1075 for (MVT VT : MVT::fp_vector_valuetypes())
1076 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1078 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1079 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1081 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1084 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1085 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1087 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1088 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1089 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1090 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1092 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1093 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1094 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1096 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1097 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1098 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1099 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1103 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1104 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1105 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1106 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1107 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1109 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1110 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1111 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1112 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1114 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1115 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1119 setOperationAction(ISD::FMA, MVT::f32, Legal);
1120 setOperationAction(ISD::FMA, MVT::f64, Legal);
1123 if (Subtarget->hasInt256()) {
1124 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1125 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1126 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1127 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1129 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1130 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1131 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1132 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1134 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1135 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1136 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1137 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1139 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1140 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1141 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1142 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1144 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1145 // when we have a 256bit-wide blend with immediate.
1146 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1148 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1153 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1154 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1160 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1161 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1164 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1165 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1166 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1168 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1169 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1170 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1173 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1174 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1175 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1176 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1179 // In the customized shift lowering, the legal cases in AVX2 will be
1181 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1184 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1187 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1189 // Custom lower several nodes for 256-bit types.
1190 for (MVT VT : MVT::vector_valuetypes()) {
1191 if (VT.getScalarSizeInBits() >= 32) {
1192 setOperationAction(ISD::MLOAD, VT, Legal);
1193 setOperationAction(ISD::MSTORE, VT, Legal);
1195 // Extract subvector is special because the value type
1196 // (result) is 128-bit but the source is 256-bit wide.
1197 if (VT.is128BitVector()) {
1198 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1200 // Do not attempt to custom lower other non-256-bit vectors
1201 if (!VT.is256BitVector())
1204 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1205 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1206 setOperationAction(ISD::VSELECT, VT, Custom);
1207 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1208 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1209 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1210 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1211 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1214 if (Subtarget->hasInt256())
1215 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1218 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1219 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1220 MVT VT = (MVT::SimpleValueType)i;
1222 // Do not attempt to promote non-256-bit vectors
1223 if (!VT.is256BitVector())
1226 setOperationAction(ISD::AND, VT, Promote);
1227 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1228 setOperationAction(ISD::OR, VT, Promote);
1229 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1230 setOperationAction(ISD::XOR, VT, Promote);
1231 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1232 setOperationAction(ISD::LOAD, VT, Promote);
1233 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1234 setOperationAction(ISD::SELECT, VT, Promote);
1235 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1239 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1240 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1242 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1245 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1246 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1247 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1249 for (MVT VT : MVT::fp_vector_valuetypes())
1250 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1252 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1253 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1254 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1255 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1256 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1257 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1258 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1259 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1260 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1261 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1262 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1263 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1265 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1266 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1267 setOperationAction(ISD::XOR, MVT::i1, Legal);
1268 setOperationAction(ISD::OR, MVT::i1, Legal);
1269 setOperationAction(ISD::AND, MVT::i1, Legal);
1270 setOperationAction(ISD::SUB, MVT::i1, Custom);
1271 setOperationAction(ISD::ADD, MVT::i1, Custom);
1272 setOperationAction(ISD::MUL, MVT::i1, Custom);
1273 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1274 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1275 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1276 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1277 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1279 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1280 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1281 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1282 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1283 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1284 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1286 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1287 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1288 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1289 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1290 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1291 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1292 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1293 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1295 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1296 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1297 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1298 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1299 if (Subtarget->is64Bit()) {
1300 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1301 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1302 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1303 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1305 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1306 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1307 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1308 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1309 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1310 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1311 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1312 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1313 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1314 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1315 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1316 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1317 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1318 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1319 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1320 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1322 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1323 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1324 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1325 if (Subtarget->hasDQI()) {
1326 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1327 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1329 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1330 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1331 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1332 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1333 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1334 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1335 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1336 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1337 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1338 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1339 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1340 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1341 if (Subtarget->hasDQI()) {
1342 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1343 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1345 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1368 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1369 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1370 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1371 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1372 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1373 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1374 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1375 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1376 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1377 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1379 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1380 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1382 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1383 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1385 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1387 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1390 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1391 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1393 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1396 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1397 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1398 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1399 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1400 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1401 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1403 if (Subtarget->hasCDI()) {
1404 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1405 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1407 if (Subtarget->hasDQI()) {
1408 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1409 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1410 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1412 // Custom lower several nodes.
1413 for (MVT VT : MVT::vector_valuetypes()) {
1414 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1416 setOperationAction(ISD::AND, VT, Legal);
1417 setOperationAction(ISD::OR, VT, Legal);
1418 setOperationAction(ISD::XOR, VT, Legal);
1420 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1421 setOperationAction(ISD::MGATHER, VT, Custom);
1422 setOperationAction(ISD::MSCATTER, VT, Custom);
1424 // Extract subvector is special because the value type
1425 // (result) is 256/128-bit but the source is 512-bit wide.
1426 if (VT.is128BitVector() || VT.is256BitVector()) {
1427 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1429 if (VT.getVectorElementType() == MVT::i1)
1430 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1432 // Do not attempt to custom lower other non-512-bit vectors
1433 if (!VT.is512BitVector())
1436 if (EltSize >= 32) {
1437 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1438 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1439 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1440 setOperationAction(ISD::VSELECT, VT, Legal);
1441 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1442 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1443 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1444 setOperationAction(ISD::MLOAD, VT, Legal);
1445 setOperationAction(ISD::MSTORE, VT, Legal);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-512-bit vectors.
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1461 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1462 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1464 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1465 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1467 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1468 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1469 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1470 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1471 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1472 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1473 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1474 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1475 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1476 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1477 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1478 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1479 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1480 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1481 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1482 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1483 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1484 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1485 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1486 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1487 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1488 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1489 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1490 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1491 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1492 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1493 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1495 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1496 const MVT VT = (MVT::SimpleValueType)i;
1498 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1500 // Do not attempt to promote non-512-bit vectors.
1501 if (!VT.is512BitVector())
1505 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1506 setOperationAction(ISD::VSELECT, VT, Legal);
1511 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1512 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1513 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1515 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1516 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1517 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1518 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1519 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1520 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1521 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1522 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1524 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1526 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1527 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1528 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1529 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1530 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1531 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1532 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1533 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1536 // We want to custom lower some of our intrinsics.
1537 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1538 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1539 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1540 if (!Subtarget->is64Bit())
1541 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1543 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1544 // handle type legalization for these operations here.
1546 // FIXME: We really should do custom legalization for addition and
1547 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1548 // than generic legalization for 64-bit multiplication-with-overflow, though.
1549 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1550 // Add/Sub/Mul with overflow operations are custom lowered.
1552 setOperationAction(ISD::SADDO, VT, Custom);
1553 setOperationAction(ISD::UADDO, VT, Custom);
1554 setOperationAction(ISD::SSUBO, VT, Custom);
1555 setOperationAction(ISD::USUBO, VT, Custom);
1556 setOperationAction(ISD::SMULO, VT, Custom);
1557 setOperationAction(ISD::UMULO, VT, Custom);
1561 if (!Subtarget->is64Bit()) {
1562 // These libcalls are not available in 32-bit.
1563 setLibcallName(RTLIB::SHL_I128, nullptr);
1564 setLibcallName(RTLIB::SRL_I128, nullptr);
1565 setLibcallName(RTLIB::SRA_I128, nullptr);
1568 // Combine sin / cos into one node or libcall if possible.
1569 if (Subtarget->hasSinCos()) {
1570 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1571 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1572 if (Subtarget->isTargetDarwin()) {
1573 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1574 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1575 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1576 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1580 if (Subtarget->isTargetWin64()) {
1581 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1582 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1583 setOperationAction(ISD::SREM, MVT::i128, Custom);
1584 setOperationAction(ISD::UREM, MVT::i128, Custom);
1585 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1586 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1589 // We have target-specific dag combine patterns for the following nodes:
1590 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1591 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1592 setTargetDAGCombine(ISD::BITCAST);
1593 setTargetDAGCombine(ISD::VSELECT);
1594 setTargetDAGCombine(ISD::SELECT);
1595 setTargetDAGCombine(ISD::SHL);
1596 setTargetDAGCombine(ISD::SRA);
1597 setTargetDAGCombine(ISD::SRL);
1598 setTargetDAGCombine(ISD::OR);
1599 setTargetDAGCombine(ISD::AND);
1600 setTargetDAGCombine(ISD::ADD);
1601 setTargetDAGCombine(ISD::FADD);
1602 setTargetDAGCombine(ISD::FSUB);
1603 setTargetDAGCombine(ISD::FMA);
1604 setTargetDAGCombine(ISD::SUB);
1605 setTargetDAGCombine(ISD::LOAD);
1606 setTargetDAGCombine(ISD::MLOAD);
1607 setTargetDAGCombine(ISD::STORE);
1608 setTargetDAGCombine(ISD::MSTORE);
1609 setTargetDAGCombine(ISD::ZERO_EXTEND);
1610 setTargetDAGCombine(ISD::ANY_EXTEND);
1611 setTargetDAGCombine(ISD::SIGN_EXTEND);
1612 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1613 setTargetDAGCombine(ISD::SINT_TO_FP);
1614 setTargetDAGCombine(ISD::SETCC);
1615 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1616 setTargetDAGCombine(ISD::BUILD_VECTOR);
1617 setTargetDAGCombine(ISD::MUL);
1618 setTargetDAGCombine(ISD::XOR);
1620 computeRegisterProperties(Subtarget->getRegisterInfo());
1622 // On Darwin, -Os means optimize for size without hurting performance,
1623 // do not reduce the limit.
1624 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1625 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1626 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1627 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1628 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1629 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1630 setPrefLoopAlignment(4); // 2^4 bytes.
1632 // Predictable cmov don't hurt on atom because it's in-order.
1633 PredictableSelectIsExpensive = !Subtarget->isAtom();
1634 EnableExtLdPromotion = true;
1635 setPrefFunctionAlignment(4); // 2^4 bytes.
1637 verifyIntrinsicTables();
1640 // This has so far only been implemented for 64-bit MachO.
1641 bool X86TargetLowering::useLoadStackGuardNode() const {
1642 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1645 TargetLoweringBase::LegalizeTypeAction
1646 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1647 if (ExperimentalVectorWideningLegalization &&
1648 VT.getVectorNumElements() != 1 &&
1649 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1650 return TypeWidenVector;
1652 return TargetLoweringBase::getPreferredVectorAction(VT);
1655 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1657 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1659 const unsigned NumElts = VT.getVectorNumElements();
1660 const EVT EltVT = VT.getVectorElementType();
1661 if (VT.is512BitVector()) {
1662 if (Subtarget->hasAVX512())
1663 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1664 EltVT == MVT::f32 || EltVT == MVT::f64)
1666 case 8: return MVT::v8i1;
1667 case 16: return MVT::v16i1;
1669 if (Subtarget->hasBWI())
1670 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1672 case 32: return MVT::v32i1;
1673 case 64: return MVT::v64i1;
1677 if (VT.is256BitVector() || VT.is128BitVector()) {
1678 if (Subtarget->hasVLX())
1679 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1680 EltVT == MVT::f32 || EltVT == MVT::f64)
1682 case 2: return MVT::v2i1;
1683 case 4: return MVT::v4i1;
1684 case 8: return MVT::v8i1;
1686 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1687 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1689 case 8: return MVT::v8i1;
1690 case 16: return MVT::v16i1;
1691 case 32: return MVT::v32i1;
1695 return VT.changeVectorElementTypeToInteger();
1698 /// Helper for getByValTypeAlignment to determine
1699 /// the desired ByVal argument alignment.
1700 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1703 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1704 if (VTy->getBitWidth() == 128)
1706 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1707 unsigned EltAlign = 0;
1708 getMaxByValAlign(ATy->getElementType(), EltAlign);
1709 if (EltAlign > MaxAlign)
1710 MaxAlign = EltAlign;
1711 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1712 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1713 unsigned EltAlign = 0;
1714 getMaxByValAlign(STy->getElementType(i), EltAlign);
1715 if (EltAlign > MaxAlign)
1716 MaxAlign = EltAlign;
1723 /// Return the desired alignment for ByVal aggregate
1724 /// function arguments in the caller parameter area. For X86, aggregates
1725 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1726 /// are at 4-byte boundaries.
1727 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1728 if (Subtarget->is64Bit()) {
1729 // Max of 8 and alignment of type.
1730 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1737 if (Subtarget->hasSSE1())
1738 getMaxByValAlign(Ty, Align);
1742 /// Returns the target specific optimal type for load
1743 /// and store operations as a result of memset, memcpy, and memmove
1744 /// lowering. If DstAlign is zero that means it's safe to destination
1745 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1746 /// means there isn't a need to check it against alignment requirement,
1747 /// probably because the source does not need to be loaded. If 'IsMemset' is
1748 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1749 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1750 /// source is constant so it does not need to be loaded.
1751 /// It returns EVT::Other if the type should be determined using generic
1752 /// target-independent logic.
1754 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1755 unsigned DstAlign, unsigned SrcAlign,
1756 bool IsMemset, bool ZeroMemset,
1758 MachineFunction &MF) const {
1759 const Function *F = MF.getFunction();
1760 if ((!IsMemset || ZeroMemset) &&
1761 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1763 (Subtarget->isUnalignedMemAccessFast() ||
1764 ((DstAlign == 0 || DstAlign >= 16) &&
1765 (SrcAlign == 0 || SrcAlign >= 16)))) {
1767 if (Subtarget->hasInt256())
1769 if (Subtarget->hasFp256())
1772 if (Subtarget->hasSSE2())
1774 if (Subtarget->hasSSE1())
1776 } else if (!MemcpyStrSrc && Size >= 8 &&
1777 !Subtarget->is64Bit() &&
1778 Subtarget->hasSSE2()) {
1779 // Do not use f64 to lower memcpy if source is string constant. It's
1780 // better to use i32 to avoid the loads.
1784 if (Subtarget->is64Bit() && Size >= 8)
1789 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1791 return X86ScalarSSEf32;
1792 else if (VT == MVT::f64)
1793 return X86ScalarSSEf64;
1798 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1803 *Fast = Subtarget->isUnalignedMemAccessFast();
1807 /// Return the entry encoding for a jump table in the
1808 /// current function. The returned value is a member of the
1809 /// MachineJumpTableInfo::JTEntryKind enum.
1810 unsigned X86TargetLowering::getJumpTableEncoding() const {
1811 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1813 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1814 Subtarget->isPICStyleGOT())
1815 return MachineJumpTableInfo::EK_Custom32;
1817 // Otherwise, use the normal jump table encoding heuristics.
1818 return TargetLowering::getJumpTableEncoding();
1821 bool X86TargetLowering::useSoftFloat() const {
1822 return Subtarget->useSoftFloat();
1826 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1827 const MachineBasicBlock *MBB,
1828 unsigned uid,MCContext &Ctx) const{
1829 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1830 Subtarget->isPICStyleGOT());
1831 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1833 return MCSymbolRefExpr::create(MBB->getSymbol(),
1834 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1837 /// Returns relocation base for the given PIC jumptable.
1838 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1839 SelectionDAG &DAG) const {
1840 if (!Subtarget->is64Bit())
1841 // This doesn't have SDLoc associated with it, but is not really the
1842 // same as a Register.
1843 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1847 /// This returns the relocation base for the given PIC jumptable,
1848 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1849 const MCExpr *X86TargetLowering::
1850 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1851 MCContext &Ctx) const {
1852 // X86-64 uses RIP relative addressing based on the jump table label.
1853 if (Subtarget->isPICStyleRIPRel())
1854 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1856 // Otherwise, the reference is relative to the PIC base.
1857 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1860 std::pair<const TargetRegisterClass *, uint8_t>
1861 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1863 const TargetRegisterClass *RRC = nullptr;
1865 switch (VT.SimpleTy) {
1867 return TargetLowering::findRepresentativeClass(TRI, VT);
1868 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1869 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1872 RRC = &X86::VR64RegClass;
1874 case MVT::f32: case MVT::f64:
1875 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1876 case MVT::v4f32: case MVT::v2f64:
1877 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1879 RRC = &X86::VR128RegClass;
1882 return std::make_pair(RRC, Cost);
1885 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1886 unsigned &Offset) const {
1887 if (!Subtarget->isTargetLinux())
1890 if (Subtarget->is64Bit()) {
1891 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1893 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1905 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1906 unsigned DestAS) const {
1907 assert(SrcAS != DestAS && "Expected different address spaces!");
1909 return SrcAS < 256 && DestAS < 256;
1912 //===----------------------------------------------------------------------===//
1913 // Return Value Calling Convention Implementation
1914 //===----------------------------------------------------------------------===//
1916 #include "X86GenCallingConv.inc"
1919 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1920 MachineFunction &MF, bool isVarArg,
1921 const SmallVectorImpl<ISD::OutputArg> &Outs,
1922 LLVMContext &Context) const {
1923 SmallVector<CCValAssign, 16> RVLocs;
1924 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1925 return CCInfo.CheckReturn(Outs, RetCC_X86);
1928 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1929 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1934 X86TargetLowering::LowerReturn(SDValue Chain,
1935 CallingConv::ID CallConv, bool isVarArg,
1936 const SmallVectorImpl<ISD::OutputArg> &Outs,
1937 const SmallVectorImpl<SDValue> &OutVals,
1938 SDLoc dl, SelectionDAG &DAG) const {
1939 MachineFunction &MF = DAG.getMachineFunction();
1940 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1942 SmallVector<CCValAssign, 16> RVLocs;
1943 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1944 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1947 SmallVector<SDValue, 6> RetOps;
1948 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1949 // Operand #1 = Bytes To Pop
1950 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1953 // Copy the result values into the output registers.
1954 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1955 CCValAssign &VA = RVLocs[i];
1956 assert(VA.isRegLoc() && "Can only return in registers!");
1957 SDValue ValToCopy = OutVals[i];
1958 EVT ValVT = ValToCopy.getValueType();
1960 // Promote values to the appropriate types.
1961 if (VA.getLocInfo() == CCValAssign::SExt)
1962 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1963 else if (VA.getLocInfo() == CCValAssign::ZExt)
1964 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1965 else if (VA.getLocInfo() == CCValAssign::AExt) {
1966 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1967 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1969 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1971 else if (VA.getLocInfo() == CCValAssign::BCvt)
1972 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1974 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1975 "Unexpected FP-extend for return value.");
1977 // If this is x86-64, and we disabled SSE, we can't return FP values,
1978 // or SSE or MMX vectors.
1979 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1980 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1981 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1982 report_fatal_error("SSE register return with SSE disabled");
1984 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1985 // llvm-gcc has never done it right and no one has noticed, so this
1986 // should be OK for now.
1987 if (ValVT == MVT::f64 &&
1988 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1989 report_fatal_error("SSE2 register return with SSE2 disabled");
1991 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1992 // the RET instruction and handled by the FP Stackifier.
1993 if (VA.getLocReg() == X86::FP0 ||
1994 VA.getLocReg() == X86::FP1) {
1995 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1996 // change the value to the FP stack register class.
1997 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1998 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1999 RetOps.push_back(ValToCopy);
2000 // Don't emit a copytoreg.
2004 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2005 // which is returned in RAX / RDX.
2006 if (Subtarget->is64Bit()) {
2007 if (ValVT == MVT::x86mmx) {
2008 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2009 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2010 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2012 // If we don't have SSE2 available, convert to v4f32 so the generated
2013 // register is legal.
2014 if (!Subtarget->hasSSE2())
2015 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2020 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2021 Flag = Chain.getValue(1);
2022 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2025 // All x86 ABIs require that for returning structs by value we copy
2026 // the sret argument into %rax/%eax (depending on ABI) for the return.
2027 // We saved the argument into a virtual register in the entry block,
2028 // so now we copy the value out and into %rax/%eax.
2030 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2031 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2032 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2033 // either case FuncInfo->setSRetReturnReg() will have been called.
2034 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2038 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2039 X86::RAX : X86::EAX;
2040 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2041 Flag = Chain.getValue(1);
2043 // RAX/EAX now acts like a return value.
2044 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2047 RetOps[0] = Chain; // Update chain.
2049 // Add the flag if we have it.
2051 RetOps.push_back(Flag);
2053 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2056 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2057 if (N->getNumValues() != 1)
2059 if (!N->hasNUsesOfValue(1, 0))
2062 SDValue TCChain = Chain;
2063 SDNode *Copy = *N->use_begin();
2064 if (Copy->getOpcode() == ISD::CopyToReg) {
2065 // If the copy has a glue operand, we conservatively assume it isn't safe to
2066 // perform a tail call.
2067 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2069 TCChain = Copy->getOperand(0);
2070 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2073 bool HasRet = false;
2074 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2076 if (UI->getOpcode() != X86ISD::RET_FLAG)
2078 // If we are returning more than one value, we can definitely
2079 // not make a tail call see PR19530
2080 if (UI->getNumOperands() > 4)
2082 if (UI->getNumOperands() == 4 &&
2083 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2096 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2097 ISD::NodeType ExtendKind) const {
2099 // TODO: Is this also valid on 32-bit?
2100 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2101 ReturnMVT = MVT::i8;
2103 ReturnMVT = MVT::i32;
2105 EVT MinVT = getRegisterType(Context, ReturnMVT);
2106 return VT.bitsLT(MinVT) ? MinVT : VT;
2109 /// Lower the result values of a call into the
2110 /// appropriate copies out of appropriate physical registers.
2113 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2114 CallingConv::ID CallConv, bool isVarArg,
2115 const SmallVectorImpl<ISD::InputArg> &Ins,
2116 SDLoc dl, SelectionDAG &DAG,
2117 SmallVectorImpl<SDValue> &InVals) const {
2119 // Assign locations to each value returned by this call.
2120 SmallVector<CCValAssign, 16> RVLocs;
2121 bool Is64Bit = Subtarget->is64Bit();
2122 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2124 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2126 // Copy all of the result registers out of their specified physreg.
2127 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2128 CCValAssign &VA = RVLocs[i];
2129 EVT CopyVT = VA.getLocVT();
2131 // If this is x86-64, and we disabled SSE, we can't return FP values
2132 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2133 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2134 report_fatal_error("SSE register return with SSE disabled");
2137 // If we prefer to use the value in xmm registers, copy it out as f80 and
2138 // use a truncate to move it from fp stack reg to xmm reg.
2139 bool RoundAfterCopy = false;
2140 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2141 isScalarFPTypeInSSEReg(VA.getValVT())) {
2143 RoundAfterCopy = (CopyVT != VA.getLocVT());
2146 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2147 CopyVT, InFlag).getValue(1);
2148 SDValue Val = Chain.getValue(0);
2151 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2152 // This truncation won't change the value.
2153 DAG.getIntPtrConstant(1, dl));
2155 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2156 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2158 InFlag = Chain.getValue(2);
2159 InVals.push_back(Val);
2165 //===----------------------------------------------------------------------===//
2166 // C & StdCall & Fast Calling Convention implementation
2167 //===----------------------------------------------------------------------===//
2168 // StdCall calling convention seems to be standard for many Windows' API
2169 // routines and around. It differs from C calling convention just a little:
2170 // callee should clean up the stack, not caller. Symbols should be also
2171 // decorated in some fancy way :) It doesn't support any vector arguments.
2172 // For info on fast calling convention see Fast Calling Convention (tail call)
2173 // implementation LowerX86_32FastCCCallTo.
2175 /// CallIsStructReturn - Determines whether a call uses struct return
2177 enum StructReturnType {
2182 static StructReturnType
2183 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2185 return NotStructReturn;
2187 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2188 if (!Flags.isSRet())
2189 return NotStructReturn;
2190 if (Flags.isInReg())
2191 return RegStructReturn;
2192 return StackStructReturn;
2195 /// Determines whether a function uses struct return semantics.
2196 static StructReturnType
2197 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2199 return NotStructReturn;
2201 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2202 if (!Flags.isSRet())
2203 return NotStructReturn;
2204 if (Flags.isInReg())
2205 return RegStructReturn;
2206 return StackStructReturn;
2209 /// Make a copy of an aggregate at address specified by "Src" to address
2210 /// "Dst" with size and alignment information specified by the specific
2211 /// parameter attribute. The copy will be passed as a byval function parameter.
2213 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2214 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2216 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2218 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2219 /*isVolatile*/false, /*AlwaysInline=*/true,
2220 /*isTailCall*/false,
2221 MachinePointerInfo(), MachinePointerInfo());
2224 /// Return true if the calling convention is one that
2225 /// supports tail call optimization.
2226 static bool IsTailCallConvention(CallingConv::ID CC) {
2227 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2228 CC == CallingConv::HiPE);
2231 /// \brief Return true if the calling convention is a C calling convention.
2232 static bool IsCCallConvention(CallingConv::ID CC) {
2233 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2234 CC == CallingConv::X86_64_SysV);
2237 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2239 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2240 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2244 CallingConv::ID CalleeCC = CS.getCallingConv();
2245 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2251 /// Return true if the function is being made into
2252 /// a tailcall target by changing its ABI.
2253 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2254 bool GuaranteedTailCallOpt) {
2255 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2259 X86TargetLowering::LowerMemArgument(SDValue Chain,
2260 CallingConv::ID CallConv,
2261 const SmallVectorImpl<ISD::InputArg> &Ins,
2262 SDLoc dl, SelectionDAG &DAG,
2263 const CCValAssign &VA,
2264 MachineFrameInfo *MFI,
2266 // Create the nodes corresponding to a load from this parameter slot.
2267 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2268 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2269 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2270 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2273 // If value is passed by pointer we have address passed instead of the value
2275 bool ExtendedInMem = VA.isExtInLoc() &&
2276 VA.getValVT().getScalarType() == MVT::i1;
2278 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2279 ValVT = VA.getLocVT();
2281 ValVT = VA.getValVT();
2283 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2284 // changed with more analysis.
2285 // In case of tail call optimization mark all arguments mutable. Since they
2286 // could be overwritten by lowering of arguments in case of a tail call.
2287 if (Flags.isByVal()) {
2288 unsigned Bytes = Flags.getByValSize();
2289 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2290 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2291 return DAG.getFrameIndex(FI, getPointerTy());
2293 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2294 VA.getLocMemOffset(), isImmutable);
2295 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2296 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2297 MachinePointerInfo::getFixedStack(FI),
2298 false, false, false, 0);
2299 return ExtendedInMem ?
2300 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2304 // FIXME: Get this from tablegen.
2305 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2306 const X86Subtarget *Subtarget) {
2307 assert(Subtarget->is64Bit());
2309 if (Subtarget->isCallingConvWin64(CallConv)) {
2310 static const MCPhysReg GPR64ArgRegsWin64[] = {
2311 X86::RCX, X86::RDX, X86::R8, X86::R9
2313 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2316 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2317 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2319 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2322 // FIXME: Get this from tablegen.
2323 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2324 CallingConv::ID CallConv,
2325 const X86Subtarget *Subtarget) {
2326 assert(Subtarget->is64Bit());
2327 if (Subtarget->isCallingConvWin64(CallConv)) {
2328 // The XMM registers which might contain var arg parameters are shadowed
2329 // in their paired GPR. So we only need to save the GPR to their home
2331 // TODO: __vectorcall will change this.
2335 const Function *Fn = MF.getFunction();
2336 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2337 bool isSoftFloat = Subtarget->useSoftFloat();
2338 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2339 "SSE register cannot be used when SSE is disabled!");
2340 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2341 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2345 static const MCPhysReg XMMArgRegs64Bit[] = {
2346 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2347 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2349 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2353 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2354 CallingConv::ID CallConv,
2356 const SmallVectorImpl<ISD::InputArg> &Ins,
2359 SmallVectorImpl<SDValue> &InVals)
2361 MachineFunction &MF = DAG.getMachineFunction();
2362 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2363 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2365 const Function* Fn = MF.getFunction();
2366 if (Fn->hasExternalLinkage() &&
2367 Subtarget->isTargetCygMing() &&
2368 Fn->getName() == "main")
2369 FuncInfo->setForceFramePointer(true);
2371 MachineFrameInfo *MFI = MF.getFrameInfo();
2372 bool Is64Bit = Subtarget->is64Bit();
2373 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2375 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2376 "Var args not supported with calling convention fastcc, ghc or hipe");
2378 // Assign locations to all of the incoming arguments.
2379 SmallVector<CCValAssign, 16> ArgLocs;
2380 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2382 // Allocate shadow area for Win64
2384 CCInfo.AllocateStack(32, 8);
2386 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2388 unsigned LastVal = ~0U;
2390 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2391 CCValAssign &VA = ArgLocs[i];
2392 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2394 assert(VA.getValNo() != LastVal &&
2395 "Don't support value assigned to multiple locs yet");
2397 LastVal = VA.getValNo();
2399 if (VA.isRegLoc()) {
2400 EVT RegVT = VA.getLocVT();
2401 const TargetRegisterClass *RC;
2402 if (RegVT == MVT::i32)
2403 RC = &X86::GR32RegClass;
2404 else if (Is64Bit && RegVT == MVT::i64)
2405 RC = &X86::GR64RegClass;
2406 else if (RegVT == MVT::f32)
2407 RC = &X86::FR32RegClass;
2408 else if (RegVT == MVT::f64)
2409 RC = &X86::FR64RegClass;
2410 else if (RegVT.is512BitVector())
2411 RC = &X86::VR512RegClass;
2412 else if (RegVT.is256BitVector())
2413 RC = &X86::VR256RegClass;
2414 else if (RegVT.is128BitVector())
2415 RC = &X86::VR128RegClass;
2416 else if (RegVT == MVT::x86mmx)
2417 RC = &X86::VR64RegClass;
2418 else if (RegVT == MVT::i1)
2419 RC = &X86::VK1RegClass;
2420 else if (RegVT == MVT::v8i1)
2421 RC = &X86::VK8RegClass;
2422 else if (RegVT == MVT::v16i1)
2423 RC = &X86::VK16RegClass;
2424 else if (RegVT == MVT::v32i1)
2425 RC = &X86::VK32RegClass;
2426 else if (RegVT == MVT::v64i1)
2427 RC = &X86::VK64RegClass;
2429 llvm_unreachable("Unknown argument type!");
2431 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2432 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2434 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2435 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2437 if (VA.getLocInfo() == CCValAssign::SExt)
2438 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2439 DAG.getValueType(VA.getValVT()));
2440 else if (VA.getLocInfo() == CCValAssign::ZExt)
2441 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2442 DAG.getValueType(VA.getValVT()));
2443 else if (VA.getLocInfo() == CCValAssign::BCvt)
2444 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2446 if (VA.isExtInLoc()) {
2447 // Handle MMX values passed in XMM regs.
2448 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2449 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2451 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2454 assert(VA.isMemLoc());
2455 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2458 // If value is passed via pointer - do a load.
2459 if (VA.getLocInfo() == CCValAssign::Indirect)
2460 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2461 MachinePointerInfo(), false, false, false, 0);
2463 InVals.push_back(ArgValue);
2466 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2467 // All x86 ABIs require that for returning structs by value we copy the
2468 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2469 // the argument into a virtual register so that we can access it from the
2471 if (Ins[i].Flags.isSRet()) {
2472 unsigned Reg = FuncInfo->getSRetReturnReg();
2474 MVT PtrTy = getPointerTy();
2475 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2476 FuncInfo->setSRetReturnReg(Reg);
2478 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2479 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2484 unsigned StackSize = CCInfo.getNextStackOffset();
2485 // Align stack specially for tail calls.
2486 if (FuncIsMadeTailCallSafe(CallConv,
2487 MF.getTarget().Options.GuaranteedTailCallOpt))
2488 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2490 // If the function takes variable number of arguments, make a frame index for
2491 // the start of the first vararg value... for expansion of llvm.va_start. We
2492 // can skip this if there are no va_start calls.
2493 if (MFI->hasVAStart() &&
2494 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2495 CallConv != CallingConv::X86_ThisCall))) {
2496 FuncInfo->setVarArgsFrameIndex(
2497 MFI->CreateFixedObject(1, StackSize, true));
2500 MachineModuleInfo &MMI = MF.getMMI();
2501 const Function *WinEHParent = nullptr;
2502 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2503 WinEHParent = MMI.getWinEHParent(Fn);
2504 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2505 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2507 // Figure out if XMM registers are in use.
2508 assert(!(Subtarget->useSoftFloat() &&
2509 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2510 "SSE register cannot be used when SSE is disabled!");
2512 // 64-bit calling conventions support varargs and register parameters, so we
2513 // have to do extra work to spill them in the prologue.
2514 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2515 // Find the first unallocated argument registers.
2516 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2517 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2518 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2519 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2520 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2521 "SSE register cannot be used when SSE is disabled!");
2523 // Gather all the live in physical registers.
2524 SmallVector<SDValue, 6> LiveGPRs;
2525 SmallVector<SDValue, 8> LiveXMMRegs;
2527 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2528 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2530 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2532 if (!ArgXMMs.empty()) {
2533 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2534 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2535 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2536 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2537 LiveXMMRegs.push_back(
2538 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2543 // Get to the caller-allocated home save location. Add 8 to account
2544 // for the return address.
2545 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2546 FuncInfo->setRegSaveFrameIndex(
2547 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2548 // Fixup to set vararg frame on shadow area (4 x i64).
2550 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2552 // For X86-64, if there are vararg parameters that are passed via
2553 // registers, then we must store them to their spots on the stack so
2554 // they may be loaded by deferencing the result of va_next.
2555 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2556 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2557 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2558 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2561 // Store the integer parameter registers.
2562 SmallVector<SDValue, 8> MemOps;
2563 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2565 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2566 for (SDValue Val : LiveGPRs) {
2567 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2568 DAG.getIntPtrConstant(Offset, dl));
2570 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2571 MachinePointerInfo::getFixedStack(
2572 FuncInfo->getRegSaveFrameIndex(), Offset),
2574 MemOps.push_back(Store);
2578 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2579 // Now store the XMM (fp + vector) parameter registers.
2580 SmallVector<SDValue, 12> SaveXMMOps;
2581 SaveXMMOps.push_back(Chain);
2582 SaveXMMOps.push_back(ALVal);
2583 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2584 FuncInfo->getRegSaveFrameIndex(), dl));
2585 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2586 FuncInfo->getVarArgsFPOffset(), dl));
2587 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2589 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2590 MVT::Other, SaveXMMOps));
2593 if (!MemOps.empty())
2594 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2595 } else if (IsWinEHOutlined) {
2596 // Get to the caller-allocated home save location. Add 8 to account
2597 // for the return address.
2598 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2599 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2600 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2602 MMI.getWinEHFuncInfo(Fn)
2603 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2604 FuncInfo->getRegSaveFrameIndex();
2606 // Store the second integer parameter (rdx) into rsp+16 relative to the
2607 // stack pointer at the entry of the function.
2609 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2610 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2611 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2612 Chain = DAG.getStore(
2613 Val.getValue(1), dl, Val, RSFIN,
2614 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2615 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2618 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2619 // Find the largest legal vector type.
2620 MVT VecVT = MVT::Other;
2621 // FIXME: Only some x86_32 calling conventions support AVX512.
2622 if (Subtarget->hasAVX512() &&
2623 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2624 CallConv == CallingConv::Intel_OCL_BI)))
2625 VecVT = MVT::v16f32;
2626 else if (Subtarget->hasAVX())
2628 else if (Subtarget->hasSSE2())
2631 // We forward some GPRs and some vector types.
2632 SmallVector<MVT, 2> RegParmTypes;
2633 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2634 RegParmTypes.push_back(IntVT);
2635 if (VecVT != MVT::Other)
2636 RegParmTypes.push_back(VecVT);
2638 // Compute the set of forwarded registers. The rest are scratch.
2639 SmallVectorImpl<ForwardedRegister> &Forwards =
2640 FuncInfo->getForwardedMustTailRegParms();
2641 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2643 // Conservatively forward AL on x86_64, since it might be used for varargs.
2644 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2645 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2646 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2649 // Copy all forwards from physical to virtual registers.
2650 for (ForwardedRegister &F : Forwards) {
2651 // FIXME: Can we use a less constrained schedule?
2652 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2653 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2654 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2658 // Some CCs need callee pop.
2659 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2660 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2661 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2663 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2664 // If this is an sret function, the return should pop the hidden pointer.
2665 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2666 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2667 argsAreStructReturn(Ins) == StackStructReturn)
2668 FuncInfo->setBytesToPopOnReturn(4);
2672 // RegSaveFrameIndex is X86-64 only.
2673 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2674 if (CallConv == CallingConv::X86_FastCall ||
2675 CallConv == CallingConv::X86_ThisCall)
2676 // fastcc functions can't have varargs.
2677 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2680 FuncInfo->setArgumentStackSize(StackSize);
2682 if (IsWinEHParent) {
2683 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2684 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2685 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2686 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2687 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2688 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2689 /*isVolatile=*/true,
2690 /*isNonTemporal=*/false, /*Alignment=*/0);
2697 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2698 SDValue StackPtr, SDValue Arg,
2699 SDLoc dl, SelectionDAG &DAG,
2700 const CCValAssign &VA,
2701 ISD::ArgFlagsTy Flags) const {
2702 unsigned LocMemOffset = VA.getLocMemOffset();
2703 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2704 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2705 if (Flags.isByVal())
2706 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2708 return DAG.getStore(Chain, dl, Arg, PtrOff,
2709 MachinePointerInfo::getStack(LocMemOffset),
2713 /// Emit a load of return address if tail call
2714 /// optimization is performed and it is required.
2716 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2717 SDValue &OutRetAddr, SDValue Chain,
2718 bool IsTailCall, bool Is64Bit,
2719 int FPDiff, SDLoc dl) const {
2720 // Adjust the Return address stack slot.
2721 EVT VT = getPointerTy();
2722 OutRetAddr = getReturnAddressFrameIndex(DAG);
2724 // Load the "old" Return address.
2725 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2726 false, false, false, 0);
2727 return SDValue(OutRetAddr.getNode(), 1);
2730 /// Emit a store of the return address if tail call
2731 /// optimization is performed and it is required (FPDiff!=0).
2732 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2733 SDValue Chain, SDValue RetAddrFrIdx,
2734 EVT PtrVT, unsigned SlotSize,
2735 int FPDiff, SDLoc dl) {
2736 // Store the return address to the appropriate stack slot.
2737 if (!FPDiff) return Chain;
2738 // Calculate the new stack slot for the return address.
2739 int NewReturnAddrFI =
2740 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2742 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2743 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2744 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2750 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2751 SmallVectorImpl<SDValue> &InVals) const {
2752 SelectionDAG &DAG = CLI.DAG;
2754 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2755 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2756 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2757 SDValue Chain = CLI.Chain;
2758 SDValue Callee = CLI.Callee;
2759 CallingConv::ID CallConv = CLI.CallConv;
2760 bool &isTailCall = CLI.IsTailCall;
2761 bool isVarArg = CLI.IsVarArg;
2763 MachineFunction &MF = DAG.getMachineFunction();
2764 bool Is64Bit = Subtarget->is64Bit();
2765 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2766 StructReturnType SR = callIsStructReturn(Outs);
2767 bool IsSibcall = false;
2768 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2769 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2771 if (Attr.getValueAsString() == "true")
2774 if (Subtarget->isPICStyleGOT() &&
2775 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2776 // If we are using a GOT, disable tail calls to external symbols with
2777 // default visibility. Tail calling such a symbol requires using a GOT
2778 // relocation, which forces early binding of the symbol. This breaks code
2779 // that require lazy function symbol resolution. Using musttail or
2780 // GuaranteedTailCallOpt will override this.
2781 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2782 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2783 G->getGlobal()->hasDefaultVisibility()))
2787 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2789 // Force this to be a tail call. The verifier rules are enough to ensure
2790 // that we can lower this successfully without moving the return address
2793 } else if (isTailCall) {
2794 // Check if it's really possible to do a tail call.
2795 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2796 isVarArg, SR != NotStructReturn,
2797 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2798 Outs, OutVals, Ins, DAG);
2800 // Sibcalls are automatically detected tailcalls which do not require
2802 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2809 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2810 "Var args not supported with calling convention fastcc, ghc or hipe");
2812 // Analyze operands of the call, assigning locations to each operand.
2813 SmallVector<CCValAssign, 16> ArgLocs;
2814 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2816 // Allocate shadow area for Win64
2818 CCInfo.AllocateStack(32, 8);
2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2822 // Get a count of how many bytes are to be pushed on the stack.
2823 unsigned NumBytes = CCInfo.getNextStackOffset();
2825 // This is a sibcall. The memory operands are available in caller's
2826 // own caller's stack.
2828 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2829 IsTailCallConvention(CallConv))
2830 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2833 if (isTailCall && !IsSibcall && !IsMustTail) {
2834 // Lower arguments at fp - stackoffset + fpdiff.
2835 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2837 FPDiff = NumBytesCallerPushed - NumBytes;
2839 // Set the delta of movement of the returnaddr stackslot.
2840 // But only set if delta is greater than previous delta.
2841 if (FPDiff < X86Info->getTCReturnAddrDelta())
2842 X86Info->setTCReturnAddrDelta(FPDiff);
2845 unsigned NumBytesToPush = NumBytes;
2846 unsigned NumBytesToPop = NumBytes;
2848 // If we have an inalloca argument, all stack space has already been allocated
2849 // for us and be right at the top of the stack. We don't support multiple
2850 // arguments passed in memory when using inalloca.
2851 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2853 if (!ArgLocs.back().isMemLoc())
2854 report_fatal_error("cannot use inalloca attribute on a register "
2856 if (ArgLocs.back().getLocMemOffset() != 0)
2857 report_fatal_error("any parameter with the inalloca attribute must be "
2858 "the only memory argument");
2862 Chain = DAG.getCALLSEQ_START(
2863 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2865 SDValue RetAddrFrIdx;
2866 // Load return address for tail calls.
2867 if (isTailCall && FPDiff)
2868 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2869 Is64Bit, FPDiff, dl);
2871 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2872 SmallVector<SDValue, 8> MemOpChains;
2875 // Walk the register/memloc assignments, inserting copies/loads. In the case
2876 // of tail call optimization arguments are handle later.
2877 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2878 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2879 // Skip inalloca arguments, they have already been written.
2880 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2881 if (Flags.isInAlloca())
2884 CCValAssign &VA = ArgLocs[i];
2885 EVT RegVT = VA.getLocVT();
2886 SDValue Arg = OutVals[i];
2887 bool isByVal = Flags.isByVal();
2889 // Promote the value if needed.
2890 switch (VA.getLocInfo()) {
2891 default: llvm_unreachable("Unknown loc info!");
2892 case CCValAssign::Full: break;
2893 case CCValAssign::SExt:
2894 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2896 case CCValAssign::ZExt:
2897 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2899 case CCValAssign::AExt:
2900 if (Arg.getValueType().isVector() &&
2901 Arg.getValueType().getScalarType() == MVT::i1)
2902 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2903 else if (RegVT.is128BitVector()) {
2904 // Special case: passing MMX values in XMM registers.
2905 Arg = DAG.getBitcast(MVT::i64, Arg);
2906 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2907 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2909 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2911 case CCValAssign::BCvt:
2912 Arg = DAG.getBitcast(RegVT, Arg);
2914 case CCValAssign::Indirect: {
2915 // Store the argument.
2916 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2917 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2918 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2919 MachinePointerInfo::getFixedStack(FI),
2926 if (VA.isRegLoc()) {
2927 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2928 if (isVarArg && IsWin64) {
2929 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2930 // shadow reg if callee is a varargs function.
2931 unsigned ShadowReg = 0;
2932 switch (VA.getLocReg()) {
2933 case X86::XMM0: ShadowReg = X86::RCX; break;
2934 case X86::XMM1: ShadowReg = X86::RDX; break;
2935 case X86::XMM2: ShadowReg = X86::R8; break;
2936 case X86::XMM3: ShadowReg = X86::R9; break;
2939 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2941 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2942 assert(VA.isMemLoc());
2943 if (!StackPtr.getNode())
2944 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2946 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2947 dl, DAG, VA, Flags));
2951 if (!MemOpChains.empty())
2952 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2954 if (Subtarget->isPICStyleGOT()) {
2955 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2958 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2959 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2961 // If we are tail calling and generating PIC/GOT style code load the
2962 // address of the callee into ECX. The value in ecx is used as target of
2963 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2964 // for tail calls on PIC/GOT architectures. Normally we would just put the
2965 // address of GOT into ebx and then call target@PLT. But for tail calls
2966 // ebx would be restored (since ebx is callee saved) before jumping to the
2969 // Note: The actual moving to ECX is done further down.
2970 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2971 if (G && !G->getGlobal()->hasLocalLinkage() &&
2972 G->getGlobal()->hasDefaultVisibility())
2973 Callee = LowerGlobalAddress(Callee, DAG);
2974 else if (isa<ExternalSymbolSDNode>(Callee))
2975 Callee = LowerExternalSymbol(Callee, DAG);
2979 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2980 // From AMD64 ABI document:
2981 // For calls that may call functions that use varargs or stdargs
2982 // (prototype-less calls or calls to functions containing ellipsis (...) in
2983 // the declaration) %al is used as hidden argument to specify the number
2984 // of SSE registers used. The contents of %al do not need to match exactly
2985 // the number of registers, but must be an ubound on the number of SSE
2986 // registers used and is in the range 0 - 8 inclusive.
2988 // Count the number of XMM registers allocated.
2989 static const MCPhysReg XMMArgRegs[] = {
2990 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2991 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2993 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2994 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2995 && "SSE registers cannot be used when SSE is disabled");
2997 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2998 DAG.getConstant(NumXMMRegs, dl,
3002 if (isVarArg && IsMustTail) {
3003 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3004 for (const auto &F : Forwards) {
3005 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3006 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3010 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3011 // don't need this because the eligibility check rejects calls that require
3012 // shuffling arguments passed in memory.
3013 if (!IsSibcall && isTailCall) {
3014 // Force all the incoming stack arguments to be loaded from the stack
3015 // before any new outgoing arguments are stored to the stack, because the
3016 // outgoing stack slots may alias the incoming argument stack slots, and
3017 // the alias isn't otherwise explicit. This is slightly more conservative
3018 // than necessary, because it means that each store effectively depends
3019 // on every argument instead of just those arguments it would clobber.
3020 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3022 SmallVector<SDValue, 8> MemOpChains2;
3025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3026 CCValAssign &VA = ArgLocs[i];
3029 assert(VA.isMemLoc());
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // Skip inalloca arguments. They don't require any work.
3033 if (Flags.isInAlloca())
3035 // Create frame index.
3036 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3037 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3038 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3039 FIN = DAG.getFrameIndex(FI, getPointerTy());
3041 if (Flags.isByVal()) {
3042 // Copy relative to framepointer.
3043 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3044 if (!StackPtr.getNode())
3045 StackPtr = DAG.getCopyFromReg(Chain, dl,
3046 RegInfo->getStackRegister(),
3048 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3050 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3054 // Store relative to framepointer.
3055 MemOpChains2.push_back(
3056 DAG.getStore(ArgChain, dl, Arg, FIN,
3057 MachinePointerInfo::getFixedStack(FI),
3062 if (!MemOpChains2.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3065 // Store the return address to the appropriate stack slot.
3066 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3067 getPointerTy(), RegInfo->getSlotSize(),
3071 // Build a sequence of copy-to-reg nodes chained together with token chain
3072 // and flag operands which copy the outgoing args into registers.
3074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3076 RegsToPass[i].second, InFlag);
3077 InFlag = Chain.getValue(1);
3080 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3081 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3082 // In the 64-bit large code model, we have to make all calls
3083 // through a register, since the call instruction's 32-bit
3084 // pc-relative offset may not be large enough to hold the whole
3086 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3087 // If the callee is a GlobalAddress node (quite common, every direct call
3088 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3090 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3092 // We should use extra load for direct calls to dllimported functions in
3094 const GlobalValue *GV = G->getGlobal();
3095 if (!GV->hasDLLImportStorageClass()) {
3096 unsigned char OpFlags = 0;
3097 bool ExtraLoad = false;
3098 unsigned WrapperKind = ISD::DELETED_NODE;
3100 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3101 // external symbols most go through the PLT in PIC mode. If the symbol
3102 // has hidden or protected visibility, or if it is static or local, then
3103 // we don't need to use the PLT - we can directly call it.
3104 if (Subtarget->isTargetELF() &&
3105 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3106 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3107 OpFlags = X86II::MO_PLT;
3108 } else if (Subtarget->isPICStyleStubAny() &&
3109 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3116 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3117 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3118 // If the function is marked as non-lazy, generate an indirect call
3119 // which loads from the GOT directly. This avoids runtime overhead
3120 // at the cost of eager binding (and one extra byte of encoding).
3121 OpFlags = X86II::MO_GOTPCREL;
3122 WrapperKind = X86ISD::WrapperRIP;
3126 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3127 G->getOffset(), OpFlags);
3129 // Add a wrapper if needed.
3130 if (WrapperKind != ISD::DELETED_NODE)
3131 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3132 // Add extra indirection if needed.
3134 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3135 MachinePointerInfo::getGOT(),
3136 false, false, false, 0);
3138 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3139 unsigned char OpFlags = 0;
3141 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3142 // external symbols should go through the PLT.
3143 if (Subtarget->isTargetELF() &&
3144 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3145 OpFlags = X86II::MO_PLT;
3146 } else if (Subtarget->isPICStyleStubAny() &&
3147 (!Subtarget->getTargetTriple().isMacOSX() ||
3148 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3149 // PC-relative references to external symbols should go through $stub,
3150 // unless we're building with the leopard linker or later, which
3151 // automatically synthesizes these stubs.
3152 OpFlags = X86II::MO_DARWIN_STUB;
3155 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3157 } else if (Subtarget->isTarget64BitILP32() &&
3158 Callee->getValueType(0) == MVT::i32) {
3159 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3160 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3163 // Returns a chain & a flag for retval copy to use.
3164 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3165 SmallVector<SDValue, 8> Ops;
3167 if (!IsSibcall && isTailCall) {
3168 Chain = DAG.getCALLSEQ_END(Chain,
3169 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3170 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3171 InFlag = Chain.getValue(1);
3174 Ops.push_back(Chain);
3175 Ops.push_back(Callee);
3178 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3180 // Add argument registers to the end of the list so that they are known live
3182 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3183 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3184 RegsToPass[i].second.getValueType()));
3186 // Add a register mask operand representing the call-preserved registers.
3187 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3188 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3189 assert(Mask && "Missing call preserved mask for calling convention");
3190 Ops.push_back(DAG.getRegisterMask(Mask));
3192 if (InFlag.getNode())
3193 Ops.push_back(InFlag);
3197 //// If this is the first return lowered for this function, add the regs
3198 //// to the liveout set for the function.
3199 // This isn't right, although it's probably harmless on x86; liveouts
3200 // should be computed from returns not tail calls. Consider a void
3201 // function making a tail call to a function returning int.
3202 MF.getFrameInfo()->setHasTailCall();
3203 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3206 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3207 InFlag = Chain.getValue(1);
3209 // Create the CALLSEQ_END node.
3210 unsigned NumBytesForCalleeToPop;
3211 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3212 DAG.getTarget().Options.GuaranteedTailCallOpt))
3213 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3214 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3215 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3216 SR == StackStructReturn)
3217 // If this is a call to a struct-return function, the callee
3218 // pops the hidden struct pointer, so we have to push it back.
3219 // This is common for Darwin/X86, Linux & Mingw32 targets.
3220 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3221 NumBytesForCalleeToPop = 4;
3223 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3225 // Returns a flag for retval copy to use.
3227 Chain = DAG.getCALLSEQ_END(Chain,
3228 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3229 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3232 InFlag = Chain.getValue(1);
3235 // Handle result values, copying them out of physregs into vregs that we
3237 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3238 Ins, dl, DAG, InVals);
3241 //===----------------------------------------------------------------------===//
3242 // Fast Calling Convention (tail call) implementation
3243 //===----------------------------------------------------------------------===//
3245 // Like std call, callee cleans arguments, convention except that ECX is
3246 // reserved for storing the tail called function address. Only 2 registers are
3247 // free for argument passing (inreg). Tail call optimization is performed
3249 // * tailcallopt is enabled
3250 // * caller/callee are fastcc
3251 // On X86_64 architecture with GOT-style position independent code only local
3252 // (within module) calls are supported at the moment.
3253 // To keep the stack aligned according to platform abi the function
3254 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3255 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3256 // If a tail called function callee has more arguments than the caller the
3257 // caller needs to make sure that there is room to move the RETADDR to. This is
3258 // achieved by reserving an area the size of the argument delta right after the
3259 // original RETADDR, but before the saved framepointer or the spilled registers
3260 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3272 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3273 /// for a 16 byte align requirement.
3275 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3276 SelectionDAG& DAG) const {
3277 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3278 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3279 unsigned StackAlignment = TFI.getStackAlignment();
3280 uint64_t AlignMask = StackAlignment - 1;
3281 int64_t Offset = StackSize;
3282 unsigned SlotSize = RegInfo->getSlotSize();
3283 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3284 // Number smaller than 12 so just add the difference.
3285 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3287 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3288 Offset = ((~AlignMask) & Offset) + StackAlignment +
3289 (StackAlignment-SlotSize);
3294 /// MatchingStackOffset - Return true if the given stack call argument is
3295 /// already available in the same position (relatively) of the caller's
3296 /// incoming argument stack.
3298 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3299 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3300 const X86InstrInfo *TII) {
3301 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3303 if (Arg.getOpcode() == ISD::CopyFromReg) {
3304 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3305 if (!TargetRegisterInfo::isVirtualRegister(VR))
3307 MachineInstr *Def = MRI->getVRegDef(VR);
3310 if (!Flags.isByVal()) {
3311 if (!TII->isLoadFromStackSlot(Def, FI))
3314 unsigned Opcode = Def->getOpcode();
3315 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3316 Opcode == X86::LEA64_32r) &&
3317 Def->getOperand(1).isFI()) {
3318 FI = Def->getOperand(1).getIndex();
3319 Bytes = Flags.getByValSize();
3323 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3324 if (Flags.isByVal())
3325 // ByVal argument is passed in as a pointer but it's now being
3326 // dereferenced. e.g.
3327 // define @foo(%struct.X* %A) {
3328 // tail call @bar(%struct.X* byval %A)
3331 SDValue Ptr = Ld->getBasePtr();
3332 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3335 FI = FINode->getIndex();
3336 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3337 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3338 FI = FINode->getIndex();
3339 Bytes = Flags.getByValSize();
3343 assert(FI != INT_MAX);
3344 if (!MFI->isFixedObjectIndex(FI))
3346 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3349 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3350 /// for tail call optimization. Targets which want to do tail call
3351 /// optimization should implement this function.
3353 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3354 CallingConv::ID CalleeCC,
3356 bool isCalleeStructRet,
3357 bool isCallerStructRet,
3359 const SmallVectorImpl<ISD::OutputArg> &Outs,
3360 const SmallVectorImpl<SDValue> &OutVals,
3361 const SmallVectorImpl<ISD::InputArg> &Ins,
3362 SelectionDAG &DAG) const {
3363 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3366 // If -tailcallopt is specified, make fastcc functions tail-callable.
3367 const MachineFunction &MF = DAG.getMachineFunction();
3368 const Function *CallerF = MF.getFunction();
3370 // If the function return type is x86_fp80 and the callee return type is not,
3371 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3372 // perform a tailcall optimization here.
3373 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3376 CallingConv::ID CallerCC = CallerF->getCallingConv();
3377 bool CCMatch = CallerCC == CalleeCC;
3378 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3379 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3381 // Win64 functions have extra shadow space for argument homing. Don't do the
3382 // sibcall if the caller and callee have mismatched expectations for this
3384 if (IsCalleeWin64 != IsCallerWin64)
3387 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3388 if (IsTailCallConvention(CalleeCC) && CCMatch)
3393 // Look for obvious safe cases to perform tail call optimization that do not
3394 // require ABI changes. This is what gcc calls sibcall.
3396 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3397 // emit a special epilogue.
3398 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3399 if (RegInfo->needsStackRealignment(MF))
3402 // Also avoid sibcall optimization if either caller or callee uses struct
3403 // return semantics.
3404 if (isCalleeStructRet || isCallerStructRet)
3407 // An stdcall/thiscall caller is expected to clean up its arguments; the
3408 // callee isn't going to do that.
3409 // FIXME: this is more restrictive than needed. We could produce a tailcall
3410 // when the stack adjustment matches. For example, with a thiscall that takes
3411 // only one argument.
3412 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3413 CallerCC == CallingConv::X86_ThisCall))
3416 // Do not sibcall optimize vararg calls unless all arguments are passed via
3418 if (isVarArg && !Outs.empty()) {
3420 // Optimizing for varargs on Win64 is unlikely to be safe without
3421 // additional testing.
3422 if (IsCalleeWin64 || IsCallerWin64)
3425 SmallVector<CCValAssign, 16> ArgLocs;
3426 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3429 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3430 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3431 if (!ArgLocs[i].isRegLoc())
3435 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3436 // stack. Therefore, if it's not used by the call it is not safe to optimize
3437 // this into a sibcall.
3438 bool Unused = false;
3439 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3446 SmallVector<CCValAssign, 16> RVLocs;
3447 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3449 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3450 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3451 CCValAssign &VA = RVLocs[i];
3452 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3457 // If the calling conventions do not match, then we'd better make sure the
3458 // results are returned in the same way as what the caller expects.
3460 SmallVector<CCValAssign, 16> RVLocs1;
3461 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3463 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3465 SmallVector<CCValAssign, 16> RVLocs2;
3466 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3468 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3470 if (RVLocs1.size() != RVLocs2.size())
3472 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3473 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3475 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3477 if (RVLocs1[i].isRegLoc()) {
3478 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3481 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3487 // If the callee takes no arguments then go on to check the results of the
3489 if (!Outs.empty()) {
3490 // Check if stack adjustment is needed. For now, do not do this if any
3491 // argument is passed on the stack.
3492 SmallVector<CCValAssign, 16> ArgLocs;
3493 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3496 // Allocate shadow area for Win64
3498 CCInfo.AllocateStack(32, 8);
3500 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3501 if (CCInfo.getNextStackOffset()) {
3502 MachineFunction &MF = DAG.getMachineFunction();
3503 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3506 // Check if the arguments are already laid out in the right way as
3507 // the caller's fixed stack objects.
3508 MachineFrameInfo *MFI = MF.getFrameInfo();
3509 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3510 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3511 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3512 CCValAssign &VA = ArgLocs[i];
3513 SDValue Arg = OutVals[i];
3514 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3515 if (VA.getLocInfo() == CCValAssign::Indirect)
3517 if (!VA.isRegLoc()) {
3518 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3525 // If the tailcall address may be in a register, then make sure it's
3526 // possible to register allocate for it. In 32-bit, the call address can
3527 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3528 // callee-saved registers are restored. These happen to be the same
3529 // registers used to pass 'inreg' arguments so watch out for those.
3530 if (!Subtarget->is64Bit() &&
3531 ((!isa<GlobalAddressSDNode>(Callee) &&
3532 !isa<ExternalSymbolSDNode>(Callee)) ||
3533 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3534 unsigned NumInRegs = 0;
3535 // In PIC we need an extra register to formulate the address computation
3537 unsigned MaxInRegs =
3538 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3540 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3541 CCValAssign &VA = ArgLocs[i];
3544 unsigned Reg = VA.getLocReg();
3547 case X86::EAX: case X86::EDX: case X86::ECX:
3548 if (++NumInRegs == MaxInRegs)
3560 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3561 const TargetLibraryInfo *libInfo) const {
3562 return X86::createFastISel(funcInfo, libInfo);
3565 //===----------------------------------------------------------------------===//
3566 // Other Lowering Hooks
3567 //===----------------------------------------------------------------------===//
3569 static bool MayFoldLoad(SDValue Op) {
3570 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3573 static bool MayFoldIntoStore(SDValue Op) {
3574 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3577 static bool isTargetShuffle(unsigned Opcode) {
3579 default: return false;
3580 case X86ISD::BLENDI:
3581 case X86ISD::PSHUFB:
3582 case X86ISD::PSHUFD:
3583 case X86ISD::PSHUFHW:
3584 case X86ISD::PSHUFLW:
3586 case X86ISD::PALIGNR:
3587 case X86ISD::MOVLHPS:
3588 case X86ISD::MOVLHPD:
3589 case X86ISD::MOVHLPS:
3590 case X86ISD::MOVLPS:
3591 case X86ISD::MOVLPD:
3592 case X86ISD::MOVSHDUP:
3593 case X86ISD::MOVSLDUP:
3594 case X86ISD::MOVDDUP:
3597 case X86ISD::UNPCKL:
3598 case X86ISD::UNPCKH:
3599 case X86ISD::VPERMILPI:
3600 case X86ISD::VPERM2X128:
3601 case X86ISD::VPERMI:
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, unsigned TargetMask,
3608 SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::PSHUFD:
3612 case X86ISD::PSHUFHW:
3613 case X86ISD::PSHUFLW:
3614 case X86ISD::VPERMILPI:
3615 case X86ISD::VPERMI:
3616 return DAG.getNode(Opc, dl, VT, V1,
3617 DAG.getConstant(TargetMask, dl, MVT::i8));
3621 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3622 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3624 default: llvm_unreachable("Unknown x86 shuffle node");
3625 case X86ISD::MOVLHPS:
3626 case X86ISD::MOVLHPD:
3627 case X86ISD::MOVHLPS:
3628 case X86ISD::MOVLPS:
3629 case X86ISD::MOVLPD:
3632 case X86ISD::UNPCKL:
3633 case X86ISD::UNPCKH:
3634 return DAG.getNode(Opc, dl, VT, V1, V2);
3638 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3639 MachineFunction &MF = DAG.getMachineFunction();
3640 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3641 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3642 int ReturnAddrIndex = FuncInfo->getRAIndex();
3644 if (ReturnAddrIndex == 0) {
3645 // Set up a frame object for the return address.
3646 unsigned SlotSize = RegInfo->getSlotSize();
3647 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3650 FuncInfo->setRAIndex(ReturnAddrIndex);
3653 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3656 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3657 bool hasSymbolicDisplacement) {
3658 // Offset should fit into 32 bit immediate field.
3659 if (!isInt<32>(Offset))
3662 // If we don't have a symbolic displacement - we don't have any extra
3664 if (!hasSymbolicDisplacement)
3667 // FIXME: Some tweaks might be needed for medium code model.
3668 if (M != CodeModel::Small && M != CodeModel::Kernel)
3671 // For small code model we assume that latest object is 16MB before end of 31
3672 // bits boundary. We may also accept pretty large negative constants knowing
3673 // that all objects are in the positive half of address space.
3674 if (M == CodeModel::Small && Offset < 16*1024*1024)
3677 // For kernel code model we know that all object resist in the negative half
3678 // of 32bits address space. We may not accept negative offsets, since they may
3679 // be just off and we may accept pretty large positive ones.
3680 if (M == CodeModel::Kernel && Offset >= 0)
3686 /// isCalleePop - Determines whether the callee is required to pop its
3687 /// own arguments. Callee pop is necessary to support tail calls.
3688 bool X86::isCalleePop(CallingConv::ID CallingConv,
3689 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3690 switch (CallingConv) {
3693 case CallingConv::X86_StdCall:
3694 case CallingConv::X86_FastCall:
3695 case CallingConv::X86_ThisCall:
3697 case CallingConv::Fast:
3698 case CallingConv::GHC:
3699 case CallingConv::HiPE:
3706 /// \brief Return true if the condition is an unsigned comparison operation.
3707 static bool isX86CCUnsigned(unsigned X86CC) {
3709 default: llvm_unreachable("Invalid integer condition!");
3710 case X86::COND_E: return true;
3711 case X86::COND_G: return false;
3712 case X86::COND_GE: return false;
3713 case X86::COND_L: return false;
3714 case X86::COND_LE: return false;
3715 case X86::COND_NE: return true;
3716 case X86::COND_B: return true;
3717 case X86::COND_A: return true;
3718 case X86::COND_BE: return true;
3719 case X86::COND_AE: return true;
3721 llvm_unreachable("covered switch fell through?!");
3724 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3725 /// specific condition code, returning the condition code and the LHS/RHS of the
3726 /// comparison to make.
3727 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3728 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3730 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3731 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3732 // X > -1 -> X == 0, jump !sign.
3733 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3734 return X86::COND_NS;
3736 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3737 // X < 0 -> X == 0, jump on sign.
3740 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3742 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3743 return X86::COND_LE;
3747 switch (SetCCOpcode) {
3748 default: llvm_unreachable("Invalid integer condition!");
3749 case ISD::SETEQ: return X86::COND_E;
3750 case ISD::SETGT: return X86::COND_G;
3751 case ISD::SETGE: return X86::COND_GE;
3752 case ISD::SETLT: return X86::COND_L;
3753 case ISD::SETLE: return X86::COND_LE;
3754 case ISD::SETNE: return X86::COND_NE;
3755 case ISD::SETULT: return X86::COND_B;
3756 case ISD::SETUGT: return X86::COND_A;
3757 case ISD::SETULE: return X86::COND_BE;
3758 case ISD::SETUGE: return X86::COND_AE;
3762 // First determine if it is required or is profitable to flip the operands.
3764 // If LHS is a foldable load, but RHS is not, flip the condition.
3765 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3766 !ISD::isNON_EXTLoad(RHS.getNode())) {
3767 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3768 std::swap(LHS, RHS);
3771 switch (SetCCOpcode) {
3777 std::swap(LHS, RHS);
3781 // On a floating point condition, the flags are set as follows:
3783 // 0 | 0 | 0 | X > Y
3784 // 0 | 0 | 1 | X < Y
3785 // 1 | 0 | 0 | X == Y
3786 // 1 | 1 | 1 | unordered
3787 switch (SetCCOpcode) {
3788 default: llvm_unreachable("Condcode should be pre-legalized away");
3790 case ISD::SETEQ: return X86::COND_E;
3791 case ISD::SETOLT: // flipped
3793 case ISD::SETGT: return X86::COND_A;
3794 case ISD::SETOLE: // flipped
3796 case ISD::SETGE: return X86::COND_AE;
3797 case ISD::SETUGT: // flipped
3799 case ISD::SETLT: return X86::COND_B;
3800 case ISD::SETUGE: // flipped
3802 case ISD::SETLE: return X86::COND_BE;
3804 case ISD::SETNE: return X86::COND_NE;
3805 case ISD::SETUO: return X86::COND_P;
3806 case ISD::SETO: return X86::COND_NP;
3808 case ISD::SETUNE: return X86::COND_INVALID;
3812 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3813 /// code. Current x86 isa includes the following FP cmov instructions:
3814 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3815 static bool hasFPCMov(unsigned X86CC) {
3831 /// isFPImmLegal - Returns true if the target can instruction select the
3832 /// specified FP immediate natively. If false, the legalizer will
3833 /// materialize the FP immediate as a load from a constant pool.
3834 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3835 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3836 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3842 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3843 ISD::LoadExtType ExtTy,
3845 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3846 // relocation target a movq or addq instruction: don't let the load shrink.
3847 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3848 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3849 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3850 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3854 /// \brief Returns true if it is beneficial to convert a load of a constant
3855 /// to just the constant itself.
3856 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3858 assert(Ty->isIntegerTy());
3860 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3861 if (BitSize == 0 || BitSize > 64)
3866 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3867 unsigned Index) const {
3868 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3871 return (Index == 0 || Index == ResVT.getVectorNumElements());
3874 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3875 // Speculate cttz only if we can directly use TZCNT.
3876 return Subtarget->hasBMI();
3879 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3880 // Speculate ctlz only if we can directly use LZCNT.
3881 return Subtarget->hasLZCNT();
3884 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3885 /// the specified range (L, H].
3886 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3887 return (Val < 0) || (Val >= Low && Val < Hi);
3890 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3891 /// specified value.
3892 static bool isUndefOrEqual(int Val, int CmpVal) {
3893 return (Val < 0 || Val == CmpVal);
3896 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3897 /// from position Pos and ending in Pos+Size, falls within the specified
3898 /// sequential range (Low, Low+Size]. or is undef.
3899 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3900 unsigned Pos, unsigned Size, int Low) {
3901 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3902 if (!isUndefOrEqual(Mask[i], Low))
3907 /// isVEXTRACTIndex - Return true if the specified
3908 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3909 /// suitable for instruction that extract 128 or 256 bit vectors
3910 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3911 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3912 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3915 // The index should be aligned on a vecWidth-bit boundary.
3917 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3919 MVT VT = N->getSimpleValueType(0);
3920 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3921 bool Result = (Index * ElSize) % vecWidth == 0;
3926 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3927 /// operand specifies a subvector insert that is suitable for input to
3928 /// insertion of 128 or 256-bit subvectors
3929 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3930 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3931 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3933 // The index should be aligned on a vecWidth-bit boundary.
3935 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3937 MVT VT = N->getSimpleValueType(0);
3938 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3939 bool Result = (Index * ElSize) % vecWidth == 0;
3944 bool X86::isVINSERT128Index(SDNode *N) {
3945 return isVINSERTIndex(N, 128);
3948 bool X86::isVINSERT256Index(SDNode *N) {
3949 return isVINSERTIndex(N, 256);
3952 bool X86::isVEXTRACT128Index(SDNode *N) {
3953 return isVEXTRACTIndex(N, 128);
3956 bool X86::isVEXTRACT256Index(SDNode *N) {
3957 return isVEXTRACTIndex(N, 256);
3960 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3961 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3962 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3963 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3966 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3968 MVT VecVT = N->getOperand(0).getSimpleValueType();
3969 MVT ElVT = VecVT.getVectorElementType();
3971 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3972 return Index / NumElemsPerChunk;
3975 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3976 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3977 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3978 llvm_unreachable("Illegal insert subvector for VINSERT");
3981 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3983 MVT VecVT = N->getSimpleValueType(0);
3984 MVT ElVT = VecVT.getVectorElementType();
3986 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3987 return Index / NumElemsPerChunk;
3990 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3991 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3992 /// and VINSERTI128 instructions.
3993 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3994 return getExtractVEXTRACTImmediate(N, 128);
3997 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3998 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3999 /// and VINSERTI64x4 instructions.
4000 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4001 return getExtractVEXTRACTImmediate(N, 256);
4004 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4005 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4006 /// and VINSERTI128 instructions.
4007 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4008 return getInsertVINSERTImmediate(N, 128);
4011 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4012 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4013 /// and VINSERTI64x4 instructions.
4014 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4015 return getInsertVINSERTImmediate(N, 256);
4018 /// isZero - Returns true if Elt is a constant integer zero
4019 static bool isZero(SDValue V) {
4020 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4021 return C && C->isNullValue();
4024 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4026 bool X86::isZeroNode(SDValue Elt) {
4029 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4030 return CFP->getValueAPF().isPosZero();
4034 /// getZeroVector - Returns a vector of specified type with all zero elements.
4036 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4037 SelectionDAG &DAG, SDLoc dl) {
4038 assert(VT.isVector() && "Expected a vector type");
4040 // Always build SSE zero vectors as <4 x i32> bitcasted
4041 // to their dest type. This ensures they get CSE'd.
4043 if (VT.is128BitVector()) { // SSE
4044 if (Subtarget->hasSSE2()) { // SSE2
4045 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4046 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4048 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4049 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4051 } else if (VT.is256BitVector()) { // AVX
4052 if (Subtarget->hasInt256()) { // AVX2
4053 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4054 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4055 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4057 // 256-bit logic and arithmetic instructions in AVX are all
4058 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4059 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4060 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4061 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4063 } else if (VT.is512BitVector()) { // AVX-512
4064 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4065 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4066 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4067 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4068 } else if (VT.getScalarType() == MVT::i1) {
4070 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4071 && "Unexpected vector type");
4072 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4073 && "Unexpected vector type");
4074 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4075 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4076 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4078 llvm_unreachable("Unexpected vector type");
4080 return DAG.getBitcast(VT, Vec);
4083 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4084 SelectionDAG &DAG, SDLoc dl,
4085 unsigned vectorWidth) {
4086 assert((vectorWidth == 128 || vectorWidth == 256) &&
4087 "Unsupported vector width");
4088 EVT VT = Vec.getValueType();
4089 EVT ElVT = VT.getVectorElementType();
4090 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4091 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4092 VT.getVectorNumElements()/Factor);
4094 // Extract from UNDEF is UNDEF.
4095 if (Vec.getOpcode() == ISD::UNDEF)
4096 return DAG.getUNDEF(ResultVT);
4098 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4099 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4101 // This is the index of the first element of the vectorWidth-bit chunk
4103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4106 // If the input is a buildvector just emit a smaller one.
4107 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4108 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4109 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4112 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4113 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4116 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4117 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4118 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4119 /// instructions or a simple subregister reference. Idx is an index in the
4120 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4121 /// lowering EXTRACT_VECTOR_ELT operations easier.
4122 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4123 SelectionDAG &DAG, SDLoc dl) {
4124 assert((Vec.getValueType().is256BitVector() ||
4125 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4126 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4129 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4130 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4131 SelectionDAG &DAG, SDLoc dl) {
4132 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4133 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4136 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4137 unsigned IdxVal, SelectionDAG &DAG,
4138 SDLoc dl, unsigned vectorWidth) {
4139 assert((vectorWidth == 128 || vectorWidth == 256) &&
4140 "Unsupported vector width");
4141 // Inserting UNDEF is Result
4142 if (Vec.getOpcode() == ISD::UNDEF)
4144 EVT VT = Vec.getValueType();
4145 EVT ElVT = VT.getVectorElementType();
4146 EVT ResultVT = Result.getValueType();
4148 // Insert the relevant vectorWidth bits.
4149 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4151 // This is the index of the first element of the vectorWidth-bit chunk
4153 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4156 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4157 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4160 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4161 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4162 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4163 /// simple superregister reference. Idx is an index in the 128 bits
4164 /// we want. It need not be aligned to a 128-bit boundary. That makes
4165 /// lowering INSERT_VECTOR_ELT operations easier.
4166 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4167 SelectionDAG &DAG, SDLoc dl) {
4168 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4170 // For insertion into the zero index (low half) of a 256-bit vector, it is
4171 // more efficient to generate a blend with immediate instead of an insert*128.
4172 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4173 // extend the subvector to the size of the result vector. Make sure that
4174 // we are not recursing on that node by checking for undef here.
4175 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4176 Result.getOpcode() != ISD::UNDEF) {
4177 EVT ResultVT = Result.getValueType();
4178 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4179 SDValue Undef = DAG.getUNDEF(ResultVT);
4180 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4183 // The blend instruction, and therefore its mask, depend on the data type.
4184 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4185 if (ScalarType.isFloatingPoint()) {
4186 // Choose either vblendps (float) or vblendpd (double).
4187 unsigned ScalarSize = ScalarType.getSizeInBits();
4188 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4189 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4190 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4191 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4194 const X86Subtarget &Subtarget =
4195 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4197 // AVX2 is needed for 256-bit integer blend support.
4198 // Integers must be cast to 32-bit because there is only vpblendd;
4199 // vpblendw can't be used for this because it has a handicapped mask.
4201 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4202 // is still more efficient than using the wrong domain vinsertf128 that
4203 // will be created by InsertSubVector().
4204 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4206 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4207 Vec256 = DAG.getBitcast(CastVT, Vec256);
4208 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4209 return DAG.getBitcast(ResultVT, Vec256);
4212 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4215 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4216 SelectionDAG &DAG, SDLoc dl) {
4217 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4218 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4221 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4222 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4223 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4224 /// large BUILD_VECTORS.
4225 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4226 unsigned NumElems, SelectionDAG &DAG,
4228 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4229 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4232 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4233 unsigned NumElems, SelectionDAG &DAG,
4235 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4236 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4239 /// getOnesVector - Returns a vector of specified type with all bits set.
4240 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4241 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4242 /// Then bitcast to their original type, ensuring they get CSE'd.
4243 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4245 assert(VT.isVector() && "Expected a vector type");
4247 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4249 if (VT.is256BitVector()) {
4250 if (HasInt256) { // AVX2
4251 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4254 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4255 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4257 } else if (VT.is128BitVector()) {
4258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4260 llvm_unreachable("Unexpected vector type");
4262 return DAG.getBitcast(VT, Vec);
4265 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4266 /// operation of specified width.
4267 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4269 unsigned NumElems = VT.getVectorNumElements();
4270 SmallVector<int, 8> Mask;
4271 Mask.push_back(NumElems);
4272 for (unsigned i = 1; i != NumElems; ++i)
4274 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4277 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4278 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4280 unsigned NumElems = VT.getVectorNumElements();
4281 SmallVector<int, 8> Mask;
4282 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4284 Mask.push_back(i + NumElems);
4286 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4289 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4290 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4292 unsigned NumElems = VT.getVectorNumElements();
4293 SmallVector<int, 8> Mask;
4294 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4295 Mask.push_back(i + Half);
4296 Mask.push_back(i + NumElems + Half);
4298 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4301 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4302 /// vector of zero or undef vector. This produces a shuffle where the low
4303 /// element of V2 is swizzled into the zero/undef vector, landing at element
4304 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4305 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4307 const X86Subtarget *Subtarget,
4308 SelectionDAG &DAG) {
4309 MVT VT = V2.getSimpleValueType();
4311 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4312 unsigned NumElems = VT.getVectorNumElements();
4313 SmallVector<int, 16> MaskVec;
4314 for (unsigned i = 0; i != NumElems; ++i)
4315 // If this is the insertion idx, put the low elt of V2 here.
4316 MaskVec.push_back(i == Idx ? NumElems : i);
4317 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4320 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4321 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4322 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4323 /// shuffles which use a single input multiple times, and in those cases it will
4324 /// adjust the mask to only have indices within that single input.
4325 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4326 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4327 unsigned NumElems = VT.getVectorNumElements();
4331 bool IsFakeUnary = false;
4332 switch(N->getOpcode()) {
4333 case X86ISD::BLENDI:
4334 ImmN = N->getOperand(N->getNumOperands()-1);
4335 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4338 ImmN = N->getOperand(N->getNumOperands()-1);
4339 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4340 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4342 case X86ISD::UNPCKH:
4343 DecodeUNPCKHMask(VT, Mask);
4344 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4346 case X86ISD::UNPCKL:
4347 DecodeUNPCKLMask(VT, Mask);
4348 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4350 case X86ISD::MOVHLPS:
4351 DecodeMOVHLPSMask(NumElems, Mask);
4352 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4354 case X86ISD::MOVLHPS:
4355 DecodeMOVLHPSMask(NumElems, Mask);
4356 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4358 case X86ISD::PALIGNR:
4359 ImmN = N->getOperand(N->getNumOperands()-1);
4360 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4362 case X86ISD::PSHUFD:
4363 case X86ISD::VPERMILPI:
4364 ImmN = N->getOperand(N->getNumOperands()-1);
4365 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4368 case X86ISD::PSHUFHW:
4369 ImmN = N->getOperand(N->getNumOperands()-1);
4370 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4373 case X86ISD::PSHUFLW:
4374 ImmN = N->getOperand(N->getNumOperands()-1);
4375 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4378 case X86ISD::PSHUFB: {
4380 SDValue MaskNode = N->getOperand(1);
4381 while (MaskNode->getOpcode() == ISD::BITCAST)
4382 MaskNode = MaskNode->getOperand(0);
4384 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4385 // If we have a build-vector, then things are easy.
4386 EVT VT = MaskNode.getValueType();
4387 assert(VT.isVector() &&
4388 "Can't produce a non-vector with a build_vector!");
4389 if (!VT.isInteger())
4392 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4394 SmallVector<uint64_t, 32> RawMask;
4395 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4396 SDValue Op = MaskNode->getOperand(i);
4397 if (Op->getOpcode() == ISD::UNDEF) {
4398 RawMask.push_back((uint64_t)SM_SentinelUndef);
4401 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4404 APInt MaskElement = CN->getAPIntValue();
4406 // We now have to decode the element which could be any integer size and
4407 // extract each byte of it.
4408 for (int j = 0; j < NumBytesPerElement; ++j) {
4409 // Note that this is x86 and so always little endian: the low byte is
4410 // the first byte of the mask.
4411 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4412 MaskElement = MaskElement.lshr(8);
4415 DecodePSHUFBMask(RawMask, Mask);
4419 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4423 SDValue Ptr = MaskLoad->getBasePtr();
4424 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4425 Ptr->getOpcode() == X86ISD::WrapperRIP)
4426 Ptr = Ptr->getOperand(0);
4428 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4429 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4432 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4433 DecodePSHUFBMask(C, Mask);
4441 case X86ISD::VPERMI:
4442 ImmN = N->getOperand(N->getNumOperands()-1);
4443 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4448 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4450 case X86ISD::VPERM2X128:
4451 ImmN = N->getOperand(N->getNumOperands()-1);
4452 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4453 if (Mask.empty()) return false;
4455 case X86ISD::MOVSLDUP:
4456 DecodeMOVSLDUPMask(VT, Mask);
4459 case X86ISD::MOVSHDUP:
4460 DecodeMOVSHDUPMask(VT, Mask);
4463 case X86ISD::MOVDDUP:
4464 DecodeMOVDDUPMask(VT, Mask);
4467 case X86ISD::MOVLHPD:
4468 case X86ISD::MOVLPD:
4469 case X86ISD::MOVLPS:
4470 // Not yet implemented
4472 default: llvm_unreachable("unknown target shuffle node");
4475 // If we have a fake unary shuffle, the shuffle mask is spread across two
4476 // inputs that are actually the same node. Re-map the mask to always point
4477 // into the first input.
4480 if (M >= (int)Mask.size())
4486 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4487 /// element of the result of the vector shuffle.
4488 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4491 return SDValue(); // Limit search depth.
4493 SDValue V = SDValue(N, 0);
4494 EVT VT = V.getValueType();
4495 unsigned Opcode = V.getOpcode();
4497 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4498 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4499 int Elt = SV->getMaskElt(Index);
4502 return DAG.getUNDEF(VT.getVectorElementType());
4504 unsigned NumElems = VT.getVectorNumElements();
4505 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4506 : SV->getOperand(1);
4507 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4510 // Recurse into target specific vector shuffles to find scalars.
4511 if (isTargetShuffle(Opcode)) {
4512 MVT ShufVT = V.getSimpleValueType();
4513 unsigned NumElems = ShufVT.getVectorNumElements();
4514 SmallVector<int, 16> ShuffleMask;
4517 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4520 int Elt = ShuffleMask[Index];
4522 return DAG.getUNDEF(ShufVT.getVectorElementType());
4524 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4526 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4530 // Actual nodes that may contain scalar elements
4531 if (Opcode == ISD::BITCAST) {
4532 V = V.getOperand(0);
4533 EVT SrcVT = V.getValueType();
4534 unsigned NumElems = VT.getVectorNumElements();
4536 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4540 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4541 return (Index == 0) ? V.getOperand(0)
4542 : DAG.getUNDEF(VT.getVectorElementType());
4544 if (V.getOpcode() == ISD::BUILD_VECTOR)
4545 return V.getOperand(Index);
4550 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4552 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4553 unsigned NumNonZero, unsigned NumZero,
4555 const X86Subtarget* Subtarget,
4556 const TargetLowering &TLI) {
4564 // SSE4.1 - use PINSRB to insert each byte directly.
4565 if (Subtarget->hasSSE41()) {
4566 for (unsigned i = 0; i < 16; ++i) {
4567 bool isNonZero = (NonZeros & (1 << i)) != 0;
4571 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4573 V = DAG.getUNDEF(MVT::v16i8);
4576 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4577 MVT::v16i8, V, Op.getOperand(i),
4578 DAG.getIntPtrConstant(i, dl));
4585 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4586 for (unsigned i = 0; i < 16; ++i) {
4587 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4588 if (ThisIsNonZero && First) {
4590 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4592 V = DAG.getUNDEF(MVT::v8i16);
4597 SDValue ThisElt, LastElt;
4598 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4599 if (LastIsNonZero) {
4600 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4601 MVT::i16, Op.getOperand(i-1));
4603 if (ThisIsNonZero) {
4604 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4605 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4606 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4608 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4612 if (ThisElt.getNode())
4613 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4614 DAG.getIntPtrConstant(i/2, dl));
4618 return DAG.getBitcast(MVT::v16i8, V);
4621 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4623 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4624 unsigned NumNonZero, unsigned NumZero,
4626 const X86Subtarget* Subtarget,
4627 const TargetLowering &TLI) {
4634 for (unsigned i = 0; i < 8; ++i) {
4635 bool isNonZero = (NonZeros & (1 << i)) != 0;
4639 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4641 V = DAG.getUNDEF(MVT::v8i16);
4644 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4645 MVT::v8i16, V, Op.getOperand(i),
4646 DAG.getIntPtrConstant(i, dl));
4653 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4654 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4655 const X86Subtarget *Subtarget,
4656 const TargetLowering &TLI) {
4657 // Find all zeroable elements.
4658 std::bitset<4> Zeroable;
4659 for (int i=0; i < 4; ++i) {
4660 SDValue Elt = Op->getOperand(i);
4661 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4663 assert(Zeroable.size() - Zeroable.count() > 1 &&
4664 "We expect at least two non-zero elements!");
4666 // We only know how to deal with build_vector nodes where elements are either
4667 // zeroable or extract_vector_elt with constant index.
4668 SDValue FirstNonZero;
4669 unsigned FirstNonZeroIdx;
4670 for (unsigned i=0; i < 4; ++i) {
4673 SDValue Elt = Op->getOperand(i);
4674 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4675 !isa<ConstantSDNode>(Elt.getOperand(1)))
4677 // Make sure that this node is extracting from a 128-bit vector.
4678 MVT VT = Elt.getOperand(0).getSimpleValueType();
4679 if (!VT.is128BitVector())
4681 if (!FirstNonZero.getNode()) {
4683 FirstNonZeroIdx = i;
4687 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4688 SDValue V1 = FirstNonZero.getOperand(0);
4689 MVT VT = V1.getSimpleValueType();
4691 // See if this build_vector can be lowered as a blend with zero.
4693 unsigned EltMaskIdx, EltIdx;
4695 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4696 if (Zeroable[EltIdx]) {
4697 // The zero vector will be on the right hand side.
4698 Mask[EltIdx] = EltIdx+4;
4702 Elt = Op->getOperand(EltIdx);
4703 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4704 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4705 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4707 Mask[EltIdx] = EltIdx;
4711 // Let the shuffle legalizer deal with blend operations.
4712 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4713 if (V1.getSimpleValueType() != VT)
4714 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4715 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4718 // See if we can lower this build_vector to a INSERTPS.
4719 if (!Subtarget->hasSSE41())
4722 SDValue V2 = Elt.getOperand(0);
4723 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4726 bool CanFold = true;
4727 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4731 SDValue Current = Op->getOperand(i);
4732 SDValue SrcVector = Current->getOperand(0);
4735 CanFold = SrcVector == V1 &&
4736 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4742 assert(V1.getNode() && "Expected at least two non-zero elements!");
4743 if (V1.getSimpleValueType() != MVT::v4f32)
4744 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4745 if (V2.getSimpleValueType() != MVT::v4f32)
4746 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4748 // Ok, we can emit an INSERTPS instruction.
4749 unsigned ZMask = Zeroable.to_ulong();
4751 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4752 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4754 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4755 DAG.getIntPtrConstant(InsertPSMask, DL));
4756 return DAG.getBitcast(VT, Result);
4759 /// Return a vector logical shift node.
4760 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4761 unsigned NumBits, SelectionDAG &DAG,
4762 const TargetLowering &TLI, SDLoc dl) {
4763 assert(VT.is128BitVector() && "Unknown type for VShift");
4764 MVT ShVT = MVT::v2i64;
4765 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4766 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4767 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4768 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4769 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4770 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4774 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4776 // Check if the scalar load can be widened into a vector load. And if
4777 // the address is "base + cst" see if the cst can be "absorbed" into
4778 // the shuffle mask.
4779 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4780 SDValue Ptr = LD->getBasePtr();
4781 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4783 EVT PVT = LD->getValueType(0);
4784 if (PVT != MVT::i32 && PVT != MVT::f32)
4789 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4790 FI = FINode->getIndex();
4792 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4793 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4794 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4795 Offset = Ptr.getConstantOperandVal(1);
4796 Ptr = Ptr.getOperand(0);
4801 // FIXME: 256-bit vector instructions don't require a strict alignment,
4802 // improve this code to support it better.
4803 unsigned RequiredAlign = VT.getSizeInBits()/8;
4804 SDValue Chain = LD->getChain();
4805 // Make sure the stack object alignment is at least 16 or 32.
4806 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4807 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4808 if (MFI->isFixedObjectIndex(FI)) {
4809 // Can't change the alignment. FIXME: It's possible to compute
4810 // the exact stack offset and reference FI + adjust offset instead.
4811 // If someone *really* cares about this. That's the way to implement it.
4814 MFI->setObjectAlignment(FI, RequiredAlign);
4818 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4819 // Ptr + (Offset & ~15).
4822 if ((Offset % RequiredAlign) & 3)
4824 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4827 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4828 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4831 int EltNo = (Offset - StartOffset) >> 2;
4832 unsigned NumElems = VT.getVectorNumElements();
4834 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4835 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4836 LD->getPointerInfo().getWithOffset(StartOffset),
4837 false, false, false, 0);
4839 SmallVector<int, 8> Mask(NumElems, EltNo);
4841 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4847 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4848 /// elements can be replaced by a single large load which has the same value as
4849 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4851 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4853 /// FIXME: we'd also like to handle the case where the last elements are zero
4854 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4855 /// There's even a handy isZeroNode for that purpose.
4856 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4857 SDLoc &DL, SelectionDAG &DAG,
4858 bool isAfterLegalize) {
4859 unsigned NumElems = Elts.size();
4861 LoadSDNode *LDBase = nullptr;
4862 unsigned LastLoadedElt = -1U;
4864 // For each element in the initializer, see if we've found a load or an undef.
4865 // If we don't find an initial load element, or later load elements are
4866 // non-consecutive, bail out.
4867 for (unsigned i = 0; i < NumElems; ++i) {
4868 SDValue Elt = Elts[i];
4869 // Look through a bitcast.
4870 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4871 Elt = Elt.getOperand(0);
4872 if (!Elt.getNode() ||
4873 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4876 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4878 LDBase = cast<LoadSDNode>(Elt.getNode());
4882 if (Elt.getOpcode() == ISD::UNDEF)
4885 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4886 EVT LdVT = Elt.getValueType();
4887 // Each loaded element must be the correct fractional portion of the
4888 // requested vector load.
4889 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4891 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4896 // If we have found an entire vector of loads and undefs, then return a large
4897 // load of the entire vector width starting at the base pointer. If we found
4898 // consecutive loads for the low half, generate a vzext_load node.
4899 if (LastLoadedElt == NumElems - 1) {
4900 assert(LDBase && "Did not find base load for merging consecutive loads");
4901 EVT EltVT = LDBase->getValueType(0);
4902 // Ensure that the input vector size for the merged loads matches the
4903 // cumulative size of the input elements.
4904 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4907 if (isAfterLegalize &&
4908 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4911 SDValue NewLd = SDValue();
4913 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4914 LDBase->getPointerInfo(), LDBase->isVolatile(),
4915 LDBase->isNonTemporal(), LDBase->isInvariant(),
4916 LDBase->getAlignment());
4918 if (LDBase->hasAnyUseOfValue(1)) {
4919 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4921 SDValue(NewLd.getNode(), 1));
4922 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4923 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4924 SDValue(NewLd.getNode(), 1));
4930 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4931 //of a v4i32 / v4f32. It's probably worth generalizing.
4932 EVT EltVT = VT.getVectorElementType();
4933 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4934 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4935 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4936 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4938 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4939 LDBase->getPointerInfo(),
4940 LDBase->getAlignment(),
4941 false/*isVolatile*/, true/*ReadMem*/,
4944 // Make sure the newly-created LOAD is in the same position as LDBase in
4945 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4946 // update uses of LDBase's output chain to use the TokenFactor.
4947 if (LDBase->hasAnyUseOfValue(1)) {
4948 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4949 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4950 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4951 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4952 SDValue(ResNode.getNode(), 1));
4955 return DAG.getBitcast(VT, ResNode);
4960 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4961 /// to generate a splat value for the following cases:
4962 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4963 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4964 /// a scalar load, or a constant.
4965 /// The VBROADCAST node is returned when a pattern is found,
4966 /// or SDValue() otherwise.
4967 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4968 SelectionDAG &DAG) {
4969 // VBROADCAST requires AVX.
4970 // TODO: Splats could be generated for non-AVX CPUs using SSE
4971 // instructions, but there's less potential gain for only 128-bit vectors.
4972 if (!Subtarget->hasAVX())
4975 MVT VT = Op.getSimpleValueType();
4978 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4979 "Unsupported vector type for broadcast.");
4984 switch (Op.getOpcode()) {
4986 // Unknown pattern found.
4989 case ISD::BUILD_VECTOR: {
4990 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4991 BitVector UndefElements;
4992 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4994 // We need a splat of a single value to use broadcast, and it doesn't
4995 // make any sense if the value is only in one element of the vector.
4996 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5000 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5001 Ld.getOpcode() == ISD::ConstantFP);
5003 // Make sure that all of the users of a non-constant load are from the
5004 // BUILD_VECTOR node.
5005 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5010 case ISD::VECTOR_SHUFFLE: {
5011 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5013 // Shuffles must have a splat mask where the first element is
5015 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5018 SDValue Sc = Op.getOperand(0);
5019 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5020 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5022 if (!Subtarget->hasInt256())
5025 // Use the register form of the broadcast instruction available on AVX2.
5026 if (VT.getSizeInBits() >= 256)
5027 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5028 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5031 Ld = Sc.getOperand(0);
5032 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5033 Ld.getOpcode() == ISD::ConstantFP);
5035 // The scalar_to_vector node and the suspected
5036 // load node must have exactly one user.
5037 // Constants may have multiple users.
5039 // AVX-512 has register version of the broadcast
5040 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5041 Ld.getValueType().getSizeInBits() >= 32;
5042 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5049 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5050 bool IsGE256 = (VT.getSizeInBits() >= 256);
5052 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5053 // instruction to save 8 or more bytes of constant pool data.
5054 // TODO: If multiple splats are generated to load the same constant,
5055 // it may be detrimental to overall size. There needs to be a way to detect
5056 // that condition to know if this is truly a size win.
5057 const Function *F = DAG.getMachineFunction().getFunction();
5058 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5060 // Handle broadcasting a single constant scalar from the constant pool
5062 // On Sandybridge (no AVX2), it is still better to load a constant vector
5063 // from the constant pool and not to broadcast it from a scalar.
5064 // But override that restriction when optimizing for size.
5065 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5066 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5067 EVT CVT = Ld.getValueType();
5068 assert(!CVT.isVector() && "Must not broadcast a vector type");
5070 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5071 // For size optimization, also splat v2f64 and v2i64, and for size opt
5072 // with AVX2, also splat i8 and i16.
5073 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5074 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5075 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5076 const Constant *C = nullptr;
5077 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5078 C = CI->getConstantIntValue();
5079 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5080 C = CF->getConstantFPValue();
5082 assert(C && "Invalid constant type");
5084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5085 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5086 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5087 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5088 MachinePointerInfo::getConstantPool(),
5089 false, false, false, Alignment);
5091 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5095 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5097 // Handle AVX2 in-register broadcasts.
5098 if (!IsLoad && Subtarget->hasInt256() &&
5099 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5100 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5102 // The scalar source must be a normal load.
5106 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5107 (Subtarget->hasVLX() && ScalarSize == 64))
5108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5110 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5111 // double since there is no vbroadcastsd xmm
5112 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5113 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5114 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5117 // Unsupported broadcast.
5121 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5122 /// underlying vector and index.
5124 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5126 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5128 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5129 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5132 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5134 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5136 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5137 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5140 // In this case the vector is the extract_subvector expression and the index
5141 // is 2, as specified by the shuffle.
5142 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5143 SDValue ShuffleVec = SVOp->getOperand(0);
5144 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5145 assert(ShuffleVecVT.getVectorElementType() ==
5146 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5148 int ShuffleIdx = SVOp->getMaskElt(Idx);
5149 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5150 ExtractedFromVec = ShuffleVec;
5156 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5157 MVT VT = Op.getSimpleValueType();
5159 // Skip if insert_vec_elt is not supported.
5160 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5161 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5165 unsigned NumElems = Op.getNumOperands();
5169 SmallVector<unsigned, 4> InsertIndices;
5170 SmallVector<int, 8> Mask(NumElems, -1);
5172 for (unsigned i = 0; i != NumElems; ++i) {
5173 unsigned Opc = Op.getOperand(i).getOpcode();
5175 if (Opc == ISD::UNDEF)
5178 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5179 // Quit if more than 1 elements need inserting.
5180 if (InsertIndices.size() > 1)
5183 InsertIndices.push_back(i);
5187 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5188 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5189 // Quit if non-constant index.
5190 if (!isa<ConstantSDNode>(ExtIdx))
5192 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5194 // Quit if extracted from vector of different type.
5195 if (ExtractedFromVec.getValueType() != VT)
5198 if (!VecIn1.getNode())
5199 VecIn1 = ExtractedFromVec;
5200 else if (VecIn1 != ExtractedFromVec) {
5201 if (!VecIn2.getNode())
5202 VecIn2 = ExtractedFromVec;
5203 else if (VecIn2 != ExtractedFromVec)
5204 // Quit if more than 2 vectors to shuffle
5208 if (ExtractedFromVec == VecIn1)
5210 else if (ExtractedFromVec == VecIn2)
5211 Mask[i] = Idx + NumElems;
5214 if (!VecIn1.getNode())
5217 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5218 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5219 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5220 unsigned Idx = InsertIndices[i];
5221 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5222 DAG.getIntPtrConstant(Idx, DL));
5228 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5229 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5230 Op.getScalarValueSizeInBits() == 1 &&
5231 "Can not convert non-constant vector");
5232 uint64_t Immediate = 0;
5233 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5234 SDValue In = Op.getOperand(idx);
5235 if (In.getOpcode() != ISD::UNDEF)
5236 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5240 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5241 return DAG.getConstant(Immediate, dl, VT);
5243 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5245 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5247 MVT VT = Op.getSimpleValueType();
5248 assert((VT.getVectorElementType() == MVT::i1) &&
5249 "Unexpected type in LowerBUILD_VECTORvXi1!");
5252 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5253 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5254 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5255 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5258 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5259 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5260 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5261 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5264 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5265 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5266 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5267 return DAG.getBitcast(VT, Imm);
5268 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5269 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5270 DAG.getIntPtrConstant(0, dl));
5273 // Vector has one or more non-const elements
5274 uint64_t Immediate = 0;
5275 SmallVector<unsigned, 16> NonConstIdx;
5276 bool IsSplat = true;
5277 bool HasConstElts = false;
5279 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5280 SDValue In = Op.getOperand(idx);
5281 if (In.getOpcode() == ISD::UNDEF)
5283 if (!isa<ConstantSDNode>(In))
5284 NonConstIdx.push_back(idx);
5286 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5287 HasConstElts = true;
5291 else if (In != Op.getOperand(SplatIdx))
5295 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5297 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5298 DAG.getConstant(1, dl, VT),
5299 DAG.getConstant(0, dl, VT));
5301 // insert elements one by one
5305 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5306 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5308 else if (HasConstElts)
5309 Imm = DAG.getConstant(0, dl, VT);
5311 Imm = DAG.getUNDEF(VT);
5312 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5313 DstVec = DAG.getBitcast(VT, Imm);
5315 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5316 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5317 DAG.getIntPtrConstant(0, dl));
5320 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5321 unsigned InsertIdx = NonConstIdx[i];
5322 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5323 Op.getOperand(InsertIdx),
5324 DAG.getIntPtrConstant(InsertIdx, dl));
5329 /// \brief Return true if \p N implements a horizontal binop and return the
5330 /// operands for the horizontal binop into V0 and V1.
5332 /// This is a helper function of LowerToHorizontalOp().
5333 /// This function checks that the build_vector \p N in input implements a
5334 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5335 /// operation to match.
5336 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5337 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5338 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5341 /// This function only analyzes elements of \p N whose indices are
5342 /// in range [BaseIdx, LastIdx).
5343 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5345 unsigned BaseIdx, unsigned LastIdx,
5346 SDValue &V0, SDValue &V1) {
5347 EVT VT = N->getValueType(0);
5349 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5350 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5351 "Invalid Vector in input!");
5353 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5354 bool CanFold = true;
5355 unsigned ExpectedVExtractIdx = BaseIdx;
5356 unsigned NumElts = LastIdx - BaseIdx;
5357 V0 = DAG.getUNDEF(VT);
5358 V1 = DAG.getUNDEF(VT);
5360 // Check if N implements a horizontal binop.
5361 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5362 SDValue Op = N->getOperand(i + BaseIdx);
5365 if (Op->getOpcode() == ISD::UNDEF) {
5366 // Update the expected vector extract index.
5367 if (i * 2 == NumElts)
5368 ExpectedVExtractIdx = BaseIdx;
5369 ExpectedVExtractIdx += 2;
5373 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5378 SDValue Op0 = Op.getOperand(0);
5379 SDValue Op1 = Op.getOperand(1);
5381 // Try to match the following pattern:
5382 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5383 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5384 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5385 Op0.getOperand(0) == Op1.getOperand(0) &&
5386 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5387 isa<ConstantSDNode>(Op1.getOperand(1)));
5391 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5392 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5394 if (i * 2 < NumElts) {
5395 if (V0.getOpcode() == ISD::UNDEF) {
5396 V0 = Op0.getOperand(0);
5397 if (V0.getValueType() != VT)
5401 if (V1.getOpcode() == ISD::UNDEF) {
5402 V1 = Op0.getOperand(0);
5403 if (V1.getValueType() != VT)
5406 if (i * 2 == NumElts)
5407 ExpectedVExtractIdx = BaseIdx;
5410 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5411 if (I0 == ExpectedVExtractIdx)
5412 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5413 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5414 // Try to match the following dag sequence:
5415 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5416 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5420 ExpectedVExtractIdx += 2;
5426 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5427 /// a concat_vector.
5429 /// This is a helper function of LowerToHorizontalOp().
5430 /// This function expects two 256-bit vectors called V0 and V1.
5431 /// At first, each vector is split into two separate 128-bit vectors.
5432 /// Then, the resulting 128-bit vectors are used to implement two
5433 /// horizontal binary operations.
5435 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5437 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5438 /// the two new horizontal binop.
5439 /// When Mode is set, the first horizontal binop dag node would take as input
5440 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5441 /// horizontal binop dag node would take as input the lower 128-bit of V1
5442 /// and the upper 128-bit of V1.
5444 /// HADD V0_LO, V0_HI
5445 /// HADD V1_LO, V1_HI
5447 /// Otherwise, the first horizontal binop dag node takes as input the lower
5448 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5449 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5451 /// HADD V0_LO, V1_LO
5452 /// HADD V0_HI, V1_HI
5454 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5455 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5456 /// the upper 128-bits of the result.
5457 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5458 SDLoc DL, SelectionDAG &DAG,
5459 unsigned X86Opcode, bool Mode,
5460 bool isUndefLO, bool isUndefHI) {
5461 EVT VT = V0.getValueType();
5462 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5463 "Invalid nodes in input!");
5465 unsigned NumElts = VT.getVectorNumElements();
5466 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5467 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5468 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5469 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5470 EVT NewVT = V0_LO.getValueType();
5472 SDValue LO = DAG.getUNDEF(NewVT);
5473 SDValue HI = DAG.getUNDEF(NewVT);
5476 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5477 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5478 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5479 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5480 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5482 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5483 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5484 V1_LO->getOpcode() != ISD::UNDEF))
5485 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5487 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5488 V1_HI->getOpcode() != ISD::UNDEF))
5489 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5492 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5495 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5497 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5498 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5499 EVT VT = BV->getValueType(0);
5500 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5501 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5505 unsigned NumElts = VT.getVectorNumElements();
5506 SDValue InVec0 = DAG.getUNDEF(VT);
5507 SDValue InVec1 = DAG.getUNDEF(VT);
5509 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5510 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5512 // Odd-numbered elements in the input build vector are obtained from
5513 // adding two integer/float elements.
5514 // Even-numbered elements in the input build vector are obtained from
5515 // subtracting two integer/float elements.
5516 unsigned ExpectedOpcode = ISD::FSUB;
5517 unsigned NextExpectedOpcode = ISD::FADD;
5518 bool AddFound = false;
5519 bool SubFound = false;
5521 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5522 SDValue Op = BV->getOperand(i);
5524 // Skip 'undef' values.
5525 unsigned Opcode = Op.getOpcode();
5526 if (Opcode == ISD::UNDEF) {
5527 std::swap(ExpectedOpcode, NextExpectedOpcode);
5531 // Early exit if we found an unexpected opcode.
5532 if (Opcode != ExpectedOpcode)
5535 SDValue Op0 = Op.getOperand(0);
5536 SDValue Op1 = Op.getOperand(1);
5538 // Try to match the following pattern:
5539 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5540 // Early exit if we cannot match that sequence.
5541 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5542 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5543 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5544 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5545 Op0.getOperand(1) != Op1.getOperand(1))
5548 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5552 // We found a valid add/sub node. Update the information accordingly.
5558 // Update InVec0 and InVec1.
5559 if (InVec0.getOpcode() == ISD::UNDEF) {
5560 InVec0 = Op0.getOperand(0);
5561 if (InVec0.getValueType() != VT)
5564 if (InVec1.getOpcode() == ISD::UNDEF) {
5565 InVec1 = Op1.getOperand(0);
5566 if (InVec1.getValueType() != VT)
5570 // Make sure that operands in input to each add/sub node always
5571 // come from a same pair of vectors.
5572 if (InVec0 != Op0.getOperand(0)) {
5573 if (ExpectedOpcode == ISD::FSUB)
5576 // FADD is commutable. Try to commute the operands
5577 // and then test again.
5578 std::swap(Op0, Op1);
5579 if (InVec0 != Op0.getOperand(0))
5583 if (InVec1 != Op1.getOperand(0))
5586 // Update the pair of expected opcodes.
5587 std::swap(ExpectedOpcode, NextExpectedOpcode);
5590 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5591 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5592 InVec1.getOpcode() != ISD::UNDEF)
5593 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5598 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5599 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5600 const X86Subtarget *Subtarget,
5601 SelectionDAG &DAG) {
5602 EVT VT = BV->getValueType(0);
5603 unsigned NumElts = VT.getVectorNumElements();
5604 unsigned NumUndefsLO = 0;
5605 unsigned NumUndefsHI = 0;
5606 unsigned Half = NumElts/2;
5608 // Count the number of UNDEF operands in the build_vector in input.
5609 for (unsigned i = 0, e = Half; i != e; ++i)
5610 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5613 for (unsigned i = Half, e = NumElts; i != e; ++i)
5614 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5617 // Early exit if this is either a build_vector of all UNDEFs or all the
5618 // operands but one are UNDEF.
5619 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5623 SDValue InVec0, InVec1;
5624 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5625 // Try to match an SSE3 float HADD/HSUB.
5626 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5627 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5629 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5630 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5631 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5632 // Try to match an SSSE3 integer HADD/HSUB.
5633 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5634 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5636 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5637 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5640 if (!Subtarget->hasAVX())
5643 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5644 // Try to match an AVX horizontal add/sub of packed single/double
5645 // precision floating point values from 256-bit vectors.
5646 SDValue InVec2, InVec3;
5647 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5648 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5649 ((InVec0.getOpcode() == ISD::UNDEF ||
5650 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5651 ((InVec1.getOpcode() == ISD::UNDEF ||
5652 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5653 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5655 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5656 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5657 ((InVec0.getOpcode() == ISD::UNDEF ||
5658 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5659 ((InVec1.getOpcode() == ISD::UNDEF ||
5660 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5661 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5662 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5663 // Try to match an AVX2 horizontal add/sub of signed integers.
5664 SDValue InVec2, InVec3;
5666 bool CanFold = true;
5668 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5669 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5670 ((InVec0.getOpcode() == ISD::UNDEF ||
5671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5672 ((InVec1.getOpcode() == ISD::UNDEF ||
5673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5674 X86Opcode = X86ISD::HADD;
5675 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5676 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5677 ((InVec0.getOpcode() == ISD::UNDEF ||
5678 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5679 ((InVec1.getOpcode() == ISD::UNDEF ||
5680 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5681 X86Opcode = X86ISD::HSUB;
5686 // Fold this build_vector into a single horizontal add/sub.
5687 // Do this only if the target has AVX2.
5688 if (Subtarget->hasAVX2())
5689 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5691 // Do not try to expand this build_vector into a pair of horizontal
5692 // add/sub if we can emit a pair of scalar add/sub.
5693 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5696 // Convert this build_vector into a pair of horizontal binop followed by
5698 bool isUndefLO = NumUndefsLO == Half;
5699 bool isUndefHI = NumUndefsHI == Half;
5700 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5701 isUndefLO, isUndefHI);
5705 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5706 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5708 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5709 X86Opcode = X86ISD::HADD;
5710 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5711 X86Opcode = X86ISD::HSUB;
5712 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5713 X86Opcode = X86ISD::FHADD;
5714 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5715 X86Opcode = X86ISD::FHSUB;
5719 // Don't try to expand this build_vector into a pair of horizontal add/sub
5720 // if we can simply emit a pair of scalar add/sub.
5721 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5724 // Convert this build_vector into two horizontal add/sub followed by
5726 bool isUndefLO = NumUndefsLO == Half;
5727 bool isUndefHI = NumUndefsHI == Half;
5728 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5729 isUndefLO, isUndefHI);
5736 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5739 MVT VT = Op.getSimpleValueType();
5740 MVT ExtVT = VT.getVectorElementType();
5741 unsigned NumElems = Op.getNumOperands();
5743 // Generate vectors for predicate vectors.
5744 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5745 return LowerBUILD_VECTORvXi1(Op, DAG);
5747 // Vectors containing all zeros can be matched by pxor and xorps later
5748 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5749 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5750 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5751 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5754 return getZeroVector(VT, Subtarget, DAG, dl);
5757 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5758 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5759 // vpcmpeqd on 256-bit vectors.
5760 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5761 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5764 if (!VT.is512BitVector())
5765 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5768 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5769 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5771 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5772 return HorizontalOp;
5773 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5776 unsigned EVTBits = ExtVT.getSizeInBits();
5778 unsigned NumZero = 0;
5779 unsigned NumNonZero = 0;
5780 unsigned NonZeros = 0;
5781 bool IsAllConstants = true;
5782 SmallSet<SDValue, 8> Values;
5783 for (unsigned i = 0; i < NumElems; ++i) {
5784 SDValue Elt = Op.getOperand(i);
5785 if (Elt.getOpcode() == ISD::UNDEF)
5788 if (Elt.getOpcode() != ISD::Constant &&
5789 Elt.getOpcode() != ISD::ConstantFP)
5790 IsAllConstants = false;
5791 if (X86::isZeroNode(Elt))
5794 NonZeros |= (1 << i);
5799 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5800 if (NumNonZero == 0)
5801 return DAG.getUNDEF(VT);
5803 // Special case for single non-zero, non-undef, element.
5804 if (NumNonZero == 1) {
5805 unsigned Idx = countTrailingZeros(NonZeros);
5806 SDValue Item = Op.getOperand(Idx);
5808 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5809 // the value are obviously zero, truncate the value to i32 and do the
5810 // insertion that way. Only do this if the value is non-constant or if the
5811 // value is a constant being inserted into element 0. It is cheaper to do
5812 // a constant pool load than it is to do a movd + shuffle.
5813 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5814 (!IsAllConstants || Idx == 0)) {
5815 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5817 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5818 EVT VecVT = MVT::v4i32;
5820 // Truncate the value (which may itself be a constant) to i32, and
5821 // convert it to a vector with movd (S2V+shuffle to zero extend).
5822 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5823 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5824 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5825 Item, Idx * 2, true, Subtarget, DAG));
5829 // If we have a constant or non-constant insertion into the low element of
5830 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5831 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5832 // depending on what the source datatype is.
5835 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5837 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5838 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5839 if (VT.is512BitVector()) {
5840 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5841 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5842 Item, DAG.getIntPtrConstant(0, dl));
5844 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5845 "Expected an SSE value type!");
5846 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5847 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5848 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5851 // We can't directly insert an i8 or i16 into a vector, so zero extend
5853 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5854 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5855 if (VT.is256BitVector()) {
5856 if (Subtarget->hasAVX()) {
5857 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5858 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5860 // Without AVX, we need to extend to a 128-bit vector and then
5861 // insert into the 256-bit vector.
5862 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5863 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5864 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5867 assert(VT.is128BitVector() && "Expected an SSE value type!");
5868 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5869 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5871 return DAG.getBitcast(VT, Item);
5875 // Is it a vector logical left shift?
5876 if (NumElems == 2 && Idx == 1 &&
5877 X86::isZeroNode(Op.getOperand(0)) &&
5878 !X86::isZeroNode(Op.getOperand(1))) {
5879 unsigned NumBits = VT.getSizeInBits();
5880 return getVShift(true, VT,
5881 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5882 VT, Op.getOperand(1)),
5883 NumBits/2, DAG, *this, dl);
5886 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5889 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5890 // is a non-constant being inserted into an element other than the low one,
5891 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5892 // movd/movss) to move this into the low element, then shuffle it into
5894 if (EVTBits == 32) {
5895 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5896 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5900 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5901 if (Values.size() == 1) {
5902 if (EVTBits == 32) {
5903 // Instead of a shuffle like this:
5904 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5905 // Check if it's possible to issue this instead.
5906 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5907 unsigned Idx = countTrailingZeros(NonZeros);
5908 SDValue Item = Op.getOperand(Idx);
5909 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5910 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5915 // A vector full of immediates; various special cases are already
5916 // handled, so this is best done with a single constant-pool load.
5920 // For AVX-length vectors, see if we can use a vector load to get all of the
5921 // elements, otherwise build the individual 128-bit pieces and use
5922 // shuffles to put them in place.
5923 if (VT.is256BitVector() || VT.is512BitVector()) {
5924 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5926 // Check for a build vector of consecutive loads.
5927 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5930 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5932 // Build both the lower and upper subvector.
5933 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5934 makeArrayRef(&V[0], NumElems/2));
5935 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5936 makeArrayRef(&V[NumElems / 2], NumElems/2));
5938 // Recreate the wider vector with the lower and upper part.
5939 if (VT.is256BitVector())
5940 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5941 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5944 // Let legalizer expand 2-wide build_vectors.
5945 if (EVTBits == 64) {
5946 if (NumNonZero == 1) {
5947 // One half is zero or undef.
5948 unsigned Idx = countTrailingZeros(NonZeros);
5949 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5950 Op.getOperand(Idx));
5951 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5956 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5957 if (EVTBits == 8 && NumElems == 16)
5958 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5962 if (EVTBits == 16 && NumElems == 8)
5963 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5967 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5968 if (EVTBits == 32 && NumElems == 4)
5969 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5972 // If element VT is == 32 bits, turn it into a number of shuffles.
5973 SmallVector<SDValue, 8> V(NumElems);
5974 if (NumElems == 4 && NumZero > 0) {
5975 for (unsigned i = 0; i < 4; ++i) {
5976 bool isZero = !(NonZeros & (1 << i));
5978 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5980 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5983 for (unsigned i = 0; i < 2; ++i) {
5984 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5987 V[i] = V[i*2]; // Must be a zero vector.
5990 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5993 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5996 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6001 bool Reverse1 = (NonZeros & 0x3) == 2;
6002 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6006 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6007 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6009 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6012 if (Values.size() > 1 && VT.is128BitVector()) {
6013 // Check for a build vector of consecutive loads.
6014 for (unsigned i = 0; i < NumElems; ++i)
6015 V[i] = Op.getOperand(i);
6017 // Check for elements which are consecutive loads.
6018 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6021 // Check for a build vector from mostly shuffle plus few inserting.
6022 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6025 // For SSE 4.1, use insertps to put the high elements into the low element.
6026 if (Subtarget->hasSSE41()) {
6028 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6029 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6031 Result = DAG.getUNDEF(VT);
6033 for (unsigned i = 1; i < NumElems; ++i) {
6034 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6035 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6036 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6041 // Otherwise, expand into a number of unpckl*, start by extending each of
6042 // our (non-undef) elements to the full vector width with the element in the
6043 // bottom slot of the vector (which generates no code for SSE).
6044 for (unsigned i = 0; i < NumElems; ++i) {
6045 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6046 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6048 V[i] = DAG.getUNDEF(VT);
6051 // Next, we iteratively mix elements, e.g. for v4f32:
6052 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6053 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6054 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6055 unsigned EltStride = NumElems >> 1;
6056 while (EltStride != 0) {
6057 for (unsigned i = 0; i < EltStride; ++i) {
6058 // If V[i+EltStride] is undef and this is the first round of mixing,
6059 // then it is safe to just drop this shuffle: V[i] is already in the
6060 // right place, the one element (since it's the first round) being
6061 // inserted as undef can be dropped. This isn't safe for successive
6062 // rounds because they will permute elements within both vectors.
6063 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6064 EltStride == NumElems/2)
6067 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6076 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6077 // to create 256-bit vectors from two other 128-bit ones.
6078 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6080 MVT ResVT = Op.getSimpleValueType();
6082 assert((ResVT.is256BitVector() ||
6083 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6085 SDValue V1 = Op.getOperand(0);
6086 SDValue V2 = Op.getOperand(1);
6087 unsigned NumElems = ResVT.getVectorNumElements();
6088 if (ResVT.is256BitVector())
6089 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6091 if (Op.getNumOperands() == 4) {
6092 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6093 ResVT.getVectorNumElements()/2);
6094 SDValue V3 = Op.getOperand(2);
6095 SDValue V4 = Op.getOperand(3);
6096 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6097 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6099 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6102 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6103 const X86Subtarget *Subtarget,
6104 SelectionDAG & DAG) {
6106 MVT ResVT = Op.getSimpleValueType();
6107 unsigned NumOfOperands = Op.getNumOperands();
6109 assert(isPowerOf2_32(NumOfOperands) &&
6110 "Unexpected number of operands in CONCAT_VECTORS");
6112 if (NumOfOperands > 2) {
6113 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6114 ResVT.getVectorNumElements()/2);
6115 SmallVector<SDValue, 2> Ops;
6116 for (unsigned i = 0; i < NumOfOperands/2; i++)
6117 Ops.push_back(Op.getOperand(i));
6118 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6120 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6121 Ops.push_back(Op.getOperand(i));
6122 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6123 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6126 SDValue V1 = Op.getOperand(0);
6127 SDValue V2 = Op.getOperand(1);
6128 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6129 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6131 if (IsZeroV1 && IsZeroV2)
6132 return getZeroVector(ResVT, Subtarget, DAG, dl);
6134 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6135 SDValue Undef = DAG.getUNDEF(ResVT);
6136 unsigned NumElems = ResVT.getVectorNumElements();
6137 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6139 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6140 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6144 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6145 // Zero the upper bits of V1
6146 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6147 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6150 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6153 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6154 const X86Subtarget *Subtarget,
6155 SelectionDAG &DAG) {
6156 MVT VT = Op.getSimpleValueType();
6157 if (VT.getVectorElementType() == MVT::i1)
6158 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6160 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6161 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6162 Op.getNumOperands() == 4)));
6164 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6165 // from two other 128-bit ones.
6167 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6168 return LowerAVXCONCAT_VECTORS(Op, DAG);
6172 //===----------------------------------------------------------------------===//
6173 // Vector shuffle lowering
6175 // This is an experimental code path for lowering vector shuffles on x86. It is
6176 // designed to handle arbitrary vector shuffles and blends, gracefully
6177 // degrading performance as necessary. It works hard to recognize idiomatic
6178 // shuffles and lower them to optimal instruction patterns without leaving
6179 // a framework that allows reasonably efficient handling of all vector shuffle
6181 //===----------------------------------------------------------------------===//
6183 /// \brief Tiny helper function to identify a no-op mask.
6185 /// This is a somewhat boring predicate function. It checks whether the mask
6186 /// array input, which is assumed to be a single-input shuffle mask of the kind
6187 /// used by the X86 shuffle instructions (not a fully general
6188 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6189 /// in-place shuffle are 'no-op's.
6190 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6191 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6192 if (Mask[i] != -1 && Mask[i] != i)
6197 /// \brief Helper function to classify a mask as a single-input mask.
6199 /// This isn't a generic single-input test because in the vector shuffle
6200 /// lowering we canonicalize single inputs to be the first input operand. This
6201 /// means we can more quickly test for a single input by only checking whether
6202 /// an input from the second operand exists. We also assume that the size of
6203 /// mask corresponds to the size of the input vectors which isn't true in the
6204 /// fully general case.
6205 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6207 if (M >= (int)Mask.size())
6212 /// \brief Test whether there are elements crossing 128-bit lanes in this
6215 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6216 /// and we routinely test for these.
6217 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6218 int LaneSize = 128 / VT.getScalarSizeInBits();
6219 int Size = Mask.size();
6220 for (int i = 0; i < Size; ++i)
6221 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6226 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6228 /// This checks a shuffle mask to see if it is performing the same
6229 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6230 /// that it is also not lane-crossing. It may however involve a blend from the
6231 /// same lane of a second vector.
6233 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6234 /// non-trivial to compute in the face of undef lanes. The representation is
6235 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6236 /// entries from both V1 and V2 inputs to the wider mask.
6238 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6239 SmallVectorImpl<int> &RepeatedMask) {
6240 int LaneSize = 128 / VT.getScalarSizeInBits();
6241 RepeatedMask.resize(LaneSize, -1);
6242 int Size = Mask.size();
6243 for (int i = 0; i < Size; ++i) {
6246 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6247 // This entry crosses lanes, so there is no way to model this shuffle.
6250 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6251 if (RepeatedMask[i % LaneSize] == -1)
6252 // This is the first non-undef entry in this slot of a 128-bit lane.
6253 RepeatedMask[i % LaneSize] =
6254 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6255 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6256 // Found a mismatch with the repeated mask.
6262 /// \brief Test whether a shuffle mask is equivalent within each 256-bit lane.
6264 /// This checks a shuffle mask to see if it is performing the same
6265 /// 256-bit lane-relative shuffle in each 256-bit lane. This trivially implies
6266 /// that it is also not lane-crossing. It may however involve a blend from the
6267 /// same lane of a second vector.
6269 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6270 /// non-trivial to compute in the face of undef lanes. The representation is
6271 /// *not* suitable for use with existing 256-bit shuffles as it will contain
6272 /// entries from both V1 and V2 inputs to the wider mask.
6274 is256BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6275 SmallVectorImpl<int> &RepeatedMask) {
6276 int LaneSize = 256 / VT.getScalarSizeInBits();
6277 RepeatedMask.resize(LaneSize, -1);
6278 int Size = Mask.size();
6279 for (int i = 0; i < Size; ++i) {
6282 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6283 // This entry crosses lanes, so there is no way to model this shuffle.
6286 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6287 if (RepeatedMask[i % LaneSize] == -1)
6288 // This is the first non-undef entry in this slot of a 256-bit lane.
6289 RepeatedMask[i % LaneSize] =
6290 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6291 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6292 // Found a mismatch with the repeated mask.
6298 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6301 /// This is a fast way to test a shuffle mask against a fixed pattern:
6303 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6305 /// It returns true if the mask is exactly as wide as the argument list, and
6306 /// each element of the mask is either -1 (signifying undef) or the value given
6307 /// in the argument.
6308 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6309 ArrayRef<int> ExpectedMask) {
6310 if (Mask.size() != ExpectedMask.size())
6313 int Size = Mask.size();
6315 // If the values are build vectors, we can look through them to find
6316 // equivalent inputs that make the shuffles equivalent.
6317 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6318 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6320 for (int i = 0; i < Size; ++i)
6321 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6322 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6323 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6324 if (!MaskBV || !ExpectedBV ||
6325 MaskBV->getOperand(Mask[i] % Size) !=
6326 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6333 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6335 /// This helper function produces an 8-bit shuffle immediate corresponding to
6336 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6337 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6340 /// NB: We rely heavily on "undef" masks preserving the input lane.
6341 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6342 SelectionDAG &DAG) {
6343 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6344 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6345 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6346 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6347 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6350 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6351 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6352 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6353 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6354 return DAG.getConstant(Imm, DL, MVT::i8);
6357 /// \brief Get a 8-bit shuffle, 1 bit per lane, immediate for a mask.
6359 /// This helper function produces an 8-bit shuffle immediate corresponding to
6360 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6361 /// shuffling 8 lanes.
6362 static SDValue get1bitLaneShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6363 SelectionDAG &DAG) {
6364 assert(Mask.size() <= 8 &&
6365 "Up to 8 elts may be in Imm8 1-bit lane shuffle mask");
6367 for (unsigned i = 0; i < Mask.size(); ++i)
6369 Imm |= (Mask[i] % 2) << i;
6370 return DAG.getConstant(Imm, DL, MVT::i8);
6373 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6375 /// This is used as a fallback approach when first class blend instructions are
6376 /// unavailable. Currently it is only suitable for integer vectors, but could
6377 /// be generalized for floating point vectors if desirable.
6378 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6379 SDValue V2, ArrayRef<int> Mask,
6380 SelectionDAG &DAG) {
6381 assert(VT.isInteger() && "Only supports integer vector types!");
6382 MVT EltVT = VT.getScalarType();
6383 int NumEltBits = EltVT.getSizeInBits();
6384 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6385 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6387 SmallVector<SDValue, 16> MaskOps;
6388 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6389 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6390 return SDValue(); // Shuffled input!
6391 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6394 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6395 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6396 // We have to cast V2 around.
6397 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6398 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6399 DAG.getBitcast(MaskVT, V1Mask),
6400 DAG.getBitcast(MaskVT, V2)));
6401 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6404 /// \brief Try to emit a blend instruction for a shuffle.
6406 /// This doesn't do any checks for the availability of instructions for blending
6407 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6408 /// be matched in the backend with the type given. What it does check for is
6409 /// that the shuffle mask is in fact a blend.
6410 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6411 SDValue V2, ArrayRef<int> Mask,
6412 const X86Subtarget *Subtarget,
6413 SelectionDAG &DAG) {
6414 unsigned BlendMask = 0;
6415 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6416 if (Mask[i] >= Size) {
6417 if (Mask[i] != i + Size)
6418 return SDValue(); // Shuffled V2 input!
6419 BlendMask |= 1u << i;
6422 if (Mask[i] >= 0 && Mask[i] != i)
6423 return SDValue(); // Shuffled V1 input!
6425 switch (VT.SimpleTy) {
6430 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6431 DAG.getConstant(BlendMask, DL, MVT::i8));
6435 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6439 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6440 // that instruction.
6441 if (Subtarget->hasAVX2()) {
6442 // Scale the blend by the number of 32-bit dwords per element.
6443 int Scale = VT.getScalarSizeInBits() / 32;
6445 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6446 if (Mask[i] >= Size)
6447 for (int j = 0; j < Scale; ++j)
6448 BlendMask |= 1u << (i * Scale + j);
6450 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6451 V1 = DAG.getBitcast(BlendVT, V1);
6452 V2 = DAG.getBitcast(BlendVT, V2);
6453 return DAG.getBitcast(
6454 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6455 DAG.getConstant(BlendMask, DL, MVT::i8)));
6459 // For integer shuffles we need to expand the mask and cast the inputs to
6460 // v8i16s prior to blending.
6461 int Scale = 8 / VT.getVectorNumElements();
6463 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6464 if (Mask[i] >= Size)
6465 for (int j = 0; j < Scale; ++j)
6466 BlendMask |= 1u << (i * Scale + j);
6468 V1 = DAG.getBitcast(MVT::v8i16, V1);
6469 V2 = DAG.getBitcast(MVT::v8i16, V2);
6470 return DAG.getBitcast(VT,
6471 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6472 DAG.getConstant(BlendMask, DL, MVT::i8)));
6476 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6477 SmallVector<int, 8> RepeatedMask;
6478 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6479 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6480 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6482 for (int i = 0; i < 8; ++i)
6483 if (RepeatedMask[i] >= 16)
6484 BlendMask |= 1u << i;
6485 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6486 DAG.getConstant(BlendMask, DL, MVT::i8));
6492 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6493 "256-bit byte-blends require AVX2 support!");
6495 // Scale the blend by the number of bytes per element.
6496 int Scale = VT.getScalarSizeInBits() / 8;
6498 // This form of blend is always done on bytes. Compute the byte vector
6500 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6502 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6503 // mix of LLVM's code generator and the x86 backend. We tell the code
6504 // generator that boolean values in the elements of an x86 vector register
6505 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6506 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6507 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6508 // of the element (the remaining are ignored) and 0 in that high bit would
6509 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6510 // the LLVM model for boolean values in vector elements gets the relevant
6511 // bit set, it is set backwards and over constrained relative to x86's
6513 SmallVector<SDValue, 32> VSELECTMask;
6514 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6515 for (int j = 0; j < Scale; ++j)
6516 VSELECTMask.push_back(
6517 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6518 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6521 V1 = DAG.getBitcast(BlendVT, V1);
6522 V2 = DAG.getBitcast(BlendVT, V2);
6523 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6524 DAG.getNode(ISD::BUILD_VECTOR, DL,
6525 BlendVT, VSELECTMask),
6530 llvm_unreachable("Not a supported integer vector type!");
6534 /// \brief Try to lower as a blend of elements from two inputs followed by
6535 /// a single-input permutation.
6537 /// This matches the pattern where we can blend elements from two inputs and
6538 /// then reduce the shuffle to a single-input permutation.
6539 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6542 SelectionDAG &DAG) {
6543 // We build up the blend mask while checking whether a blend is a viable way
6544 // to reduce the shuffle.
6545 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6546 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6548 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6552 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6554 if (BlendMask[Mask[i] % Size] == -1)
6555 BlendMask[Mask[i] % Size] = Mask[i];
6556 else if (BlendMask[Mask[i] % Size] != Mask[i])
6557 return SDValue(); // Can't blend in the needed input!
6559 PermuteMask[i] = Mask[i] % Size;
6562 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6563 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6566 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6567 /// blends and permutes.
6569 /// This matches the extremely common pattern for handling combined
6570 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6571 /// operations. It will try to pick the best arrangement of shuffles and
6573 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6577 SelectionDAG &DAG) {
6578 // Shuffle the input elements into the desired positions in V1 and V2 and
6579 // blend them together.
6580 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6581 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6582 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6583 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6584 if (Mask[i] >= 0 && Mask[i] < Size) {
6585 V1Mask[i] = Mask[i];
6587 } else if (Mask[i] >= Size) {
6588 V2Mask[i] = Mask[i] - Size;
6589 BlendMask[i] = i + Size;
6592 // Try to lower with the simpler initial blend strategy unless one of the
6593 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6594 // shuffle may be able to fold with a load or other benefit. However, when
6595 // we'll have to do 2x as many shuffles in order to achieve this, blending
6596 // first is a better strategy.
6597 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6598 if (SDValue BlendPerm =
6599 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6602 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6603 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6604 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6607 /// \brief Try to lower a vector shuffle as a byte rotation.
6609 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6610 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6611 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6612 /// try to generically lower a vector shuffle through such an pattern. It
6613 /// does not check for the profitability of lowering either as PALIGNR or
6614 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6615 /// This matches shuffle vectors that look like:
6617 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6619 /// Essentially it concatenates V1 and V2, shifts right by some number of
6620 /// elements, and takes the low elements as the result. Note that while this is
6621 /// specified as a *right shift* because x86 is little-endian, it is a *left
6622 /// rotate* of the vector lanes.
6623 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6626 const X86Subtarget *Subtarget,
6627 SelectionDAG &DAG) {
6628 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6630 int NumElts = Mask.size();
6631 int NumLanes = VT.getSizeInBits() / 128;
6632 int NumLaneElts = NumElts / NumLanes;
6634 // We need to detect various ways of spelling a rotation:
6635 // [11, 12, 13, 14, 15, 0, 1, 2]
6636 // [-1, 12, 13, 14, -1, -1, 1, -1]
6637 // [-1, -1, -1, -1, -1, -1, 1, 2]
6638 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6639 // [-1, 4, 5, 6, -1, -1, 9, -1]
6640 // [-1, 4, 5, 6, -1, -1, -1, -1]
6643 for (int l = 0; l < NumElts; l += NumLaneElts) {
6644 for (int i = 0; i < NumLaneElts; ++i) {
6645 if (Mask[l + i] == -1)
6647 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6649 // Get the mod-Size index and lane correct it.
6650 int LaneIdx = (Mask[l + i] % NumElts) - l;
6651 // Make sure it was in this lane.
6652 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6655 // Determine where a rotated vector would have started.
6656 int StartIdx = i - LaneIdx;
6658 // The identity rotation isn't interesting, stop.
6661 // If we found the tail of a vector the rotation must be the missing
6662 // front. If we found the head of a vector, it must be how much of the
6664 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6667 Rotation = CandidateRotation;
6668 else if (Rotation != CandidateRotation)
6669 // The rotations don't match, so we can't match this mask.
6672 // Compute which value this mask is pointing at.
6673 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6675 // Compute which of the two target values this index should be assigned
6676 // to. This reflects whether the high elements are remaining or the low
6677 // elements are remaining.
6678 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6680 // Either set up this value if we've not encountered it before, or check
6681 // that it remains consistent.
6684 else if (TargetV != MaskV)
6685 // This may be a rotation, but it pulls from the inputs in some
6686 // unsupported interleaving.
6691 // Check that we successfully analyzed the mask, and normalize the results.
6692 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6693 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6699 // The actual rotate instruction rotates bytes, so we need to scale the
6700 // rotation based on how many bytes are in the vector lane.
6701 int Scale = 16 / NumLaneElts;
6703 // SSSE3 targets can use the palignr instruction.
6704 if (Subtarget->hasSSSE3()) {
6705 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6706 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6707 Lo = DAG.getBitcast(AlignVT, Lo);
6708 Hi = DAG.getBitcast(AlignVT, Hi);
6710 return DAG.getBitcast(
6711 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6712 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6715 assert(VT.getSizeInBits() == 128 &&
6716 "Rotate-based lowering only supports 128-bit lowering!");
6717 assert(Mask.size() <= 16 &&
6718 "Can shuffle at most 16 bytes in a 128-bit vector!");
6720 // Default SSE2 implementation
6721 int LoByteShift = 16 - Rotation * Scale;
6722 int HiByteShift = Rotation * Scale;
6724 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6725 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6726 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6728 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6729 DAG.getConstant(LoByteShift, DL, MVT::i8));
6730 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6731 DAG.getConstant(HiByteShift, DL, MVT::i8));
6732 return DAG.getBitcast(VT,
6733 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6736 /// \brief Compute whether each element of a shuffle is zeroable.
6738 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6739 /// Either it is an undef element in the shuffle mask, the element of the input
6740 /// referenced is undef, or the element of the input referenced is known to be
6741 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6742 /// as many lanes with this technique as possible to simplify the remaining
6744 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6745 SDValue V1, SDValue V2) {
6746 SmallBitVector Zeroable(Mask.size(), false);
6748 while (V1.getOpcode() == ISD::BITCAST)
6749 V1 = V1->getOperand(0);
6750 while (V2.getOpcode() == ISD::BITCAST)
6751 V2 = V2->getOperand(0);
6753 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6754 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6756 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6758 // Handle the easy cases.
6759 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6764 // If this is an index into a build_vector node (which has the same number
6765 // of elements), dig out the input value and use it.
6766 SDValue V = M < Size ? V1 : V2;
6767 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6770 SDValue Input = V.getOperand(M % Size);
6771 // The UNDEF opcode check really should be dead code here, but not quite
6772 // worth asserting on (it isn't invalid, just unexpected).
6773 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6780 /// \brief Try to emit a bitmask instruction for a shuffle.
6782 /// This handles cases where we can model a blend exactly as a bitmask due to
6783 /// one of the inputs being zeroable.
6784 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6785 SDValue V2, ArrayRef<int> Mask,
6786 SelectionDAG &DAG) {
6787 MVT EltVT = VT.getScalarType();
6788 int NumEltBits = EltVT.getSizeInBits();
6789 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6790 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6791 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6793 if (EltVT.isFloatingPoint()) {
6794 Zero = DAG.getBitcast(EltVT, Zero);
6795 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6797 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6798 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6800 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6803 if (Mask[i] % Size != i)
6804 return SDValue(); // Not a blend.
6806 V = Mask[i] < Size ? V1 : V2;
6807 else if (V != (Mask[i] < Size ? V1 : V2))
6808 return SDValue(); // Can only let one input through the mask.
6810 VMaskOps[i] = AllOnes;
6813 return SDValue(); // No non-zeroable elements!
6815 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6816 V = DAG.getNode(VT.isFloatingPoint()
6817 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6822 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6824 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6825 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6826 /// matches elements from one of the input vectors shuffled to the left or
6827 /// right with zeroable elements 'shifted in'. It handles both the strictly
6828 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6831 /// PSHL : (little-endian) left bit shift.
6832 /// [ zz, 0, zz, 2 ]
6833 /// [ -1, 4, zz, -1 ]
6834 /// PSRL : (little-endian) right bit shift.
6836 /// [ -1, -1, 7, zz]
6837 /// PSLLDQ : (little-endian) left byte shift
6838 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6839 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6840 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6841 /// PSRLDQ : (little-endian) right byte shift
6842 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6843 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6844 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6845 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6846 SDValue V2, ArrayRef<int> Mask,
6847 SelectionDAG &DAG) {
6848 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6850 int Size = Mask.size();
6851 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6853 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6854 for (int i = 0; i < Size; i += Scale)
6855 for (int j = 0; j < Shift; ++j)
6856 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6862 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6863 for (int i = 0; i != Size; i += Scale) {
6864 unsigned Pos = Left ? i + Shift : i;
6865 unsigned Low = Left ? i : i + Shift;
6866 unsigned Len = Scale - Shift;
6867 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6868 Low + (V == V1 ? 0 : Size)))
6872 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6873 bool ByteShift = ShiftEltBits > 64;
6874 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6875 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6876 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6878 // Normalize the scale for byte shifts to still produce an i64 element
6880 Scale = ByteShift ? Scale / 2 : Scale;
6882 // We need to round trip through the appropriate type for the shift.
6883 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6884 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6885 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6886 "Illegal integer vector type");
6887 V = DAG.getBitcast(ShiftVT, V);
6889 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6890 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6891 return DAG.getBitcast(VT, V);
6894 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6895 // keep doubling the size of the integer elements up to that. We can
6896 // then shift the elements of the integer vector by whole multiples of
6897 // their width within the elements of the larger integer vector. Test each
6898 // multiple to see if we can find a match with the moved element indices
6899 // and that the shifted in elements are all zeroable.
6900 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6901 for (int Shift = 1; Shift != Scale; ++Shift)
6902 for (bool Left : {true, false})
6903 if (CheckZeros(Shift, Scale, Left))
6904 for (SDValue V : {V1, V2})
6905 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6912 /// \brief Lower a vector shuffle as a zero or any extension.
6914 /// Given a specific number of elements, element bit width, and extension
6915 /// stride, produce either a zero or any extension based on the available
6916 /// features of the subtarget.
6917 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6918 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6919 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6920 assert(Scale > 1 && "Need a scale to extend.");
6921 int NumElements = VT.getVectorNumElements();
6922 int EltBits = VT.getScalarSizeInBits();
6923 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6924 "Only 8, 16, and 32 bit elements can be extended.");
6925 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6927 // Found a valid zext mask! Try various lowering strategies based on the
6928 // input type and available ISA extensions.
6929 if (Subtarget->hasSSE41()) {
6930 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6931 NumElements / Scale);
6932 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6935 // For any extends we can cheat for larger element sizes and use shuffle
6936 // instructions that can fold with a load and/or copy.
6937 if (AnyExt && EltBits == 32) {
6938 int PSHUFDMask[4] = {0, -1, 1, -1};
6939 return DAG.getBitcast(
6940 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6941 DAG.getBitcast(MVT::v4i32, InputV),
6942 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6944 if (AnyExt && EltBits == 16 && Scale > 2) {
6945 int PSHUFDMask[4] = {0, -1, 0, -1};
6946 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6947 DAG.getBitcast(MVT::v4i32, InputV),
6948 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6949 int PSHUFHWMask[4] = {1, -1, -1, -1};
6950 return DAG.getBitcast(
6951 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6952 DAG.getBitcast(MVT::v8i16, InputV),
6953 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6956 // If this would require more than 2 unpack instructions to expand, use
6957 // pshufb when available. We can only use more than 2 unpack instructions
6958 // when zero extending i8 elements which also makes it easier to use pshufb.
6959 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6960 assert(NumElements == 16 && "Unexpected byte vector width!");
6961 SDValue PSHUFBMask[16];
6962 for (int i = 0; i < 16; ++i)
6964 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6965 InputV = DAG.getBitcast(MVT::v16i8, InputV);
6966 return DAG.getBitcast(VT,
6967 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6968 DAG.getNode(ISD::BUILD_VECTOR, DL,
6969 MVT::v16i8, PSHUFBMask)));
6972 // Otherwise emit a sequence of unpacks.
6974 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6975 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6976 : getZeroVector(InputVT, Subtarget, DAG, DL);
6977 InputV = DAG.getBitcast(InputVT, InputV);
6978 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6982 } while (Scale > 1);
6983 return DAG.getBitcast(VT, InputV);
6986 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6988 /// This routine will try to do everything in its power to cleverly lower
6989 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6990 /// check for the profitability of this lowering, it tries to aggressively
6991 /// match this pattern. It will use all of the micro-architectural details it
6992 /// can to emit an efficient lowering. It handles both blends with all-zero
6993 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6994 /// masking out later).
6996 /// The reason we have dedicated lowering for zext-style shuffles is that they
6997 /// are both incredibly common and often quite performance sensitive.
6998 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6999 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7000 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7001 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7003 int Bits = VT.getSizeInBits();
7004 int NumElements = VT.getVectorNumElements();
7005 assert(VT.getScalarSizeInBits() <= 32 &&
7006 "Exceeds 32-bit integer zero extension limit");
7007 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7009 // Define a helper function to check a particular ext-scale and lower to it if
7011 auto Lower = [&](int Scale) -> SDValue {
7014 for (int i = 0; i < NumElements; ++i) {
7016 continue; // Valid anywhere but doesn't tell us anything.
7017 if (i % Scale != 0) {
7018 // Each of the extended elements need to be zeroable.
7022 // We no longer are in the anyext case.
7027 // Each of the base elements needs to be consecutive indices into the
7028 // same input vector.
7029 SDValue V = Mask[i] < NumElements ? V1 : V2;
7032 else if (InputV != V)
7033 return SDValue(); // Flip-flopping inputs.
7035 if (Mask[i] % NumElements != i / Scale)
7036 return SDValue(); // Non-consecutive strided elements.
7039 // If we fail to find an input, we have a zero-shuffle which should always
7040 // have already been handled.
7041 // FIXME: Maybe handle this here in case during blending we end up with one?
7045 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7046 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
7049 // The widest scale possible for extending is to a 64-bit integer.
7050 assert(Bits % 64 == 0 &&
7051 "The number of bits in a vector must be divisible by 64 on x86!");
7052 int NumExtElements = Bits / 64;
7054 // Each iteration, try extending the elements half as much, but into twice as
7056 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7057 assert(NumElements % NumExtElements == 0 &&
7058 "The input vector size must be divisible by the extended size.");
7059 if (SDValue V = Lower(NumElements / NumExtElements))
7063 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7067 // Returns one of the source operands if the shuffle can be reduced to a
7068 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7069 auto CanZExtLowHalf = [&]() {
7070 for (int i = NumElements / 2; i != NumElements; ++i)
7073 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7075 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7080 if (SDValue V = CanZExtLowHalf()) {
7081 V = DAG.getBitcast(MVT::v2i64, V);
7082 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7083 return DAG.getBitcast(VT, V);
7086 // No viable ext lowering found.
7090 /// \brief Try to get a scalar value for a specific element of a vector.
7092 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7093 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7094 SelectionDAG &DAG) {
7095 MVT VT = V.getSimpleValueType();
7096 MVT EltVT = VT.getVectorElementType();
7097 while (V.getOpcode() == ISD::BITCAST)
7098 V = V.getOperand(0);
7099 // If the bitcasts shift the element size, we can't extract an equivalent
7101 MVT NewVT = V.getSimpleValueType();
7102 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7105 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7106 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7107 // Ensure the scalar operand is the same size as the destination.
7108 // FIXME: Add support for scalar truncation where possible.
7109 SDValue S = V.getOperand(Idx);
7110 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7111 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7117 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7119 /// This is particularly important because the set of instructions varies
7120 /// significantly based on whether the operand is a load or not.
7121 static bool isShuffleFoldableLoad(SDValue V) {
7122 while (V.getOpcode() == ISD::BITCAST)
7123 V = V.getOperand(0);
7125 return ISD::isNON_EXTLoad(V.getNode());
7128 /// \brief Try to lower insertion of a single element into a zero vector.
7130 /// This is a common pattern that we have especially efficient patterns to lower
7131 /// across all subtarget feature sets.
7132 static SDValue lowerVectorShuffleAsElementInsertion(
7133 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7134 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7135 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7137 MVT EltVT = VT.getVectorElementType();
7139 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7140 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7142 bool IsV1Zeroable = true;
7143 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7144 if (i != V2Index && !Zeroable[i]) {
7145 IsV1Zeroable = false;
7149 // Check for a single input from a SCALAR_TO_VECTOR node.
7150 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7151 // all the smarts here sunk into that routine. However, the current
7152 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7153 // vector shuffle lowering is dead.
7154 if (SDValue V2S = getScalarValueForVectorElement(
7155 V2, Mask[V2Index] - Mask.size(), DAG)) {
7156 // We need to zext the scalar if it is smaller than an i32.
7157 V2S = DAG.getBitcast(EltVT, V2S);
7158 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7159 // Using zext to expand a narrow element won't work for non-zero
7164 // Zero-extend directly to i32.
7166 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7168 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7169 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7170 EltVT == MVT::i16) {
7171 // Either not inserting from the low element of the input or the input
7172 // element size is too small to use VZEXT_MOVL to clear the high bits.
7176 if (!IsV1Zeroable) {
7177 // If V1 can't be treated as a zero vector we have fewer options to lower
7178 // this. We can't support integer vectors or non-zero targets cheaply, and
7179 // the V1 elements can't be permuted in any way.
7180 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7181 if (!VT.isFloatingPoint() || V2Index != 0)
7183 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7184 V1Mask[V2Index] = -1;
7185 if (!isNoopShuffleMask(V1Mask))
7187 // This is essentially a special case blend operation, but if we have
7188 // general purpose blend operations, they are always faster. Bail and let
7189 // the rest of the lowering handle these as blends.
7190 if (Subtarget->hasSSE41())
7193 // Otherwise, use MOVSD or MOVSS.
7194 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7195 "Only two types of floating point element types to handle!");
7196 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7200 // This lowering only works for the low element with floating point vectors.
7201 if (VT.isFloatingPoint() && V2Index != 0)
7204 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7206 V2 = DAG.getBitcast(VT, V2);
7209 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7210 // the desired position. Otherwise it is more efficient to do a vector
7211 // shift left. We know that we can do a vector shift left because all
7212 // the inputs are zero.
7213 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7214 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7215 V2Shuffle[V2Index] = 0;
7216 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7218 V2 = DAG.getBitcast(MVT::v2i64, V2);
7220 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7222 V2Index * EltVT.getSizeInBits()/8, DL,
7223 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7224 V2 = DAG.getBitcast(VT, V2);
7230 /// \brief Try to lower broadcast of a single element.
7232 /// For convenience, this code also bundles all of the subtarget feature set
7233 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7234 /// a convenient way to factor it out.
7235 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7237 const X86Subtarget *Subtarget,
7238 SelectionDAG &DAG) {
7239 if (!Subtarget->hasAVX())
7241 if (VT.isInteger() && !Subtarget->hasAVX2())
7244 // Check that the mask is a broadcast.
7245 int BroadcastIdx = -1;
7247 if (M >= 0 && BroadcastIdx == -1)
7249 else if (M >= 0 && M != BroadcastIdx)
7252 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7253 "a sorted mask where the broadcast "
7256 // Go up the chain of (vector) values to find a scalar load that we can
7257 // combine with the broadcast.
7259 switch (V.getOpcode()) {
7260 case ISD::CONCAT_VECTORS: {
7261 int OperandSize = Mask.size() / V.getNumOperands();
7262 V = V.getOperand(BroadcastIdx / OperandSize);
7263 BroadcastIdx %= OperandSize;
7267 case ISD::INSERT_SUBVECTOR: {
7268 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7269 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7273 int BeginIdx = (int)ConstantIdx->getZExtValue();
7275 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7276 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7277 BroadcastIdx -= BeginIdx;
7288 // Check if this is a broadcast of a scalar. We special case lowering
7289 // for scalars so that we can more effectively fold with loads.
7290 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7291 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7292 V = V.getOperand(BroadcastIdx);
7294 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7295 // Only AVX2 has register broadcasts.
7296 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7298 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7299 // We can't broadcast from a vector register without AVX2, and we can only
7300 // broadcast from the zero-element of a vector register.
7304 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7307 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7308 // INSERTPS when the V1 elements are already in the correct locations
7309 // because otherwise we can just always use two SHUFPS instructions which
7310 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7311 // perform INSERTPS if a single V1 element is out of place and all V2
7312 // elements are zeroable.
7313 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7315 SelectionDAG &DAG) {
7316 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7317 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7318 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7319 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7321 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7324 int V1DstIndex = -1;
7325 int V2DstIndex = -1;
7326 bool V1UsedInPlace = false;
7328 for (int i = 0; i < 4; ++i) {
7329 // Synthesize a zero mask from the zeroable elements (includes undefs).
7335 // Flag if we use any V1 inputs in place.
7337 V1UsedInPlace = true;
7341 // We can only insert a single non-zeroable element.
7342 if (V1DstIndex != -1 || V2DstIndex != -1)
7346 // V1 input out of place for insertion.
7349 // V2 input for insertion.
7354 // Don't bother if we have no (non-zeroable) element for insertion.
7355 if (V1DstIndex == -1 && V2DstIndex == -1)
7358 // Determine element insertion src/dst indices. The src index is from the
7359 // start of the inserted vector, not the start of the concatenated vector.
7360 unsigned V2SrcIndex = 0;
7361 if (V1DstIndex != -1) {
7362 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7363 // and don't use the original V2 at all.
7364 V2SrcIndex = Mask[V1DstIndex];
7365 V2DstIndex = V1DstIndex;
7368 V2SrcIndex = Mask[V2DstIndex] - 4;
7371 // If no V1 inputs are used in place, then the result is created only from
7372 // the zero mask and the V2 insertion - so remove V1 dependency.
7374 V1 = DAG.getUNDEF(MVT::v4f32);
7376 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7377 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7379 // Insert the V2 element into the desired position.
7381 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7382 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7385 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7386 /// UNPCK instruction.
7388 /// This specifically targets cases where we end up with alternating between
7389 /// the two inputs, and so can permute them into something that feeds a single
7390 /// UNPCK instruction. Note that this routine only targets integer vectors
7391 /// because for floating point vectors we have a generalized SHUFPS lowering
7392 /// strategy that handles everything that doesn't *exactly* match an unpack,
7393 /// making this clever lowering unnecessary.
7394 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7395 SDValue V2, ArrayRef<int> Mask,
7396 SelectionDAG &DAG) {
7397 assert(!VT.isFloatingPoint() &&
7398 "This routine only supports integer vectors.");
7399 assert(!isSingleInputShuffleMask(Mask) &&
7400 "This routine should only be used when blending two inputs.");
7401 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7403 int Size = Mask.size();
7405 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7406 return M >= 0 && M % Size < Size / 2;
7408 int NumHiInputs = std::count_if(
7409 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7411 bool UnpackLo = NumLoInputs >= NumHiInputs;
7413 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7414 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7415 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7417 for (int i = 0; i < Size; ++i) {
7421 // Each element of the unpack contains Scale elements from this mask.
7422 int UnpackIdx = i / Scale;
7424 // We only handle the case where V1 feeds the first slots of the unpack.
7425 // We rely on canonicalization to ensure this is the case.
7426 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7429 // Setup the mask for this input. The indexing is tricky as we have to
7430 // handle the unpack stride.
7431 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7432 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7436 // If we will have to shuffle both inputs to use the unpack, check whether
7437 // we can just unpack first and shuffle the result. If so, skip this unpack.
7438 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7439 !isNoopShuffleMask(V2Mask))
7442 // Shuffle the inputs into place.
7443 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7444 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 // Cast the inputs to the type we will use to unpack them.
7447 V1 = DAG.getBitcast(UnpackVT, V1);
7448 V2 = DAG.getBitcast(UnpackVT, V2);
7450 // Unpack the inputs and cast the result back to the desired type.
7451 return DAG.getBitcast(
7452 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7456 // We try each unpack from the largest to the smallest to try and find one
7457 // that fits this mask.
7458 int OrigNumElements = VT.getVectorNumElements();
7459 int OrigScalarSize = VT.getScalarSizeInBits();
7460 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7461 int Scale = ScalarSize / OrigScalarSize;
7462 int NumElements = OrigNumElements / Scale;
7463 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7464 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7468 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7470 if (NumLoInputs == 0 || NumHiInputs == 0) {
7471 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7472 "We have to have *some* inputs!");
7473 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7475 // FIXME: We could consider the total complexity of the permute of each
7476 // possible unpacking. Or at the least we should consider how many
7477 // half-crossings are created.
7478 // FIXME: We could consider commuting the unpacks.
7480 SmallVector<int, 32> PermMask;
7481 PermMask.assign(Size, -1);
7482 for (int i = 0; i < Size; ++i) {
7486 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7489 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7491 return DAG.getVectorShuffle(
7492 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7494 DAG.getUNDEF(VT), PermMask);
7500 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7502 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7503 /// support for floating point shuffles but not integer shuffles. These
7504 /// instructions will incur a domain crossing penalty on some chips though so
7505 /// it is better to avoid lowering through this for integer vectors where
7507 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7508 const X86Subtarget *Subtarget,
7509 SelectionDAG &DAG) {
7511 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7512 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7513 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7515 ArrayRef<int> Mask = SVOp->getMask();
7516 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7518 if (isSingleInputShuffleMask(Mask)) {
7519 // Use low duplicate instructions for masks that match their pattern.
7520 if (Subtarget->hasSSE3())
7521 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7522 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7524 // Straight shuffle of a single input vector. Simulate this by using the
7525 // single input as both of the "inputs" to this instruction..
7526 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7528 if (Subtarget->hasAVX()) {
7529 // If we have AVX, we can use VPERMILPS which will allow folding a load
7530 // into the shuffle.
7531 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7532 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7535 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7536 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7538 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7539 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7541 // If we have a single input, insert that into V1 if we can do so cheaply.
7542 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7543 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7544 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7546 // Try inverting the insertion since for v2 masks it is easy to do and we
7547 // can't reliably sort the mask one way or the other.
7548 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7549 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7550 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7551 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7555 // Try to use one of the special instruction patterns to handle two common
7556 // blend patterns if a zero-blend above didn't work.
7557 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7558 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7559 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7560 // We can either use a special instruction to load over the low double or
7561 // to move just the low double.
7563 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7565 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7567 if (Subtarget->hasSSE41())
7568 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7572 // Use dedicated unpack instructions for masks that match their pattern.
7573 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7574 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7575 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7576 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7578 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7579 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7580 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7583 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7585 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7586 /// the integer unit to minimize domain crossing penalties. However, for blends
7587 /// it falls back to the floating point shuffle operation with appropriate bit
7589 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7590 const X86Subtarget *Subtarget,
7591 SelectionDAG &DAG) {
7593 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7594 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7595 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7596 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7597 ArrayRef<int> Mask = SVOp->getMask();
7598 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7600 if (isSingleInputShuffleMask(Mask)) {
7601 // Check for being able to broadcast a single element.
7602 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7603 Mask, Subtarget, DAG))
7606 // Straight shuffle of a single input vector. For everything from SSE2
7607 // onward this has a single fast instruction with no scary immediates.
7608 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7609 V1 = DAG.getBitcast(MVT::v4i32, V1);
7610 int WidenedMask[4] = {
7611 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7612 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7613 return DAG.getBitcast(
7615 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7616 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7618 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7619 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7620 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7621 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7623 // If we have a blend of two PACKUS operations an the blend aligns with the
7624 // low and half halves, we can just merge the PACKUS operations. This is
7625 // particularly important as it lets us merge shuffles that this routine itself
7627 auto GetPackNode = [](SDValue V) {
7628 while (V.getOpcode() == ISD::BITCAST)
7629 V = V.getOperand(0);
7631 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7633 if (SDValue V1Pack = GetPackNode(V1))
7634 if (SDValue V2Pack = GetPackNode(V2))
7635 return DAG.getBitcast(MVT::v2i64,
7636 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7637 Mask[0] == 0 ? V1Pack.getOperand(0)
7638 : V1Pack.getOperand(1),
7639 Mask[1] == 2 ? V2Pack.getOperand(0)
7640 : V2Pack.getOperand(1)));
7642 // Try to use shift instructions.
7644 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7647 // When loading a scalar and then shuffling it into a vector we can often do
7648 // the insertion cheaply.
7649 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7650 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7652 // Try inverting the insertion since for v2 masks it is easy to do and we
7653 // can't reliably sort the mask one way or the other.
7654 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7655 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7656 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7659 // We have different paths for blend lowering, but they all must use the
7660 // *exact* same predicate.
7661 bool IsBlendSupported = Subtarget->hasSSE41();
7662 if (IsBlendSupported)
7663 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7667 // Use dedicated unpack instructions for masks that match their pattern.
7668 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7669 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7670 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7671 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7673 // Try to use byte rotation instructions.
7674 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7675 if (Subtarget->hasSSSE3())
7676 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7677 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7680 // If we have direct support for blends, we should lower by decomposing into
7681 // a permute. That will be faster than the domain cross.
7682 if (IsBlendSupported)
7683 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7686 // We implement this with SHUFPD which is pretty lame because it will likely
7687 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7688 // However, all the alternatives are still more cycles and newer chips don't
7689 // have this problem. It would be really nice if x86 had better shuffles here.
7690 V1 = DAG.getBitcast(MVT::v2f64, V1);
7691 V2 = DAG.getBitcast(MVT::v2f64, V2);
7692 return DAG.getBitcast(MVT::v2i64,
7693 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7696 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7698 /// This is used to disable more specialized lowerings when the shufps lowering
7699 /// will happen to be efficient.
7700 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7701 // This routine only handles 128-bit shufps.
7702 assert(Mask.size() == 4 && "Unsupported mask size!");
7704 // To lower with a single SHUFPS we need to have the low half and high half
7705 // each requiring a single input.
7706 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7708 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7714 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7716 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7717 /// It makes no assumptions about whether this is the *best* lowering, it simply
7719 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7720 ArrayRef<int> Mask, SDValue V1,
7721 SDValue V2, SelectionDAG &DAG) {
7722 SDValue LowV = V1, HighV = V2;
7723 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7726 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7728 if (NumV2Elements == 1) {
7730 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7733 // Compute the index adjacent to V2Index and in the same half by toggling
7735 int V2AdjIndex = V2Index ^ 1;
7737 if (Mask[V2AdjIndex] == -1) {
7738 // Handles all the cases where we have a single V2 element and an undef.
7739 // This will only ever happen in the high lanes because we commute the
7740 // vector otherwise.
7742 std::swap(LowV, HighV);
7743 NewMask[V2Index] -= 4;
7745 // Handle the case where the V2 element ends up adjacent to a V1 element.
7746 // To make this work, blend them together as the first step.
7747 int V1Index = V2AdjIndex;
7748 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7749 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7750 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7752 // Now proceed to reconstruct the final blend as we have the necessary
7753 // high or low half formed.
7760 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7761 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7763 } else if (NumV2Elements == 2) {
7764 if (Mask[0] < 4 && Mask[1] < 4) {
7765 // Handle the easy case where we have V1 in the low lanes and V2 in the
7769 } else if (Mask[2] < 4 && Mask[3] < 4) {
7770 // We also handle the reversed case because this utility may get called
7771 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7772 // arrange things in the right direction.
7778 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7779 // trying to place elements directly, just blend them and set up the final
7780 // shuffle to place them.
7782 // The first two blend mask elements are for V1, the second two are for
7784 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7785 Mask[2] < 4 ? Mask[2] : Mask[3],
7786 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7787 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7788 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7789 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7791 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7794 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7795 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7796 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7797 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7800 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7801 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7804 /// \brief Lower 4-lane 32-bit floating point shuffles.
7806 /// Uses instructions exclusively from the floating point unit to minimize
7807 /// domain crossing penalties, as these are sufficient to implement all v4f32
7809 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7810 const X86Subtarget *Subtarget,
7811 SelectionDAG &DAG) {
7813 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7814 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7815 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7816 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7817 ArrayRef<int> Mask = SVOp->getMask();
7818 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7821 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7823 if (NumV2Elements == 0) {
7824 // Check for being able to broadcast a single element.
7825 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7826 Mask, Subtarget, DAG))
7829 // Use even/odd duplicate instructions for masks that match their pattern.
7830 if (Subtarget->hasSSE3()) {
7831 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7832 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7833 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7834 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7837 if (Subtarget->hasAVX()) {
7838 // If we have AVX, we can use VPERMILPS which will allow folding a load
7839 // into the shuffle.
7840 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7841 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7844 // Otherwise, use a straight shuffle of a single input vector. We pass the
7845 // input vector to both operands to simulate this with a SHUFPS.
7846 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7847 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7850 // There are special ways we can lower some single-element blends. However, we
7851 // have custom ways we can lower more complex single-element blends below that
7852 // we defer to if both this and BLENDPS fail to match, so restrict this to
7853 // when the V2 input is targeting element 0 of the mask -- that is the fast
7855 if (NumV2Elements == 1 && Mask[0] >= 4)
7856 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7857 Mask, Subtarget, DAG))
7860 if (Subtarget->hasSSE41()) {
7861 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7865 // Use INSERTPS if we can complete the shuffle efficiently.
7866 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7869 if (!isSingleSHUFPSMask(Mask))
7870 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7871 DL, MVT::v4f32, V1, V2, Mask, DAG))
7875 // Use dedicated unpack instructions for masks that match their pattern.
7876 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7877 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7878 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7879 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7880 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7881 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7882 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7883 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7885 // Otherwise fall back to a SHUFPS lowering strategy.
7886 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7889 /// \brief Lower 4-lane i32 vector shuffles.
7891 /// We try to handle these with integer-domain shuffles where we can, but for
7892 /// blends we use the floating point domain blend instructions.
7893 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7894 const X86Subtarget *Subtarget,
7895 SelectionDAG &DAG) {
7897 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7898 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7899 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7901 ArrayRef<int> Mask = SVOp->getMask();
7902 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7904 // Whenever we can lower this as a zext, that instruction is strictly faster
7905 // than any alternative. It also allows us to fold memory operands into the
7906 // shuffle in many cases.
7907 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7908 Mask, Subtarget, DAG))
7912 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7914 if (NumV2Elements == 0) {
7915 // Check for being able to broadcast a single element.
7916 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7917 Mask, Subtarget, DAG))
7920 // Straight shuffle of a single input vector. For everything from SSE2
7921 // onward this has a single fast instruction with no scary immediates.
7922 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7923 // but we aren't actually going to use the UNPCK instruction because doing
7924 // so prevents folding a load into this instruction or making a copy.
7925 const int UnpackLoMask[] = {0, 0, 1, 1};
7926 const int UnpackHiMask[] = {2, 2, 3, 3};
7927 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7928 Mask = UnpackLoMask;
7929 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7930 Mask = UnpackHiMask;
7932 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7933 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7936 // Try to use shift instructions.
7938 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7941 // There are special ways we can lower some single-element blends.
7942 if (NumV2Elements == 1)
7943 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7944 Mask, Subtarget, DAG))
7947 // We have different paths for blend lowering, but they all must use the
7948 // *exact* same predicate.
7949 bool IsBlendSupported = Subtarget->hasSSE41();
7950 if (IsBlendSupported)
7951 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7955 if (SDValue Masked =
7956 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7959 // Use dedicated unpack instructions for masks that match their pattern.
7960 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7961 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7962 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7963 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7964 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7965 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7966 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7967 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7969 // Try to use byte rotation instructions.
7970 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7971 if (Subtarget->hasSSSE3())
7972 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7973 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7976 // If we have direct support for blends, we should lower by decomposing into
7977 // a permute. That will be faster than the domain cross.
7978 if (IsBlendSupported)
7979 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7982 // Try to lower by permuting the inputs into an unpack instruction.
7983 if (SDValue Unpack =
7984 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7987 // We implement this with SHUFPS because it can blend from two vectors.
7988 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7989 // up the inputs, bypassing domain shift penalties that we would encur if we
7990 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7992 return DAG.getBitcast(
7994 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
7995 DAG.getBitcast(MVT::v4f32, V2), Mask));
7998 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7999 /// shuffle lowering, and the most complex part.
8001 /// The lowering strategy is to try to form pairs of input lanes which are
8002 /// targeted at the same half of the final vector, and then use a dword shuffle
8003 /// to place them onto the right half, and finally unpack the paired lanes into
8004 /// their final position.
8006 /// The exact breakdown of how to form these dword pairs and align them on the
8007 /// correct sides is really tricky. See the comments within the function for
8008 /// more of the details.
8010 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8011 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8012 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8013 /// vector, form the analogous 128-bit 8-element Mask.
8014 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8015 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8016 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8017 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8018 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8020 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8021 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8022 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8024 SmallVector<int, 4> LoInputs;
8025 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8026 [](int M) { return M >= 0; });
8027 std::sort(LoInputs.begin(), LoInputs.end());
8028 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8029 SmallVector<int, 4> HiInputs;
8030 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8031 [](int M) { return M >= 0; });
8032 std::sort(HiInputs.begin(), HiInputs.end());
8033 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8035 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8036 int NumHToL = LoInputs.size() - NumLToL;
8038 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8039 int NumHToH = HiInputs.size() - NumLToH;
8040 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8041 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8042 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8043 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8045 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8046 // such inputs we can swap two of the dwords across the half mark and end up
8047 // with <=2 inputs to each half in each half. Once there, we can fall through
8048 // to the generic code below. For example:
8050 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8051 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8053 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8054 // and an existing 2-into-2 on the other half. In this case we may have to
8055 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8056 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8057 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8058 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8059 // half than the one we target for fixing) will be fixed when we re-enter this
8060 // path. We will also combine away any sequence of PSHUFD instructions that
8061 // result into a single instruction. Here is an example of the tricky case:
8063 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8064 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8066 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8068 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8069 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8071 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8072 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8074 // The result is fine to be handled by the generic logic.
8075 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8076 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8077 int AOffset, int BOffset) {
8078 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8079 "Must call this with A having 3 or 1 inputs from the A half.");
8080 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8081 "Must call this with B having 1 or 3 inputs from the B half.");
8082 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8083 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8085 // Compute the index of dword with only one word among the three inputs in
8086 // a half by taking the sum of the half with three inputs and subtracting
8087 // the sum of the actual three inputs. The difference is the remaining
8090 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8091 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8092 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8093 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8094 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8095 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8096 int TripleNonInputIdx =
8097 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8098 TripleDWord = TripleNonInputIdx / 2;
8100 // We use xor with one to compute the adjacent DWord to whichever one the
8102 OneInputDWord = (OneInput / 2) ^ 1;
8104 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8105 // and BToA inputs. If there is also such a problem with the BToB and AToB
8106 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8107 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8108 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8109 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8110 // Compute how many inputs will be flipped by swapping these DWords. We
8112 // to balance this to ensure we don't form a 3-1 shuffle in the other
8114 int NumFlippedAToBInputs =
8115 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8116 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8117 int NumFlippedBToBInputs =
8118 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8119 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8120 if ((NumFlippedAToBInputs == 1 &&
8121 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8122 (NumFlippedBToBInputs == 1 &&
8123 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8124 // We choose whether to fix the A half or B half based on whether that
8125 // half has zero flipped inputs. At zero, we may not be able to fix it
8126 // with that half. We also bias towards fixing the B half because that
8127 // will more commonly be the high half, and we have to bias one way.
8128 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8129 ArrayRef<int> Inputs) {
8130 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8131 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8132 PinnedIdx ^ 1) != Inputs.end();
8133 // Determine whether the free index is in the flipped dword or the
8134 // unflipped dword based on where the pinned index is. We use this bit
8135 // in an xor to conditionally select the adjacent dword.
8136 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8137 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8138 FixFreeIdx) != Inputs.end();
8139 if (IsFixIdxInput == IsFixFreeIdxInput)
8141 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8142 FixFreeIdx) != Inputs.end();
8143 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8144 "We need to be changing the number of flipped inputs!");
8145 int PSHUFHalfMask[] = {0, 1, 2, 3};
8146 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8147 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8149 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8152 if (M != -1 && M == FixIdx)
8154 else if (M != -1 && M == FixFreeIdx)
8157 if (NumFlippedBToBInputs != 0) {
8159 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8160 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8162 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8164 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8165 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8170 int PSHUFDMask[] = {0, 1, 2, 3};
8171 PSHUFDMask[ADWord] = BDWord;
8172 PSHUFDMask[BDWord] = ADWord;
8175 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8176 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8178 // Adjust the mask to match the new locations of A and B.
8180 if (M != -1 && M/2 == ADWord)
8181 M = 2 * BDWord + M % 2;
8182 else if (M != -1 && M/2 == BDWord)
8183 M = 2 * ADWord + M % 2;
8185 // Recurse back into this routine to re-compute state now that this isn't
8186 // a 3 and 1 problem.
8187 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8190 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8191 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8192 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8193 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8195 // At this point there are at most two inputs to the low and high halves from
8196 // each half. That means the inputs can always be grouped into dwords and
8197 // those dwords can then be moved to the correct half with a dword shuffle.
8198 // We use at most one low and one high word shuffle to collect these paired
8199 // inputs into dwords, and finally a dword shuffle to place them.
8200 int PSHUFLMask[4] = {-1, -1, -1, -1};
8201 int PSHUFHMask[4] = {-1, -1, -1, -1};
8202 int PSHUFDMask[4] = {-1, -1, -1, -1};
8204 // First fix the masks for all the inputs that are staying in their
8205 // original halves. This will then dictate the targets of the cross-half
8207 auto fixInPlaceInputs =
8208 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8209 MutableArrayRef<int> SourceHalfMask,
8210 MutableArrayRef<int> HalfMask, int HalfOffset) {
8211 if (InPlaceInputs.empty())
8213 if (InPlaceInputs.size() == 1) {
8214 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8215 InPlaceInputs[0] - HalfOffset;
8216 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8219 if (IncomingInputs.empty()) {
8220 // Just fix all of the in place inputs.
8221 for (int Input : InPlaceInputs) {
8222 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8223 PSHUFDMask[Input / 2] = Input / 2;
8228 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8229 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8230 InPlaceInputs[0] - HalfOffset;
8231 // Put the second input next to the first so that they are packed into
8232 // a dword. We find the adjacent index by toggling the low bit.
8233 int AdjIndex = InPlaceInputs[0] ^ 1;
8234 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8235 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8236 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8238 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8239 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8241 // Now gather the cross-half inputs and place them into a free dword of
8242 // their target half.
8243 // FIXME: This operation could almost certainly be simplified dramatically to
8244 // look more like the 3-1 fixing operation.
8245 auto moveInputsToRightHalf = [&PSHUFDMask](
8246 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8247 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8248 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8250 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8251 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8253 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8255 int LowWord = Word & ~1;
8256 int HighWord = Word | 1;
8257 return isWordClobbered(SourceHalfMask, LowWord) ||
8258 isWordClobbered(SourceHalfMask, HighWord);
8261 if (IncomingInputs.empty())
8264 if (ExistingInputs.empty()) {
8265 // Map any dwords with inputs from them into the right half.
8266 for (int Input : IncomingInputs) {
8267 // If the source half mask maps over the inputs, turn those into
8268 // swaps and use the swapped lane.
8269 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8270 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8271 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8272 Input - SourceOffset;
8273 // We have to swap the uses in our half mask in one sweep.
8274 for (int &M : HalfMask)
8275 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8277 else if (M == Input)
8278 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8280 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8281 Input - SourceOffset &&
8282 "Previous placement doesn't match!");
8284 // Note that this correctly re-maps both when we do a swap and when
8285 // we observe the other side of the swap above. We rely on that to
8286 // avoid swapping the members of the input list directly.
8287 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8290 // Map the input's dword into the correct half.
8291 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8292 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8294 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8296 "Previous placement doesn't match!");
8299 // And just directly shift any other-half mask elements to be same-half
8300 // as we will have mirrored the dword containing the element into the
8301 // same position within that half.
8302 for (int &M : HalfMask)
8303 if (M >= SourceOffset && M < SourceOffset + 4) {
8304 M = M - SourceOffset + DestOffset;
8305 assert(M >= 0 && "This should never wrap below zero!");
8310 // Ensure we have the input in a viable dword of its current half. This
8311 // is particularly tricky because the original position may be clobbered
8312 // by inputs being moved and *staying* in that half.
8313 if (IncomingInputs.size() == 1) {
8314 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8315 int InputFixed = std::find(std::begin(SourceHalfMask),
8316 std::end(SourceHalfMask), -1) -
8317 std::begin(SourceHalfMask) + SourceOffset;
8318 SourceHalfMask[InputFixed - SourceOffset] =
8319 IncomingInputs[0] - SourceOffset;
8320 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8322 IncomingInputs[0] = InputFixed;
8324 } else if (IncomingInputs.size() == 2) {
8325 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8326 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8327 // We have two non-adjacent or clobbered inputs we need to extract from
8328 // the source half. To do this, we need to map them into some adjacent
8329 // dword slot in the source mask.
8330 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8331 IncomingInputs[1] - SourceOffset};
8333 // If there is a free slot in the source half mask adjacent to one of
8334 // the inputs, place the other input in it. We use (Index XOR 1) to
8335 // compute an adjacent index.
8336 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8337 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8338 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8339 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8340 InputsFixed[1] = InputsFixed[0] ^ 1;
8341 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8342 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8343 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8344 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8345 InputsFixed[0] = InputsFixed[1] ^ 1;
8346 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8347 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8348 // The two inputs are in the same DWord but it is clobbered and the
8349 // adjacent DWord isn't used at all. Move both inputs to the free
8351 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8352 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8353 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8354 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8356 // The only way we hit this point is if there is no clobbering
8357 // (because there are no off-half inputs to this half) and there is no
8358 // free slot adjacent to one of the inputs. In this case, we have to
8359 // swap an input with a non-input.
8360 for (int i = 0; i < 4; ++i)
8361 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8362 "We can't handle any clobbers here!");
8363 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8364 "Cannot have adjacent inputs here!");
8366 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8367 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8369 // We also have to update the final source mask in this case because
8370 // it may need to undo the above swap.
8371 for (int &M : FinalSourceHalfMask)
8372 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8373 M = InputsFixed[1] + SourceOffset;
8374 else if (M == InputsFixed[1] + SourceOffset)
8375 M = (InputsFixed[0] ^ 1) + SourceOffset;
8377 InputsFixed[1] = InputsFixed[0] ^ 1;
8380 // Point everything at the fixed inputs.
8381 for (int &M : HalfMask)
8382 if (M == IncomingInputs[0])
8383 M = InputsFixed[0] + SourceOffset;
8384 else if (M == IncomingInputs[1])
8385 M = InputsFixed[1] + SourceOffset;
8387 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8388 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8391 llvm_unreachable("Unhandled input size!");
8394 // Now hoist the DWord down to the right half.
8395 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8396 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8397 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8398 for (int &M : HalfMask)
8399 for (int Input : IncomingInputs)
8401 M = FreeDWord * 2 + Input % 2;
8403 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8404 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8405 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8406 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8408 // Now enact all the shuffles we've computed to move the inputs into their
8410 if (!isNoopShuffleMask(PSHUFLMask))
8411 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8412 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8413 if (!isNoopShuffleMask(PSHUFHMask))
8414 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8415 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8416 if (!isNoopShuffleMask(PSHUFDMask))
8419 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8420 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8422 // At this point, each half should contain all its inputs, and we can then
8423 // just shuffle them into their final position.
8424 assert(std::count_if(LoMask.begin(), LoMask.end(),
8425 [](int M) { return M >= 4; }) == 0 &&
8426 "Failed to lift all the high half inputs to the low mask!");
8427 assert(std::count_if(HiMask.begin(), HiMask.end(),
8428 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8429 "Failed to lift all the low half inputs to the high mask!");
8431 // Do a half shuffle for the low mask.
8432 if (!isNoopShuffleMask(LoMask))
8433 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8434 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8436 // Do a half shuffle with the high mask after shifting its values down.
8437 for (int &M : HiMask)
8440 if (!isNoopShuffleMask(HiMask))
8441 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8442 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8447 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8448 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8449 SDValue V2, ArrayRef<int> Mask,
8450 SelectionDAG &DAG, bool &V1InUse,
8452 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8458 int Size = Mask.size();
8459 int Scale = 16 / Size;
8460 for (int i = 0; i < 16; ++i) {
8461 if (Mask[i / Scale] == -1) {
8462 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8464 const int ZeroMask = 0x80;
8465 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8467 int V2Idx = Mask[i / Scale] < Size
8469 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8470 if (Zeroable[i / Scale])
8471 V1Idx = V2Idx = ZeroMask;
8472 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8473 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8474 V1InUse |= (ZeroMask != V1Idx);
8475 V2InUse |= (ZeroMask != V2Idx);
8480 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8481 DAG.getBitcast(MVT::v16i8, V1),
8482 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8484 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8485 DAG.getBitcast(MVT::v16i8, V2),
8486 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8488 // If we need shuffled inputs from both, blend the two.
8490 if (V1InUse && V2InUse)
8491 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8493 V = V1InUse ? V1 : V2;
8495 // Cast the result back to the correct type.
8496 return DAG.getBitcast(VT, V);
8499 /// \brief Generic lowering of 8-lane i16 shuffles.
8501 /// This handles both single-input shuffles and combined shuffle/blends with
8502 /// two inputs. The single input shuffles are immediately delegated to
8503 /// a dedicated lowering routine.
8505 /// The blends are lowered in one of three fundamental ways. If there are few
8506 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8507 /// of the input is significantly cheaper when lowered as an interleaving of
8508 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8509 /// halves of the inputs separately (making them have relatively few inputs)
8510 /// and then concatenate them.
8511 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8512 const X86Subtarget *Subtarget,
8513 SelectionDAG &DAG) {
8515 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8516 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8517 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8518 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8519 ArrayRef<int> OrigMask = SVOp->getMask();
8520 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8521 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8522 MutableArrayRef<int> Mask(MaskStorage);
8524 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8526 // Whenever we can lower this as a zext, that instruction is strictly faster
8527 // than any alternative.
8528 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8529 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8532 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8534 auto isV2 = [](int M) { return M >= 8; };
8536 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8538 if (NumV2Inputs == 0) {
8539 // Check for being able to broadcast a single element.
8540 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8541 Mask, Subtarget, DAG))
8544 // Try to use shift instructions.
8546 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8549 // Use dedicated unpack instructions for masks that match their pattern.
8550 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8551 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8552 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8553 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8555 // Try to use byte rotation instructions.
8556 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8557 Mask, Subtarget, DAG))
8560 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8564 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8565 "All single-input shuffles should be canonicalized to be V1-input "
8568 // Try to use shift instructions.
8570 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8573 // There are special ways we can lower some single-element blends.
8574 if (NumV2Inputs == 1)
8575 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8576 Mask, Subtarget, DAG))
8579 // We have different paths for blend lowering, but they all must use the
8580 // *exact* same predicate.
8581 bool IsBlendSupported = Subtarget->hasSSE41();
8582 if (IsBlendSupported)
8583 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8587 if (SDValue Masked =
8588 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8591 // Use dedicated unpack instructions for masks that match their pattern.
8592 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8593 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8594 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8595 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8597 // Try to use byte rotation instructions.
8598 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8599 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8602 if (SDValue BitBlend =
8603 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8606 if (SDValue Unpack =
8607 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8610 // If we can't directly blend but can use PSHUFB, that will be better as it
8611 // can both shuffle and set up the inefficient blend.
8612 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8613 bool V1InUse, V2InUse;
8614 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8618 // We can always bit-blend if we have to so the fallback strategy is to
8619 // decompose into single-input permutes and blends.
8620 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8624 /// \brief Check whether a compaction lowering can be done by dropping even
8625 /// elements and compute how many times even elements must be dropped.
8627 /// This handles shuffles which take every Nth element where N is a power of
8628 /// two. Example shuffle masks:
8630 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8631 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8632 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8633 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8634 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8635 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8637 /// Any of these lanes can of course be undef.
8639 /// This routine only supports N <= 3.
8640 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8643 /// \returns N above, or the number of times even elements must be dropped if
8644 /// there is such a number. Otherwise returns zero.
8645 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8646 // Figure out whether we're looping over two inputs or just one.
8647 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8649 // The modulus for the shuffle vector entries is based on whether this is
8650 // a single input or not.
8651 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8652 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8653 "We should only be called with masks with a power-of-2 size!");
8655 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8657 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8658 // and 2^3 simultaneously. This is because we may have ambiguity with
8659 // partially undef inputs.
8660 bool ViableForN[3] = {true, true, true};
8662 for (int i = 0, e = Mask.size(); i < e; ++i) {
8663 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8668 bool IsAnyViable = false;
8669 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8670 if (ViableForN[j]) {
8673 // The shuffle mask must be equal to (i * 2^N) % M.
8674 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8677 ViableForN[j] = false;
8679 // Early exit if we exhaust the possible powers of two.
8684 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8688 // Return 0 as there is no viable power of two.
8692 /// \brief Generic lowering of v16i8 shuffles.
8694 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8695 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8696 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8697 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8699 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8700 const X86Subtarget *Subtarget,
8701 SelectionDAG &DAG) {
8703 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8704 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8705 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8707 ArrayRef<int> Mask = SVOp->getMask();
8708 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8710 // Try to use shift instructions.
8712 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8715 // Try to use byte rotation instructions.
8716 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8717 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8720 // Try to use a zext lowering.
8721 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8722 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8726 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8728 // For single-input shuffles, there are some nicer lowering tricks we can use.
8729 if (NumV2Elements == 0) {
8730 // Check for being able to broadcast a single element.
8731 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8732 Mask, Subtarget, DAG))
8735 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8736 // Notably, this handles splat and partial-splat shuffles more efficiently.
8737 // However, it only makes sense if the pre-duplication shuffle simplifies
8738 // things significantly. Currently, this means we need to be able to
8739 // express the pre-duplication shuffle as an i16 shuffle.
8741 // FIXME: We should check for other patterns which can be widened into an
8742 // i16 shuffle as well.
8743 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8744 for (int i = 0; i < 16; i += 2)
8745 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8750 auto tryToWidenViaDuplication = [&]() -> SDValue {
8751 if (!canWidenViaDuplication(Mask))
8753 SmallVector<int, 4> LoInputs;
8754 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8755 [](int M) { return M >= 0 && M < 8; });
8756 std::sort(LoInputs.begin(), LoInputs.end());
8757 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8759 SmallVector<int, 4> HiInputs;
8760 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8761 [](int M) { return M >= 8; });
8762 std::sort(HiInputs.begin(), HiInputs.end());
8763 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8766 bool TargetLo = LoInputs.size() >= HiInputs.size();
8767 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8768 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8770 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8771 SmallDenseMap<int, int, 8> LaneMap;
8772 for (int I : InPlaceInputs) {
8773 PreDupI16Shuffle[I/2] = I/2;
8776 int j = TargetLo ? 0 : 4, je = j + 4;
8777 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8778 // Check if j is already a shuffle of this input. This happens when
8779 // there are two adjacent bytes after we move the low one.
8780 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8781 // If we haven't yet mapped the input, search for a slot into which
8783 while (j < je && PreDupI16Shuffle[j] != -1)
8787 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8790 // Map this input with the i16 shuffle.
8791 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8794 // Update the lane map based on the mapping we ended up with.
8795 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8797 V1 = DAG.getBitcast(
8799 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8800 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8802 // Unpack the bytes to form the i16s that will be shuffled into place.
8803 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8804 MVT::v16i8, V1, V1);
8806 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8807 for (int i = 0; i < 16; ++i)
8808 if (Mask[i] != -1) {
8809 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8810 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8811 if (PostDupI16Shuffle[i / 2] == -1)
8812 PostDupI16Shuffle[i / 2] = MappedMask;
8814 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8815 "Conflicting entrties in the original shuffle!");
8817 return DAG.getBitcast(
8819 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8820 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8822 if (SDValue V = tryToWidenViaDuplication())
8826 // Use dedicated unpack instructions for masks that match their pattern.
8827 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8828 0, 16, 1, 17, 2, 18, 3, 19,
8830 4, 20, 5, 21, 6, 22, 7, 23}))
8831 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8832 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8833 8, 24, 9, 25, 10, 26, 11, 27,
8835 12, 28, 13, 29, 14, 30, 15, 31}))
8836 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8838 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8839 // with PSHUFB. It is important to do this before we attempt to generate any
8840 // blends but after all of the single-input lowerings. If the single input
8841 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8842 // want to preserve that and we can DAG combine any longer sequences into
8843 // a PSHUFB in the end. But once we start blending from multiple inputs,
8844 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8845 // and there are *very* few patterns that would actually be faster than the
8846 // PSHUFB approach because of its ability to zero lanes.
8848 // FIXME: The only exceptions to the above are blends which are exact
8849 // interleavings with direct instructions supporting them. We currently don't
8850 // handle those well here.
8851 if (Subtarget->hasSSSE3()) {
8852 bool V1InUse = false;
8853 bool V2InUse = false;
8855 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8856 DAG, V1InUse, V2InUse);
8858 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8859 // do so. This avoids using them to handle blends-with-zero which is
8860 // important as a single pshufb is significantly faster for that.
8861 if (V1InUse && V2InUse) {
8862 if (Subtarget->hasSSE41())
8863 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8864 Mask, Subtarget, DAG))
8867 // We can use an unpack to do the blending rather than an or in some
8868 // cases. Even though the or may be (very minorly) more efficient, we
8869 // preference this lowering because there are common cases where part of
8870 // the complexity of the shuffles goes away when we do the final blend as
8872 // FIXME: It might be worth trying to detect if the unpack-feeding
8873 // shuffles will both be pshufb, in which case we shouldn't bother with
8875 if (SDValue Unpack =
8876 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8883 // There are special ways we can lower some single-element blends.
8884 if (NumV2Elements == 1)
8885 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8886 Mask, Subtarget, DAG))
8889 if (SDValue BitBlend =
8890 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8893 // Check whether a compaction lowering can be done. This handles shuffles
8894 // which take every Nth element for some even N. See the helper function for
8897 // We special case these as they can be particularly efficiently handled with
8898 // the PACKUSB instruction on x86 and they show up in common patterns of
8899 // rearranging bytes to truncate wide elements.
8900 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8901 // NumEvenDrops is the power of two stride of the elements. Another way of
8902 // thinking about it is that we need to drop the even elements this many
8903 // times to get the original input.
8904 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8906 // First we need to zero all the dropped bytes.
8907 assert(NumEvenDrops <= 3 &&
8908 "No support for dropping even elements more than 3 times.");
8909 // We use the mask type to pick which bytes are preserved based on how many
8910 // elements are dropped.
8911 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8912 SDValue ByteClearMask = DAG.getBitcast(
8913 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8914 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8916 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8918 // Now pack things back together.
8919 V1 = DAG.getBitcast(MVT::v8i16, V1);
8920 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
8921 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8922 for (int i = 1; i < NumEvenDrops; ++i) {
8923 Result = DAG.getBitcast(MVT::v8i16, Result);
8924 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8930 // Handle multi-input cases by blending single-input shuffles.
8931 if (NumV2Elements > 0)
8932 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8935 // The fallback path for single-input shuffles widens this into two v8i16
8936 // vectors with unpacks, shuffles those, and then pulls them back together
8940 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8941 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8942 for (int i = 0; i < 16; ++i)
8944 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8946 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8948 SDValue VLoHalf, VHiHalf;
8949 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8950 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8952 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8953 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8954 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8955 [](int M) { return M >= 0 && M % 2 == 1; })) {
8956 // Use a mask to drop the high bytes.
8957 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
8958 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8959 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8961 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8962 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8964 // Squash the masks to point directly into VLoHalf.
8965 for (int &M : LoBlendMask)
8968 for (int &M : HiBlendMask)
8972 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8973 // VHiHalf so that we can blend them as i16s.
8974 VLoHalf = DAG.getBitcast(
8975 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8976 VHiHalf = DAG.getBitcast(
8977 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8980 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8981 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8983 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8986 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8988 /// This routine breaks down the specific type of 128-bit shuffle and
8989 /// dispatches to the lowering routines accordingly.
8990 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8991 MVT VT, const X86Subtarget *Subtarget,
8992 SelectionDAG &DAG) {
8993 switch (VT.SimpleTy) {
8995 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8997 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8999 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9001 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9003 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9005 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9008 llvm_unreachable("Unimplemented!");
9012 /// \brief Helper function to test whether a shuffle mask could be
9013 /// simplified by widening the elements being shuffled.
9015 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9016 /// leaves it in an unspecified state.
9018 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9019 /// shuffle masks. The latter have the special property of a '-2' representing
9020 /// a zero-ed lane of a vector.
9021 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9022 SmallVectorImpl<int> &WidenedMask) {
9023 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9024 // If both elements are undef, its trivial.
9025 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9026 WidenedMask.push_back(SM_SentinelUndef);
9030 // Check for an undef mask and a mask value properly aligned to fit with
9031 // a pair of values. If we find such a case, use the non-undef mask's value.
9032 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9033 WidenedMask.push_back(Mask[i + 1] / 2);
9036 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9037 WidenedMask.push_back(Mask[i] / 2);
9041 // When zeroing, we need to spread the zeroing across both lanes to widen.
9042 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9043 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9044 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9045 WidenedMask.push_back(SM_SentinelZero);
9051 // Finally check if the two mask values are adjacent and aligned with
9053 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9054 WidenedMask.push_back(Mask[i] / 2);
9058 // Otherwise we can't safely widen the elements used in this shuffle.
9061 assert(WidenedMask.size() == Mask.size() / 2 &&
9062 "Incorrect size of mask after widening the elements!");
9067 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9069 /// This routine just extracts two subvectors, shuffles them independently, and
9070 /// then concatenates them back together. This should work effectively with all
9071 /// AVX vector shuffle types.
9072 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9073 SDValue V2, ArrayRef<int> Mask,
9074 SelectionDAG &DAG) {
9075 assert(VT.getSizeInBits() >= 256 &&
9076 "Only for 256-bit or wider vector shuffles!");
9077 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9078 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9080 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9081 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9083 int NumElements = VT.getVectorNumElements();
9084 int SplitNumElements = NumElements / 2;
9085 MVT ScalarVT = VT.getScalarType();
9086 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9088 // Rather than splitting build-vectors, just build two narrower build
9089 // vectors. This helps shuffling with splats and zeros.
9090 auto SplitVector = [&](SDValue V) {
9091 while (V.getOpcode() == ISD::BITCAST)
9092 V = V->getOperand(0);
9094 MVT OrigVT = V.getSimpleValueType();
9095 int OrigNumElements = OrigVT.getVectorNumElements();
9096 int OrigSplitNumElements = OrigNumElements / 2;
9097 MVT OrigScalarVT = OrigVT.getScalarType();
9098 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9102 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9104 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9105 DAG.getIntPtrConstant(0, DL));
9106 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9107 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9110 SmallVector<SDValue, 16> LoOps, HiOps;
9111 for (int i = 0; i < OrigSplitNumElements; ++i) {
9112 LoOps.push_back(BV->getOperand(i));
9113 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9115 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9116 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9118 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9119 DAG.getBitcast(SplitVT, HiV));
9122 SDValue LoV1, HiV1, LoV2, HiV2;
9123 std::tie(LoV1, HiV1) = SplitVector(V1);
9124 std::tie(LoV2, HiV2) = SplitVector(V2);
9126 // Now create two 4-way blends of these half-width vectors.
9127 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9128 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9129 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9130 for (int i = 0; i < SplitNumElements; ++i) {
9131 int M = HalfMask[i];
9132 if (M >= NumElements) {
9133 if (M >= NumElements + SplitNumElements)
9137 V2BlendMask.push_back(M - NumElements);
9138 V1BlendMask.push_back(-1);
9139 BlendMask.push_back(SplitNumElements + i);
9140 } else if (M >= 0) {
9141 if (M >= SplitNumElements)
9145 V2BlendMask.push_back(-1);
9146 V1BlendMask.push_back(M);
9147 BlendMask.push_back(i);
9149 V2BlendMask.push_back(-1);
9150 V1BlendMask.push_back(-1);
9151 BlendMask.push_back(-1);
9155 // Because the lowering happens after all combining takes place, we need to
9156 // manually combine these blend masks as much as possible so that we create
9157 // a minimal number of high-level vector shuffle nodes.
9159 // First try just blending the halves of V1 or V2.
9160 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9161 return DAG.getUNDEF(SplitVT);
9162 if (!UseLoV2 && !UseHiV2)
9163 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9164 if (!UseLoV1 && !UseHiV1)
9165 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9167 SDValue V1Blend, V2Blend;
9168 if (UseLoV1 && UseHiV1) {
9170 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9172 // We only use half of V1 so map the usage down into the final blend mask.
9173 V1Blend = UseLoV1 ? LoV1 : HiV1;
9174 for (int i = 0; i < SplitNumElements; ++i)
9175 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9176 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9178 if (UseLoV2 && UseHiV2) {
9180 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9182 // We only use half of V2 so map the usage down into the final blend mask.
9183 V2Blend = UseLoV2 ? LoV2 : HiV2;
9184 for (int i = 0; i < SplitNumElements; ++i)
9185 if (BlendMask[i] >= SplitNumElements)
9186 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9188 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9190 SDValue Lo = HalfBlend(LoMask);
9191 SDValue Hi = HalfBlend(HiMask);
9192 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9195 /// \brief Either split a vector in halves or decompose the shuffles and the
9198 /// This is provided as a good fallback for many lowerings of non-single-input
9199 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9200 /// between splitting the shuffle into 128-bit components and stitching those
9201 /// back together vs. extracting the single-input shuffles and blending those
9203 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9204 SDValue V2, ArrayRef<int> Mask,
9205 SelectionDAG &DAG) {
9206 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9207 "lower single-input shuffles as it "
9208 "could then recurse on itself.");
9209 int Size = Mask.size();
9211 // If this can be modeled as a broadcast of two elements followed by a blend,
9212 // prefer that lowering. This is especially important because broadcasts can
9213 // often fold with memory operands.
9214 auto DoBothBroadcast = [&] {
9215 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9218 if (V2BroadcastIdx == -1)
9219 V2BroadcastIdx = M - Size;
9220 else if (M - Size != V2BroadcastIdx)
9222 } else if (M >= 0) {
9223 if (V1BroadcastIdx == -1)
9225 else if (M != V1BroadcastIdx)
9230 if (DoBothBroadcast())
9231 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9234 // If the inputs all stem from a single 128-bit lane of each input, then we
9235 // split them rather than blending because the split will decompose to
9236 // unusually few instructions.
9237 int LaneCount = VT.getSizeInBits() / 128;
9238 int LaneSize = Size / LaneCount;
9239 SmallBitVector LaneInputs[2];
9240 LaneInputs[0].resize(LaneCount, false);
9241 LaneInputs[1].resize(LaneCount, false);
9242 for (int i = 0; i < Size; ++i)
9244 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9245 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9246 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9248 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9249 // that the decomposed single-input shuffles don't end up here.
9250 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9253 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9254 /// a permutation and blend of those lanes.
9256 /// This essentially blends the out-of-lane inputs to each lane into the lane
9257 /// from a permuted copy of the vector. This lowering strategy results in four
9258 /// instructions in the worst case for a single-input cross lane shuffle which
9259 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9260 /// of. Special cases for each particular shuffle pattern should be handled
9261 /// prior to trying this lowering.
9262 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9263 SDValue V1, SDValue V2,
9265 SelectionDAG &DAG) {
9266 // FIXME: This should probably be generalized for 512-bit vectors as well.
9267 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9268 int LaneSize = Mask.size() / 2;
9270 // If there are only inputs from one 128-bit lane, splitting will in fact be
9271 // less expensive. The flags track whether the given lane contains an element
9272 // that crosses to another lane.
9273 bool LaneCrossing[2] = {false, false};
9274 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9275 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9276 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9277 if (!LaneCrossing[0] || !LaneCrossing[1])
9278 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9280 if (isSingleInputShuffleMask(Mask)) {
9281 SmallVector<int, 32> FlippedBlendMask;
9282 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9283 FlippedBlendMask.push_back(
9284 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9286 : Mask[i] % LaneSize +
9287 (i / LaneSize) * LaneSize + Size));
9289 // Flip the vector, and blend the results which should now be in-lane. The
9290 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9291 // 5 for the high source. The value 3 selects the high half of source 2 and
9292 // the value 2 selects the low half of source 2. We only use source 2 to
9293 // allow folding it into a memory operand.
9294 unsigned PERMMask = 3 | 2 << 4;
9295 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9296 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9297 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9300 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9301 // will be handled by the above logic and a blend of the results, much like
9302 // other patterns in AVX.
9303 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9306 /// \brief Handle lowering 2-lane 128-bit shuffles.
9307 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9308 SDValue V2, ArrayRef<int> Mask,
9309 const X86Subtarget *Subtarget,
9310 SelectionDAG &DAG) {
9311 // TODO: If minimizing size and one of the inputs is a zero vector and the
9312 // the zero vector has only one use, we could use a VPERM2X128 to save the
9313 // instruction bytes needed to explicitly generate the zero vector.
9315 // Blends are faster and handle all the non-lane-crossing cases.
9316 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9320 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9321 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9323 // If either input operand is a zero vector, use VPERM2X128 because its mask
9324 // allows us to replace the zero input with an implicit zero.
9325 if (!IsV1Zero && !IsV2Zero) {
9326 // Check for patterns which can be matched with a single insert of a 128-bit
9328 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9329 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9330 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9331 VT.getVectorNumElements() / 2);
9332 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9333 DAG.getIntPtrConstant(0, DL));
9334 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9335 OnlyUsesV1 ? V1 : V2,
9336 DAG.getIntPtrConstant(0, DL));
9337 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9341 // Otherwise form a 128-bit permutation. After accounting for undefs,
9342 // convert the 64-bit shuffle mask selection values into 128-bit
9343 // selection bits by dividing the indexes by 2 and shifting into positions
9344 // defined by a vperm2*128 instruction's immediate control byte.
9346 // The immediate permute control byte looks like this:
9347 // [1:0] - select 128 bits from sources for low half of destination
9349 // [3] - zero low half of destination
9350 // [5:4] - select 128 bits from sources for high half of destination
9352 // [7] - zero high half of destination
9354 int MaskLO = Mask[0];
9355 if (MaskLO == SM_SentinelUndef)
9356 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9358 int MaskHI = Mask[2];
9359 if (MaskHI == SM_SentinelUndef)
9360 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9362 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9364 // If either input is a zero vector, replace it with an undef input.
9365 // Shuffle mask values < 4 are selecting elements of V1.
9366 // Shuffle mask values >= 4 are selecting elements of V2.
9367 // Adjust each half of the permute mask by clearing the half that was
9368 // selecting the zero vector and setting the zero mask bit.
9370 V1 = DAG.getUNDEF(VT);
9372 PermMask = (PermMask & 0xf0) | 0x08;
9374 PermMask = (PermMask & 0x0f) | 0x80;
9377 V2 = DAG.getUNDEF(VT);
9379 PermMask = (PermMask & 0xf0) | 0x08;
9381 PermMask = (PermMask & 0x0f) | 0x80;
9384 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9385 DAG.getConstant(PermMask, DL, MVT::i8));
9388 /// \brief Handle lowering 4-lane 128-bit shuffles.
9389 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9390 SDValue V2, ArrayRef<int> WidenedMask,
9391 SelectionDAG &DAG) {
9393 assert(WidenedMask.size() == 4 && "Unexpected mask size for 128bit shuffle!");
9394 // form a 128-bit permutation.
9395 // convert the 64-bit shuffle mask selection values into 128-bit selection
9396 // bits defined by a vshuf64x2 instruction's immediate control byte.
9397 unsigned PermMask = 0, Imm = 0;
9399 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
9400 if(WidenedMask[i] == SM_SentinelZero)
9403 // use first element in place of undef musk
9404 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
9405 PermMask |= (Imm % 4) << (i * 2);
9408 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
9409 DAG.getConstant(PermMask, DL, MVT::i8));
9412 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9413 /// shuffling each lane.
9415 /// This will only succeed when the result of fixing the 128-bit lanes results
9416 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9417 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9418 /// the lane crosses early and then use simpler shuffles within each lane.
9420 /// FIXME: It might be worthwhile at some point to support this without
9421 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9422 /// in x86 only floating point has interesting non-repeating shuffles, and even
9423 /// those are still *marginally* more expensive.
9424 static SDValue lowerVectorShuffleByMerging128BitLanes(
9425 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9426 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9427 assert(!isSingleInputShuffleMask(Mask) &&
9428 "This is only useful with multiple inputs.");
9430 int Size = Mask.size();
9431 int LaneSize = 128 / VT.getScalarSizeInBits();
9432 int NumLanes = Size / LaneSize;
9433 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9435 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9436 // check whether the in-128-bit lane shuffles share a repeating pattern.
9437 SmallVector<int, 4> Lanes;
9438 Lanes.resize(NumLanes, -1);
9439 SmallVector<int, 4> InLaneMask;
9440 InLaneMask.resize(LaneSize, -1);
9441 for (int i = 0; i < Size; ++i) {
9445 int j = i / LaneSize;
9448 // First entry we've seen for this lane.
9449 Lanes[j] = Mask[i] / LaneSize;
9450 } else if (Lanes[j] != Mask[i] / LaneSize) {
9451 // This doesn't match the lane selected previously!
9455 // Check that within each lane we have a consistent shuffle mask.
9456 int k = i % LaneSize;
9457 if (InLaneMask[k] < 0) {
9458 InLaneMask[k] = Mask[i] % LaneSize;
9459 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9460 // This doesn't fit a repeating in-lane mask.
9465 // First shuffle the lanes into place.
9466 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9467 VT.getSizeInBits() / 64);
9468 SmallVector<int, 8> LaneMask;
9469 LaneMask.resize(NumLanes * 2, -1);
9470 for (int i = 0; i < NumLanes; ++i)
9471 if (Lanes[i] >= 0) {
9472 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9473 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9476 V1 = DAG.getBitcast(LaneVT, V1);
9477 V2 = DAG.getBitcast(LaneVT, V2);
9478 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9480 // Cast it back to the type we actually want.
9481 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9483 // Now do a simple shuffle that isn't lane crossing.
9484 SmallVector<int, 8> NewMask;
9485 NewMask.resize(Size, -1);
9486 for (int i = 0; i < Size; ++i)
9488 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9489 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9490 "Must not introduce lane crosses at this point!");
9492 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9495 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9498 /// This returns true if the elements from a particular input are already in the
9499 /// slot required by the given mask and require no permutation.
9500 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9501 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9502 int Size = Mask.size();
9503 for (int i = 0; i < Size; ++i)
9504 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9510 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9511 ArrayRef<int> Mask, SDValue V1,
9512 SDValue V2, SelectionDAG &DAG) {
9514 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9515 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9516 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9517 int NumElts = VT.getVectorNumElements();
9518 bool ShufpdMask = true;
9519 bool CommutableMask = true;
9520 unsigned Immediate = 0;
9521 for (int i = 0; i < NumElts; ++i) {
9524 int Val = (i & 6) + NumElts * (i & 1);
9525 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9526 if (Mask[i] < Val || Mask[i] > Val + 1)
9528 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9529 CommutableMask = false;
9530 Immediate |= (Mask[i] % 2) << i;
9533 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9534 DAG.getConstant(Immediate, DL, MVT::i8));
9536 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9537 DAG.getConstant(Immediate, DL, MVT::i8));
9541 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9543 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9544 /// isn't available.
9545 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9546 const X86Subtarget *Subtarget,
9547 SelectionDAG &DAG) {
9549 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9550 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9551 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9552 ArrayRef<int> Mask = SVOp->getMask();
9553 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9555 SmallVector<int, 4> WidenedMask;
9556 if (canWidenShuffleElements(Mask, WidenedMask))
9557 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9560 if (isSingleInputShuffleMask(Mask)) {
9561 // Check for being able to broadcast a single element.
9562 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9563 Mask, Subtarget, DAG))
9566 // Use low duplicate instructions for masks that match their pattern.
9567 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9568 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9570 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9571 // Non-half-crossing single input shuffles can be lowerid with an
9572 // interleaved permutation.
9573 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9574 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9575 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9576 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9579 // With AVX2 we have direct support for this permutation.
9580 if (Subtarget->hasAVX2())
9581 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9582 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9584 // Otherwise, fall back.
9585 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9589 // X86 has dedicated unpack instructions that can handle specific blend
9590 // operations: UNPCKH and UNPCKL.
9591 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9592 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9593 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9594 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9595 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9596 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9597 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9598 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9600 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9604 // Check if the blend happens to exactly fit that of SHUFPD.
9606 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9609 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9610 // shuffle. However, if we have AVX2 and either inputs are already in place,
9611 // we will be able to shuffle even across lanes the other input in a single
9612 // instruction so skip this pattern.
9613 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9614 isShuffleMaskInputInPlace(1, Mask))))
9615 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9616 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9619 // If we have AVX2 then we always want to lower with a blend because an v4 we
9620 // can fully permute the elements.
9621 if (Subtarget->hasAVX2())
9622 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9625 // Otherwise fall back on generic lowering.
9626 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9629 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9631 /// This routine is only called when we have AVX2 and thus a reasonable
9632 /// instruction set for v4i64 shuffling..
9633 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9634 const X86Subtarget *Subtarget,
9635 SelectionDAG &DAG) {
9637 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9638 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9639 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9640 ArrayRef<int> Mask = SVOp->getMask();
9641 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9642 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9644 SmallVector<int, 4> WidenedMask;
9645 if (canWidenShuffleElements(Mask, WidenedMask))
9646 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9649 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9653 // Check for being able to broadcast a single element.
9654 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9655 Mask, Subtarget, DAG))
9658 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9659 // use lower latency instructions that will operate on both 128-bit lanes.
9660 SmallVector<int, 2> RepeatedMask;
9661 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9662 if (isSingleInputShuffleMask(Mask)) {
9663 int PSHUFDMask[] = {-1, -1, -1, -1};
9664 for (int i = 0; i < 2; ++i)
9665 if (RepeatedMask[i] >= 0) {
9666 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9667 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9669 return DAG.getBitcast(
9671 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9672 DAG.getBitcast(MVT::v8i32, V1),
9673 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9677 // AVX2 provides a direct instruction for permuting a single input across
9679 if (isSingleInputShuffleMask(Mask))
9680 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9681 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9683 // Try to use shift instructions.
9685 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9688 // Use dedicated unpack instructions for masks that match their pattern.
9689 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9690 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9691 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9692 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9693 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9694 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9695 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9696 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9698 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9699 // shuffle. However, if we have AVX2 and either inputs are already in place,
9700 // we will be able to shuffle even across lanes the other input in a single
9701 // instruction so skip this pattern.
9702 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9703 isShuffleMaskInputInPlace(1, Mask))))
9704 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9705 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9708 // Otherwise fall back on generic blend lowering.
9709 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9713 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9715 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9716 /// isn't available.
9717 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9718 const X86Subtarget *Subtarget,
9719 SelectionDAG &DAG) {
9721 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9722 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9723 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9724 ArrayRef<int> Mask = SVOp->getMask();
9725 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9727 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9731 // Check for being able to broadcast a single element.
9732 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9733 Mask, Subtarget, DAG))
9736 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9737 // options to efficiently lower the shuffle.
9738 SmallVector<int, 4> RepeatedMask;
9739 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9740 assert(RepeatedMask.size() == 4 &&
9741 "Repeated masks must be half the mask width!");
9743 // Use even/odd duplicate instructions for masks that match their pattern.
9744 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9745 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9746 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9747 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9749 if (isSingleInputShuffleMask(Mask))
9750 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9751 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9753 // Use dedicated unpack instructions for masks that match their pattern.
9754 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9755 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9756 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9757 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9758 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9759 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9760 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9761 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9763 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9764 // have already handled any direct blends. We also need to squash the
9765 // repeated mask into a simulated v4f32 mask.
9766 for (int i = 0; i < 4; ++i)
9767 if (RepeatedMask[i] >= 8)
9768 RepeatedMask[i] -= 4;
9769 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9772 // If we have a single input shuffle with different shuffle patterns in the
9773 // two 128-bit lanes use the variable mask to VPERMILPS.
9774 if (isSingleInputShuffleMask(Mask)) {
9775 SDValue VPermMask[8];
9776 for (int i = 0; i < 8; ++i)
9777 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9778 : DAG.getConstant(Mask[i], DL, MVT::i32);
9779 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9781 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9782 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9784 if (Subtarget->hasAVX2())
9786 X86ISD::VPERMV, DL, MVT::v8f32,
9787 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9788 MVT::v8i32, VPermMask)),
9791 // Otherwise, fall back.
9792 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9796 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9798 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9799 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9802 // If we have AVX2 then we always want to lower with a blend because at v8 we
9803 // can fully permute the elements.
9804 if (Subtarget->hasAVX2())
9805 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9808 // Otherwise fall back on generic lowering.
9809 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9812 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9814 /// This routine is only called when we have AVX2 and thus a reasonable
9815 /// instruction set for v8i32 shuffling..
9816 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9817 const X86Subtarget *Subtarget,
9818 SelectionDAG &DAG) {
9820 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9821 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9823 ArrayRef<int> Mask = SVOp->getMask();
9824 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9825 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9827 // Whenever we can lower this as a zext, that instruction is strictly faster
9828 // than any alternative. It also allows us to fold memory operands into the
9829 // shuffle in many cases.
9830 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9831 Mask, Subtarget, DAG))
9834 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9838 // Check for being able to broadcast a single element.
9839 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9840 Mask, Subtarget, DAG))
9843 // If the shuffle mask is repeated in each 128-bit lane we can use more
9844 // efficient instructions that mirror the shuffles across the two 128-bit
9846 SmallVector<int, 4> RepeatedMask;
9847 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9848 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9849 if (isSingleInputShuffleMask(Mask))
9850 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9851 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9853 // Use dedicated unpack instructions for masks that match their pattern.
9854 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9855 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9856 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9857 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9858 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9859 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9860 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9861 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9864 // Try to use shift instructions.
9866 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9869 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9870 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9873 // If the shuffle patterns aren't repeated but it is a single input, directly
9874 // generate a cross-lane VPERMD instruction.
9875 if (isSingleInputShuffleMask(Mask)) {
9876 SDValue VPermMask[8];
9877 for (int i = 0; i < 8; ++i)
9878 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9879 : DAG.getConstant(Mask[i], DL, MVT::i32);
9881 X86ISD::VPERMV, DL, MVT::v8i32,
9882 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9885 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9887 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9888 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9891 // Otherwise fall back on generic blend lowering.
9892 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9896 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9898 /// This routine is only called when we have AVX2 and thus a reasonable
9899 /// instruction set for v16i16 shuffling..
9900 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9901 const X86Subtarget *Subtarget,
9902 SelectionDAG &DAG) {
9904 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9905 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9906 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9907 ArrayRef<int> Mask = SVOp->getMask();
9908 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9909 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9911 // Whenever we can lower this as a zext, that instruction is strictly faster
9912 // than any alternative. It also allows us to fold memory operands into the
9913 // shuffle in many cases.
9914 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9915 Mask, Subtarget, DAG))
9918 // Check for being able to broadcast a single element.
9919 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9920 Mask, Subtarget, DAG))
9923 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9927 // Use dedicated unpack instructions for masks that match their pattern.
9928 if (isShuffleEquivalent(V1, V2, Mask,
9929 {// First 128-bit lane:
9930 0, 16, 1, 17, 2, 18, 3, 19,
9931 // Second 128-bit lane:
9932 8, 24, 9, 25, 10, 26, 11, 27}))
9933 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9934 if (isShuffleEquivalent(V1, V2, Mask,
9935 {// First 128-bit lane:
9936 4, 20, 5, 21, 6, 22, 7, 23,
9937 // Second 128-bit lane:
9938 12, 28, 13, 29, 14, 30, 15, 31}))
9939 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9941 // Try to use shift instructions.
9943 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9946 // Try to use byte rotation instructions.
9947 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9948 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9951 if (isSingleInputShuffleMask(Mask)) {
9952 // There are no generalized cross-lane shuffle operations available on i16
9954 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9955 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9958 SmallVector<int, 8> RepeatedMask;
9959 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9960 // As this is a single-input shuffle, the repeated mask should be
9961 // a strictly valid v8i16 mask that we can pass through to the v8i16
9962 // lowering to handle even the v16 case.
9963 return lowerV8I16GeneralSingleInputVectorShuffle(
9964 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9967 SDValue PSHUFBMask[32];
9968 for (int i = 0; i < 16; ++i) {
9969 if (Mask[i] == -1) {
9970 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9974 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9975 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9976 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9977 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9979 return DAG.getBitcast(MVT::v16i16,
9980 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
9981 DAG.getBitcast(MVT::v32i8, V1),
9982 DAG.getNode(ISD::BUILD_VECTOR, DL,
9983 MVT::v32i8, PSHUFBMask)));
9986 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9988 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9989 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9992 // Otherwise fall back on generic lowering.
9993 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9996 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9998 /// This routine is only called when we have AVX2 and thus a reasonable
9999 /// instruction set for v32i8 shuffling..
10000 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10001 const X86Subtarget *Subtarget,
10002 SelectionDAG &DAG) {
10004 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10005 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10006 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10007 ArrayRef<int> Mask = SVOp->getMask();
10008 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10009 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10011 // Whenever we can lower this as a zext, that instruction is strictly faster
10012 // than any alternative. It also allows us to fold memory operands into the
10013 // shuffle in many cases.
10014 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10015 Mask, Subtarget, DAG))
10018 // Check for being able to broadcast a single element.
10019 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10020 Mask, Subtarget, DAG))
10023 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10027 // Use dedicated unpack instructions for masks that match their pattern.
10028 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10030 if (isShuffleEquivalent(
10032 {// First 128-bit lane:
10033 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10034 // Second 128-bit lane:
10035 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10036 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10037 if (isShuffleEquivalent(
10039 {// First 128-bit lane:
10040 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10041 // Second 128-bit lane:
10042 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10043 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10045 // Try to use shift instructions.
10046 if (SDValue Shift =
10047 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10050 // Try to use byte rotation instructions.
10051 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10052 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10055 if (isSingleInputShuffleMask(Mask)) {
10056 // There are no generalized cross-lane shuffle operations available on i8
10058 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10059 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10062 SDValue PSHUFBMask[32];
10063 for (int i = 0; i < 32; ++i)
10066 ? DAG.getUNDEF(MVT::i8)
10067 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10070 return DAG.getNode(
10071 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10072 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10075 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10077 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10078 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10081 // Otherwise fall back on generic lowering.
10082 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10085 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10087 /// This routine either breaks down the specific type of a 256-bit x86 vector
10088 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10089 /// together based on the available instructions.
10090 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10091 MVT VT, const X86Subtarget *Subtarget,
10092 SelectionDAG &DAG) {
10094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10095 ArrayRef<int> Mask = SVOp->getMask();
10097 // If we have a single input to the zero element, insert that into V1 if we
10098 // can do so cheaply.
10099 int NumElts = VT.getVectorNumElements();
10100 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10101 return M >= NumElts;
10104 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10105 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10106 DL, VT, V1, V2, Mask, Subtarget, DAG))
10109 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10110 // check for those subtargets here and avoid much of the subtarget querying in
10111 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10112 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10113 // floating point types there eventually, just immediately cast everything to
10114 // a float and operate entirely in that domain.
10115 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10116 int ElementBits = VT.getScalarSizeInBits();
10117 if (ElementBits < 32)
10118 // No floating point type available, decompose into 128-bit vectors.
10119 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10121 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10122 VT.getVectorNumElements());
10123 V1 = DAG.getBitcast(FpVT, V1);
10124 V2 = DAG.getBitcast(FpVT, V2);
10125 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10128 switch (VT.SimpleTy) {
10130 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10132 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10134 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10136 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10138 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10140 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10143 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10147 static SDValue lowerVectorShuffleWithVALIGN(SDLoc DL, MVT VT,
10148 ArrayRef<int> Mask, SDValue V1,
10149 SDValue V2, SelectionDAG &DAG) {
10151 assert(VT.getScalarSizeInBits() >= 32 && "Unexpected data type for VALIGN");
10152 // VALIGN pattern 2, 3, 4, 5, .. (sequential, shifted right)
10154 for (int i = 0; i < (signed)VT.getVectorNumElements(); ++i) {
10159 if (AlignVal == -1)
10160 AlignVal = Mask[i] - i;
10161 else if (Mask[i] - i != AlignVal)
10164 // Vector source operands should be swapped
10165 return DAG.getNode(X86ISD::VALIGN, DL, VT, V2, V1,
10166 DAG.getConstant(AlignVal, DL, MVT::i8));
10169 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10170 ArrayRef<int> Mask, SDValue V1,
10171 SDValue V2, SelectionDAG &DAG) {
10173 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10175 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10176 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10178 SmallVector<SDValue, 32> VPermMask;
10179 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10180 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10181 DAG.getConstant(Mask[i], DL,MaskEltVT));
10182 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10184 if (isSingleInputShuffleMask(Mask))
10185 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10187 return DAG.getNode(X86ISD::VPERMV3, DL, VT, MaskNode, V1, V2);
10191 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10192 static SDValue lowerV8X64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10193 const X86Subtarget *Subtarget,
10194 SelectionDAG &DAG) {
10196 MVT VT = Op.getSimpleValueType();
10197 assert((V1.getSimpleValueType() == MVT::v8f64 ||
10198 V1.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
10199 assert((V2.getSimpleValueType() == MVT::v8f64 ||
10200 V2.getSimpleValueType() == MVT::v8i64) && "Bad operand type!");
10201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10202 ArrayRef<int> Mask = SVOp->getMask();
10203 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10205 SmallVector<int, 4> WidenedMask;
10206 if (canWidenShuffleElements(Mask, WidenedMask))
10207 if(SDValue Op = lowerV4X128VectorShuffle(DL, VT, V1, V2, WidenedMask, DAG))
10209 // X86 has dedicated unpack instructions that can handle specific blend
10210 // operations: UNPCKH and UNPCKL.
10211 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10212 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
10213 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10214 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
10216 if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
10219 if (SDValue Op = lowerVectorShuffleWithSHUFPD(DL, VT, Mask, V1, V2, DAG))
10222 // PERMILPD instruction - mask 0/1, 0/1, 2/3, 2/3, 4/5, 4/5, 6/7, 6/7
10223 if (isSingleInputShuffleMask(Mask)) {
10224 if (!is128BitLaneCrossingShuffleMask(VT, Mask))
10225 return DAG.getNode(X86ISD::VPERMILPI, DL, VT, V1,
10226 get1bitLaneShuffleImm8ForMask(Mask, DL, DAG));
10228 SmallVector<int, 4> RepeatedMask;
10229 if (is256BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask))
10230 return DAG.getNode(X86ISD::VPERMI, DL, VT, V1,
10231 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10233 return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
10236 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10237 static SDValue lowerV16X32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10238 const X86Subtarget *Subtarget,
10239 SelectionDAG &DAG) {
10240 MVT VT = Op.getSimpleValueType();
10242 assert((V1.getSimpleValueType() == MVT::v16i32 ||
10243 V1.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
10244 assert((V2.getSimpleValueType() == MVT::v16i32 ||
10245 V2.getSimpleValueType() == MVT::v16f32) && "Bad operand type!");
10246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10247 ArrayRef<int> Mask = SVOp->getMask();
10248 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10250 // Use dedicated unpack instructions for masks that match their pattern.
10251 if (isShuffleEquivalent(V1, V2, Mask,
10252 {// First 128-bit lane.
10253 0, 16, 1, 17, 4, 20, 5, 21,
10254 // Second 128-bit lane.
10255 8, 24, 9, 25, 12, 28, 13, 29}))
10256 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
10257 if (isShuffleEquivalent(V1, V2, Mask,
10258 {// First 128-bit lane.
10259 2, 18, 3, 19, 6, 22, 7, 23,
10260 // Second 128-bit lane.
10261 10, 26, 11, 27, 14, 30, 15, 31}))
10262 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
10264 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10,
10266 return DAG.getNode(X86ISD::MOVSLDUP, DL, VT, V1);
10267 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11,
10269 return DAG.getNode(X86ISD::MOVSHDUP, DL, VT, V1);
10271 SmallVector<int, 4> RepeatedMask;
10272 if (is128BitLaneRepeatedShuffleMask(VT, Mask, RepeatedMask)) {
10273 if (isSingleInputShuffleMask(Mask)) {
10274 unsigned Opc = VT.isInteger() ? X86ISD::PSHUFD : X86ISD::VPERMILPI;
10275 return DAG.getNode(Opc, DL, VT, V1,
10276 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10279 for (int i = 0; i < 4; ++i)
10280 if (RepeatedMask[i] >= 16)
10281 RepeatedMask[i] -= 12;
10282 return lowerVectorShuffleWithSHUFPS(DL, VT, RepeatedMask, V1, V2, DAG);
10285 if (SDValue Op = lowerVectorShuffleWithVALIGN(DL, VT, Mask, V1, V2, DAG))
10288 return lowerVectorShuffleWithPERMV(DL, VT, Mask, V1, V2, DAG);
10291 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10292 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10293 const X86Subtarget *Subtarget,
10294 SelectionDAG &DAG) {
10296 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10297 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10299 ArrayRef<int> Mask = SVOp->getMask();
10300 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10301 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10303 // FIXME: Implement direct support for this type!
10304 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10307 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10308 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10309 const X86Subtarget *Subtarget,
10310 SelectionDAG &DAG) {
10312 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10313 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10314 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10315 ArrayRef<int> Mask = SVOp->getMask();
10316 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10317 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10319 // FIXME: Implement direct support for this type!
10320 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10323 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10325 /// This routine either breaks down the specific type of a 512-bit x86 vector
10326 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10327 /// together based on the available instructions.
10328 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10329 MVT VT, const X86Subtarget *Subtarget,
10330 SelectionDAG &DAG) {
10332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10333 ArrayRef<int> Mask = SVOp->getMask();
10334 assert(Subtarget->hasAVX512() &&
10335 "Cannot lower 512-bit vectors w/ basic ISA!");
10337 // Check for being able to broadcast a single element.
10338 if (SDValue Broadcast =
10339 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10342 // Dispatch to each element type for lowering. If we don't have supprot for
10343 // specific element type shuffles at 512 bits, immediately split them and
10344 // lower them. Each lowering routine of a given type is allowed to assume that
10345 // the requisite ISA extensions for that element type are available.
10346 switch (VT.SimpleTy) {
10349 return lowerV8X64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10352 return lowerV16X32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10354 if (Subtarget->hasBWI())
10355 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10358 if (Subtarget->hasBWI())
10359 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10363 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10366 // Otherwise fall back on splitting.
10367 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10370 /// \brief Top-level lowering for x86 vector shuffles.
10372 /// This handles decomposition, canonicalization, and lowering of all x86
10373 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10374 /// above in helper routines. The canonicalization attempts to widen shuffles
10375 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10376 /// s.t. only one of the two inputs needs to be tested, etc.
10377 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10378 SelectionDAG &DAG) {
10379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10380 ArrayRef<int> Mask = SVOp->getMask();
10381 SDValue V1 = Op.getOperand(0);
10382 SDValue V2 = Op.getOperand(1);
10383 MVT VT = Op.getSimpleValueType();
10384 int NumElements = VT.getVectorNumElements();
10387 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10389 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10390 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10391 if (V1IsUndef && V2IsUndef)
10392 return DAG.getUNDEF(VT);
10394 // When we create a shuffle node we put the UNDEF node to second operand,
10395 // but in some cases the first operand may be transformed to UNDEF.
10396 // In this case we should just commute the node.
10398 return DAG.getCommutedVectorShuffle(*SVOp);
10400 // Check for non-undef masks pointing at an undef vector and make the masks
10401 // undef as well. This makes it easier to match the shuffle based solely on
10405 if (M >= NumElements) {
10406 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10407 for (int &M : NewMask)
10408 if (M >= NumElements)
10410 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10413 // We actually see shuffles that are entirely re-arrangements of a set of
10414 // zero inputs. This mostly happens while decomposing complex shuffles into
10415 // simple ones. Directly lower these as a buildvector of zeros.
10416 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10417 if (Zeroable.all())
10418 return getZeroVector(VT, Subtarget, DAG, dl);
10420 // Try to collapse shuffles into using a vector type with fewer elements but
10421 // wider element types. We cap this to not form integers or floating point
10422 // elements wider than 64 bits, but it might be interesting to form i128
10423 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10424 SmallVector<int, 16> WidenedMask;
10425 if (VT.getScalarSizeInBits() < 64 &&
10426 canWidenShuffleElements(Mask, WidenedMask)) {
10427 MVT NewEltVT = VT.isFloatingPoint()
10428 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10429 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10430 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10431 // Make sure that the new vector type is legal. For example, v2f64 isn't
10433 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10434 V1 = DAG.getBitcast(NewVT, V1);
10435 V2 = DAG.getBitcast(NewVT, V2);
10436 return DAG.getBitcast(
10437 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10441 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10442 for (int M : SVOp->getMask())
10444 ++NumUndefElements;
10445 else if (M < NumElements)
10450 // Commute the shuffle as needed such that more elements come from V1 than
10451 // V2. This allows us to match the shuffle pattern strictly on how many
10452 // elements come from V1 without handling the symmetric cases.
10453 if (NumV2Elements > NumV1Elements)
10454 return DAG.getCommutedVectorShuffle(*SVOp);
10456 // When the number of V1 and V2 elements are the same, try to minimize the
10457 // number of uses of V2 in the low half of the vector. When that is tied,
10458 // ensure that the sum of indices for V1 is equal to or lower than the sum
10459 // indices for V2. When those are equal, try to ensure that the number of odd
10460 // indices for V1 is lower than the number of odd indices for V2.
10461 if (NumV1Elements == NumV2Elements) {
10462 int LowV1Elements = 0, LowV2Elements = 0;
10463 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10464 if (M >= NumElements)
10468 if (LowV2Elements > LowV1Elements) {
10469 return DAG.getCommutedVectorShuffle(*SVOp);
10470 } else if (LowV2Elements == LowV1Elements) {
10471 int SumV1Indices = 0, SumV2Indices = 0;
10472 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10473 if (SVOp->getMask()[i] >= NumElements)
10475 else if (SVOp->getMask()[i] >= 0)
10477 if (SumV2Indices < SumV1Indices) {
10478 return DAG.getCommutedVectorShuffle(*SVOp);
10479 } else if (SumV2Indices == SumV1Indices) {
10480 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10481 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10482 if (SVOp->getMask()[i] >= NumElements)
10483 NumV2OddIndices += i % 2;
10484 else if (SVOp->getMask()[i] >= 0)
10485 NumV1OddIndices += i % 2;
10486 if (NumV2OddIndices < NumV1OddIndices)
10487 return DAG.getCommutedVectorShuffle(*SVOp);
10492 // For each vector width, delegate to a specialized lowering routine.
10493 if (VT.getSizeInBits() == 128)
10494 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10496 if (VT.getSizeInBits() == 256)
10497 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10499 // Force AVX-512 vectors to be scalarized for now.
10500 // FIXME: Implement AVX-512 support!
10501 if (VT.getSizeInBits() == 512)
10502 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10504 llvm_unreachable("Unimplemented!");
10507 // This function assumes its argument is a BUILD_VECTOR of constants or
10508 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10510 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10511 unsigned &MaskValue) {
10513 unsigned NumElems = BuildVector->getNumOperands();
10514 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10515 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10516 unsigned NumElemsInLane = NumElems / NumLanes;
10518 // Blend for v16i16 should be symetric for the both lanes.
10519 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10520 SDValue EltCond = BuildVector->getOperand(i);
10521 SDValue SndLaneEltCond =
10522 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10524 int Lane1Cond = -1, Lane2Cond = -1;
10525 if (isa<ConstantSDNode>(EltCond))
10526 Lane1Cond = !isZero(EltCond);
10527 if (isa<ConstantSDNode>(SndLaneEltCond))
10528 Lane2Cond = !isZero(SndLaneEltCond);
10530 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10531 // Lane1Cond != 0, means we want the first argument.
10532 // Lane1Cond == 0, means we want the second argument.
10533 // The encoding of this argument is 0 for the first argument, 1
10534 // for the second. Therefore, invert the condition.
10535 MaskValue |= !Lane1Cond << i;
10536 else if (Lane1Cond < 0)
10537 MaskValue |= !Lane2Cond << i;
10544 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10545 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10546 const X86Subtarget *Subtarget,
10547 SelectionDAG &DAG) {
10548 SDValue Cond = Op.getOperand(0);
10549 SDValue LHS = Op.getOperand(1);
10550 SDValue RHS = Op.getOperand(2);
10552 MVT VT = Op.getSimpleValueType();
10554 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10556 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10558 // Only non-legal VSELECTs reach this lowering, convert those into generic
10559 // shuffles and re-use the shuffle lowering path for blends.
10560 SmallVector<int, 32> Mask;
10561 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10562 SDValue CondElt = CondBV->getOperand(i);
10564 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10566 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10569 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10570 // A vselect where all conditions and data are constants can be optimized into
10571 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10572 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10573 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10574 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10577 // Try to lower this to a blend-style vector shuffle. This can handle all
10578 // constant condition cases.
10579 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10582 // Variable blends are only legal from SSE4.1 onward.
10583 if (!Subtarget->hasSSE41())
10586 // Only some types will be legal on some subtargets. If we can emit a legal
10587 // VSELECT-matching blend, return Op, and but if we need to expand, return
10589 switch (Op.getSimpleValueType().SimpleTy) {
10591 // Most of the vector types have blends past SSE4.1.
10595 // The byte blends for AVX vectors were introduced only in AVX2.
10596 if (Subtarget->hasAVX2())
10603 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10604 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10607 // FIXME: We should custom lower this by fixing the condition and using i8
10613 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10614 MVT VT = Op.getSimpleValueType();
10617 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10620 if (VT.getSizeInBits() == 8) {
10621 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10622 Op.getOperand(0), Op.getOperand(1));
10623 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10624 DAG.getValueType(VT));
10625 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10628 if (VT.getSizeInBits() == 16) {
10629 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10630 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10632 return DAG.getNode(
10633 ISD::TRUNCATE, dl, MVT::i16,
10634 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10635 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10636 Op.getOperand(1)));
10637 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10638 Op.getOperand(0), Op.getOperand(1));
10639 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10640 DAG.getValueType(VT));
10641 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10644 if (VT == MVT::f32) {
10645 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10646 // the result back to FR32 register. It's only worth matching if the
10647 // result has a single use which is a store or a bitcast to i32. And in
10648 // the case of a store, it's not worth it if the index is a constant 0,
10649 // because a MOVSSmr can be used instead, which is smaller and faster.
10650 if (!Op.hasOneUse())
10652 SDNode *User = *Op.getNode()->use_begin();
10653 if ((User->getOpcode() != ISD::STORE ||
10654 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10655 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10656 (User->getOpcode() != ISD::BITCAST ||
10657 User->getValueType(0) != MVT::i32))
10659 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10660 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10662 return DAG.getBitcast(MVT::f32, Extract);
10665 if (VT == MVT::i32 || VT == MVT::i64) {
10666 // ExtractPS/pextrq works with constant index.
10667 if (isa<ConstantSDNode>(Op.getOperand(1)))
10673 /// Extract one bit from mask vector, like v16i1 or v8i1.
10674 /// AVX-512 feature.
10676 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10677 SDValue Vec = Op.getOperand(0);
10679 MVT VecVT = Vec.getSimpleValueType();
10680 SDValue Idx = Op.getOperand(1);
10681 MVT EltVT = Op.getSimpleValueType();
10683 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10684 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10685 "Unexpected vector type in ExtractBitFromMaskVector");
10687 // variable index can't be handled in mask registers,
10688 // extend vector to VR512
10689 if (!isa<ConstantSDNode>(Idx)) {
10690 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10691 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10692 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10693 ExtVT.getVectorElementType(), Ext, Idx);
10694 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10697 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10698 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10699 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10700 rc = getRegClassFor(MVT::v16i1);
10701 unsigned MaxSift = rc->getSize()*8 - 1;
10702 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10703 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10704 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10705 DAG.getConstant(MaxSift, dl, MVT::i8));
10706 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10707 DAG.getIntPtrConstant(0, dl));
10711 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10712 SelectionDAG &DAG) const {
10714 SDValue Vec = Op.getOperand(0);
10715 MVT VecVT = Vec.getSimpleValueType();
10716 SDValue Idx = Op.getOperand(1);
10718 if (Op.getSimpleValueType() == MVT::i1)
10719 return ExtractBitFromMaskVector(Op, DAG);
10721 if (!isa<ConstantSDNode>(Idx)) {
10722 if (VecVT.is512BitVector() ||
10723 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10724 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10727 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10728 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10729 MaskEltVT.getSizeInBits());
10731 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10732 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10733 getZeroVector(MaskVT, Subtarget, DAG, dl),
10734 Idx, DAG.getConstant(0, dl, getPointerTy()));
10735 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10736 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10737 Perm, DAG.getConstant(0, dl, getPointerTy()));
10742 // If this is a 256-bit vector result, first extract the 128-bit vector and
10743 // then extract the element from the 128-bit vector.
10744 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10746 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10747 // Get the 128-bit vector.
10748 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10749 MVT EltVT = VecVT.getVectorElementType();
10751 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10753 //if (IdxVal >= NumElems/2)
10754 // IdxVal -= NumElems/2;
10755 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10756 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10757 DAG.getConstant(IdxVal, dl, MVT::i32));
10760 assert(VecVT.is128BitVector() && "Unexpected vector length");
10762 if (Subtarget->hasSSE41()) {
10763 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10768 MVT VT = Op.getSimpleValueType();
10769 // TODO: handle v16i8.
10770 if (VT.getSizeInBits() == 16) {
10771 SDValue Vec = Op.getOperand(0);
10772 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10774 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10775 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10776 DAG.getBitcast(MVT::v4i32, Vec),
10777 Op.getOperand(1)));
10778 // Transform it so it match pextrw which produces a 32-bit result.
10779 MVT EltVT = MVT::i32;
10780 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10781 Op.getOperand(0), Op.getOperand(1));
10782 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10783 DAG.getValueType(VT));
10784 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10787 if (VT.getSizeInBits() == 32) {
10788 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10792 // SHUFPS the element to the lowest double word, then movss.
10793 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10794 MVT VVT = Op.getOperand(0).getSimpleValueType();
10795 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10796 DAG.getUNDEF(VVT), Mask);
10797 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10798 DAG.getIntPtrConstant(0, dl));
10801 if (VT.getSizeInBits() == 64) {
10802 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10803 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10804 // to match extract_elt for f64.
10805 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10809 // UNPCKHPD the element to the lowest double word, then movsd.
10810 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10811 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10812 int Mask[2] = { 1, -1 };
10813 MVT VVT = Op.getOperand(0).getSimpleValueType();
10814 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10815 DAG.getUNDEF(VVT), Mask);
10816 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10817 DAG.getIntPtrConstant(0, dl));
10823 /// Insert one bit to mask vector, like v16i1 or v8i1.
10824 /// AVX-512 feature.
10826 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10828 SDValue Vec = Op.getOperand(0);
10829 SDValue Elt = Op.getOperand(1);
10830 SDValue Idx = Op.getOperand(2);
10831 MVT VecVT = Vec.getSimpleValueType();
10833 if (!isa<ConstantSDNode>(Idx)) {
10834 // Non constant index. Extend source and destination,
10835 // insert element and then truncate the result.
10836 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10837 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10838 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10839 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10840 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10841 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10844 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10845 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10847 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10848 DAG.getConstant(IdxVal, dl, MVT::i8));
10849 if (Vec.getOpcode() == ISD::UNDEF)
10851 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10854 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10855 SelectionDAG &DAG) const {
10856 MVT VT = Op.getSimpleValueType();
10857 MVT EltVT = VT.getVectorElementType();
10859 if (EltVT == MVT::i1)
10860 return InsertBitToMaskVector(Op, DAG);
10863 SDValue N0 = Op.getOperand(0);
10864 SDValue N1 = Op.getOperand(1);
10865 SDValue N2 = Op.getOperand(2);
10866 if (!isa<ConstantSDNode>(N2))
10868 auto *N2C = cast<ConstantSDNode>(N2);
10869 unsigned IdxVal = N2C->getZExtValue();
10871 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10872 // into that, and then insert the subvector back into the result.
10873 if (VT.is256BitVector() || VT.is512BitVector()) {
10874 // With a 256-bit vector, we can insert into the zero element efficiently
10875 // using a blend if we have AVX or AVX2 and the right data type.
10876 if (VT.is256BitVector() && IdxVal == 0) {
10877 // TODO: It is worthwhile to cast integer to floating point and back
10878 // and incur a domain crossing penalty if that's what we'll end up
10879 // doing anyway after extracting to a 128-bit vector.
10880 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10881 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10882 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10883 N2 = DAG.getIntPtrConstant(1, dl);
10884 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10888 // Get the desired 128-bit vector chunk.
10889 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10891 // Insert the element into the desired chunk.
10892 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10893 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10895 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10896 DAG.getConstant(IdxIn128, dl, MVT::i32));
10898 // Insert the changed part back into the bigger vector
10899 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10901 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10903 if (Subtarget->hasSSE41()) {
10904 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10906 if (VT == MVT::v8i16) {
10907 Opc = X86ISD::PINSRW;
10909 assert(VT == MVT::v16i8);
10910 Opc = X86ISD::PINSRB;
10913 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10915 if (N1.getValueType() != MVT::i32)
10916 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10917 if (N2.getValueType() != MVT::i32)
10918 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10919 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10922 if (EltVT == MVT::f32) {
10923 // Bits [7:6] of the constant are the source select. This will always be
10924 // zero here. The DAG Combiner may combine an extract_elt index into
10925 // these bits. For example (insert (extract, 3), 2) could be matched by
10926 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10927 // Bits [5:4] of the constant are the destination select. This is the
10928 // value of the incoming immediate.
10929 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10930 // combine either bitwise AND or insert of float 0.0 to set these bits.
10932 const Function *F = DAG.getMachineFunction().getFunction();
10933 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10934 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10935 // If this is an insertion of 32-bits into the low 32-bits of
10936 // a vector, we prefer to generate a blend with immediate rather
10937 // than an insertps. Blends are simpler operations in hardware and so
10938 // will always have equal or better performance than insertps.
10939 // But if optimizing for size and there's a load folding opportunity,
10940 // generate insertps because blendps does not have a 32-bit memory
10942 N2 = DAG.getIntPtrConstant(1, dl);
10943 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10944 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10946 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10947 // Create this as a scalar to vector..
10948 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10949 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10952 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10953 // PINSR* works with constant index.
10958 if (EltVT == MVT::i8)
10961 if (EltVT.getSizeInBits() == 16) {
10962 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10963 // as its second argument.
10964 if (N1.getValueType() != MVT::i32)
10965 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10966 if (N2.getValueType() != MVT::i32)
10967 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10968 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10973 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10975 MVT OpVT = Op.getSimpleValueType();
10977 // If this is a 256-bit vector result, first insert into a 128-bit
10978 // vector and then insert into the 256-bit vector.
10979 if (!OpVT.is128BitVector()) {
10980 // Insert into a 128-bit vector.
10981 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10982 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10983 OpVT.getVectorNumElements() / SizeFactor);
10985 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10987 // Insert the 128-bit vector.
10988 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10991 if (OpVT == MVT::v1i64 &&
10992 Op.getOperand(0).getValueType() == MVT::i64)
10993 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10995 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10996 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10997 return DAG.getBitcast(
10998 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11001 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11002 // a simple subregister reference or explicit instructions to grab
11003 // upper bits of a vector.
11004 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11005 SelectionDAG &DAG) {
11007 SDValue In = Op.getOperand(0);
11008 SDValue Idx = Op.getOperand(1);
11009 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11010 MVT ResVT = Op.getSimpleValueType();
11011 MVT InVT = In.getSimpleValueType();
11013 if (Subtarget->hasFp256()) {
11014 if (ResVT.is128BitVector() &&
11015 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11016 isa<ConstantSDNode>(Idx)) {
11017 return Extract128BitVector(In, IdxVal, DAG, dl);
11019 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11020 isa<ConstantSDNode>(Idx)) {
11021 return Extract256BitVector(In, IdxVal, DAG, dl);
11027 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11028 // simple superregister reference or explicit instructions to insert
11029 // the upper bits of a vector.
11030 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11031 SelectionDAG &DAG) {
11032 if (!Subtarget->hasAVX())
11036 SDValue Vec = Op.getOperand(0);
11037 SDValue SubVec = Op.getOperand(1);
11038 SDValue Idx = Op.getOperand(2);
11040 if (!isa<ConstantSDNode>(Idx))
11043 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11044 MVT OpVT = Op.getSimpleValueType();
11045 MVT SubVecVT = SubVec.getSimpleValueType();
11047 // Fold two 16-byte subvector loads into one 32-byte load:
11048 // (insert_subvector (insert_subvector undef, (load addr), 0),
11049 // (load addr + 16), Elts/2)
11051 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11052 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11053 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
11054 !Subtarget->isUnalignedMem32Slow()) {
11055 SDValue SubVec2 = Vec.getOperand(1);
11056 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
11057 if (Idx2->getZExtValue() == 0) {
11058 SDValue Ops[] = { SubVec2, SubVec };
11059 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
11066 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11067 SubVecVT.is128BitVector())
11068 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11070 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11071 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11073 if (OpVT.getVectorElementType() == MVT::i1) {
11074 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11076 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11077 SDValue Undef = DAG.getUNDEF(OpVT);
11078 unsigned NumElems = OpVT.getVectorNumElements();
11079 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11081 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11082 // Zero upper bits of the Vec
11083 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11084 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11086 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11088 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11089 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11092 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11094 // Zero upper bits of the Vec2
11095 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11096 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11097 // Zero lower bits of the Vec
11098 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11099 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11100 // Merge them together
11101 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11107 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11108 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11109 // one of the above mentioned nodes. It has to be wrapped because otherwise
11110 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11111 // be used to form addressing mode. These wrapped nodes will be selected
11114 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11115 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11117 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11118 // global base reg.
11119 unsigned char OpFlag = 0;
11120 unsigned WrapperKind = X86ISD::Wrapper;
11121 CodeModel::Model M = DAG.getTarget().getCodeModel();
11123 if (Subtarget->isPICStyleRIPRel() &&
11124 (M == CodeModel::Small || M == CodeModel::Kernel))
11125 WrapperKind = X86ISD::WrapperRIP;
11126 else if (Subtarget->isPICStyleGOT())
11127 OpFlag = X86II::MO_GOTOFF;
11128 else if (Subtarget->isPICStyleStubPIC())
11129 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11131 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11132 CP->getAlignment(),
11133 CP->getOffset(), OpFlag);
11135 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11136 // With PIC, the address is actually $g + Offset.
11138 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11139 DAG.getNode(X86ISD::GlobalBaseReg,
11140 SDLoc(), getPointerTy()),
11147 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11148 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11150 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11151 // global base reg.
11152 unsigned char OpFlag = 0;
11153 unsigned WrapperKind = X86ISD::Wrapper;
11154 CodeModel::Model M = DAG.getTarget().getCodeModel();
11156 if (Subtarget->isPICStyleRIPRel() &&
11157 (M == CodeModel::Small || M == CodeModel::Kernel))
11158 WrapperKind = X86ISD::WrapperRIP;
11159 else if (Subtarget->isPICStyleGOT())
11160 OpFlag = X86II::MO_GOTOFF;
11161 else if (Subtarget->isPICStyleStubPIC())
11162 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11164 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11167 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11169 // With PIC, the address is actually $g + Offset.
11171 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11172 DAG.getNode(X86ISD::GlobalBaseReg,
11173 SDLoc(), getPointerTy()),
11180 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11181 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11183 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11184 // global base reg.
11185 unsigned char OpFlag = 0;
11186 unsigned WrapperKind = X86ISD::Wrapper;
11187 CodeModel::Model M = DAG.getTarget().getCodeModel();
11189 if (Subtarget->isPICStyleRIPRel() &&
11190 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11191 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11192 OpFlag = X86II::MO_GOTPCREL;
11193 WrapperKind = X86ISD::WrapperRIP;
11194 } else if (Subtarget->isPICStyleGOT()) {
11195 OpFlag = X86II::MO_GOT;
11196 } else if (Subtarget->isPICStyleStubPIC()) {
11197 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11198 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11199 OpFlag = X86II::MO_DARWIN_NONLAZY;
11202 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11205 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11207 // With PIC, the address is actually $g + Offset.
11208 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11209 !Subtarget->is64Bit()) {
11210 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11211 DAG.getNode(X86ISD::GlobalBaseReg,
11212 SDLoc(), getPointerTy()),
11216 // For symbols that require a load from a stub to get the address, emit the
11218 if (isGlobalStubReference(OpFlag))
11219 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11220 MachinePointerInfo::getGOT(), false, false, false, 0);
11226 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11227 // Create the TargetBlockAddressAddress node.
11228 unsigned char OpFlags =
11229 Subtarget->ClassifyBlockAddressReference();
11230 CodeModel::Model M = DAG.getTarget().getCodeModel();
11231 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11232 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11234 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11237 if (Subtarget->isPICStyleRIPRel() &&
11238 (M == CodeModel::Small || M == CodeModel::Kernel))
11239 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11241 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11243 // With PIC, the address is actually $g + Offset.
11244 if (isGlobalRelativeToPICBase(OpFlags)) {
11245 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11246 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11254 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11255 int64_t Offset, SelectionDAG &DAG) const {
11256 // Create the TargetGlobalAddress node, folding in the constant
11257 // offset if it is legal.
11258 unsigned char OpFlags =
11259 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11260 CodeModel::Model M = DAG.getTarget().getCodeModel();
11262 if (OpFlags == X86II::MO_NO_FLAG &&
11263 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11264 // A direct static reference to a global.
11265 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11268 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11271 if (Subtarget->isPICStyleRIPRel() &&
11272 (M == CodeModel::Small || M == CodeModel::Kernel))
11273 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11275 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11277 // With PIC, the address is actually $g + Offset.
11278 if (isGlobalRelativeToPICBase(OpFlags)) {
11279 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11280 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11284 // For globals that require a load from a stub to get the address, emit the
11286 if (isGlobalStubReference(OpFlags))
11287 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11288 MachinePointerInfo::getGOT(), false, false, false, 0);
11290 // If there was a non-zero offset that we didn't fold, create an explicit
11291 // addition for it.
11293 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11294 DAG.getConstant(Offset, dl, getPointerTy()));
11300 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11301 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11302 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11303 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11307 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11308 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11309 unsigned char OperandFlags, bool LocalDynamic = false) {
11310 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11311 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11313 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11314 GA->getValueType(0),
11318 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11322 SDValue Ops[] = { Chain, TGA, *InFlag };
11323 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11325 SDValue Ops[] = { Chain, TGA };
11326 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11329 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11330 MFI->setAdjustsStack(true);
11331 MFI->setHasCalls(true);
11333 SDValue Flag = Chain.getValue(1);
11334 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11337 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11339 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11342 SDLoc dl(GA); // ? function entry point might be better
11343 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11344 DAG.getNode(X86ISD::GlobalBaseReg,
11345 SDLoc(), PtrVT), InFlag);
11346 InFlag = Chain.getValue(1);
11348 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11351 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11353 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11355 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11356 X86::RAX, X86II::MO_TLSGD);
11359 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11365 // Get the start address of the TLS block for this module.
11366 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11367 .getInfo<X86MachineFunctionInfo>();
11368 MFI->incNumLocalDynamicTLSAccesses();
11372 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11373 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11376 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11377 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11378 InFlag = Chain.getValue(1);
11379 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11380 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11383 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11387 unsigned char OperandFlags = X86II::MO_DTPOFF;
11388 unsigned WrapperKind = X86ISD::Wrapper;
11389 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11390 GA->getValueType(0),
11391 GA->getOffset(), OperandFlags);
11392 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11394 // Add x@dtpoff with the base.
11395 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11398 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11399 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11400 const EVT PtrVT, TLSModel::Model model,
11401 bool is64Bit, bool isPIC) {
11404 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11405 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11406 is64Bit ? 257 : 256));
11408 SDValue ThreadPointer =
11409 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11410 MachinePointerInfo(Ptr), false, false, false, 0);
11412 unsigned char OperandFlags = 0;
11413 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11415 unsigned WrapperKind = X86ISD::Wrapper;
11416 if (model == TLSModel::LocalExec) {
11417 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11418 } else if (model == TLSModel::InitialExec) {
11420 OperandFlags = X86II::MO_GOTTPOFF;
11421 WrapperKind = X86ISD::WrapperRIP;
11423 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11426 llvm_unreachable("Unexpected model");
11429 // emit "addl x@ntpoff,%eax" (local exec)
11430 // or "addl x@indntpoff,%eax" (initial exec)
11431 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11433 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11434 GA->getOffset(), OperandFlags);
11435 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11437 if (model == TLSModel::InitialExec) {
11438 if (isPIC && !is64Bit) {
11439 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11440 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11444 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11445 MachinePointerInfo::getGOT(), false, false, false, 0);
11448 // The address of the thread local variable is the add of the thread
11449 // pointer with the offset of the variable.
11450 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11454 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11456 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11457 const GlobalValue *GV = GA->getGlobal();
11459 if (Subtarget->isTargetELF()) {
11460 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11462 case TLSModel::GeneralDynamic:
11463 if (Subtarget->is64Bit())
11464 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11465 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11466 case TLSModel::LocalDynamic:
11467 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11468 Subtarget->is64Bit());
11469 case TLSModel::InitialExec:
11470 case TLSModel::LocalExec:
11471 return LowerToTLSExecModel(
11472 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11473 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11475 llvm_unreachable("Unknown TLS model.");
11478 if (Subtarget->isTargetDarwin()) {
11479 // Darwin only has one model of TLS. Lower to that.
11480 unsigned char OpFlag = 0;
11481 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11482 X86ISD::WrapperRIP : X86ISD::Wrapper;
11484 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11485 // global base reg.
11486 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11487 !Subtarget->is64Bit();
11489 OpFlag = X86II::MO_TLVP_PIC_BASE;
11491 OpFlag = X86II::MO_TLVP;
11493 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11494 GA->getValueType(0),
11495 GA->getOffset(), OpFlag);
11496 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11498 // With PIC32, the address is actually $g + Offset.
11500 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11501 DAG.getNode(X86ISD::GlobalBaseReg,
11502 SDLoc(), getPointerTy()),
11505 // Lowering the machine isd will make sure everything is in the right
11507 SDValue Chain = DAG.getEntryNode();
11508 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11509 SDValue Args[] = { Chain, Offset };
11510 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11512 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11513 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11514 MFI->setAdjustsStack(true);
11516 // And our return value (tls address) is in the standard call return value
11518 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11519 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11520 Chain.getValue(1));
11523 if (Subtarget->isTargetKnownWindowsMSVC() ||
11524 Subtarget->isTargetWindowsGNU()) {
11525 // Just use the implicit TLS architecture
11526 // Need to generate someting similar to:
11527 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11529 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11530 // mov rcx, qword [rdx+rcx*8]
11531 // mov eax, .tls$:tlsvar
11532 // [rax+rcx] contains the address
11533 // Windows 64bit: gs:0x58
11534 // Windows 32bit: fs:__tls_array
11537 SDValue Chain = DAG.getEntryNode();
11539 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11540 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11541 // use its literal value of 0x2C.
11542 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11543 ? Type::getInt8PtrTy(*DAG.getContext(),
11545 : Type::getInt32PtrTy(*DAG.getContext(),
11549 Subtarget->is64Bit()
11550 ? DAG.getIntPtrConstant(0x58, dl)
11551 : (Subtarget->isTargetWindowsGNU()
11552 ? DAG.getIntPtrConstant(0x2C, dl)
11553 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11555 SDValue ThreadPointer =
11556 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11557 MachinePointerInfo(Ptr), false, false, false, 0);
11560 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11561 res = ThreadPointer;
11563 // Load the _tls_index variable
11564 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11565 if (Subtarget->is64Bit())
11566 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11567 MachinePointerInfo(), MVT::i32, false, false,
11570 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11571 false, false, false, 0);
11573 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11575 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11577 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11580 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11581 false, false, false, 0);
11583 // Get the offset of start of .tls section
11584 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11585 GA->getValueType(0),
11586 GA->getOffset(), X86II::MO_SECREL);
11587 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11589 // The address of the thread local variable is the add of the thread
11590 // pointer with the offset of the variable.
11591 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11594 llvm_unreachable("TLS not implemented for this target.");
11597 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11598 /// and take a 2 x i32 value to shift plus a shift amount.
11599 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11600 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11601 MVT VT = Op.getSimpleValueType();
11602 unsigned VTBits = VT.getSizeInBits();
11604 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11605 SDValue ShOpLo = Op.getOperand(0);
11606 SDValue ShOpHi = Op.getOperand(1);
11607 SDValue ShAmt = Op.getOperand(2);
11608 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11609 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11611 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11612 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11613 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11614 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11615 : DAG.getConstant(0, dl, VT);
11617 SDValue Tmp2, Tmp3;
11618 if (Op.getOpcode() == ISD::SHL_PARTS) {
11619 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11620 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11622 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11623 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11626 // If the shift amount is larger or equal than the width of a part we can't
11627 // rely on the results of shld/shrd. Insert a test and select the appropriate
11628 // values for large shift amounts.
11629 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11630 DAG.getConstant(VTBits, dl, MVT::i8));
11631 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11632 AndNode, DAG.getConstant(0, dl, MVT::i8));
11635 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11636 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11637 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11639 if (Op.getOpcode() == ISD::SHL_PARTS) {
11640 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11641 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11643 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11644 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11647 SDValue Ops[2] = { Lo, Hi };
11648 return DAG.getMergeValues(Ops, dl);
11651 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11652 SelectionDAG &DAG) const {
11653 SDValue Src = Op.getOperand(0);
11654 MVT SrcVT = Src.getSimpleValueType();
11655 MVT VT = Op.getSimpleValueType();
11658 if (SrcVT.isVector()) {
11659 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11660 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11661 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11662 DAG.getUNDEF(SrcVT)));
11664 if (SrcVT.getVectorElementType() == MVT::i1) {
11665 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11666 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11667 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11672 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11673 "Unknown SINT_TO_FP to lower!");
11675 // These are really Legal; return the operand so the caller accepts it as
11677 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11679 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11680 Subtarget->is64Bit()) {
11684 unsigned Size = SrcVT.getSizeInBits()/8;
11685 MachineFunction &MF = DAG.getMachineFunction();
11686 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11687 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11688 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11690 MachinePointerInfo::getFixedStack(SSFI),
11692 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11695 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11697 SelectionDAG &DAG) const {
11701 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11703 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11705 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11707 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11709 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11710 MachineMemOperand *MMO;
11712 int SSFI = FI->getIndex();
11714 DAG.getMachineFunction()
11715 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11716 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11718 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11719 StackSlot = StackSlot.getOperand(1);
11721 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11722 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11724 Tys, Ops, SrcVT, MMO);
11727 Chain = Result.getValue(1);
11728 SDValue InFlag = Result.getValue(2);
11730 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11731 // shouldn't be necessary except that RFP cannot be live across
11732 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11733 MachineFunction &MF = DAG.getMachineFunction();
11734 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11735 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11736 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11737 Tys = DAG.getVTList(MVT::Other);
11739 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11741 MachineMemOperand *MMO =
11742 DAG.getMachineFunction()
11743 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11744 MachineMemOperand::MOStore, SSFISize, SSFISize);
11746 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11747 Ops, Op.getValueType(), MMO);
11748 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11749 MachinePointerInfo::getFixedStack(SSFI),
11750 false, false, false, 0);
11756 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11757 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11758 SelectionDAG &DAG) const {
11759 // This algorithm is not obvious. Here it is what we're trying to output:
11762 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11763 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11765 haddpd %xmm0, %xmm0
11767 pshufd $0x4e, %xmm0, %xmm1
11773 LLVMContext *Context = DAG.getContext();
11775 // Build some magic constants.
11776 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11777 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11778 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11780 SmallVector<Constant*,2> CV1;
11782 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11783 APInt(64, 0x4330000000000000ULL))));
11785 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11786 APInt(64, 0x4530000000000000ULL))));
11787 Constant *C1 = ConstantVector::get(CV1);
11788 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11790 // Load the 64-bit value into an XMM register.
11791 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11793 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11794 MachinePointerInfo::getConstantPool(),
11795 false, false, false, 16);
11797 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11799 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11800 MachinePointerInfo::getConstantPool(),
11801 false, false, false, 16);
11802 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11803 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11806 if (Subtarget->hasSSE3()) {
11807 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11808 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11810 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11811 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11813 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11814 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11817 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11818 DAG.getIntPtrConstant(0, dl));
11821 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11822 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11823 SelectionDAG &DAG) const {
11825 // FP constant to bias correct the final result.
11826 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11829 // Load the 32-bit value into an XMM register.
11830 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11833 // Zero out the upper parts of the register.
11834 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11836 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11837 DAG.getBitcast(MVT::v2f64, Load),
11838 DAG.getIntPtrConstant(0, dl));
11840 // Or the load with the bias.
11841 SDValue Or = DAG.getNode(
11842 ISD::OR, dl, MVT::v2i64,
11843 DAG.getBitcast(MVT::v2i64,
11844 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11845 DAG.getBitcast(MVT::v2i64,
11846 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11848 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11849 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11851 // Subtract the bias.
11852 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11854 // Handle final rounding.
11855 EVT DestVT = Op.getValueType();
11857 if (DestVT.bitsLT(MVT::f64))
11858 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11859 DAG.getIntPtrConstant(0, dl));
11860 if (DestVT.bitsGT(MVT::f64))
11861 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11863 // Handle final rounding.
11867 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11868 const X86Subtarget &Subtarget) {
11869 // The algorithm is the following:
11870 // #ifdef __SSE4_1__
11871 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11872 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11873 // (uint4) 0x53000000, 0xaa);
11875 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11876 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11878 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11879 // return (float4) lo + fhi;
11882 SDValue V = Op->getOperand(0);
11883 EVT VecIntVT = V.getValueType();
11884 bool Is128 = VecIntVT == MVT::v4i32;
11885 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11886 // If we convert to something else than the supported type, e.g., to v4f64,
11888 if (VecFloatVT != Op->getValueType(0))
11891 unsigned NumElts = VecIntVT.getVectorNumElements();
11892 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11893 "Unsupported custom type");
11894 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11896 // In the #idef/#else code, we have in common:
11897 // - The vector of constants:
11903 // Create the splat vector for 0x4b000000.
11904 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11905 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11906 CstLow, CstLow, CstLow, CstLow};
11907 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11908 makeArrayRef(&CstLowArray[0], NumElts));
11909 // Create the splat vector for 0x53000000.
11910 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11911 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11912 CstHigh, CstHigh, CstHigh, CstHigh};
11913 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11914 makeArrayRef(&CstHighArray[0], NumElts));
11916 // Create the right shift.
11917 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11918 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11919 CstShift, CstShift, CstShift, CstShift};
11920 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11921 makeArrayRef(&CstShiftArray[0], NumElts));
11922 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11925 if (Subtarget.hasSSE41()) {
11926 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11927 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11928 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
11929 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
11930 // Low will be bitcasted right away, so do not bother bitcasting back to its
11932 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11933 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11934 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11935 // (uint4) 0x53000000, 0xaa);
11936 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
11937 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
11938 // High will be bitcasted right away, so do not bother bitcasting back to
11939 // its original type.
11940 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11941 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11943 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11944 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11945 CstMask, CstMask, CstMask);
11946 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11947 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11948 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11950 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11951 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11954 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11955 SDValue CstFAdd = DAG.getConstantFP(
11956 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11957 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11958 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11959 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11960 makeArrayRef(&CstFAddArray[0], NumElts));
11962 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11963 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
11965 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11966 // return (float4) lo + fhi;
11967 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
11968 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11971 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11972 SelectionDAG &DAG) const {
11973 SDValue N0 = Op.getOperand(0);
11974 MVT SVT = N0.getSimpleValueType();
11977 switch (SVT.SimpleTy) {
11979 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11984 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11985 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11986 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11990 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11993 if (Subtarget->hasAVX512())
11994 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11995 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11997 llvm_unreachable(nullptr);
12000 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12001 SelectionDAG &DAG) const {
12002 SDValue N0 = Op.getOperand(0);
12005 if (Op.getValueType().isVector())
12006 return lowerUINT_TO_FP_vec(Op, DAG);
12008 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12009 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12010 // the optimization here.
12011 if (DAG.SignBitIsZero(N0))
12012 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12014 MVT SrcVT = N0.getSimpleValueType();
12015 MVT DstVT = Op.getSimpleValueType();
12016 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12017 return LowerUINT_TO_FP_i64(Op, DAG);
12018 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12019 return LowerUINT_TO_FP_i32(Op, DAG);
12020 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12023 // Make a 64-bit buffer, and use it to build an FILD.
12024 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12025 if (SrcVT == MVT::i32) {
12026 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
12027 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12028 getPointerTy(), StackSlot, WordOff);
12029 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12030 StackSlot, MachinePointerInfo(),
12032 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12033 OffsetSlot, MachinePointerInfo(),
12035 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12039 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12040 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12041 StackSlot, MachinePointerInfo(),
12043 // For i64 source, we need to add the appropriate power of 2 if the input
12044 // was negative. This is the same as the optimization in
12045 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12046 // we must be careful to do the computation in x87 extended precision, not
12047 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12048 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12049 MachineMemOperand *MMO =
12050 DAG.getMachineFunction()
12051 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12052 MachineMemOperand::MOLoad, 8, 8);
12054 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12055 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12056 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12059 APInt FF(32, 0x5F800000ULL);
12061 // Check whether the sign bit is set.
12062 SDValue SignSet = DAG.getSetCC(dl,
12063 getSetCCResultType(*DAG.getContext(), MVT::i64),
12065 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12067 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12068 SDValue FudgePtr = DAG.getConstantPool(
12069 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12072 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12073 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12074 SDValue Four = DAG.getIntPtrConstant(4, dl);
12075 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12077 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12079 // Load the value out, extending it from f32 to f80.
12080 // FIXME: Avoid the extend by constructing the right constant pool?
12081 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12082 FudgePtr, MachinePointerInfo::getConstantPool(),
12083 MVT::f32, false, false, false, 4);
12084 // Extend everything to 80 bits to force it to be done on x87.
12085 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12086 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12087 DAG.getIntPtrConstant(0, dl));
12090 std::pair<SDValue,SDValue>
12091 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12092 bool IsSigned, bool IsReplace) const {
12095 EVT DstTy = Op.getValueType();
12097 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12098 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12102 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12103 DstTy.getSimpleVT() >= MVT::i16 &&
12104 "Unknown FP_TO_INT to lower!");
12106 // These are really Legal.
12107 if (DstTy == MVT::i32 &&
12108 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12109 return std::make_pair(SDValue(), SDValue());
12110 if (Subtarget->is64Bit() &&
12111 DstTy == MVT::i64 &&
12112 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12113 return std::make_pair(SDValue(), SDValue());
12115 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12116 // stack slot, or into the FTOL runtime function.
12117 MachineFunction &MF = DAG.getMachineFunction();
12118 unsigned MemSize = DstTy.getSizeInBits()/8;
12119 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12120 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12123 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12124 Opc = X86ISD::WIN_FTOL;
12126 switch (DstTy.getSimpleVT().SimpleTy) {
12127 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12128 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12129 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12130 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12133 SDValue Chain = DAG.getEntryNode();
12134 SDValue Value = Op.getOperand(0);
12135 EVT TheVT = Op.getOperand(0).getValueType();
12136 // FIXME This causes a redundant load/store if the SSE-class value is already
12137 // in memory, such as if it is on the callstack.
12138 if (isScalarFPTypeInSSEReg(TheVT)) {
12139 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12140 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12141 MachinePointerInfo::getFixedStack(SSFI),
12143 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12145 Chain, StackSlot, DAG.getValueType(TheVT)
12148 MachineMemOperand *MMO =
12149 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12150 MachineMemOperand::MOLoad, MemSize, MemSize);
12151 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12152 Chain = Value.getValue(1);
12153 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12154 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12157 MachineMemOperand *MMO =
12158 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12159 MachineMemOperand::MOStore, MemSize, MemSize);
12161 if (Opc != X86ISD::WIN_FTOL) {
12162 // Build the FP_TO_INT*_IN_MEM
12163 SDValue Ops[] = { Chain, Value, StackSlot };
12164 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12166 return std::make_pair(FIST, StackSlot);
12168 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12169 DAG.getVTList(MVT::Other, MVT::Glue),
12171 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12172 MVT::i32, ftol.getValue(1));
12173 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12174 MVT::i32, eax.getValue(2));
12175 SDValue Ops[] = { eax, edx };
12176 SDValue pair = IsReplace
12177 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12178 : DAG.getMergeValues(Ops, DL);
12179 return std::make_pair(pair, SDValue());
12183 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12184 const X86Subtarget *Subtarget) {
12185 MVT VT = Op->getSimpleValueType(0);
12186 SDValue In = Op->getOperand(0);
12187 MVT InVT = In.getSimpleValueType();
12190 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12191 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12193 // Optimize vectors in AVX mode:
12196 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12197 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12198 // Concat upper and lower parts.
12201 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12202 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12203 // Concat upper and lower parts.
12206 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12207 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12208 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12211 if (Subtarget->hasInt256())
12212 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12214 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12215 SDValue Undef = DAG.getUNDEF(InVT);
12216 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12217 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12218 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12220 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12221 VT.getVectorNumElements()/2);
12223 OpLo = DAG.getBitcast(HVT, OpLo);
12224 OpHi = DAG.getBitcast(HVT, OpHi);
12226 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12229 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12230 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12231 MVT VT = Op->getSimpleValueType(0);
12232 SDValue In = Op->getOperand(0);
12233 MVT InVT = In.getSimpleValueType();
12235 unsigned int NumElts = VT.getVectorNumElements();
12236 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12239 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12240 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12242 assert(InVT.getVectorElementType() == MVT::i1);
12243 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12245 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12247 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12249 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12250 if (VT.is512BitVector())
12252 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12255 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12256 SelectionDAG &DAG) {
12257 if (Subtarget->hasFp256()) {
12258 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12266 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12267 SelectionDAG &DAG) {
12269 MVT VT = Op.getSimpleValueType();
12270 SDValue In = Op.getOperand(0);
12271 MVT SVT = In.getSimpleValueType();
12273 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12274 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12276 if (Subtarget->hasFp256()) {
12277 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12282 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12283 VT.getVectorNumElements() != SVT.getVectorNumElements());
12287 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12289 MVT VT = Op.getSimpleValueType();
12290 SDValue In = Op.getOperand(0);
12291 MVT InVT = In.getSimpleValueType();
12293 if (VT == MVT::i1) {
12294 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12295 "Invalid scalar TRUNCATE operation");
12296 if (InVT.getSizeInBits() >= 32)
12298 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12299 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12301 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12302 "Invalid TRUNCATE operation");
12304 // move vector to mask - truncate solution for SKX
12305 if (VT.getVectorElementType() == MVT::i1) {
12306 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12307 Subtarget->hasBWI())
12308 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12309 if ((InVT.is256BitVector() || InVT.is128BitVector())
12310 && InVT.getScalarSizeInBits() <= 16 &&
12311 Subtarget->hasBWI() && Subtarget->hasVLX())
12312 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12313 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12314 Subtarget->hasDQI())
12315 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12316 if ((InVT.is256BitVector() || InVT.is128BitVector())
12317 && InVT.getScalarSizeInBits() >= 32 &&
12318 Subtarget->hasDQI() && Subtarget->hasVLX())
12319 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12321 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12322 if (VT.getVectorElementType().getSizeInBits() >=8)
12323 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12325 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12326 unsigned NumElts = InVT.getVectorNumElements();
12327 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12328 if (InVT.getSizeInBits() < 512) {
12329 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12330 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12335 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12336 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12337 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12340 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12341 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12342 if (Subtarget->hasInt256()) {
12343 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12344 In = DAG.getBitcast(MVT::v8i32, In);
12345 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12347 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12348 DAG.getIntPtrConstant(0, DL));
12351 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12352 DAG.getIntPtrConstant(0, DL));
12353 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12354 DAG.getIntPtrConstant(2, DL));
12355 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12356 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12357 static const int ShufMask[] = {0, 2, 4, 6};
12358 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12361 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12362 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12363 if (Subtarget->hasInt256()) {
12364 In = DAG.getBitcast(MVT::v32i8, In);
12366 SmallVector<SDValue,32> pshufbMask;
12367 for (unsigned i = 0; i < 2; ++i) {
12368 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12369 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12370 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12371 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12372 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12373 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12374 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12375 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12376 for (unsigned j = 0; j < 8; ++j)
12377 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12379 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12380 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12381 In = DAG.getBitcast(MVT::v4i64, In);
12383 static const int ShufMask[] = {0, 2, -1, -1};
12384 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12386 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12387 DAG.getIntPtrConstant(0, DL));
12388 return DAG.getBitcast(VT, In);
12391 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12392 DAG.getIntPtrConstant(0, DL));
12394 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12395 DAG.getIntPtrConstant(4, DL));
12397 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12398 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12400 // The PSHUFB mask:
12401 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12402 -1, -1, -1, -1, -1, -1, -1, -1};
12404 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12405 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12406 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12408 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12409 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12411 // The MOVLHPS Mask:
12412 static const int ShufMask2[] = {0, 1, 4, 5};
12413 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12414 return DAG.getBitcast(MVT::v8i16, res);
12417 // Handle truncation of V256 to V128 using shuffles.
12418 if (!VT.is128BitVector() || !InVT.is256BitVector())
12421 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12423 unsigned NumElems = VT.getVectorNumElements();
12424 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12426 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12427 // Prepare truncation shuffle mask
12428 for (unsigned i = 0; i != NumElems; ++i)
12429 MaskVec[i] = i * 2;
12430 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12431 DAG.getUNDEF(NVT), &MaskVec[0]);
12432 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12433 DAG.getIntPtrConstant(0, DL));
12436 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12437 SelectionDAG &DAG) const {
12438 assert(!Op.getSimpleValueType().isVector());
12440 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12441 /*IsSigned=*/ true, /*IsReplace=*/ false);
12442 SDValue FIST = Vals.first, StackSlot = Vals.second;
12443 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12444 if (!FIST.getNode()) return Op;
12446 if (StackSlot.getNode())
12447 // Load the result.
12448 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12449 FIST, StackSlot, MachinePointerInfo(),
12450 false, false, false, 0);
12452 // The node is the result.
12456 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12457 SelectionDAG &DAG) const {
12458 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12459 /*IsSigned=*/ false, /*IsReplace=*/ false);
12460 SDValue FIST = Vals.first, StackSlot = Vals.second;
12461 assert(FIST.getNode() && "Unexpected failure");
12463 if (StackSlot.getNode())
12464 // Load the result.
12465 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12466 FIST, StackSlot, MachinePointerInfo(),
12467 false, false, false, 0);
12469 // The node is the result.
12473 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12475 MVT VT = Op.getSimpleValueType();
12476 SDValue In = Op.getOperand(0);
12477 MVT SVT = In.getSimpleValueType();
12479 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12481 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12482 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12483 In, DAG.getUNDEF(SVT)));
12486 /// The only differences between FABS and FNEG are the mask and the logic op.
12487 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12488 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12489 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12490 "Wrong opcode for lowering FABS or FNEG.");
12492 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12494 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12495 // into an FNABS. We'll lower the FABS after that if it is still in use.
12497 for (SDNode *User : Op->uses())
12498 if (User->getOpcode() == ISD::FNEG)
12501 SDValue Op0 = Op.getOperand(0);
12502 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12505 MVT VT = Op.getSimpleValueType();
12506 // Assume scalar op for initialization; update for vector if needed.
12507 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12508 // generate a 16-byte vector constant and logic op even for the scalar case.
12509 // Using a 16-byte mask allows folding the load of the mask with
12510 // the logic op, so it can save (~4 bytes) on code size.
12512 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12513 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12514 // decide if we should generate a 16-byte constant mask when we only need 4 or
12515 // 8 bytes for the scalar case.
12516 if (VT.isVector()) {
12517 EltVT = VT.getVectorElementType();
12518 NumElts = VT.getVectorNumElements();
12521 unsigned EltBits = EltVT.getSizeInBits();
12522 LLVMContext *Context = DAG.getContext();
12523 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12525 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12526 Constant *C = ConstantInt::get(*Context, MaskElt);
12527 C = ConstantVector::getSplat(NumElts, C);
12528 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12529 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12530 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12531 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12532 MachinePointerInfo::getConstantPool(),
12533 false, false, false, Alignment);
12535 if (VT.isVector()) {
12536 // For a vector, cast operands to a vector type, perform the logic op,
12537 // and cast the result back to the original value type.
12538 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12539 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12540 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12541 : DAG.getBitcast(VecVT, Op0);
12542 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12543 return DAG.getBitcast(VT,
12544 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12547 // If not vector, then scalar.
12548 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12549 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12550 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12553 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12554 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12555 LLVMContext *Context = DAG.getContext();
12556 SDValue Op0 = Op.getOperand(0);
12557 SDValue Op1 = Op.getOperand(1);
12559 MVT VT = Op.getSimpleValueType();
12560 MVT SrcVT = Op1.getSimpleValueType();
12562 // If second operand is smaller, extend it first.
12563 if (SrcVT.bitsLT(VT)) {
12564 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12567 // And if it is bigger, shrink it first.
12568 if (SrcVT.bitsGT(VT)) {
12569 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12573 // At this point the operands and the result should have the same
12574 // type, and that won't be f80 since that is not custom lowered.
12576 const fltSemantics &Sem =
12577 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12578 const unsigned SizeInBits = VT.getSizeInBits();
12580 SmallVector<Constant *, 4> CV(
12581 VT == MVT::f64 ? 2 : 4,
12582 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12584 // First, clear all bits but the sign bit from the second operand (sign).
12585 CV[0] = ConstantFP::get(*Context,
12586 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12587 Constant *C = ConstantVector::get(CV);
12588 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12589 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12590 MachinePointerInfo::getConstantPool(),
12591 false, false, false, 16);
12592 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12594 // Next, clear the sign bit from the first operand (magnitude).
12595 // If it's a constant, we can clear it here.
12596 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12597 APFloat APF = Op0CN->getValueAPF();
12598 // If the magnitude is a positive zero, the sign bit alone is enough.
12599 if (APF.isPosZero())
12602 CV[0] = ConstantFP::get(*Context, APF);
12604 CV[0] = ConstantFP::get(
12606 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12608 C = ConstantVector::get(CV);
12609 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12610 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12611 MachinePointerInfo::getConstantPool(),
12612 false, false, false, 16);
12613 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12614 if (!isa<ConstantFPSDNode>(Op0))
12615 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12617 // OR the magnitude value with the sign bit.
12618 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12621 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12622 SDValue N0 = Op.getOperand(0);
12624 MVT VT = Op.getSimpleValueType();
12626 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12627 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12628 DAG.getConstant(1, dl, VT));
12629 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12632 // Check whether an OR'd tree is PTEST-able.
12633 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12634 SelectionDAG &DAG) {
12635 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12637 if (!Subtarget->hasSSE41())
12640 if (!Op->hasOneUse())
12643 SDNode *N = Op.getNode();
12646 SmallVector<SDValue, 8> Opnds;
12647 DenseMap<SDValue, unsigned> VecInMap;
12648 SmallVector<SDValue, 8> VecIns;
12649 EVT VT = MVT::Other;
12651 // Recognize a special case where a vector is casted into wide integer to
12653 Opnds.push_back(N->getOperand(0));
12654 Opnds.push_back(N->getOperand(1));
12656 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12657 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12658 // BFS traverse all OR'd operands.
12659 if (I->getOpcode() == ISD::OR) {
12660 Opnds.push_back(I->getOperand(0));
12661 Opnds.push_back(I->getOperand(1));
12662 // Re-evaluate the number of nodes to be traversed.
12663 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12667 // Quit if a non-EXTRACT_VECTOR_ELT
12668 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12671 // Quit if without a constant index.
12672 SDValue Idx = I->getOperand(1);
12673 if (!isa<ConstantSDNode>(Idx))
12676 SDValue ExtractedFromVec = I->getOperand(0);
12677 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12678 if (M == VecInMap.end()) {
12679 VT = ExtractedFromVec.getValueType();
12680 // Quit if not 128/256-bit vector.
12681 if (!VT.is128BitVector() && !VT.is256BitVector())
12683 // Quit if not the same type.
12684 if (VecInMap.begin() != VecInMap.end() &&
12685 VT != VecInMap.begin()->first.getValueType())
12687 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12688 VecIns.push_back(ExtractedFromVec);
12690 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12693 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12694 "Not extracted from 128-/256-bit vector.");
12696 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12698 for (DenseMap<SDValue, unsigned>::const_iterator
12699 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12700 // Quit if not all elements are used.
12701 if (I->second != FullMask)
12705 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12707 // Cast all vectors into TestVT for PTEST.
12708 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12709 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12711 // If more than one full vectors are evaluated, OR them first before PTEST.
12712 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12713 // Each iteration will OR 2 nodes and append the result until there is only
12714 // 1 node left, i.e. the final OR'd value of all vectors.
12715 SDValue LHS = VecIns[Slot];
12716 SDValue RHS = VecIns[Slot + 1];
12717 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12720 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12721 VecIns.back(), VecIns.back());
12724 /// \brief return true if \c Op has a use that doesn't just read flags.
12725 static bool hasNonFlagsUse(SDValue Op) {
12726 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12728 SDNode *User = *UI;
12729 unsigned UOpNo = UI.getOperandNo();
12730 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12731 // Look pass truncate.
12732 UOpNo = User->use_begin().getOperandNo();
12733 User = *User->use_begin();
12736 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12737 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12743 /// Emit nodes that will be selected as "test Op0,Op0", or something
12745 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12746 SelectionDAG &DAG) const {
12747 if (Op.getValueType() == MVT::i1) {
12748 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12749 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12750 DAG.getConstant(0, dl, MVT::i8));
12752 // CF and OF aren't always set the way we want. Determine which
12753 // of these we need.
12754 bool NeedCF = false;
12755 bool NeedOF = false;
12758 case X86::COND_A: case X86::COND_AE:
12759 case X86::COND_B: case X86::COND_BE:
12762 case X86::COND_G: case X86::COND_GE:
12763 case X86::COND_L: case X86::COND_LE:
12764 case X86::COND_O: case X86::COND_NO: {
12765 // Check if we really need to set the
12766 // Overflow flag. If NoSignedWrap is present
12767 // that is not actually needed.
12768 switch (Op->getOpcode()) {
12773 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12774 if (BinNode->Flags.hasNoSignedWrap())
12784 // See if we can use the EFLAGS value from the operand instead of
12785 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12786 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12787 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12788 // Emit a CMP with 0, which is the TEST pattern.
12789 //if (Op.getValueType() == MVT::i1)
12790 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12791 // DAG.getConstant(0, MVT::i1));
12792 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12793 DAG.getConstant(0, dl, Op.getValueType()));
12795 unsigned Opcode = 0;
12796 unsigned NumOperands = 0;
12798 // Truncate operations may prevent the merge of the SETCC instruction
12799 // and the arithmetic instruction before it. Attempt to truncate the operands
12800 // of the arithmetic instruction and use a reduced bit-width instruction.
12801 bool NeedTruncation = false;
12802 SDValue ArithOp = Op;
12803 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12804 SDValue Arith = Op->getOperand(0);
12805 // Both the trunc and the arithmetic op need to have one user each.
12806 if (Arith->hasOneUse())
12807 switch (Arith.getOpcode()) {
12814 NeedTruncation = true;
12820 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12821 // which may be the result of a CAST. We use the variable 'Op', which is the
12822 // non-casted variable when we check for possible users.
12823 switch (ArithOp.getOpcode()) {
12825 // Due to an isel shortcoming, be conservative if this add is likely to be
12826 // selected as part of a load-modify-store instruction. When the root node
12827 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12828 // uses of other nodes in the match, such as the ADD in this case. This
12829 // leads to the ADD being left around and reselected, with the result being
12830 // two adds in the output. Alas, even if none our users are stores, that
12831 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12832 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12833 // climbing the DAG back to the root, and it doesn't seem to be worth the
12835 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12836 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12837 if (UI->getOpcode() != ISD::CopyToReg &&
12838 UI->getOpcode() != ISD::SETCC &&
12839 UI->getOpcode() != ISD::STORE)
12842 if (ConstantSDNode *C =
12843 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12844 // An add of one will be selected as an INC.
12845 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12846 Opcode = X86ISD::INC;
12851 // An add of negative one (subtract of one) will be selected as a DEC.
12852 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12853 Opcode = X86ISD::DEC;
12859 // Otherwise use a regular EFLAGS-setting add.
12860 Opcode = X86ISD::ADD;
12865 // If we have a constant logical shift that's only used in a comparison
12866 // against zero turn it into an equivalent AND. This allows turning it into
12867 // a TEST instruction later.
12868 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12869 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12870 EVT VT = Op.getValueType();
12871 unsigned BitWidth = VT.getSizeInBits();
12872 unsigned ShAmt = Op->getConstantOperandVal(1);
12873 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12875 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12876 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12877 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12878 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12880 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12881 DAG.getConstant(Mask, dl, VT));
12882 DAG.ReplaceAllUsesWith(Op, New);
12888 // If the primary and result isn't used, don't bother using X86ISD::AND,
12889 // because a TEST instruction will be better.
12890 if (!hasNonFlagsUse(Op))
12896 // Due to the ISEL shortcoming noted above, be conservative if this op is
12897 // likely to be selected as part of a load-modify-store instruction.
12898 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12899 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12900 if (UI->getOpcode() == ISD::STORE)
12903 // Otherwise use a regular EFLAGS-setting instruction.
12904 switch (ArithOp.getOpcode()) {
12905 default: llvm_unreachable("unexpected operator!");
12906 case ISD::SUB: Opcode = X86ISD::SUB; break;
12907 case ISD::XOR: Opcode = X86ISD::XOR; break;
12908 case ISD::AND: Opcode = X86ISD::AND; break;
12910 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12911 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12912 if (EFLAGS.getNode())
12915 Opcode = X86ISD::OR;
12929 return SDValue(Op.getNode(), 1);
12935 // If we found that truncation is beneficial, perform the truncation and
12937 if (NeedTruncation) {
12938 EVT VT = Op.getValueType();
12939 SDValue WideVal = Op->getOperand(0);
12940 EVT WideVT = WideVal.getValueType();
12941 unsigned ConvertedOp = 0;
12942 // Use a target machine opcode to prevent further DAGCombine
12943 // optimizations that may separate the arithmetic operations
12944 // from the setcc node.
12945 switch (WideVal.getOpcode()) {
12947 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12948 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12949 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12950 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12951 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12956 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12957 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12958 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12959 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12965 // Emit a CMP with 0, which is the TEST pattern.
12966 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12967 DAG.getConstant(0, dl, Op.getValueType()));
12969 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12970 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12972 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12973 DAG.ReplaceAllUsesWith(Op, New);
12974 return SDValue(New.getNode(), 1);
12977 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12979 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12980 SDLoc dl, SelectionDAG &DAG) const {
12981 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12982 if (C->getAPIntValue() == 0)
12983 return EmitTest(Op0, X86CC, dl, DAG);
12985 if (Op0.getValueType() == MVT::i1)
12986 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12989 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12990 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12991 // Do the comparison at i32 if it's smaller, besides the Atom case.
12992 // This avoids subregister aliasing issues. Keep the smaller reference
12993 // if we're optimizing for size, however, as that'll allow better folding
12994 // of memory operations.
12995 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12996 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12997 Attribute::MinSize) &&
12998 !Subtarget->isAtom()) {
12999 unsigned ExtendOp =
13000 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13001 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13002 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13004 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13005 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13006 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13008 return SDValue(Sub.getNode(), 1);
13010 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13013 /// Convert a comparison if required by the subtarget.
13014 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13015 SelectionDAG &DAG) const {
13016 // If the subtarget does not support the FUCOMI instruction, floating-point
13017 // comparisons have to be converted.
13018 if (Subtarget->hasCMov() ||
13019 Cmp.getOpcode() != X86ISD::CMP ||
13020 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13021 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13024 // The instruction selector will select an FUCOM instruction instead of
13025 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13026 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13027 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13029 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13030 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13031 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13032 DAG.getConstant(8, dl, MVT::i8));
13033 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13034 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13037 /// The minimum architected relative accuracy is 2^-12. We need one
13038 /// Newton-Raphson step to have a good float result (24 bits of precision).
13039 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13040 DAGCombinerInfo &DCI,
13041 unsigned &RefinementSteps,
13042 bool &UseOneConstNR) const {
13043 EVT VT = Op.getValueType();
13044 const char *RecipOp;
13046 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13047 // TODO: Add support for AVX512 (v16f32).
13048 // It is likely not profitable to do this for f64 because a double-precision
13049 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13050 // instructions: convert to single, rsqrtss, convert back to double, refine
13051 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13052 // along with FMA, this could be a throughput win.
13053 if (VT == MVT::f32 && Subtarget->hasSSE1())
13055 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13056 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13057 RecipOp = "vec-sqrtf";
13061 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13062 if (!Recips.isEnabled(RecipOp))
13065 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13066 UseOneConstNR = false;
13067 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13070 /// The minimum architected relative accuracy is 2^-12. We need one
13071 /// Newton-Raphson step to have a good float result (24 bits of precision).
13072 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13073 DAGCombinerInfo &DCI,
13074 unsigned &RefinementSteps) const {
13075 EVT VT = Op.getValueType();
13076 const char *RecipOp;
13078 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13079 // TODO: Add support for AVX512 (v16f32).
13080 // It is likely not profitable to do this for f64 because a double-precision
13081 // reciprocal estimate with refinement on x86 prior to FMA requires
13082 // 15 instructions: convert to single, rcpss, convert back to double, refine
13083 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13084 // along with FMA, this could be a throughput win.
13085 if (VT == MVT::f32 && Subtarget->hasSSE1())
13087 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13088 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13089 RecipOp = "vec-divf";
13093 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13094 if (!Recips.isEnabled(RecipOp))
13097 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13098 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13101 /// If we have at least two divisions that use the same divisor, convert to
13102 /// multplication by a reciprocal. This may need to be adjusted for a given
13103 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13104 /// This is because we still need one division to calculate the reciprocal and
13105 /// then we need two multiplies by that reciprocal as replacements for the
13106 /// original divisions.
13107 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13108 return NumUsers > 1;
13111 static bool isAllOnes(SDValue V) {
13112 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13113 return C && C->isAllOnesValue();
13116 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13117 /// if it's possible.
13118 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13119 SDLoc dl, SelectionDAG &DAG) const {
13120 SDValue Op0 = And.getOperand(0);
13121 SDValue Op1 = And.getOperand(1);
13122 if (Op0.getOpcode() == ISD::TRUNCATE)
13123 Op0 = Op0.getOperand(0);
13124 if (Op1.getOpcode() == ISD::TRUNCATE)
13125 Op1 = Op1.getOperand(0);
13128 if (Op1.getOpcode() == ISD::SHL)
13129 std::swap(Op0, Op1);
13130 if (Op0.getOpcode() == ISD::SHL) {
13131 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13132 if (And00C->getZExtValue() == 1) {
13133 // If we looked past a truncate, check that it's only truncating away
13135 unsigned BitWidth = Op0.getValueSizeInBits();
13136 unsigned AndBitWidth = And.getValueSizeInBits();
13137 if (BitWidth > AndBitWidth) {
13139 DAG.computeKnownBits(Op0, Zeros, Ones);
13140 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13144 RHS = Op0.getOperand(1);
13146 } else if (Op1.getOpcode() == ISD::Constant) {
13147 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13148 uint64_t AndRHSVal = AndRHS->getZExtValue();
13149 SDValue AndLHS = Op0;
13151 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13152 LHS = AndLHS.getOperand(0);
13153 RHS = AndLHS.getOperand(1);
13156 // Use BT if the immediate can't be encoded in a TEST instruction.
13157 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13159 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13163 if (LHS.getNode()) {
13164 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13165 // instruction. Since the shift amount is in-range-or-undefined, we know
13166 // that doing a bittest on the i32 value is ok. We extend to i32 because
13167 // the encoding for the i16 version is larger than the i32 version.
13168 // Also promote i16 to i32 for performance / code size reason.
13169 if (LHS.getValueType() == MVT::i8 ||
13170 LHS.getValueType() == MVT::i16)
13171 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13173 // If the operand types disagree, extend the shift amount to match. Since
13174 // BT ignores high bits (like shifts) we can use anyextend.
13175 if (LHS.getValueType() != RHS.getValueType())
13176 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13178 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13179 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13180 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13181 DAG.getConstant(Cond, dl, MVT::i8), BT);
13187 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13189 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13194 // SSE Condition code mapping:
13203 switch (SetCCOpcode) {
13204 default: llvm_unreachable("Unexpected SETCC condition");
13206 case ISD::SETEQ: SSECC = 0; break;
13208 case ISD::SETGT: Swap = true; // Fallthrough
13210 case ISD::SETOLT: SSECC = 1; break;
13212 case ISD::SETGE: Swap = true; // Fallthrough
13214 case ISD::SETOLE: SSECC = 2; break;
13215 case ISD::SETUO: SSECC = 3; break;
13217 case ISD::SETNE: SSECC = 4; break;
13218 case ISD::SETULE: Swap = true; // Fallthrough
13219 case ISD::SETUGE: SSECC = 5; break;
13220 case ISD::SETULT: Swap = true; // Fallthrough
13221 case ISD::SETUGT: SSECC = 6; break;
13222 case ISD::SETO: SSECC = 7; break;
13224 case ISD::SETONE: SSECC = 8; break;
13227 std::swap(Op0, Op1);
13232 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13233 // ones, and then concatenate the result back.
13234 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13235 MVT VT = Op.getSimpleValueType();
13237 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13238 "Unsupported value type for operation");
13240 unsigned NumElems = VT.getVectorNumElements();
13242 SDValue CC = Op.getOperand(2);
13244 // Extract the LHS vectors
13245 SDValue LHS = Op.getOperand(0);
13246 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13247 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13249 // Extract the RHS vectors
13250 SDValue RHS = Op.getOperand(1);
13251 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13252 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13254 // Issue the operation on the smaller types and concatenate the result back
13255 MVT EltVT = VT.getVectorElementType();
13256 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13257 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13258 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13259 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13262 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13263 SDValue Op0 = Op.getOperand(0);
13264 SDValue Op1 = Op.getOperand(1);
13265 SDValue CC = Op.getOperand(2);
13266 MVT VT = Op.getSimpleValueType();
13269 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13270 "Unexpected type for boolean compare operation");
13271 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13272 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13273 DAG.getConstant(-1, dl, VT));
13274 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13275 DAG.getConstant(-1, dl, VT));
13276 switch (SetCCOpcode) {
13277 default: llvm_unreachable("Unexpected SETCC condition");
13279 // (x == y) -> ~(x ^ y)
13280 return DAG.getNode(ISD::XOR, dl, VT,
13281 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13282 DAG.getConstant(-1, dl, VT));
13284 // (x != y) -> (x ^ y)
13285 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13288 // (x > y) -> (x & ~y)
13289 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13292 // (x < y) -> (~x & y)
13293 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13296 // (x <= y) -> (~x | y)
13297 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13300 // (x >=y) -> (x | ~y)
13301 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13305 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13306 const X86Subtarget *Subtarget) {
13307 SDValue Op0 = Op.getOperand(0);
13308 SDValue Op1 = Op.getOperand(1);
13309 SDValue CC = Op.getOperand(2);
13310 MVT VT = Op.getSimpleValueType();
13313 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13314 Op.getValueType().getScalarType() == MVT::i1 &&
13315 "Cannot set masked compare for this operation");
13317 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13319 bool Unsigned = false;
13322 switch (SetCCOpcode) {
13323 default: llvm_unreachable("Unexpected SETCC condition");
13324 case ISD::SETNE: SSECC = 4; break;
13325 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13326 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13327 case ISD::SETLT: Swap = true; //fall-through
13328 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13329 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13330 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13331 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13332 case ISD::SETULE: Unsigned = true; //fall-through
13333 case ISD::SETLE: SSECC = 2; break;
13337 std::swap(Op0, Op1);
13339 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13340 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13341 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13342 DAG.getConstant(SSECC, dl, MVT::i8));
13345 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13346 /// operand \p Op1. If non-trivial (for example because it's not constant)
13347 /// return an empty value.
13348 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13350 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13354 MVT VT = Op1.getSimpleValueType();
13355 MVT EVT = VT.getVectorElementType();
13356 unsigned n = VT.getVectorNumElements();
13357 SmallVector<SDValue, 8> ULTOp1;
13359 for (unsigned i = 0; i < n; ++i) {
13360 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13361 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13364 // Avoid underflow.
13365 APInt Val = Elt->getAPIntValue();
13369 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13372 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13375 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13376 SelectionDAG &DAG) {
13377 SDValue Op0 = Op.getOperand(0);
13378 SDValue Op1 = Op.getOperand(1);
13379 SDValue CC = Op.getOperand(2);
13380 MVT VT = Op.getSimpleValueType();
13381 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13382 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13387 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13388 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13391 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13392 unsigned Opc = X86ISD::CMPP;
13393 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13394 assert(VT.getVectorNumElements() <= 16);
13395 Opc = X86ISD::CMPM;
13397 // In the two special cases we can't handle, emit two comparisons.
13400 unsigned CombineOpc;
13401 if (SetCCOpcode == ISD::SETUEQ) {
13402 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13404 assert(SetCCOpcode == ISD::SETONE);
13405 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13408 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13409 DAG.getConstant(CC0, dl, MVT::i8));
13410 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13411 DAG.getConstant(CC1, dl, MVT::i8));
13412 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13414 // Handle all other FP comparisons here.
13415 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13416 DAG.getConstant(SSECC, dl, MVT::i8));
13419 // Break 256-bit integer vector compare into smaller ones.
13420 if (VT.is256BitVector() && !Subtarget->hasInt256())
13421 return Lower256IntVSETCC(Op, DAG);
13423 EVT OpVT = Op1.getValueType();
13424 if (OpVT.getVectorElementType() == MVT::i1)
13425 return LowerBoolVSETCC_AVX512(Op, DAG);
13427 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13428 if (Subtarget->hasAVX512()) {
13429 if (Op1.getValueType().is512BitVector() ||
13430 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13431 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13432 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13434 // In AVX-512 architecture setcc returns mask with i1 elements,
13435 // But there is no compare instruction for i8 and i16 elements in KNL.
13436 // We are not talking about 512-bit operands in this case, these
13437 // types are illegal.
13439 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13440 OpVT.getVectorElementType().getSizeInBits() >= 8))
13441 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13442 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13445 // We are handling one of the integer comparisons here. Since SSE only has
13446 // GT and EQ comparisons for integer, swapping operands and multiple
13447 // operations may be required for some comparisons.
13449 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13450 bool Subus = false;
13452 switch (SetCCOpcode) {
13453 default: llvm_unreachable("Unexpected SETCC condition");
13454 case ISD::SETNE: Invert = true;
13455 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13456 case ISD::SETLT: Swap = true;
13457 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13458 case ISD::SETGE: Swap = true;
13459 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13460 Invert = true; break;
13461 case ISD::SETULT: Swap = true;
13462 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13463 FlipSigns = true; break;
13464 case ISD::SETUGE: Swap = true;
13465 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13466 FlipSigns = true; Invert = true; break;
13469 // Special case: Use min/max operations for SETULE/SETUGE
13470 MVT VET = VT.getVectorElementType();
13472 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13473 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13476 switch (SetCCOpcode) {
13478 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13479 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13482 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13485 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13486 if (!MinMax && hasSubus) {
13487 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13489 // t = psubus Op0, Op1
13490 // pcmpeq t, <0..0>
13491 switch (SetCCOpcode) {
13493 case ISD::SETULT: {
13494 // If the comparison is against a constant we can turn this into a
13495 // setule. With psubus, setule does not require a swap. This is
13496 // beneficial because the constant in the register is no longer
13497 // destructed as the destination so it can be hoisted out of a loop.
13498 // Only do this pre-AVX since vpcmp* is no longer destructive.
13499 if (Subtarget->hasAVX())
13501 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13502 if (ULEOp1.getNode()) {
13504 Subus = true; Invert = false; Swap = false;
13508 // Psubus is better than flip-sign because it requires no inversion.
13509 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13510 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13514 Opc = X86ISD::SUBUS;
13520 std::swap(Op0, Op1);
13522 // Check that the operation in question is available (most are plain SSE2,
13523 // but PCMPGTQ and PCMPEQQ have different requirements).
13524 if (VT == MVT::v2i64) {
13525 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13526 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13528 // First cast everything to the right type.
13529 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13530 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13532 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13533 // bits of the inputs before performing those operations. The lower
13534 // compare is always unsigned.
13537 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13539 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13540 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13541 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13542 Sign, Zero, Sign, Zero);
13544 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13545 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13547 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13548 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13549 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13551 // Create masks for only the low parts/high parts of the 64 bit integers.
13552 static const int MaskHi[] = { 1, 1, 3, 3 };
13553 static const int MaskLo[] = { 0, 0, 2, 2 };
13554 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13555 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13556 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13558 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13559 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13562 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13564 return DAG.getBitcast(VT, Result);
13567 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13568 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13569 // pcmpeqd + pshufd + pand.
13570 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13572 // First cast everything to the right type.
13573 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13574 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13577 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13579 // Make sure the lower and upper halves are both all-ones.
13580 static const int Mask[] = { 1, 0, 3, 2 };
13581 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13582 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13585 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13587 return DAG.getBitcast(VT, Result);
13591 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13592 // bits of the inputs before performing those operations.
13594 EVT EltVT = VT.getVectorElementType();
13595 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13597 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13598 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13601 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13603 // If the logical-not of the result is required, perform that now.
13605 Result = DAG.getNOT(dl, Result, VT);
13608 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13611 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13612 getZeroVector(VT, Subtarget, DAG, dl));
13617 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13619 MVT VT = Op.getSimpleValueType();
13621 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13623 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13624 && "SetCC type must be 8-bit or 1-bit integer");
13625 SDValue Op0 = Op.getOperand(0);
13626 SDValue Op1 = Op.getOperand(1);
13628 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13630 // Optimize to BT if possible.
13631 // Lower (X & (1 << N)) == 0 to BT(X, N).
13632 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13633 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13634 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13635 Op1.getOpcode() == ISD::Constant &&
13636 cast<ConstantSDNode>(Op1)->isNullValue() &&
13637 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13638 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13639 if (NewSetCC.getNode()) {
13641 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13646 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13648 if (Op1.getOpcode() == ISD::Constant &&
13649 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13650 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13651 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13653 // If the input is a setcc, then reuse the input setcc or use a new one with
13654 // the inverted condition.
13655 if (Op0.getOpcode() == X86ISD::SETCC) {
13656 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13657 bool Invert = (CC == ISD::SETNE) ^
13658 cast<ConstantSDNode>(Op1)->isNullValue();
13662 CCode = X86::GetOppositeBranchCondition(CCode);
13663 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13664 DAG.getConstant(CCode, dl, MVT::i8),
13665 Op0.getOperand(1));
13667 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13671 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13672 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13673 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13675 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13676 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13679 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13680 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13681 if (X86CC == X86::COND_INVALID)
13684 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13685 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13686 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13687 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13689 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13693 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13694 static bool isX86LogicalCmp(SDValue Op) {
13695 unsigned Opc = Op.getNode()->getOpcode();
13696 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13697 Opc == X86ISD::SAHF)
13699 if (Op.getResNo() == 1 &&
13700 (Opc == X86ISD::ADD ||
13701 Opc == X86ISD::SUB ||
13702 Opc == X86ISD::ADC ||
13703 Opc == X86ISD::SBB ||
13704 Opc == X86ISD::SMUL ||
13705 Opc == X86ISD::UMUL ||
13706 Opc == X86ISD::INC ||
13707 Opc == X86ISD::DEC ||
13708 Opc == X86ISD::OR ||
13709 Opc == X86ISD::XOR ||
13710 Opc == X86ISD::AND))
13713 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13719 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13720 if (V.getOpcode() != ISD::TRUNCATE)
13723 SDValue VOp0 = V.getOperand(0);
13724 unsigned InBits = VOp0.getValueSizeInBits();
13725 unsigned Bits = V.getValueSizeInBits();
13726 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13729 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13730 bool addTest = true;
13731 SDValue Cond = Op.getOperand(0);
13732 SDValue Op1 = Op.getOperand(1);
13733 SDValue Op2 = Op.getOperand(2);
13735 EVT VT = Op1.getValueType();
13738 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13739 // are available or VBLENDV if AVX is available.
13740 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13741 if (Cond.getOpcode() == ISD::SETCC &&
13742 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13743 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13744 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13745 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13746 int SSECC = translateX86FSETCC(
13747 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13750 if (Subtarget->hasAVX512()) {
13751 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13752 DAG.getConstant(SSECC, DL, MVT::i8));
13753 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13756 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13757 DAG.getConstant(SSECC, DL, MVT::i8));
13759 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13760 // of 3 logic instructions for size savings and potentially speed.
13761 // Unfortunately, there is no scalar form of VBLENDV.
13763 // If either operand is a constant, don't try this. We can expect to
13764 // optimize away at least one of the logic instructions later in that
13765 // case, so that sequence would be faster than a variable blend.
13767 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13768 // uses XMM0 as the selection register. That may need just as many
13769 // instructions as the AND/ANDN/OR sequence due to register moves, so
13772 if (Subtarget->hasAVX() &&
13773 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13775 // Convert to vectors, do a VSELECT, and convert back to scalar.
13776 // All of the conversions should be optimized away.
13778 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13779 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13780 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13781 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13783 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13784 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13786 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13788 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13789 VSel, DAG.getIntPtrConstant(0, DL));
13791 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13792 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13793 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13797 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13799 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13800 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13801 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13802 Op1Scalar = Op1.getOperand(0);
13804 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13805 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13806 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13807 Op2Scalar = Op2.getOperand(0);
13808 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13809 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13810 Op1Scalar.getValueType(),
13811 Cond, Op1Scalar, Op2Scalar);
13812 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13813 return DAG.getBitcast(VT, newSelect);
13814 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13815 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13816 DAG.getIntPtrConstant(0, DL));
13820 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13821 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13822 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13823 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13824 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13825 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13826 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13828 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13831 if (Cond.getOpcode() == ISD::SETCC) {
13832 SDValue NewCond = LowerSETCC(Cond, DAG);
13833 if (NewCond.getNode())
13837 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13838 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13839 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13840 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13841 if (Cond.getOpcode() == X86ISD::SETCC &&
13842 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13843 isZero(Cond.getOperand(1).getOperand(1))) {
13844 SDValue Cmp = Cond.getOperand(1);
13846 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13848 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13849 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13850 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13852 SDValue CmpOp0 = Cmp.getOperand(0);
13853 // Apply further optimizations for special cases
13854 // (select (x != 0), -1, 0) -> neg & sbb
13855 // (select (x == 0), 0, -1) -> neg & sbb
13856 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13857 if (YC->isNullValue() &&
13858 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13859 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13860 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13861 DAG.getConstant(0, DL,
13862 CmpOp0.getValueType()),
13864 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13865 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13866 SDValue(Neg.getNode(), 1));
13870 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13871 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13872 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13874 SDValue Res = // Res = 0 or -1.
13875 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13876 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13878 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13879 Res = DAG.getNOT(DL, Res, Res.getValueType());
13881 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13882 if (!N2C || !N2C->isNullValue())
13883 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13888 // Look past (and (setcc_carry (cmp ...)), 1).
13889 if (Cond.getOpcode() == ISD::AND &&
13890 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13891 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13892 if (C && C->getAPIntValue() == 1)
13893 Cond = Cond.getOperand(0);
13896 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13897 // setting operand in place of the X86ISD::SETCC.
13898 unsigned CondOpcode = Cond.getOpcode();
13899 if (CondOpcode == X86ISD::SETCC ||
13900 CondOpcode == X86ISD::SETCC_CARRY) {
13901 CC = Cond.getOperand(0);
13903 SDValue Cmp = Cond.getOperand(1);
13904 unsigned Opc = Cmp.getOpcode();
13905 MVT VT = Op.getSimpleValueType();
13907 bool IllegalFPCMov = false;
13908 if (VT.isFloatingPoint() && !VT.isVector() &&
13909 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13910 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13912 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13913 Opc == X86ISD::BT) { // FIXME
13917 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13918 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13919 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13920 Cond.getOperand(0).getValueType() != MVT::i8)) {
13921 SDValue LHS = Cond.getOperand(0);
13922 SDValue RHS = Cond.getOperand(1);
13923 unsigned X86Opcode;
13926 switch (CondOpcode) {
13927 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13928 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13929 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13930 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13931 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13932 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13933 default: llvm_unreachable("unexpected overflowing operator");
13935 if (CondOpcode == ISD::UMULO)
13936 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13939 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13941 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13943 if (CondOpcode == ISD::UMULO)
13944 Cond = X86Op.getValue(2);
13946 Cond = X86Op.getValue(1);
13948 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13953 // Look pass the truncate if the high bits are known zero.
13954 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13955 Cond = Cond.getOperand(0);
13957 // We know the result of AND is compared against zero. Try to match
13959 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13960 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13961 if (NewSetCC.getNode()) {
13962 CC = NewSetCC.getOperand(0);
13963 Cond = NewSetCC.getOperand(1);
13970 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13971 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13974 // a < b ? -1 : 0 -> RES = ~setcc_carry
13975 // a < b ? 0 : -1 -> RES = setcc_carry
13976 // a >= b ? -1 : 0 -> RES = setcc_carry
13977 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13978 if (Cond.getOpcode() == X86ISD::SUB) {
13979 Cond = ConvertCmpIfNecessary(Cond, DAG);
13980 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13982 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13983 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13984 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13985 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13987 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13988 return DAG.getNOT(DL, Res, Res.getValueType());
13993 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13994 // widen the cmov and push the truncate through. This avoids introducing a new
13995 // branch during isel and doesn't add any extensions.
13996 if (Op.getValueType() == MVT::i8 &&
13997 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13998 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13999 if (T1.getValueType() == T2.getValueType() &&
14000 // Blacklist CopyFromReg to avoid partial register stalls.
14001 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14002 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14003 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14004 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14008 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14009 // condition is true.
14010 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14011 SDValue Ops[] = { Op2, Op1, CC, Cond };
14012 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14015 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14016 const X86Subtarget *Subtarget,
14017 SelectionDAG &DAG) {
14018 MVT VT = Op->getSimpleValueType(0);
14019 SDValue In = Op->getOperand(0);
14020 MVT InVT = In.getSimpleValueType();
14021 MVT VTElt = VT.getVectorElementType();
14022 MVT InVTElt = InVT.getVectorElementType();
14026 if ((InVTElt == MVT::i1) &&
14027 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14028 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14030 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14031 VTElt.getSizeInBits() <= 16)) ||
14033 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14034 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14036 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14037 VTElt.getSizeInBits() >= 32))))
14038 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14040 unsigned int NumElts = VT.getVectorNumElements();
14042 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14045 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14046 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14047 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14048 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14051 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14052 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14054 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14057 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14059 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14060 if (VT.is512BitVector())
14062 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14065 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14066 const X86Subtarget *Subtarget,
14067 SelectionDAG &DAG) {
14068 SDValue In = Op->getOperand(0);
14069 MVT VT = Op->getSimpleValueType(0);
14070 MVT InVT = In.getSimpleValueType();
14071 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14073 MVT InSVT = InVT.getScalarType();
14074 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14076 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14078 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14083 // SSE41 targets can use the pmovsx* instructions directly.
14084 if (Subtarget->hasSSE41())
14085 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14087 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14091 // As SRAI is only available on i16/i32 types, we expand only up to i32
14092 // and handle i64 separately.
14093 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14094 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14095 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14096 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14097 Curr = DAG.getBitcast(CurrVT, Curr);
14100 SDValue SignExt = Curr;
14101 if (CurrVT != InVT) {
14102 unsigned SignExtShift =
14103 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14104 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14105 DAG.getConstant(SignExtShift, dl, MVT::i8));
14111 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14112 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14113 DAG.getConstant(31, dl, MVT::i8));
14114 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14115 return DAG.getBitcast(VT, Ext);
14121 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14122 SelectionDAG &DAG) {
14123 MVT VT = Op->getSimpleValueType(0);
14124 SDValue In = Op->getOperand(0);
14125 MVT InVT = In.getSimpleValueType();
14128 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14129 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14131 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14132 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14133 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14136 if (Subtarget->hasInt256())
14137 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14139 // Optimize vectors in AVX mode
14140 // Sign extend v8i16 to v8i32 and
14143 // Divide input vector into two parts
14144 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14145 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14146 // concat the vectors to original VT
14148 unsigned NumElems = InVT.getVectorNumElements();
14149 SDValue Undef = DAG.getUNDEF(InVT);
14151 SmallVector<int,8> ShufMask1(NumElems, -1);
14152 for (unsigned i = 0; i != NumElems/2; ++i)
14155 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14157 SmallVector<int,8> ShufMask2(NumElems, -1);
14158 for (unsigned i = 0; i != NumElems/2; ++i)
14159 ShufMask2[i] = i + NumElems/2;
14161 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14163 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14164 VT.getVectorNumElements()/2);
14166 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14167 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14169 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14172 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14173 // may emit an illegal shuffle but the expansion is still better than scalar
14174 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14175 // we'll emit a shuffle and a arithmetic shift.
14176 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14177 // TODO: It is possible to support ZExt by zeroing the undef values during
14178 // the shuffle phase or after the shuffle.
14179 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14180 SelectionDAG &DAG) {
14181 MVT RegVT = Op.getSimpleValueType();
14182 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14183 assert(RegVT.isInteger() &&
14184 "We only custom lower integer vector sext loads.");
14186 // Nothing useful we can do without SSE2 shuffles.
14187 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14189 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14191 EVT MemVT = Ld->getMemoryVT();
14192 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14193 unsigned RegSz = RegVT.getSizeInBits();
14195 ISD::LoadExtType Ext = Ld->getExtensionType();
14197 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14198 && "Only anyext and sext are currently implemented.");
14199 assert(MemVT != RegVT && "Cannot extend to the same type");
14200 assert(MemVT.isVector() && "Must load a vector from memory");
14202 unsigned NumElems = RegVT.getVectorNumElements();
14203 unsigned MemSz = MemVT.getSizeInBits();
14204 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14206 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14207 // The only way in which we have a legal 256-bit vector result but not the
14208 // integer 256-bit operations needed to directly lower a sextload is if we
14209 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14210 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14211 // correctly legalized. We do this late to allow the canonical form of
14212 // sextload to persist throughout the rest of the DAG combiner -- it wants
14213 // to fold together any extensions it can, and so will fuse a sign_extend
14214 // of an sextload into a sextload targeting a wider value.
14216 if (MemSz == 128) {
14217 // Just switch this to a normal load.
14218 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14219 "it must be a legal 128-bit vector "
14221 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14222 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14223 Ld->isInvariant(), Ld->getAlignment());
14225 assert(MemSz < 128 &&
14226 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14227 // Do an sext load to a 128-bit vector type. We want to use the same
14228 // number of elements, but elements half as wide. This will end up being
14229 // recursively lowered by this routine, but will succeed as we definitely
14230 // have all the necessary features if we're using AVX1.
14232 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14233 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14235 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14236 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14237 Ld->isNonTemporal(), Ld->isInvariant(),
14238 Ld->getAlignment());
14241 // Replace chain users with the new chain.
14242 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14243 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14245 // Finally, do a normal sign-extend to the desired register.
14246 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14249 // All sizes must be a power of two.
14250 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14251 "Non-power-of-two elements are not custom lowered!");
14253 // Attempt to load the original value using scalar loads.
14254 // Find the largest scalar type that divides the total loaded size.
14255 MVT SclrLoadTy = MVT::i8;
14256 for (MVT Tp : MVT::integer_valuetypes()) {
14257 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14262 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14263 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14265 SclrLoadTy = MVT::f64;
14267 // Calculate the number of scalar loads that we need to perform
14268 // in order to load our vector from memory.
14269 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14271 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14272 "Can only lower sext loads with a single scalar load!");
14274 unsigned loadRegZize = RegSz;
14275 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14278 // Represent our vector as a sequence of elements which are the
14279 // largest scalar that we can load.
14280 EVT LoadUnitVecVT = EVT::getVectorVT(
14281 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14283 // Represent the data using the same element type that is stored in
14284 // memory. In practice, we ''widen'' MemVT.
14286 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14287 loadRegZize / MemVT.getScalarType().getSizeInBits());
14289 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14290 "Invalid vector type");
14292 // We can't shuffle using an illegal type.
14293 assert(TLI.isTypeLegal(WideVecVT) &&
14294 "We only lower types that form legal widened vector types");
14296 SmallVector<SDValue, 8> Chains;
14297 SDValue Ptr = Ld->getBasePtr();
14298 SDValue Increment =
14299 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14300 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14302 for (unsigned i = 0; i < NumLoads; ++i) {
14303 // Perform a single load.
14304 SDValue ScalarLoad =
14305 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14306 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14307 Ld->getAlignment());
14308 Chains.push_back(ScalarLoad.getValue(1));
14309 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14310 // another round of DAGCombining.
14312 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14314 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14315 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14317 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14320 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14322 // Bitcast the loaded value to a vector of the original element type, in
14323 // the size of the target vector type.
14324 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14325 unsigned SizeRatio = RegSz / MemSz;
14327 if (Ext == ISD::SEXTLOAD) {
14328 // If we have SSE4.1, we can directly emit a VSEXT node.
14329 if (Subtarget->hasSSE41()) {
14330 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14331 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14335 // Otherwise we'll shuffle the small elements in the high bits of the
14336 // larger type and perform an arithmetic shift. If the shift is not legal
14337 // it's better to scalarize.
14338 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14339 "We can't implement a sext load without an arithmetic right shift!");
14341 // Redistribute the loaded elements into the different locations.
14342 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14343 for (unsigned i = 0; i != NumElems; ++i)
14344 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14346 SDValue Shuff = DAG.getVectorShuffle(
14347 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14349 Shuff = DAG.getBitcast(RegVT, Shuff);
14351 // Build the arithmetic shift.
14352 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14353 MemVT.getVectorElementType().getSizeInBits();
14355 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14356 DAG.getConstant(Amt, dl, RegVT));
14358 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14362 // Redistribute the loaded elements into the different locations.
14363 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14364 for (unsigned i = 0; i != NumElems; ++i)
14365 ShuffleVec[i * SizeRatio] = i;
14367 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14368 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14370 // Bitcast to the requested type.
14371 Shuff = DAG.getBitcast(RegVT, Shuff);
14372 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14376 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14377 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14378 // from the AND / OR.
14379 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14380 Opc = Op.getOpcode();
14381 if (Opc != ISD::OR && Opc != ISD::AND)
14383 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14384 Op.getOperand(0).hasOneUse() &&
14385 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14386 Op.getOperand(1).hasOneUse());
14389 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14390 // 1 and that the SETCC node has a single use.
14391 static bool isXor1OfSetCC(SDValue Op) {
14392 if (Op.getOpcode() != ISD::XOR)
14394 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14395 if (N1C && N1C->getAPIntValue() == 1) {
14396 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14397 Op.getOperand(0).hasOneUse();
14402 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14403 bool addTest = true;
14404 SDValue Chain = Op.getOperand(0);
14405 SDValue Cond = Op.getOperand(1);
14406 SDValue Dest = Op.getOperand(2);
14409 bool Inverted = false;
14411 if (Cond.getOpcode() == ISD::SETCC) {
14412 // Check for setcc([su]{add,sub,mul}o == 0).
14413 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14414 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14415 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14416 Cond.getOperand(0).getResNo() == 1 &&
14417 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14418 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14419 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14420 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14421 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14422 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14424 Cond = Cond.getOperand(0);
14426 SDValue NewCond = LowerSETCC(Cond, DAG);
14427 if (NewCond.getNode())
14432 // FIXME: LowerXALUO doesn't handle these!!
14433 else if (Cond.getOpcode() == X86ISD::ADD ||
14434 Cond.getOpcode() == X86ISD::SUB ||
14435 Cond.getOpcode() == X86ISD::SMUL ||
14436 Cond.getOpcode() == X86ISD::UMUL)
14437 Cond = LowerXALUO(Cond, DAG);
14440 // Look pass (and (setcc_carry (cmp ...)), 1).
14441 if (Cond.getOpcode() == ISD::AND &&
14442 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14443 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14444 if (C && C->getAPIntValue() == 1)
14445 Cond = Cond.getOperand(0);
14448 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14449 // setting operand in place of the X86ISD::SETCC.
14450 unsigned CondOpcode = Cond.getOpcode();
14451 if (CondOpcode == X86ISD::SETCC ||
14452 CondOpcode == X86ISD::SETCC_CARRY) {
14453 CC = Cond.getOperand(0);
14455 SDValue Cmp = Cond.getOperand(1);
14456 unsigned Opc = Cmp.getOpcode();
14457 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14458 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14462 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14466 // These can only come from an arithmetic instruction with overflow,
14467 // e.g. SADDO, UADDO.
14468 Cond = Cond.getNode()->getOperand(1);
14474 CondOpcode = Cond.getOpcode();
14475 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14476 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14477 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14478 Cond.getOperand(0).getValueType() != MVT::i8)) {
14479 SDValue LHS = Cond.getOperand(0);
14480 SDValue RHS = Cond.getOperand(1);
14481 unsigned X86Opcode;
14484 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14485 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14487 switch (CondOpcode) {
14488 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14492 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14495 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14496 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14500 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14503 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14504 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14505 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14506 default: llvm_unreachable("unexpected overflowing operator");
14509 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14510 if (CondOpcode == ISD::UMULO)
14511 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14514 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14516 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14518 if (CondOpcode == ISD::UMULO)
14519 Cond = X86Op.getValue(2);
14521 Cond = X86Op.getValue(1);
14523 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14527 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14528 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14529 if (CondOpc == ISD::OR) {
14530 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14531 // two branches instead of an explicit OR instruction with a
14533 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14534 isX86LogicalCmp(Cmp)) {
14535 CC = Cond.getOperand(0).getOperand(0);
14536 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14537 Chain, Dest, CC, Cmp);
14538 CC = Cond.getOperand(1).getOperand(0);
14542 } else { // ISD::AND
14543 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14544 // two branches instead of an explicit AND instruction with a
14545 // separate test. However, we only do this if this block doesn't
14546 // have a fall-through edge, because this requires an explicit
14547 // jmp when the condition is false.
14548 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14549 isX86LogicalCmp(Cmp) &&
14550 Op.getNode()->hasOneUse()) {
14551 X86::CondCode CCode =
14552 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14553 CCode = X86::GetOppositeBranchCondition(CCode);
14554 CC = DAG.getConstant(CCode, dl, MVT::i8);
14555 SDNode *User = *Op.getNode()->use_begin();
14556 // Look for an unconditional branch following this conditional branch.
14557 // We need this because we need to reverse the successors in order
14558 // to implement FCMP_OEQ.
14559 if (User->getOpcode() == ISD::BR) {
14560 SDValue FalseBB = User->getOperand(1);
14562 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14563 assert(NewBR == User);
14567 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14568 Chain, Dest, CC, Cmp);
14569 X86::CondCode CCode =
14570 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14571 CCode = X86::GetOppositeBranchCondition(CCode);
14572 CC = DAG.getConstant(CCode, dl, MVT::i8);
14578 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14579 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14580 // It should be transformed during dag combiner except when the condition
14581 // is set by a arithmetics with overflow node.
14582 X86::CondCode CCode =
14583 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14584 CCode = X86::GetOppositeBranchCondition(CCode);
14585 CC = DAG.getConstant(CCode, dl, MVT::i8);
14586 Cond = Cond.getOperand(0).getOperand(1);
14588 } else if (Cond.getOpcode() == ISD::SETCC &&
14589 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14590 // For FCMP_OEQ, we can emit
14591 // two branches instead of an explicit AND instruction with a
14592 // separate test. However, we only do this if this block doesn't
14593 // have a fall-through edge, because this requires an explicit
14594 // jmp when the condition is false.
14595 if (Op.getNode()->hasOneUse()) {
14596 SDNode *User = *Op.getNode()->use_begin();
14597 // Look for an unconditional branch following this conditional branch.
14598 // We need this because we need to reverse the successors in order
14599 // to implement FCMP_OEQ.
14600 if (User->getOpcode() == ISD::BR) {
14601 SDValue FalseBB = User->getOperand(1);
14603 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14604 assert(NewBR == User);
14608 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14609 Cond.getOperand(0), Cond.getOperand(1));
14610 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14611 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14612 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14613 Chain, Dest, CC, Cmp);
14614 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14619 } else if (Cond.getOpcode() == ISD::SETCC &&
14620 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14621 // For FCMP_UNE, we can emit
14622 // two branches instead of an explicit AND instruction with a
14623 // separate test. However, we only do this if this block doesn't
14624 // have a fall-through edge, because this requires an explicit
14625 // jmp when the condition is false.
14626 if (Op.getNode()->hasOneUse()) {
14627 SDNode *User = *Op.getNode()->use_begin();
14628 // Look for an unconditional branch following this conditional branch.
14629 // We need this because we need to reverse the successors in order
14630 // to implement FCMP_UNE.
14631 if (User->getOpcode() == ISD::BR) {
14632 SDValue FalseBB = User->getOperand(1);
14634 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14635 assert(NewBR == User);
14638 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14639 Cond.getOperand(0), Cond.getOperand(1));
14640 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14641 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14642 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14643 Chain, Dest, CC, Cmp);
14644 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14654 // Look pass the truncate if the high bits are known zero.
14655 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14656 Cond = Cond.getOperand(0);
14658 // We know the result of AND is compared against zero. Try to match
14660 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14661 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14662 if (NewSetCC.getNode()) {
14663 CC = NewSetCC.getOperand(0);
14664 Cond = NewSetCC.getOperand(1);
14671 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14672 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14673 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14675 Cond = ConvertCmpIfNecessary(Cond, DAG);
14676 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14677 Chain, Dest, CC, Cond);
14680 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14681 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14682 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14683 // that the guard pages used by the OS virtual memory manager are allocated in
14684 // correct sequence.
14686 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14687 SelectionDAG &DAG) const {
14688 MachineFunction &MF = DAG.getMachineFunction();
14689 bool SplitStack = MF.shouldSplitStack();
14690 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14696 SDNode* Node = Op.getNode();
14698 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14699 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14700 " not tell us which reg is the stack pointer!");
14701 EVT VT = Node->getValueType(0);
14702 SDValue Tmp1 = SDValue(Node, 0);
14703 SDValue Tmp2 = SDValue(Node, 1);
14704 SDValue Tmp3 = Node->getOperand(2);
14705 SDValue Chain = Tmp1.getOperand(0);
14707 // Chain the dynamic stack allocation so that it doesn't modify the stack
14708 // pointer when other instructions are using the stack.
14709 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14712 SDValue Size = Tmp2.getOperand(1);
14713 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14714 Chain = SP.getValue(1);
14715 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14716 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14717 unsigned StackAlign = TFI.getStackAlignment();
14718 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14719 if (Align > StackAlign)
14720 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14721 DAG.getConstant(-(uint64_t)Align, dl, VT));
14722 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14724 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14725 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14728 SDValue Ops[2] = { Tmp1, Tmp2 };
14729 return DAG.getMergeValues(Ops, dl);
14733 SDValue Chain = Op.getOperand(0);
14734 SDValue Size = Op.getOperand(1);
14735 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14736 EVT VT = Op.getNode()->getValueType(0);
14738 bool Is64Bit = Subtarget->is64Bit();
14739 EVT SPTy = getPointerTy();
14742 MachineRegisterInfo &MRI = MF.getRegInfo();
14745 // The 64 bit implementation of segmented stacks needs to clobber both r10
14746 // r11. This makes it impossible to use it along with nested parameters.
14747 const Function *F = MF.getFunction();
14749 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14751 if (I->hasNestAttr())
14752 report_fatal_error("Cannot use segmented stacks with functions that "
14753 "have nested arguments.");
14756 const TargetRegisterClass *AddrRegClass =
14757 getRegClassFor(getPointerTy());
14758 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14759 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14760 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14761 DAG.getRegister(Vreg, SPTy));
14762 SDValue Ops1[2] = { Value, Chain };
14763 return DAG.getMergeValues(Ops1, dl);
14766 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14768 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14769 Flag = Chain.getValue(1);
14770 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14772 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14774 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14775 unsigned SPReg = RegInfo->getStackRegister();
14776 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14777 Chain = SP.getValue(1);
14780 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14781 DAG.getConstant(-(uint64_t)Align, dl, VT));
14782 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14785 SDValue Ops1[2] = { SP, Chain };
14786 return DAG.getMergeValues(Ops1, dl);
14790 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14791 MachineFunction &MF = DAG.getMachineFunction();
14792 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14794 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14797 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14798 // vastart just stores the address of the VarArgsFrameIndex slot into the
14799 // memory location argument.
14800 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14802 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14803 MachinePointerInfo(SV), false, false, 0);
14807 // gp_offset (0 - 6 * 8)
14808 // fp_offset (48 - 48 + 8 * 16)
14809 // overflow_arg_area (point to parameters coming in memory).
14811 SmallVector<SDValue, 8> MemOps;
14812 SDValue FIN = Op.getOperand(1);
14814 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14815 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14817 FIN, MachinePointerInfo(SV), false, false, 0);
14818 MemOps.push_back(Store);
14821 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14822 FIN, DAG.getIntPtrConstant(4, DL));
14823 Store = DAG.getStore(Op.getOperand(0), DL,
14824 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14826 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14827 MemOps.push_back(Store);
14829 // Store ptr to overflow_arg_area
14830 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14831 FIN, DAG.getIntPtrConstant(4, DL));
14832 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14834 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14835 MachinePointerInfo(SV, 8),
14837 MemOps.push_back(Store);
14839 // Store ptr to reg_save_area.
14840 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14841 FIN, DAG.getIntPtrConstant(8, DL));
14842 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14844 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14845 MachinePointerInfo(SV, 16), false, false, 0);
14846 MemOps.push_back(Store);
14847 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14850 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14851 assert(Subtarget->is64Bit() &&
14852 "LowerVAARG only handles 64-bit va_arg!");
14853 assert((Subtarget->isTargetLinux() ||
14854 Subtarget->isTargetDarwin()) &&
14855 "Unhandled target in LowerVAARG");
14856 assert(Op.getNode()->getNumOperands() == 4);
14857 SDValue Chain = Op.getOperand(0);
14858 SDValue SrcPtr = Op.getOperand(1);
14859 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14860 unsigned Align = Op.getConstantOperandVal(3);
14863 EVT ArgVT = Op.getNode()->getValueType(0);
14864 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14865 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14868 // Decide which area this value should be read from.
14869 // TODO: Implement the AMD64 ABI in its entirety. This simple
14870 // selection mechanism works only for the basic types.
14871 if (ArgVT == MVT::f80) {
14872 llvm_unreachable("va_arg for f80 not yet implemented");
14873 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14874 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14875 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14876 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14878 llvm_unreachable("Unhandled argument type in LowerVAARG");
14881 if (ArgMode == 2) {
14882 // Sanity Check: Make sure using fp_offset makes sense.
14883 assert(!Subtarget->useSoftFloat() &&
14884 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14885 Attribute::NoImplicitFloat)) &&
14886 Subtarget->hasSSE1());
14889 // Insert VAARG_64 node into the DAG
14890 // VAARG_64 returns two values: Variable Argument Address, Chain
14891 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14892 DAG.getConstant(ArgMode, dl, MVT::i8),
14893 DAG.getConstant(Align, dl, MVT::i32)};
14894 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14895 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14896 VTs, InstOps, MVT::i64,
14897 MachinePointerInfo(SV),
14899 /*Volatile=*/false,
14901 /*WriteMem=*/true);
14902 Chain = VAARG.getValue(1);
14904 // Load the next argument and return it
14905 return DAG.getLoad(ArgVT, dl,
14908 MachinePointerInfo(),
14909 false, false, false, 0);
14912 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14913 SelectionDAG &DAG) {
14914 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14915 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14916 SDValue Chain = Op.getOperand(0);
14917 SDValue DstPtr = Op.getOperand(1);
14918 SDValue SrcPtr = Op.getOperand(2);
14919 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14920 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14923 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14924 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14926 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14929 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14930 // amount is a constant. Takes immediate version of shift as input.
14931 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14932 SDValue SrcOp, uint64_t ShiftAmt,
14933 SelectionDAG &DAG) {
14934 MVT ElementType = VT.getVectorElementType();
14936 // Fold this packed shift into its first operand if ShiftAmt is 0.
14940 // Check for ShiftAmt >= element width
14941 if (ShiftAmt >= ElementType.getSizeInBits()) {
14942 if (Opc == X86ISD::VSRAI)
14943 ShiftAmt = ElementType.getSizeInBits() - 1;
14945 return DAG.getConstant(0, dl, VT);
14948 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14949 && "Unknown target vector shift-by-constant node");
14951 // Fold this packed vector shift into a build vector if SrcOp is a
14952 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14953 if (VT == SrcOp.getSimpleValueType() &&
14954 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14955 SmallVector<SDValue, 8> Elts;
14956 unsigned NumElts = SrcOp->getNumOperands();
14957 ConstantSDNode *ND;
14960 default: llvm_unreachable(nullptr);
14961 case X86ISD::VSHLI:
14962 for (unsigned i=0; i!=NumElts; ++i) {
14963 SDValue CurrentOp = SrcOp->getOperand(i);
14964 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14965 Elts.push_back(CurrentOp);
14968 ND = cast<ConstantSDNode>(CurrentOp);
14969 const APInt &C = ND->getAPIntValue();
14970 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14973 case X86ISD::VSRLI:
14974 for (unsigned i=0; i!=NumElts; ++i) {
14975 SDValue CurrentOp = SrcOp->getOperand(i);
14976 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14977 Elts.push_back(CurrentOp);
14980 ND = cast<ConstantSDNode>(CurrentOp);
14981 const APInt &C = ND->getAPIntValue();
14982 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14985 case X86ISD::VSRAI:
14986 for (unsigned i=0; i!=NumElts; ++i) {
14987 SDValue CurrentOp = SrcOp->getOperand(i);
14988 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14989 Elts.push_back(CurrentOp);
14992 ND = cast<ConstantSDNode>(CurrentOp);
14993 const APInt &C = ND->getAPIntValue();
14994 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14999 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15002 return DAG.getNode(Opc, dl, VT, SrcOp,
15003 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15006 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15007 // may or may not be a constant. Takes immediate version of shift as input.
15008 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15009 SDValue SrcOp, SDValue ShAmt,
15010 SelectionDAG &DAG) {
15011 MVT SVT = ShAmt.getSimpleValueType();
15012 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15014 // Catch shift-by-constant.
15015 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15016 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15017 CShAmt->getZExtValue(), DAG);
15019 // Change opcode to non-immediate version
15021 default: llvm_unreachable("Unknown target vector shift node");
15022 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15023 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15024 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15027 const X86Subtarget &Subtarget =
15028 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15029 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15030 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15031 // Let the shuffle legalizer expand this shift amount node.
15032 SDValue Op0 = ShAmt.getOperand(0);
15033 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15034 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15036 // Need to build a vector containing shift amount.
15037 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15038 SmallVector<SDValue, 4> ShOps;
15039 ShOps.push_back(ShAmt);
15040 if (SVT == MVT::i32) {
15041 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15042 ShOps.push_back(DAG.getUNDEF(SVT));
15044 ShOps.push_back(DAG.getUNDEF(SVT));
15046 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15047 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15050 // The return type has to be a 128-bit type with the same element
15051 // type as the input type.
15052 MVT EltVT = VT.getVectorElementType();
15053 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15055 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15056 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15059 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15060 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15061 /// necessary casting for \p Mask when lowering masking intrinsics.
15062 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15063 SDValue PreservedSrc,
15064 const X86Subtarget *Subtarget,
15065 SelectionDAG &DAG) {
15066 EVT VT = Op.getValueType();
15067 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15068 MVT::i1, VT.getVectorNumElements());
15069 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15070 Mask.getValueType().getSizeInBits());
15073 assert(MaskVT.isSimple() && "invalid mask type");
15075 if (isAllOnes(Mask))
15078 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15079 // are extracted by EXTRACT_SUBVECTOR.
15080 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15081 DAG.getBitcast(BitcastVT, Mask),
15082 DAG.getIntPtrConstant(0, dl));
15084 switch (Op.getOpcode()) {
15086 case X86ISD::PCMPEQM:
15087 case X86ISD::PCMPGTM:
15089 case X86ISD::CMPMU:
15090 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15092 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15093 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15094 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15097 /// \brief Creates an SDNode for a predicated scalar operation.
15098 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15099 /// The mask is comming as MVT::i8 and it should be truncated
15100 /// to MVT::i1 while lowering masking intrinsics.
15101 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15102 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
15103 /// a scalar instruction.
15104 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15105 SDValue PreservedSrc,
15106 const X86Subtarget *Subtarget,
15107 SelectionDAG &DAG) {
15108 if (isAllOnes(Mask))
15111 EVT VT = Op.getValueType();
15113 // The mask should be of type MVT::i1
15114 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15116 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15117 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15118 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15121 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15122 SelectionDAG &DAG) {
15124 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15125 EVT VT = Op.getValueType();
15126 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15128 switch(IntrData->Type) {
15129 case INTR_TYPE_1OP:
15130 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15131 case INTR_TYPE_2OP:
15132 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15134 case INTR_TYPE_3OP:
15135 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15136 Op.getOperand(2), Op.getOperand(3));
15137 case INTR_TYPE_1OP_MASK_RM: {
15138 SDValue Src = Op.getOperand(1);
15139 SDValue PassThru = Op.getOperand(2);
15140 SDValue Mask = Op.getOperand(3);
15141 SDValue RoundingMode;
15142 if (Op.getNumOperands() == 4)
15143 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15145 RoundingMode = Op.getOperand(4);
15146 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15147 if (IntrWithRoundingModeOpcode != 0) {
15148 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15149 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15150 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15151 dl, Op.getValueType(), Src, RoundingMode),
15152 Mask, PassThru, Subtarget, DAG);
15154 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15156 Mask, PassThru, Subtarget, DAG);
15158 case INTR_TYPE_1OP_MASK: {
15159 SDValue Src = Op.getOperand(1);
15160 SDValue Passthru = Op.getOperand(2);
15161 SDValue Mask = Op.getOperand(3);
15162 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15163 Mask, Passthru, Subtarget, DAG);
15165 case INTR_TYPE_SCALAR_MASK_RM: {
15166 SDValue Src1 = Op.getOperand(1);
15167 SDValue Src2 = Op.getOperand(2);
15168 SDValue Src0 = Op.getOperand(3);
15169 SDValue Mask = Op.getOperand(4);
15170 // There are 2 kinds of intrinsics in this group:
15171 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15172 // (2) With rounding mode and sae - 7 operands.
15173 if (Op.getNumOperands() == 6) {
15174 SDValue Sae = Op.getOperand(5);
15175 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15176 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15178 Mask, Src0, Subtarget, DAG);
15180 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15181 SDValue RoundingMode = Op.getOperand(5);
15182 SDValue Sae = Op.getOperand(6);
15183 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15184 RoundingMode, Sae),
15185 Mask, Src0, Subtarget, DAG);
15187 case INTR_TYPE_2OP_MASK: {
15188 SDValue Src1 = Op.getOperand(1);
15189 SDValue Src2 = Op.getOperand(2);
15190 SDValue PassThru = Op.getOperand(3);
15191 SDValue Mask = Op.getOperand(4);
15192 // We specify 2 possible opcodes for intrinsics with rounding modes.
15193 // First, we check if the intrinsic may have non-default rounding mode,
15194 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15195 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15196 if (IntrWithRoundingModeOpcode != 0) {
15197 SDValue Rnd = Op.getOperand(5);
15198 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15199 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15200 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15201 dl, Op.getValueType(),
15203 Mask, PassThru, Subtarget, DAG);
15206 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15208 Mask, PassThru, Subtarget, DAG);
15210 case INTR_TYPE_3OP_MASK: {
15211 SDValue Src1 = Op.getOperand(1);
15212 SDValue Src2 = Op.getOperand(2);
15213 SDValue Src3 = Op.getOperand(3);
15214 SDValue PassThru = Op.getOperand(4);
15215 SDValue Mask = Op.getOperand(5);
15216 // We specify 2 possible opcodes for intrinsics with rounding modes.
15217 // First, we check if the intrinsic may have non-default rounding mode,
15218 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15219 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15220 if (IntrWithRoundingModeOpcode != 0) {
15221 SDValue Rnd = Op.getOperand(6);
15222 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15223 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15224 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15225 dl, Op.getValueType(),
15226 Src1, Src2, Src3, Rnd),
15227 Mask, PassThru, Subtarget, DAG);
15230 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15232 Mask, PassThru, Subtarget, DAG);
15234 case FMA_OP_MASK: {
15235 SDValue Src1 = Op.getOperand(1);
15236 SDValue Src2 = Op.getOperand(2);
15237 SDValue Src3 = Op.getOperand(3);
15238 SDValue Mask = Op.getOperand(4);
15239 // We specify 2 possible opcodes for intrinsics with rounding modes.
15240 // First, we check if the intrinsic may have non-default rounding mode,
15241 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15242 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15243 if (IntrWithRoundingModeOpcode != 0) {
15244 SDValue Rnd = Op.getOperand(5);
15245 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15246 X86::STATIC_ROUNDING::CUR_DIRECTION)
15247 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15248 dl, Op.getValueType(),
15249 Src1, Src2, Src3, Rnd),
15250 Mask, Src1, Subtarget, DAG);
15252 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15253 dl, Op.getValueType(),
15255 Mask, Src1, Subtarget, DAG);
15258 case CMP_MASK_CC: {
15259 // Comparison intrinsics with masks.
15260 // Example of transformation:
15261 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15262 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15264 // (v8i1 (insert_subvector undef,
15265 // (v2i1 (and (PCMPEQM %a, %b),
15266 // (extract_subvector
15267 // (v8i1 (bitcast %mask)), 0))), 0))))
15268 EVT VT = Op.getOperand(1).getValueType();
15269 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15270 VT.getVectorNumElements());
15271 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15272 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15273 Mask.getValueType().getSizeInBits());
15275 if (IntrData->Type == CMP_MASK_CC) {
15276 SDValue CC = Op.getOperand(3);
15277 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15278 // We specify 2 possible opcodes for intrinsics with rounding modes.
15279 // First, we check if the intrinsic may have non-default rounding mode,
15280 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15281 if (IntrData->Opc1 != 0) {
15282 SDValue Rnd = Op.getOperand(5);
15283 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15284 X86::STATIC_ROUNDING::CUR_DIRECTION)
15285 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15286 Op.getOperand(2), CC, Rnd);
15288 //default rounding mode
15290 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15291 Op.getOperand(2), CC);
15294 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15295 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15298 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15299 DAG.getTargetConstant(0, dl,
15302 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15303 DAG.getUNDEF(BitcastVT), CmpMask,
15304 DAG.getIntPtrConstant(0, dl));
15305 return DAG.getBitcast(Op.getValueType(), Res);
15307 case COMI: { // Comparison intrinsics
15308 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15309 SDValue LHS = Op.getOperand(1);
15310 SDValue RHS = Op.getOperand(2);
15311 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15312 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15313 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15314 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15315 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15316 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15319 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15320 Op.getOperand(1), Op.getOperand(2), DAG);
15322 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15323 Op.getSimpleValueType(),
15325 Op.getOperand(2), DAG),
15326 Op.getOperand(4), Op.getOperand(3), Subtarget,
15328 case COMPRESS_EXPAND_IN_REG: {
15329 SDValue Mask = Op.getOperand(3);
15330 SDValue DataToCompress = Op.getOperand(1);
15331 SDValue PassThru = Op.getOperand(2);
15332 if (isAllOnes(Mask)) // return data as is
15333 return Op.getOperand(1);
15334 EVT VT = Op.getValueType();
15335 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15336 VT.getVectorNumElements());
15337 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15338 Mask.getValueType().getSizeInBits());
15340 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15341 DAG.getBitcast(BitcastVT, Mask),
15342 DAG.getIntPtrConstant(0, dl));
15344 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
15348 SDValue Mask = Op.getOperand(3);
15349 EVT VT = Op.getValueType();
15350 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15351 VT.getVectorNumElements());
15352 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15353 Mask.getValueType().getSizeInBits());
15355 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15356 DAG.getBitcast(BitcastVT, Mask),
15357 DAG.getIntPtrConstant(0, dl));
15358 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15367 default: return SDValue(); // Don't custom lower most intrinsics.
15369 case Intrinsic::x86_avx2_permd:
15370 case Intrinsic::x86_avx2_permps:
15371 // Operands intentionally swapped. Mask is last operand to intrinsic,
15372 // but second operand for node/instruction.
15373 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15374 Op.getOperand(2), Op.getOperand(1));
15376 // ptest and testp intrinsics. The intrinsic these come from are designed to
15377 // return an integer value, not just an instruction so lower it to the ptest
15378 // or testp pattern and a setcc for the result.
15379 case Intrinsic::x86_sse41_ptestz:
15380 case Intrinsic::x86_sse41_ptestc:
15381 case Intrinsic::x86_sse41_ptestnzc:
15382 case Intrinsic::x86_avx_ptestz_256:
15383 case Intrinsic::x86_avx_ptestc_256:
15384 case Intrinsic::x86_avx_ptestnzc_256:
15385 case Intrinsic::x86_avx_vtestz_ps:
15386 case Intrinsic::x86_avx_vtestc_ps:
15387 case Intrinsic::x86_avx_vtestnzc_ps:
15388 case Intrinsic::x86_avx_vtestz_pd:
15389 case Intrinsic::x86_avx_vtestc_pd:
15390 case Intrinsic::x86_avx_vtestnzc_pd:
15391 case Intrinsic::x86_avx_vtestz_ps_256:
15392 case Intrinsic::x86_avx_vtestc_ps_256:
15393 case Intrinsic::x86_avx_vtestnzc_ps_256:
15394 case Intrinsic::x86_avx_vtestz_pd_256:
15395 case Intrinsic::x86_avx_vtestc_pd_256:
15396 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15397 bool IsTestPacked = false;
15400 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15401 case Intrinsic::x86_avx_vtestz_ps:
15402 case Intrinsic::x86_avx_vtestz_pd:
15403 case Intrinsic::x86_avx_vtestz_ps_256:
15404 case Intrinsic::x86_avx_vtestz_pd_256:
15405 IsTestPacked = true; // Fallthrough
15406 case Intrinsic::x86_sse41_ptestz:
15407 case Intrinsic::x86_avx_ptestz_256:
15409 X86CC = X86::COND_E;
15411 case Intrinsic::x86_avx_vtestc_ps:
15412 case Intrinsic::x86_avx_vtestc_pd:
15413 case Intrinsic::x86_avx_vtestc_ps_256:
15414 case Intrinsic::x86_avx_vtestc_pd_256:
15415 IsTestPacked = true; // Fallthrough
15416 case Intrinsic::x86_sse41_ptestc:
15417 case Intrinsic::x86_avx_ptestc_256:
15419 X86CC = X86::COND_B;
15421 case Intrinsic::x86_avx_vtestnzc_ps:
15422 case Intrinsic::x86_avx_vtestnzc_pd:
15423 case Intrinsic::x86_avx_vtestnzc_ps_256:
15424 case Intrinsic::x86_avx_vtestnzc_pd_256:
15425 IsTestPacked = true; // Fallthrough
15426 case Intrinsic::x86_sse41_ptestnzc:
15427 case Intrinsic::x86_avx_ptestnzc_256:
15429 X86CC = X86::COND_A;
15433 SDValue LHS = Op.getOperand(1);
15434 SDValue RHS = Op.getOperand(2);
15435 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15436 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15437 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15438 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15439 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15441 case Intrinsic::x86_avx512_kortestz_w:
15442 case Intrinsic::x86_avx512_kortestc_w: {
15443 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15444 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15445 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15446 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15447 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15448 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15449 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15452 case Intrinsic::x86_sse42_pcmpistria128:
15453 case Intrinsic::x86_sse42_pcmpestria128:
15454 case Intrinsic::x86_sse42_pcmpistric128:
15455 case Intrinsic::x86_sse42_pcmpestric128:
15456 case Intrinsic::x86_sse42_pcmpistrio128:
15457 case Intrinsic::x86_sse42_pcmpestrio128:
15458 case Intrinsic::x86_sse42_pcmpistris128:
15459 case Intrinsic::x86_sse42_pcmpestris128:
15460 case Intrinsic::x86_sse42_pcmpistriz128:
15461 case Intrinsic::x86_sse42_pcmpestriz128: {
15465 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15466 case Intrinsic::x86_sse42_pcmpistria128:
15467 Opcode = X86ISD::PCMPISTRI;
15468 X86CC = X86::COND_A;
15470 case Intrinsic::x86_sse42_pcmpestria128:
15471 Opcode = X86ISD::PCMPESTRI;
15472 X86CC = X86::COND_A;
15474 case Intrinsic::x86_sse42_pcmpistric128:
15475 Opcode = X86ISD::PCMPISTRI;
15476 X86CC = X86::COND_B;
15478 case Intrinsic::x86_sse42_pcmpestric128:
15479 Opcode = X86ISD::PCMPESTRI;
15480 X86CC = X86::COND_B;
15482 case Intrinsic::x86_sse42_pcmpistrio128:
15483 Opcode = X86ISD::PCMPISTRI;
15484 X86CC = X86::COND_O;
15486 case Intrinsic::x86_sse42_pcmpestrio128:
15487 Opcode = X86ISD::PCMPESTRI;
15488 X86CC = X86::COND_O;
15490 case Intrinsic::x86_sse42_pcmpistris128:
15491 Opcode = X86ISD::PCMPISTRI;
15492 X86CC = X86::COND_S;
15494 case Intrinsic::x86_sse42_pcmpestris128:
15495 Opcode = X86ISD::PCMPESTRI;
15496 X86CC = X86::COND_S;
15498 case Intrinsic::x86_sse42_pcmpistriz128:
15499 Opcode = X86ISD::PCMPISTRI;
15500 X86CC = X86::COND_E;
15502 case Intrinsic::x86_sse42_pcmpestriz128:
15503 Opcode = X86ISD::PCMPESTRI;
15504 X86CC = X86::COND_E;
15507 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15508 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15509 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15510 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15511 DAG.getConstant(X86CC, dl, MVT::i8),
15512 SDValue(PCMP.getNode(), 1));
15513 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15516 case Intrinsic::x86_sse42_pcmpistri128:
15517 case Intrinsic::x86_sse42_pcmpestri128: {
15519 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15520 Opcode = X86ISD::PCMPISTRI;
15522 Opcode = X86ISD::PCMPESTRI;
15524 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15525 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15526 return DAG.getNode(Opcode, dl, VTs, NewOps);
15529 case Intrinsic::x86_seh_lsda: {
15530 // Compute the symbol for the LSDA. We know it'll get emitted later.
15531 MachineFunction &MF = DAG.getMachineFunction();
15532 SDValue Op1 = Op.getOperand(1);
15533 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15534 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15535 GlobalValue::getRealLinkageName(Fn->getName()));
15536 StringRef Name = LSDASym->getName();
15537 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15539 // Generate a simple absolute symbol reference. This intrinsic is only
15540 // supported on 32-bit Windows, which isn't PIC.
15542 DAG.getTargetExternalSymbol(Name.data(), VT, X86II::MO_NOPREFIX);
15543 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15548 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15549 SDValue Src, SDValue Mask, SDValue Base,
15550 SDValue Index, SDValue ScaleOp, SDValue Chain,
15551 const X86Subtarget * Subtarget) {
15553 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15554 assert(C && "Invalid scale type");
15555 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15556 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15557 Index.getSimpleValueType().getVectorNumElements());
15559 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15561 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15563 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15564 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15565 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15566 SDValue Segment = DAG.getRegister(0, MVT::i32);
15567 if (Src.getOpcode() == ISD::UNDEF)
15568 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15569 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15570 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15571 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15572 return DAG.getMergeValues(RetOps, dl);
15575 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15576 SDValue Src, SDValue Mask, SDValue Base,
15577 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15579 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15580 assert(C && "Invalid scale type");
15581 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15582 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15583 SDValue Segment = DAG.getRegister(0, MVT::i32);
15584 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15585 Index.getSimpleValueType().getVectorNumElements());
15587 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15589 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15591 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15592 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15593 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15594 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15595 return SDValue(Res, 1);
15598 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15599 SDValue Mask, SDValue Base, SDValue Index,
15600 SDValue ScaleOp, SDValue Chain) {
15602 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15603 assert(C && "Invalid scale type");
15604 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15605 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15606 SDValue Segment = DAG.getRegister(0, MVT::i32);
15608 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15610 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15612 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15614 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15615 //SDVTList VTs = DAG.getVTList(MVT::Other);
15616 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15617 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15618 return SDValue(Res, 0);
15621 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15622 // read performance monitor counters (x86_rdpmc).
15623 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15624 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15625 SmallVectorImpl<SDValue> &Results) {
15626 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15627 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15630 // The ECX register is used to select the index of the performance counter
15632 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15634 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15636 // Reads the content of a 64-bit performance counter and returns it in the
15637 // registers EDX:EAX.
15638 if (Subtarget->is64Bit()) {
15639 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15640 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15643 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15644 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15647 Chain = HI.getValue(1);
15649 if (Subtarget->is64Bit()) {
15650 // The EAX register is loaded with the low-order 32 bits. The EDX register
15651 // is loaded with the supported high-order bits of the counter.
15652 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15653 DAG.getConstant(32, DL, MVT::i8));
15654 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15655 Results.push_back(Chain);
15659 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15660 SDValue Ops[] = { LO, HI };
15661 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15662 Results.push_back(Pair);
15663 Results.push_back(Chain);
15666 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15667 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15668 // also used to custom lower READCYCLECOUNTER nodes.
15669 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15670 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15671 SmallVectorImpl<SDValue> &Results) {
15672 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15673 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15676 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15677 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15678 // and the EAX register is loaded with the low-order 32 bits.
15679 if (Subtarget->is64Bit()) {
15680 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15681 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15684 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15685 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15688 SDValue Chain = HI.getValue(1);
15690 if (Opcode == X86ISD::RDTSCP_DAG) {
15691 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15693 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15694 // the ECX register. Add 'ecx' explicitly to the chain.
15695 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15697 // Explicitly store the content of ECX at the location passed in input
15698 // to the 'rdtscp' intrinsic.
15699 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15700 MachinePointerInfo(), false, false, 0);
15703 if (Subtarget->is64Bit()) {
15704 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15705 // the EAX register is loaded with the low-order 32 bits.
15706 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15707 DAG.getConstant(32, DL, MVT::i8));
15708 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15709 Results.push_back(Chain);
15713 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15714 SDValue Ops[] = { LO, HI };
15715 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15716 Results.push_back(Pair);
15717 Results.push_back(Chain);
15720 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15721 SelectionDAG &DAG) {
15722 SmallVector<SDValue, 2> Results;
15724 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15726 return DAG.getMergeValues(Results, DL);
15729 static SDValue LowerEXCEPTIONINFO(SDValue Op, const X86Subtarget *Subtarget,
15730 SelectionDAG &DAG) {
15731 MachineFunction &MF = DAG.getMachineFunction();
15733 SDValue FnOp = Op.getOperand(2);
15734 SDValue FPOp = Op.getOperand(3);
15736 // Compute the symbol for the parent EH registration. We know it'll get
15738 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(FnOp)->getGlobal());
15739 MCSymbol *ParentFrameSym =
15740 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15741 GlobalValue::getRealLinkageName(Fn->getName()));
15742 StringRef Name = ParentFrameSym->getName();
15743 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
15745 // Create a TargetExternalSymbol for the label to avoid any target lowering
15746 // that would make this PC relative.
15747 MVT PtrVT = Op.getSimpleValueType();
15748 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
15749 SDValue OffsetVal =
15750 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, dl, PtrVT, OffsetSym);
15752 // Add the offset to the FP.
15753 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, FPOp, OffsetVal);
15755 // Load the second field of the struct, which is 4 bytes in. See
15756 // WinEHStatePass for more info.
15757 Add = DAG.getNode(ISD::ADD, dl, PtrVT, Add, DAG.getConstant(4, dl, PtrVT));
15758 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Add, MachinePointerInfo(),
15759 false, false, false, 0);
15762 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15763 SelectionDAG &DAG) {
15764 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15766 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15768 if (IntNo == Intrinsic::x86_seh_exceptioninfo)
15769 return LowerEXCEPTIONINFO(Op, Subtarget, DAG);
15774 switch(IntrData->Type) {
15776 llvm_unreachable("Unknown Intrinsic Type");
15780 // Emit the node with the right value type.
15781 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15782 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15784 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15785 // Otherwise return the value from Rand, which is always 0, casted to i32.
15786 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15787 DAG.getConstant(1, dl, Op->getValueType(1)),
15788 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15789 SDValue(Result.getNode(), 1) };
15790 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15791 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15794 // Return { result, isValid, chain }.
15795 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15796 SDValue(Result.getNode(), 2));
15799 //gather(v1, mask, index, base, scale);
15800 SDValue Chain = Op.getOperand(0);
15801 SDValue Src = Op.getOperand(2);
15802 SDValue Base = Op.getOperand(3);
15803 SDValue Index = Op.getOperand(4);
15804 SDValue Mask = Op.getOperand(5);
15805 SDValue Scale = Op.getOperand(6);
15806 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15810 //scatter(base, mask, index, v1, scale);
15811 SDValue Chain = Op.getOperand(0);
15812 SDValue Base = Op.getOperand(2);
15813 SDValue Mask = Op.getOperand(3);
15814 SDValue Index = Op.getOperand(4);
15815 SDValue Src = Op.getOperand(5);
15816 SDValue Scale = Op.getOperand(6);
15817 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15821 SDValue Hint = Op.getOperand(6);
15822 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15823 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15824 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15825 SDValue Chain = Op.getOperand(0);
15826 SDValue Mask = Op.getOperand(2);
15827 SDValue Index = Op.getOperand(3);
15828 SDValue Base = Op.getOperand(4);
15829 SDValue Scale = Op.getOperand(5);
15830 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15832 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15834 SmallVector<SDValue, 2> Results;
15835 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15837 return DAG.getMergeValues(Results, dl);
15839 // Read Performance Monitoring Counters.
15841 SmallVector<SDValue, 2> Results;
15842 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15843 return DAG.getMergeValues(Results, dl);
15845 // XTEST intrinsics.
15847 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15848 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15849 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15850 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15852 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15853 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15854 Ret, SDValue(InTrans.getNode(), 1));
15858 SmallVector<SDValue, 2> Results;
15859 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15860 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15861 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15862 DAG.getConstant(-1, dl, MVT::i8));
15863 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15864 Op.getOperand(4), GenCF.getValue(1));
15865 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15866 Op.getOperand(5), MachinePointerInfo(),
15868 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15869 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15871 Results.push_back(SetCC);
15872 Results.push_back(Store);
15873 return DAG.getMergeValues(Results, dl);
15875 case COMPRESS_TO_MEM: {
15877 SDValue Mask = Op.getOperand(4);
15878 SDValue DataToCompress = Op.getOperand(3);
15879 SDValue Addr = Op.getOperand(2);
15880 SDValue Chain = Op.getOperand(0);
15882 EVT VT = DataToCompress.getValueType();
15883 if (isAllOnes(Mask)) // return just a store
15884 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15885 MachinePointerInfo(), false, false,
15886 VT.getScalarSizeInBits()/8);
15888 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15889 VT.getVectorNumElements());
15890 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15891 Mask.getValueType().getSizeInBits());
15892 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15893 DAG.getBitcast(BitcastVT, Mask),
15894 DAG.getIntPtrConstant(0, dl));
15896 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15897 DataToCompress, DAG.getUNDEF(VT));
15898 return DAG.getStore(Chain, dl, Compressed, Addr,
15899 MachinePointerInfo(), false, false,
15900 VT.getScalarSizeInBits()/8);
15902 case EXPAND_FROM_MEM: {
15904 SDValue Mask = Op.getOperand(4);
15905 SDValue PathThru = Op.getOperand(3);
15906 SDValue Addr = Op.getOperand(2);
15907 SDValue Chain = Op.getOperand(0);
15908 EVT VT = Op.getValueType();
15910 if (isAllOnes(Mask)) // return just a load
15911 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15912 false, VT.getScalarSizeInBits()/8);
15913 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15914 VT.getVectorNumElements());
15915 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15916 Mask.getValueType().getSizeInBits());
15917 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15918 DAG.getBitcast(BitcastVT, Mask),
15919 DAG.getIntPtrConstant(0, dl));
15921 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15922 false, false, false,
15923 VT.getScalarSizeInBits()/8);
15925 SDValue Results[] = {
15926 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15928 return DAG.getMergeValues(Results, dl);
15933 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15934 SelectionDAG &DAG) const {
15935 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15936 MFI->setReturnAddressIsTaken(true);
15938 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15941 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15943 EVT PtrVT = getPointerTy();
15946 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15947 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15948 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15949 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15950 DAG.getNode(ISD::ADD, dl, PtrVT,
15951 FrameAddr, Offset),
15952 MachinePointerInfo(), false, false, false, 0);
15955 // Just load the return address.
15956 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15957 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15958 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15961 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15962 MachineFunction &MF = DAG.getMachineFunction();
15963 MachineFrameInfo *MFI = MF.getFrameInfo();
15964 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15965 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15966 EVT VT = Op.getValueType();
15968 MFI->setFrameAddressIsTaken(true);
15970 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15971 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15972 // is not possible to crawl up the stack without looking at the unwind codes
15974 int FrameAddrIndex = FuncInfo->getFAIndex();
15975 if (!FrameAddrIndex) {
15976 // Set up a frame object for the return address.
15977 unsigned SlotSize = RegInfo->getSlotSize();
15978 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15979 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15980 FuncInfo->setFAIndex(FrameAddrIndex);
15982 return DAG.getFrameIndex(FrameAddrIndex, VT);
15985 unsigned FrameReg =
15986 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15987 SDLoc dl(Op); // FIXME probably not meaningful
15988 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15989 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15990 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15991 "Invalid Frame Register!");
15992 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15994 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15995 MachinePointerInfo(),
15996 false, false, false, 0);
16000 // FIXME? Maybe this could be a TableGen attribute on some registers and
16001 // this table could be generated automatically from RegInfo.
16002 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16004 unsigned Reg = StringSwitch<unsigned>(RegName)
16005 .Case("esp", X86::ESP)
16006 .Case("rsp", X86::RSP)
16010 report_fatal_error("Invalid register name global variable");
16013 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16014 SelectionDAG &DAG) const {
16015 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16016 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16019 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16020 SDValue Chain = Op.getOperand(0);
16021 SDValue Offset = Op.getOperand(1);
16022 SDValue Handler = Op.getOperand(2);
16025 EVT PtrVT = getPointerTy();
16026 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16027 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16028 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16029 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16030 "Invalid Frame Register!");
16031 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16032 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16034 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16035 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16037 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16038 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16040 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16042 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16043 DAG.getRegister(StoreAddrReg, PtrVT));
16046 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16047 SelectionDAG &DAG) const {
16049 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16050 DAG.getVTList(MVT::i32, MVT::Other),
16051 Op.getOperand(0), Op.getOperand(1));
16054 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16055 SelectionDAG &DAG) const {
16057 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16058 Op.getOperand(0), Op.getOperand(1));
16061 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16062 return Op.getOperand(0);
16065 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16066 SelectionDAG &DAG) const {
16067 SDValue Root = Op.getOperand(0);
16068 SDValue Trmp = Op.getOperand(1); // trampoline
16069 SDValue FPtr = Op.getOperand(2); // nested function
16070 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16073 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16074 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16076 if (Subtarget->is64Bit()) {
16077 SDValue OutChains[6];
16079 // Large code-model.
16080 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16081 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16083 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16084 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16086 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16088 // Load the pointer to the nested function into R11.
16089 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16090 SDValue Addr = Trmp;
16091 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16092 Addr, MachinePointerInfo(TrmpAddr),
16095 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16096 DAG.getConstant(2, dl, MVT::i64));
16097 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16098 MachinePointerInfo(TrmpAddr, 2),
16101 // Load the 'nest' parameter value into R10.
16102 // R10 is specified in X86CallingConv.td
16103 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16104 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16105 DAG.getConstant(10, dl, MVT::i64));
16106 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16107 Addr, MachinePointerInfo(TrmpAddr, 10),
16110 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16111 DAG.getConstant(12, dl, MVT::i64));
16112 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16113 MachinePointerInfo(TrmpAddr, 12),
16116 // Jump to the nested function.
16117 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16118 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16119 DAG.getConstant(20, dl, MVT::i64));
16120 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16121 Addr, MachinePointerInfo(TrmpAddr, 20),
16124 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16125 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16126 DAG.getConstant(22, dl, MVT::i64));
16127 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16128 Addr, MachinePointerInfo(TrmpAddr, 22),
16131 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16133 const Function *Func =
16134 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16135 CallingConv::ID CC = Func->getCallingConv();
16140 llvm_unreachable("Unsupported calling convention");
16141 case CallingConv::C:
16142 case CallingConv::X86_StdCall: {
16143 // Pass 'nest' parameter in ECX.
16144 // Must be kept in sync with X86CallingConv.td
16145 NestReg = X86::ECX;
16147 // Check that ECX wasn't needed by an 'inreg' parameter.
16148 FunctionType *FTy = Func->getFunctionType();
16149 const AttributeSet &Attrs = Func->getAttributes();
16151 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16152 unsigned InRegCount = 0;
16155 for (FunctionType::param_iterator I = FTy->param_begin(),
16156 E = FTy->param_end(); I != E; ++I, ++Idx)
16157 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16158 // FIXME: should only count parameters that are lowered to integers.
16159 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16161 if (InRegCount > 2) {
16162 report_fatal_error("Nest register in use - reduce number of inreg"
16168 case CallingConv::X86_FastCall:
16169 case CallingConv::X86_ThisCall:
16170 case CallingConv::Fast:
16171 // Pass 'nest' parameter in EAX.
16172 // Must be kept in sync with X86CallingConv.td
16173 NestReg = X86::EAX;
16177 SDValue OutChains[4];
16178 SDValue Addr, Disp;
16180 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16181 DAG.getConstant(10, dl, MVT::i32));
16182 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16184 // This is storing the opcode for MOV32ri.
16185 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16186 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16187 OutChains[0] = DAG.getStore(Root, dl,
16188 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16189 Trmp, MachinePointerInfo(TrmpAddr),
16192 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16193 DAG.getConstant(1, dl, MVT::i32));
16194 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16195 MachinePointerInfo(TrmpAddr, 1),
16198 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16199 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16200 DAG.getConstant(5, dl, MVT::i32));
16201 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16202 Addr, MachinePointerInfo(TrmpAddr, 5),
16205 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16206 DAG.getConstant(6, dl, MVT::i32));
16207 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16208 MachinePointerInfo(TrmpAddr, 6),
16211 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16215 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16216 SelectionDAG &DAG) const {
16218 The rounding mode is in bits 11:10 of FPSR, and has the following
16220 00 Round to nearest
16225 FLT_ROUNDS, on the other hand, expects the following:
16232 To perform the conversion, we do:
16233 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16236 MachineFunction &MF = DAG.getMachineFunction();
16237 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16238 unsigned StackAlignment = TFI.getStackAlignment();
16239 MVT VT = Op.getSimpleValueType();
16242 // Save FP Control Word to stack slot
16243 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16244 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16246 MachineMemOperand *MMO =
16247 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16248 MachineMemOperand::MOStore, 2, 2);
16250 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16251 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16252 DAG.getVTList(MVT::Other),
16253 Ops, MVT::i16, MMO);
16255 // Load FP Control Word from stack slot
16256 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16257 MachinePointerInfo(), false, false, false, 0);
16259 // Transform as necessary
16261 DAG.getNode(ISD::SRL, DL, MVT::i16,
16262 DAG.getNode(ISD::AND, DL, MVT::i16,
16263 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16264 DAG.getConstant(11, DL, MVT::i8));
16266 DAG.getNode(ISD::SRL, DL, MVT::i16,
16267 DAG.getNode(ISD::AND, DL, MVT::i16,
16268 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16269 DAG.getConstant(9, DL, MVT::i8));
16272 DAG.getNode(ISD::AND, DL, MVT::i16,
16273 DAG.getNode(ISD::ADD, DL, MVT::i16,
16274 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16275 DAG.getConstant(1, DL, MVT::i16)),
16276 DAG.getConstant(3, DL, MVT::i16));
16278 return DAG.getNode((VT.getSizeInBits() < 16 ?
16279 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16282 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16283 MVT VT = Op.getSimpleValueType();
16285 unsigned NumBits = VT.getSizeInBits();
16288 Op = Op.getOperand(0);
16289 if (VT == MVT::i8) {
16290 // Zero extend to i32 since there is not an i8 bsr.
16292 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16295 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16296 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16297 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16299 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16302 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16303 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16306 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16308 // Finally xor with NumBits-1.
16309 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16310 DAG.getConstant(NumBits - 1, dl, OpVT));
16313 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16317 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16318 MVT VT = Op.getSimpleValueType();
16320 unsigned NumBits = VT.getSizeInBits();
16323 Op = Op.getOperand(0);
16324 if (VT == MVT::i8) {
16325 // Zero extend to i32 since there is not an i8 bsr.
16327 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16330 // Issue a bsr (scan bits in reverse).
16331 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16332 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16334 // And xor with NumBits-1.
16335 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16336 DAG.getConstant(NumBits - 1, dl, OpVT));
16339 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16343 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16344 MVT VT = Op.getSimpleValueType();
16345 unsigned NumBits = VT.getSizeInBits();
16347 Op = Op.getOperand(0);
16349 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16350 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16351 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16353 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16356 DAG.getConstant(NumBits, dl, VT),
16357 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16360 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16363 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16364 // ones, and then concatenate the result back.
16365 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16366 MVT VT = Op.getSimpleValueType();
16368 assert(VT.is256BitVector() && VT.isInteger() &&
16369 "Unsupported value type for operation");
16371 unsigned NumElems = VT.getVectorNumElements();
16374 // Extract the LHS vectors
16375 SDValue LHS = Op.getOperand(0);
16376 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16377 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16379 // Extract the RHS vectors
16380 SDValue RHS = Op.getOperand(1);
16381 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16382 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16384 MVT EltVT = VT.getVectorElementType();
16385 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16387 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16388 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16389 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16392 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16393 if (Op.getValueType() == MVT::i1)
16394 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16395 Op.getOperand(0), Op.getOperand(1));
16396 assert(Op.getSimpleValueType().is256BitVector() &&
16397 Op.getSimpleValueType().isInteger() &&
16398 "Only handle AVX 256-bit vector integer operation");
16399 return Lower256IntArith(Op, DAG);
16402 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16403 if (Op.getValueType() == MVT::i1)
16404 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16405 Op.getOperand(0), Op.getOperand(1));
16406 assert(Op.getSimpleValueType().is256BitVector() &&
16407 Op.getSimpleValueType().isInteger() &&
16408 "Only handle AVX 256-bit vector integer operation");
16409 return Lower256IntArith(Op, DAG);
16412 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16413 SelectionDAG &DAG) {
16415 MVT VT = Op.getSimpleValueType();
16418 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16420 // Decompose 256-bit ops into smaller 128-bit ops.
16421 if (VT.is256BitVector() && !Subtarget->hasInt256())
16422 return Lower256IntArith(Op, DAG);
16424 SDValue A = Op.getOperand(0);
16425 SDValue B = Op.getOperand(1);
16427 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16428 // pairs, multiply and truncate.
16429 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16430 if (Subtarget->hasInt256()) {
16431 if (VT == MVT::v32i8) {
16432 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16433 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16434 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16435 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16436 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16437 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16438 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16439 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16440 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16441 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16444 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16445 return DAG.getNode(
16446 ISD::TRUNCATE, dl, VT,
16447 DAG.getNode(ISD::MUL, dl, ExVT,
16448 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16449 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16452 assert(VT == MVT::v16i8 &&
16453 "Pre-AVX2 support only supports v16i8 multiplication");
16454 MVT ExVT = MVT::v8i16;
16456 // Extract the lo parts and sign extend to i16
16458 if (Subtarget->hasSSE41()) {
16459 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16460 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16462 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16463 -1, 4, -1, 5, -1, 6, -1, 7};
16464 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16465 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16466 ALo = DAG.getBitcast(ExVT, ALo);
16467 BLo = DAG.getBitcast(ExVT, BLo);
16468 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16469 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16472 // Extract the hi parts and sign extend to i16
16474 if (Subtarget->hasSSE41()) {
16475 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16476 -1, -1, -1, -1, -1, -1, -1, -1};
16477 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16478 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16479 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16480 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16482 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16483 -1, 12, -1, 13, -1, 14, -1, 15};
16484 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16485 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16486 AHi = DAG.getBitcast(ExVT, AHi);
16487 BHi = DAG.getBitcast(ExVT, BHi);
16488 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16489 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16492 // Multiply, mask the lower 8bits of the lo/hi results and pack
16493 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16494 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16495 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16496 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16497 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16500 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16501 if (VT == MVT::v4i32) {
16502 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16503 "Should not custom lower when pmuldq is available!");
16505 // Extract the odd parts.
16506 static const int UnpackMask[] = { 1, -1, 3, -1 };
16507 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16508 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16510 // Multiply the even parts.
16511 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16512 // Now multiply odd parts.
16513 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16515 Evens = DAG.getBitcast(VT, Evens);
16516 Odds = DAG.getBitcast(VT, Odds);
16518 // Merge the two vectors back together with a shuffle. This expands into 2
16520 static const int ShufMask[] = { 0, 4, 2, 6 };
16521 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16524 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16525 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16527 // Ahi = psrlqi(a, 32);
16528 // Bhi = psrlqi(b, 32);
16530 // AloBlo = pmuludq(a, b);
16531 // AloBhi = pmuludq(a, Bhi);
16532 // AhiBlo = pmuludq(Ahi, b);
16534 // AloBhi = psllqi(AloBhi, 32);
16535 // AhiBlo = psllqi(AhiBlo, 32);
16536 // return AloBlo + AloBhi + AhiBlo;
16538 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16539 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16541 SDValue AhiBlo = Ahi;
16542 SDValue AloBhi = Bhi;
16543 // Bit cast to 32-bit vectors for MULUDQ
16544 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16545 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16546 A = DAG.getBitcast(MulVT, A);
16547 B = DAG.getBitcast(MulVT, B);
16548 Ahi = DAG.getBitcast(MulVT, Ahi);
16549 Bhi = DAG.getBitcast(MulVT, Bhi);
16551 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16552 // After shifting right const values the result may be all-zero.
16553 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
16554 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16555 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16557 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
16558 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16559 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16562 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16563 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16566 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16567 assert(Subtarget->isTargetWin64() && "Unexpected target");
16568 EVT VT = Op.getValueType();
16569 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16570 "Unexpected return type for lowering");
16574 switch (Op->getOpcode()) {
16575 default: llvm_unreachable("Unexpected request for libcall!");
16576 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16577 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16578 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16579 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16580 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16581 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16585 SDValue InChain = DAG.getEntryNode();
16587 TargetLowering::ArgListTy Args;
16588 TargetLowering::ArgListEntry Entry;
16589 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16590 EVT ArgVT = Op->getOperand(i).getValueType();
16591 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16592 "Unexpected argument type for lowering");
16593 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16594 Entry.Node = StackPtr;
16595 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16597 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16598 Entry.Ty = PointerType::get(ArgTy,0);
16599 Entry.isSExt = false;
16600 Entry.isZExt = false;
16601 Args.push_back(Entry);
16604 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16607 TargetLowering::CallLoweringInfo CLI(DAG);
16608 CLI.setDebugLoc(dl).setChain(InChain)
16609 .setCallee(getLibcallCallingConv(LC),
16610 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16611 Callee, std::move(Args), 0)
16612 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16614 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16615 return DAG.getBitcast(VT, CallInfo.first);
16618 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16619 SelectionDAG &DAG) {
16620 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16621 EVT VT = Op0.getValueType();
16624 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16625 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16627 // PMULxD operations multiply each even value (starting at 0) of LHS with
16628 // the related value of RHS and produce a widen result.
16629 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16630 // => <2 x i64> <ae|cg>
16632 // In other word, to have all the results, we need to perform two PMULxD:
16633 // 1. one with the even values.
16634 // 2. one with the odd values.
16635 // To achieve #2, with need to place the odd values at an even position.
16637 // Place the odd value at an even position (basically, shift all values 1
16638 // step to the left):
16639 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16640 // <a|b|c|d> => <b|undef|d|undef>
16641 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16642 // <e|f|g|h> => <f|undef|h|undef>
16643 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16645 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16647 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16648 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16650 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16651 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16652 // => <2 x i64> <ae|cg>
16653 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16654 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16655 // => <2 x i64> <bf|dh>
16656 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16658 // Shuffle it back into the right order.
16659 SDValue Highs, Lows;
16660 if (VT == MVT::v8i32) {
16661 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16662 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16663 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16664 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16666 const int HighMask[] = {1, 5, 3, 7};
16667 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16668 const int LowMask[] = {0, 4, 2, 6};
16669 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16672 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16673 // unsigned multiply.
16674 if (IsSigned && !Subtarget->hasSSE41()) {
16676 DAG.getConstant(31, dl,
16677 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16678 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16679 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16680 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16681 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16683 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16684 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16687 // The first result of MUL_LOHI is actually the low value, followed by the
16689 SDValue Ops[] = {Lows, Highs};
16690 return DAG.getMergeValues(Ops, dl);
16693 // Return true if the requred (according to Opcode) shift-imm form is natively
16694 // supported by the Subtarget
16695 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16697 if (VT.getScalarSizeInBits() < 16)
16700 if (VT.is512BitVector() &&
16701 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16704 bool LShift = VT.is128BitVector() ||
16705 (VT.is256BitVector() && Subtarget->hasInt256());
16707 bool AShift = LShift && (Subtarget->hasVLX() ||
16708 (VT != MVT::v2i64 && VT != MVT::v4i64));
16709 return (Opcode == ISD::SRA) ? AShift : LShift;
16712 // The shift amount is a variable, but it is the same for all vector lanes.
16713 // These instrcutions are defined together with shift-immediate.
16715 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16717 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16720 // Return true if the requred (according to Opcode) variable-shift form is
16721 // natively supported by the Subtarget
16722 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16725 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16728 // vXi16 supported only on AVX-512, BWI
16729 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16732 if (VT.is512BitVector() || Subtarget->hasVLX())
16735 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16736 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16737 return (Opcode == ISD::SRA) ? AShift : LShift;
16740 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16741 const X86Subtarget *Subtarget) {
16742 MVT VT = Op.getSimpleValueType();
16744 SDValue R = Op.getOperand(0);
16745 SDValue Amt = Op.getOperand(1);
16747 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16748 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16750 // Optimize shl/srl/sra with constant shift amount.
16751 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16752 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16753 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16755 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16756 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16758 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16759 unsigned NumElts = VT.getVectorNumElements();
16760 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16762 if (Op.getOpcode() == ISD::SHL) {
16763 // Simple i8 add case
16765 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16767 // Make a large shift.
16768 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16770 SHL = DAG.getBitcast(VT, SHL);
16771 // Zero out the rightmost bits.
16772 SmallVector<SDValue, 32> V(
16773 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16774 return DAG.getNode(ISD::AND, dl, VT, SHL,
16775 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16777 if (Op.getOpcode() == ISD::SRL) {
16778 // Make a large shift.
16779 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16781 SRL = DAG.getBitcast(VT, SRL);
16782 // Zero out the leftmost bits.
16783 SmallVector<SDValue, 32> V(
16784 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16785 return DAG.getNode(ISD::AND, dl, VT, SRL,
16786 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16788 if (Op.getOpcode() == ISD::SRA) {
16789 if (ShiftAmt == 7) {
16790 // R s>> 7 === R s< 0
16791 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16792 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16795 // R s>> a === ((R u>> a) ^ m) - m
16796 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16797 SmallVector<SDValue, 32> V(NumElts,
16798 DAG.getConstant(128 >> ShiftAmt, dl,
16800 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16801 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16802 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16805 llvm_unreachable("Unknown shift opcode.");
16810 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16811 if (!Subtarget->is64Bit() &&
16812 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16813 Amt.getOpcode() == ISD::BITCAST &&
16814 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16815 Amt = Amt.getOperand(0);
16816 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16817 VT.getVectorNumElements();
16818 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16819 uint64_t ShiftAmt = 0;
16820 for (unsigned i = 0; i != Ratio; ++i) {
16821 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16825 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16827 // Check remaining shift amounts.
16828 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16829 uint64_t ShAmt = 0;
16830 for (unsigned j = 0; j != Ratio; ++j) {
16831 ConstantSDNode *C =
16832 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16836 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16838 if (ShAmt != ShiftAmt)
16841 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16847 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16848 const X86Subtarget* Subtarget) {
16849 MVT VT = Op.getSimpleValueType();
16851 SDValue R = Op.getOperand(0);
16852 SDValue Amt = Op.getOperand(1);
16854 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16855 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16857 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16858 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16860 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16862 EVT EltVT = VT.getVectorElementType();
16864 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16865 // Check if this build_vector node is doing a splat.
16866 // If so, then set BaseShAmt equal to the splat value.
16867 BaseShAmt = BV->getSplatValue();
16868 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16869 BaseShAmt = SDValue();
16871 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16872 Amt = Amt.getOperand(0);
16874 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16875 if (SVN && SVN->isSplat()) {
16876 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16877 SDValue InVec = Amt.getOperand(0);
16878 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16879 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16880 "Unexpected shuffle index found!");
16881 BaseShAmt = InVec.getOperand(SplatIdx);
16882 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16883 if (ConstantSDNode *C =
16884 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16885 if (C->getZExtValue() == SplatIdx)
16886 BaseShAmt = InVec.getOperand(1);
16891 // Avoid introducing an extract element from a shuffle.
16892 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16893 DAG.getIntPtrConstant(SplatIdx, dl));
16897 if (BaseShAmt.getNode()) {
16898 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16899 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16900 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16901 else if (EltVT.bitsLT(MVT::i32))
16902 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16904 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16908 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16909 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16910 Amt.getOpcode() == ISD::BITCAST &&
16911 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16912 Amt = Amt.getOperand(0);
16913 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16914 VT.getVectorNumElements();
16915 std::vector<SDValue> Vals(Ratio);
16916 for (unsigned i = 0; i != Ratio; ++i)
16917 Vals[i] = Amt.getOperand(i);
16918 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16919 for (unsigned j = 0; j != Ratio; ++j)
16920 if (Vals[j] != Amt.getOperand(i + j))
16923 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16928 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16929 SelectionDAG &DAG) {
16930 MVT VT = Op.getSimpleValueType();
16932 SDValue R = Op.getOperand(0);
16933 SDValue Amt = Op.getOperand(1);
16935 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16936 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16938 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16941 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16944 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16947 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16948 // shifts per-lane and then shuffle the partial results back together.
16949 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16950 // Splat the shift amounts so the scalar shifts above will catch it.
16951 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16952 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16953 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16954 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16955 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16958 // If possible, lower this packed shift into a vector multiply instead of
16959 // expanding it into a sequence of scalar shifts.
16960 // Do this only if the vector shift count is a constant build_vector.
16961 if (Op.getOpcode() == ISD::SHL &&
16962 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16963 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16964 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16965 SmallVector<SDValue, 8> Elts;
16966 EVT SVT = VT.getScalarType();
16967 unsigned SVTBits = SVT.getSizeInBits();
16968 const APInt &One = APInt(SVTBits, 1);
16969 unsigned NumElems = VT.getVectorNumElements();
16971 for (unsigned i=0; i !=NumElems; ++i) {
16972 SDValue Op = Amt->getOperand(i);
16973 if (Op->getOpcode() == ISD::UNDEF) {
16974 Elts.push_back(Op);
16978 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16979 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16980 uint64_t ShAmt = C.getZExtValue();
16981 if (ShAmt >= SVTBits) {
16982 Elts.push_back(DAG.getUNDEF(SVT));
16985 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16987 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16988 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16991 // Lower SHL with variable shift amount.
16992 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16993 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16995 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16996 DAG.getConstant(0x3f800000U, dl, VT));
16997 Op = DAG.getBitcast(MVT::v4f32, Op);
16998 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16999 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17002 // If possible, lower this shift as a sequence of two shifts by
17003 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17005 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17007 // Could be rewritten as:
17008 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17010 // The advantage is that the two shifts from the example would be
17011 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17012 // the vector shift into four scalar shifts plus four pairs of vector
17014 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17015 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17016 unsigned TargetOpcode = X86ISD::MOVSS;
17017 bool CanBeSimplified;
17018 // The splat value for the first packed shift (the 'X' from the example).
17019 SDValue Amt1 = Amt->getOperand(0);
17020 // The splat value for the second packed shift (the 'Y' from the example).
17021 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17022 Amt->getOperand(2);
17024 // See if it is possible to replace this node with a sequence of
17025 // two shifts followed by a MOVSS/MOVSD
17026 if (VT == MVT::v4i32) {
17027 // Check if it is legal to use a MOVSS.
17028 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17029 Amt2 == Amt->getOperand(3);
17030 if (!CanBeSimplified) {
17031 // Otherwise, check if we can still simplify this node using a MOVSD.
17032 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17033 Amt->getOperand(2) == Amt->getOperand(3);
17034 TargetOpcode = X86ISD::MOVSD;
17035 Amt2 = Amt->getOperand(2);
17038 // Do similar checks for the case where the machine value type
17040 CanBeSimplified = Amt1 == Amt->getOperand(1);
17041 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17042 CanBeSimplified = Amt2 == Amt->getOperand(i);
17044 if (!CanBeSimplified) {
17045 TargetOpcode = X86ISD::MOVSD;
17046 CanBeSimplified = true;
17047 Amt2 = Amt->getOperand(4);
17048 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17049 CanBeSimplified = Amt1 == Amt->getOperand(i);
17050 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17051 CanBeSimplified = Amt2 == Amt->getOperand(j);
17055 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17056 isa<ConstantSDNode>(Amt2)) {
17057 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17058 EVT CastVT = MVT::v4i32;
17060 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17061 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17063 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17064 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17065 if (TargetOpcode == X86ISD::MOVSD)
17066 CastVT = MVT::v2i64;
17067 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17068 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17069 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17071 return DAG.getBitcast(VT, Result);
17075 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17076 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17077 unsigned ShiftOpcode = Op->getOpcode();
17079 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17080 // On SSE41 targets we make use of the fact that VSELECT lowers
17081 // to PBLENDVB which selects bytes based just on the sign bit.
17082 if (Subtarget->hasSSE41()) {
17083 V0 = DAG.getBitcast(VT, V0);
17084 V1 = DAG.getBitcast(VT, V1);
17085 Sel = DAG.getBitcast(VT, Sel);
17086 return DAG.getBitcast(SelVT,
17087 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17089 // On pre-SSE41 targets we test for the sign bit by comparing to
17090 // zero - a negative value will set all bits of the lanes to true
17091 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17092 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17093 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17094 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17097 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17098 // We can safely do this using i16 shifts as we're only interested in
17099 // the 3 lower bits of each byte.
17100 Amt = DAG.getBitcast(ExtVT, Amt);
17101 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17102 Amt = DAG.getBitcast(VT, Amt);
17104 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17105 // r = VSELECT(r, shift(r, 4), a);
17107 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17108 R = SignBitSelect(VT, Amt, M, R);
17111 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17113 // r = VSELECT(r, shift(r, 2), a);
17114 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17115 R = SignBitSelect(VT, Amt, M, R);
17118 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17120 // return VSELECT(r, shift(r, 1), a);
17121 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17122 R = SignBitSelect(VT, Amt, M, R);
17126 if (Op->getOpcode() == ISD::SRA) {
17127 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17128 // so we can correctly sign extend. We don't care what happens to the
17130 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17131 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17132 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17133 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17134 ALo = DAG.getBitcast(ExtVT, ALo);
17135 AHi = DAG.getBitcast(ExtVT, AHi);
17136 RLo = DAG.getBitcast(ExtVT, RLo);
17137 RHi = DAG.getBitcast(ExtVT, RHi);
17139 // r = VSELECT(r, shift(r, 4), a);
17140 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17141 DAG.getConstant(4, dl, ExtVT));
17142 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17143 DAG.getConstant(4, dl, ExtVT));
17144 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17145 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17148 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17149 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17151 // r = VSELECT(r, shift(r, 2), a);
17152 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17153 DAG.getConstant(2, dl, ExtVT));
17154 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17155 DAG.getConstant(2, dl, ExtVT));
17156 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17157 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17160 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17161 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17163 // r = VSELECT(r, shift(r, 1), a);
17164 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17165 DAG.getConstant(1, dl, ExtVT));
17166 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17167 DAG.getConstant(1, dl, ExtVT));
17168 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17169 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17171 // Logical shift the result back to the lower byte, leaving a zero upper
17173 // meaning that we can safely pack with PACKUSWB.
17175 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17177 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17178 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17182 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17183 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17184 // solution better.
17185 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17186 MVT ExtVT = MVT::v8i32;
17188 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17189 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17190 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17191 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17192 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17195 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17196 MVT ExtVT = MVT::v8i32;
17197 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17198 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17199 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17200 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17201 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17202 ALo = DAG.getBitcast(ExtVT, ALo);
17203 AHi = DAG.getBitcast(ExtVT, AHi);
17204 RLo = DAG.getBitcast(ExtVT, RLo);
17205 RHi = DAG.getBitcast(ExtVT, RHi);
17206 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17207 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17208 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17209 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17210 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17213 if (VT == MVT::v8i16) {
17214 unsigned ShiftOpcode = Op->getOpcode();
17216 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17217 // On SSE41 targets we make use of the fact that VSELECT lowers
17218 // to PBLENDVB which selects bytes based just on the sign bit.
17219 if (Subtarget->hasSSE41()) {
17220 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17221 V0 = DAG.getBitcast(ExtVT, V0);
17222 V1 = DAG.getBitcast(ExtVT, V1);
17223 Sel = DAG.getBitcast(ExtVT, Sel);
17224 return DAG.getBitcast(
17225 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17227 // On pre-SSE41 targets we splat the sign bit - a negative value will
17228 // set all bits of the lanes to true and VSELECT uses that in
17229 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17231 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17232 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17235 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17236 if (Subtarget->hasSSE41()) {
17237 // On SSE41 targets we need to replicate the shift mask in both
17238 // bytes for PBLENDVB.
17241 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17242 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17244 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17247 // r = VSELECT(r, shift(r, 8), a);
17248 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17249 R = SignBitSelect(Amt, M, R);
17252 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17254 // r = VSELECT(r, shift(r, 4), a);
17255 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17256 R = SignBitSelect(Amt, M, R);
17259 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17261 // r = VSELECT(r, shift(r, 2), a);
17262 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17263 R = SignBitSelect(Amt, M, R);
17266 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17268 // return VSELECT(r, shift(r, 1), a);
17269 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17270 R = SignBitSelect(Amt, M, R);
17274 // Decompose 256-bit shifts into smaller 128-bit shifts.
17275 if (VT.is256BitVector()) {
17276 unsigned NumElems = VT.getVectorNumElements();
17277 MVT EltVT = VT.getVectorElementType();
17278 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17280 // Extract the two vectors
17281 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17282 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17284 // Recreate the shift amount vectors
17285 SDValue Amt1, Amt2;
17286 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17287 // Constant shift amount
17288 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17289 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17290 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17292 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17293 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17295 // Variable shift amount
17296 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17297 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17300 // Issue new vector shifts for the smaller types
17301 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17302 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17304 // Concatenate the result back
17305 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17311 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17312 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17313 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17314 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17315 // has only one use.
17316 SDNode *N = Op.getNode();
17317 SDValue LHS = N->getOperand(0);
17318 SDValue RHS = N->getOperand(1);
17319 unsigned BaseOp = 0;
17322 switch (Op.getOpcode()) {
17323 default: llvm_unreachable("Unknown ovf instruction!");
17325 // A subtract of one will be selected as a INC. Note that INC doesn't
17326 // set CF, so we can't do this for UADDO.
17327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17329 BaseOp = X86ISD::INC;
17330 Cond = X86::COND_O;
17333 BaseOp = X86ISD::ADD;
17334 Cond = X86::COND_O;
17337 BaseOp = X86ISD::ADD;
17338 Cond = X86::COND_B;
17341 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17342 // set CF, so we can't do this for USUBO.
17343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17345 BaseOp = X86ISD::DEC;
17346 Cond = X86::COND_O;
17349 BaseOp = X86ISD::SUB;
17350 Cond = X86::COND_O;
17353 BaseOp = X86ISD::SUB;
17354 Cond = X86::COND_B;
17357 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17358 Cond = X86::COND_O;
17360 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17361 if (N->getValueType(0) == MVT::i8) {
17362 BaseOp = X86ISD::UMUL8;
17363 Cond = X86::COND_O;
17366 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17368 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17371 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17372 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17373 SDValue(Sum.getNode(), 2));
17375 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17379 // Also sets EFLAGS.
17380 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17381 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17384 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17385 DAG.getConstant(Cond, DL, MVT::i32),
17386 SDValue(Sum.getNode(), 1));
17388 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17391 /// Returns true if the operand type is exactly twice the native width, and
17392 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17393 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17394 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17395 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17396 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17399 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17400 else if (OpWidth == 128)
17401 return Subtarget->hasCmpxchg16b();
17406 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17407 return needsCmpXchgNb(SI->getValueOperand()->getType());
17410 // Note: this turns large loads into lock cmpxchg8b/16b.
17411 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17412 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17413 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17414 return needsCmpXchgNb(PTy->getElementType());
17417 TargetLoweringBase::AtomicRMWExpansionKind
17418 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17419 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17420 const Type *MemType = AI->getType();
17422 // If the operand is too big, we must see if cmpxchg8/16b is available
17423 // and default to library calls otherwise.
17424 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17425 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17426 : AtomicRMWExpansionKind::None;
17429 AtomicRMWInst::BinOp Op = AI->getOperation();
17432 llvm_unreachable("Unknown atomic operation");
17433 case AtomicRMWInst::Xchg:
17434 case AtomicRMWInst::Add:
17435 case AtomicRMWInst::Sub:
17436 // It's better to use xadd, xsub or xchg for these in all cases.
17437 return AtomicRMWExpansionKind::None;
17438 case AtomicRMWInst::Or:
17439 case AtomicRMWInst::And:
17440 case AtomicRMWInst::Xor:
17441 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17442 // prefix to a normal instruction for these operations.
17443 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17444 : AtomicRMWExpansionKind::None;
17445 case AtomicRMWInst::Nand:
17446 case AtomicRMWInst::Max:
17447 case AtomicRMWInst::Min:
17448 case AtomicRMWInst::UMax:
17449 case AtomicRMWInst::UMin:
17450 // These always require a non-trivial set of data operations on x86. We must
17451 // use a cmpxchg loop.
17452 return AtomicRMWExpansionKind::CmpXChg;
17456 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17457 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17458 // no-sse2). There isn't any reason to disable it if the target processor
17460 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17464 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17465 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17466 const Type *MemType = AI->getType();
17467 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17468 // there is no benefit in turning such RMWs into loads, and it is actually
17469 // harmful as it introduces a mfence.
17470 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17473 auto Builder = IRBuilder<>(AI);
17474 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17475 auto SynchScope = AI->getSynchScope();
17476 // We must restrict the ordering to avoid generating loads with Release or
17477 // ReleaseAcquire orderings.
17478 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17479 auto Ptr = AI->getPointerOperand();
17481 // Before the load we need a fence. Here is an example lifted from
17482 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17485 // x.store(1, relaxed);
17486 // r1 = y.fetch_add(0, release);
17488 // y.fetch_add(42, acquire);
17489 // r2 = x.load(relaxed);
17490 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17491 // lowered to just a load without a fence. A mfence flushes the store buffer,
17492 // making the optimization clearly correct.
17493 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17494 // otherwise, we might be able to be more agressive on relaxed idempotent
17495 // rmw. In practice, they do not look useful, so we don't try to be
17496 // especially clever.
17497 if (SynchScope == SingleThread)
17498 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17499 // the IR level, so we must wrap it in an intrinsic.
17502 if (!hasMFENCE(*Subtarget))
17503 // FIXME: it might make sense to use a locked operation here but on a
17504 // different cache-line to prevent cache-line bouncing. In practice it
17505 // is probably a small win, and x86 processors without mfence are rare
17506 // enough that we do not bother.
17510 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17511 Builder.CreateCall(MFence, {});
17513 // Finally we can emit the atomic load.
17514 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17515 AI->getType()->getPrimitiveSizeInBits());
17516 Loaded->setAtomic(Order, SynchScope);
17517 AI->replaceAllUsesWith(Loaded);
17518 AI->eraseFromParent();
17522 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17523 SelectionDAG &DAG) {
17525 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17526 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17527 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17528 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17530 // The only fence that needs an instruction is a sequentially-consistent
17531 // cross-thread fence.
17532 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17533 if (hasMFENCE(*Subtarget))
17534 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17536 SDValue Chain = Op.getOperand(0);
17537 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17539 DAG.getRegister(X86::ESP, MVT::i32), // Base
17540 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17541 DAG.getRegister(0, MVT::i32), // Index
17542 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17543 DAG.getRegister(0, MVT::i32), // Segment.
17547 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17548 return SDValue(Res, 0);
17551 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17552 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17555 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17556 SelectionDAG &DAG) {
17557 MVT T = Op.getSimpleValueType();
17561 switch(T.SimpleTy) {
17562 default: llvm_unreachable("Invalid value type!");
17563 case MVT::i8: Reg = X86::AL; size = 1; break;
17564 case MVT::i16: Reg = X86::AX; size = 2; break;
17565 case MVT::i32: Reg = X86::EAX; size = 4; break;
17567 assert(Subtarget->is64Bit() && "Node not type legal!");
17568 Reg = X86::RAX; size = 8;
17571 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17572 Op.getOperand(2), SDValue());
17573 SDValue Ops[] = { cpIn.getValue(0),
17576 DAG.getTargetConstant(size, DL, MVT::i8),
17577 cpIn.getValue(1) };
17578 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17579 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17580 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17584 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17585 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17586 MVT::i32, cpOut.getValue(2));
17587 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17588 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17591 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17592 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17593 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17597 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17598 SelectionDAG &DAG) {
17599 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17600 MVT DstVT = Op.getSimpleValueType();
17602 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17603 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17604 if (DstVT != MVT::f64)
17605 // This conversion needs to be expanded.
17608 SDValue InVec = Op->getOperand(0);
17610 unsigned NumElts = SrcVT.getVectorNumElements();
17611 EVT SVT = SrcVT.getVectorElementType();
17613 // Widen the vector in input in the case of MVT::v2i32.
17614 // Example: from MVT::v2i32 to MVT::v4i32.
17615 SmallVector<SDValue, 16> Elts;
17616 for (unsigned i = 0, e = NumElts; i != e; ++i)
17617 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17618 DAG.getIntPtrConstant(i, dl)));
17620 // Explicitly mark the extra elements as Undef.
17621 Elts.append(NumElts, DAG.getUNDEF(SVT));
17623 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17624 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17625 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17626 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17627 DAG.getIntPtrConstant(0, dl));
17630 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17631 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17632 assert((DstVT == MVT::i64 ||
17633 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17634 "Unexpected custom BITCAST");
17635 // i64 <=> MMX conversions are Legal.
17636 if (SrcVT==MVT::i64 && DstVT.isVector())
17638 if (DstVT==MVT::i64 && SrcVT.isVector())
17640 // MMX <=> MMX conversions are Legal.
17641 if (SrcVT.isVector() && DstVT.isVector())
17643 // All other conversions need to be expanded.
17647 /// Compute the horizontal sum of bytes in V for the elements of VT.
17649 /// Requires V to be a byte vector and VT to be an integer vector type with
17650 /// wider elements than V's type. The width of the elements of VT determines
17651 /// how many bytes of V are summed horizontally to produce each element of the
17653 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17654 const X86Subtarget *Subtarget,
17655 SelectionDAG &DAG) {
17657 MVT ByteVecVT = V.getSimpleValueType();
17658 MVT EltVT = VT.getVectorElementType();
17659 int NumElts = VT.getVectorNumElements();
17660 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17661 "Expected value to have byte element type.");
17662 assert(EltVT != MVT::i8 &&
17663 "Horizontal byte sum only makes sense for wider elements!");
17664 unsigned VecSize = VT.getSizeInBits();
17665 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17667 // PSADBW instruction horizontally add all bytes and leave the result in i64
17668 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17669 if (EltVT == MVT::i64) {
17670 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17671 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17672 return DAG.getBitcast(VT, V);
17675 if (EltVT == MVT::i32) {
17676 // We unpack the low half and high half into i32s interleaved with zeros so
17677 // that we can use PSADBW to horizontally sum them. The most useful part of
17678 // this is that it lines up the results of two PSADBW instructions to be
17679 // two v2i64 vectors which concatenated are the 4 population counts. We can
17680 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17681 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17682 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17683 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17685 // Do the horizontal sums into two v2i64s.
17686 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17687 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17688 DAG.getBitcast(ByteVecVT, Low), Zeros);
17689 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17690 DAG.getBitcast(ByteVecVT, High), Zeros);
17692 // Merge them together.
17693 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17694 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17695 DAG.getBitcast(ShortVecVT, Low),
17696 DAG.getBitcast(ShortVecVT, High));
17698 return DAG.getBitcast(VT, V);
17701 // The only element type left is i16.
17702 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17704 // To obtain pop count for each i16 element starting from the pop count for
17705 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
17706 // right by 8. It is important to shift as i16s as i8 vector shift isn't
17707 // directly supported.
17708 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
17709 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
17710 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17711 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
17712 DAG.getBitcast(ByteVecVT, V));
17713 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17716 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17717 const X86Subtarget *Subtarget,
17718 SelectionDAG &DAG) {
17719 MVT VT = Op.getSimpleValueType();
17720 MVT EltVT = VT.getVectorElementType();
17721 unsigned VecSize = VT.getSizeInBits();
17723 // Implement a lookup table in register by using an algorithm based on:
17724 // http://wm.ite.pl/articles/sse-popcount.html
17726 // The general idea is that every lower byte nibble in the input vector is an
17727 // index into a in-register pre-computed pop count table. We then split up the
17728 // input vector in two new ones: (1) a vector with only the shifted-right
17729 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17730 // masked out higher ones) for each byte. PSHUB is used separately with both
17731 // to index the in-register table. Next, both are added and the result is a
17732 // i8 vector where each element contains the pop count for input byte.
17734 // To obtain the pop count for elements != i8, we follow up with the same
17735 // approach and use additional tricks as described below.
17737 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17738 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17739 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17740 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17742 int NumByteElts = VecSize / 8;
17743 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
17744 SDValue In = DAG.getBitcast(ByteVecVT, Op);
17745 SmallVector<SDValue, 16> LUTVec;
17746 for (int i = 0; i < NumByteElts; ++i)
17747 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
17748 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
17749 SmallVector<SDValue, 16> Mask0F(NumByteElts,
17750 DAG.getConstant(0x0F, DL, MVT::i8));
17751 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
17754 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
17755 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
17756 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
17759 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
17761 // The input vector is used as the shuffle mask that index elements into the
17762 // LUT. After counting low and high nibbles, add the vector to obtain the
17763 // final pop count per i8 element.
17764 SDValue HighPopCnt =
17765 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
17766 SDValue LowPopCnt =
17767 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
17768 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
17770 if (EltVT == MVT::i8)
17773 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
17776 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17777 const X86Subtarget *Subtarget,
17778 SelectionDAG &DAG) {
17779 MVT VT = Op.getSimpleValueType();
17780 assert(VT.is128BitVector() &&
17781 "Only 128-bit vector bitmath lowering supported.");
17783 int VecSize = VT.getSizeInBits();
17784 MVT EltVT = VT.getVectorElementType();
17785 int Len = EltVT.getSizeInBits();
17787 // This is the vectorized version of the "best" algorithm from
17788 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17789 // with a minor tweak to use a series of adds + shifts instead of vector
17790 // multiplications. Implemented for all integer vector types. We only use
17791 // this when we don't have SSSE3 which allows a LUT-based lowering that is
17792 // much faster, even faster than using native popcnt instructions.
17794 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
17795 MVT VT = V.getSimpleValueType();
17796 SmallVector<SDValue, 32> Shifters(
17797 VT.getVectorNumElements(),
17798 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
17799 return DAG.getNode(OpCode, DL, VT, V,
17800 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
17802 auto GetMask = [&](SDValue V, APInt Mask) {
17803 MVT VT = V.getSimpleValueType();
17804 SmallVector<SDValue, 32> Masks(
17805 VT.getVectorNumElements(),
17806 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
17807 return DAG.getNode(ISD::AND, DL, VT, V,
17808 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
17811 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
17812 // x86, so set the SRL type to have elements at least i16 wide. This is
17813 // correct because all of our SRLs are followed immediately by a mask anyways
17814 // that handles any bits that sneak into the high bits of the byte elements.
17815 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
17819 // v = v - ((v >> 1) & 0x55555555...)
17821 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
17822 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
17823 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
17825 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17826 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
17827 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
17828 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
17829 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
17831 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17832 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
17833 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
17834 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
17836 // At this point, V contains the byte-wise population count, and we are
17837 // merely doing a horizontal sum if necessary to get the wider element
17839 if (EltVT == MVT::i8)
17842 return LowerHorizontalByteSum(
17843 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
17847 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17848 SelectionDAG &DAG) {
17849 MVT VT = Op.getSimpleValueType();
17850 // FIXME: Need to add AVX-512 support here!
17851 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17852 "Unknown CTPOP type to handle");
17853 SDLoc DL(Op.getNode());
17854 SDValue Op0 = Op.getOperand(0);
17856 if (!Subtarget->hasSSSE3()) {
17857 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
17858 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
17859 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
17862 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
17863 unsigned NumElems = VT.getVectorNumElements();
17865 // Extract each 128-bit vector, compute pop count and concat the result.
17866 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
17867 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
17869 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
17870 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
17871 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
17874 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
17877 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17878 SelectionDAG &DAG) {
17879 assert(Op.getValueType().isVector() &&
17880 "We only do custom lowering for vector population count.");
17881 return LowerVectorCTPOP(Op, Subtarget, DAG);
17884 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17885 SDNode *Node = Op.getNode();
17887 EVT T = Node->getValueType(0);
17888 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17889 DAG.getConstant(0, dl, T), Node->getOperand(2));
17890 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17891 cast<AtomicSDNode>(Node)->getMemoryVT(),
17892 Node->getOperand(0),
17893 Node->getOperand(1), negOp,
17894 cast<AtomicSDNode>(Node)->getMemOperand(),
17895 cast<AtomicSDNode>(Node)->getOrdering(),
17896 cast<AtomicSDNode>(Node)->getSynchScope());
17899 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17900 SDNode *Node = Op.getNode();
17902 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17904 // Convert seq_cst store -> xchg
17905 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17906 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17907 // (The only way to get a 16-byte store is cmpxchg16b)
17908 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17909 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17910 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17911 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17912 cast<AtomicSDNode>(Node)->getMemoryVT(),
17913 Node->getOperand(0),
17914 Node->getOperand(1), Node->getOperand(2),
17915 cast<AtomicSDNode>(Node)->getMemOperand(),
17916 cast<AtomicSDNode>(Node)->getOrdering(),
17917 cast<AtomicSDNode>(Node)->getSynchScope());
17918 return Swap.getValue(1);
17920 // Other atomic stores have a simple pattern.
17924 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17925 EVT VT = Op.getNode()->getSimpleValueType(0);
17927 // Let legalize expand this if it isn't a legal type yet.
17928 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17931 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17934 bool ExtraOp = false;
17935 switch (Op.getOpcode()) {
17936 default: llvm_unreachable("Invalid code");
17937 case ISD::ADDC: Opc = X86ISD::ADD; break;
17938 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17939 case ISD::SUBC: Opc = X86ISD::SUB; break;
17940 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17944 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17946 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17947 Op.getOperand(1), Op.getOperand(2));
17950 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17951 SelectionDAG &DAG) {
17952 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17954 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17955 // which returns the values as { float, float } (in XMM0) or
17956 // { double, double } (which is returned in XMM0, XMM1).
17958 SDValue Arg = Op.getOperand(0);
17959 EVT ArgVT = Arg.getValueType();
17960 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17962 TargetLowering::ArgListTy Args;
17963 TargetLowering::ArgListEntry Entry;
17967 Entry.isSExt = false;
17968 Entry.isZExt = false;
17969 Args.push_back(Entry);
17971 bool isF64 = ArgVT == MVT::f64;
17972 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17973 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17974 // the results are returned via SRet in memory.
17975 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17976 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17977 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17979 Type *RetTy = isF64
17980 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17981 : (Type*)VectorType::get(ArgTy, 4);
17983 TargetLowering::CallLoweringInfo CLI(DAG);
17984 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17985 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17987 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17990 // Returned in xmm0 and xmm1.
17991 return CallResult.first;
17993 // Returned in bits 0:31 and 32:64 xmm0.
17994 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17995 CallResult.first, DAG.getIntPtrConstant(0, dl));
17996 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17997 CallResult.first, DAG.getIntPtrConstant(1, dl));
17998 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17999 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18002 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
18003 SelectionDAG &DAG) {
18004 assert(Subtarget->hasAVX512() &&
18005 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18007 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
18008 EVT VT = N->getValue().getValueType();
18009 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
18012 // X86 scatter kills mask register, so its type should be added to
18013 // the list of return values
18014 if (N->getNumValues() == 1) {
18015 SDValue Index = N->getIndex();
18016 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18017 !Index.getValueType().is512BitVector())
18018 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18020 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
18021 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18022 N->getOperand(3), Index };
18024 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
18025 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
18026 return SDValue(NewScatter.getNode(), 0);
18031 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
18032 SelectionDAG &DAG) {
18033 assert(Subtarget->hasAVX512() &&
18034 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18036 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
18037 EVT VT = Op.getValueType();
18038 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
18041 SDValue Index = N->getIndex();
18042 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18043 !Index.getValueType().is512BitVector()) {
18044 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18045 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18046 N->getOperand(3), Index };
18047 DAG.UpdateNodeOperands(N, Ops);
18052 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18053 SelectionDAG &DAG) const {
18054 // TODO: Eventually, the lowering of these nodes should be informed by or
18055 // deferred to the GC strategy for the function in which they appear. For
18056 // now, however, they must be lowered to something. Since they are logically
18057 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18058 // require special handling for these nodes), lower them as literal NOOPs for
18060 SmallVector<SDValue, 2> Ops;
18062 Ops.push_back(Op.getOperand(0));
18063 if (Op->getGluedNode())
18064 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18067 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18068 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18073 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18074 SelectionDAG &DAG) const {
18075 // TODO: Eventually, the lowering of these nodes should be informed by or
18076 // deferred to the GC strategy for the function in which they appear. For
18077 // now, however, they must be lowered to something. Since they are logically
18078 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18079 // require special handling for these nodes), lower them as literal NOOPs for
18081 SmallVector<SDValue, 2> Ops;
18083 Ops.push_back(Op.getOperand(0));
18084 if (Op->getGluedNode())
18085 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18088 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18089 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18094 /// LowerOperation - Provide custom lowering hooks for some operations.
18096 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18097 switch (Op.getOpcode()) {
18098 default: llvm_unreachable("Should not custom lower this!");
18099 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18100 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18101 return LowerCMP_SWAP(Op, Subtarget, DAG);
18102 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18103 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18104 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18105 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18106 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18107 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18108 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18109 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18110 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18111 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18112 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18113 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18114 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18115 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18116 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18117 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18118 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18119 case ISD::SHL_PARTS:
18120 case ISD::SRA_PARTS:
18121 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18122 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18123 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18124 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18125 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18126 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18127 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18128 case ISD::SIGN_EXTEND_VECTOR_INREG:
18129 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18130 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18131 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18132 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18133 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18135 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18136 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18137 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18138 case ISD::SETCC: return LowerSETCC(Op, DAG);
18139 case ISD::SELECT: return LowerSELECT(Op, DAG);
18140 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18141 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18142 case ISD::VASTART: return LowerVASTART(Op, DAG);
18143 case ISD::VAARG: return LowerVAARG(Op, DAG);
18144 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18145 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18146 case ISD::INTRINSIC_VOID:
18147 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18148 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18149 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18150 case ISD::FRAME_TO_ARGS_OFFSET:
18151 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18152 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18153 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18154 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18155 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18156 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18157 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18158 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18159 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18160 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18161 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18162 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18163 case ISD::UMUL_LOHI:
18164 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18167 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18173 case ISD::UMULO: return LowerXALUO(Op, DAG);
18174 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18175 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18179 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18180 case ISD::ADD: return LowerADD(Op, DAG);
18181 case ISD::SUB: return LowerSUB(Op, DAG);
18182 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18183 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18184 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18185 case ISD::GC_TRANSITION_START:
18186 return LowerGC_TRANSITION_START(Op, DAG);
18187 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18191 /// ReplaceNodeResults - Replace a node with an illegal result type
18192 /// with a new node built out of custom code.
18193 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18194 SmallVectorImpl<SDValue>&Results,
18195 SelectionDAG &DAG) const {
18197 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18198 switch (N->getOpcode()) {
18200 llvm_unreachable("Do not know how to custom type legalize this operation!");
18201 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18202 case X86ISD::FMINC:
18204 case X86ISD::FMAXC:
18205 case X86ISD::FMAX: {
18206 EVT VT = N->getValueType(0);
18207 if (VT != MVT::v2f32)
18208 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18209 SDValue UNDEF = DAG.getUNDEF(VT);
18210 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18211 N->getOperand(0), UNDEF);
18212 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18213 N->getOperand(1), UNDEF);
18214 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18217 case ISD::SIGN_EXTEND_INREG:
18222 // We don't want to expand or promote these.
18229 case ISD::UDIVREM: {
18230 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18231 Results.push_back(V);
18234 case ISD::FP_TO_SINT:
18235 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18236 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18237 if (N->getOperand(0).getValueType() == MVT::f16)
18240 case ISD::FP_TO_UINT: {
18241 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18243 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18246 std::pair<SDValue,SDValue> Vals =
18247 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18248 SDValue FIST = Vals.first, StackSlot = Vals.second;
18249 if (FIST.getNode()) {
18250 EVT VT = N->getValueType(0);
18251 // Return a load from the stack slot.
18252 if (StackSlot.getNode())
18253 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18254 MachinePointerInfo(),
18255 false, false, false, 0));
18257 Results.push_back(FIST);
18261 case ISD::UINT_TO_FP: {
18262 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18263 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18264 N->getValueType(0) != MVT::v2f32)
18266 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18268 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18270 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18271 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18272 DAG.getBitcast(MVT::v2i64, VBias));
18273 Or = DAG.getBitcast(MVT::v2f64, Or);
18274 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18275 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18278 case ISD::FP_ROUND: {
18279 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18281 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18282 Results.push_back(V);
18285 case ISD::FP_EXTEND: {
18286 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18287 // No other ValueType for FP_EXTEND should reach this point.
18288 assert(N->getValueType(0) == MVT::v2f32 &&
18289 "Do not know how to legalize this Node");
18292 case ISD::INTRINSIC_W_CHAIN: {
18293 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18295 default : llvm_unreachable("Do not know how to custom type "
18296 "legalize this intrinsic operation!");
18297 case Intrinsic::x86_rdtsc:
18298 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18300 case Intrinsic::x86_rdtscp:
18301 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18303 case Intrinsic::x86_rdpmc:
18304 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18307 case ISD::READCYCLECOUNTER: {
18308 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18311 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18312 EVT T = N->getValueType(0);
18313 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18314 bool Regs64bit = T == MVT::i128;
18315 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18316 SDValue cpInL, cpInH;
18317 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18318 DAG.getConstant(0, dl, HalfT));
18319 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18320 DAG.getConstant(1, dl, HalfT));
18321 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18322 Regs64bit ? X86::RAX : X86::EAX,
18324 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18325 Regs64bit ? X86::RDX : X86::EDX,
18326 cpInH, cpInL.getValue(1));
18327 SDValue swapInL, swapInH;
18328 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18329 DAG.getConstant(0, dl, HalfT));
18330 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18331 DAG.getConstant(1, dl, HalfT));
18332 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18333 Regs64bit ? X86::RBX : X86::EBX,
18334 swapInL, cpInH.getValue(1));
18335 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18336 Regs64bit ? X86::RCX : X86::ECX,
18337 swapInH, swapInL.getValue(1));
18338 SDValue Ops[] = { swapInH.getValue(0),
18340 swapInH.getValue(1) };
18341 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18342 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18343 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18344 X86ISD::LCMPXCHG8_DAG;
18345 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18346 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18347 Regs64bit ? X86::RAX : X86::EAX,
18348 HalfT, Result.getValue(1));
18349 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18350 Regs64bit ? X86::RDX : X86::EDX,
18351 HalfT, cpOutL.getValue(2));
18352 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18354 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18355 MVT::i32, cpOutH.getValue(2));
18357 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18358 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18359 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18361 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18362 Results.push_back(Success);
18363 Results.push_back(EFLAGS.getValue(1));
18366 case ISD::ATOMIC_SWAP:
18367 case ISD::ATOMIC_LOAD_ADD:
18368 case ISD::ATOMIC_LOAD_SUB:
18369 case ISD::ATOMIC_LOAD_AND:
18370 case ISD::ATOMIC_LOAD_OR:
18371 case ISD::ATOMIC_LOAD_XOR:
18372 case ISD::ATOMIC_LOAD_NAND:
18373 case ISD::ATOMIC_LOAD_MIN:
18374 case ISD::ATOMIC_LOAD_MAX:
18375 case ISD::ATOMIC_LOAD_UMIN:
18376 case ISD::ATOMIC_LOAD_UMAX:
18377 case ISD::ATOMIC_LOAD: {
18378 // Delegate to generic TypeLegalization. Situations we can really handle
18379 // should have already been dealt with by AtomicExpandPass.cpp.
18382 case ISD::BITCAST: {
18383 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18384 EVT DstVT = N->getValueType(0);
18385 EVT SrcVT = N->getOperand(0)->getValueType(0);
18387 if (SrcVT != MVT::f64 ||
18388 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18391 unsigned NumElts = DstVT.getVectorNumElements();
18392 EVT SVT = DstVT.getVectorElementType();
18393 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18394 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18395 MVT::v2f64, N->getOperand(0));
18396 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18398 if (ExperimentalVectorWideningLegalization) {
18399 // If we are legalizing vectors by widening, we already have the desired
18400 // legal vector type, just return it.
18401 Results.push_back(ToVecInt);
18405 SmallVector<SDValue, 8> Elts;
18406 for (unsigned i = 0, e = NumElts; i != e; ++i)
18407 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18408 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18410 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18415 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18416 switch ((X86ISD::NodeType)Opcode) {
18417 case X86ISD::FIRST_NUMBER: break;
18418 case X86ISD::BSF: return "X86ISD::BSF";
18419 case X86ISD::BSR: return "X86ISD::BSR";
18420 case X86ISD::SHLD: return "X86ISD::SHLD";
18421 case X86ISD::SHRD: return "X86ISD::SHRD";
18422 case X86ISD::FAND: return "X86ISD::FAND";
18423 case X86ISD::FANDN: return "X86ISD::FANDN";
18424 case X86ISD::FOR: return "X86ISD::FOR";
18425 case X86ISD::FXOR: return "X86ISD::FXOR";
18426 case X86ISD::FILD: return "X86ISD::FILD";
18427 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18428 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18429 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18430 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18431 case X86ISD::FLD: return "X86ISD::FLD";
18432 case X86ISD::FST: return "X86ISD::FST";
18433 case X86ISD::CALL: return "X86ISD::CALL";
18434 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18435 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18436 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18437 case X86ISD::BT: return "X86ISD::BT";
18438 case X86ISD::CMP: return "X86ISD::CMP";
18439 case X86ISD::COMI: return "X86ISD::COMI";
18440 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18441 case X86ISD::CMPM: return "X86ISD::CMPM";
18442 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18443 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18444 case X86ISD::SETCC: return "X86ISD::SETCC";
18445 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18446 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18447 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18448 case X86ISD::CMOV: return "X86ISD::CMOV";
18449 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18450 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18451 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18452 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18453 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18454 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18455 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18456 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18457 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18458 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18459 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18460 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18461 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18462 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18463 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18464 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18465 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18466 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18467 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18468 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18469 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18470 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18471 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18472 case X86ISD::HADD: return "X86ISD::HADD";
18473 case X86ISD::HSUB: return "X86ISD::HSUB";
18474 case X86ISD::FHADD: return "X86ISD::FHADD";
18475 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18476 case X86ISD::UMAX: return "X86ISD::UMAX";
18477 case X86ISD::UMIN: return "X86ISD::UMIN";
18478 case X86ISD::SMAX: return "X86ISD::SMAX";
18479 case X86ISD::SMIN: return "X86ISD::SMIN";
18480 case X86ISD::FMAX: return "X86ISD::FMAX";
18481 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18482 case X86ISD::FMIN: return "X86ISD::FMIN";
18483 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18484 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18485 case X86ISD::FMINC: return "X86ISD::FMINC";
18486 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18487 case X86ISD::FRCP: return "X86ISD::FRCP";
18488 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18489 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18490 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18491 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18492 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18493 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18494 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18495 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18496 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18497 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18498 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18499 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18500 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18501 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18502 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18503 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18504 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18505 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18506 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18507 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18508 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18509 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
18510 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18511 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18512 case X86ISD::VSHL: return "X86ISD::VSHL";
18513 case X86ISD::VSRL: return "X86ISD::VSRL";
18514 case X86ISD::VSRA: return "X86ISD::VSRA";
18515 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18516 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18517 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18518 case X86ISD::CMPP: return "X86ISD::CMPP";
18519 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18520 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18521 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18522 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18523 case X86ISD::ADD: return "X86ISD::ADD";
18524 case X86ISD::SUB: return "X86ISD::SUB";
18525 case X86ISD::ADC: return "X86ISD::ADC";
18526 case X86ISD::SBB: return "X86ISD::SBB";
18527 case X86ISD::SMUL: return "X86ISD::SMUL";
18528 case X86ISD::UMUL: return "X86ISD::UMUL";
18529 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18530 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18531 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18532 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18533 case X86ISD::INC: return "X86ISD::INC";
18534 case X86ISD::DEC: return "X86ISD::DEC";
18535 case X86ISD::OR: return "X86ISD::OR";
18536 case X86ISD::XOR: return "X86ISD::XOR";
18537 case X86ISD::AND: return "X86ISD::AND";
18538 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18539 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18540 case X86ISD::PTEST: return "X86ISD::PTEST";
18541 case X86ISD::TESTP: return "X86ISD::TESTP";
18542 case X86ISD::TESTM: return "X86ISD::TESTM";
18543 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18544 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18545 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18546 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18547 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18548 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18549 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18550 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18551 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18552 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18553 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18554 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18555 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18556 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18557 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18558 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18559 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18560 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18561 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18562 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18563 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18564 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18565 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18566 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18567 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18568 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18569 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18570 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18571 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18572 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18573 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18574 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18575 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18576 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18577 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18578 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18579 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18580 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18581 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18582 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18583 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18584 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18585 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18586 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18587 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18588 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18589 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18590 case X86ISD::SAHF: return "X86ISD::SAHF";
18591 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18592 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18593 case X86ISD::FMADD: return "X86ISD::FMADD";
18594 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18595 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18596 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18597 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18598 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18599 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18600 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18601 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18602 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18603 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18604 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18605 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18606 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18607 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18608 case X86ISD::XTEST: return "X86ISD::XTEST";
18609 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18610 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18611 case X86ISD::SELECT: return "X86ISD::SELECT";
18612 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18613 case X86ISD::RCP28: return "X86ISD::RCP28";
18614 case X86ISD::EXP2: return "X86ISD::EXP2";
18615 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18616 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18617 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18618 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18619 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18620 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18621 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18622 case X86ISD::ADDS: return "X86ISD::ADDS";
18623 case X86ISD::SUBS: return "X86ISD::SUBS";
18624 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
18625 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
18630 // isLegalAddressingMode - Return true if the addressing mode represented
18631 // by AM is legal for this target, for a load/store of the specified type.
18632 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18634 unsigned AS) const {
18635 // X86 supports extremely general addressing modes.
18636 CodeModel::Model M = getTargetMachine().getCodeModel();
18637 Reloc::Model R = getTargetMachine().getRelocationModel();
18639 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18640 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18645 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18647 // If a reference to this global requires an extra load, we can't fold it.
18648 if (isGlobalStubReference(GVFlags))
18651 // If BaseGV requires a register for the PIC base, we cannot also have a
18652 // BaseReg specified.
18653 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18656 // If lower 4G is not available, then we must use rip-relative addressing.
18657 if ((M != CodeModel::Small || R != Reloc::Static) &&
18658 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18662 switch (AM.Scale) {
18668 // These scales always work.
18673 // These scales are formed with basereg+scalereg. Only accept if there is
18678 default: // Other stuff never works.
18685 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18686 unsigned Bits = Ty->getScalarSizeInBits();
18688 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18689 // particularly cheaper than those without.
18693 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18694 // variable shifts just as cheap as scalar ones.
18695 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18698 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18699 // fully general vector.
18703 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18704 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18706 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18707 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18708 return NumBits1 > NumBits2;
18711 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18712 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18715 if (!isTypeLegal(EVT::getEVT(Ty1)))
18718 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18720 // Assuming the caller doesn't have a zeroext or signext return parameter,
18721 // truncation all the way down to i1 is valid.
18725 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18726 return isInt<32>(Imm);
18729 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18730 // Can also use sub to handle negated immediates.
18731 return isInt<32>(Imm);
18734 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18735 if (!VT1.isInteger() || !VT2.isInteger())
18737 unsigned NumBits1 = VT1.getSizeInBits();
18738 unsigned NumBits2 = VT2.getSizeInBits();
18739 return NumBits1 > NumBits2;
18742 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18743 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18744 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18747 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18748 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18749 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18752 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18753 EVT VT1 = Val.getValueType();
18754 if (isZExtFree(VT1, VT2))
18757 if (Val.getOpcode() != ISD::LOAD)
18760 if (!VT1.isSimple() || !VT1.isInteger() ||
18761 !VT2.isSimple() || !VT2.isInteger())
18764 switch (VT1.getSimpleVT().SimpleTy) {
18769 // X86 has 8, 16, and 32-bit zero-extending loads.
18776 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18779 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18780 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18783 VT = VT.getScalarType();
18785 if (!VT.isSimple())
18788 switch (VT.getSimpleVT().SimpleTy) {
18799 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18800 // i16 instructions are longer (0x66 prefix) and potentially slower.
18801 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18804 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18805 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18806 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18807 /// are assumed to be legal.
18809 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18811 if (!VT.isSimple())
18814 // Not for i1 vectors
18815 if (VT.getScalarType() == MVT::i1)
18818 // Very little shuffling can be done for 64-bit vectors right now.
18819 if (VT.getSizeInBits() == 64)
18822 // We only care that the types being shuffled are legal. The lowering can
18823 // handle any possible shuffle mask that results.
18824 return isTypeLegal(VT.getSimpleVT());
18828 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18830 // Just delegate to the generic legality, clear masks aren't special.
18831 return isShuffleMaskLegal(Mask, VT);
18834 //===----------------------------------------------------------------------===//
18835 // X86 Scheduler Hooks
18836 //===----------------------------------------------------------------------===//
18838 /// Utility function to emit xbegin specifying the start of an RTM region.
18839 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18840 const TargetInstrInfo *TII) {
18841 DebugLoc DL = MI->getDebugLoc();
18843 const BasicBlock *BB = MBB->getBasicBlock();
18844 MachineFunction::iterator I = MBB;
18847 // For the v = xbegin(), we generate
18858 MachineBasicBlock *thisMBB = MBB;
18859 MachineFunction *MF = MBB->getParent();
18860 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18861 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18862 MF->insert(I, mainMBB);
18863 MF->insert(I, sinkMBB);
18865 // Transfer the remainder of BB and its successor edges to sinkMBB.
18866 sinkMBB->splice(sinkMBB->begin(), MBB,
18867 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18868 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18872 // # fallthrough to mainMBB
18873 // # abortion to sinkMBB
18874 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18875 thisMBB->addSuccessor(mainMBB);
18876 thisMBB->addSuccessor(sinkMBB);
18880 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18881 mainMBB->addSuccessor(sinkMBB);
18884 // EAX is live into the sinkMBB
18885 sinkMBB->addLiveIn(X86::EAX);
18886 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18887 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18890 MI->eraseFromParent();
18894 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18895 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18896 // in the .td file.
18897 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18898 const TargetInstrInfo *TII) {
18900 switch (MI->getOpcode()) {
18901 default: llvm_unreachable("illegal opcode!");
18902 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18903 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18904 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18905 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18906 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18907 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18908 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18909 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18912 DebugLoc dl = MI->getDebugLoc();
18913 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18915 unsigned NumArgs = MI->getNumOperands();
18916 for (unsigned i = 1; i < NumArgs; ++i) {
18917 MachineOperand &Op = MI->getOperand(i);
18918 if (!(Op.isReg() && Op.isImplicit()))
18919 MIB.addOperand(Op);
18921 if (MI->hasOneMemOperand())
18922 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18924 BuildMI(*BB, MI, dl,
18925 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18926 .addReg(X86::XMM0);
18928 MI->eraseFromParent();
18932 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18933 // defs in an instruction pattern
18934 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18935 const TargetInstrInfo *TII) {
18937 switch (MI->getOpcode()) {
18938 default: llvm_unreachable("illegal opcode!");
18939 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18940 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18941 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18942 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18943 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18944 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18945 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18946 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18949 DebugLoc dl = MI->getDebugLoc();
18950 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18952 unsigned NumArgs = MI->getNumOperands(); // remove the results
18953 for (unsigned i = 1; i < NumArgs; ++i) {
18954 MachineOperand &Op = MI->getOperand(i);
18955 if (!(Op.isReg() && Op.isImplicit()))
18956 MIB.addOperand(Op);
18958 if (MI->hasOneMemOperand())
18959 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18961 BuildMI(*BB, MI, dl,
18962 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18965 MI->eraseFromParent();
18969 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18970 const X86Subtarget *Subtarget) {
18971 DebugLoc dl = MI->getDebugLoc();
18972 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18973 // Address into RAX/EAX, other two args into ECX, EDX.
18974 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18975 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18976 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18977 for (int i = 0; i < X86::AddrNumOperands; ++i)
18978 MIB.addOperand(MI->getOperand(i));
18980 unsigned ValOps = X86::AddrNumOperands;
18981 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18982 .addReg(MI->getOperand(ValOps).getReg());
18983 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18984 .addReg(MI->getOperand(ValOps+1).getReg());
18986 // The instruction doesn't actually take any operands though.
18987 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18989 MI->eraseFromParent(); // The pseudo is gone now.
18993 MachineBasicBlock *
18994 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18995 MachineBasicBlock *MBB) const {
18996 // Emit va_arg instruction on X86-64.
18998 // Operands to this pseudo-instruction:
18999 // 0 ) Output : destination address (reg)
19000 // 1-5) Input : va_list address (addr, i64mem)
19001 // 6 ) ArgSize : Size (in bytes) of vararg type
19002 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19003 // 8 ) Align : Alignment of type
19004 // 9 ) EFLAGS (implicit-def)
19006 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19007 static_assert(X86::AddrNumOperands == 5,
19008 "VAARG_64 assumes 5 address operands");
19010 unsigned DestReg = MI->getOperand(0).getReg();
19011 MachineOperand &Base = MI->getOperand(1);
19012 MachineOperand &Scale = MI->getOperand(2);
19013 MachineOperand &Index = MI->getOperand(3);
19014 MachineOperand &Disp = MI->getOperand(4);
19015 MachineOperand &Segment = MI->getOperand(5);
19016 unsigned ArgSize = MI->getOperand(6).getImm();
19017 unsigned ArgMode = MI->getOperand(7).getImm();
19018 unsigned Align = MI->getOperand(8).getImm();
19020 // Memory Reference
19021 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19022 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19023 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19025 // Machine Information
19026 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19027 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19028 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19029 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19030 DebugLoc DL = MI->getDebugLoc();
19032 // struct va_list {
19035 // i64 overflow_area (address)
19036 // i64 reg_save_area (address)
19038 // sizeof(va_list) = 24
19039 // alignment(va_list) = 8
19041 unsigned TotalNumIntRegs = 6;
19042 unsigned TotalNumXMMRegs = 8;
19043 bool UseGPOffset = (ArgMode == 1);
19044 bool UseFPOffset = (ArgMode == 2);
19045 unsigned MaxOffset = TotalNumIntRegs * 8 +
19046 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19048 /* Align ArgSize to a multiple of 8 */
19049 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19050 bool NeedsAlign = (Align > 8);
19052 MachineBasicBlock *thisMBB = MBB;
19053 MachineBasicBlock *overflowMBB;
19054 MachineBasicBlock *offsetMBB;
19055 MachineBasicBlock *endMBB;
19057 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19058 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19059 unsigned OffsetReg = 0;
19061 if (!UseGPOffset && !UseFPOffset) {
19062 // If we only pull from the overflow region, we don't create a branch.
19063 // We don't need to alter control flow.
19064 OffsetDestReg = 0; // unused
19065 OverflowDestReg = DestReg;
19067 offsetMBB = nullptr;
19068 overflowMBB = thisMBB;
19071 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19072 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19073 // If not, pull from overflow_area. (branch to overflowMBB)
19078 // offsetMBB overflowMBB
19083 // Registers for the PHI in endMBB
19084 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19085 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19087 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19088 MachineFunction *MF = MBB->getParent();
19089 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19090 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19091 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19093 MachineFunction::iterator MBBIter = MBB;
19096 // Insert the new basic blocks
19097 MF->insert(MBBIter, offsetMBB);
19098 MF->insert(MBBIter, overflowMBB);
19099 MF->insert(MBBIter, endMBB);
19101 // Transfer the remainder of MBB and its successor edges to endMBB.
19102 endMBB->splice(endMBB->begin(), thisMBB,
19103 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19104 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19106 // Make offsetMBB and overflowMBB successors of thisMBB
19107 thisMBB->addSuccessor(offsetMBB);
19108 thisMBB->addSuccessor(overflowMBB);
19110 // endMBB is a successor of both offsetMBB and overflowMBB
19111 offsetMBB->addSuccessor(endMBB);
19112 overflowMBB->addSuccessor(endMBB);
19114 // Load the offset value into a register
19115 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19116 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19120 .addDisp(Disp, UseFPOffset ? 4 : 0)
19121 .addOperand(Segment)
19122 .setMemRefs(MMOBegin, MMOEnd);
19124 // Check if there is enough room left to pull this argument.
19125 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19127 .addImm(MaxOffset + 8 - ArgSizeA8);
19129 // Branch to "overflowMBB" if offset >= max
19130 // Fall through to "offsetMBB" otherwise
19131 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19132 .addMBB(overflowMBB);
19135 // In offsetMBB, emit code to use the reg_save_area.
19137 assert(OffsetReg != 0);
19139 // Read the reg_save_area address.
19140 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19141 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19146 .addOperand(Segment)
19147 .setMemRefs(MMOBegin, MMOEnd);
19149 // Zero-extend the offset
19150 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19151 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19154 .addImm(X86::sub_32bit);
19156 // Add the offset to the reg_save_area to get the final address.
19157 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19158 .addReg(OffsetReg64)
19159 .addReg(RegSaveReg);
19161 // Compute the offset for the next argument
19162 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19163 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19165 .addImm(UseFPOffset ? 16 : 8);
19167 // Store it back into the va_list.
19168 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19172 .addDisp(Disp, UseFPOffset ? 4 : 0)
19173 .addOperand(Segment)
19174 .addReg(NextOffsetReg)
19175 .setMemRefs(MMOBegin, MMOEnd);
19178 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19183 // Emit code to use overflow area
19186 // Load the overflow_area address into a register.
19187 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19188 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19193 .addOperand(Segment)
19194 .setMemRefs(MMOBegin, MMOEnd);
19196 // If we need to align it, do so. Otherwise, just copy the address
19197 // to OverflowDestReg.
19199 // Align the overflow address
19200 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19201 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19203 // aligned_addr = (addr + (align-1)) & ~(align-1)
19204 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19205 .addReg(OverflowAddrReg)
19208 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19210 .addImm(~(uint64_t)(Align-1));
19212 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19213 .addReg(OverflowAddrReg);
19216 // Compute the next overflow address after this argument.
19217 // (the overflow address should be kept 8-byte aligned)
19218 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19219 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19220 .addReg(OverflowDestReg)
19221 .addImm(ArgSizeA8);
19223 // Store the new overflow address.
19224 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19229 .addOperand(Segment)
19230 .addReg(NextAddrReg)
19231 .setMemRefs(MMOBegin, MMOEnd);
19233 // If we branched, emit the PHI to the front of endMBB.
19235 BuildMI(*endMBB, endMBB->begin(), DL,
19236 TII->get(X86::PHI), DestReg)
19237 .addReg(OffsetDestReg).addMBB(offsetMBB)
19238 .addReg(OverflowDestReg).addMBB(overflowMBB);
19241 // Erase the pseudo instruction
19242 MI->eraseFromParent();
19247 MachineBasicBlock *
19248 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19250 MachineBasicBlock *MBB) const {
19251 // Emit code to save XMM registers to the stack. The ABI says that the
19252 // number of registers to save is given in %al, so it's theoretically
19253 // possible to do an indirect jump trick to avoid saving all of them,
19254 // however this code takes a simpler approach and just executes all
19255 // of the stores if %al is non-zero. It's less code, and it's probably
19256 // easier on the hardware branch predictor, and stores aren't all that
19257 // expensive anyway.
19259 // Create the new basic blocks. One block contains all the XMM stores,
19260 // and one block is the final destination regardless of whether any
19261 // stores were performed.
19262 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19263 MachineFunction *F = MBB->getParent();
19264 MachineFunction::iterator MBBIter = MBB;
19266 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19267 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19268 F->insert(MBBIter, XMMSaveMBB);
19269 F->insert(MBBIter, EndMBB);
19271 // Transfer the remainder of MBB and its successor edges to EndMBB.
19272 EndMBB->splice(EndMBB->begin(), MBB,
19273 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19274 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19276 // The original block will now fall through to the XMM save block.
19277 MBB->addSuccessor(XMMSaveMBB);
19278 // The XMMSaveMBB will fall through to the end block.
19279 XMMSaveMBB->addSuccessor(EndMBB);
19281 // Now add the instructions.
19282 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19283 DebugLoc DL = MI->getDebugLoc();
19285 unsigned CountReg = MI->getOperand(0).getReg();
19286 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19287 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19289 if (!Subtarget->isTargetWin64()) {
19290 // If %al is 0, branch around the XMM save block.
19291 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19292 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19293 MBB->addSuccessor(EndMBB);
19296 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19297 // that was just emitted, but clearly shouldn't be "saved".
19298 assert((MI->getNumOperands() <= 3 ||
19299 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19300 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19301 && "Expected last argument to be EFLAGS");
19302 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19303 // In the XMM save block, save all the XMM argument registers.
19304 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19305 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19306 MachineMemOperand *MMO =
19307 F->getMachineMemOperand(
19308 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19309 MachineMemOperand::MOStore,
19310 /*Size=*/16, /*Align=*/16);
19311 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19312 .addFrameIndex(RegSaveFrameIndex)
19313 .addImm(/*Scale=*/1)
19314 .addReg(/*IndexReg=*/0)
19315 .addImm(/*Disp=*/Offset)
19316 .addReg(/*Segment=*/0)
19317 .addReg(MI->getOperand(i).getReg())
19318 .addMemOperand(MMO);
19321 MI->eraseFromParent(); // The pseudo instruction is gone now.
19326 // The EFLAGS operand of SelectItr might be missing a kill marker
19327 // because there were multiple uses of EFLAGS, and ISel didn't know
19328 // which to mark. Figure out whether SelectItr should have had a
19329 // kill marker, and set it if it should. Returns the correct kill
19331 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19332 MachineBasicBlock* BB,
19333 const TargetRegisterInfo* TRI) {
19334 // Scan forward through BB for a use/def of EFLAGS.
19335 MachineBasicBlock::iterator miI(std::next(SelectItr));
19336 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19337 const MachineInstr& mi = *miI;
19338 if (mi.readsRegister(X86::EFLAGS))
19340 if (mi.definesRegister(X86::EFLAGS))
19341 break; // Should have kill-flag - update below.
19344 // If we hit the end of the block, check whether EFLAGS is live into a
19346 if (miI == BB->end()) {
19347 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19348 sEnd = BB->succ_end();
19349 sItr != sEnd; ++sItr) {
19350 MachineBasicBlock* succ = *sItr;
19351 if (succ->isLiveIn(X86::EFLAGS))
19356 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19357 // out. SelectMI should have a kill flag on EFLAGS.
19358 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19362 MachineBasicBlock *
19363 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19364 MachineBasicBlock *BB) const {
19365 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19366 DebugLoc DL = MI->getDebugLoc();
19368 // To "insert" a SELECT_CC instruction, we actually have to insert the
19369 // diamond control-flow pattern. The incoming instruction knows the
19370 // destination vreg to set, the condition code register to branch on, the
19371 // true/false values to select between, and a branch opcode to use.
19372 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19373 MachineFunction::iterator It = BB;
19379 // cmpTY ccX, r1, r2
19381 // fallthrough --> copy0MBB
19382 MachineBasicBlock *thisMBB = BB;
19383 MachineFunction *F = BB->getParent();
19385 // We also lower double CMOVs:
19386 // (CMOV (CMOV F, T, cc1), T, cc2)
19387 // to two successives branches. For that, we look for another CMOV as the
19388 // following instruction.
19390 // Without this, we would add a PHI between the two jumps, which ends up
19391 // creating a few copies all around. For instance, for
19393 // (sitofp (zext (fcmp une)))
19395 // we would generate:
19397 // ucomiss %xmm1, %xmm0
19398 // movss <1.0f>, %xmm0
19399 // movaps %xmm0, %xmm1
19401 // xorps %xmm1, %xmm1
19404 // movaps %xmm1, %xmm0
19408 // because this custom-inserter would have generated:
19420 // A: X = ...; Y = ...
19422 // C: Z = PHI [X, A], [Y, B]
19424 // E: PHI [X, C], [Z, D]
19426 // If we lower both CMOVs in a single step, we can instead generate:
19438 // A: X = ...; Y = ...
19440 // E: PHI [X, A], [X, C], [Y, D]
19442 // Which, in our sitofp/fcmp example, gives us something like:
19444 // ucomiss %xmm1, %xmm0
19445 // movss <1.0f>, %xmm0
19448 // xorps %xmm0, %xmm0
19452 MachineInstr *NextCMOV = nullptr;
19453 MachineBasicBlock::iterator NextMIIt =
19454 std::next(MachineBasicBlock::iterator(MI));
19455 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19456 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19457 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19458 NextCMOV = &*NextMIIt;
19460 MachineBasicBlock *jcc1MBB = nullptr;
19462 // If we have a double CMOV, we lower it to two successive branches to
19463 // the same block. EFLAGS is used by both, so mark it as live in the second.
19465 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19466 F->insert(It, jcc1MBB);
19467 jcc1MBB->addLiveIn(X86::EFLAGS);
19470 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19471 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19472 F->insert(It, copy0MBB);
19473 F->insert(It, sinkMBB);
19475 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19476 // live into the sink and copy blocks.
19477 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19479 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19480 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19481 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19482 copy0MBB->addLiveIn(X86::EFLAGS);
19483 sinkMBB->addLiveIn(X86::EFLAGS);
19486 // Transfer the remainder of BB and its successor edges to sinkMBB.
19487 sinkMBB->splice(sinkMBB->begin(), BB,
19488 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19489 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19491 // Add the true and fallthrough blocks as its successors.
19493 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19494 BB->addSuccessor(jcc1MBB);
19496 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19497 // jump to the sinkMBB.
19498 jcc1MBB->addSuccessor(copy0MBB);
19499 jcc1MBB->addSuccessor(sinkMBB);
19501 BB->addSuccessor(copy0MBB);
19504 // The true block target of the first (or only) branch is always sinkMBB.
19505 BB->addSuccessor(sinkMBB);
19507 // Create the conditional branch instruction.
19509 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19510 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19513 unsigned Opc2 = X86::GetCondBranchFromCond(
19514 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19515 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19519 // %FalseValue = ...
19520 // # fallthrough to sinkMBB
19521 copy0MBB->addSuccessor(sinkMBB);
19524 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19526 MachineInstrBuilder MIB =
19527 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19528 MI->getOperand(0).getReg())
19529 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19530 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19532 // If we have a double CMOV, the second Jcc provides the same incoming
19533 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19535 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19536 // Copy the PHI result to the register defined by the second CMOV.
19537 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19538 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19539 .addReg(MI->getOperand(0).getReg());
19540 NextCMOV->eraseFromParent();
19543 MI->eraseFromParent(); // The pseudo instruction is gone now.
19547 MachineBasicBlock *
19548 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19549 MachineBasicBlock *BB) const {
19550 MachineFunction *MF = BB->getParent();
19551 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19552 DebugLoc DL = MI->getDebugLoc();
19553 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19555 assert(MF->shouldSplitStack());
19557 const bool Is64Bit = Subtarget->is64Bit();
19558 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19560 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19561 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19564 // ... [Till the alloca]
19565 // If stacklet is not large enough, jump to mallocMBB
19568 // Allocate by subtracting from RSP
19569 // Jump to continueMBB
19572 // Allocate by call to runtime
19576 // [rest of original BB]
19579 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19580 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19581 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19583 MachineRegisterInfo &MRI = MF->getRegInfo();
19584 const TargetRegisterClass *AddrRegClass =
19585 getRegClassFor(getPointerTy());
19587 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19588 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19589 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19590 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19591 sizeVReg = MI->getOperand(1).getReg(),
19592 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19594 MachineFunction::iterator MBBIter = BB;
19597 MF->insert(MBBIter, bumpMBB);
19598 MF->insert(MBBIter, mallocMBB);
19599 MF->insert(MBBIter, continueMBB);
19601 continueMBB->splice(continueMBB->begin(), BB,
19602 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19603 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19605 // Add code to the main basic block to check if the stack limit has been hit,
19606 // and if so, jump to mallocMBB otherwise to bumpMBB.
19607 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19608 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19609 .addReg(tmpSPVReg).addReg(sizeVReg);
19610 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19611 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19612 .addReg(SPLimitVReg);
19613 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19615 // bumpMBB simply decreases the stack pointer, since we know the current
19616 // stacklet has enough space.
19617 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19618 .addReg(SPLimitVReg);
19619 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19620 .addReg(SPLimitVReg);
19621 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19623 // Calls into a routine in libgcc to allocate more space from the heap.
19624 const uint32_t *RegMask =
19625 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19627 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19629 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19630 .addExternalSymbol("__morestack_allocate_stack_space")
19631 .addRegMask(RegMask)
19632 .addReg(X86::RDI, RegState::Implicit)
19633 .addReg(X86::RAX, RegState::ImplicitDefine);
19634 } else if (Is64Bit) {
19635 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19637 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19638 .addExternalSymbol("__morestack_allocate_stack_space")
19639 .addRegMask(RegMask)
19640 .addReg(X86::EDI, RegState::Implicit)
19641 .addReg(X86::EAX, RegState::ImplicitDefine);
19643 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19645 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19646 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19647 .addExternalSymbol("__morestack_allocate_stack_space")
19648 .addRegMask(RegMask)
19649 .addReg(X86::EAX, RegState::ImplicitDefine);
19653 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19656 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19657 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19658 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19660 // Set up the CFG correctly.
19661 BB->addSuccessor(bumpMBB);
19662 BB->addSuccessor(mallocMBB);
19663 mallocMBB->addSuccessor(continueMBB);
19664 bumpMBB->addSuccessor(continueMBB);
19666 // Take care of the PHI nodes.
19667 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19668 MI->getOperand(0).getReg())
19669 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19670 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19672 // Delete the original pseudo instruction.
19673 MI->eraseFromParent();
19676 return continueMBB;
19679 MachineBasicBlock *
19680 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19681 MachineBasicBlock *BB) const {
19682 DebugLoc DL = MI->getDebugLoc();
19684 assert(!Subtarget->isTargetMachO());
19686 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
19688 MI->eraseFromParent(); // The pseudo instruction is gone now.
19692 MachineBasicBlock *
19693 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19694 MachineBasicBlock *BB) const {
19695 // This is pretty easy. We're taking the value that we received from
19696 // our load from the relocation, sticking it in either RDI (x86-64)
19697 // or EAX and doing an indirect call. The return value will then
19698 // be in the normal return register.
19699 MachineFunction *F = BB->getParent();
19700 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19701 DebugLoc DL = MI->getDebugLoc();
19703 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19704 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19706 // Get a register mask for the lowered call.
19707 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19708 // proper register mask.
19709 const uint32_t *RegMask =
19710 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19711 if (Subtarget->is64Bit()) {
19712 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19713 TII->get(X86::MOV64rm), X86::RDI)
19715 .addImm(0).addReg(0)
19716 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19717 MI->getOperand(3).getTargetFlags())
19719 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19720 addDirectMem(MIB, X86::RDI);
19721 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19722 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19723 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19724 TII->get(X86::MOV32rm), X86::EAX)
19726 .addImm(0).addReg(0)
19727 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19728 MI->getOperand(3).getTargetFlags())
19730 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19731 addDirectMem(MIB, X86::EAX);
19732 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19734 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19735 TII->get(X86::MOV32rm), X86::EAX)
19736 .addReg(TII->getGlobalBaseReg(F))
19737 .addImm(0).addReg(0)
19738 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19739 MI->getOperand(3).getTargetFlags())
19741 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19742 addDirectMem(MIB, X86::EAX);
19743 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19746 MI->eraseFromParent(); // The pseudo instruction is gone now.
19750 MachineBasicBlock *
19751 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19752 MachineBasicBlock *MBB) const {
19753 DebugLoc DL = MI->getDebugLoc();
19754 MachineFunction *MF = MBB->getParent();
19755 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19756 MachineRegisterInfo &MRI = MF->getRegInfo();
19758 const BasicBlock *BB = MBB->getBasicBlock();
19759 MachineFunction::iterator I = MBB;
19762 // Memory Reference
19763 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19764 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19767 unsigned MemOpndSlot = 0;
19769 unsigned CurOp = 0;
19771 DstReg = MI->getOperand(CurOp++).getReg();
19772 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19773 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19774 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19775 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19777 MemOpndSlot = CurOp;
19779 MVT PVT = getPointerTy();
19780 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19781 "Invalid Pointer Size!");
19783 // For v = setjmp(buf), we generate
19786 // buf[LabelOffset] = restoreMBB
19787 // SjLjSetup restoreMBB
19793 // v = phi(main, restore)
19796 // if base pointer being used, load it from frame
19799 MachineBasicBlock *thisMBB = MBB;
19800 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19801 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19802 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19803 MF->insert(I, mainMBB);
19804 MF->insert(I, sinkMBB);
19805 MF->push_back(restoreMBB);
19807 MachineInstrBuilder MIB;
19809 // Transfer the remainder of BB and its successor edges to sinkMBB.
19810 sinkMBB->splice(sinkMBB->begin(), MBB,
19811 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19812 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19815 unsigned PtrStoreOpc = 0;
19816 unsigned LabelReg = 0;
19817 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19818 Reloc::Model RM = MF->getTarget().getRelocationModel();
19819 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19820 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19822 // Prepare IP either in reg or imm.
19823 if (!UseImmLabel) {
19824 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19825 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19826 LabelReg = MRI.createVirtualRegister(PtrRC);
19827 if (Subtarget->is64Bit()) {
19828 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19832 .addMBB(restoreMBB)
19835 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19836 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19837 .addReg(XII->getGlobalBaseReg(MF))
19840 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19844 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19846 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19847 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19848 if (i == X86::AddrDisp)
19849 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19851 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19854 MIB.addReg(LabelReg);
19856 MIB.addMBB(restoreMBB);
19857 MIB.setMemRefs(MMOBegin, MMOEnd);
19859 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19860 .addMBB(restoreMBB);
19862 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19863 MIB.addRegMask(RegInfo->getNoPreservedMask());
19864 thisMBB->addSuccessor(mainMBB);
19865 thisMBB->addSuccessor(restoreMBB);
19869 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19870 mainMBB->addSuccessor(sinkMBB);
19873 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19874 TII->get(X86::PHI), DstReg)
19875 .addReg(mainDstReg).addMBB(mainMBB)
19876 .addReg(restoreDstReg).addMBB(restoreMBB);
19879 if (RegInfo->hasBasePointer(*MF)) {
19880 const bool Uses64BitFramePtr =
19881 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19882 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19883 X86FI->setRestoreBasePointer(MF);
19884 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19885 unsigned BasePtr = RegInfo->getBaseRegister();
19886 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19887 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19888 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19889 .setMIFlag(MachineInstr::FrameSetup);
19891 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19892 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19893 restoreMBB->addSuccessor(sinkMBB);
19895 MI->eraseFromParent();
19899 MachineBasicBlock *
19900 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19901 MachineBasicBlock *MBB) const {
19902 DebugLoc DL = MI->getDebugLoc();
19903 MachineFunction *MF = MBB->getParent();
19904 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19905 MachineRegisterInfo &MRI = MF->getRegInfo();
19907 // Memory Reference
19908 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19909 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19911 MVT PVT = getPointerTy();
19912 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19913 "Invalid Pointer Size!");
19915 const TargetRegisterClass *RC =
19916 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19917 unsigned Tmp = MRI.createVirtualRegister(RC);
19918 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19919 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19920 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19921 unsigned SP = RegInfo->getStackRegister();
19923 MachineInstrBuilder MIB;
19925 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19926 const int64_t SPOffset = 2 * PVT.getStoreSize();
19928 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19929 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19932 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19933 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19934 MIB.addOperand(MI->getOperand(i));
19935 MIB.setMemRefs(MMOBegin, MMOEnd);
19937 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19938 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19939 if (i == X86::AddrDisp)
19940 MIB.addDisp(MI->getOperand(i), LabelOffset);
19942 MIB.addOperand(MI->getOperand(i));
19944 MIB.setMemRefs(MMOBegin, MMOEnd);
19946 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19947 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19948 if (i == X86::AddrDisp)
19949 MIB.addDisp(MI->getOperand(i), SPOffset);
19951 MIB.addOperand(MI->getOperand(i));
19953 MIB.setMemRefs(MMOBegin, MMOEnd);
19955 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19957 MI->eraseFromParent();
19961 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19962 // accumulator loops. Writing back to the accumulator allows the coalescer
19963 // to remove extra copies in the loop.
19964 MachineBasicBlock *
19965 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19966 MachineBasicBlock *MBB) const {
19967 MachineOperand &AddendOp = MI->getOperand(3);
19969 // Bail out early if the addend isn't a register - we can't switch these.
19970 if (!AddendOp.isReg())
19973 MachineFunction &MF = *MBB->getParent();
19974 MachineRegisterInfo &MRI = MF.getRegInfo();
19976 // Check whether the addend is defined by a PHI:
19977 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19978 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19979 if (!AddendDef.isPHI())
19982 // Look for the following pattern:
19984 // %addend = phi [%entry, 0], [%loop, %result]
19986 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19990 // %addend = phi [%entry, 0], [%loop, %result]
19992 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19994 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19995 assert(AddendDef.getOperand(i).isReg());
19996 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19997 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19998 if (&PHISrcInst == MI) {
19999 // Found a matching instruction.
20000 unsigned NewFMAOpc = 0;
20001 switch (MI->getOpcode()) {
20002 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20003 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20004 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20005 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20006 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20007 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20008 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20009 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20010 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20011 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20012 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20013 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20014 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20015 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20016 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20017 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20018 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20019 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20020 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20021 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20023 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20024 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20025 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20026 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20027 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20028 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20029 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20030 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20031 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20032 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20033 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20034 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20035 default: llvm_unreachable("Unrecognized FMA variant.");
20038 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
20039 MachineInstrBuilder MIB =
20040 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20041 .addOperand(MI->getOperand(0))
20042 .addOperand(MI->getOperand(3))
20043 .addOperand(MI->getOperand(2))
20044 .addOperand(MI->getOperand(1));
20045 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20046 MI->eraseFromParent();
20053 MachineBasicBlock *
20054 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20055 MachineBasicBlock *BB) const {
20056 switch (MI->getOpcode()) {
20057 default: llvm_unreachable("Unexpected instr type to insert");
20058 case X86::TAILJMPd64:
20059 case X86::TAILJMPr64:
20060 case X86::TAILJMPm64:
20061 case X86::TAILJMPd64_REX:
20062 case X86::TAILJMPr64_REX:
20063 case X86::TAILJMPm64_REX:
20064 llvm_unreachable("TAILJMP64 would not be touched here.");
20065 case X86::TCRETURNdi64:
20066 case X86::TCRETURNri64:
20067 case X86::TCRETURNmi64:
20069 case X86::WIN_ALLOCA:
20070 return EmitLoweredWinAlloca(MI, BB);
20071 case X86::SEG_ALLOCA_32:
20072 case X86::SEG_ALLOCA_64:
20073 return EmitLoweredSegAlloca(MI, BB);
20074 case X86::TLSCall_32:
20075 case X86::TLSCall_64:
20076 return EmitLoweredTLSCall(MI, BB);
20077 case X86::CMOV_GR8:
20078 case X86::CMOV_FR32:
20079 case X86::CMOV_FR64:
20080 case X86::CMOV_V4F32:
20081 case X86::CMOV_V2F64:
20082 case X86::CMOV_V2I64:
20083 case X86::CMOV_V8F32:
20084 case X86::CMOV_V4F64:
20085 case X86::CMOV_V4I64:
20086 case X86::CMOV_V16F32:
20087 case X86::CMOV_V8F64:
20088 case X86::CMOV_V8I64:
20089 case X86::CMOV_GR16:
20090 case X86::CMOV_GR32:
20091 case X86::CMOV_RFP32:
20092 case X86::CMOV_RFP64:
20093 case X86::CMOV_RFP80:
20094 case X86::CMOV_V8I1:
20095 case X86::CMOV_V16I1:
20096 case X86::CMOV_V32I1:
20097 case X86::CMOV_V64I1:
20098 return EmitLoweredSelect(MI, BB);
20100 case X86::FP32_TO_INT16_IN_MEM:
20101 case X86::FP32_TO_INT32_IN_MEM:
20102 case X86::FP32_TO_INT64_IN_MEM:
20103 case X86::FP64_TO_INT16_IN_MEM:
20104 case X86::FP64_TO_INT32_IN_MEM:
20105 case X86::FP64_TO_INT64_IN_MEM:
20106 case X86::FP80_TO_INT16_IN_MEM:
20107 case X86::FP80_TO_INT32_IN_MEM:
20108 case X86::FP80_TO_INT64_IN_MEM: {
20109 MachineFunction *F = BB->getParent();
20110 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20111 DebugLoc DL = MI->getDebugLoc();
20113 // Change the floating point control register to use "round towards zero"
20114 // mode when truncating to an integer value.
20115 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20116 addFrameReference(BuildMI(*BB, MI, DL,
20117 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20119 // Load the old value of the high byte of the control word...
20121 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20122 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20125 // Set the high part to be round to zero...
20126 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20129 // Reload the modified control word now...
20130 addFrameReference(BuildMI(*BB, MI, DL,
20131 TII->get(X86::FLDCW16m)), CWFrameIdx);
20133 // Restore the memory image of control word to original value
20134 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20137 // Get the X86 opcode to use.
20139 switch (MI->getOpcode()) {
20140 default: llvm_unreachable("illegal opcode!");
20141 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20142 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20143 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20144 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20145 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20146 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20147 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20148 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20149 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20153 MachineOperand &Op = MI->getOperand(0);
20155 AM.BaseType = X86AddressMode::RegBase;
20156 AM.Base.Reg = Op.getReg();
20158 AM.BaseType = X86AddressMode::FrameIndexBase;
20159 AM.Base.FrameIndex = Op.getIndex();
20161 Op = MI->getOperand(1);
20163 AM.Scale = Op.getImm();
20164 Op = MI->getOperand(2);
20166 AM.IndexReg = Op.getImm();
20167 Op = MI->getOperand(3);
20168 if (Op.isGlobal()) {
20169 AM.GV = Op.getGlobal();
20171 AM.Disp = Op.getImm();
20173 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20174 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20176 // Reload the original control word now.
20177 addFrameReference(BuildMI(*BB, MI, DL,
20178 TII->get(X86::FLDCW16m)), CWFrameIdx);
20180 MI->eraseFromParent(); // The pseudo instruction is gone now.
20183 // String/text processing lowering.
20184 case X86::PCMPISTRM128REG:
20185 case X86::VPCMPISTRM128REG:
20186 case X86::PCMPISTRM128MEM:
20187 case X86::VPCMPISTRM128MEM:
20188 case X86::PCMPESTRM128REG:
20189 case X86::VPCMPESTRM128REG:
20190 case X86::PCMPESTRM128MEM:
20191 case X86::VPCMPESTRM128MEM:
20192 assert(Subtarget->hasSSE42() &&
20193 "Target must have SSE4.2 or AVX features enabled");
20194 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20196 // String/text processing lowering.
20197 case X86::PCMPISTRIREG:
20198 case X86::VPCMPISTRIREG:
20199 case X86::PCMPISTRIMEM:
20200 case X86::VPCMPISTRIMEM:
20201 case X86::PCMPESTRIREG:
20202 case X86::VPCMPESTRIREG:
20203 case X86::PCMPESTRIMEM:
20204 case X86::VPCMPESTRIMEM:
20205 assert(Subtarget->hasSSE42() &&
20206 "Target must have SSE4.2 or AVX features enabled");
20207 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20209 // Thread synchronization.
20211 return EmitMonitor(MI, BB, Subtarget);
20215 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20217 case X86::VASTART_SAVE_XMM_REGS:
20218 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20220 case X86::VAARG_64:
20221 return EmitVAARG64WithCustomInserter(MI, BB);
20223 case X86::EH_SjLj_SetJmp32:
20224 case X86::EH_SjLj_SetJmp64:
20225 return emitEHSjLjSetJmp(MI, BB);
20227 case X86::EH_SjLj_LongJmp32:
20228 case X86::EH_SjLj_LongJmp64:
20229 return emitEHSjLjLongJmp(MI, BB);
20231 case TargetOpcode::STATEPOINT:
20232 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20233 // this point in the process. We diverge later.
20234 return emitPatchPoint(MI, BB);
20236 case TargetOpcode::STACKMAP:
20237 case TargetOpcode::PATCHPOINT:
20238 return emitPatchPoint(MI, BB);
20240 case X86::VFMADDPDr213r:
20241 case X86::VFMADDPSr213r:
20242 case X86::VFMADDSDr213r:
20243 case X86::VFMADDSSr213r:
20244 case X86::VFMSUBPDr213r:
20245 case X86::VFMSUBPSr213r:
20246 case X86::VFMSUBSDr213r:
20247 case X86::VFMSUBSSr213r:
20248 case X86::VFNMADDPDr213r:
20249 case X86::VFNMADDPSr213r:
20250 case X86::VFNMADDSDr213r:
20251 case X86::VFNMADDSSr213r:
20252 case X86::VFNMSUBPDr213r:
20253 case X86::VFNMSUBPSr213r:
20254 case X86::VFNMSUBSDr213r:
20255 case X86::VFNMSUBSSr213r:
20256 case X86::VFMADDSUBPDr213r:
20257 case X86::VFMADDSUBPSr213r:
20258 case X86::VFMSUBADDPDr213r:
20259 case X86::VFMSUBADDPSr213r:
20260 case X86::VFMADDPDr213rY:
20261 case X86::VFMADDPSr213rY:
20262 case X86::VFMSUBPDr213rY:
20263 case X86::VFMSUBPSr213rY:
20264 case X86::VFNMADDPDr213rY:
20265 case X86::VFNMADDPSr213rY:
20266 case X86::VFNMSUBPDr213rY:
20267 case X86::VFNMSUBPSr213rY:
20268 case X86::VFMADDSUBPDr213rY:
20269 case X86::VFMADDSUBPSr213rY:
20270 case X86::VFMSUBADDPDr213rY:
20271 case X86::VFMSUBADDPSr213rY:
20272 return emitFMA3Instr(MI, BB);
20276 //===----------------------------------------------------------------------===//
20277 // X86 Optimization Hooks
20278 //===----------------------------------------------------------------------===//
20280 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20283 const SelectionDAG &DAG,
20284 unsigned Depth) const {
20285 unsigned BitWidth = KnownZero.getBitWidth();
20286 unsigned Opc = Op.getOpcode();
20287 assert((Opc >= ISD::BUILTIN_OP_END ||
20288 Opc == ISD::INTRINSIC_WO_CHAIN ||
20289 Opc == ISD::INTRINSIC_W_CHAIN ||
20290 Opc == ISD::INTRINSIC_VOID) &&
20291 "Should use MaskedValueIsZero if you don't know whether Op"
20292 " is a target node!");
20294 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20308 // These nodes' second result is a boolean.
20309 if (Op.getResNo() == 0)
20312 case X86ISD::SETCC:
20313 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20315 case ISD::INTRINSIC_WO_CHAIN: {
20316 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20317 unsigned NumLoBits = 0;
20320 case Intrinsic::x86_sse_movmsk_ps:
20321 case Intrinsic::x86_avx_movmsk_ps_256:
20322 case Intrinsic::x86_sse2_movmsk_pd:
20323 case Intrinsic::x86_avx_movmsk_pd_256:
20324 case Intrinsic::x86_mmx_pmovmskb:
20325 case Intrinsic::x86_sse2_pmovmskb_128:
20326 case Intrinsic::x86_avx2_pmovmskb: {
20327 // High bits of movmskp{s|d}, pmovmskb are known zero.
20329 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20330 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20331 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20332 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20333 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20334 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20335 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20336 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20338 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20347 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20349 const SelectionDAG &,
20350 unsigned Depth) const {
20351 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20352 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20353 return Op.getValueType().getScalarType().getSizeInBits();
20359 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20360 /// node is a GlobalAddress + offset.
20361 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20362 const GlobalValue* &GA,
20363 int64_t &Offset) const {
20364 if (N->getOpcode() == X86ISD::Wrapper) {
20365 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20366 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20367 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20371 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20374 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20375 /// same as extracting the high 128-bit part of 256-bit vector and then
20376 /// inserting the result into the low part of a new 256-bit vector
20377 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20378 EVT VT = SVOp->getValueType(0);
20379 unsigned NumElems = VT.getVectorNumElements();
20381 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20382 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20383 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20384 SVOp->getMaskElt(j) >= 0)
20390 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20391 /// same as extracting the low 128-bit part of 256-bit vector and then
20392 /// inserting the result into the high part of a new 256-bit vector
20393 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20394 EVT VT = SVOp->getValueType(0);
20395 unsigned NumElems = VT.getVectorNumElements();
20397 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20398 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20399 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20400 SVOp->getMaskElt(j) >= 0)
20406 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20407 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20408 TargetLowering::DAGCombinerInfo &DCI,
20409 const X86Subtarget* Subtarget) {
20411 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20412 SDValue V1 = SVOp->getOperand(0);
20413 SDValue V2 = SVOp->getOperand(1);
20414 EVT VT = SVOp->getValueType(0);
20415 unsigned NumElems = VT.getVectorNumElements();
20417 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20418 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20422 // V UNDEF BUILD_VECTOR UNDEF
20424 // CONCAT_VECTOR CONCAT_VECTOR
20427 // RESULT: V + zero extended
20429 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20430 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20431 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20434 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20437 // To match the shuffle mask, the first half of the mask should
20438 // be exactly the first vector, and all the rest a splat with the
20439 // first element of the second one.
20440 for (unsigned i = 0; i != NumElems/2; ++i)
20441 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20442 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20445 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20446 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20447 if (Ld->hasNUsesOfValue(1, 0)) {
20448 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20449 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20451 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20453 Ld->getPointerInfo(),
20454 Ld->getAlignment(),
20455 false/*isVolatile*/, true/*ReadMem*/,
20456 false/*WriteMem*/);
20458 // Make sure the newly-created LOAD is in the same position as Ld in
20459 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20460 // and update uses of Ld's output chain to use the TokenFactor.
20461 if (Ld->hasAnyUseOfValue(1)) {
20462 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20463 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20464 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20465 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20466 SDValue(ResNode.getNode(), 1));
20469 return DAG.getBitcast(VT, ResNode);
20473 // Emit a zeroed vector and insert the desired subvector on its
20475 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20476 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20477 return DCI.CombineTo(N, InsV);
20480 //===--------------------------------------------------------------------===//
20481 // Combine some shuffles into subvector extracts and inserts:
20484 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20485 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20486 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20487 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20488 return DCI.CombineTo(N, InsV);
20491 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20492 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20493 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20494 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20495 return DCI.CombineTo(N, InsV);
20501 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20504 /// This is the leaf of the recursive combinine below. When we have found some
20505 /// chain of single-use x86 shuffle instructions and accumulated the combined
20506 /// shuffle mask represented by them, this will try to pattern match that mask
20507 /// into either a single instruction if there is a special purpose instruction
20508 /// for this operation, or into a PSHUFB instruction which is a fully general
20509 /// instruction but should only be used to replace chains over a certain depth.
20510 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20511 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20512 TargetLowering::DAGCombinerInfo &DCI,
20513 const X86Subtarget *Subtarget) {
20514 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20516 // Find the operand that enters the chain. Note that multiple uses are OK
20517 // here, we're not going to remove the operand we find.
20518 SDValue Input = Op.getOperand(0);
20519 while (Input.getOpcode() == ISD::BITCAST)
20520 Input = Input.getOperand(0);
20522 MVT VT = Input.getSimpleValueType();
20523 MVT RootVT = Root.getSimpleValueType();
20526 // Just remove no-op shuffle masks.
20527 if (Mask.size() == 1) {
20528 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20533 // Use the float domain if the operand type is a floating point type.
20534 bool FloatDomain = VT.isFloatingPoint();
20536 // For floating point shuffles, we don't have free copies in the shuffle
20537 // instructions or the ability to load as part of the instruction, so
20538 // canonicalize their shuffles to UNPCK or MOV variants.
20540 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20541 // vectors because it can have a load folded into it that UNPCK cannot. This
20542 // doesn't preclude something switching to the shorter encoding post-RA.
20544 // FIXME: Should teach these routines about AVX vector widths.
20545 if (FloatDomain && VT.getSizeInBits() == 128) {
20546 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20547 bool Lo = Mask.equals({0, 0});
20550 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20551 // is no slower than UNPCKLPD but has the option to fold the input operand
20552 // into even an unaligned memory load.
20553 if (Lo && Subtarget->hasSSE3()) {
20554 Shuffle = X86ISD::MOVDDUP;
20555 ShuffleVT = MVT::v2f64;
20557 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20558 // than the UNPCK variants.
20559 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20560 ShuffleVT = MVT::v4f32;
20562 if (Depth == 1 && Root->getOpcode() == Shuffle)
20563 return false; // Nothing to do!
20564 Op = DAG.getBitcast(ShuffleVT, Input);
20565 DCI.AddToWorklist(Op.getNode());
20566 if (Shuffle == X86ISD::MOVDDUP)
20567 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20569 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20570 DCI.AddToWorklist(Op.getNode());
20571 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20575 if (Subtarget->hasSSE3() &&
20576 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20577 bool Lo = Mask.equals({0, 0, 2, 2});
20578 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20579 MVT ShuffleVT = MVT::v4f32;
20580 if (Depth == 1 && Root->getOpcode() == Shuffle)
20581 return false; // Nothing to do!
20582 Op = DAG.getBitcast(ShuffleVT, Input);
20583 DCI.AddToWorklist(Op.getNode());
20584 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20585 DCI.AddToWorklist(Op.getNode());
20586 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20590 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20591 bool Lo = Mask.equals({0, 0, 1, 1});
20592 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20593 MVT ShuffleVT = MVT::v4f32;
20594 if (Depth == 1 && Root->getOpcode() == Shuffle)
20595 return false; // Nothing to do!
20596 Op = DAG.getBitcast(ShuffleVT, Input);
20597 DCI.AddToWorklist(Op.getNode());
20598 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20599 DCI.AddToWorklist(Op.getNode());
20600 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20606 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20607 // variants as none of these have single-instruction variants that are
20608 // superior to the UNPCK formulation.
20609 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20610 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20611 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20612 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20614 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20615 bool Lo = Mask[0] == 0;
20616 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20617 if (Depth == 1 && Root->getOpcode() == Shuffle)
20618 return false; // Nothing to do!
20620 switch (Mask.size()) {
20622 ShuffleVT = MVT::v8i16;
20625 ShuffleVT = MVT::v16i8;
20628 llvm_unreachable("Impossible mask size!");
20630 Op = DAG.getBitcast(ShuffleVT, Input);
20631 DCI.AddToWorklist(Op.getNode());
20632 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20633 DCI.AddToWorklist(Op.getNode());
20634 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20639 // Don't try to re-form single instruction chains under any circumstances now
20640 // that we've done encoding canonicalization for them.
20644 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20645 // can replace them with a single PSHUFB instruction profitably. Intel's
20646 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20647 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20648 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20649 SmallVector<SDValue, 16> PSHUFBMask;
20650 int NumBytes = VT.getSizeInBits() / 8;
20651 int Ratio = NumBytes / Mask.size();
20652 for (int i = 0; i < NumBytes; ++i) {
20653 if (Mask[i / Ratio] == SM_SentinelUndef) {
20654 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20657 int M = Mask[i / Ratio] != SM_SentinelZero
20658 ? Ratio * Mask[i / Ratio] + i % Ratio
20660 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20662 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20663 Op = DAG.getBitcast(ByteVT, Input);
20664 DCI.AddToWorklist(Op.getNode());
20665 SDValue PSHUFBMaskOp =
20666 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20667 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20668 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20669 DCI.AddToWorklist(Op.getNode());
20670 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20675 // Failed to find any combines.
20679 /// \brief Fully generic combining of x86 shuffle instructions.
20681 /// This should be the last combine run over the x86 shuffle instructions. Once
20682 /// they have been fully optimized, this will recursively consider all chains
20683 /// of single-use shuffle instructions, build a generic model of the cumulative
20684 /// shuffle operation, and check for simpler instructions which implement this
20685 /// operation. We use this primarily for two purposes:
20687 /// 1) Collapse generic shuffles to specialized single instructions when
20688 /// equivalent. In most cases, this is just an encoding size win, but
20689 /// sometimes we will collapse multiple generic shuffles into a single
20690 /// special-purpose shuffle.
20691 /// 2) Look for sequences of shuffle instructions with 3 or more total
20692 /// instructions, and replace them with the slightly more expensive SSSE3
20693 /// PSHUFB instruction if available. We do this as the last combining step
20694 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20695 /// a suitable short sequence of other instructions. The PHUFB will either
20696 /// use a register or have to read from memory and so is slightly (but only
20697 /// slightly) more expensive than the other shuffle instructions.
20699 /// Because this is inherently a quadratic operation (for each shuffle in
20700 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20701 /// This should never be an issue in practice as the shuffle lowering doesn't
20702 /// produce sequences of more than 8 instructions.
20704 /// FIXME: We will currently miss some cases where the redundant shuffling
20705 /// would simplify under the threshold for PSHUFB formation because of
20706 /// combine-ordering. To fix this, we should do the redundant instruction
20707 /// combining in this recursive walk.
20708 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20709 ArrayRef<int> RootMask,
20710 int Depth, bool HasPSHUFB,
20712 TargetLowering::DAGCombinerInfo &DCI,
20713 const X86Subtarget *Subtarget) {
20714 // Bound the depth of our recursive combine because this is ultimately
20715 // quadratic in nature.
20719 // Directly rip through bitcasts to find the underlying operand.
20720 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20721 Op = Op.getOperand(0);
20723 MVT VT = Op.getSimpleValueType();
20724 if (!VT.isVector())
20725 return false; // Bail if we hit a non-vector.
20727 assert(Root.getSimpleValueType().isVector() &&
20728 "Shuffles operate on vector types!");
20729 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20730 "Can only combine shuffles of the same vector register size.");
20732 if (!isTargetShuffle(Op.getOpcode()))
20734 SmallVector<int, 16> OpMask;
20736 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20737 // We only can combine unary shuffles which we can decode the mask for.
20738 if (!HaveMask || !IsUnary)
20741 assert(VT.getVectorNumElements() == OpMask.size() &&
20742 "Different mask size from vector size!");
20743 assert(((RootMask.size() > OpMask.size() &&
20744 RootMask.size() % OpMask.size() == 0) ||
20745 (OpMask.size() > RootMask.size() &&
20746 OpMask.size() % RootMask.size() == 0) ||
20747 OpMask.size() == RootMask.size()) &&
20748 "The smaller number of elements must divide the larger.");
20749 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20750 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20751 assert(((RootRatio == 1 && OpRatio == 1) ||
20752 (RootRatio == 1) != (OpRatio == 1)) &&
20753 "Must not have a ratio for both incoming and op masks!");
20755 SmallVector<int, 16> Mask;
20756 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20758 // Merge this shuffle operation's mask into our accumulated mask. Note that
20759 // this shuffle's mask will be the first applied to the input, followed by the
20760 // root mask to get us all the way to the root value arrangement. The reason
20761 // for this order is that we are recursing up the operation chain.
20762 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20763 int RootIdx = i / RootRatio;
20764 if (RootMask[RootIdx] < 0) {
20765 // This is a zero or undef lane, we're done.
20766 Mask.push_back(RootMask[RootIdx]);
20770 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20771 int OpIdx = RootMaskedIdx / OpRatio;
20772 if (OpMask[OpIdx] < 0) {
20773 // The incoming lanes are zero or undef, it doesn't matter which ones we
20775 Mask.push_back(OpMask[OpIdx]);
20779 // Ok, we have non-zero lanes, map them through.
20780 Mask.push_back(OpMask[OpIdx] * OpRatio +
20781 RootMaskedIdx % OpRatio);
20784 // See if we can recurse into the operand to combine more things.
20785 switch (Op.getOpcode()) {
20786 case X86ISD::PSHUFB:
20788 case X86ISD::PSHUFD:
20789 case X86ISD::PSHUFHW:
20790 case X86ISD::PSHUFLW:
20791 if (Op.getOperand(0).hasOneUse() &&
20792 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20793 HasPSHUFB, DAG, DCI, Subtarget))
20797 case X86ISD::UNPCKL:
20798 case X86ISD::UNPCKH:
20799 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20800 // We can't check for single use, we have to check that this shuffle is the only user.
20801 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20802 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20803 HasPSHUFB, DAG, DCI, Subtarget))
20808 // Minor canonicalization of the accumulated shuffle mask to make it easier
20809 // to match below. All this does is detect masks with squential pairs of
20810 // elements, and shrink them to the half-width mask. It does this in a loop
20811 // so it will reduce the size of the mask to the minimal width mask which
20812 // performs an equivalent shuffle.
20813 SmallVector<int, 16> WidenedMask;
20814 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20815 Mask = std::move(WidenedMask);
20816 WidenedMask.clear();
20819 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20823 /// \brief Get the PSHUF-style mask from PSHUF node.
20825 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20826 /// PSHUF-style masks that can be reused with such instructions.
20827 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20828 MVT VT = N.getSimpleValueType();
20829 SmallVector<int, 4> Mask;
20831 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20835 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20836 // matter. Check that the upper masks are repeats and remove them.
20837 if (VT.getSizeInBits() > 128) {
20838 int LaneElts = 128 / VT.getScalarSizeInBits();
20840 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20841 for (int j = 0; j < LaneElts; ++j)
20842 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
20843 "Mask doesn't repeat in high 128-bit lanes!");
20845 Mask.resize(LaneElts);
20848 switch (N.getOpcode()) {
20849 case X86ISD::PSHUFD:
20851 case X86ISD::PSHUFLW:
20854 case X86ISD::PSHUFHW:
20855 Mask.erase(Mask.begin(), Mask.begin() + 4);
20856 for (int &M : Mask)
20860 llvm_unreachable("No valid shuffle instruction found!");
20864 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20866 /// We walk up the chain and look for a combinable shuffle, skipping over
20867 /// shuffles that we could hoist this shuffle's transformation past without
20868 /// altering anything.
20870 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20872 TargetLowering::DAGCombinerInfo &DCI) {
20873 assert(N.getOpcode() == X86ISD::PSHUFD &&
20874 "Called with something other than an x86 128-bit half shuffle!");
20877 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20878 // of the shuffles in the chain so that we can form a fresh chain to replace
20880 SmallVector<SDValue, 8> Chain;
20881 SDValue V = N.getOperand(0);
20882 for (; V.hasOneUse(); V = V.getOperand(0)) {
20883 switch (V.getOpcode()) {
20885 return SDValue(); // Nothing combined!
20888 // Skip bitcasts as we always know the type for the target specific
20892 case X86ISD::PSHUFD:
20893 // Found another dword shuffle.
20896 case X86ISD::PSHUFLW:
20897 // Check that the low words (being shuffled) are the identity in the
20898 // dword shuffle, and the high words are self-contained.
20899 if (Mask[0] != 0 || Mask[1] != 1 ||
20900 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20903 Chain.push_back(V);
20906 case X86ISD::PSHUFHW:
20907 // Check that the high words (being shuffled) are the identity in the
20908 // dword shuffle, and the low words are self-contained.
20909 if (Mask[2] != 2 || Mask[3] != 3 ||
20910 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20913 Chain.push_back(V);
20916 case X86ISD::UNPCKL:
20917 case X86ISD::UNPCKH:
20918 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20919 // shuffle into a preceding word shuffle.
20920 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20921 V.getSimpleValueType().getScalarType() != MVT::i16)
20924 // Search for a half-shuffle which we can combine with.
20925 unsigned CombineOp =
20926 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20927 if (V.getOperand(0) != V.getOperand(1) ||
20928 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20930 Chain.push_back(V);
20931 V = V.getOperand(0);
20933 switch (V.getOpcode()) {
20935 return SDValue(); // Nothing to combine.
20937 case X86ISD::PSHUFLW:
20938 case X86ISD::PSHUFHW:
20939 if (V.getOpcode() == CombineOp)
20942 Chain.push_back(V);
20946 V = V.getOperand(0);
20950 } while (V.hasOneUse());
20953 // Break out of the loop if we break out of the switch.
20957 if (!V.hasOneUse())
20958 // We fell out of the loop without finding a viable combining instruction.
20961 // Merge this node's mask and our incoming mask.
20962 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20963 for (int &M : Mask)
20965 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20966 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20968 // Rebuild the chain around this new shuffle.
20969 while (!Chain.empty()) {
20970 SDValue W = Chain.pop_back_val();
20972 if (V.getValueType() != W.getOperand(0).getValueType())
20973 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
20975 switch (W.getOpcode()) {
20977 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20979 case X86ISD::UNPCKL:
20980 case X86ISD::UNPCKH:
20981 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20984 case X86ISD::PSHUFD:
20985 case X86ISD::PSHUFLW:
20986 case X86ISD::PSHUFHW:
20987 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20991 if (V.getValueType() != N.getValueType())
20992 V = DAG.getBitcast(N.getValueType(), V);
20994 // Return the new chain to replace N.
20998 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21000 /// We walk up the chain, skipping shuffles of the other half and looking
21001 /// through shuffles which switch halves trying to find a shuffle of the same
21002 /// pair of dwords.
21003 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21005 TargetLowering::DAGCombinerInfo &DCI) {
21007 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21008 "Called with something other than an x86 128-bit half shuffle!");
21010 unsigned CombineOpcode = N.getOpcode();
21012 // Walk up a single-use chain looking for a combinable shuffle.
21013 SDValue V = N.getOperand(0);
21014 for (; V.hasOneUse(); V = V.getOperand(0)) {
21015 switch (V.getOpcode()) {
21017 return false; // Nothing combined!
21020 // Skip bitcasts as we always know the type for the target specific
21024 case X86ISD::PSHUFLW:
21025 case X86ISD::PSHUFHW:
21026 if (V.getOpcode() == CombineOpcode)
21029 // Other-half shuffles are no-ops.
21032 // Break out of the loop if we break out of the switch.
21036 if (!V.hasOneUse())
21037 // We fell out of the loop without finding a viable combining instruction.
21040 // Combine away the bottom node as its shuffle will be accumulated into
21041 // a preceding shuffle.
21042 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21044 // Record the old value.
21047 // Merge this node's mask and our incoming mask (adjusted to account for all
21048 // the pshufd instructions encountered).
21049 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21050 for (int &M : Mask)
21052 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21053 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21055 // Check that the shuffles didn't cancel each other out. If not, we need to
21056 // combine to the new one.
21058 // Replace the combinable shuffle with the combined one, updating all users
21059 // so that we re-evaluate the chain here.
21060 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21065 /// \brief Try to combine x86 target specific shuffles.
21066 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21067 TargetLowering::DAGCombinerInfo &DCI,
21068 const X86Subtarget *Subtarget) {
21070 MVT VT = N.getSimpleValueType();
21071 SmallVector<int, 4> Mask;
21073 switch (N.getOpcode()) {
21074 case X86ISD::PSHUFD:
21075 case X86ISD::PSHUFLW:
21076 case X86ISD::PSHUFHW:
21077 Mask = getPSHUFShuffleMask(N);
21078 assert(Mask.size() == 4);
21084 // Nuke no-op shuffles that show up after combining.
21085 if (isNoopShuffleMask(Mask))
21086 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21088 // Look for simplifications involving one or two shuffle instructions.
21089 SDValue V = N.getOperand(0);
21090 switch (N.getOpcode()) {
21093 case X86ISD::PSHUFLW:
21094 case X86ISD::PSHUFHW:
21095 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21097 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21098 return SDValue(); // We combined away this shuffle, so we're done.
21100 // See if this reduces to a PSHUFD which is no more expensive and can
21101 // combine with more operations. Note that it has to at least flip the
21102 // dwords as otherwise it would have been removed as a no-op.
21103 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21104 int DMask[] = {0, 1, 2, 3};
21105 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21106 DMask[DOffset + 0] = DOffset + 1;
21107 DMask[DOffset + 1] = DOffset + 0;
21108 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21109 V = DAG.getBitcast(DVT, V);
21110 DCI.AddToWorklist(V.getNode());
21111 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21112 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21113 DCI.AddToWorklist(V.getNode());
21114 return DAG.getBitcast(VT, V);
21117 // Look for shuffle patterns which can be implemented as a single unpack.
21118 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21119 // only works when we have a PSHUFD followed by two half-shuffles.
21120 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21121 (V.getOpcode() == X86ISD::PSHUFLW ||
21122 V.getOpcode() == X86ISD::PSHUFHW) &&
21123 V.getOpcode() != N.getOpcode() &&
21125 SDValue D = V.getOperand(0);
21126 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21127 D = D.getOperand(0);
21128 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21129 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21130 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21131 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21132 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21134 for (int i = 0; i < 4; ++i) {
21135 WordMask[i + NOffset] = Mask[i] + NOffset;
21136 WordMask[i + VOffset] = VMask[i] + VOffset;
21138 // Map the word mask through the DWord mask.
21140 for (int i = 0; i < 8; ++i)
21141 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21142 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21143 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21144 // We can replace all three shuffles with an unpack.
21145 V = DAG.getBitcast(VT, D.getOperand(0));
21146 DCI.AddToWorklist(V.getNode());
21147 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21156 case X86ISD::PSHUFD:
21157 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21166 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21168 /// We combine this directly on the abstract vector shuffle nodes so it is
21169 /// easier to generically match. We also insert dummy vector shuffle nodes for
21170 /// the operands which explicitly discard the lanes which are unused by this
21171 /// operation to try to flow through the rest of the combiner the fact that
21172 /// they're unused.
21173 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21175 EVT VT = N->getValueType(0);
21177 // We only handle target-independent shuffles.
21178 // FIXME: It would be easy and harmless to use the target shuffle mask
21179 // extraction tool to support more.
21180 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21183 auto *SVN = cast<ShuffleVectorSDNode>(N);
21184 ArrayRef<int> Mask = SVN->getMask();
21185 SDValue V1 = N->getOperand(0);
21186 SDValue V2 = N->getOperand(1);
21188 // We require the first shuffle operand to be the SUB node, and the second to
21189 // be the ADD node.
21190 // FIXME: We should support the commuted patterns.
21191 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21194 // If there are other uses of these operations we can't fold them.
21195 if (!V1->hasOneUse() || !V2->hasOneUse())
21198 // Ensure that both operations have the same operands. Note that we can
21199 // commute the FADD operands.
21200 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21201 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21202 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21205 // We're looking for blends between FADD and FSUB nodes. We insist on these
21206 // nodes being lined up in a specific expected pattern.
21207 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21208 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21209 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21212 // Only specific types are legal at this point, assert so we notice if and
21213 // when these change.
21214 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21215 VT == MVT::v4f64) &&
21216 "Unknown vector type encountered!");
21218 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21221 /// PerformShuffleCombine - Performs several different shuffle combines.
21222 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21223 TargetLowering::DAGCombinerInfo &DCI,
21224 const X86Subtarget *Subtarget) {
21226 SDValue N0 = N->getOperand(0);
21227 SDValue N1 = N->getOperand(1);
21228 EVT VT = N->getValueType(0);
21230 // Don't create instructions with illegal types after legalize types has run.
21231 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21232 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21235 // If we have legalized the vector types, look for blends of FADD and FSUB
21236 // nodes that we can fuse into an ADDSUB node.
21237 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21238 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21241 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21242 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21243 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21244 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21246 // During Type Legalization, when promoting illegal vector types,
21247 // the backend might introduce new shuffle dag nodes and bitcasts.
21249 // This code performs the following transformation:
21250 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21251 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21253 // We do this only if both the bitcast and the BINOP dag nodes have
21254 // one use. Also, perform this transformation only if the new binary
21255 // operation is legal. This is to avoid introducing dag nodes that
21256 // potentially need to be further expanded (or custom lowered) into a
21257 // less optimal sequence of dag nodes.
21258 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21259 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21260 N0.getOpcode() == ISD::BITCAST) {
21261 SDValue BC0 = N0.getOperand(0);
21262 EVT SVT = BC0.getValueType();
21263 unsigned Opcode = BC0.getOpcode();
21264 unsigned NumElts = VT.getVectorNumElements();
21266 if (BC0.hasOneUse() && SVT.isVector() &&
21267 SVT.getVectorNumElements() * 2 == NumElts &&
21268 TLI.isOperationLegal(Opcode, VT)) {
21269 bool CanFold = false;
21281 unsigned SVTNumElts = SVT.getVectorNumElements();
21282 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21283 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21284 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21285 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21286 CanFold = SVOp->getMaskElt(i) < 0;
21289 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21290 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21291 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21292 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21297 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21298 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21299 // consecutive, non-overlapping, and in the right order.
21300 SmallVector<SDValue, 16> Elts;
21301 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21302 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21304 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21308 if (isTargetShuffle(N->getOpcode())) {
21310 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21311 if (Shuffle.getNode())
21314 // Try recursively combining arbitrary sequences of x86 shuffle
21315 // instructions into higher-order shuffles. We do this after combining
21316 // specific PSHUF instruction sequences into their minimal form so that we
21317 // can evaluate how many specialized shuffle instructions are involved in
21318 // a particular chain.
21319 SmallVector<int, 1> NonceMask; // Just a placeholder.
21320 NonceMask.push_back(0);
21321 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21322 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21324 return SDValue(); // This routine will use CombineTo to replace N.
21330 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21331 /// specific shuffle of a load can be folded into a single element load.
21332 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21333 /// shuffles have been custom lowered so we need to handle those here.
21334 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21335 TargetLowering::DAGCombinerInfo &DCI) {
21336 if (DCI.isBeforeLegalizeOps())
21339 SDValue InVec = N->getOperand(0);
21340 SDValue EltNo = N->getOperand(1);
21342 if (!isa<ConstantSDNode>(EltNo))
21345 EVT OriginalVT = InVec.getValueType();
21347 if (InVec.getOpcode() == ISD::BITCAST) {
21348 // Don't duplicate a load with other uses.
21349 if (!InVec.hasOneUse())
21351 EVT BCVT = InVec.getOperand(0).getValueType();
21352 if (!BCVT.isVector() ||
21353 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21355 InVec = InVec.getOperand(0);
21358 EVT CurrentVT = InVec.getValueType();
21360 if (!isTargetShuffle(InVec.getOpcode()))
21363 // Don't duplicate a load with other uses.
21364 if (!InVec.hasOneUse())
21367 SmallVector<int, 16> ShuffleMask;
21369 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21370 ShuffleMask, UnaryShuffle))
21373 // Select the input vector, guarding against out of range extract vector.
21374 unsigned NumElems = CurrentVT.getVectorNumElements();
21375 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21376 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21377 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21378 : InVec.getOperand(1);
21380 // If inputs to shuffle are the same for both ops, then allow 2 uses
21381 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21382 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21384 if (LdNode.getOpcode() == ISD::BITCAST) {
21385 // Don't duplicate a load with other uses.
21386 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21389 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21390 LdNode = LdNode.getOperand(0);
21393 if (!ISD::isNormalLoad(LdNode.getNode()))
21396 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21398 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21401 EVT EltVT = N->getValueType(0);
21402 // If there's a bitcast before the shuffle, check if the load type and
21403 // alignment is valid.
21404 unsigned Align = LN0->getAlignment();
21405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21406 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21407 EltVT.getTypeForEVT(*DAG.getContext()));
21409 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21412 // All checks match so transform back to vector_shuffle so that DAG combiner
21413 // can finish the job
21416 // Create shuffle node taking into account the case that its a unary shuffle
21417 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21418 : InVec.getOperand(1);
21419 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21420 InVec.getOperand(0), Shuffle,
21422 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21423 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21427 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21428 /// special and don't usually play with other vector types, it's better to
21429 /// handle them early to be sure we emit efficient code by avoiding
21430 /// store-load conversions.
21431 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21432 if (N->getValueType(0) != MVT::x86mmx ||
21433 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21434 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21437 SDValue V = N->getOperand(0);
21438 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21439 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21440 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21441 N->getValueType(0), V.getOperand(0));
21446 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21447 /// generation and convert it from being a bunch of shuffles and extracts
21448 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21449 /// storing the value and loading scalars back, while for x64 we should
21450 /// use 64-bit extracts and shifts.
21451 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21452 TargetLowering::DAGCombinerInfo &DCI) {
21453 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21454 if (NewOp.getNode())
21457 SDValue InputVector = N->getOperand(0);
21458 SDLoc dl(InputVector);
21459 // Detect mmx to i32 conversion through a v2i32 elt extract.
21460 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21461 N->getValueType(0) == MVT::i32 &&
21462 InputVector.getValueType() == MVT::v2i32) {
21464 // The bitcast source is a direct mmx result.
21465 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21466 if (MMXSrc.getValueType() == MVT::x86mmx)
21467 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21468 N->getValueType(0),
21469 InputVector.getNode()->getOperand(0));
21471 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21472 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21473 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21474 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21475 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21476 MMXSrcOp.getValueType() == MVT::v1i64 &&
21477 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21478 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21479 N->getValueType(0),
21480 MMXSrcOp.getOperand(0));
21483 EVT VT = N->getValueType(0);
21485 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21486 InputVector.getOpcode() == ISD::BITCAST &&
21487 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21488 uint64_t ExtractedElt =
21489 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21490 uint64_t InputValue =
21491 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21492 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21493 return DAG.getConstant(Res, dl, MVT::i1);
21495 // Only operate on vectors of 4 elements, where the alternative shuffling
21496 // gets to be more expensive.
21497 if (InputVector.getValueType() != MVT::v4i32)
21500 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21501 // single use which is a sign-extend or zero-extend, and all elements are
21503 SmallVector<SDNode *, 4> Uses;
21504 unsigned ExtractedElements = 0;
21505 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21506 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21507 if (UI.getUse().getResNo() != InputVector.getResNo())
21510 SDNode *Extract = *UI;
21511 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21514 if (Extract->getValueType(0) != MVT::i32)
21516 if (!Extract->hasOneUse())
21518 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21519 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21521 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21524 // Record which element was extracted.
21525 ExtractedElements |=
21526 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21528 Uses.push_back(Extract);
21531 // If not all the elements were used, this may not be worthwhile.
21532 if (ExtractedElements != 15)
21535 // Ok, we've now decided to do the transformation.
21536 // If 64-bit shifts are legal, use the extract-shift sequence,
21537 // otherwise bounce the vector off the cache.
21538 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21541 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21542 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21543 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21544 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21545 DAG.getConstant(0, dl, VecIdxTy));
21546 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21547 DAG.getConstant(1, dl, VecIdxTy));
21549 SDValue ShAmt = DAG.getConstant(32, dl,
21550 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21551 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21552 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21553 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21554 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21555 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21556 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21558 // Store the value to a temporary stack slot.
21559 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21560 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21561 MachinePointerInfo(), false, false, 0);
21563 EVT ElementType = InputVector.getValueType().getVectorElementType();
21564 unsigned EltSize = ElementType.getSizeInBits() / 8;
21566 // Replace each use (extract) with a load of the appropriate element.
21567 for (unsigned i = 0; i < 4; ++i) {
21568 uint64_t Offset = EltSize * i;
21569 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21571 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21572 StackPtr, OffsetVal);
21574 // Load the scalar.
21575 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21576 ScalarAddr, MachinePointerInfo(),
21577 false, false, false, 0);
21582 // Replace the extracts
21583 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21584 UE = Uses.end(); UI != UE; ++UI) {
21585 SDNode *Extract = *UI;
21587 SDValue Idx = Extract->getOperand(1);
21588 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21589 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21592 // The replacement was made in place; don't return anything.
21596 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21597 static std::pair<unsigned, bool>
21598 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21599 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21600 if (!VT.isVector())
21601 return std::make_pair(0, false);
21603 bool NeedSplit = false;
21604 switch (VT.getSimpleVT().SimpleTy) {
21605 default: return std::make_pair(0, false);
21608 if (!Subtarget->hasVLX())
21609 return std::make_pair(0, false);
21613 if (!Subtarget->hasBWI())
21614 return std::make_pair(0, false);
21618 if (!Subtarget->hasAVX512())
21619 return std::make_pair(0, false);
21624 if (!Subtarget->hasAVX2())
21626 if (!Subtarget->hasAVX())
21627 return std::make_pair(0, false);
21632 if (!Subtarget->hasSSE2())
21633 return std::make_pair(0, false);
21636 // SSE2 has only a small subset of the operations.
21637 bool hasUnsigned = Subtarget->hasSSE41() ||
21638 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21639 bool hasSigned = Subtarget->hasSSE41() ||
21640 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21642 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21645 // Check for x CC y ? x : y.
21646 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21647 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21652 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21655 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21658 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21661 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21663 // Check for x CC y ? y : x -- a min/max with reversed arms.
21664 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21665 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21670 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21673 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21676 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21679 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21683 return std::make_pair(Opc, NeedSplit);
21687 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21688 const X86Subtarget *Subtarget) {
21690 SDValue Cond = N->getOperand(0);
21691 SDValue LHS = N->getOperand(1);
21692 SDValue RHS = N->getOperand(2);
21694 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21695 SDValue CondSrc = Cond->getOperand(0);
21696 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21697 Cond = CondSrc->getOperand(0);
21700 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21703 // A vselect where all conditions and data are constants can be optimized into
21704 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21705 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21706 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21709 unsigned MaskValue = 0;
21710 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21713 MVT VT = N->getSimpleValueType(0);
21714 unsigned NumElems = VT.getVectorNumElements();
21715 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21716 for (unsigned i = 0; i < NumElems; ++i) {
21717 // Be sure we emit undef where we can.
21718 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21719 ShuffleMask[i] = -1;
21721 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21724 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21725 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21727 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21730 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21732 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21733 TargetLowering::DAGCombinerInfo &DCI,
21734 const X86Subtarget *Subtarget) {
21736 SDValue Cond = N->getOperand(0);
21737 // Get the LHS/RHS of the select.
21738 SDValue LHS = N->getOperand(1);
21739 SDValue RHS = N->getOperand(2);
21740 EVT VT = LHS.getValueType();
21741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21743 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21744 // instructions match the semantics of the common C idiom x<y?x:y but not
21745 // x<=y?x:y, because of how they handle negative zero (which can be
21746 // ignored in unsafe-math mode).
21747 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21748 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21749 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21750 (Subtarget->hasSSE2() ||
21751 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21752 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21754 unsigned Opcode = 0;
21755 // Check for x CC y ? x : y.
21756 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21757 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21761 // Converting this to a min would handle NaNs incorrectly, and swapping
21762 // the operands would cause it to handle comparisons between positive
21763 // and negative zero incorrectly.
21764 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21765 if (!DAG.getTarget().Options.UnsafeFPMath &&
21766 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21768 std::swap(LHS, RHS);
21770 Opcode = X86ISD::FMIN;
21773 // Converting this to a min would handle comparisons between positive
21774 // and negative zero incorrectly.
21775 if (!DAG.getTarget().Options.UnsafeFPMath &&
21776 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21778 Opcode = X86ISD::FMIN;
21781 // Converting this to a min would handle both negative zeros and NaNs
21782 // incorrectly, but we can swap the operands to fix both.
21783 std::swap(LHS, RHS);
21787 Opcode = X86ISD::FMIN;
21791 // Converting this to a max would handle comparisons between positive
21792 // and negative zero incorrectly.
21793 if (!DAG.getTarget().Options.UnsafeFPMath &&
21794 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21796 Opcode = X86ISD::FMAX;
21799 // Converting this to a max would handle NaNs incorrectly, and swapping
21800 // the operands would cause it to handle comparisons between positive
21801 // and negative zero incorrectly.
21802 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21803 if (!DAG.getTarget().Options.UnsafeFPMath &&
21804 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21806 std::swap(LHS, RHS);
21808 Opcode = X86ISD::FMAX;
21811 // Converting this to a max would handle both negative zeros and NaNs
21812 // incorrectly, but we can swap the operands to fix both.
21813 std::swap(LHS, RHS);
21817 Opcode = X86ISD::FMAX;
21820 // Check for x CC y ? y : x -- a min/max with reversed arms.
21821 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21822 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21826 // Converting this to a min would handle comparisons between positive
21827 // and negative zero incorrectly, and swapping the operands would
21828 // cause it to handle NaNs incorrectly.
21829 if (!DAG.getTarget().Options.UnsafeFPMath &&
21830 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21831 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21833 std::swap(LHS, RHS);
21835 Opcode = X86ISD::FMIN;
21838 // Converting this to a min would handle NaNs incorrectly.
21839 if (!DAG.getTarget().Options.UnsafeFPMath &&
21840 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21842 Opcode = X86ISD::FMIN;
21845 // Converting this to a min would handle both negative zeros and NaNs
21846 // incorrectly, but we can swap the operands to fix both.
21847 std::swap(LHS, RHS);
21851 Opcode = X86ISD::FMIN;
21855 // Converting this to a max would handle NaNs incorrectly.
21856 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21858 Opcode = X86ISD::FMAX;
21861 // Converting this to a max would handle comparisons between positive
21862 // and negative zero incorrectly, and swapping the operands would
21863 // cause it to handle NaNs incorrectly.
21864 if (!DAG.getTarget().Options.UnsafeFPMath &&
21865 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21866 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21868 std::swap(LHS, RHS);
21870 Opcode = X86ISD::FMAX;
21873 // Converting this to a max would handle both negative zeros and NaNs
21874 // incorrectly, but we can swap the operands to fix both.
21875 std::swap(LHS, RHS);
21879 Opcode = X86ISD::FMAX;
21885 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21888 EVT CondVT = Cond.getValueType();
21889 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21890 CondVT.getVectorElementType() == MVT::i1) {
21891 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21892 // lowering on KNL. In this case we convert it to
21893 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21894 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21895 // Since SKX these selects have a proper lowering.
21896 EVT OpVT = LHS.getValueType();
21897 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21898 (OpVT.getVectorElementType() == MVT::i8 ||
21899 OpVT.getVectorElementType() == MVT::i16) &&
21900 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21901 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21902 DCI.AddToWorklist(Cond.getNode());
21903 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21906 // If this is a select between two integer constants, try to do some
21908 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21909 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21910 // Don't do this for crazy integer types.
21911 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21912 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21913 // so that TrueC (the true value) is larger than FalseC.
21914 bool NeedsCondInvert = false;
21916 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21917 // Efficiently invertible.
21918 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21919 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21920 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21921 NeedsCondInvert = true;
21922 std::swap(TrueC, FalseC);
21925 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21926 if (FalseC->getAPIntValue() == 0 &&
21927 TrueC->getAPIntValue().isPowerOf2()) {
21928 if (NeedsCondInvert) // Invert the condition if needed.
21929 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21930 DAG.getConstant(1, DL, Cond.getValueType()));
21932 // Zero extend the condition if needed.
21933 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21935 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21936 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21937 DAG.getConstant(ShAmt, DL, MVT::i8));
21940 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21941 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21942 if (NeedsCondInvert) // Invert the condition if needed.
21943 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21944 DAG.getConstant(1, DL, Cond.getValueType()));
21946 // Zero extend the condition if needed.
21947 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21948 FalseC->getValueType(0), Cond);
21949 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21950 SDValue(FalseC, 0));
21953 // Optimize cases that will turn into an LEA instruction. This requires
21954 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21955 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21956 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21957 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21959 bool isFastMultiplier = false;
21961 switch ((unsigned char)Diff) {
21963 case 1: // result = add base, cond
21964 case 2: // result = lea base( , cond*2)
21965 case 3: // result = lea base(cond, cond*2)
21966 case 4: // result = lea base( , cond*4)
21967 case 5: // result = lea base(cond, cond*4)
21968 case 8: // result = lea base( , cond*8)
21969 case 9: // result = lea base(cond, cond*8)
21970 isFastMultiplier = true;
21975 if (isFastMultiplier) {
21976 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21977 if (NeedsCondInvert) // Invert the condition if needed.
21978 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21979 DAG.getConstant(1, DL, Cond.getValueType()));
21981 // Zero extend the condition if needed.
21982 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21984 // Scale the condition by the difference.
21986 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21987 DAG.getConstant(Diff, DL,
21988 Cond.getValueType()));
21990 // Add the base if non-zero.
21991 if (FalseC->getAPIntValue() != 0)
21992 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21993 SDValue(FalseC, 0));
22000 // Canonicalize max and min:
22001 // (x > y) ? x : y -> (x >= y) ? x : y
22002 // (x < y) ? x : y -> (x <= y) ? x : y
22003 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22004 // the need for an extra compare
22005 // against zero. e.g.
22006 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22008 // testl %edi, %edi
22010 // cmovgl %edi, %eax
22014 // cmovsl %eax, %edi
22015 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22016 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22017 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22018 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22023 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22024 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22025 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22026 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22031 // Early exit check
22032 if (!TLI.isTypeLegal(VT))
22035 // Match VSELECTs into subs with unsigned saturation.
22036 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22037 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22038 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22039 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22040 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22042 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22043 // left side invert the predicate to simplify logic below.
22045 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22047 CC = ISD::getSetCCInverse(CC, true);
22048 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22052 if (Other.getNode() && Other->getNumOperands() == 2 &&
22053 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22054 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22055 SDValue CondRHS = Cond->getOperand(1);
22057 // Look for a general sub with unsigned saturation first.
22058 // x >= y ? x-y : 0 --> subus x, y
22059 // x > y ? x-y : 0 --> subus x, y
22060 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22061 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22062 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22064 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22065 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22066 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22067 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22068 // If the RHS is a constant we have to reverse the const
22069 // canonicalization.
22070 // x > C-1 ? x+-C : 0 --> subus x, C
22071 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22072 CondRHSConst->getAPIntValue() ==
22073 (-OpRHSConst->getAPIntValue() - 1))
22074 return DAG.getNode(
22075 X86ISD::SUBUS, DL, VT, OpLHS,
22076 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22078 // Another special case: If C was a sign bit, the sub has been
22079 // canonicalized into a xor.
22080 // FIXME: Would it be better to use computeKnownBits to determine
22081 // whether it's safe to decanonicalize the xor?
22082 // x s< 0 ? x^C : 0 --> subus x, C
22083 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22084 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22085 OpRHSConst->getAPIntValue().isSignBit())
22086 // Note that we have to rebuild the RHS constant here to ensure we
22087 // don't rely on particular values of undef lanes.
22088 return DAG.getNode(
22089 X86ISD::SUBUS, DL, VT, OpLHS,
22090 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22095 // Try to match a min/max vector operation.
22096 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22097 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22098 unsigned Opc = ret.first;
22099 bool NeedSplit = ret.second;
22101 if (Opc && NeedSplit) {
22102 unsigned NumElems = VT.getVectorNumElements();
22103 // Extract the LHS vectors
22104 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22105 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22107 // Extract the RHS vectors
22108 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22109 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22111 // Create min/max for each subvector
22112 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22113 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22115 // Merge the result
22116 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22118 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22121 // Simplify vector selection if condition value type matches vselect
22123 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22124 assert(Cond.getValueType().isVector() &&
22125 "vector select expects a vector selector!");
22127 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22128 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22130 // Try invert the condition if true value is not all 1s and false value
22132 if (!TValIsAllOnes && !FValIsAllZeros &&
22133 // Check if the selector will be produced by CMPP*/PCMP*
22134 Cond.getOpcode() == ISD::SETCC &&
22135 // Check if SETCC has already been promoted
22136 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22137 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22138 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22140 if (TValIsAllZeros || FValIsAllOnes) {
22141 SDValue CC = Cond.getOperand(2);
22142 ISD::CondCode NewCC =
22143 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22144 Cond.getOperand(0).getValueType().isInteger());
22145 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22146 std::swap(LHS, RHS);
22147 TValIsAllOnes = FValIsAllOnes;
22148 FValIsAllZeros = TValIsAllZeros;
22152 if (TValIsAllOnes || FValIsAllZeros) {
22155 if (TValIsAllOnes && FValIsAllZeros)
22157 else if (TValIsAllOnes)
22159 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22160 else if (FValIsAllZeros)
22161 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22162 DAG.getBitcast(CondVT, LHS));
22164 return DAG.getBitcast(VT, Ret);
22168 // We should generate an X86ISD::BLENDI from a vselect if its argument
22169 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22170 // constants. This specific pattern gets generated when we split a
22171 // selector for a 512 bit vector in a machine without AVX512 (but with
22172 // 256-bit vectors), during legalization:
22174 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22176 // Iff we find this pattern and the build_vectors are built from
22177 // constants, we translate the vselect into a shuffle_vector that we
22178 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22179 if ((N->getOpcode() == ISD::VSELECT ||
22180 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22181 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22182 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22183 if (Shuffle.getNode())
22187 // If this is a *dynamic* select (non-constant condition) and we can match
22188 // this node with one of the variable blend instructions, restructure the
22189 // condition so that the blends can use the high bit of each element and use
22190 // SimplifyDemandedBits to simplify the condition operand.
22191 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22192 !DCI.isBeforeLegalize() &&
22193 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22194 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22196 // Don't optimize vector selects that map to mask-registers.
22200 // We can only handle the cases where VSELECT is directly legal on the
22201 // subtarget. We custom lower VSELECT nodes with constant conditions and
22202 // this makes it hard to see whether a dynamic VSELECT will correctly
22203 // lower, so we both check the operation's status and explicitly handle the
22204 // cases where a *dynamic* blend will fail even though a constant-condition
22205 // blend could be custom lowered.
22206 // FIXME: We should find a better way to handle this class of problems.
22207 // Potentially, we should combine constant-condition vselect nodes
22208 // pre-legalization into shuffles and not mark as many types as custom
22210 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22212 // FIXME: We don't support i16-element blends currently. We could and
22213 // should support them by making *all* the bits in the condition be set
22214 // rather than just the high bit and using an i8-element blend.
22215 if (VT.getScalarType() == MVT::i16)
22217 // Dynamic blending was only available from SSE4.1 onward.
22218 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22220 // Byte blends are only available in AVX2
22221 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22222 !Subtarget->hasAVX2())
22225 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22226 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22228 APInt KnownZero, KnownOne;
22229 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22230 DCI.isBeforeLegalizeOps());
22231 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22232 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22234 // If we changed the computation somewhere in the DAG, this change
22235 // will affect all users of Cond.
22236 // Make sure it is fine and update all the nodes so that we do not
22237 // use the generic VSELECT anymore. Otherwise, we may perform
22238 // wrong optimizations as we messed up with the actual expectation
22239 // for the vector boolean values.
22240 if (Cond != TLO.Old) {
22241 // Check all uses of that condition operand to check whether it will be
22242 // consumed by non-BLEND instructions, which may depend on all bits are
22244 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22246 if (I->getOpcode() != ISD::VSELECT)
22247 // TODO: Add other opcodes eventually lowered into BLEND.
22250 // Update all the users of the condition, before committing the change,
22251 // so that the VSELECT optimizations that expect the correct vector
22252 // boolean value will not be triggered.
22253 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22255 DAG.ReplaceAllUsesOfValueWith(
22257 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22258 Cond, I->getOperand(1), I->getOperand(2)));
22259 DCI.CommitTargetLoweringOpt(TLO);
22262 // At this point, only Cond is changed. Change the condition
22263 // just for N to keep the opportunity to optimize all other
22264 // users their own way.
22265 DAG.ReplaceAllUsesOfValueWith(
22267 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22268 TLO.New, N->getOperand(1), N->getOperand(2)));
22276 // Check whether a boolean test is testing a boolean value generated by
22277 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22280 // Simplify the following patterns:
22281 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22282 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22283 // to (Op EFLAGS Cond)
22285 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22286 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22287 // to (Op EFLAGS !Cond)
22289 // where Op could be BRCOND or CMOV.
22291 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22292 // Quit if not CMP and SUB with its value result used.
22293 if (Cmp.getOpcode() != X86ISD::CMP &&
22294 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22297 // Quit if not used as a boolean value.
22298 if (CC != X86::COND_E && CC != X86::COND_NE)
22301 // Check CMP operands. One of them should be 0 or 1 and the other should be
22302 // an SetCC or extended from it.
22303 SDValue Op1 = Cmp.getOperand(0);
22304 SDValue Op2 = Cmp.getOperand(1);
22307 const ConstantSDNode* C = nullptr;
22308 bool needOppositeCond = (CC == X86::COND_E);
22309 bool checkAgainstTrue = false; // Is it a comparison against 1?
22311 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22313 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22315 else // Quit if all operands are not constants.
22318 if (C->getZExtValue() == 1) {
22319 needOppositeCond = !needOppositeCond;
22320 checkAgainstTrue = true;
22321 } else if (C->getZExtValue() != 0)
22322 // Quit if the constant is neither 0 or 1.
22325 bool truncatedToBoolWithAnd = false;
22326 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22327 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22328 SetCC.getOpcode() == ISD::TRUNCATE ||
22329 SetCC.getOpcode() == ISD::AND) {
22330 if (SetCC.getOpcode() == ISD::AND) {
22332 ConstantSDNode *CS;
22333 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22334 CS->getZExtValue() == 1)
22336 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22337 CS->getZExtValue() == 1)
22341 SetCC = SetCC.getOperand(OpIdx);
22342 truncatedToBoolWithAnd = true;
22344 SetCC = SetCC.getOperand(0);
22347 switch (SetCC.getOpcode()) {
22348 case X86ISD::SETCC_CARRY:
22349 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22350 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22351 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22352 // truncated to i1 using 'and'.
22353 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22355 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22356 "Invalid use of SETCC_CARRY!");
22358 case X86ISD::SETCC:
22359 // Set the condition code or opposite one if necessary.
22360 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22361 if (needOppositeCond)
22362 CC = X86::GetOppositeBranchCondition(CC);
22363 return SetCC.getOperand(1);
22364 case X86ISD::CMOV: {
22365 // Check whether false/true value has canonical one, i.e. 0 or 1.
22366 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22367 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22368 // Quit if true value is not a constant.
22371 // Quit if false value is not a constant.
22373 SDValue Op = SetCC.getOperand(0);
22374 // Skip 'zext' or 'trunc' node.
22375 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22376 Op.getOpcode() == ISD::TRUNCATE)
22377 Op = Op.getOperand(0);
22378 // A special case for rdrand/rdseed, where 0 is set if false cond is
22380 if ((Op.getOpcode() != X86ISD::RDRAND &&
22381 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22384 // Quit if false value is not the constant 0 or 1.
22385 bool FValIsFalse = true;
22386 if (FVal && FVal->getZExtValue() != 0) {
22387 if (FVal->getZExtValue() != 1)
22389 // If FVal is 1, opposite cond is needed.
22390 needOppositeCond = !needOppositeCond;
22391 FValIsFalse = false;
22393 // Quit if TVal is not the constant opposite of FVal.
22394 if (FValIsFalse && TVal->getZExtValue() != 1)
22396 if (!FValIsFalse && TVal->getZExtValue() != 0)
22398 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22399 if (needOppositeCond)
22400 CC = X86::GetOppositeBranchCondition(CC);
22401 return SetCC.getOperand(3);
22408 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22410 /// (X86or (X86setcc) (X86setcc))
22411 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22412 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22413 X86::CondCode &CC1, SDValue &Flags,
22415 if (Cond->getOpcode() == X86ISD::CMP) {
22416 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22417 if (!CondOp1C || !CondOp1C->isNullValue())
22420 Cond = Cond->getOperand(0);
22425 SDValue SetCC0, SetCC1;
22426 switch (Cond->getOpcode()) {
22427 default: return false;
22434 SetCC0 = Cond->getOperand(0);
22435 SetCC1 = Cond->getOperand(1);
22439 // Make sure we have SETCC nodes, using the same flags value.
22440 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22441 SetCC1.getOpcode() != X86ISD::SETCC ||
22442 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22445 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22446 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22447 Flags = SetCC0->getOperand(1);
22451 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22452 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22453 TargetLowering::DAGCombinerInfo &DCI,
22454 const X86Subtarget *Subtarget) {
22457 // If the flag operand isn't dead, don't touch this CMOV.
22458 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22461 SDValue FalseOp = N->getOperand(0);
22462 SDValue TrueOp = N->getOperand(1);
22463 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22464 SDValue Cond = N->getOperand(3);
22466 if (CC == X86::COND_E || CC == X86::COND_NE) {
22467 switch (Cond.getOpcode()) {
22471 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22472 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22473 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22479 Flags = checkBoolTestSetCCCombine(Cond, CC);
22480 if (Flags.getNode() &&
22481 // Extra check as FCMOV only supports a subset of X86 cond.
22482 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22483 SDValue Ops[] = { FalseOp, TrueOp,
22484 DAG.getConstant(CC, DL, MVT::i8), Flags };
22485 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22488 // If this is a select between two integer constants, try to do some
22489 // optimizations. Note that the operands are ordered the opposite of SELECT
22491 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22492 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22493 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22494 // larger than FalseC (the false value).
22495 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22496 CC = X86::GetOppositeBranchCondition(CC);
22497 std::swap(TrueC, FalseC);
22498 std::swap(TrueOp, FalseOp);
22501 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22502 // This is efficient for any integer data type (including i8/i16) and
22504 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22505 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22506 DAG.getConstant(CC, DL, MVT::i8), Cond);
22508 // Zero extend the condition if needed.
22509 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22511 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22512 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22513 DAG.getConstant(ShAmt, DL, MVT::i8));
22514 if (N->getNumValues() == 2) // Dead flag value?
22515 return DCI.CombineTo(N, Cond, SDValue());
22519 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22520 // for any integer data type, including i8/i16.
22521 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22522 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22523 DAG.getConstant(CC, DL, MVT::i8), Cond);
22525 // Zero extend the condition if needed.
22526 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22527 FalseC->getValueType(0), Cond);
22528 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22529 SDValue(FalseC, 0));
22531 if (N->getNumValues() == 2) // Dead flag value?
22532 return DCI.CombineTo(N, Cond, SDValue());
22536 // Optimize cases that will turn into an LEA instruction. This requires
22537 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22538 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22539 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22540 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22542 bool isFastMultiplier = false;
22544 switch ((unsigned char)Diff) {
22546 case 1: // result = add base, cond
22547 case 2: // result = lea base( , cond*2)
22548 case 3: // result = lea base(cond, cond*2)
22549 case 4: // result = lea base( , cond*4)
22550 case 5: // result = lea base(cond, cond*4)
22551 case 8: // result = lea base( , cond*8)
22552 case 9: // result = lea base(cond, cond*8)
22553 isFastMultiplier = true;
22558 if (isFastMultiplier) {
22559 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22560 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22561 DAG.getConstant(CC, DL, MVT::i8), Cond);
22562 // Zero extend the condition if needed.
22563 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22565 // Scale the condition by the difference.
22567 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22568 DAG.getConstant(Diff, DL, Cond.getValueType()));
22570 // Add the base if non-zero.
22571 if (FalseC->getAPIntValue() != 0)
22572 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22573 SDValue(FalseC, 0));
22574 if (N->getNumValues() == 2) // Dead flag value?
22575 return DCI.CombineTo(N, Cond, SDValue());
22582 // Handle these cases:
22583 // (select (x != c), e, c) -> select (x != c), e, x),
22584 // (select (x == c), c, e) -> select (x == c), x, e)
22585 // where the c is an integer constant, and the "select" is the combination
22586 // of CMOV and CMP.
22588 // The rationale for this change is that the conditional-move from a constant
22589 // needs two instructions, however, conditional-move from a register needs
22590 // only one instruction.
22592 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22593 // some instruction-combining opportunities. This opt needs to be
22594 // postponed as late as possible.
22596 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22597 // the DCI.xxxx conditions are provided to postpone the optimization as
22598 // late as possible.
22600 ConstantSDNode *CmpAgainst = nullptr;
22601 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22602 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22603 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22605 if (CC == X86::COND_NE &&
22606 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22607 CC = X86::GetOppositeBranchCondition(CC);
22608 std::swap(TrueOp, FalseOp);
22611 if (CC == X86::COND_E &&
22612 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22613 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22614 DAG.getConstant(CC, DL, MVT::i8), Cond };
22615 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22620 // Fold and/or of setcc's to double CMOV:
22621 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22622 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22624 // This combine lets us generate:
22625 // cmovcc1 (jcc1 if we don't have CMOV)
22631 // cmovne (jne if we don't have CMOV)
22632 // When we can't use the CMOV instruction, it might increase branch
22634 // When we can use CMOV, or when there is no mispredict, this improves
22635 // throughput and reduces register pressure.
22637 if (CC == X86::COND_NE) {
22639 X86::CondCode CC0, CC1;
22641 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22643 std::swap(FalseOp, TrueOp);
22644 CC0 = X86::GetOppositeBranchCondition(CC0);
22645 CC1 = X86::GetOppositeBranchCondition(CC1);
22648 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22650 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22651 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22652 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22653 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22661 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22662 const X86Subtarget *Subtarget) {
22663 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22665 default: return SDValue();
22666 // SSE/AVX/AVX2 blend intrinsics.
22667 case Intrinsic::x86_avx2_pblendvb:
22668 // Don't try to simplify this intrinsic if we don't have AVX2.
22669 if (!Subtarget->hasAVX2())
22672 case Intrinsic::x86_avx_blendv_pd_256:
22673 case Intrinsic::x86_avx_blendv_ps_256:
22674 // Don't try to simplify this intrinsic if we don't have AVX.
22675 if (!Subtarget->hasAVX())
22678 case Intrinsic::x86_sse41_blendvps:
22679 case Intrinsic::x86_sse41_blendvpd:
22680 case Intrinsic::x86_sse41_pblendvb: {
22681 SDValue Op0 = N->getOperand(1);
22682 SDValue Op1 = N->getOperand(2);
22683 SDValue Mask = N->getOperand(3);
22685 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22686 if (!Subtarget->hasSSE41())
22689 // fold (blend A, A, Mask) -> A
22692 // fold (blend A, B, allZeros) -> A
22693 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22695 // fold (blend A, B, allOnes) -> B
22696 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22699 // Simplify the case where the mask is a constant i32 value.
22700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22701 if (C->isNullValue())
22703 if (C->isAllOnesValue())
22710 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22711 case Intrinsic::x86_sse2_psrai_w:
22712 case Intrinsic::x86_sse2_psrai_d:
22713 case Intrinsic::x86_avx2_psrai_w:
22714 case Intrinsic::x86_avx2_psrai_d:
22715 case Intrinsic::x86_sse2_psra_w:
22716 case Intrinsic::x86_sse2_psra_d:
22717 case Intrinsic::x86_avx2_psra_w:
22718 case Intrinsic::x86_avx2_psra_d: {
22719 SDValue Op0 = N->getOperand(1);
22720 SDValue Op1 = N->getOperand(2);
22721 EVT VT = Op0.getValueType();
22722 assert(VT.isVector() && "Expected a vector type!");
22724 if (isa<BuildVectorSDNode>(Op1))
22725 Op1 = Op1.getOperand(0);
22727 if (!isa<ConstantSDNode>(Op1))
22730 EVT SVT = VT.getVectorElementType();
22731 unsigned SVTBits = SVT.getSizeInBits();
22733 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22734 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22735 uint64_t ShAmt = C.getZExtValue();
22737 // Don't try to convert this shift into a ISD::SRA if the shift
22738 // count is bigger than or equal to the element size.
22739 if (ShAmt >= SVTBits)
22742 // Trivial case: if the shift count is zero, then fold this
22743 // into the first operand.
22747 // Replace this packed shift intrinsic with a target independent
22750 SDValue Splat = DAG.getConstant(C, DL, VT);
22751 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22756 /// PerformMulCombine - Optimize a single multiply with constant into two
22757 /// in order to implement it with two cheaper instructions, e.g.
22758 /// LEA + SHL, LEA + LEA.
22759 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22760 TargetLowering::DAGCombinerInfo &DCI) {
22761 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22764 EVT VT = N->getValueType(0);
22765 if (VT != MVT::i64 && VT != MVT::i32)
22768 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22771 uint64_t MulAmt = C->getZExtValue();
22772 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22775 uint64_t MulAmt1 = 0;
22776 uint64_t MulAmt2 = 0;
22777 if ((MulAmt % 9) == 0) {
22779 MulAmt2 = MulAmt / 9;
22780 } else if ((MulAmt % 5) == 0) {
22782 MulAmt2 = MulAmt / 5;
22783 } else if ((MulAmt % 3) == 0) {
22785 MulAmt2 = MulAmt / 3;
22788 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22791 if (isPowerOf2_64(MulAmt2) &&
22792 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22793 // If second multiplifer is pow2, issue it first. We want the multiply by
22794 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22796 std::swap(MulAmt1, MulAmt2);
22799 if (isPowerOf2_64(MulAmt1))
22800 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22801 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22803 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22804 DAG.getConstant(MulAmt1, DL, VT));
22806 if (isPowerOf2_64(MulAmt2))
22807 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22808 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22810 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22811 DAG.getConstant(MulAmt2, DL, VT));
22813 // Do not add new nodes to DAG combiner worklist.
22814 DCI.CombineTo(N, NewMul, false);
22819 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22820 SDValue N0 = N->getOperand(0);
22821 SDValue N1 = N->getOperand(1);
22822 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22823 EVT VT = N0.getValueType();
22825 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22826 // since the result of setcc_c is all zero's or all ones.
22827 if (VT.isInteger() && !VT.isVector() &&
22828 N1C && N0.getOpcode() == ISD::AND &&
22829 N0.getOperand(1).getOpcode() == ISD::Constant) {
22830 SDValue N00 = N0.getOperand(0);
22831 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22832 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22833 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22834 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22835 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22836 APInt ShAmt = N1C->getAPIntValue();
22837 Mask = Mask.shl(ShAmt);
22840 return DAG.getNode(ISD::AND, DL, VT,
22841 N00, DAG.getConstant(Mask, DL, VT));
22846 // Hardware support for vector shifts is sparse which makes us scalarize the
22847 // vector operations in many cases. Also, on sandybridge ADD is faster than
22849 // (shl V, 1) -> add V,V
22850 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22851 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22852 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22853 // We shift all of the values by one. In many cases we do not have
22854 // hardware support for this operation. This is better expressed as an ADD
22856 if (N1SplatC->getZExtValue() == 1)
22857 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22863 /// \brief Returns a vector of 0s if the node in input is a vector logical
22864 /// shift by a constant amount which is known to be bigger than or equal
22865 /// to the vector element size in bits.
22866 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22867 const X86Subtarget *Subtarget) {
22868 EVT VT = N->getValueType(0);
22870 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22871 (!Subtarget->hasInt256() ||
22872 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22875 SDValue Amt = N->getOperand(1);
22877 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22878 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22879 APInt ShiftAmt = AmtSplat->getAPIntValue();
22880 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22882 // SSE2/AVX2 logical shifts always return a vector of 0s
22883 // if the shift amount is bigger than or equal to
22884 // the element size. The constant shift amount will be
22885 // encoded as a 8-bit immediate.
22886 if (ShiftAmt.trunc(8).uge(MaxAmount))
22887 return getZeroVector(VT, Subtarget, DAG, DL);
22893 /// PerformShiftCombine - Combine shifts.
22894 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22895 TargetLowering::DAGCombinerInfo &DCI,
22896 const X86Subtarget *Subtarget) {
22897 if (N->getOpcode() == ISD::SHL) {
22898 SDValue V = PerformSHLCombine(N, DAG);
22899 if (V.getNode()) return V;
22902 if (N->getOpcode() != ISD::SRA) {
22903 // Try to fold this logical shift into a zero vector.
22904 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22905 if (V.getNode()) return V;
22911 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22912 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22913 // and friends. Likewise for OR -> CMPNEQSS.
22914 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22915 TargetLowering::DAGCombinerInfo &DCI,
22916 const X86Subtarget *Subtarget) {
22919 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22920 // we're requiring SSE2 for both.
22921 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22922 SDValue N0 = N->getOperand(0);
22923 SDValue N1 = N->getOperand(1);
22924 SDValue CMP0 = N0->getOperand(1);
22925 SDValue CMP1 = N1->getOperand(1);
22928 // The SETCCs should both refer to the same CMP.
22929 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22932 SDValue CMP00 = CMP0->getOperand(0);
22933 SDValue CMP01 = CMP0->getOperand(1);
22934 EVT VT = CMP00.getValueType();
22936 if (VT == MVT::f32 || VT == MVT::f64) {
22937 bool ExpectingFlags = false;
22938 // Check for any users that want flags:
22939 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22940 !ExpectingFlags && UI != UE; ++UI)
22941 switch (UI->getOpcode()) {
22946 ExpectingFlags = true;
22948 case ISD::CopyToReg:
22949 case ISD::SIGN_EXTEND:
22950 case ISD::ZERO_EXTEND:
22951 case ISD::ANY_EXTEND:
22955 if (!ExpectingFlags) {
22956 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22957 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22959 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22960 X86::CondCode tmp = cc0;
22965 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22966 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22967 // FIXME: need symbolic constants for these magic numbers.
22968 // See X86ATTInstPrinter.cpp:printSSECC().
22969 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22970 if (Subtarget->hasAVX512()) {
22971 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22973 DAG.getConstant(x86cc, DL, MVT::i8));
22974 if (N->getValueType(0) != MVT::i1)
22975 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22979 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22980 CMP00.getValueType(), CMP00, CMP01,
22981 DAG.getConstant(x86cc, DL,
22984 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22985 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22987 if (is64BitFP && !Subtarget->is64Bit()) {
22988 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22989 // 64-bit integer, since that's not a legal type. Since
22990 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22991 // bits, but can do this little dance to extract the lowest 32 bits
22992 // and work with those going forward.
22993 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22995 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
22996 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22997 Vector32, DAG.getIntPtrConstant(0, DL));
23001 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23002 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23003 DAG.getConstant(1, DL, IntVT));
23004 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23006 return OneBitOfTruth;
23014 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23015 /// so it can be folded inside ANDNP.
23016 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23017 EVT VT = N->getValueType(0);
23019 // Match direct AllOnes for 128 and 256-bit vectors
23020 if (ISD::isBuildVectorAllOnes(N))
23023 // Look through a bit convert.
23024 if (N->getOpcode() == ISD::BITCAST)
23025 N = N->getOperand(0).getNode();
23027 // Sometimes the operand may come from a insert_subvector building a 256-bit
23029 if (VT.is256BitVector() &&
23030 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23031 SDValue V1 = N->getOperand(0);
23032 SDValue V2 = N->getOperand(1);
23034 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23035 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23036 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23037 ISD::isBuildVectorAllOnes(V2.getNode()))
23044 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23045 // register. In most cases we actually compare or select YMM-sized registers
23046 // and mixing the two types creates horrible code. This method optimizes
23047 // some of the transition sequences.
23048 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23049 TargetLowering::DAGCombinerInfo &DCI,
23050 const X86Subtarget *Subtarget) {
23051 EVT VT = N->getValueType(0);
23052 if (!VT.is256BitVector())
23055 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23056 N->getOpcode() == ISD::ZERO_EXTEND ||
23057 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23059 SDValue Narrow = N->getOperand(0);
23060 EVT NarrowVT = Narrow->getValueType(0);
23061 if (!NarrowVT.is128BitVector())
23064 if (Narrow->getOpcode() != ISD::XOR &&
23065 Narrow->getOpcode() != ISD::AND &&
23066 Narrow->getOpcode() != ISD::OR)
23069 SDValue N0 = Narrow->getOperand(0);
23070 SDValue N1 = Narrow->getOperand(1);
23073 // The Left side has to be a trunc.
23074 if (N0.getOpcode() != ISD::TRUNCATE)
23077 // The type of the truncated inputs.
23078 EVT WideVT = N0->getOperand(0)->getValueType(0);
23082 // The right side has to be a 'trunc' or a constant vector.
23083 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23084 ConstantSDNode *RHSConstSplat = nullptr;
23085 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23086 RHSConstSplat = RHSBV->getConstantSplatNode();
23087 if (!RHSTrunc && !RHSConstSplat)
23090 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23092 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23095 // Set N0 and N1 to hold the inputs to the new wide operation.
23096 N0 = N0->getOperand(0);
23097 if (RHSConstSplat) {
23098 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23099 SDValue(RHSConstSplat, 0));
23100 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23101 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23102 } else if (RHSTrunc) {
23103 N1 = N1->getOperand(0);
23106 // Generate the wide operation.
23107 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23108 unsigned Opcode = N->getOpcode();
23110 case ISD::ANY_EXTEND:
23112 case ISD::ZERO_EXTEND: {
23113 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23114 APInt Mask = APInt::getAllOnesValue(InBits);
23115 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23116 return DAG.getNode(ISD::AND, DL, VT,
23117 Op, DAG.getConstant(Mask, DL, VT));
23119 case ISD::SIGN_EXTEND:
23120 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23121 Op, DAG.getValueType(NarrowVT));
23123 llvm_unreachable("Unexpected opcode");
23127 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23128 TargetLowering::DAGCombinerInfo &DCI,
23129 const X86Subtarget *Subtarget) {
23130 SDValue N0 = N->getOperand(0);
23131 SDValue N1 = N->getOperand(1);
23134 // A vector zext_in_reg may be represented as a shuffle,
23135 // feeding into a bitcast (this represents anyext) feeding into
23136 // an and with a mask.
23137 // We'd like to try to combine that into a shuffle with zero
23138 // plus a bitcast, removing the and.
23139 if (N0.getOpcode() != ISD::BITCAST ||
23140 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23143 // The other side of the AND should be a splat of 2^C, where C
23144 // is the number of bits in the source type.
23145 if (N1.getOpcode() == ISD::BITCAST)
23146 N1 = N1.getOperand(0);
23147 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23149 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23151 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23152 EVT SrcType = Shuffle->getValueType(0);
23154 // We expect a single-source shuffle
23155 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23158 unsigned SrcSize = SrcType.getScalarSizeInBits();
23160 APInt SplatValue, SplatUndef;
23161 unsigned SplatBitSize;
23163 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23164 SplatBitSize, HasAnyUndefs))
23167 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23168 // Make sure the splat matches the mask we expect
23169 if (SplatBitSize > ResSize ||
23170 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23173 // Make sure the input and output size make sense
23174 if (SrcSize >= ResSize || ResSize % SrcSize)
23177 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23178 // The number of u's between each two values depends on the ratio between
23179 // the source and dest type.
23180 unsigned ZextRatio = ResSize / SrcSize;
23181 bool IsZext = true;
23182 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23183 if (i % ZextRatio) {
23184 if (Shuffle->getMaskElt(i) > 0) {
23190 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23191 // Expected element number
23201 // Ok, perform the transformation - replace the shuffle with
23202 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23203 // (instead of undef) where the k elements come from the zero vector.
23204 SmallVector<int, 8> Mask;
23205 unsigned NumElems = SrcType.getVectorNumElements();
23206 for (unsigned i = 0; i < NumElems; ++i)
23208 Mask.push_back(NumElems);
23210 Mask.push_back(i / ZextRatio);
23212 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23213 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23214 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23217 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23218 TargetLowering::DAGCombinerInfo &DCI,
23219 const X86Subtarget *Subtarget) {
23220 if (DCI.isBeforeLegalizeOps())
23223 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23226 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23229 EVT VT = N->getValueType(0);
23230 SDValue N0 = N->getOperand(0);
23231 SDValue N1 = N->getOperand(1);
23234 // Create BEXTR instructions
23235 // BEXTR is ((X >> imm) & (2**size-1))
23236 if (VT == MVT::i32 || VT == MVT::i64) {
23237 // Check for BEXTR.
23238 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23239 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23240 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23241 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23242 if (MaskNode && ShiftNode) {
23243 uint64_t Mask = MaskNode->getZExtValue();
23244 uint64_t Shift = ShiftNode->getZExtValue();
23245 if (isMask_64(Mask)) {
23246 uint64_t MaskSize = countPopulation(Mask);
23247 if (Shift + MaskSize <= VT.getSizeInBits())
23248 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23249 DAG.getConstant(Shift | (MaskSize << 8), DL,
23258 // Want to form ANDNP nodes:
23259 // 1) In the hopes of then easily combining them with OR and AND nodes
23260 // to form PBLEND/PSIGN.
23261 // 2) To match ANDN packed intrinsics
23262 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23265 // Check LHS for vnot
23266 if (N0.getOpcode() == ISD::XOR &&
23267 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23268 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23269 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23271 // Check RHS for vnot
23272 if (N1.getOpcode() == ISD::XOR &&
23273 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23274 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23275 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23280 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23281 TargetLowering::DAGCombinerInfo &DCI,
23282 const X86Subtarget *Subtarget) {
23283 if (DCI.isBeforeLegalizeOps())
23286 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23290 SDValue N0 = N->getOperand(0);
23291 SDValue N1 = N->getOperand(1);
23292 EVT VT = N->getValueType(0);
23294 // look for psign/blend
23295 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23296 if (!Subtarget->hasSSSE3() ||
23297 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23300 // Canonicalize pandn to RHS
23301 if (N0.getOpcode() == X86ISD::ANDNP)
23303 // or (and (m, y), (pandn m, x))
23304 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23305 SDValue Mask = N1.getOperand(0);
23306 SDValue X = N1.getOperand(1);
23308 if (N0.getOperand(0) == Mask)
23309 Y = N0.getOperand(1);
23310 if (N0.getOperand(1) == Mask)
23311 Y = N0.getOperand(0);
23313 // Check to see if the mask appeared in both the AND and ANDNP and
23317 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23318 // Look through mask bitcast.
23319 if (Mask.getOpcode() == ISD::BITCAST)
23320 Mask = Mask.getOperand(0);
23321 if (X.getOpcode() == ISD::BITCAST)
23322 X = X.getOperand(0);
23323 if (Y.getOpcode() == ISD::BITCAST)
23324 Y = Y.getOperand(0);
23326 EVT MaskVT = Mask.getValueType();
23328 // Validate that the Mask operand is a vector sra node.
23329 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23330 // there is no psrai.b
23331 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23332 unsigned SraAmt = ~0;
23333 if (Mask.getOpcode() == ISD::SRA) {
23334 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23335 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23336 SraAmt = AmtConst->getZExtValue();
23337 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23338 SDValue SraC = Mask.getOperand(1);
23339 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23341 if ((SraAmt + 1) != EltBits)
23346 // Now we know we at least have a plendvb with the mask val. See if
23347 // we can form a psignb/w/d.
23348 // psign = x.type == y.type == mask.type && y = sub(0, x);
23349 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23350 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23351 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23352 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23353 "Unsupported VT for PSIGN");
23354 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23355 return DAG.getBitcast(VT, Mask);
23357 // PBLENDVB only available on SSE 4.1
23358 if (!Subtarget->hasSSE41())
23361 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23363 X = DAG.getBitcast(BlendVT, X);
23364 Y = DAG.getBitcast(BlendVT, Y);
23365 Mask = DAG.getBitcast(BlendVT, Mask);
23366 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23367 return DAG.getBitcast(VT, Mask);
23371 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23374 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23375 MachineFunction &MF = DAG.getMachineFunction();
23377 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23379 // SHLD/SHRD instructions have lower register pressure, but on some
23380 // platforms they have higher latency than the equivalent
23381 // series of shifts/or that would otherwise be generated.
23382 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23383 // have higher latencies and we are not optimizing for size.
23384 if (!OptForSize && Subtarget->isSHLDSlow())
23387 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23389 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23391 if (!N0.hasOneUse() || !N1.hasOneUse())
23394 SDValue ShAmt0 = N0.getOperand(1);
23395 if (ShAmt0.getValueType() != MVT::i8)
23397 SDValue ShAmt1 = N1.getOperand(1);
23398 if (ShAmt1.getValueType() != MVT::i8)
23400 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23401 ShAmt0 = ShAmt0.getOperand(0);
23402 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23403 ShAmt1 = ShAmt1.getOperand(0);
23406 unsigned Opc = X86ISD::SHLD;
23407 SDValue Op0 = N0.getOperand(0);
23408 SDValue Op1 = N1.getOperand(0);
23409 if (ShAmt0.getOpcode() == ISD::SUB) {
23410 Opc = X86ISD::SHRD;
23411 std::swap(Op0, Op1);
23412 std::swap(ShAmt0, ShAmt1);
23415 unsigned Bits = VT.getSizeInBits();
23416 if (ShAmt1.getOpcode() == ISD::SUB) {
23417 SDValue Sum = ShAmt1.getOperand(0);
23418 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23419 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23420 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23421 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23422 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23423 return DAG.getNode(Opc, DL, VT,
23425 DAG.getNode(ISD::TRUNCATE, DL,
23428 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23429 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23431 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23432 return DAG.getNode(Opc, DL, VT,
23433 N0.getOperand(0), N1.getOperand(0),
23434 DAG.getNode(ISD::TRUNCATE, DL,
23441 // Generate NEG and CMOV for integer abs.
23442 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23443 EVT VT = N->getValueType(0);
23445 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23446 // 8-bit integer abs to NEG and CMOV.
23447 if (VT.isInteger() && VT.getSizeInBits() == 8)
23450 SDValue N0 = N->getOperand(0);
23451 SDValue N1 = N->getOperand(1);
23454 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23455 // and change it to SUB and CMOV.
23456 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23457 N0.getOpcode() == ISD::ADD &&
23458 N0.getOperand(1) == N1 &&
23459 N1.getOpcode() == ISD::SRA &&
23460 N1.getOperand(0) == N0.getOperand(0))
23461 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23462 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23463 // Generate SUB & CMOV.
23464 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23465 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23467 SDValue Ops[] = { N0.getOperand(0), Neg,
23468 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23469 SDValue(Neg.getNode(), 1) };
23470 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23475 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23476 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23477 TargetLowering::DAGCombinerInfo &DCI,
23478 const X86Subtarget *Subtarget) {
23479 if (DCI.isBeforeLegalizeOps())
23482 if (Subtarget->hasCMov()) {
23483 SDValue RV = performIntegerAbsCombine(N, DAG);
23491 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23492 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23493 TargetLowering::DAGCombinerInfo &DCI,
23494 const X86Subtarget *Subtarget) {
23495 LoadSDNode *Ld = cast<LoadSDNode>(N);
23496 EVT RegVT = Ld->getValueType(0);
23497 EVT MemVT = Ld->getMemoryVT();
23499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23501 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23502 // into two 16-byte operations.
23503 ISD::LoadExtType Ext = Ld->getExtensionType();
23504 unsigned Alignment = Ld->getAlignment();
23505 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23506 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23507 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23508 unsigned NumElems = RegVT.getVectorNumElements();
23512 SDValue Ptr = Ld->getBasePtr();
23513 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23515 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23517 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23518 Ld->getPointerInfo(), Ld->isVolatile(),
23519 Ld->isNonTemporal(), Ld->isInvariant(),
23521 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23522 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23523 Ld->getPointerInfo(), Ld->isVolatile(),
23524 Ld->isNonTemporal(), Ld->isInvariant(),
23525 std::min(16U, Alignment));
23526 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23528 Load2.getValue(1));
23530 SDValue NewVec = DAG.getUNDEF(RegVT);
23531 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23532 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23533 return DCI.CombineTo(N, NewVec, TF, true);
23539 /// PerformMLOADCombine - Resolve extending loads
23540 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23541 TargetLowering::DAGCombinerInfo &DCI,
23542 const X86Subtarget *Subtarget) {
23543 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23544 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23547 EVT VT = Mld->getValueType(0);
23548 unsigned NumElems = VT.getVectorNumElements();
23549 EVT LdVT = Mld->getMemoryVT();
23552 assert(LdVT != VT && "Cannot extend to the same type");
23553 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23554 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23555 // From, To sizes and ElemCount must be pow of two
23556 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23557 "Unexpected size for extending masked load");
23559 unsigned SizeRatio = ToSz / FromSz;
23560 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23562 // Create a type on which we perform the shuffle
23563 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23564 LdVT.getScalarType(), NumElems*SizeRatio);
23565 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23567 // Convert Src0 value
23568 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23569 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23570 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23571 for (unsigned i = 0; i != NumElems; ++i)
23572 ShuffleVec[i] = i * SizeRatio;
23574 // Can't shuffle using an illegal type.
23575 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23576 && "WideVecVT should be legal");
23577 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23578 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23580 // Prepare the new mask
23582 SDValue Mask = Mld->getMask();
23583 if (Mask.getValueType() == VT) {
23584 // Mask and original value have the same type
23585 NewMask = DAG.getBitcast(WideVecVT, Mask);
23586 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23587 for (unsigned i = 0; i != NumElems; ++i)
23588 ShuffleVec[i] = i * SizeRatio;
23589 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23590 ShuffleVec[i] = NumElems*SizeRatio;
23591 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23592 DAG.getConstant(0, dl, WideVecVT),
23596 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23597 unsigned WidenNumElts = NumElems*SizeRatio;
23598 unsigned MaskNumElts = VT.getVectorNumElements();
23599 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23602 unsigned NumConcat = WidenNumElts / MaskNumElts;
23603 SmallVector<SDValue, 16> Ops(NumConcat);
23604 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23606 for (unsigned i = 1; i != NumConcat; ++i)
23609 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23612 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23613 Mld->getBasePtr(), NewMask, WideSrc0,
23614 Mld->getMemoryVT(), Mld->getMemOperand(),
23616 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23617 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23620 /// PerformMSTORECombine - Resolve truncating stores
23621 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23622 const X86Subtarget *Subtarget) {
23623 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23624 if (!Mst->isTruncatingStore())
23627 EVT VT = Mst->getValue().getValueType();
23628 unsigned NumElems = VT.getVectorNumElements();
23629 EVT StVT = Mst->getMemoryVT();
23632 assert(StVT != VT && "Cannot truncate to the same type");
23633 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23634 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23636 // From, To sizes and ElemCount must be pow of two
23637 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23638 "Unexpected size for truncating masked store");
23639 // We are going to use the original vector elt for storing.
23640 // Accumulated smaller vector elements must be a multiple of the store size.
23641 assert (((NumElems * FromSz) % ToSz) == 0 &&
23642 "Unexpected ratio for truncating masked store");
23644 unsigned SizeRatio = FromSz / ToSz;
23645 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23647 // Create a type on which we perform the shuffle
23648 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23649 StVT.getScalarType(), NumElems*SizeRatio);
23651 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23653 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23654 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23655 for (unsigned i = 0; i != NumElems; ++i)
23656 ShuffleVec[i] = i * SizeRatio;
23658 // Can't shuffle using an illegal type.
23659 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23660 && "WideVecVT should be legal");
23662 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23663 DAG.getUNDEF(WideVecVT),
23667 SDValue Mask = Mst->getMask();
23668 if (Mask.getValueType() == VT) {
23669 // Mask and original value have the same type
23670 NewMask = DAG.getBitcast(WideVecVT, Mask);
23671 for (unsigned i = 0; i != NumElems; ++i)
23672 ShuffleVec[i] = i * SizeRatio;
23673 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23674 ShuffleVec[i] = NumElems*SizeRatio;
23675 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23676 DAG.getConstant(0, dl, WideVecVT),
23680 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23681 unsigned WidenNumElts = NumElems*SizeRatio;
23682 unsigned MaskNumElts = VT.getVectorNumElements();
23683 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23686 unsigned NumConcat = WidenNumElts / MaskNumElts;
23687 SmallVector<SDValue, 16> Ops(NumConcat);
23688 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23690 for (unsigned i = 1; i != NumConcat; ++i)
23693 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23696 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23697 NewMask, StVT, Mst->getMemOperand(), false);
23699 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23700 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23701 const X86Subtarget *Subtarget) {
23702 StoreSDNode *St = cast<StoreSDNode>(N);
23703 EVT VT = St->getValue().getValueType();
23704 EVT StVT = St->getMemoryVT();
23706 SDValue StoredVal = St->getOperand(1);
23707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23709 // If we are saving a concatenation of two XMM registers and 32-byte stores
23710 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23711 unsigned Alignment = St->getAlignment();
23712 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23713 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23714 StVT == VT && !IsAligned) {
23715 unsigned NumElems = VT.getVectorNumElements();
23719 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23720 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23722 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23723 SDValue Ptr0 = St->getBasePtr();
23724 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23726 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23727 St->getPointerInfo(), St->isVolatile(),
23728 St->isNonTemporal(), Alignment);
23729 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23730 St->getPointerInfo(), St->isVolatile(),
23731 St->isNonTemporal(),
23732 std::min(16U, Alignment));
23733 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23736 // Optimize trunc store (of multiple scalars) to shuffle and store.
23737 // First, pack all of the elements in one place. Next, store to memory
23738 // in fewer chunks.
23739 if (St->isTruncatingStore() && VT.isVector()) {
23740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23741 unsigned NumElems = VT.getVectorNumElements();
23742 assert(StVT != VT && "Cannot truncate to the same type");
23743 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23744 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23746 // From, To sizes and ElemCount must be pow of two
23747 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23748 // We are going to use the original vector elt for storing.
23749 // Accumulated smaller vector elements must be a multiple of the store size.
23750 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23752 unsigned SizeRatio = FromSz / ToSz;
23754 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23756 // Create a type on which we perform the shuffle
23757 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23758 StVT.getScalarType(), NumElems*SizeRatio);
23760 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23762 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
23763 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23764 for (unsigned i = 0; i != NumElems; ++i)
23765 ShuffleVec[i] = i * SizeRatio;
23767 // Can't shuffle using an illegal type.
23768 if (!TLI.isTypeLegal(WideVecVT))
23771 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23772 DAG.getUNDEF(WideVecVT),
23774 // At this point all of the data is stored at the bottom of the
23775 // register. We now need to save it to mem.
23777 // Find the largest store unit
23778 MVT StoreType = MVT::i8;
23779 for (MVT Tp : MVT::integer_valuetypes()) {
23780 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23784 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23785 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23786 (64 <= NumElems * ToSz))
23787 StoreType = MVT::f64;
23789 // Bitcast the original vector into a vector of store-size units
23790 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23791 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23792 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23793 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
23794 SmallVector<SDValue, 8> Chains;
23795 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23796 TLI.getPointerTy());
23797 SDValue Ptr = St->getBasePtr();
23799 // Perform one or more big stores into memory.
23800 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23801 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23802 StoreType, ShuffWide,
23803 DAG.getIntPtrConstant(i, dl));
23804 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23805 St->getPointerInfo(), St->isVolatile(),
23806 St->isNonTemporal(), St->getAlignment());
23807 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23808 Chains.push_back(Ch);
23811 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23814 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23815 // the FP state in cases where an emms may be missing.
23816 // A preferable solution to the general problem is to figure out the right
23817 // places to insert EMMS. This qualifies as a quick hack.
23819 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23820 if (VT.getSizeInBits() != 64)
23823 const Function *F = DAG.getMachineFunction().getFunction();
23824 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23826 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23827 if ((VT.isVector() ||
23828 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23829 isa<LoadSDNode>(St->getValue()) &&
23830 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23831 St->getChain().hasOneUse() && !St->isVolatile()) {
23832 SDNode* LdVal = St->getValue().getNode();
23833 LoadSDNode *Ld = nullptr;
23834 int TokenFactorIndex = -1;
23835 SmallVector<SDValue, 8> Ops;
23836 SDNode* ChainVal = St->getChain().getNode();
23837 // Must be a store of a load. We currently handle two cases: the load
23838 // is a direct child, and it's under an intervening TokenFactor. It is
23839 // possible to dig deeper under nested TokenFactors.
23840 if (ChainVal == LdVal)
23841 Ld = cast<LoadSDNode>(St->getChain());
23842 else if (St->getValue().hasOneUse() &&
23843 ChainVal->getOpcode() == ISD::TokenFactor) {
23844 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23845 if (ChainVal->getOperand(i).getNode() == LdVal) {
23846 TokenFactorIndex = i;
23847 Ld = cast<LoadSDNode>(St->getValue());
23849 Ops.push_back(ChainVal->getOperand(i));
23853 if (!Ld || !ISD::isNormalLoad(Ld))
23856 // If this is not the MMX case, i.e. we are just turning i64 load/store
23857 // into f64 load/store, avoid the transformation if there are multiple
23858 // uses of the loaded value.
23859 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23864 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23865 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23867 if (Subtarget->is64Bit() || F64IsLegal) {
23868 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23869 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23870 Ld->getPointerInfo(), Ld->isVolatile(),
23871 Ld->isNonTemporal(), Ld->isInvariant(),
23872 Ld->getAlignment());
23873 SDValue NewChain = NewLd.getValue(1);
23874 if (TokenFactorIndex != -1) {
23875 Ops.push_back(NewChain);
23876 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23878 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23879 St->getPointerInfo(),
23880 St->isVolatile(), St->isNonTemporal(),
23881 St->getAlignment());
23884 // Otherwise, lower to two pairs of 32-bit loads / stores.
23885 SDValue LoAddr = Ld->getBasePtr();
23886 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23887 DAG.getConstant(4, LdDL, MVT::i32));
23889 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23890 Ld->getPointerInfo(),
23891 Ld->isVolatile(), Ld->isNonTemporal(),
23892 Ld->isInvariant(), Ld->getAlignment());
23893 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23894 Ld->getPointerInfo().getWithOffset(4),
23895 Ld->isVolatile(), Ld->isNonTemporal(),
23897 MinAlign(Ld->getAlignment(), 4));
23899 SDValue NewChain = LoLd.getValue(1);
23900 if (TokenFactorIndex != -1) {
23901 Ops.push_back(LoLd);
23902 Ops.push_back(HiLd);
23903 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23906 LoAddr = St->getBasePtr();
23907 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23908 DAG.getConstant(4, StDL, MVT::i32));
23910 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23911 St->getPointerInfo(),
23912 St->isVolatile(), St->isNonTemporal(),
23913 St->getAlignment());
23914 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23915 St->getPointerInfo().getWithOffset(4),
23917 St->isNonTemporal(),
23918 MinAlign(St->getAlignment(), 4));
23919 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23922 // This is similar to the above case, but here we handle a scalar 64-bit
23923 // integer store that is extracted from a vector on a 32-bit target.
23924 // If we have SSE2, then we can treat it like a floating-point double
23925 // to get past legalization. The execution dependencies fixup pass will
23926 // choose the optimal machine instruction for the store if this really is
23927 // an integer or v2f32 rather than an f64.
23928 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23929 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23930 SDValue OldExtract = St->getOperand(1);
23931 SDValue ExtOp0 = OldExtract.getOperand(0);
23932 unsigned VecSize = ExtOp0.getValueSizeInBits();
23933 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23934 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
23935 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23936 BitCast, OldExtract.getOperand(1));
23937 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23938 St->getPointerInfo(), St->isVolatile(),
23939 St->isNonTemporal(), St->getAlignment());
23945 /// Return 'true' if this vector operation is "horizontal"
23946 /// and return the operands for the horizontal operation in LHS and RHS. A
23947 /// horizontal operation performs the binary operation on successive elements
23948 /// of its first operand, then on successive elements of its second operand,
23949 /// returning the resulting values in a vector. For example, if
23950 /// A = < float a0, float a1, float a2, float a3 >
23952 /// B = < float b0, float b1, float b2, float b3 >
23953 /// then the result of doing a horizontal operation on A and B is
23954 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23955 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23956 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23957 /// set to A, RHS to B, and the routine returns 'true'.
23958 /// Note that the binary operation should have the property that if one of the
23959 /// operands is UNDEF then the result is UNDEF.
23960 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23961 // Look for the following pattern: if
23962 // A = < float a0, float a1, float a2, float a3 >
23963 // B = < float b0, float b1, float b2, float b3 >
23965 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23966 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23967 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23968 // which is A horizontal-op B.
23970 // At least one of the operands should be a vector shuffle.
23971 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23972 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23975 MVT VT = LHS.getSimpleValueType();
23977 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23978 "Unsupported vector type for horizontal add/sub");
23980 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23981 // operate independently on 128-bit lanes.
23982 unsigned NumElts = VT.getVectorNumElements();
23983 unsigned NumLanes = VT.getSizeInBits()/128;
23984 unsigned NumLaneElts = NumElts / NumLanes;
23985 assert((NumLaneElts % 2 == 0) &&
23986 "Vector type should have an even number of elements in each lane");
23987 unsigned HalfLaneElts = NumLaneElts/2;
23989 // View LHS in the form
23990 // LHS = VECTOR_SHUFFLE A, B, LMask
23991 // If LHS is not a shuffle then pretend it is the shuffle
23992 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23993 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23996 SmallVector<int, 16> LMask(NumElts);
23997 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23998 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23999 A = LHS.getOperand(0);
24000 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24001 B = LHS.getOperand(1);
24002 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24003 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24005 if (LHS.getOpcode() != ISD::UNDEF)
24007 for (unsigned i = 0; i != NumElts; ++i)
24011 // Likewise, view RHS in the form
24012 // RHS = VECTOR_SHUFFLE C, D, RMask
24014 SmallVector<int, 16> RMask(NumElts);
24015 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24016 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24017 C = RHS.getOperand(0);
24018 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24019 D = RHS.getOperand(1);
24020 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24021 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24023 if (RHS.getOpcode() != ISD::UNDEF)
24025 for (unsigned i = 0; i != NumElts; ++i)
24029 // Check that the shuffles are both shuffling the same vectors.
24030 if (!(A == C && B == D) && !(A == D && B == C))
24033 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24034 if (!A.getNode() && !B.getNode())
24037 // If A and B occur in reverse order in RHS, then "swap" them (which means
24038 // rewriting the mask).
24040 ShuffleVectorSDNode::commuteMask(RMask);
24042 // At this point LHS and RHS are equivalent to
24043 // LHS = VECTOR_SHUFFLE A, B, LMask
24044 // RHS = VECTOR_SHUFFLE A, B, RMask
24045 // Check that the masks correspond to performing a horizontal operation.
24046 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24047 for (unsigned i = 0; i != NumLaneElts; ++i) {
24048 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24050 // Ignore any UNDEF components.
24051 if (LIdx < 0 || RIdx < 0 ||
24052 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24053 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24056 // Check that successive elements are being operated on. If not, this is
24057 // not a horizontal operation.
24058 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24059 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24060 if (!(LIdx == Index && RIdx == Index + 1) &&
24061 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24066 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24067 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24071 /// Do target-specific dag combines on floating point adds.
24072 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24073 const X86Subtarget *Subtarget) {
24074 EVT VT = N->getValueType(0);
24075 SDValue LHS = N->getOperand(0);
24076 SDValue RHS = N->getOperand(1);
24078 // Try to synthesize horizontal adds from adds of shuffles.
24079 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24080 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24081 isHorizontalBinOp(LHS, RHS, true))
24082 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24086 /// Do target-specific dag combines on floating point subs.
24087 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24088 const X86Subtarget *Subtarget) {
24089 EVT VT = N->getValueType(0);
24090 SDValue LHS = N->getOperand(0);
24091 SDValue RHS = N->getOperand(1);
24093 // Try to synthesize horizontal subs from subs of shuffles.
24094 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24095 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24096 isHorizontalBinOp(LHS, RHS, false))
24097 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24101 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24102 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24103 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24105 // F[X]OR(0.0, x) -> x
24106 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24107 if (C->getValueAPF().isPosZero())
24108 return N->getOperand(1);
24110 // F[X]OR(x, 0.0) -> x
24111 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24112 if (C->getValueAPF().isPosZero())
24113 return N->getOperand(0);
24117 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24118 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24119 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24121 // Only perform optimizations if UnsafeMath is used.
24122 if (!DAG.getTarget().Options.UnsafeFPMath)
24125 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24126 // into FMINC and FMAXC, which are Commutative operations.
24127 unsigned NewOp = 0;
24128 switch (N->getOpcode()) {
24129 default: llvm_unreachable("unknown opcode");
24130 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24131 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24134 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24135 N->getOperand(0), N->getOperand(1));
24138 /// Do target-specific dag combines on X86ISD::FAND nodes.
24139 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24140 // FAND(0.0, x) -> 0.0
24141 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24142 if (C->getValueAPF().isPosZero())
24143 return N->getOperand(0);
24145 // FAND(x, 0.0) -> 0.0
24146 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24147 if (C->getValueAPF().isPosZero())
24148 return N->getOperand(1);
24153 /// Do target-specific dag combines on X86ISD::FANDN nodes
24154 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24155 // FANDN(0.0, x) -> x
24156 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24157 if (C->getValueAPF().isPosZero())
24158 return N->getOperand(1);
24160 // FANDN(x, 0.0) -> 0.0
24161 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24162 if (C->getValueAPF().isPosZero())
24163 return N->getOperand(1);
24168 static SDValue PerformBTCombine(SDNode *N,
24170 TargetLowering::DAGCombinerInfo &DCI) {
24171 // BT ignores high bits in the bit index operand.
24172 SDValue Op1 = N->getOperand(1);
24173 if (Op1.hasOneUse()) {
24174 unsigned BitWidth = Op1.getValueSizeInBits();
24175 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24176 APInt KnownZero, KnownOne;
24177 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24178 !DCI.isBeforeLegalizeOps());
24179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24180 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24181 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24182 DCI.CommitTargetLoweringOpt(TLO);
24187 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24188 SDValue Op = N->getOperand(0);
24189 if (Op.getOpcode() == ISD::BITCAST)
24190 Op = Op.getOperand(0);
24191 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24192 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24193 VT.getVectorElementType().getSizeInBits() ==
24194 OpVT.getVectorElementType().getSizeInBits()) {
24195 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24200 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24201 const X86Subtarget *Subtarget) {
24202 EVT VT = N->getValueType(0);
24203 if (!VT.isVector())
24206 SDValue N0 = N->getOperand(0);
24207 SDValue N1 = N->getOperand(1);
24208 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24211 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24212 // both SSE and AVX2 since there is no sign-extended shift right
24213 // operation on a vector with 64-bit elements.
24214 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24215 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24216 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24217 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24218 SDValue N00 = N0.getOperand(0);
24220 // EXTLOAD has a better solution on AVX2,
24221 // it may be replaced with X86ISD::VSEXT node.
24222 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24223 if (!ISD::isNormalLoad(N00.getNode()))
24226 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24227 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24229 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24235 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24236 TargetLowering::DAGCombinerInfo &DCI,
24237 const X86Subtarget *Subtarget) {
24238 SDValue N0 = N->getOperand(0);
24239 EVT VT = N->getValueType(0);
24240 EVT SVT = VT.getScalarType();
24241 EVT InVT = N0->getValueType(0);
24242 EVT InSVT = InVT.getScalarType();
24245 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24246 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24247 // This exposes the sext to the sdivrem lowering, so that it directly extends
24248 // from AH (which we otherwise need to do contortions to access).
24249 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24250 InVT == MVT::i8 && VT == MVT::i32) {
24251 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24252 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24253 N0.getOperand(0), N0.getOperand(1));
24254 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24255 return R.getValue(1);
24258 if (!DCI.isBeforeLegalizeOps()) {
24259 if (N0.getValueType() == MVT::i1) {
24260 SDValue Zero = DAG.getConstant(0, DL, VT);
24262 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24263 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24268 if (VT.isVector()) {
24269 auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
24270 EVT InVT = N->getValueType(0);
24271 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24272 128 / InVT.getScalarSizeInBits());
24273 SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
24274 DAG.getUNDEF(InVT));
24276 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24279 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24280 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24281 if (VT.getSizeInBits() == 128 &&
24282 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24283 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24284 SDValue ExOp = ExtendToVec128(DL, N0);
24285 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24288 // On pre-AVX2 targets, split into 128-bit nodes of
24289 // ISD::SIGN_EXTEND_VECTOR_INREG.
24290 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24291 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24292 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24293 unsigned NumVecs = VT.getSizeInBits() / 128;
24294 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24295 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24296 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24298 SmallVector<SDValue, 8> Opnds;
24299 for (unsigned i = 0, Offset = 0; i != NumVecs;
24300 ++i, Offset += NumSubElts) {
24301 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24302 DAG.getIntPtrConstant(Offset, DL));
24303 SrcVec = ExtendToVec128(DL, SrcVec);
24304 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24305 Opnds.push_back(SrcVec);
24307 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24311 if (!Subtarget->hasFp256())
24314 if (VT.isVector() && VT.getSizeInBits() == 256) {
24315 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24323 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24324 const X86Subtarget* Subtarget) {
24326 EVT VT = N->getValueType(0);
24328 // Let legalize expand this if it isn't a legal type yet.
24329 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24332 EVT ScalarVT = VT.getScalarType();
24333 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24334 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24337 SDValue A = N->getOperand(0);
24338 SDValue B = N->getOperand(1);
24339 SDValue C = N->getOperand(2);
24341 bool NegA = (A.getOpcode() == ISD::FNEG);
24342 bool NegB = (B.getOpcode() == ISD::FNEG);
24343 bool NegC = (C.getOpcode() == ISD::FNEG);
24345 // Negative multiplication when NegA xor NegB
24346 bool NegMul = (NegA != NegB);
24348 A = A.getOperand(0);
24350 B = B.getOperand(0);
24352 C = C.getOperand(0);
24356 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24358 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24360 return DAG.getNode(Opcode, dl, VT, A, B, C);
24363 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24364 TargetLowering::DAGCombinerInfo &DCI,
24365 const X86Subtarget *Subtarget) {
24366 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24367 // (and (i32 x86isd::setcc_carry), 1)
24368 // This eliminates the zext. This transformation is necessary because
24369 // ISD::SETCC is always legalized to i8.
24371 SDValue N0 = N->getOperand(0);
24372 EVT VT = N->getValueType(0);
24374 if (N0.getOpcode() == ISD::AND &&
24376 N0.getOperand(0).hasOneUse()) {
24377 SDValue N00 = N0.getOperand(0);
24378 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24379 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24380 if (!C || C->getZExtValue() != 1)
24382 return DAG.getNode(ISD::AND, dl, VT,
24383 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24384 N00.getOperand(0), N00.getOperand(1)),
24385 DAG.getConstant(1, dl, VT));
24389 if (N0.getOpcode() == ISD::TRUNCATE &&
24391 N0.getOperand(0).hasOneUse()) {
24392 SDValue N00 = N0.getOperand(0);
24393 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24394 return DAG.getNode(ISD::AND, dl, VT,
24395 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24396 N00.getOperand(0), N00.getOperand(1)),
24397 DAG.getConstant(1, dl, VT));
24400 if (VT.is256BitVector()) {
24401 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24406 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24407 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24408 // This exposes the zext to the udivrem lowering, so that it directly extends
24409 // from AH (which we otherwise need to do contortions to access).
24410 if (N0.getOpcode() == ISD::UDIVREM &&
24411 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24412 (VT == MVT::i32 || VT == MVT::i64)) {
24413 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24414 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24415 N0.getOperand(0), N0.getOperand(1));
24416 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24417 return R.getValue(1);
24423 // Optimize x == -y --> x+y == 0
24424 // x != -y --> x+y != 0
24425 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24426 const X86Subtarget* Subtarget) {
24427 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24428 SDValue LHS = N->getOperand(0);
24429 SDValue RHS = N->getOperand(1);
24430 EVT VT = N->getValueType(0);
24433 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24434 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24435 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24436 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24437 LHS.getOperand(1));
24438 return DAG.getSetCC(DL, N->getValueType(0), addV,
24439 DAG.getConstant(0, DL, addV.getValueType()), CC);
24441 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24442 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24443 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24444 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24445 RHS.getOperand(1));
24446 return DAG.getSetCC(DL, N->getValueType(0), addV,
24447 DAG.getConstant(0, DL, addV.getValueType()), CC);
24450 if (VT.getScalarType() == MVT::i1 &&
24451 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24453 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24454 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24455 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24457 if (!IsSEXT0 || !IsVZero1) {
24458 // Swap the operands and update the condition code.
24459 std::swap(LHS, RHS);
24460 CC = ISD::getSetCCSwappedOperands(CC);
24462 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24463 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24464 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24467 if (IsSEXT0 && IsVZero1) {
24468 assert(VT == LHS.getOperand(0).getValueType() &&
24469 "Uexpected operand type");
24470 if (CC == ISD::SETGT)
24471 return DAG.getConstant(0, DL, VT);
24472 if (CC == ISD::SETLE)
24473 return DAG.getConstant(1, DL, VT);
24474 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24475 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24477 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24478 "Unexpected condition code!");
24479 return LHS.getOperand(0);
24486 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24487 SelectionDAG &DAG) {
24489 MVT VT = Load->getSimpleValueType(0);
24490 MVT EVT = VT.getVectorElementType();
24491 SDValue Addr = Load->getOperand(1);
24492 SDValue NewAddr = DAG.getNode(
24493 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24494 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24495 Addr.getSimpleValueType()));
24498 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24499 DAG.getMachineFunction().getMachineMemOperand(
24500 Load->getMemOperand(), 0, EVT.getStoreSize()));
24504 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24505 const X86Subtarget *Subtarget) {
24507 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24508 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24509 "X86insertps is only defined for v4x32");
24511 SDValue Ld = N->getOperand(1);
24512 if (MayFoldLoad(Ld)) {
24513 // Extract the countS bits from the immediate so we can get the proper
24514 // address when narrowing the vector load to a specific element.
24515 // When the second source op is a memory address, insertps doesn't use
24516 // countS and just gets an f32 from that address.
24517 unsigned DestIndex =
24518 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24520 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24522 // Create this as a scalar to vector to match the instruction pattern.
24523 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24524 // countS bits are ignored when loading from memory on insertps, which
24525 // means we don't need to explicitly set them to 0.
24526 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24527 LoadScalarToVector, N->getOperand(2));
24532 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24533 SDValue V0 = N->getOperand(0);
24534 SDValue V1 = N->getOperand(1);
24536 EVT VT = N->getValueType(0);
24538 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24539 // operands and changing the mask to 1. This saves us a bunch of
24540 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24541 // x86InstrInfo knows how to commute this back after instruction selection
24542 // if it would help register allocation.
24544 // TODO: If optimizing for size or a processor that doesn't suffer from
24545 // partial register update stalls, this should be transformed into a MOVSD
24546 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24548 if (VT == MVT::v2f64)
24549 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24550 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24551 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24552 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24558 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24559 // as "sbb reg,reg", since it can be extended without zext and produces
24560 // an all-ones bit which is more useful than 0/1 in some cases.
24561 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24564 return DAG.getNode(ISD::AND, DL, VT,
24565 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24566 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24568 DAG.getConstant(1, DL, VT));
24569 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24570 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24571 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24572 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24576 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24577 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24578 TargetLowering::DAGCombinerInfo &DCI,
24579 const X86Subtarget *Subtarget) {
24581 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24582 SDValue EFLAGS = N->getOperand(1);
24584 if (CC == X86::COND_A) {
24585 // Try to convert COND_A into COND_B in an attempt to facilitate
24586 // materializing "setb reg".
24588 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24589 // cannot take an immediate as its first operand.
24591 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24592 EFLAGS.getValueType().isInteger() &&
24593 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24594 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24595 EFLAGS.getNode()->getVTList(),
24596 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24597 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24598 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24602 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24603 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24605 if (CC == X86::COND_B)
24606 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24610 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24611 if (Flags.getNode()) {
24612 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24613 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24619 // Optimize branch condition evaluation.
24621 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24622 TargetLowering::DAGCombinerInfo &DCI,
24623 const X86Subtarget *Subtarget) {
24625 SDValue Chain = N->getOperand(0);
24626 SDValue Dest = N->getOperand(1);
24627 SDValue EFLAGS = N->getOperand(3);
24628 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24632 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24633 if (Flags.getNode()) {
24634 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24635 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24642 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24643 SelectionDAG &DAG) {
24644 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24645 // optimize away operation when it's from a constant.
24647 // The general transformation is:
24648 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24649 // AND(VECTOR_CMP(x,y), constant2)
24650 // constant2 = UNARYOP(constant)
24652 // Early exit if this isn't a vector operation, the operand of the
24653 // unary operation isn't a bitwise AND, or if the sizes of the operations
24654 // aren't the same.
24655 EVT VT = N->getValueType(0);
24656 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24657 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24658 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24661 // Now check that the other operand of the AND is a constant. We could
24662 // make the transformation for non-constant splats as well, but it's unclear
24663 // that would be a benefit as it would not eliminate any operations, just
24664 // perform one more step in scalar code before moving to the vector unit.
24665 if (BuildVectorSDNode *BV =
24666 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24667 // Bail out if the vector isn't a constant.
24668 if (!BV->isConstant())
24671 // Everything checks out. Build up the new and improved node.
24673 EVT IntVT = BV->getValueType(0);
24674 // Create a new constant of the appropriate type for the transformed
24676 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24677 // The AND node needs bitcasts to/from an integer vector type around it.
24678 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24679 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24680 N->getOperand(0)->getOperand(0), MaskConst);
24681 SDValue Res = DAG.getBitcast(VT, NewAnd);
24688 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24689 const X86Subtarget *Subtarget) {
24690 // First try to optimize away the conversion entirely when it's
24691 // conditionally from a constant. Vectors only.
24692 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24693 if (Res != SDValue())
24696 // Now move on to more general possibilities.
24697 SDValue Op0 = N->getOperand(0);
24698 EVT InVT = Op0->getValueType(0);
24700 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24701 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24703 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24704 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24705 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24708 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24709 // a 32-bit target where SSE doesn't support i64->FP operations.
24710 if (Op0.getOpcode() == ISD::LOAD) {
24711 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24712 EVT VT = Ld->getValueType(0);
24714 // This transformation is not supported if the result type is f16
24715 if (N->getValueType(0) == MVT::f16)
24718 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24719 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24720 !Subtarget->is64Bit() && VT == MVT::i64) {
24721 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24722 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
24723 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24730 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24731 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24732 X86TargetLowering::DAGCombinerInfo &DCI) {
24733 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24734 // the result is either zero or one (depending on the input carry bit).
24735 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24736 if (X86::isZeroNode(N->getOperand(0)) &&
24737 X86::isZeroNode(N->getOperand(1)) &&
24738 // We don't have a good way to replace an EFLAGS use, so only do this when
24740 SDValue(N, 1).use_empty()) {
24742 EVT VT = N->getValueType(0);
24743 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24744 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24745 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24746 DAG.getConstant(X86::COND_B, DL,
24749 DAG.getConstant(1, DL, VT));
24750 return DCI.CombineTo(N, Res1, CarryOut);
24756 // fold (add Y, (sete X, 0)) -> adc 0, Y
24757 // (add Y, (setne X, 0)) -> sbb -1, Y
24758 // (sub (sete X, 0), Y) -> sbb 0, Y
24759 // (sub (setne X, 0), Y) -> adc -1, Y
24760 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24763 // Look through ZExts.
24764 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24765 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24768 SDValue SetCC = Ext.getOperand(0);
24769 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24772 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24773 if (CC != X86::COND_E && CC != X86::COND_NE)
24776 SDValue Cmp = SetCC.getOperand(1);
24777 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24778 !X86::isZeroNode(Cmp.getOperand(1)) ||
24779 !Cmp.getOperand(0).getValueType().isInteger())
24782 SDValue CmpOp0 = Cmp.getOperand(0);
24783 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24784 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24786 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24787 if (CC == X86::COND_NE)
24788 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24789 DL, OtherVal.getValueType(), OtherVal,
24790 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24792 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24793 DL, OtherVal.getValueType(), OtherVal,
24794 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24797 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24798 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24799 const X86Subtarget *Subtarget) {
24800 EVT VT = N->getValueType(0);
24801 SDValue Op0 = N->getOperand(0);
24802 SDValue Op1 = N->getOperand(1);
24804 // Try to synthesize horizontal adds from adds of shuffles.
24805 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24806 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24807 isHorizontalBinOp(Op0, Op1, true))
24808 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24810 return OptimizeConditionalInDecrement(N, DAG);
24813 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24814 const X86Subtarget *Subtarget) {
24815 SDValue Op0 = N->getOperand(0);
24816 SDValue Op1 = N->getOperand(1);
24818 // X86 can't encode an immediate LHS of a sub. See if we can push the
24819 // negation into a preceding instruction.
24820 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24821 // If the RHS of the sub is a XOR with one use and a constant, invert the
24822 // immediate. Then add one to the LHS of the sub so we can turn
24823 // X-Y -> X+~Y+1, saving one register.
24824 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24825 isa<ConstantSDNode>(Op1.getOperand(1))) {
24826 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24827 EVT VT = Op0.getValueType();
24828 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24830 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24831 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24832 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24836 // Try to synthesize horizontal adds from adds of shuffles.
24837 EVT VT = N->getValueType(0);
24838 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24839 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24840 isHorizontalBinOp(Op0, Op1, true))
24841 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24843 return OptimizeConditionalInDecrement(N, DAG);
24846 /// performVZEXTCombine - Performs build vector combines
24847 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24848 TargetLowering::DAGCombinerInfo &DCI,
24849 const X86Subtarget *Subtarget) {
24851 MVT VT = N->getSimpleValueType(0);
24852 SDValue Op = N->getOperand(0);
24853 MVT OpVT = Op.getSimpleValueType();
24854 MVT OpEltVT = OpVT.getVectorElementType();
24855 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24857 // (vzext (bitcast (vzext (x)) -> (vzext x)
24859 while (V.getOpcode() == ISD::BITCAST)
24860 V = V.getOperand(0);
24862 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24863 MVT InnerVT = V.getSimpleValueType();
24864 MVT InnerEltVT = InnerVT.getVectorElementType();
24866 // If the element sizes match exactly, we can just do one larger vzext. This
24867 // is always an exact type match as vzext operates on integer types.
24868 if (OpEltVT == InnerEltVT) {
24869 assert(OpVT == InnerVT && "Types must match for vzext!");
24870 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24873 // The only other way we can combine them is if only a single element of the
24874 // inner vzext is used in the input to the outer vzext.
24875 if (InnerEltVT.getSizeInBits() < InputBits)
24878 // In this case, the inner vzext is completely dead because we're going to
24879 // only look at bits inside of the low element. Just do the outer vzext on
24880 // a bitcast of the input to the inner.
24881 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
24884 // Check if we can bypass extracting and re-inserting an element of an input
24885 // vector. Essentialy:
24886 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24887 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24888 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24889 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24890 SDValue ExtractedV = V.getOperand(0);
24891 SDValue OrigV = ExtractedV.getOperand(0);
24892 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24893 if (ExtractIdx->getZExtValue() == 0) {
24894 MVT OrigVT = OrigV.getSimpleValueType();
24895 // Extract a subvector if necessary...
24896 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24897 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24898 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24899 OrigVT.getVectorNumElements() / Ratio);
24900 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24901 DAG.getIntPtrConstant(0, DL));
24903 Op = DAG.getBitcast(OpVT, OrigV);
24904 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24911 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24912 DAGCombinerInfo &DCI) const {
24913 SelectionDAG &DAG = DCI.DAG;
24914 switch (N->getOpcode()) {
24916 case ISD::EXTRACT_VECTOR_ELT:
24917 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24920 case X86ISD::SHRUNKBLEND:
24921 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24922 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24923 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24924 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24925 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24926 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24927 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24930 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24931 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24932 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24933 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24934 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24935 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24936 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24937 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24938 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24939 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24940 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24942 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24944 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24945 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24946 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24947 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24948 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24949 case ISD::ANY_EXTEND:
24950 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24951 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24952 case ISD::SIGN_EXTEND_INREG:
24953 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24954 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24955 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24956 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24957 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24958 case X86ISD::SHUFP: // Handle all target specific shuffles
24959 case X86ISD::PALIGNR:
24960 case X86ISD::UNPCKH:
24961 case X86ISD::UNPCKL:
24962 case X86ISD::MOVHLPS:
24963 case X86ISD::MOVLHPS:
24964 case X86ISD::PSHUFB:
24965 case X86ISD::PSHUFD:
24966 case X86ISD::PSHUFHW:
24967 case X86ISD::PSHUFLW:
24968 case X86ISD::MOVSS:
24969 case X86ISD::MOVSD:
24970 case X86ISD::VPERMILPI:
24971 case X86ISD::VPERM2X128:
24972 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24973 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24974 case ISD::INTRINSIC_WO_CHAIN:
24975 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24976 case X86ISD::INSERTPS: {
24977 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24978 return PerformINSERTPSCombine(N, DAG, Subtarget);
24981 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24987 /// isTypeDesirableForOp - Return true if the target has native support for
24988 /// the specified value type and it is 'desirable' to use the type for the
24989 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24990 /// instruction encodings are longer and some i16 instructions are slow.
24991 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24992 if (!isTypeLegal(VT))
24994 if (VT != MVT::i16)
25001 case ISD::SIGN_EXTEND:
25002 case ISD::ZERO_EXTEND:
25003 case ISD::ANY_EXTEND:
25016 /// IsDesirableToPromoteOp - This method query the target whether it is
25017 /// beneficial for dag combiner to promote the specified node. If true, it
25018 /// should return the desired promotion type by reference.
25019 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25020 EVT VT = Op.getValueType();
25021 if (VT != MVT::i16)
25024 bool Promote = false;
25025 bool Commute = false;
25026 switch (Op.getOpcode()) {
25029 LoadSDNode *LD = cast<LoadSDNode>(Op);
25030 // If the non-extending load has a single use and it's not live out, then it
25031 // might be folded.
25032 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25033 Op.hasOneUse()*/) {
25034 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25035 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25036 // The only case where we'd want to promote LOAD (rather then it being
25037 // promoted as an operand is when it's only use is liveout.
25038 if (UI->getOpcode() != ISD::CopyToReg)
25045 case ISD::SIGN_EXTEND:
25046 case ISD::ZERO_EXTEND:
25047 case ISD::ANY_EXTEND:
25052 SDValue N0 = Op.getOperand(0);
25053 // Look out for (store (shl (load), x)).
25054 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25067 SDValue N0 = Op.getOperand(0);
25068 SDValue N1 = Op.getOperand(1);
25069 if (!Commute && MayFoldLoad(N1))
25071 // Avoid disabling potential load folding opportunities.
25072 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25074 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25084 //===----------------------------------------------------------------------===//
25085 // X86 Inline Assembly Support
25086 //===----------------------------------------------------------------------===//
25088 // Helper to match a string separated by whitespace.
25089 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25090 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25092 for (StringRef Piece : Pieces) {
25093 if (!S.startswith(Piece)) // Check if the piece matches.
25096 S = S.substr(Piece.size());
25097 StringRef::size_type Pos = S.find_first_not_of(" \t");
25098 if (Pos == 0) // We matched a prefix.
25107 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25109 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25110 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25111 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25112 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25114 if (AsmPieces.size() == 3)
25116 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25123 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25124 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25126 std::string AsmStr = IA->getAsmString();
25128 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25129 if (!Ty || Ty->getBitWidth() % 16 != 0)
25132 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25133 SmallVector<StringRef, 4> AsmPieces;
25134 SplitString(AsmStr, AsmPieces, ";\n");
25136 switch (AsmPieces.size()) {
25137 default: return false;
25139 // FIXME: this should verify that we are targeting a 486 or better. If not,
25140 // we will turn this bswap into something that will be lowered to logical
25141 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25142 // lower so don't worry about this.
25144 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25145 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25146 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25147 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25148 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25149 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25150 // No need to check constraints, nothing other than the equivalent of
25151 // "=r,0" would be valid here.
25152 return IntrinsicLowering::LowerToByteSwap(CI);
25155 // rorw $$8, ${0:w} --> llvm.bswap.i16
25156 if (CI->getType()->isIntegerTy(16) &&
25157 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25158 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25159 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25161 const std::string &ConstraintsStr = IA->getConstraintString();
25162 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25163 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25164 if (clobbersFlagRegisters(AsmPieces))
25165 return IntrinsicLowering::LowerToByteSwap(CI);
25169 if (CI->getType()->isIntegerTy(32) &&
25170 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25171 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25172 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25173 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25175 const std::string &ConstraintsStr = IA->getConstraintString();
25176 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25177 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25178 if (clobbersFlagRegisters(AsmPieces))
25179 return IntrinsicLowering::LowerToByteSwap(CI);
25182 if (CI->getType()->isIntegerTy(64)) {
25183 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25184 if (Constraints.size() >= 2 &&
25185 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25186 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25187 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25188 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25189 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25190 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25191 return IntrinsicLowering::LowerToByteSwap(CI);
25199 /// getConstraintType - Given a constraint letter, return the type of
25200 /// constraint it is for this target.
25201 X86TargetLowering::ConstraintType
25202 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25203 if (Constraint.size() == 1) {
25204 switch (Constraint[0]) {
25215 return C_RegisterClass;
25239 return TargetLowering::getConstraintType(Constraint);
25242 /// Examine constraint type and operand type and determine a weight value.
25243 /// This object must already have been set up with the operand type
25244 /// and the current alternative constraint selected.
25245 TargetLowering::ConstraintWeight
25246 X86TargetLowering::getSingleConstraintMatchWeight(
25247 AsmOperandInfo &info, const char *constraint) const {
25248 ConstraintWeight weight = CW_Invalid;
25249 Value *CallOperandVal = info.CallOperandVal;
25250 // If we don't have a value, we can't do a match,
25251 // but allow it at the lowest weight.
25252 if (!CallOperandVal)
25254 Type *type = CallOperandVal->getType();
25255 // Look at the constraint type.
25256 switch (*constraint) {
25258 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25269 if (CallOperandVal->getType()->isIntegerTy())
25270 weight = CW_SpecificReg;
25275 if (type->isFloatingPointTy())
25276 weight = CW_SpecificReg;
25279 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25280 weight = CW_SpecificReg;
25284 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25285 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25286 weight = CW_Register;
25289 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25290 if (C->getZExtValue() <= 31)
25291 weight = CW_Constant;
25295 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25296 if (C->getZExtValue() <= 63)
25297 weight = CW_Constant;
25301 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25302 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25303 weight = CW_Constant;
25307 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25308 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25309 weight = CW_Constant;
25313 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25314 if (C->getZExtValue() <= 3)
25315 weight = CW_Constant;
25319 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25320 if (C->getZExtValue() <= 0xff)
25321 weight = CW_Constant;
25326 if (isa<ConstantFP>(CallOperandVal)) {
25327 weight = CW_Constant;
25331 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25332 if ((C->getSExtValue() >= -0x80000000LL) &&
25333 (C->getSExtValue() <= 0x7fffffffLL))
25334 weight = CW_Constant;
25338 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25339 if (C->getZExtValue() <= 0xffffffff)
25340 weight = CW_Constant;
25347 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25348 /// with another that has more specific requirements based on the type of the
25349 /// corresponding operand.
25350 const char *X86TargetLowering::
25351 LowerXConstraint(EVT ConstraintVT) const {
25352 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25353 // 'f' like normal targets.
25354 if (ConstraintVT.isFloatingPoint()) {
25355 if (Subtarget->hasSSE2())
25357 if (Subtarget->hasSSE1())
25361 return TargetLowering::LowerXConstraint(ConstraintVT);
25364 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25365 /// vector. If it is invalid, don't add anything to Ops.
25366 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25367 std::string &Constraint,
25368 std::vector<SDValue>&Ops,
25369 SelectionDAG &DAG) const {
25372 // Only support length 1 constraints for now.
25373 if (Constraint.length() > 1) return;
25375 char ConstraintLetter = Constraint[0];
25376 switch (ConstraintLetter) {
25379 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25380 if (C->getZExtValue() <= 31) {
25381 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25382 Op.getValueType());
25388 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25389 if (C->getZExtValue() <= 63) {
25390 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25391 Op.getValueType());
25397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25398 if (isInt<8>(C->getSExtValue())) {
25399 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25400 Op.getValueType());
25406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25407 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25408 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25409 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25410 Op.getValueType());
25416 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25417 if (C->getZExtValue() <= 3) {
25418 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25419 Op.getValueType());
25425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25426 if (C->getZExtValue() <= 255) {
25427 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25428 Op.getValueType());
25434 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25435 if (C->getZExtValue() <= 127) {
25436 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25437 Op.getValueType());
25443 // 32-bit signed value
25444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25445 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25446 C->getSExtValue())) {
25447 // Widen to 64 bits here to get it sign extended.
25448 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25451 // FIXME gcc accepts some relocatable values here too, but only in certain
25452 // memory models; it's complicated.
25457 // 32-bit unsigned value
25458 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25459 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25460 C->getZExtValue())) {
25461 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25462 Op.getValueType());
25466 // FIXME gcc accepts some relocatable values here too, but only in certain
25467 // memory models; it's complicated.
25471 // Literal immediates are always ok.
25472 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25473 // Widen to 64 bits here to get it sign extended.
25474 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25478 // In any sort of PIC mode addresses need to be computed at runtime by
25479 // adding in a register or some sort of table lookup. These can't
25480 // be used as immediates.
25481 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25484 // If we are in non-pic codegen mode, we allow the address of a global (with
25485 // an optional displacement) to be used with 'i'.
25486 GlobalAddressSDNode *GA = nullptr;
25487 int64_t Offset = 0;
25489 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25491 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25492 Offset += GA->getOffset();
25494 } else if (Op.getOpcode() == ISD::ADD) {
25495 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25496 Offset += C->getZExtValue();
25497 Op = Op.getOperand(0);
25500 } else if (Op.getOpcode() == ISD::SUB) {
25501 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25502 Offset += -C->getZExtValue();
25503 Op = Op.getOperand(0);
25508 // Otherwise, this isn't something we can handle, reject it.
25512 const GlobalValue *GV = GA->getGlobal();
25513 // If we require an extra load to get this address, as in PIC mode, we
25514 // can't accept it.
25515 if (isGlobalStubReference(
25516 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25519 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25520 GA->getValueType(0), Offset);
25525 if (Result.getNode()) {
25526 Ops.push_back(Result);
25529 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25532 std::pair<unsigned, const TargetRegisterClass *>
25533 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25534 const std::string &Constraint,
25536 // First, see if this is a constraint that directly corresponds to an LLVM
25538 if (Constraint.size() == 1) {
25539 // GCC Constraint Letters
25540 switch (Constraint[0]) {
25542 // TODO: Slight differences here in allocation order and leaving
25543 // RIP in the class. Do they matter any more here than they do
25544 // in the normal allocation?
25545 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25546 if (Subtarget->is64Bit()) {
25547 if (VT == MVT::i32 || VT == MVT::f32)
25548 return std::make_pair(0U, &X86::GR32RegClass);
25549 if (VT == MVT::i16)
25550 return std::make_pair(0U, &X86::GR16RegClass);
25551 if (VT == MVT::i8 || VT == MVT::i1)
25552 return std::make_pair(0U, &X86::GR8RegClass);
25553 if (VT == MVT::i64 || VT == MVT::f64)
25554 return std::make_pair(0U, &X86::GR64RegClass);
25557 // 32-bit fallthrough
25558 case 'Q': // Q_REGS
25559 if (VT == MVT::i32 || VT == MVT::f32)
25560 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25561 if (VT == MVT::i16)
25562 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25563 if (VT == MVT::i8 || VT == MVT::i1)
25564 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25565 if (VT == MVT::i64)
25566 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25568 case 'r': // GENERAL_REGS
25569 case 'l': // INDEX_REGS
25570 if (VT == MVT::i8 || VT == MVT::i1)
25571 return std::make_pair(0U, &X86::GR8RegClass);
25572 if (VT == MVT::i16)
25573 return std::make_pair(0U, &X86::GR16RegClass);
25574 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25575 return std::make_pair(0U, &X86::GR32RegClass);
25576 return std::make_pair(0U, &X86::GR64RegClass);
25577 case 'R': // LEGACY_REGS
25578 if (VT == MVT::i8 || VT == MVT::i1)
25579 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25580 if (VT == MVT::i16)
25581 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25582 if (VT == MVT::i32 || !Subtarget->is64Bit())
25583 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25584 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25585 case 'f': // FP Stack registers.
25586 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25587 // value to the correct fpstack register class.
25588 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25589 return std::make_pair(0U, &X86::RFP32RegClass);
25590 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25591 return std::make_pair(0U, &X86::RFP64RegClass);
25592 return std::make_pair(0U, &X86::RFP80RegClass);
25593 case 'y': // MMX_REGS if MMX allowed.
25594 if (!Subtarget->hasMMX()) break;
25595 return std::make_pair(0U, &X86::VR64RegClass);
25596 case 'Y': // SSE_REGS if SSE2 allowed
25597 if (!Subtarget->hasSSE2()) break;
25599 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25600 if (!Subtarget->hasSSE1()) break;
25602 switch (VT.SimpleTy) {
25604 // Scalar SSE types.
25607 return std::make_pair(0U, &X86::FR32RegClass);
25610 return std::make_pair(0U, &X86::FR64RegClass);
25618 return std::make_pair(0U, &X86::VR128RegClass);
25626 return std::make_pair(0U, &X86::VR256RegClass);
25631 return std::make_pair(0U, &X86::VR512RegClass);
25637 // Use the default implementation in TargetLowering to convert the register
25638 // constraint into a member of a register class.
25639 std::pair<unsigned, const TargetRegisterClass*> Res;
25640 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25642 // Not found as a standard register?
25644 // Map st(0) -> st(7) -> ST0
25645 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25646 tolower(Constraint[1]) == 's' &&
25647 tolower(Constraint[2]) == 't' &&
25648 Constraint[3] == '(' &&
25649 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25650 Constraint[5] == ')' &&
25651 Constraint[6] == '}') {
25653 Res.first = X86::FP0+Constraint[4]-'0';
25654 Res.second = &X86::RFP80RegClass;
25658 // GCC allows "st(0)" to be called just plain "st".
25659 if (StringRef("{st}").equals_lower(Constraint)) {
25660 Res.first = X86::FP0;
25661 Res.second = &X86::RFP80RegClass;
25666 if (StringRef("{flags}").equals_lower(Constraint)) {
25667 Res.first = X86::EFLAGS;
25668 Res.second = &X86::CCRRegClass;
25672 // 'A' means EAX + EDX.
25673 if (Constraint == "A") {
25674 Res.first = X86::EAX;
25675 Res.second = &X86::GR32_ADRegClass;
25681 // Otherwise, check to see if this is a register class of the wrong value
25682 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25683 // turn into {ax},{dx}.
25684 if (Res.second->hasType(VT))
25685 return Res; // Correct type already, nothing to do.
25687 // All of the single-register GCC register classes map their values onto
25688 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25689 // really want an 8-bit or 32-bit register, map to the appropriate register
25690 // class and return the appropriate register.
25691 if (Res.second == &X86::GR16RegClass) {
25692 if (VT == MVT::i8 || VT == MVT::i1) {
25693 unsigned DestReg = 0;
25694 switch (Res.first) {
25696 case X86::AX: DestReg = X86::AL; break;
25697 case X86::DX: DestReg = X86::DL; break;
25698 case X86::CX: DestReg = X86::CL; break;
25699 case X86::BX: DestReg = X86::BL; break;
25702 Res.first = DestReg;
25703 Res.second = &X86::GR8RegClass;
25705 } else if (VT == MVT::i32 || VT == MVT::f32) {
25706 unsigned DestReg = 0;
25707 switch (Res.first) {
25709 case X86::AX: DestReg = X86::EAX; break;
25710 case X86::DX: DestReg = X86::EDX; break;
25711 case X86::CX: DestReg = X86::ECX; break;
25712 case X86::BX: DestReg = X86::EBX; break;
25713 case X86::SI: DestReg = X86::ESI; break;
25714 case X86::DI: DestReg = X86::EDI; break;
25715 case X86::BP: DestReg = X86::EBP; break;
25716 case X86::SP: DestReg = X86::ESP; break;
25719 Res.first = DestReg;
25720 Res.second = &X86::GR32RegClass;
25722 } else if (VT == MVT::i64 || VT == MVT::f64) {
25723 unsigned DestReg = 0;
25724 switch (Res.first) {
25726 case X86::AX: DestReg = X86::RAX; break;
25727 case X86::DX: DestReg = X86::RDX; break;
25728 case X86::CX: DestReg = X86::RCX; break;
25729 case X86::BX: DestReg = X86::RBX; break;
25730 case X86::SI: DestReg = X86::RSI; break;
25731 case X86::DI: DestReg = X86::RDI; break;
25732 case X86::BP: DestReg = X86::RBP; break;
25733 case X86::SP: DestReg = X86::RSP; break;
25736 Res.first = DestReg;
25737 Res.second = &X86::GR64RegClass;
25739 } else if (VT != MVT::Other) {
25740 // Type mismatch and not a clobber: Return an error;
25742 Res.second = nullptr;
25744 } else if (Res.second == &X86::FR32RegClass ||
25745 Res.second == &X86::FR64RegClass ||
25746 Res.second == &X86::VR128RegClass ||
25747 Res.second == &X86::VR256RegClass ||
25748 Res.second == &X86::FR32XRegClass ||
25749 Res.second == &X86::FR64XRegClass ||
25750 Res.second == &X86::VR128XRegClass ||
25751 Res.second == &X86::VR256XRegClass ||
25752 Res.second == &X86::VR512RegClass) {
25753 // Handle references to XMM physical registers that got mapped into the
25754 // wrong class. This can happen with constraints like {xmm0} where the
25755 // target independent register mapper will just pick the first match it can
25756 // find, ignoring the required type.
25758 if (VT == MVT::f32 || VT == MVT::i32)
25759 Res.second = &X86::FR32RegClass;
25760 else if (VT == MVT::f64 || VT == MVT::i64)
25761 Res.second = &X86::FR64RegClass;
25762 else if (X86::VR128RegClass.hasType(VT))
25763 Res.second = &X86::VR128RegClass;
25764 else if (X86::VR256RegClass.hasType(VT))
25765 Res.second = &X86::VR256RegClass;
25766 else if (X86::VR512RegClass.hasType(VT))
25767 Res.second = &X86::VR512RegClass;
25768 else if (VT != MVT::Other) {
25769 // Type mismatch and not a clobber: Return an error;
25771 Res.second = nullptr;
25773 } else if (VT != MVT::Other) {
25774 // Type mismatch and not a clobber: Return an error;
25776 Res.second = nullptr;
25782 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25784 unsigned AS) const {
25785 // Scaling factors are not free at all.
25786 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25787 // will take 2 allocations in the out of order engine instead of 1
25788 // for plain addressing mode, i.e. inst (reg1).
25790 // vaddps (%rsi,%drx), %ymm0, %ymm1
25791 // Requires two allocations (one for the load, one for the computation)
25793 // vaddps (%rsi), %ymm0, %ymm1
25794 // Requires just 1 allocation, i.e., freeing allocations for other operations
25795 // and having less micro operations to execute.
25797 // For some X86 architectures, this is even worse because for instance for
25798 // stores, the complex addressing mode forces the instruction to use the
25799 // "load" ports instead of the dedicated "store" port.
25800 // E.g., on Haswell:
25801 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25802 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25803 if (isLegalAddressingMode(AM, Ty, AS))
25804 // Scale represents reg2 * scale, thus account for 1
25805 // as soon as we use a second register.
25806 return AM.Scale != 0;
25810 bool X86TargetLowering::isTargetFTOL() const {
25811 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();