1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static SDValue Insert128BitVector(SDValue Result,
70 static SDValue Extract128BitVector(SDValue Vec,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
77 /// simple subregister reference. Idx is an index in the 128 bits we
78 /// want. It need not be aligned to a 128-bit bounday. That makes
79 /// lowering EXTRACT_VECTOR_ELT operations easier.
80 static SDValue Extract128BitVector(SDValue Vec,
84 EVT VT = Vec.getValueType();
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
86 EVT ElVT = VT.getVectorElementType();
87 int Factor = VT.getSizeInBits()/128;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
95 if (isa<ConstantSDNode>(Idx)) {
96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
99 // we can match to VEXTRACTF128.
100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
102 // This is the index of the first element of the 128-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
118 /// sets things up to match to an AVX VINSERTF128 instruction or a
119 /// simple superregister reference. Idx is an index in the 128 bits
120 /// we want. It need not be aligned to a 128-bit bounday. That makes
121 /// lowering INSERT_VECTOR_ELT operations easier.
122 static SDValue Insert128BitVector(SDValue Result,
127 if (isa<ConstantSDNode>(Idx)) {
128 EVT VT = Vec.getValueType();
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
131 EVT ElVT = VT.getVectorElementType();
132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
133 EVT ResultVT = Result.getValueType();
135 // Insert the relevant 128 bits.
136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
138 // This is the index of the first element of the 128-bit chunk
140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
154 bool is64Bit = Subtarget->is64Bit();
156 if (Subtarget->isTargetEnvMacho()) {
158 return new X8664_MachoTargetObjectFile();
159 return new TargetLoweringObjectFileMachO();
162 if (Subtarget->isTargetELF())
163 return new TargetLoweringObjectFileELF();
164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
165 return new TargetLoweringObjectFileCOFF();
166 llvm_unreachable("unknown subtarget type");
169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<X86Subtarget>();
172 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
173 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
176 RegInfo = TM.getRegisterInfo();
177 TD = getTargetData();
179 // Set up the TargetLowering object.
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
183 setBooleanContents(ZeroOrOneBooleanContent);
184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
187 // For 64-bit since we have so many registers use the ILP scheduler, for
188 // 32-bit code use the register pressure specific scheduling.
189 if (Subtarget->is64Bit())
190 setSchedulingPreference(Sched::ILP);
192 setSchedulingPreference(Sched::RegPressure);
193 setStackPointerRegisterToSaveRestore(X86StackPtr);
195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
196 // Setup Windows compiler runtime calls.
197 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
199 setLibcallName(RTLIB::SREM_I64, "_allrem");
200 setLibcallName(RTLIB::UREM_I64, "_aullrem");
201 setLibcallName(RTLIB::MUL_I64, "_allmul");
202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
213 if (Subtarget->isTargetDarwin()) {
214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
215 setUseUnderscoreSetJmp(false);
216 setUseUnderscoreLongJmp(false);
217 } else if (Subtarget->isTargetMingw()) {
218 // MS runtime is weird: it exports _setjmp, but longjmp!
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(false);
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(true);
226 // Set up the register classes.
227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
228 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
230 if (Subtarget->is64Bit())
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // We don't accept any truncstore of integer registers.
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
239 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
241 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
243 // SETOEQ and SETUNE require checking two conditions.
244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
257 if (Subtarget->is64Bit()) {
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
260 } else if (!UseSoftFloat) {
261 // We have an algorithm for SSE2->double, and we turn this into a
262 // 64-bit FILD followed by conditional FADD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
264 // We have an algorithm for SSE2, and we turn this into a 64-bit
265 // FILD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
275 // SSE has no i16 to fp conversion, only i32
276 if (X86ScalarSSEf32) {
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 // f32 and f64 cases are Legal, f80 case is not
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
290 // are Legal, f80 is custom lowered.
291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
299 if (X86ScalarSSEf32) {
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
301 // f32 and f64 cases are Legal, f80 case is not
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 // Handle FP_TO_UINT by promoting the destination to a larger signed
310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
314 if (Subtarget->is64Bit()) {
315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
317 } else if (!UseSoftFloat) {
318 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
319 // Expand FP_TO_UINT into a select.
320 // FIXME: We would like to use a Custom expander here eventually to do
321 // the optimal thing for SSE vs. the default expansion in the legalizer.
322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
324 // With SSE3 we can use fisttpll to convert to a signed i64; without
325 // SSE, we're stuck with a fistpll.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0, e = 4; i != e; ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
382 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
383 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
384 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
385 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
387 if (Subtarget->is64Bit()) {
388 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
389 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
392 if (Subtarget->hasPOPCNT()) {
393 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
395 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
396 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
397 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
402 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
403 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
405 // These should be promoted to a larger select which is supported.
406 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
407 // X86 wants to expand cmov itself.
408 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
410 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
413 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
416 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
424 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
427 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
428 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
429 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
431 if (Subtarget->is64Bit())
432 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
433 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
434 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
435 if (Subtarget->is64Bit()) {
436 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
437 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
438 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
439 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
440 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
442 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
443 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
444 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
446 if (Subtarget->is64Bit()) {
447 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
448 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
452 if (Subtarget->hasXMM())
453 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
455 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // On X86 and X86-64, atomic operations are lowered to locked instructions.
459 // Locked instructions, in turn, have implicit fence semantics (all memory
460 // operations are flushed before issuing the locked instruction, and they
461 // are not buffered), so we can fold away the common pattern of
462 // fence-atomic-fence.
463 setShouldFoldAtomicFences(true);
465 // Expand certain atomics
466 for (unsigned i = 0, e = 4; i != e; ++i) {
468 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
469 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
470 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
473 if (!Subtarget->is64Bit()) {
474 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
479 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
480 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
481 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
484 if (Subtarget->hasCmpxchg16b()) {
485 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
488 // FIXME - use subtarget debug flags
489 if (!Subtarget->isTargetDarwin() &&
490 !Subtarget->isTargetELF() &&
491 !Subtarget->isTargetCygMing()) {
492 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
495 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
496 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
497 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
498 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
499 if (Subtarget->is64Bit()) {
500 setExceptionPointerRegister(X86::RAX);
501 setExceptionSelectorRegister(X86::RDX);
503 setExceptionPointerRegister(X86::EAX);
504 setExceptionSelectorRegister(X86::EDX);
506 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
507 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
509 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
510 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
512 setOperationAction(ISD::TRAP, MVT::Other, Legal);
514 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
515 setOperationAction(ISD::VASTART , MVT::Other, Custom);
516 setOperationAction(ISD::VAEND , MVT::Other, Expand);
517 if (Subtarget->is64Bit()) {
518 setOperationAction(ISD::VAARG , MVT::Other, Custom);
519 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
521 setOperationAction(ISD::VAARG , MVT::Other, Expand);
522 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
525 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
526 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
528 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
529 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
530 MVT::i64 : MVT::i32, Custom);
531 else if (EnableSegmentedStacks)
532 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
533 MVT::i64 : MVT::i32, Custom);
535 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
536 MVT::i64 : MVT::i32, Expand);
538 if (!UseSoftFloat && X86ScalarSSEf64) {
539 // f32 and f64 use SSE.
540 // Set up the FP register classes.
541 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
542 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
544 // Use ANDPD to simulate FABS.
545 setOperationAction(ISD::FABS , MVT::f64, Custom);
546 setOperationAction(ISD::FABS , MVT::f32, Custom);
548 // Use XORP to simulate FNEG.
549 setOperationAction(ISD::FNEG , MVT::f64, Custom);
550 setOperationAction(ISD::FNEG , MVT::f32, Custom);
552 // Use ANDPD and ORPD to simulate FCOPYSIGN.
553 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
554 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
556 // Lower this to FGETSIGNx86 plus an AND.
557 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
558 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
560 // We don't support sin/cos/fmod
561 setOperationAction(ISD::FSIN , MVT::f64, Expand);
562 setOperationAction(ISD::FCOS , MVT::f64, Expand);
563 setOperationAction(ISD::FSIN , MVT::f32, Expand);
564 setOperationAction(ISD::FCOS , MVT::f32, Expand);
566 // Expand FP immediates into loads from the stack, except for the special
568 addLegalFPImmediate(APFloat(+0.0)); // xorpd
569 addLegalFPImmediate(APFloat(+0.0f)); // xorps
570 } else if (!UseSoftFloat && X86ScalarSSEf32) {
571 // Use SSE for f32, x87 for f64.
572 // Set up the FP register classes.
573 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
574 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
576 // Use ANDPS to simulate FABS.
577 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 // Use XORP to simulate FNEG.
580 setOperationAction(ISD::FNEG , MVT::f32, Custom);
582 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
584 // Use ANDPS and ORPS to simulate FCOPYSIGN.
585 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
586 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
588 // We don't support sin/cos/fmod
589 setOperationAction(ISD::FSIN , MVT::f32, Expand);
590 setOperationAction(ISD::FCOS , MVT::f32, Expand);
592 // Special cases we handle for FP constants.
593 addLegalFPImmediate(APFloat(+0.0f)); // xorps
594 addLegalFPImmediate(APFloat(+0.0)); // FLD0
595 addLegalFPImmediate(APFloat(+1.0)); // FLD1
596 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
597 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
600 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
601 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
603 } else if (!UseSoftFloat) {
604 // f32 and f64 in x87.
605 // Set up the FP register classes.
606 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
607 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
609 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
610 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
612 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
615 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
616 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
618 addLegalFPImmediate(APFloat(+0.0)); // FLD0
619 addLegalFPImmediate(APFloat(+1.0)); // FLD1
620 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
621 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
622 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
623 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
624 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
625 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
628 // We don't support FMA.
629 setOperationAction(ISD::FMA, MVT::f64, Expand);
630 setOperationAction(ISD::FMA, MVT::f32, Expand);
632 // Long double always uses X87.
634 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
635 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
638 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
639 addLegalFPImmediate(TmpFlt); // FLD0
641 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
644 APFloat TmpFlt2(+1.0);
645 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
647 addLegalFPImmediate(TmpFlt2); // FLD1
648 TmpFlt2.changeSign();
649 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
653 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
654 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
657 setOperationAction(ISD::FMA, MVT::f80, Expand);
660 // Always use a library call for pow.
661 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
662 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
663 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
665 setOperationAction(ISD::FLOG, MVT::f80, Expand);
666 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
667 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
668 setOperationAction(ISD::FEXP, MVT::f80, Expand);
669 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
671 // First set operation action for all vector types to either promote
672 // (for widening) or expand (for scalarization). Then we will selectively
673 // turn on ones that can be effectively codegen'd.
674 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
675 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
676 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
678 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
691 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
693 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
694 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
730 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
731 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
732 setTruncStoreAction((MVT::SimpleValueType)VT,
733 (MVT::SimpleValueType)InnerVT, Expand);
734 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
735 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
736 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
739 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
740 // with -msoft-float, disable use of MMX as well.
741 if (!UseSoftFloat && Subtarget->hasMMX()) {
742 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
743 // No operations on x86mmx supported, everything uses intrinsics.
746 // MMX-sized vectors (other than x86mmx) are expected to be expanded
747 // into smaller operations.
748 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
749 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
750 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
751 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
752 setOperationAction(ISD::AND, MVT::v8i8, Expand);
753 setOperationAction(ISD::AND, MVT::v4i16, Expand);
754 setOperationAction(ISD::AND, MVT::v2i32, Expand);
755 setOperationAction(ISD::AND, MVT::v1i64, Expand);
756 setOperationAction(ISD::OR, MVT::v8i8, Expand);
757 setOperationAction(ISD::OR, MVT::v4i16, Expand);
758 setOperationAction(ISD::OR, MVT::v2i32, Expand);
759 setOperationAction(ISD::OR, MVT::v1i64, Expand);
760 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
761 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
762 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
763 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
764 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
765 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
767 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
769 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
770 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
771 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
772 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
773 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
774 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
775 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
776 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
778 if (!UseSoftFloat && Subtarget->hasXMM()) {
779 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
781 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
783 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
784 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
786 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
787 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
789 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
791 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
792 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
795 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
796 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
798 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
799 // registers cannot be used even for integer operations.
800 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
801 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
802 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
803 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
805 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
806 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
807 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
808 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
809 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
810 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
811 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
812 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
813 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
815 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
816 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
817 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
818 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
819 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
820 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
822 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
823 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
824 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
827 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
828 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
829 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
830 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
833 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
834 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
835 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
836 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
837 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
839 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
840 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
841 EVT VT = (MVT::SimpleValueType)i;
842 // Do not attempt to custom lower non-power-of-2 vectors
843 if (!isPowerOf2_32(VT.getVectorNumElements()))
845 // Do not attempt to custom lower non-128-bit vectors
846 if (!VT.is128BitVector())
848 setOperationAction(ISD::BUILD_VECTOR,
849 VT.getSimpleVT().SimpleTy, Custom);
850 setOperationAction(ISD::VECTOR_SHUFFLE,
851 VT.getSimpleVT().SimpleTy, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
853 VT.getSimpleVT().SimpleTy, Custom);
856 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
857 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
858 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
863 if (Subtarget->is64Bit()) {
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
868 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
869 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
870 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
873 // Do not attempt to promote non-128-bit vectors
874 if (!VT.is128BitVector())
877 setOperationAction(ISD::AND, SVT, Promote);
878 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
879 setOperationAction(ISD::OR, SVT, Promote);
880 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
881 setOperationAction(ISD::XOR, SVT, Promote);
882 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
883 setOperationAction(ISD::LOAD, SVT, Promote);
884 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
885 setOperationAction(ISD::SELECT, SVT, Promote);
886 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
889 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
891 // Custom lower v2i64 and v2f64 selects.
892 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
893 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
894 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
895 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
897 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
898 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
901 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
902 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
903 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
904 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
905 setOperationAction(ISD::FRINT, MVT::f32, Legal);
906 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
907 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
908 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
909 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
910 setOperationAction(ISD::FRINT, MVT::f64, Legal);
911 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
913 // FIXME: Do we need to handle scalar-to-vector here?
914 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
916 // Can turn SHL into an integer multiply.
917 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
918 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
920 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
921 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::VSELECT, MVT::v16i8, Custom);
923 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
924 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
925 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
927 // i8 and i16 vectors are custom , because the source register and source
928 // source memory operand types are not the same width. f32 vectors are
929 // custom since the immediate controlling the insert encodes additional
931 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
938 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
939 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
941 if (Subtarget->is64Bit()) {
942 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
947 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
948 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
949 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
950 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
951 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
953 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
954 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
955 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
957 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
958 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
961 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
962 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
964 if (!UseSoftFloat && Subtarget->hasAVX()) {
965 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
966 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
967 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
968 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
969 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
970 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
972 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
973 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
974 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
976 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
977 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
978 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
979 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
980 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
981 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
983 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
984 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
985 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
986 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
987 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
988 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
990 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
991 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
992 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
994 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
995 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
996 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
997 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
998 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
999 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1001 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1003 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1004 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1006 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1007 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1008 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1009 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1011 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1012 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1014 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1015 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1016 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1017 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1023 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1024 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1025 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1026 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1028 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1029 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1030 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1031 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1033 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1034 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1035 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1036 // Don't lower v32i8 because there is no 128-bit byte mul
1038 // Custom lower several nodes for 256-bit types.
1039 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1040 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1041 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1044 // Extract subvector is special because the value type
1045 // (result) is 128-bit but the source is 256-bit wide.
1046 if (VT.is128BitVector())
1047 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1049 // Do not attempt to custom lower other non-256-bit vectors
1050 if (!VT.is256BitVector())
1053 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1054 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1055 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1056 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1057 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1058 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1061 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1062 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1063 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1066 // Do not attempt to promote non-256-bit vectors
1067 if (!VT.is256BitVector())
1070 setOperationAction(ISD::AND, SVT, Promote);
1071 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1072 setOperationAction(ISD::OR, SVT, Promote);
1073 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1074 setOperationAction(ISD::XOR, SVT, Promote);
1075 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1076 setOperationAction(ISD::LOAD, SVT, Promote);
1077 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1078 setOperationAction(ISD::SELECT, SVT, Promote);
1079 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1083 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1084 // of this type with custom code.
1085 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1086 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1087 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1090 // We want to custom lower some of our intrinsics.
1091 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1094 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1095 // handle type legalization for these operations here.
1097 // FIXME: We really should do custom legalization for addition and
1098 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1099 // than generic legalization for 64-bit multiplication-with-overflow, though.
1100 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1101 // Add/Sub/Mul with overflow operations are custom lowered.
1103 setOperationAction(ISD::SADDO, VT, Custom);
1104 setOperationAction(ISD::UADDO, VT, Custom);
1105 setOperationAction(ISD::SSUBO, VT, Custom);
1106 setOperationAction(ISD::USUBO, VT, Custom);
1107 setOperationAction(ISD::SMULO, VT, Custom);
1108 setOperationAction(ISD::UMULO, VT, Custom);
1111 // There are no 8-bit 3-address imul/mul instructions
1112 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1113 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1115 if (!Subtarget->is64Bit()) {
1116 // These libcalls are not available in 32-bit.
1117 setLibcallName(RTLIB::SHL_I128, 0);
1118 setLibcallName(RTLIB::SRL_I128, 0);
1119 setLibcallName(RTLIB::SRA_I128, 0);
1122 // We have target-specific dag combine patterns for the following nodes:
1123 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1124 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1125 setTargetDAGCombine(ISD::BUILD_VECTOR);
1126 setTargetDAGCombine(ISD::SELECT);
1127 setTargetDAGCombine(ISD::SHL);
1128 setTargetDAGCombine(ISD::SRA);
1129 setTargetDAGCombine(ISD::SRL);
1130 setTargetDAGCombine(ISD::OR);
1131 setTargetDAGCombine(ISD::AND);
1132 setTargetDAGCombine(ISD::ADD);
1133 setTargetDAGCombine(ISD::SUB);
1134 setTargetDAGCombine(ISD::STORE);
1135 setTargetDAGCombine(ISD::ZERO_EXTEND);
1136 setTargetDAGCombine(ISD::SINT_TO_FP);
1137 if (Subtarget->is64Bit())
1138 setTargetDAGCombine(ISD::MUL);
1140 computeRegisterProperties();
1142 // On Darwin, -Os means optimize for size without hurting performance,
1143 // do not reduce the limit.
1144 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1145 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1146 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1147 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1148 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1149 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1150 setPrefLoopAlignment(16);
1151 benefitFromCodePlacementOpt = true;
1153 setPrefFunctionAlignment(4);
1157 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1158 if (!VT.isVector()) return MVT::i8;
1159 return VT.changeVectorElementTypeToInteger();
1163 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1164 /// the desired ByVal argument alignment.
1165 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1168 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1169 if (VTy->getBitWidth() == 128)
1171 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1172 unsigned EltAlign = 0;
1173 getMaxByValAlign(ATy->getElementType(), EltAlign);
1174 if (EltAlign > MaxAlign)
1175 MaxAlign = EltAlign;
1176 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1177 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1178 unsigned EltAlign = 0;
1179 getMaxByValAlign(STy->getElementType(i), EltAlign);
1180 if (EltAlign > MaxAlign)
1181 MaxAlign = EltAlign;
1189 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1190 /// function arguments in the caller parameter area. For X86, aggregates
1191 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1192 /// are at 4-byte boundaries.
1193 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1194 if (Subtarget->is64Bit()) {
1195 // Max of 8 and alignment of type.
1196 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1203 if (Subtarget->hasXMM())
1204 getMaxByValAlign(Ty, Align);
1208 /// getOptimalMemOpType - Returns the target specific optimal type for load
1209 /// and store operations as a result of memset, memcpy, and memmove
1210 /// lowering. If DstAlign is zero that means it's safe to destination
1211 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1212 /// means there isn't a need to check it against alignment requirement,
1213 /// probably because the source does not need to be loaded. If
1214 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1215 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1216 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1217 /// constant so it does not need to be loaded.
1218 /// It returns EVT::Other if the type should be determined using generic
1219 /// target-independent logic.
1221 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1222 unsigned DstAlign, unsigned SrcAlign,
1223 bool NonScalarIntSafe,
1225 MachineFunction &MF) const {
1226 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1227 // linux. This is because the stack realignment code can't handle certain
1228 // cases like PR2962. This should be removed when PR2962 is fixed.
1229 const Function *F = MF.getFunction();
1230 if (NonScalarIntSafe &&
1231 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1233 (Subtarget->isUnalignedMemAccessFast() ||
1234 ((DstAlign == 0 || DstAlign >= 16) &&
1235 (SrcAlign == 0 || SrcAlign >= 16))) &&
1236 Subtarget->getStackAlignment() >= 16) {
1237 if (Subtarget->hasSSE2())
1239 if (Subtarget->hasSSE1())
1241 } else if (!MemcpyStrSrc && Size >= 8 &&
1242 !Subtarget->is64Bit() &&
1243 Subtarget->getStackAlignment() >= 8 &&
1244 Subtarget->hasXMMInt()) {
1245 // Do not use f64 to lower memcpy if source is string constant. It's
1246 // better to use i32 to avoid the loads.
1250 if (Subtarget->is64Bit() && Size >= 8)
1255 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1256 /// current function. The returned value is a member of the
1257 /// MachineJumpTableInfo::JTEntryKind enum.
1258 unsigned X86TargetLowering::getJumpTableEncoding() const {
1259 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1261 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1262 Subtarget->isPICStyleGOT())
1263 return MachineJumpTableInfo::EK_Custom32;
1265 // Otherwise, use the normal jump table encoding heuristics.
1266 return TargetLowering::getJumpTableEncoding();
1270 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1271 const MachineBasicBlock *MBB,
1272 unsigned uid,MCContext &Ctx) const{
1273 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1274 Subtarget->isPICStyleGOT());
1275 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1277 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1278 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1281 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1283 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1284 SelectionDAG &DAG) const {
1285 if (!Subtarget->is64Bit())
1286 // This doesn't have DebugLoc associated with it, but is not really the
1287 // same as a Register.
1288 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1292 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1293 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1295 const MCExpr *X86TargetLowering::
1296 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1297 MCContext &Ctx) const {
1298 // X86-64 uses RIP relative addressing based on the jump table label.
1299 if (Subtarget->isPICStyleRIPRel())
1300 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1302 // Otherwise, the reference is relative to the PIC base.
1303 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1306 // FIXME: Why this routine is here? Move to RegInfo!
1307 std::pair<const TargetRegisterClass*, uint8_t>
1308 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1309 const TargetRegisterClass *RRC = 0;
1311 switch (VT.getSimpleVT().SimpleTy) {
1313 return TargetLowering::findRepresentativeClass(VT);
1314 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1315 RRC = (Subtarget->is64Bit()
1316 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1319 RRC = X86::VR64RegisterClass;
1321 case MVT::f32: case MVT::f64:
1322 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1323 case MVT::v4f32: case MVT::v2f64:
1324 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1326 RRC = X86::VR128RegisterClass;
1329 return std::make_pair(RRC, Cost);
1332 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1333 unsigned &Offset) const {
1334 if (!Subtarget->isTargetLinux())
1337 if (Subtarget->is64Bit()) {
1338 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1340 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1353 //===----------------------------------------------------------------------===//
1354 // Return Value Calling Convention Implementation
1355 //===----------------------------------------------------------------------===//
1357 #include "X86GenCallingConv.inc"
1360 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1361 MachineFunction &MF, bool isVarArg,
1362 const SmallVectorImpl<ISD::OutputArg> &Outs,
1363 LLVMContext &Context) const {
1364 SmallVector<CCValAssign, 16> RVLocs;
1365 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1367 return CCInfo.CheckReturn(Outs, RetCC_X86);
1371 X86TargetLowering::LowerReturn(SDValue Chain,
1372 CallingConv::ID CallConv, bool isVarArg,
1373 const SmallVectorImpl<ISD::OutputArg> &Outs,
1374 const SmallVectorImpl<SDValue> &OutVals,
1375 DebugLoc dl, SelectionDAG &DAG) const {
1376 MachineFunction &MF = DAG.getMachineFunction();
1377 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1379 SmallVector<CCValAssign, 16> RVLocs;
1380 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1381 RVLocs, *DAG.getContext());
1382 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1384 // Add the regs to the liveout set for the function.
1385 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1386 for (unsigned i = 0; i != RVLocs.size(); ++i)
1387 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1388 MRI.addLiveOut(RVLocs[i].getLocReg());
1392 SmallVector<SDValue, 6> RetOps;
1393 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1394 // Operand #1 = Bytes To Pop
1395 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1398 // Copy the result values into the output registers.
1399 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1400 CCValAssign &VA = RVLocs[i];
1401 assert(VA.isRegLoc() && "Can only return in registers!");
1402 SDValue ValToCopy = OutVals[i];
1403 EVT ValVT = ValToCopy.getValueType();
1405 // If this is x86-64, and we disabled SSE, we can't return FP values,
1406 // or SSE or MMX vectors.
1407 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1408 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1409 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1410 report_fatal_error("SSE register return with SSE disabled");
1412 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1413 // llvm-gcc has never done it right and no one has noticed, so this
1414 // should be OK for now.
1415 if (ValVT == MVT::f64 &&
1416 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1417 report_fatal_error("SSE2 register return with SSE2 disabled");
1419 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1420 // the RET instruction and handled by the FP Stackifier.
1421 if (VA.getLocReg() == X86::ST0 ||
1422 VA.getLocReg() == X86::ST1) {
1423 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1424 // change the value to the FP stack register class.
1425 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1426 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1427 RetOps.push_back(ValToCopy);
1428 // Don't emit a copytoreg.
1432 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1433 // which is returned in RAX / RDX.
1434 if (Subtarget->is64Bit()) {
1435 if (ValVT == MVT::x86mmx) {
1436 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1437 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1438 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1440 // If we don't have SSE2 available, convert to v4f32 so the generated
1441 // register is legal.
1442 if (!Subtarget->hasSSE2())
1443 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1448 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1449 Flag = Chain.getValue(1);
1452 // The x86-64 ABI for returning structs by value requires that we copy
1453 // the sret argument into %rax for the return. We saved the argument into
1454 // a virtual register in the entry block, so now we copy the value out
1456 if (Subtarget->is64Bit() &&
1457 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1458 MachineFunction &MF = DAG.getMachineFunction();
1459 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1460 unsigned Reg = FuncInfo->getSRetReturnReg();
1462 "SRetReturnReg should have been set in LowerFormalArguments().");
1463 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1465 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1466 Flag = Chain.getValue(1);
1468 // RAX now acts like a return value.
1469 MRI.addLiveOut(X86::RAX);
1472 RetOps[0] = Chain; // Update chain.
1474 // Add the flag if we have it.
1476 RetOps.push_back(Flag);
1478 return DAG.getNode(X86ISD::RET_FLAG, dl,
1479 MVT::Other, &RetOps[0], RetOps.size());
1482 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1483 if (N->getNumValues() != 1)
1485 if (!N->hasNUsesOfValue(1, 0))
1488 SDNode *Copy = *N->use_begin();
1489 if (Copy->getOpcode() != ISD::CopyToReg &&
1490 Copy->getOpcode() != ISD::FP_EXTEND)
1493 bool HasRet = false;
1494 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1496 if (UI->getOpcode() != X86ISD::RET_FLAG)
1505 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1506 ISD::NodeType ExtendKind) const {
1508 // TODO: Is this also valid on 32-bit?
1509 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1510 ReturnMVT = MVT::i8;
1512 ReturnMVT = MVT::i32;
1514 EVT MinVT = getRegisterType(Context, ReturnMVT);
1515 return VT.bitsLT(MinVT) ? MinVT : VT;
1518 /// LowerCallResult - Lower the result values of a call into the
1519 /// appropriate copies out of appropriate physical registers.
1522 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1523 CallingConv::ID CallConv, bool isVarArg,
1524 const SmallVectorImpl<ISD::InputArg> &Ins,
1525 DebugLoc dl, SelectionDAG &DAG,
1526 SmallVectorImpl<SDValue> &InVals) const {
1528 // Assign locations to each value returned by this call.
1529 SmallVector<CCValAssign, 16> RVLocs;
1530 bool Is64Bit = Subtarget->is64Bit();
1531 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1532 getTargetMachine(), RVLocs, *DAG.getContext());
1533 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1535 // Copy all of the result registers out of their specified physreg.
1536 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1537 CCValAssign &VA = RVLocs[i];
1538 EVT CopyVT = VA.getValVT();
1540 // If this is x86-64, and we disabled SSE, we can't return FP values
1541 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1542 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1543 report_fatal_error("SSE register return with SSE disabled");
1548 // If this is a call to a function that returns an fp value on the floating
1549 // point stack, we must guarantee the the value is popped from the stack, so
1550 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1551 // if the return value is not used. We use the FpPOP_RETVAL instruction
1553 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1554 // If we prefer to use the value in xmm registers, copy it out as f80 and
1555 // use a truncate to move it from fp stack reg to xmm reg.
1556 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1557 SDValue Ops[] = { Chain, InFlag };
1558 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1559 MVT::Other, MVT::Glue, Ops, 2), 1);
1560 Val = Chain.getValue(0);
1562 // Round the f80 to the right size, which also moves it to the appropriate
1564 if (CopyVT != VA.getValVT())
1565 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1566 // This truncation won't change the value.
1567 DAG.getIntPtrConstant(1));
1569 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1570 CopyVT, InFlag).getValue(1);
1571 Val = Chain.getValue(0);
1573 InFlag = Chain.getValue(2);
1574 InVals.push_back(Val);
1581 //===----------------------------------------------------------------------===//
1582 // C & StdCall & Fast Calling Convention implementation
1583 //===----------------------------------------------------------------------===//
1584 // StdCall calling convention seems to be standard for many Windows' API
1585 // routines and around. It differs from C calling convention just a little:
1586 // callee should clean up the stack, not caller. Symbols should be also
1587 // decorated in some fancy way :) It doesn't support any vector arguments.
1588 // For info on fast calling convention see Fast Calling Convention (tail call)
1589 // implementation LowerX86_32FastCCCallTo.
1591 /// CallIsStructReturn - Determines whether a call uses struct return
1593 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1597 return Outs[0].Flags.isSRet();
1600 /// ArgsAreStructReturn - Determines whether a function uses struct
1601 /// return semantics.
1603 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1607 return Ins[0].Flags.isSRet();
1610 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1611 /// by "Src" to address "Dst" with size and alignment information specified by
1612 /// the specific parameter attribute. The copy will be passed as a byval
1613 /// function parameter.
1615 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1616 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1618 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1620 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1621 /*isVolatile*/false, /*AlwaysInline=*/true,
1622 MachinePointerInfo(), MachinePointerInfo());
1625 /// IsTailCallConvention - Return true if the calling convention is one that
1626 /// supports tail call optimization.
1627 static bool IsTailCallConvention(CallingConv::ID CC) {
1628 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1631 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1632 if (!CI->isTailCall())
1636 CallingConv::ID CalleeCC = CS.getCallingConv();
1637 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1643 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1644 /// a tailcall target by changing its ABI.
1645 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1646 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1650 X86TargetLowering::LowerMemArgument(SDValue Chain,
1651 CallingConv::ID CallConv,
1652 const SmallVectorImpl<ISD::InputArg> &Ins,
1653 DebugLoc dl, SelectionDAG &DAG,
1654 const CCValAssign &VA,
1655 MachineFrameInfo *MFI,
1657 // Create the nodes corresponding to a load from this parameter slot.
1658 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1659 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1660 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1663 // If value is passed by pointer we have address passed instead of the value
1665 if (VA.getLocInfo() == CCValAssign::Indirect)
1666 ValVT = VA.getLocVT();
1668 ValVT = VA.getValVT();
1670 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1671 // changed with more analysis.
1672 // In case of tail call optimization mark all arguments mutable. Since they
1673 // could be overwritten by lowering of arguments in case of a tail call.
1674 if (Flags.isByVal()) {
1675 unsigned Bytes = Flags.getByValSize();
1676 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1677 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1678 return DAG.getFrameIndex(FI, getPointerTy());
1680 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1681 VA.getLocMemOffset(), isImmutable);
1682 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1683 return DAG.getLoad(ValVT, dl, Chain, FIN,
1684 MachinePointerInfo::getFixedStack(FI),
1690 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1691 CallingConv::ID CallConv,
1693 const SmallVectorImpl<ISD::InputArg> &Ins,
1696 SmallVectorImpl<SDValue> &InVals)
1698 MachineFunction &MF = DAG.getMachineFunction();
1699 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1701 const Function* Fn = MF.getFunction();
1702 if (Fn->hasExternalLinkage() &&
1703 Subtarget->isTargetCygMing() &&
1704 Fn->getName() == "main")
1705 FuncInfo->setForceFramePointer(true);
1707 MachineFrameInfo *MFI = MF.getFrameInfo();
1708 bool Is64Bit = Subtarget->is64Bit();
1709 bool IsWin64 = Subtarget->isTargetWin64();
1711 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1712 "Var args not supported with calling convention fastcc or ghc");
1714 // Assign locations to all of the incoming arguments.
1715 SmallVector<CCValAssign, 16> ArgLocs;
1716 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1717 ArgLocs, *DAG.getContext());
1719 // Allocate shadow area for Win64
1721 CCInfo.AllocateStack(32, 8);
1724 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1726 unsigned LastVal = ~0U;
1728 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1729 CCValAssign &VA = ArgLocs[i];
1730 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1732 assert(VA.getValNo() != LastVal &&
1733 "Don't support value assigned to multiple locs yet");
1734 LastVal = VA.getValNo();
1736 if (VA.isRegLoc()) {
1737 EVT RegVT = VA.getLocVT();
1738 TargetRegisterClass *RC = NULL;
1739 if (RegVT == MVT::i32)
1740 RC = X86::GR32RegisterClass;
1741 else if (Is64Bit && RegVT == MVT::i64)
1742 RC = X86::GR64RegisterClass;
1743 else if (RegVT == MVT::f32)
1744 RC = X86::FR32RegisterClass;
1745 else if (RegVT == MVT::f64)
1746 RC = X86::FR64RegisterClass;
1747 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1748 RC = X86::VR256RegisterClass;
1749 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1750 RC = X86::VR128RegisterClass;
1751 else if (RegVT == MVT::x86mmx)
1752 RC = X86::VR64RegisterClass;
1754 llvm_unreachable("Unknown argument type!");
1756 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1757 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1759 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1760 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1762 if (VA.getLocInfo() == CCValAssign::SExt)
1763 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1764 DAG.getValueType(VA.getValVT()));
1765 else if (VA.getLocInfo() == CCValAssign::ZExt)
1766 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1767 DAG.getValueType(VA.getValVT()));
1768 else if (VA.getLocInfo() == CCValAssign::BCvt)
1769 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1771 if (VA.isExtInLoc()) {
1772 // Handle MMX values passed in XMM regs.
1773 if (RegVT.isVector()) {
1774 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1777 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1780 assert(VA.isMemLoc());
1781 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1784 // If value is passed via pointer - do a load.
1785 if (VA.getLocInfo() == CCValAssign::Indirect)
1786 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1787 MachinePointerInfo(), false, false, 0);
1789 InVals.push_back(ArgValue);
1792 // The x86-64 ABI for returning structs by value requires that we copy
1793 // the sret argument into %rax for the return. Save the argument into
1794 // a virtual register so that we can access it from the return points.
1795 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1796 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1797 unsigned Reg = FuncInfo->getSRetReturnReg();
1799 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1800 FuncInfo->setSRetReturnReg(Reg);
1802 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1803 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1806 unsigned StackSize = CCInfo.getNextStackOffset();
1807 // Align stack specially for tail calls.
1808 if (FuncIsMadeTailCallSafe(CallConv))
1809 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1811 // If the function takes variable number of arguments, make a frame index for
1812 // the start of the first vararg value... for expansion of llvm.va_start.
1814 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1815 CallConv != CallingConv::X86_ThisCall)) {
1816 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1819 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1821 // FIXME: We should really autogenerate these arrays
1822 static const unsigned GPR64ArgRegsWin64[] = {
1823 X86::RCX, X86::RDX, X86::R8, X86::R9
1825 static const unsigned GPR64ArgRegs64Bit[] = {
1826 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1828 static const unsigned XMMArgRegs64Bit[] = {
1829 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1830 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1832 const unsigned *GPR64ArgRegs;
1833 unsigned NumXMMRegs = 0;
1836 // The XMM registers which might contain var arg parameters are shadowed
1837 // in their paired GPR. So we only need to save the GPR to their home
1839 TotalNumIntRegs = 4;
1840 GPR64ArgRegs = GPR64ArgRegsWin64;
1842 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1843 GPR64ArgRegs = GPR64ArgRegs64Bit;
1845 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1847 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1850 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1851 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1852 "SSE register cannot be used when SSE is disabled!");
1853 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1854 "SSE register cannot be used when SSE is disabled!");
1855 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1856 // Kernel mode asks for SSE to be disabled, so don't push them
1858 TotalNumXMMRegs = 0;
1861 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1862 // Get to the caller-allocated home save location. Add 8 to account
1863 // for the return address.
1864 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1865 FuncInfo->setRegSaveFrameIndex(
1866 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1867 // Fixup to set vararg frame on shadow area (4 x i64).
1869 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1871 // For X86-64, if there are vararg parameters that are passed via
1872 // registers, then we must store them to their spots on the stack so they
1873 // may be loaded by deferencing the result of va_next.
1874 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1875 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1876 FuncInfo->setRegSaveFrameIndex(
1877 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1881 // Store the integer parameter registers.
1882 SmallVector<SDValue, 8> MemOps;
1883 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1885 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1886 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1887 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1888 DAG.getIntPtrConstant(Offset));
1889 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1890 X86::GR64RegisterClass);
1891 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1893 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1894 MachinePointerInfo::getFixedStack(
1895 FuncInfo->getRegSaveFrameIndex(), Offset),
1897 MemOps.push_back(Store);
1901 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1902 // Now store the XMM (fp + vector) parameter registers.
1903 SmallVector<SDValue, 11> SaveXMMOps;
1904 SaveXMMOps.push_back(Chain);
1906 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1907 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1908 SaveXMMOps.push_back(ALVal);
1910 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1911 FuncInfo->getRegSaveFrameIndex()));
1912 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1913 FuncInfo->getVarArgsFPOffset()));
1915 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1916 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1917 X86::VR128RegisterClass);
1918 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1919 SaveXMMOps.push_back(Val);
1921 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1923 &SaveXMMOps[0], SaveXMMOps.size()));
1926 if (!MemOps.empty())
1927 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1928 &MemOps[0], MemOps.size());
1932 // Some CCs need callee pop.
1933 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1934 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1936 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1937 // If this is an sret function, the return should pop the hidden pointer.
1938 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1939 FuncInfo->setBytesToPopOnReturn(4);
1943 // RegSaveFrameIndex is X86-64 only.
1944 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1945 if (CallConv == CallingConv::X86_FastCall ||
1946 CallConv == CallingConv::X86_ThisCall)
1947 // fastcc functions can't have varargs.
1948 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1951 FuncInfo->setArgumentStackSize(StackSize);
1957 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1958 SDValue StackPtr, SDValue Arg,
1959 DebugLoc dl, SelectionDAG &DAG,
1960 const CCValAssign &VA,
1961 ISD::ArgFlagsTy Flags) const {
1962 unsigned LocMemOffset = VA.getLocMemOffset();
1963 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1964 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1965 if (Flags.isByVal())
1966 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1968 return DAG.getStore(Chain, dl, Arg, PtrOff,
1969 MachinePointerInfo::getStack(LocMemOffset),
1973 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1974 /// optimization is performed and it is required.
1976 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1977 SDValue &OutRetAddr, SDValue Chain,
1978 bool IsTailCall, bool Is64Bit,
1979 int FPDiff, DebugLoc dl) const {
1980 // Adjust the Return address stack slot.
1981 EVT VT = getPointerTy();
1982 OutRetAddr = getReturnAddressFrameIndex(DAG);
1984 // Load the "old" Return address.
1985 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1987 return SDValue(OutRetAddr.getNode(), 1);
1990 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1991 /// optimization is performed and it is required (FPDiff!=0).
1993 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1994 SDValue Chain, SDValue RetAddrFrIdx,
1995 bool Is64Bit, int FPDiff, DebugLoc dl) {
1996 // Store the return address to the appropriate stack slot.
1997 if (!FPDiff) return Chain;
1998 // Calculate the new stack slot for the return address.
1999 int SlotSize = Is64Bit ? 8 : 4;
2000 int NewReturnAddrFI =
2001 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2002 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2003 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2004 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2005 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2011 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2012 CallingConv::ID CallConv, bool isVarArg,
2014 const SmallVectorImpl<ISD::OutputArg> &Outs,
2015 const SmallVectorImpl<SDValue> &OutVals,
2016 const SmallVectorImpl<ISD::InputArg> &Ins,
2017 DebugLoc dl, SelectionDAG &DAG,
2018 SmallVectorImpl<SDValue> &InVals) const {
2019 MachineFunction &MF = DAG.getMachineFunction();
2020 bool Is64Bit = Subtarget->is64Bit();
2021 bool IsWin64 = Subtarget->isTargetWin64();
2022 bool IsStructRet = CallIsStructReturn(Outs);
2023 bool IsSibcall = false;
2026 // Check if it's really possible to do a tail call.
2027 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2028 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2029 Outs, OutVals, Ins, DAG);
2031 // Sibcalls are automatically detected tailcalls which do not require
2033 if (!GuaranteedTailCallOpt && isTailCall)
2040 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2041 "Var args not supported with calling convention fastcc or ghc");
2043 // Analyze operands of the call, assigning locations to each operand.
2044 SmallVector<CCValAssign, 16> ArgLocs;
2045 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2046 ArgLocs, *DAG.getContext());
2048 // Allocate shadow area for Win64
2050 CCInfo.AllocateStack(32, 8);
2053 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2055 // Get a count of how many bytes are to be pushed on the stack.
2056 unsigned NumBytes = CCInfo.getNextStackOffset();
2058 // This is a sibcall. The memory operands are available in caller's
2059 // own caller's stack.
2061 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2062 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2065 if (isTailCall && !IsSibcall) {
2066 // Lower arguments at fp - stackoffset + fpdiff.
2067 unsigned NumBytesCallerPushed =
2068 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2069 FPDiff = NumBytesCallerPushed - NumBytes;
2071 // Set the delta of movement of the returnaddr stackslot.
2072 // But only set if delta is greater than previous delta.
2073 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2074 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2078 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2080 SDValue RetAddrFrIdx;
2081 // Load return address for tail calls.
2082 if (isTailCall && FPDiff)
2083 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2084 Is64Bit, FPDiff, dl);
2086 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2087 SmallVector<SDValue, 8> MemOpChains;
2090 // Walk the register/memloc assignments, inserting copies/loads. In the case
2091 // of tail call optimization arguments are handle later.
2092 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2093 CCValAssign &VA = ArgLocs[i];
2094 EVT RegVT = VA.getLocVT();
2095 SDValue Arg = OutVals[i];
2096 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2097 bool isByVal = Flags.isByVal();
2099 // Promote the value if needed.
2100 switch (VA.getLocInfo()) {
2101 default: llvm_unreachable("Unknown loc info!");
2102 case CCValAssign::Full: break;
2103 case CCValAssign::SExt:
2104 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2106 case CCValAssign::ZExt:
2107 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2109 case CCValAssign::AExt:
2110 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2111 // Special case: passing MMX values in XMM registers.
2112 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2113 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2114 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2116 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2118 case CCValAssign::BCvt:
2119 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2121 case CCValAssign::Indirect: {
2122 // Store the argument.
2123 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2124 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2125 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2126 MachinePointerInfo::getFixedStack(FI),
2133 if (VA.isRegLoc()) {
2134 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2135 if (isVarArg && IsWin64) {
2136 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2137 // shadow reg if callee is a varargs function.
2138 unsigned ShadowReg = 0;
2139 switch (VA.getLocReg()) {
2140 case X86::XMM0: ShadowReg = X86::RCX; break;
2141 case X86::XMM1: ShadowReg = X86::RDX; break;
2142 case X86::XMM2: ShadowReg = X86::R8; break;
2143 case X86::XMM3: ShadowReg = X86::R9; break;
2146 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2148 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2149 assert(VA.isMemLoc());
2150 if (StackPtr.getNode() == 0)
2151 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2152 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2153 dl, DAG, VA, Flags));
2157 if (!MemOpChains.empty())
2158 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2159 &MemOpChains[0], MemOpChains.size());
2161 // Build a sequence of copy-to-reg nodes chained together with token chain
2162 // and flag operands which copy the outgoing args into registers.
2164 // Tail call byval lowering might overwrite argument registers so in case of
2165 // tail call optimization the copies to registers are lowered later.
2167 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2168 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2169 RegsToPass[i].second, InFlag);
2170 InFlag = Chain.getValue(1);
2173 if (Subtarget->isPICStyleGOT()) {
2174 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2177 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2178 DAG.getNode(X86ISD::GlobalBaseReg,
2179 DebugLoc(), getPointerTy()),
2181 InFlag = Chain.getValue(1);
2183 // If we are tail calling and generating PIC/GOT style code load the
2184 // address of the callee into ECX. The value in ecx is used as target of
2185 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2186 // for tail calls on PIC/GOT architectures. Normally we would just put the
2187 // address of GOT into ebx and then call target@PLT. But for tail calls
2188 // ebx would be restored (since ebx is callee saved) before jumping to the
2191 // Note: The actual moving to ECX is done further down.
2192 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2193 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2194 !G->getGlobal()->hasProtectedVisibility())
2195 Callee = LowerGlobalAddress(Callee, DAG);
2196 else if (isa<ExternalSymbolSDNode>(Callee))
2197 Callee = LowerExternalSymbol(Callee, DAG);
2201 if (Is64Bit && isVarArg && !IsWin64) {
2202 // From AMD64 ABI document:
2203 // For calls that may call functions that use varargs or stdargs
2204 // (prototype-less calls or calls to functions containing ellipsis (...) in
2205 // the declaration) %al is used as hidden argument to specify the number
2206 // of SSE registers used. The contents of %al do not need to match exactly
2207 // the number of registers, but must be an ubound on the number of SSE
2208 // registers used and is in the range 0 - 8 inclusive.
2210 // Count the number of XMM registers allocated.
2211 static const unsigned XMMArgRegs[] = {
2212 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2213 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2215 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2216 assert((Subtarget->hasXMM() || !NumXMMRegs)
2217 && "SSE registers cannot be used when SSE is disabled");
2219 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2220 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2221 InFlag = Chain.getValue(1);
2225 // For tail calls lower the arguments to the 'real' stack slot.
2227 // Force all the incoming stack arguments to be loaded from the stack
2228 // before any new outgoing arguments are stored to the stack, because the
2229 // outgoing stack slots may alias the incoming argument stack slots, and
2230 // the alias isn't otherwise explicit. This is slightly more conservative
2231 // than necessary, because it means that each store effectively depends
2232 // on every argument instead of just those arguments it would clobber.
2233 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2235 SmallVector<SDValue, 8> MemOpChains2;
2238 // Do not flag preceding copytoreg stuff together with the following stuff.
2240 if (GuaranteedTailCallOpt) {
2241 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2242 CCValAssign &VA = ArgLocs[i];
2245 assert(VA.isMemLoc());
2246 SDValue Arg = OutVals[i];
2247 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2248 // Create frame index.
2249 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2250 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2251 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2252 FIN = DAG.getFrameIndex(FI, getPointerTy());
2254 if (Flags.isByVal()) {
2255 // Copy relative to framepointer.
2256 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2257 if (StackPtr.getNode() == 0)
2258 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2260 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2262 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2266 // Store relative to framepointer.
2267 MemOpChains2.push_back(
2268 DAG.getStore(ArgChain, dl, Arg, FIN,
2269 MachinePointerInfo::getFixedStack(FI),
2275 if (!MemOpChains2.empty())
2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2277 &MemOpChains2[0], MemOpChains2.size());
2279 // Copy arguments to their registers.
2280 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2281 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2282 RegsToPass[i].second, InFlag);
2283 InFlag = Chain.getValue(1);
2287 // Store the return address to the appropriate stack slot.
2288 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2292 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2293 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2294 // In the 64-bit large code model, we have to make all calls
2295 // through a register, since the call instruction's 32-bit
2296 // pc-relative offset may not be large enough to hold the whole
2298 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2299 // If the callee is a GlobalAddress node (quite common, every direct call
2300 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2303 // We should use extra load for direct calls to dllimported functions in
2305 const GlobalValue *GV = G->getGlobal();
2306 if (!GV->hasDLLImportLinkage()) {
2307 unsigned char OpFlags = 0;
2308 bool ExtraLoad = false;
2309 unsigned WrapperKind = ISD::DELETED_NODE;
2311 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2312 // external symbols most go through the PLT in PIC mode. If the symbol
2313 // has hidden or protected visibility, or if it is static or local, then
2314 // we don't need to use the PLT - we can directly call it.
2315 if (Subtarget->isTargetELF() &&
2316 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2317 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2318 OpFlags = X86II::MO_PLT;
2319 } else if (Subtarget->isPICStyleStubAny() &&
2320 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2321 (!Subtarget->getTargetTriple().isMacOSX() ||
2322 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2323 // PC-relative references to external symbols should go through $stub,
2324 // unless we're building with the leopard linker or later, which
2325 // automatically synthesizes these stubs.
2326 OpFlags = X86II::MO_DARWIN_STUB;
2327 } else if (Subtarget->isPICStyleRIPRel() &&
2328 isa<Function>(GV) &&
2329 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2330 // If the function is marked as non-lazy, generate an indirect call
2331 // which loads from the GOT directly. This avoids runtime overhead
2332 // at the cost of eager binding (and one extra byte of encoding).
2333 OpFlags = X86II::MO_GOTPCREL;
2334 WrapperKind = X86ISD::WrapperRIP;
2338 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2339 G->getOffset(), OpFlags);
2341 // Add a wrapper if needed.
2342 if (WrapperKind != ISD::DELETED_NODE)
2343 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2344 // Add extra indirection if needed.
2346 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2347 MachinePointerInfo::getGOT(),
2350 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2351 unsigned char OpFlags = 0;
2353 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2354 // external symbols should go through the PLT.
2355 if (Subtarget->isTargetELF() &&
2356 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2357 OpFlags = X86II::MO_PLT;
2358 } else if (Subtarget->isPICStyleStubAny() &&
2359 (!Subtarget->getTargetTriple().isMacOSX() ||
2360 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2361 // PC-relative references to external symbols should go through $stub,
2362 // unless we're building with the leopard linker or later, which
2363 // automatically synthesizes these stubs.
2364 OpFlags = X86II::MO_DARWIN_STUB;
2367 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2371 // Returns a chain & a flag for retval copy to use.
2372 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2373 SmallVector<SDValue, 8> Ops;
2375 if (!IsSibcall && isTailCall) {
2376 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2377 DAG.getIntPtrConstant(0, true), InFlag);
2378 InFlag = Chain.getValue(1);
2381 Ops.push_back(Chain);
2382 Ops.push_back(Callee);
2385 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2387 // Add argument registers to the end of the list so that they are known live
2389 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2390 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2391 RegsToPass[i].second.getValueType()));
2393 // Add an implicit use GOT pointer in EBX.
2394 if (!isTailCall && Subtarget->isPICStyleGOT())
2395 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2397 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2398 if (Is64Bit && isVarArg && !IsWin64)
2399 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2401 if (InFlag.getNode())
2402 Ops.push_back(InFlag);
2406 //// If this is the first return lowered for this function, add the regs
2407 //// to the liveout set for the function.
2408 // This isn't right, although it's probably harmless on x86; liveouts
2409 // should be computed from returns not tail calls. Consider a void
2410 // function making a tail call to a function returning int.
2411 return DAG.getNode(X86ISD::TC_RETURN, dl,
2412 NodeTys, &Ops[0], Ops.size());
2415 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2416 InFlag = Chain.getValue(1);
2418 // Create the CALLSEQ_END node.
2419 unsigned NumBytesForCalleeToPush;
2420 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2421 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2422 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2423 // If this is a call to a struct-return function, the callee
2424 // pops the hidden struct pointer, so we have to push it back.
2425 // This is common for Darwin/X86, Linux & Mingw32 targets.
2426 NumBytesForCalleeToPush = 4;
2428 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2430 // Returns a flag for retval copy to use.
2432 Chain = DAG.getCALLSEQ_END(Chain,
2433 DAG.getIntPtrConstant(NumBytes, true),
2434 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2437 InFlag = Chain.getValue(1);
2440 // Handle result values, copying them out of physregs into vregs that we
2442 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2443 Ins, dl, DAG, InVals);
2447 //===----------------------------------------------------------------------===//
2448 // Fast Calling Convention (tail call) implementation
2449 //===----------------------------------------------------------------------===//
2451 // Like std call, callee cleans arguments, convention except that ECX is
2452 // reserved for storing the tail called function address. Only 2 registers are
2453 // free for argument passing (inreg). Tail call optimization is performed
2455 // * tailcallopt is enabled
2456 // * caller/callee are fastcc
2457 // On X86_64 architecture with GOT-style position independent code only local
2458 // (within module) calls are supported at the moment.
2459 // To keep the stack aligned according to platform abi the function
2460 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2461 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2462 // If a tail called function callee has more arguments than the caller the
2463 // caller needs to make sure that there is room to move the RETADDR to. This is
2464 // achieved by reserving an area the size of the argument delta right after the
2465 // original REtADDR, but before the saved framepointer or the spilled registers
2466 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2478 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2479 /// for a 16 byte align requirement.
2481 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2482 SelectionDAG& DAG) const {
2483 MachineFunction &MF = DAG.getMachineFunction();
2484 const TargetMachine &TM = MF.getTarget();
2485 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2486 unsigned StackAlignment = TFI.getStackAlignment();
2487 uint64_t AlignMask = StackAlignment - 1;
2488 int64_t Offset = StackSize;
2489 uint64_t SlotSize = TD->getPointerSize();
2490 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2491 // Number smaller than 12 so just add the difference.
2492 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2494 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2495 Offset = ((~AlignMask) & Offset) + StackAlignment +
2496 (StackAlignment-SlotSize);
2501 /// MatchingStackOffset - Return true if the given stack call argument is
2502 /// already available in the same position (relatively) of the caller's
2503 /// incoming argument stack.
2505 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2506 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2507 const X86InstrInfo *TII) {
2508 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2510 if (Arg.getOpcode() == ISD::CopyFromReg) {
2511 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2512 if (!TargetRegisterInfo::isVirtualRegister(VR))
2514 MachineInstr *Def = MRI->getVRegDef(VR);
2517 if (!Flags.isByVal()) {
2518 if (!TII->isLoadFromStackSlot(Def, FI))
2521 unsigned Opcode = Def->getOpcode();
2522 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2523 Def->getOperand(1).isFI()) {
2524 FI = Def->getOperand(1).getIndex();
2525 Bytes = Flags.getByValSize();
2529 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2530 if (Flags.isByVal())
2531 // ByVal argument is passed in as a pointer but it's now being
2532 // dereferenced. e.g.
2533 // define @foo(%struct.X* %A) {
2534 // tail call @bar(%struct.X* byval %A)
2537 SDValue Ptr = Ld->getBasePtr();
2538 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2541 FI = FINode->getIndex();
2542 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2543 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2544 FI = FINode->getIndex();
2545 Bytes = Flags.getByValSize();
2549 assert(FI != INT_MAX);
2550 if (!MFI->isFixedObjectIndex(FI))
2552 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2555 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2556 /// for tail call optimization. Targets which want to do tail call
2557 /// optimization should implement this function.
2559 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2560 CallingConv::ID CalleeCC,
2562 bool isCalleeStructRet,
2563 bool isCallerStructRet,
2564 const SmallVectorImpl<ISD::OutputArg> &Outs,
2565 const SmallVectorImpl<SDValue> &OutVals,
2566 const SmallVectorImpl<ISD::InputArg> &Ins,
2567 SelectionDAG& DAG) const {
2568 if (!IsTailCallConvention(CalleeCC) &&
2569 CalleeCC != CallingConv::C)
2572 // If -tailcallopt is specified, make fastcc functions tail-callable.
2573 const MachineFunction &MF = DAG.getMachineFunction();
2574 const Function *CallerF = DAG.getMachineFunction().getFunction();
2575 CallingConv::ID CallerCC = CallerF->getCallingConv();
2576 bool CCMatch = CallerCC == CalleeCC;
2578 if (GuaranteedTailCallOpt) {
2579 if (IsTailCallConvention(CalleeCC) && CCMatch)
2584 // Look for obvious safe cases to perform tail call optimization that do not
2585 // require ABI changes. This is what gcc calls sibcall.
2587 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2588 // emit a special epilogue.
2589 if (RegInfo->needsStackRealignment(MF))
2592 // Also avoid sibcall optimization if either caller or callee uses struct
2593 // return semantics.
2594 if (isCalleeStructRet || isCallerStructRet)
2597 // An stdcall caller is expected to clean up its arguments; the callee
2598 // isn't going to do that.
2599 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2602 // Do not sibcall optimize vararg calls unless all arguments are passed via
2604 if (isVarArg && !Outs.empty()) {
2606 // Optimizing for varargs on Win64 is unlikely to be safe without
2607 // additional testing.
2608 if (Subtarget->isTargetWin64())
2611 SmallVector<CCValAssign, 16> ArgLocs;
2612 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2613 getTargetMachine(), ArgLocs, *DAG.getContext());
2615 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2616 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2617 if (!ArgLocs[i].isRegLoc())
2621 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2622 // Therefore if it's not used by the call it is not safe to optimize this into
2624 bool Unused = false;
2625 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2632 SmallVector<CCValAssign, 16> RVLocs;
2633 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2634 getTargetMachine(), RVLocs, *DAG.getContext());
2635 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2636 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2637 CCValAssign &VA = RVLocs[i];
2638 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2643 // If the calling conventions do not match, then we'd better make sure the
2644 // results are returned in the same way as what the caller expects.
2646 SmallVector<CCValAssign, 16> RVLocs1;
2647 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2648 getTargetMachine(), RVLocs1, *DAG.getContext());
2649 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2651 SmallVector<CCValAssign, 16> RVLocs2;
2652 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2653 getTargetMachine(), RVLocs2, *DAG.getContext());
2654 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2656 if (RVLocs1.size() != RVLocs2.size())
2658 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2659 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2661 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2663 if (RVLocs1[i].isRegLoc()) {
2664 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2667 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2673 // If the callee takes no arguments then go on to check the results of the
2675 if (!Outs.empty()) {
2676 // Check if stack adjustment is needed. For now, do not do this if any
2677 // argument is passed on the stack.
2678 SmallVector<CCValAssign, 16> ArgLocs;
2679 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2680 getTargetMachine(), ArgLocs, *DAG.getContext());
2682 // Allocate shadow area for Win64
2683 if (Subtarget->isTargetWin64()) {
2684 CCInfo.AllocateStack(32, 8);
2687 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2688 if (CCInfo.getNextStackOffset()) {
2689 MachineFunction &MF = DAG.getMachineFunction();
2690 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2693 // Check if the arguments are already laid out in the right way as
2694 // the caller's fixed stack objects.
2695 MachineFrameInfo *MFI = MF.getFrameInfo();
2696 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2697 const X86InstrInfo *TII =
2698 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2699 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2700 CCValAssign &VA = ArgLocs[i];
2701 SDValue Arg = OutVals[i];
2702 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2703 if (VA.getLocInfo() == CCValAssign::Indirect)
2705 if (!VA.isRegLoc()) {
2706 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2713 // If the tailcall address may be in a register, then make sure it's
2714 // possible to register allocate for it. In 32-bit, the call address can
2715 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2716 // callee-saved registers are restored. These happen to be the same
2717 // registers used to pass 'inreg' arguments so watch out for those.
2718 if (!Subtarget->is64Bit() &&
2719 !isa<GlobalAddressSDNode>(Callee) &&
2720 !isa<ExternalSymbolSDNode>(Callee)) {
2721 unsigned NumInRegs = 0;
2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2723 CCValAssign &VA = ArgLocs[i];
2726 unsigned Reg = VA.getLocReg();
2729 case X86::EAX: case X86::EDX: case X86::ECX:
2730 if (++NumInRegs == 3)
2742 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2743 return X86::createFastISel(funcInfo);
2747 //===----------------------------------------------------------------------===//
2748 // Other Lowering Hooks
2749 //===----------------------------------------------------------------------===//
2751 static bool MayFoldLoad(SDValue Op) {
2752 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2755 static bool MayFoldIntoStore(SDValue Op) {
2756 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2759 static bool isTargetShuffle(unsigned Opcode) {
2761 default: return false;
2762 case X86ISD::PSHUFD:
2763 case X86ISD::PSHUFHW:
2764 case X86ISD::PSHUFLW:
2765 case X86ISD::SHUFPD:
2766 case X86ISD::PALIGN:
2767 case X86ISD::SHUFPS:
2768 case X86ISD::MOVLHPS:
2769 case X86ISD::MOVLHPD:
2770 case X86ISD::MOVHLPS:
2771 case X86ISD::MOVLPS:
2772 case X86ISD::MOVLPD:
2773 case X86ISD::MOVSHDUP:
2774 case X86ISD::MOVSLDUP:
2775 case X86ISD::MOVDDUP:
2778 case X86ISD::UNPCKLPS:
2779 case X86ISD::UNPCKLPD:
2780 case X86ISD::VUNPCKLPSY:
2781 case X86ISD::VUNPCKLPDY:
2782 case X86ISD::PUNPCKLWD:
2783 case X86ISD::PUNPCKLBW:
2784 case X86ISD::PUNPCKLDQ:
2785 case X86ISD::PUNPCKLQDQ:
2786 case X86ISD::UNPCKHPS:
2787 case X86ISD::UNPCKHPD:
2788 case X86ISD::VUNPCKHPSY:
2789 case X86ISD::VUNPCKHPDY:
2790 case X86ISD::PUNPCKHWD:
2791 case X86ISD::PUNPCKHBW:
2792 case X86ISD::PUNPCKHDQ:
2793 case X86ISD::PUNPCKHQDQ:
2794 case X86ISD::VPERMILPS:
2795 case X86ISD::VPERMILPSY:
2796 case X86ISD::VPERMILPD:
2797 case X86ISD::VPERMILPDY:
2798 case X86ISD::VPERM2F128:
2804 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2805 SDValue V1, SelectionDAG &DAG) {
2807 default: llvm_unreachable("Unknown x86 shuffle node");
2808 case X86ISD::MOVSHDUP:
2809 case X86ISD::MOVSLDUP:
2810 case X86ISD::MOVDDUP:
2811 return DAG.getNode(Opc, dl, VT, V1);
2817 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2818 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2820 default: llvm_unreachable("Unknown x86 shuffle node");
2821 case X86ISD::PSHUFD:
2822 case X86ISD::PSHUFHW:
2823 case X86ISD::PSHUFLW:
2824 case X86ISD::VPERMILPS:
2825 case X86ISD::VPERMILPSY:
2826 case X86ISD::VPERMILPD:
2827 case X86ISD::VPERMILPDY:
2828 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2834 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2835 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2837 default: llvm_unreachable("Unknown x86 shuffle node");
2838 case X86ISD::PALIGN:
2839 case X86ISD::SHUFPD:
2840 case X86ISD::SHUFPS:
2841 case X86ISD::VPERM2F128:
2842 return DAG.getNode(Opc, dl, VT, V1, V2,
2843 DAG.getConstant(TargetMask, MVT::i8));
2848 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2849 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2851 default: llvm_unreachable("Unknown x86 shuffle node");
2852 case X86ISD::MOVLHPS:
2853 case X86ISD::MOVLHPD:
2854 case X86ISD::MOVHLPS:
2855 case X86ISD::MOVLPS:
2856 case X86ISD::MOVLPD:
2859 case X86ISD::UNPCKLPS:
2860 case X86ISD::UNPCKLPD:
2861 case X86ISD::VUNPCKLPSY:
2862 case X86ISD::VUNPCKLPDY:
2863 case X86ISD::PUNPCKLWD:
2864 case X86ISD::PUNPCKLBW:
2865 case X86ISD::PUNPCKLDQ:
2866 case X86ISD::PUNPCKLQDQ:
2867 case X86ISD::UNPCKHPS:
2868 case X86ISD::UNPCKHPD:
2869 case X86ISD::VUNPCKHPSY:
2870 case X86ISD::VUNPCKHPDY:
2871 case X86ISD::PUNPCKHWD:
2872 case X86ISD::PUNPCKHBW:
2873 case X86ISD::PUNPCKHDQ:
2874 case X86ISD::PUNPCKHQDQ:
2875 return DAG.getNode(Opc, dl, VT, V1, V2);
2880 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2881 MachineFunction &MF = DAG.getMachineFunction();
2882 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2883 int ReturnAddrIndex = FuncInfo->getRAIndex();
2885 if (ReturnAddrIndex == 0) {
2886 // Set up a frame object for the return address.
2887 uint64_t SlotSize = TD->getPointerSize();
2888 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2890 FuncInfo->setRAIndex(ReturnAddrIndex);
2893 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2897 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2898 bool hasSymbolicDisplacement) {
2899 // Offset should fit into 32 bit immediate field.
2900 if (!isInt<32>(Offset))
2903 // If we don't have a symbolic displacement - we don't have any extra
2905 if (!hasSymbolicDisplacement)
2908 // FIXME: Some tweaks might be needed for medium code model.
2909 if (M != CodeModel::Small && M != CodeModel::Kernel)
2912 // For small code model we assume that latest object is 16MB before end of 31
2913 // bits boundary. We may also accept pretty large negative constants knowing
2914 // that all objects are in the positive half of address space.
2915 if (M == CodeModel::Small && Offset < 16*1024*1024)
2918 // For kernel code model we know that all object resist in the negative half
2919 // of 32bits address space. We may not accept negative offsets, since they may
2920 // be just off and we may accept pretty large positive ones.
2921 if (M == CodeModel::Kernel && Offset > 0)
2927 /// isCalleePop - Determines whether the callee is required to pop its
2928 /// own arguments. Callee pop is necessary to support tail calls.
2929 bool X86::isCalleePop(CallingConv::ID CallingConv,
2930 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2934 switch (CallingConv) {
2937 case CallingConv::X86_StdCall:
2939 case CallingConv::X86_FastCall:
2941 case CallingConv::X86_ThisCall:
2943 case CallingConv::Fast:
2945 case CallingConv::GHC:
2950 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2951 /// specific condition code, returning the condition code and the LHS/RHS of the
2952 /// comparison to make.
2953 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2954 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2956 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2957 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2958 // X > -1 -> X == 0, jump !sign.
2959 RHS = DAG.getConstant(0, RHS.getValueType());
2960 return X86::COND_NS;
2961 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2962 // X < 0 -> X == 0, jump on sign.
2964 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2966 RHS = DAG.getConstant(0, RHS.getValueType());
2967 return X86::COND_LE;
2971 switch (SetCCOpcode) {
2972 default: llvm_unreachable("Invalid integer condition!");
2973 case ISD::SETEQ: return X86::COND_E;
2974 case ISD::SETGT: return X86::COND_G;
2975 case ISD::SETGE: return X86::COND_GE;
2976 case ISD::SETLT: return X86::COND_L;
2977 case ISD::SETLE: return X86::COND_LE;
2978 case ISD::SETNE: return X86::COND_NE;
2979 case ISD::SETULT: return X86::COND_B;
2980 case ISD::SETUGT: return X86::COND_A;
2981 case ISD::SETULE: return X86::COND_BE;
2982 case ISD::SETUGE: return X86::COND_AE;
2986 // First determine if it is required or is profitable to flip the operands.
2988 // If LHS is a foldable load, but RHS is not, flip the condition.
2989 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2990 !ISD::isNON_EXTLoad(RHS.getNode())) {
2991 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2992 std::swap(LHS, RHS);
2995 switch (SetCCOpcode) {
3001 std::swap(LHS, RHS);
3005 // On a floating point condition, the flags are set as follows:
3007 // 0 | 0 | 0 | X > Y
3008 // 0 | 0 | 1 | X < Y
3009 // 1 | 0 | 0 | X == Y
3010 // 1 | 1 | 1 | unordered
3011 switch (SetCCOpcode) {
3012 default: llvm_unreachable("Condcode should be pre-legalized away");
3014 case ISD::SETEQ: return X86::COND_E;
3015 case ISD::SETOLT: // flipped
3017 case ISD::SETGT: return X86::COND_A;
3018 case ISD::SETOLE: // flipped
3020 case ISD::SETGE: return X86::COND_AE;
3021 case ISD::SETUGT: // flipped
3023 case ISD::SETLT: return X86::COND_B;
3024 case ISD::SETUGE: // flipped
3026 case ISD::SETLE: return X86::COND_BE;
3028 case ISD::SETNE: return X86::COND_NE;
3029 case ISD::SETUO: return X86::COND_P;
3030 case ISD::SETO: return X86::COND_NP;
3032 case ISD::SETUNE: return X86::COND_INVALID;
3036 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3037 /// code. Current x86 isa includes the following FP cmov instructions:
3038 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3039 static bool hasFPCMov(unsigned X86CC) {
3055 /// isFPImmLegal - Returns true if the target can instruction select the
3056 /// specified FP immediate natively. If false, the legalizer will
3057 /// materialize the FP immediate as a load from a constant pool.
3058 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3059 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3060 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3066 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3067 /// the specified range (L, H].
3068 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3069 return (Val < 0) || (Val >= Low && Val < Hi);
3072 /// isUndefOrInRange - Return true if every element in Mask, begining
3073 /// from position Pos and ending in Pos+Size, falls within the specified
3074 /// range (L, L+Pos]. or is undef.
3075 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3076 int Pos, int Size, int Low, int Hi) {
3077 for (int i = Pos, e = Pos+Size; i != e; ++i)
3078 if (!isUndefOrInRange(Mask[i], Low, Hi))
3083 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3084 /// specified value.
3085 static bool isUndefOrEqual(int Val, int CmpVal) {
3086 if (Val < 0 || Val == CmpVal)
3091 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3092 /// from position Pos and ending in Pos+Size, falls within the specified
3093 /// sequential range (L, L+Pos]. or is undef.
3094 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3095 int Pos, int Size, int Low) {
3096 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3097 if (!isUndefOrEqual(Mask[i], Low))
3102 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3103 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3104 /// the second operand.
3105 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3106 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3107 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3108 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3109 return (Mask[0] < 2 && Mask[1] < 2);
3113 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3114 SmallVector<int, 8> M;
3116 return ::isPSHUFDMask(M, N->getValueType(0));
3119 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3120 /// is suitable for input to PSHUFHW.
3121 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3122 if (VT != MVT::v8i16)
3125 // Lower quadword copied in order or undef.
3126 for (int i = 0; i != 4; ++i)
3127 if (Mask[i] >= 0 && Mask[i] != i)
3130 // Upper quadword shuffled.
3131 for (int i = 4; i != 8; ++i)
3132 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3138 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3139 SmallVector<int, 8> M;
3141 return ::isPSHUFHWMask(M, N->getValueType(0));
3144 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3145 /// is suitable for input to PSHUFLW.
3146 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3147 if (VT != MVT::v8i16)
3150 // Upper quadword copied in order.
3151 for (int i = 4; i != 8; ++i)
3152 if (Mask[i] >= 0 && Mask[i] != i)
3155 // Lower quadword shuffled.
3156 for (int i = 0; i != 4; ++i)
3163 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3164 SmallVector<int, 8> M;
3166 return ::isPSHUFLWMask(M, N->getValueType(0));
3169 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3170 /// is suitable for input to PALIGNR.
3171 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3173 int i, e = VT.getVectorNumElements();
3174 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3177 // Do not handle v2i64 / v2f64 shuffles with palignr.
3178 if (e < 4 || !hasSSSE3)
3181 for (i = 0; i != e; ++i)
3185 // All undef, not a palignr.
3189 // Make sure we're shifting in the right direction.
3193 int s = Mask[i] - i;
3195 // Check the rest of the elements to see if they are consecutive.
3196 for (++i; i != e; ++i) {
3198 if (m >= 0 && m != s+i)
3204 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3205 /// specifies a shuffle of elements that is suitable for input to 256-bit
3207 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3208 const X86Subtarget *Subtarget) {
3209 int NumElems = VT.getVectorNumElements();
3211 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3217 // VSHUFPSY divides the resulting vector into 4 chunks.
3218 // The sources are also splitted into 4 chunks, and each destination
3219 // chunk must come from a different source chunk.
3221 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3222 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3224 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3225 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3227 int QuarterSize = NumElems/4;
3228 int HalfSize = QuarterSize*2;
3229 for (int i = 0; i < QuarterSize; ++i)
3230 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3232 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3233 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3236 // The mask of the second half must be the same as the first but with
3237 // the appropriate offsets. This works in the same way as VPERMILPS
3238 // works with masks.
3239 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3240 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3242 int FstHalfIdx = i-HalfSize;
3243 if (Mask[FstHalfIdx] < 0)
3245 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3248 for (int i = QuarterSize*3; i < NumElems; ++i) {
3249 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3251 int FstHalfIdx = i-HalfSize;
3252 if (Mask[FstHalfIdx] < 0)
3254 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3262 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3263 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3264 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3265 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3266 EVT VT = SVOp->getValueType(0);
3267 int NumElems = VT.getVectorNumElements();
3269 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3270 "Only supports v8i32 and v8f32 types");
3272 int HalfSize = NumElems/2;
3274 for (int i = 0; i != NumElems ; ++i) {
3275 if (SVOp->getMaskElt(i) < 0)
3277 // The mask of the first half must be equal to the second one.
3278 unsigned Shamt = (i%HalfSize)*2;
3279 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3280 Mask |= Elt << Shamt;
3286 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3287 /// specifies a shuffle of elements that is suitable for input to 256-bit
3288 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3289 /// version and the mask of the second half isn't binded with the first
3291 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3292 const X86Subtarget *Subtarget) {
3293 int NumElems = VT.getVectorNumElements();
3295 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3301 // VSHUFPSY divides the resulting vector into 4 chunks.
3302 // The sources are also splitted into 4 chunks, and each destination
3303 // chunk must come from a different source chunk.
3305 // SRC1 => X3 X2 X1 X0
3306 // SRC2 => Y3 Y2 Y1 Y0
3308 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3310 int QuarterSize = NumElems/4;
3311 int HalfSize = QuarterSize*2;
3312 for (int i = 0; i < QuarterSize; ++i)
3313 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3315 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3316 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3318 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3319 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3321 for (int i = QuarterSize*3; i < NumElems; ++i)
3322 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3328 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3329 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3330 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3331 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3332 EVT VT = SVOp->getValueType(0);
3333 int NumElems = VT.getVectorNumElements();
3335 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3336 "Only supports v4i64 and v4f64 types");
3338 int HalfSize = NumElems/2;
3340 for (int i = 0; i != NumElems ; ++i) {
3341 if (SVOp->getMaskElt(i) < 0)
3343 int Elt = SVOp->getMaskElt(i) % HalfSize;
3350 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3351 /// specifies a shuffle of elements that is suitable for input to 128-bit
3352 /// SHUFPS and SHUFPD.
3353 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3354 int NumElems = VT.getVectorNumElements();
3356 if (VT.getSizeInBits() != 128)
3359 if (NumElems != 2 && NumElems != 4)
3362 int Half = NumElems / 2;
3363 for (int i = 0; i < Half; ++i)
3364 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3366 for (int i = Half; i < NumElems; ++i)
3367 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3373 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3374 SmallVector<int, 8> M;
3376 return ::isSHUFPMask(M, N->getValueType(0));
3379 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3380 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3381 /// half elements to come from vector 1 (which would equal the dest.) and
3382 /// the upper half to come from vector 2.
3383 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3384 int NumElems = VT.getVectorNumElements();
3386 if (NumElems != 2 && NumElems != 4)
3389 int Half = NumElems / 2;
3390 for (int i = 0; i < Half; ++i)
3391 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3393 for (int i = Half; i < NumElems; ++i)
3394 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3399 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3400 SmallVector<int, 8> M;
3402 return isCommutedSHUFPMask(M, N->getValueType(0));
3405 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3406 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3407 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3408 EVT VT = N->getValueType(0);
3409 unsigned NumElems = VT.getVectorNumElements();
3411 if (VT.getSizeInBits() != 128)
3417 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3418 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3419 isUndefOrEqual(N->getMaskElt(1), 7) &&
3420 isUndefOrEqual(N->getMaskElt(2), 2) &&
3421 isUndefOrEqual(N->getMaskElt(3), 3);
3424 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3425 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3427 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3428 EVT VT = N->getValueType(0);
3429 unsigned NumElems = VT.getVectorNumElements();
3431 if (VT.getSizeInBits() != 128)
3437 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3438 isUndefOrEqual(N->getMaskElt(1), 3) &&
3439 isUndefOrEqual(N->getMaskElt(2), 2) &&
3440 isUndefOrEqual(N->getMaskElt(3), 3);
3443 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3444 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3445 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3446 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3448 if (NumElems != 2 && NumElems != 4)
3451 for (unsigned i = 0; i < NumElems/2; ++i)
3452 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3455 for (unsigned i = NumElems/2; i < NumElems; ++i)
3456 if (!isUndefOrEqual(N->getMaskElt(i), i))
3462 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3463 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3464 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3465 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3467 if ((NumElems != 2 && NumElems != 4)
3468 || N->getValueType(0).getSizeInBits() > 128)
3471 for (unsigned i = 0; i < NumElems/2; ++i)
3472 if (!isUndefOrEqual(N->getMaskElt(i), i))
3475 for (unsigned i = 0; i < NumElems/2; ++i)
3476 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3482 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3483 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3484 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3485 bool V2IsSplat = false) {
3486 int NumElts = VT.getVectorNumElements();
3488 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3489 "Unsupported vector type for unpckh");
3491 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3494 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3495 // independently on 128-bit lanes.
3496 unsigned NumLanes = VT.getSizeInBits()/128;
3497 unsigned NumLaneElts = NumElts/NumLanes;
3500 unsigned End = NumLaneElts;
3501 for (unsigned s = 0; s < NumLanes; ++s) {
3502 for (unsigned i = Start, j = s * NumLaneElts;
3506 int BitI1 = Mask[i+1];
3507 if (!isUndefOrEqual(BitI, j))
3510 if (!isUndefOrEqual(BitI1, NumElts))
3513 if (!isUndefOrEqual(BitI1, j + NumElts))
3517 // Process the next 128 bits.
3518 Start += NumLaneElts;
3525 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3526 SmallVector<int, 8> M;
3528 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3531 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3532 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3533 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3534 bool V2IsSplat = false) {
3535 int NumElts = VT.getVectorNumElements();
3537 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3538 "Unsupported vector type for unpckh");
3540 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3543 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3544 // independently on 128-bit lanes.
3545 unsigned NumLanes = VT.getSizeInBits()/128;
3546 unsigned NumLaneElts = NumElts/NumLanes;
3549 unsigned End = NumLaneElts;
3550 for (unsigned l = 0; l != NumLanes; ++l) {
3551 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3552 i != End; i += 2, ++j) {
3554 int BitI1 = Mask[i+1];
3555 if (!isUndefOrEqual(BitI, j))
3558 if (isUndefOrEqual(BitI1, NumElts))
3561 if (!isUndefOrEqual(BitI1, j+NumElts))
3565 // Process the next 128 bits.
3566 Start += NumLaneElts;
3572 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3573 SmallVector<int, 8> M;
3575 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3578 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3579 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3581 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3582 int NumElems = VT.getVectorNumElements();
3583 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3586 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3587 // FIXME: Need a better way to get rid of this, there's no latency difference
3588 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3589 // the former later. We should also remove the "_undef" special mask.
3590 if (NumElems == 4 && VT.getSizeInBits() == 256)
3593 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3594 // independently on 128-bit lanes.
3595 unsigned NumLanes = VT.getSizeInBits() / 128;
3596 unsigned NumLaneElts = NumElems / NumLanes;
3598 for (unsigned s = 0; s < NumLanes; ++s) {
3599 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3600 i != NumLaneElts * (s + 1);
3603 int BitI1 = Mask[i+1];
3605 if (!isUndefOrEqual(BitI, j))
3607 if (!isUndefOrEqual(BitI1, j))
3615 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3616 SmallVector<int, 8> M;
3618 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3621 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3622 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3624 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3625 int NumElems = VT.getVectorNumElements();
3626 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3629 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3631 int BitI1 = Mask[i+1];
3632 if (!isUndefOrEqual(BitI, j))
3634 if (!isUndefOrEqual(BitI1, j))
3640 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3641 SmallVector<int, 8> M;
3643 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3646 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3647 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3648 /// MOVSD, and MOVD, i.e. setting the lowest element.
3649 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3650 if (VT.getVectorElementType().getSizeInBits() < 32)
3653 int NumElts = VT.getVectorNumElements();
3655 if (!isUndefOrEqual(Mask[0], NumElts))
3658 for (int i = 1; i < NumElts; ++i)
3659 if (!isUndefOrEqual(Mask[i], i))
3665 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3666 SmallVector<int, 8> M;
3668 return ::isMOVLMask(M, N->getValueType(0));
3671 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3672 /// as permutations between 128-bit chunks or halves. As an example: this
3674 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3675 /// The first half comes from the second half of V1 and the second half from the
3676 /// the second half of V2.
3677 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3678 const X86Subtarget *Subtarget) {
3679 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3682 // The shuffle result is divided into half A and half B. In total the two
3683 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3684 // B must come from C, D, E or F.
3685 int HalfSize = VT.getVectorNumElements()/2;
3686 bool MatchA = false, MatchB = false;
3688 // Check if A comes from one of C, D, E, F.
3689 for (int Half = 0; Half < 4; ++Half) {
3690 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3696 // Check if B comes from one of C, D, E, F.
3697 for (int Half = 0; Half < 4; ++Half) {
3698 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3704 return MatchA && MatchB;
3707 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3708 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3709 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3711 EVT VT = SVOp->getValueType(0);
3713 int HalfSize = VT.getVectorNumElements()/2;
3715 int FstHalf = 0, SndHalf = 0;
3716 for (int i = 0; i < HalfSize; ++i) {
3717 if (SVOp->getMaskElt(i) > 0) {
3718 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3722 for (int i = HalfSize; i < HalfSize*2; ++i) {
3723 if (SVOp->getMaskElt(i) > 0) {
3724 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3729 return (FstHalf | (SndHalf << 4));
3732 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3733 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3734 /// Note that VPERMIL mask matching is different depending whether theunderlying
3735 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3736 /// to the same elements of the low, but to the higher half of the source.
3737 /// In VPERMILPD the two lanes could be shuffled independently of each other
3738 /// with the same restriction that lanes can't be crossed.
3739 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3740 const X86Subtarget *Subtarget) {
3741 int NumElts = VT.getVectorNumElements();
3742 int NumLanes = VT.getSizeInBits()/128;
3744 if (!Subtarget->hasAVX())
3747 // Match any permutation of 128-bit vector with 64-bit types
3748 if (NumLanes == 1 && NumElts != 2)
3751 // Only match 256-bit with 32 types
3752 if (VT.getSizeInBits() == 256 && NumElts != 4)
3755 // The mask on the high lane is independent of the low. Both can match
3756 // any element in inside its own lane, but can't cross.
3757 int LaneSize = NumElts/NumLanes;
3758 for (int l = 0; l < NumLanes; ++l)
3759 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3760 int LaneStart = l*LaneSize;
3761 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3768 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3769 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3770 /// Note that VPERMIL mask matching is different depending whether theunderlying
3771 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3772 /// to the same elements of the low, but to the higher half of the source.
3773 /// In VPERMILPD the two lanes could be shuffled independently of each other
3774 /// with the same restriction that lanes can't be crossed.
3775 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3776 const X86Subtarget *Subtarget) {
3777 unsigned NumElts = VT.getVectorNumElements();
3778 unsigned NumLanes = VT.getSizeInBits()/128;
3780 if (!Subtarget->hasAVX())
3783 // Match any permutation of 128-bit vector with 32-bit types
3784 if (NumLanes == 1 && NumElts != 4)
3787 // Only match 256-bit with 32 types
3788 if (VT.getSizeInBits() == 256 && NumElts != 8)
3791 // The mask on the high lane should be the same as the low. Actually,
3792 // they can differ if any of the corresponding index in a lane is undef
3793 // and the other stays in range.
3794 int LaneSize = NumElts/NumLanes;
3795 for (int i = 0; i < LaneSize; ++i) {
3796 int HighElt = i+LaneSize;
3797 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3798 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3800 if (!HighValid || !LowValid)
3802 if (Mask[i] < 0 || Mask[HighElt] < 0)
3804 if (Mask[HighElt]-Mask[i] != LaneSize)
3811 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3812 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3813 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3814 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3815 EVT VT = SVOp->getValueType(0);
3817 int NumElts = VT.getVectorNumElements();
3818 int NumLanes = VT.getSizeInBits()/128;
3819 int LaneSize = NumElts/NumLanes;
3821 // Although the mask is equal for both lanes do it twice to get the cases
3822 // where a mask will match because the same mask element is undef on the
3823 // first half but valid on the second. This would get pathological cases
3824 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3826 for (int l = 0; l < NumLanes; ++l) {
3827 for (int i = 0; i < LaneSize; ++i) {
3828 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3831 if (MaskElt >= LaneSize)
3832 MaskElt -= LaneSize;
3833 Mask |= MaskElt << (i*2);
3840 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3841 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3842 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3843 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3844 EVT VT = SVOp->getValueType(0);
3846 int NumElts = VT.getVectorNumElements();
3847 int NumLanes = VT.getSizeInBits()/128;
3850 int LaneSize = NumElts/NumLanes;
3851 for (int l = 0; l < NumLanes; ++l)
3852 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3853 int MaskElt = SVOp->getMaskElt(i);
3856 Mask |= (MaskElt-l*LaneSize) << i;
3862 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3863 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3864 /// element of vector 2 and the other elements to come from vector 1 in order.
3865 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3866 bool V2IsSplat = false, bool V2IsUndef = false) {
3867 int NumOps = VT.getVectorNumElements();
3868 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3871 if (!isUndefOrEqual(Mask[0], 0))
3874 for (int i = 1; i < NumOps; ++i)
3875 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3876 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3877 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3883 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3884 bool V2IsUndef = false) {
3885 SmallVector<int, 8> M;
3887 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3890 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3891 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3892 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3893 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3894 const X86Subtarget *Subtarget) {
3895 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3898 // The second vector must be undef
3899 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3902 EVT VT = N->getValueType(0);
3903 unsigned NumElems = VT.getVectorNumElements();
3905 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3906 (VT.getSizeInBits() == 256 && NumElems != 8))
3909 // "i+1" is the value the indexed mask element must have
3910 for (unsigned i = 0; i < NumElems; i += 2)
3911 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3912 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3918 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3919 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3920 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3921 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3922 const X86Subtarget *Subtarget) {
3923 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3926 // The second vector must be undef
3927 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3930 EVT VT = N->getValueType(0);
3931 unsigned NumElems = VT.getVectorNumElements();
3933 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3934 (VT.getSizeInBits() == 256 && NumElems != 8))
3937 // "i" is the value the indexed mask element must have
3938 for (unsigned i = 0; i < NumElems; i += 2)
3939 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3940 !isUndefOrEqual(N->getMaskElt(i+1), i))
3946 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3947 /// specifies a shuffle of elements that is suitable for input to 256-bit
3948 /// version of MOVDDUP.
3949 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N,
3950 const X86Subtarget *Subtarget) {
3951 EVT VT = N->getValueType(0);
3952 int NumElts = VT.getVectorNumElements();
3953 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF;
3955 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 ||
3956 !V2IsUndef || NumElts != 4)
3959 for (int i = 0; i != NumElts/2; ++i)
3960 if (!isUndefOrEqual(N->getMaskElt(i), 0))
3962 for (int i = NumElts/2; i != NumElts; ++i)
3963 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2))
3968 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3969 /// specifies a shuffle of elements that is suitable for input to 128-bit
3970 /// version of MOVDDUP.
3971 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3972 EVT VT = N->getValueType(0);
3974 if (VT.getSizeInBits() != 128)
3977 int e = VT.getVectorNumElements() / 2;
3978 for (int i = 0; i < e; ++i)
3979 if (!isUndefOrEqual(N->getMaskElt(i), i))
3981 for (int i = 0; i < e; ++i)
3982 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3987 /// isVEXTRACTF128Index - Return true if the specified
3988 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3989 /// suitable for input to VEXTRACTF128.
3990 bool X86::isVEXTRACTF128Index(SDNode *N) {
3991 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3994 // The index should be aligned on a 128-bit boundary.
3996 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3998 unsigned VL = N->getValueType(0).getVectorNumElements();
3999 unsigned VBits = N->getValueType(0).getSizeInBits();
4000 unsigned ElSize = VBits / VL;
4001 bool Result = (Index * ElSize) % 128 == 0;
4006 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4007 /// operand specifies a subvector insert that is suitable for input to
4009 bool X86::isVINSERTF128Index(SDNode *N) {
4010 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4013 // The index should be aligned on a 128-bit boundary.
4015 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4017 unsigned VL = N->getValueType(0).getVectorNumElements();
4018 unsigned VBits = N->getValueType(0).getSizeInBits();
4019 unsigned ElSize = VBits / VL;
4020 bool Result = (Index * ElSize) % 128 == 0;
4025 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4026 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4027 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
4028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4029 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
4031 unsigned Shift = (NumOperands == 4) ? 2 : 1;
4033 for (int i = 0; i < NumOperands; ++i) {
4034 int Val = SVOp->getMaskElt(NumOperands-i-1);
4035 if (Val < 0) Val = 0;
4036 if (Val >= NumOperands) Val -= NumOperands;
4038 if (i != NumOperands - 1)
4044 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4045 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4046 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
4047 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4049 // 8 nodes, but we only care about the last 4.
4050 for (unsigned i = 7; i >= 4; --i) {
4051 int Val = SVOp->getMaskElt(i);
4060 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4061 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4062 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4063 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4065 // 8 nodes, but we only care about the first 4.
4066 for (int i = 3; i >= 0; --i) {
4067 int Val = SVOp->getMaskElt(i);
4076 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4077 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4078 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4079 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4080 EVT VVT = N->getValueType(0);
4081 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4085 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4086 Val = SVOp->getMaskElt(i);
4090 assert(Val - i > 0 && "PALIGNR imm should be positive");
4091 return (Val - i) * EltSize;
4094 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4095 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4097 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4098 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4099 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4102 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4104 EVT VecVT = N->getOperand(0).getValueType();
4105 EVT ElVT = VecVT.getVectorElementType();
4107 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4108 return Index / NumElemsPerChunk;
4111 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4112 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4114 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4115 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4116 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4119 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4121 EVT VecVT = N->getValueType(0);
4122 EVT ElVT = VecVT.getVectorElementType();
4124 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4125 return Index / NumElemsPerChunk;
4128 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4130 bool X86::isZeroNode(SDValue Elt) {
4131 return ((isa<ConstantSDNode>(Elt) &&
4132 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4133 (isa<ConstantFPSDNode>(Elt) &&
4134 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4137 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4138 /// their permute mask.
4139 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4140 SelectionDAG &DAG) {
4141 EVT VT = SVOp->getValueType(0);
4142 unsigned NumElems = VT.getVectorNumElements();
4143 SmallVector<int, 8> MaskVec;
4145 for (unsigned i = 0; i != NumElems; ++i) {
4146 int idx = SVOp->getMaskElt(i);
4148 MaskVec.push_back(idx);
4149 else if (idx < (int)NumElems)
4150 MaskVec.push_back(idx + NumElems);
4152 MaskVec.push_back(idx - NumElems);
4154 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4155 SVOp->getOperand(0), &MaskVec[0]);
4158 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4159 /// the two vector operands have swapped position.
4160 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4161 unsigned NumElems = VT.getVectorNumElements();
4162 for (unsigned i = 0; i != NumElems; ++i) {
4166 else if (idx < (int)NumElems)
4167 Mask[i] = idx + NumElems;
4169 Mask[i] = idx - NumElems;
4173 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4174 /// match movhlps. The lower half elements should come from upper half of
4175 /// V1 (and in order), and the upper half elements should come from the upper
4176 /// half of V2 (and in order).
4177 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4178 EVT VT = Op->getValueType(0);
4179 if (VT.getSizeInBits() != 128)
4181 if (VT.getVectorNumElements() != 4)
4183 for (unsigned i = 0, e = 2; i != e; ++i)
4184 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4186 for (unsigned i = 2; i != 4; ++i)
4187 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4192 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4193 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4195 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4196 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4198 N = N->getOperand(0).getNode();
4199 if (!ISD::isNON_EXTLoad(N))
4202 *LD = cast<LoadSDNode>(N);
4206 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4207 /// match movlp{s|d}. The lower half elements should come from lower half of
4208 /// V1 (and in order), and the upper half elements should come from the upper
4209 /// half of V2 (and in order). And since V1 will become the source of the
4210 /// MOVLP, it must be either a vector load or a scalar load to vector.
4211 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4212 ShuffleVectorSDNode *Op) {
4213 EVT VT = Op->getValueType(0);
4214 if (VT.getSizeInBits() != 128)
4217 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4219 // Is V2 is a vector load, don't do this transformation. We will try to use
4220 // load folding shufps op.
4221 if (ISD::isNON_EXTLoad(V2))
4224 unsigned NumElems = VT.getVectorNumElements();
4226 if (NumElems != 2 && NumElems != 4)
4228 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4229 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4231 for (unsigned i = NumElems/2; i != NumElems; ++i)
4232 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4237 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4239 static bool isSplatVector(SDNode *N) {
4240 if (N->getOpcode() != ISD::BUILD_VECTOR)
4243 SDValue SplatValue = N->getOperand(0);
4244 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4245 if (N->getOperand(i) != SplatValue)
4250 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4251 /// to an zero vector.
4252 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4253 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4254 SDValue V1 = N->getOperand(0);
4255 SDValue V2 = N->getOperand(1);
4256 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4257 for (unsigned i = 0; i != NumElems; ++i) {
4258 int Idx = N->getMaskElt(i);
4259 if (Idx >= (int)NumElems) {
4260 unsigned Opc = V2.getOpcode();
4261 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4263 if (Opc != ISD::BUILD_VECTOR ||
4264 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4266 } else if (Idx >= 0) {
4267 unsigned Opc = V1.getOpcode();
4268 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4270 if (Opc != ISD::BUILD_VECTOR ||
4271 !X86::isZeroNode(V1.getOperand(Idx)))
4278 /// getZeroVector - Returns a vector of specified type with all zero elements.
4280 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4282 assert(VT.isVector() && "Expected a vector type");
4284 // Always build SSE zero vectors as <4 x i32> bitcasted
4285 // to their dest type. This ensures they get CSE'd.
4287 if (VT.getSizeInBits() == 128) { // SSE
4288 if (HasSSE2) { // SSE2
4289 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4290 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4292 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4293 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4295 } else if (VT.getSizeInBits() == 256) { // AVX
4296 // 256-bit logic and arithmetic instructions in AVX are
4297 // all floating-point, no support for integer ops. Default
4298 // to emitting fp zeroed vectors then.
4299 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4300 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4301 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4303 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4306 /// getOnesVector - Returns a vector of specified type with all bits set.
4307 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4308 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4309 /// original type, ensuring they get CSE'd.
4310 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4311 assert(VT.isVector() && "Expected a vector type");
4312 assert((VT.is128BitVector() || VT.is256BitVector())
4313 && "Expected a 128-bit or 256-bit vector type");
4315 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4316 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4317 Cst, Cst, Cst, Cst);
4319 if (VT.is256BitVector()) {
4320 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4321 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4322 Vec = Insert128BitVector(InsV, Vec,
4323 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4326 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4329 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4330 /// that point to V2 points to its first element.
4331 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4332 EVT VT = SVOp->getValueType(0);
4333 unsigned NumElems = VT.getVectorNumElements();
4335 bool Changed = false;
4336 SmallVector<int, 8> MaskVec;
4337 SVOp->getMask(MaskVec);
4339 for (unsigned i = 0; i != NumElems; ++i) {
4340 if (MaskVec[i] > (int)NumElems) {
4341 MaskVec[i] = NumElems;
4346 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4347 SVOp->getOperand(1), &MaskVec[0]);
4348 return SDValue(SVOp, 0);
4351 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4352 /// operation of specified width.
4353 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4355 unsigned NumElems = VT.getVectorNumElements();
4356 SmallVector<int, 8> Mask;
4357 Mask.push_back(NumElems);
4358 for (unsigned i = 1; i != NumElems; ++i)
4360 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4363 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4364 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4366 unsigned NumElems = VT.getVectorNumElements();
4367 SmallVector<int, 8> Mask;
4368 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4370 Mask.push_back(i + NumElems);
4372 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4375 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4376 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4378 unsigned NumElems = VT.getVectorNumElements();
4379 unsigned Half = NumElems/2;
4380 SmallVector<int, 8> Mask;
4381 for (unsigned i = 0; i != Half; ++i) {
4382 Mask.push_back(i + Half);
4383 Mask.push_back(i + NumElems + Half);
4385 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4388 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4389 // a generic shuffle instruction because the target has no such instructions.
4390 // Generate shuffles which repeat i16 and i8 several times until they can be
4391 // represented by v4f32 and then be manipulated by target suported shuffles.
4392 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4393 EVT VT = V.getValueType();
4394 int NumElems = VT.getVectorNumElements();
4395 DebugLoc dl = V.getDebugLoc();
4397 while (NumElems > 4) {
4398 if (EltNo < NumElems/2) {
4399 V = getUnpackl(DAG, dl, VT, V, V);
4401 V = getUnpackh(DAG, dl, VT, V, V);
4402 EltNo -= NumElems/2;
4409 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4410 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4411 EVT VT = V.getValueType();
4412 DebugLoc dl = V.getDebugLoc();
4413 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4414 && "Vector size not supported");
4416 if (VT.getSizeInBits() == 128) {
4417 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4418 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4419 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4422 // To use VPERMILPS to splat scalars, the second half of indicies must
4423 // refer to the higher part, which is a duplication of the lower one,
4424 // because VPERMILPS can only handle in-lane permutations.
4425 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4426 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4428 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4429 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4433 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4436 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4437 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4438 EVT SrcVT = SV->getValueType(0);
4439 SDValue V1 = SV->getOperand(0);
4440 DebugLoc dl = SV->getDebugLoc();
4442 int EltNo = SV->getSplatIndex();
4443 int NumElems = SrcVT.getVectorNumElements();
4444 unsigned Size = SrcVT.getSizeInBits();
4446 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4447 "Unknown how to promote splat for type");
4449 // Extract the 128-bit part containing the splat element and update
4450 // the splat element index when it refers to the higher register.
4452 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4453 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4455 EltNo -= NumElems/2;
4458 // All i16 and i8 vector types can't be used directly by a generic shuffle
4459 // instruction because the target has no such instruction. Generate shuffles
4460 // which repeat i16 and i8 several times until they fit in i32, and then can
4461 // be manipulated by target suported shuffles.
4462 EVT EltVT = SrcVT.getVectorElementType();
4463 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4464 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4466 // Recreate the 256-bit vector and place the same 128-bit vector
4467 // into the low and high part. This is necessary because we want
4468 // to use VPERM* to shuffle the vectors
4470 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4471 DAG.getConstant(0, MVT::i32), DAG, dl);
4472 V1 = Insert128BitVector(InsV, V1,
4473 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4476 return getLegalSplat(DAG, V1, EltNo);
4479 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4480 /// vector of zero or undef vector. This produces a shuffle where the low
4481 /// element of V2 is swizzled into the zero/undef vector, landing at element
4482 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4483 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4484 bool isZero, bool HasSSE2,
4485 SelectionDAG &DAG) {
4486 EVT VT = V2.getValueType();
4488 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4489 unsigned NumElems = VT.getVectorNumElements();
4490 SmallVector<int, 16> MaskVec;
4491 for (unsigned i = 0; i != NumElems; ++i)
4492 // If this is the insertion idx, put the low elt of V2 here.
4493 MaskVec.push_back(i == Idx ? NumElems : i);
4494 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4497 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4498 /// element of the result of the vector shuffle.
4499 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4502 return SDValue(); // Limit search depth.
4504 SDValue V = SDValue(N, 0);
4505 EVT VT = V.getValueType();
4506 unsigned Opcode = V.getOpcode();
4508 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4509 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4510 Index = SV->getMaskElt(Index);
4513 return DAG.getUNDEF(VT.getVectorElementType());
4515 int NumElems = VT.getVectorNumElements();
4516 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4517 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4520 // Recurse into target specific vector shuffles to find scalars.
4521 if (isTargetShuffle(Opcode)) {
4522 int NumElems = VT.getVectorNumElements();
4523 SmallVector<unsigned, 16> ShuffleMask;
4527 case X86ISD::SHUFPS:
4528 case X86ISD::SHUFPD:
4529 ImmN = N->getOperand(N->getNumOperands()-1);
4530 DecodeSHUFPSMask(NumElems,
4531 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4534 case X86ISD::PUNPCKHBW:
4535 case X86ISD::PUNPCKHWD:
4536 case X86ISD::PUNPCKHDQ:
4537 case X86ISD::PUNPCKHQDQ:
4538 DecodePUNPCKHMask(NumElems, ShuffleMask);
4540 case X86ISD::UNPCKHPS:
4541 case X86ISD::UNPCKHPD:
4542 case X86ISD::VUNPCKHPSY:
4543 case X86ISD::VUNPCKHPDY:
4544 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4546 case X86ISD::PUNPCKLBW:
4547 case X86ISD::PUNPCKLWD:
4548 case X86ISD::PUNPCKLDQ:
4549 case X86ISD::PUNPCKLQDQ:
4550 DecodePUNPCKLMask(VT, ShuffleMask);
4552 case X86ISD::UNPCKLPS:
4553 case X86ISD::UNPCKLPD:
4554 case X86ISD::VUNPCKLPSY:
4555 case X86ISD::VUNPCKLPDY:
4556 DecodeUNPCKLPMask(VT, ShuffleMask);
4558 case X86ISD::MOVHLPS:
4559 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4561 case X86ISD::MOVLHPS:
4562 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4564 case X86ISD::PSHUFD:
4565 ImmN = N->getOperand(N->getNumOperands()-1);
4566 DecodePSHUFMask(NumElems,
4567 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4570 case X86ISD::PSHUFHW:
4571 ImmN = N->getOperand(N->getNumOperands()-1);
4572 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4575 case X86ISD::PSHUFLW:
4576 ImmN = N->getOperand(N->getNumOperands()-1);
4577 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4581 case X86ISD::MOVSD: {
4582 // The index 0 always comes from the first element of the second source,
4583 // this is why MOVSS and MOVSD are used in the first place. The other
4584 // elements come from the other positions of the first source vector.
4585 unsigned OpNum = (Index == 0) ? 1 : 0;
4586 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4589 case X86ISD::VPERMILPS:
4590 ImmN = N->getOperand(N->getNumOperands()-1);
4591 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4594 case X86ISD::VPERMILPSY:
4595 ImmN = N->getOperand(N->getNumOperands()-1);
4596 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4599 case X86ISD::VPERMILPD:
4600 ImmN = N->getOperand(N->getNumOperands()-1);
4601 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4604 case X86ISD::VPERMILPDY:
4605 ImmN = N->getOperand(N->getNumOperands()-1);
4606 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4609 case X86ISD::VPERM2F128:
4610 ImmN = N->getOperand(N->getNumOperands()-1);
4611 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4615 assert("not implemented for target shuffle node");
4619 Index = ShuffleMask[Index];
4621 return DAG.getUNDEF(VT.getVectorElementType());
4623 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4624 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4628 // Actual nodes that may contain scalar elements
4629 if (Opcode == ISD::BITCAST) {
4630 V = V.getOperand(0);
4631 EVT SrcVT = V.getValueType();
4632 unsigned NumElems = VT.getVectorNumElements();
4634 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4638 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4639 return (Index == 0) ? V.getOperand(0)
4640 : DAG.getUNDEF(VT.getVectorElementType());
4642 if (V.getOpcode() == ISD::BUILD_VECTOR)
4643 return V.getOperand(Index);
4648 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4649 /// shuffle operation which come from a consecutively from a zero. The
4650 /// search can start in two different directions, from left or right.
4652 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4653 bool ZerosFromLeft, SelectionDAG &DAG) {
4656 while (i < NumElems) {
4657 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4658 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4659 if (!(Elt.getNode() &&
4660 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4668 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4669 /// MaskE correspond consecutively to elements from one of the vector operands,
4670 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4672 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4673 int OpIdx, int NumElems, unsigned &OpNum) {
4674 bool SeenV1 = false;
4675 bool SeenV2 = false;
4677 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4678 int Idx = SVOp->getMaskElt(i);
4679 // Ignore undef indicies
4688 // Only accept consecutive elements from the same vector
4689 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4693 OpNum = SeenV1 ? 0 : 1;
4697 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4698 /// logical left shift of a vector.
4699 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4700 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4701 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4702 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4703 false /* check zeros from right */, DAG);
4709 // Considering the elements in the mask that are not consecutive zeros,
4710 // check if they consecutively come from only one of the source vectors.
4712 // V1 = {X, A, B, C} 0
4714 // vector_shuffle V1, V2 <1, 2, 3, X>
4716 if (!isShuffleMaskConsecutive(SVOp,
4717 0, // Mask Start Index
4718 NumElems-NumZeros-1, // Mask End Index
4719 NumZeros, // Where to start looking in the src vector
4720 NumElems, // Number of elements in vector
4721 OpSrc)) // Which source operand ?
4726 ShVal = SVOp->getOperand(OpSrc);
4730 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4731 /// logical left shift of a vector.
4732 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4733 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4734 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4735 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4736 true /* check zeros from left */, DAG);
4742 // Considering the elements in the mask that are not consecutive zeros,
4743 // check if they consecutively come from only one of the source vectors.
4745 // 0 { A, B, X, X } = V2
4747 // vector_shuffle V1, V2 <X, X, 4, 5>
4749 if (!isShuffleMaskConsecutive(SVOp,
4750 NumZeros, // Mask Start Index
4751 NumElems-1, // Mask End Index
4752 0, // Where to start looking in the src vector
4753 NumElems, // Number of elements in vector
4754 OpSrc)) // Which source operand ?
4759 ShVal = SVOp->getOperand(OpSrc);
4763 /// isVectorShift - Returns true if the shuffle can be implemented as a
4764 /// logical left or right shift of a vector.
4765 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4766 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4767 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4768 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4774 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4776 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4777 unsigned NumNonZero, unsigned NumZero,
4779 const TargetLowering &TLI) {
4783 DebugLoc dl = Op.getDebugLoc();
4786 for (unsigned i = 0; i < 16; ++i) {
4787 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4788 if (ThisIsNonZero && First) {
4790 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4792 V = DAG.getUNDEF(MVT::v8i16);
4797 SDValue ThisElt(0, 0), LastElt(0, 0);
4798 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4799 if (LastIsNonZero) {
4800 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4801 MVT::i16, Op.getOperand(i-1));
4803 if (ThisIsNonZero) {
4804 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4805 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4806 ThisElt, DAG.getConstant(8, MVT::i8));
4808 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4812 if (ThisElt.getNode())
4813 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4814 DAG.getIntPtrConstant(i/2));
4818 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4821 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4823 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4824 unsigned NumNonZero, unsigned NumZero,
4826 const TargetLowering &TLI) {
4830 DebugLoc dl = Op.getDebugLoc();
4833 for (unsigned i = 0; i < 8; ++i) {
4834 bool isNonZero = (NonZeros & (1 << i)) != 0;
4838 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4840 V = DAG.getUNDEF(MVT::v8i16);
4843 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4844 MVT::v8i16, V, Op.getOperand(i),
4845 DAG.getIntPtrConstant(i));
4852 /// getVShift - Return a vector logical shift node.
4854 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4855 unsigned NumBits, SelectionDAG &DAG,
4856 const TargetLowering &TLI, DebugLoc dl) {
4857 EVT ShVT = MVT::v2i64;
4858 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4859 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4860 return DAG.getNode(ISD::BITCAST, dl, VT,
4861 DAG.getNode(Opc, dl, ShVT, SrcOp,
4862 DAG.getConstant(NumBits,
4863 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4867 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4868 SelectionDAG &DAG) const {
4870 // Check if the scalar load can be widened into a vector load. And if
4871 // the address is "base + cst" see if the cst can be "absorbed" into
4872 // the shuffle mask.
4873 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4874 SDValue Ptr = LD->getBasePtr();
4875 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4877 EVT PVT = LD->getValueType(0);
4878 if (PVT != MVT::i32 && PVT != MVT::f32)
4883 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4884 FI = FINode->getIndex();
4886 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4887 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4888 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4889 Offset = Ptr.getConstantOperandVal(1);
4890 Ptr = Ptr.getOperand(0);
4895 // FIXME: 256-bit vector instructions don't require a strict alignment,
4896 // improve this code to support it better.
4897 unsigned RequiredAlign = VT.getSizeInBits()/8;
4898 SDValue Chain = LD->getChain();
4899 // Make sure the stack object alignment is at least 16 or 32.
4900 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4901 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4902 if (MFI->isFixedObjectIndex(FI)) {
4903 // Can't change the alignment. FIXME: It's possible to compute
4904 // the exact stack offset and reference FI + adjust offset instead.
4905 // If someone *really* cares about this. That's the way to implement it.
4908 MFI->setObjectAlignment(FI, RequiredAlign);
4912 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4913 // Ptr + (Offset & ~15).
4916 if ((Offset % RequiredAlign) & 3)
4918 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4920 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4921 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4923 int EltNo = (Offset - StartOffset) >> 2;
4924 int NumElems = VT.getVectorNumElements();
4926 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4927 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4928 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4929 LD->getPointerInfo().getWithOffset(StartOffset),
4932 // Canonicalize it to a v4i32 or v8i32 shuffle.
4933 SmallVector<int, 8> Mask;
4934 for (int i = 0; i < NumElems; ++i)
4935 Mask.push_back(EltNo);
4937 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4938 return DAG.getNode(ISD::BITCAST, dl, NVT,
4939 DAG.getVectorShuffle(CanonVT, dl, V1,
4940 DAG.getUNDEF(CanonVT),&Mask[0]));
4946 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4947 /// vector of type 'VT', see if the elements can be replaced by a single large
4948 /// load which has the same value as a build_vector whose operands are 'elts'.
4950 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4952 /// FIXME: we'd also like to handle the case where the last elements are zero
4953 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4954 /// There's even a handy isZeroNode for that purpose.
4955 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4956 DebugLoc &DL, SelectionDAG &DAG) {
4957 EVT EltVT = VT.getVectorElementType();
4958 unsigned NumElems = Elts.size();
4960 LoadSDNode *LDBase = NULL;
4961 unsigned LastLoadedElt = -1U;
4963 // For each element in the initializer, see if we've found a load or an undef.
4964 // If we don't find an initial load element, or later load elements are
4965 // non-consecutive, bail out.
4966 for (unsigned i = 0; i < NumElems; ++i) {
4967 SDValue Elt = Elts[i];
4969 if (!Elt.getNode() ||
4970 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4973 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4975 LDBase = cast<LoadSDNode>(Elt.getNode());
4979 if (Elt.getOpcode() == ISD::UNDEF)
4982 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4983 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4988 // If we have found an entire vector of loads and undefs, then return a large
4989 // load of the entire vector width starting at the base pointer. If we found
4990 // consecutive loads for the low half, generate a vzext_load node.
4991 if (LastLoadedElt == NumElems - 1) {
4992 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4993 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4994 LDBase->getPointerInfo(),
4995 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4996 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4997 LDBase->getPointerInfo(),
4998 LDBase->isVolatile(), LDBase->isNonTemporal(),
4999 LDBase->getAlignment());
5000 } else if (NumElems == 4 && LastLoadedElt == 1 &&
5001 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5002 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5003 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5004 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
5006 LDBase->getMemOperand());
5007 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5013 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5014 DebugLoc dl = Op.getDebugLoc();
5016 EVT VT = Op.getValueType();
5017 EVT ExtVT = VT.getVectorElementType();
5018 unsigned NumElems = Op.getNumOperands();
5020 // Vectors containing all zeros can be matched by pxor and xorps later
5021 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5022 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5023 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5024 if (Op.getValueType() == MVT::v4i32 ||
5025 Op.getValueType() == MVT::v8i32)
5028 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
5031 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5032 // vectors or broken into v4i32 operations on 256-bit vectors.
5033 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5034 if (Op.getValueType() == MVT::v4i32)
5037 return getOnesVector(Op.getValueType(), DAG, dl);
5040 unsigned EVTBits = ExtVT.getSizeInBits();
5042 unsigned NumZero = 0;
5043 unsigned NumNonZero = 0;
5044 unsigned NonZeros = 0;
5045 bool IsAllConstants = true;
5046 SmallSet<SDValue, 8> Values;
5047 for (unsigned i = 0; i < NumElems; ++i) {
5048 SDValue Elt = Op.getOperand(i);
5049 if (Elt.getOpcode() == ISD::UNDEF)
5052 if (Elt.getOpcode() != ISD::Constant &&
5053 Elt.getOpcode() != ISD::ConstantFP)
5054 IsAllConstants = false;
5055 if (X86::isZeroNode(Elt))
5058 NonZeros |= (1 << i);
5063 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5064 if (NumNonZero == 0)
5065 return DAG.getUNDEF(VT);
5067 // Special case for single non-zero, non-undef, element.
5068 if (NumNonZero == 1) {
5069 unsigned Idx = CountTrailingZeros_32(NonZeros);
5070 SDValue Item = Op.getOperand(Idx);
5072 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5073 // the value are obviously zero, truncate the value to i32 and do the
5074 // insertion that way. Only do this if the value is non-constant or if the
5075 // value is a constant being inserted into element 0. It is cheaper to do
5076 // a constant pool load than it is to do a movd + shuffle.
5077 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5078 (!IsAllConstants || Idx == 0)) {
5079 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5081 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5082 EVT VecVT = MVT::v4i32;
5083 unsigned VecElts = 4;
5085 // Truncate the value (which may itself be a constant) to i32, and
5086 // convert it to a vector with movd (S2V+shuffle to zero extend).
5087 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5088 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5089 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5090 Subtarget->hasSSE2(), DAG);
5092 // Now we have our 32-bit value zero extended in the low element of
5093 // a vector. If Idx != 0, swizzle it into place.
5095 SmallVector<int, 4> Mask;
5096 Mask.push_back(Idx);
5097 for (unsigned i = 1; i != VecElts; ++i)
5099 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5100 DAG.getUNDEF(Item.getValueType()),
5103 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5107 // If we have a constant or non-constant insertion into the low element of
5108 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5109 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5110 // depending on what the source datatype is.
5113 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5114 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5115 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5116 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5117 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5118 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
5120 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5121 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5122 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5123 EVT MiddleVT = MVT::v4i32;
5124 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5125 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5126 Subtarget->hasSSE2(), DAG);
5127 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5131 // Is it a vector logical left shift?
5132 if (NumElems == 2 && Idx == 1 &&
5133 X86::isZeroNode(Op.getOperand(0)) &&
5134 !X86::isZeroNode(Op.getOperand(1))) {
5135 unsigned NumBits = VT.getSizeInBits();
5136 return getVShift(true, VT,
5137 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5138 VT, Op.getOperand(1)),
5139 NumBits/2, DAG, *this, dl);
5142 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5145 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5146 // is a non-constant being inserted into an element other than the low one,
5147 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5148 // movd/movss) to move this into the low element, then shuffle it into
5150 if (EVTBits == 32) {
5151 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5153 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5154 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5155 Subtarget->hasSSE2(), DAG);
5156 SmallVector<int, 8> MaskVec;
5157 for (unsigned i = 0; i < NumElems; i++)
5158 MaskVec.push_back(i == Idx ? 0 : 1);
5159 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5163 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5164 if (Values.size() == 1) {
5165 if (EVTBits == 32) {
5166 // Instead of a shuffle like this:
5167 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5168 // Check if it's possible to issue this instead.
5169 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5170 unsigned Idx = CountTrailingZeros_32(NonZeros);
5171 SDValue Item = Op.getOperand(Idx);
5172 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5173 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5178 // A vector full of immediates; various special cases are already
5179 // handled, so this is best done with a single constant-pool load.
5183 // For AVX-length vectors, build the individual 128-bit pieces and use
5184 // shuffles to put them in place.
5185 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5186 SmallVector<SDValue, 32> V;
5187 for (unsigned i = 0; i < NumElems; ++i)
5188 V.push_back(Op.getOperand(i));
5190 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5192 // Build both the lower and upper subvector.
5193 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5194 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5197 // Recreate the wider vector with the lower and upper part.
5198 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5199 DAG.getConstant(0, MVT::i32), DAG, dl);
5200 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5204 // Let legalizer expand 2-wide build_vectors.
5205 if (EVTBits == 64) {
5206 if (NumNonZero == 1) {
5207 // One half is zero or undef.
5208 unsigned Idx = CountTrailingZeros_32(NonZeros);
5209 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5210 Op.getOperand(Idx));
5211 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5212 Subtarget->hasSSE2(), DAG);
5217 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5218 if (EVTBits == 8 && NumElems == 16) {
5219 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5221 if (V.getNode()) return V;
5224 if (EVTBits == 16 && NumElems == 8) {
5225 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5227 if (V.getNode()) return V;
5230 // If element VT is == 32 bits, turn it into a number of shuffles.
5231 SmallVector<SDValue, 8> V;
5233 if (NumElems == 4 && NumZero > 0) {
5234 for (unsigned i = 0; i < 4; ++i) {
5235 bool isZero = !(NonZeros & (1 << i));
5237 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5239 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5242 for (unsigned i = 0; i < 2; ++i) {
5243 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5246 V[i] = V[i*2]; // Must be a zero vector.
5249 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5252 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5255 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5260 SmallVector<int, 8> MaskVec;
5261 bool Reverse = (NonZeros & 0x3) == 2;
5262 for (unsigned i = 0; i < 2; ++i)
5263 MaskVec.push_back(Reverse ? 1-i : i);
5264 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5265 for (unsigned i = 0; i < 2; ++i)
5266 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5267 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5270 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5271 // Check for a build vector of consecutive loads.
5272 for (unsigned i = 0; i < NumElems; ++i)
5273 V[i] = Op.getOperand(i);
5275 // Check for elements which are consecutive loads.
5276 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5280 // For SSE 4.1, use insertps to put the high elements into the low element.
5281 if (getSubtarget()->hasSSE41()) {
5283 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5284 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5286 Result = DAG.getUNDEF(VT);
5288 for (unsigned i = 1; i < NumElems; ++i) {
5289 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5290 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5291 Op.getOperand(i), DAG.getIntPtrConstant(i));
5296 // Otherwise, expand into a number of unpckl*, start by extending each of
5297 // our (non-undef) elements to the full vector width with the element in the
5298 // bottom slot of the vector (which generates no code for SSE).
5299 for (unsigned i = 0; i < NumElems; ++i) {
5300 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5301 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5303 V[i] = DAG.getUNDEF(VT);
5306 // Next, we iteratively mix elements, e.g. for v4f32:
5307 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5308 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5309 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5310 unsigned EltStride = NumElems >> 1;
5311 while (EltStride != 0) {
5312 for (unsigned i = 0; i < EltStride; ++i) {
5313 // If V[i+EltStride] is undef and this is the first round of mixing,
5314 // then it is safe to just drop this shuffle: V[i] is already in the
5315 // right place, the one element (since it's the first round) being
5316 // inserted as undef can be dropped. This isn't safe for successive
5317 // rounds because they will permute elements within both vectors.
5318 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5319 EltStride == NumElems/2)
5322 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5331 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5332 // them in a MMX register. This is better than doing a stack convert.
5333 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5334 DebugLoc dl = Op.getDebugLoc();
5335 EVT ResVT = Op.getValueType();
5337 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5338 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5340 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5341 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5342 InVec = Op.getOperand(1);
5343 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5344 unsigned NumElts = ResVT.getVectorNumElements();
5345 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5346 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5347 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5349 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5350 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5351 Mask[0] = 0; Mask[1] = 2;
5352 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5354 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5357 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5358 // to create 256-bit vectors from two other 128-bit ones.
5359 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5360 DebugLoc dl = Op.getDebugLoc();
5361 EVT ResVT = Op.getValueType();
5363 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5365 SDValue V1 = Op.getOperand(0);
5366 SDValue V2 = Op.getOperand(1);
5367 unsigned NumElems = ResVT.getVectorNumElements();
5369 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5370 DAG.getConstant(0, MVT::i32), DAG, dl);
5371 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5376 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5377 EVT ResVT = Op.getValueType();
5379 assert(Op.getNumOperands() == 2);
5380 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5381 "Unsupported CONCAT_VECTORS for value type");
5383 // We support concatenate two MMX registers and place them in a MMX register.
5384 // This is better than doing a stack convert.
5385 if (ResVT.is128BitVector())
5386 return LowerMMXCONCAT_VECTORS(Op, DAG);
5388 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5389 // from two other 128-bit ones.
5390 return LowerAVXCONCAT_VECTORS(Op, DAG);
5393 // v8i16 shuffles - Prefer shuffles in the following order:
5394 // 1. [all] pshuflw, pshufhw, optional move
5395 // 2. [ssse3] 1 x pshufb
5396 // 3. [ssse3] 2 x pshufb + 1 x por
5397 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5399 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5400 SelectionDAG &DAG) const {
5401 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5402 SDValue V1 = SVOp->getOperand(0);
5403 SDValue V2 = SVOp->getOperand(1);
5404 DebugLoc dl = SVOp->getDebugLoc();
5405 SmallVector<int, 8> MaskVals;
5407 // Determine if more than 1 of the words in each of the low and high quadwords
5408 // of the result come from the same quadword of one of the two inputs. Undef
5409 // mask values count as coming from any quadword, for better codegen.
5410 SmallVector<unsigned, 4> LoQuad(4);
5411 SmallVector<unsigned, 4> HiQuad(4);
5412 BitVector InputQuads(4);
5413 for (unsigned i = 0; i < 8; ++i) {
5414 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5415 int EltIdx = SVOp->getMaskElt(i);
5416 MaskVals.push_back(EltIdx);
5425 InputQuads.set(EltIdx / 4);
5428 int BestLoQuad = -1;
5429 unsigned MaxQuad = 1;
5430 for (unsigned i = 0; i < 4; ++i) {
5431 if (LoQuad[i] > MaxQuad) {
5433 MaxQuad = LoQuad[i];
5437 int BestHiQuad = -1;
5439 for (unsigned i = 0; i < 4; ++i) {
5440 if (HiQuad[i] > MaxQuad) {
5442 MaxQuad = HiQuad[i];
5446 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5447 // of the two input vectors, shuffle them into one input vector so only a
5448 // single pshufb instruction is necessary. If There are more than 2 input
5449 // quads, disable the next transformation since it does not help SSSE3.
5450 bool V1Used = InputQuads[0] || InputQuads[1];
5451 bool V2Used = InputQuads[2] || InputQuads[3];
5452 if (Subtarget->hasSSSE3()) {
5453 if (InputQuads.count() == 2 && V1Used && V2Used) {
5454 BestLoQuad = InputQuads.find_first();
5455 BestHiQuad = InputQuads.find_next(BestLoQuad);
5457 if (InputQuads.count() > 2) {
5463 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5464 // the shuffle mask. If a quad is scored as -1, that means that it contains
5465 // words from all 4 input quadwords.
5467 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5468 SmallVector<int, 8> MaskV;
5469 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5470 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5471 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5472 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5473 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5474 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5476 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5477 // source words for the shuffle, to aid later transformations.
5478 bool AllWordsInNewV = true;
5479 bool InOrder[2] = { true, true };
5480 for (unsigned i = 0; i != 8; ++i) {
5481 int idx = MaskVals[i];
5483 InOrder[i/4] = false;
5484 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5486 AllWordsInNewV = false;
5490 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5491 if (AllWordsInNewV) {
5492 for (int i = 0; i != 8; ++i) {
5493 int idx = MaskVals[i];
5496 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5497 if ((idx != i) && idx < 4)
5499 if ((idx != i) && idx > 3)
5508 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5509 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5510 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5511 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5512 unsigned TargetMask = 0;
5513 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5514 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5515 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5516 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5517 V1 = NewV.getOperand(0);
5518 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5522 // If we have SSSE3, and all words of the result are from 1 input vector,
5523 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5524 // is present, fall back to case 4.
5525 if (Subtarget->hasSSSE3()) {
5526 SmallVector<SDValue,16> pshufbMask;
5528 // If we have elements from both input vectors, set the high bit of the
5529 // shuffle mask element to zero out elements that come from V2 in the V1
5530 // mask, and elements that come from V1 in the V2 mask, so that the two
5531 // results can be OR'd together.
5532 bool TwoInputs = V1Used && V2Used;
5533 for (unsigned i = 0; i != 8; ++i) {
5534 int EltIdx = MaskVals[i] * 2;
5535 if (TwoInputs && (EltIdx >= 16)) {
5536 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5537 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5540 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5541 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5543 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5544 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5545 DAG.getNode(ISD::BUILD_VECTOR, dl,
5546 MVT::v16i8, &pshufbMask[0], 16));
5548 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5550 // Calculate the shuffle mask for the second input, shuffle it, and
5551 // OR it with the first shuffled input.
5553 for (unsigned i = 0; i != 8; ++i) {
5554 int EltIdx = MaskVals[i] * 2;
5556 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5557 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5560 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5561 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5563 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5564 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5565 DAG.getNode(ISD::BUILD_VECTOR, dl,
5566 MVT::v16i8, &pshufbMask[0], 16));
5567 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5568 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5571 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5572 // and update MaskVals with new element order.
5573 BitVector InOrder(8);
5574 if (BestLoQuad >= 0) {
5575 SmallVector<int, 8> MaskV;
5576 for (int i = 0; i != 4; ++i) {
5577 int idx = MaskVals[i];
5579 MaskV.push_back(-1);
5581 } else if ((idx / 4) == BestLoQuad) {
5582 MaskV.push_back(idx & 3);
5585 MaskV.push_back(-1);
5588 for (unsigned i = 4; i != 8; ++i)
5590 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5593 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5594 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5596 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5600 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5601 // and update MaskVals with the new element order.
5602 if (BestHiQuad >= 0) {
5603 SmallVector<int, 8> MaskV;
5604 for (unsigned i = 0; i != 4; ++i)
5606 for (unsigned i = 4; i != 8; ++i) {
5607 int idx = MaskVals[i];
5609 MaskV.push_back(-1);
5611 } else if ((idx / 4) == BestHiQuad) {
5612 MaskV.push_back((idx & 3) + 4);
5615 MaskV.push_back(-1);
5618 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5621 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5622 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5624 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5628 // In case BestHi & BestLo were both -1, which means each quadword has a word
5629 // from each of the four input quadwords, calculate the InOrder bitvector now
5630 // before falling through to the insert/extract cleanup.
5631 if (BestLoQuad == -1 && BestHiQuad == -1) {
5633 for (int i = 0; i != 8; ++i)
5634 if (MaskVals[i] < 0 || MaskVals[i] == i)
5638 // The other elements are put in the right place using pextrw and pinsrw.
5639 for (unsigned i = 0; i != 8; ++i) {
5642 int EltIdx = MaskVals[i];
5645 SDValue ExtOp = (EltIdx < 8)
5646 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5647 DAG.getIntPtrConstant(EltIdx))
5648 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5649 DAG.getIntPtrConstant(EltIdx - 8));
5650 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5651 DAG.getIntPtrConstant(i));
5656 // v16i8 shuffles - Prefer shuffles in the following order:
5657 // 1. [ssse3] 1 x pshufb
5658 // 2. [ssse3] 2 x pshufb + 1 x por
5659 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5661 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5663 const X86TargetLowering &TLI) {
5664 SDValue V1 = SVOp->getOperand(0);
5665 SDValue V2 = SVOp->getOperand(1);
5666 DebugLoc dl = SVOp->getDebugLoc();
5667 SmallVector<int, 16> MaskVals;
5668 SVOp->getMask(MaskVals);
5670 // If we have SSSE3, case 1 is generated when all result bytes come from
5671 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5672 // present, fall back to case 3.
5673 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5676 for (unsigned i = 0; i < 16; ++i) {
5677 int EltIdx = MaskVals[i];
5686 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5687 if (TLI.getSubtarget()->hasSSSE3()) {
5688 SmallVector<SDValue,16> pshufbMask;
5690 // If all result elements are from one input vector, then only translate
5691 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5693 // Otherwise, we have elements from both input vectors, and must zero out
5694 // elements that come from V2 in the first mask, and V1 in the second mask
5695 // so that we can OR them together.
5696 bool TwoInputs = !(V1Only || V2Only);
5697 for (unsigned i = 0; i != 16; ++i) {
5698 int EltIdx = MaskVals[i];
5699 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5700 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5703 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5705 // If all the elements are from V2, assign it to V1 and return after
5706 // building the first pshufb.
5709 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5710 DAG.getNode(ISD::BUILD_VECTOR, dl,
5711 MVT::v16i8, &pshufbMask[0], 16));
5715 // Calculate the shuffle mask for the second input, shuffle it, and
5716 // OR it with the first shuffled input.
5718 for (unsigned i = 0; i != 16; ++i) {
5719 int EltIdx = MaskVals[i];
5721 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5724 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5726 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5727 DAG.getNode(ISD::BUILD_VECTOR, dl,
5728 MVT::v16i8, &pshufbMask[0], 16));
5729 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5732 // No SSSE3 - Calculate in place words and then fix all out of place words
5733 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5734 // the 16 different words that comprise the two doublequadword input vectors.
5735 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5736 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5737 SDValue NewV = V2Only ? V2 : V1;
5738 for (int i = 0; i != 8; ++i) {
5739 int Elt0 = MaskVals[i*2];
5740 int Elt1 = MaskVals[i*2+1];
5742 // This word of the result is all undef, skip it.
5743 if (Elt0 < 0 && Elt1 < 0)
5746 // This word of the result is already in the correct place, skip it.
5747 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5749 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5752 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5753 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5756 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5757 // using a single extract together, load it and store it.
5758 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5759 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5760 DAG.getIntPtrConstant(Elt1 / 2));
5761 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5762 DAG.getIntPtrConstant(i));
5766 // If Elt1 is defined, extract it from the appropriate source. If the
5767 // source byte is not also odd, shift the extracted word left 8 bits
5768 // otherwise clear the bottom 8 bits if we need to do an or.
5770 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5771 DAG.getIntPtrConstant(Elt1 / 2));
5772 if ((Elt1 & 1) == 0)
5773 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5775 TLI.getShiftAmountTy(InsElt.getValueType())));
5777 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5778 DAG.getConstant(0xFF00, MVT::i16));
5780 // If Elt0 is defined, extract it from the appropriate source. If the
5781 // source byte is not also even, shift the extracted word right 8 bits. If
5782 // Elt1 was also defined, OR the extracted values together before
5783 // inserting them in the result.
5785 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5786 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5787 if ((Elt0 & 1) != 0)
5788 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5790 TLI.getShiftAmountTy(InsElt0.getValueType())));
5792 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5793 DAG.getConstant(0x00FF, MVT::i16));
5794 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5797 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5798 DAG.getIntPtrConstant(i));
5800 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5803 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5804 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5805 /// done when every pair / quad of shuffle mask elements point to elements in
5806 /// the right sequence. e.g.
5807 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5809 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5810 SelectionDAG &DAG, DebugLoc dl) {
5811 EVT VT = SVOp->getValueType(0);
5812 SDValue V1 = SVOp->getOperand(0);
5813 SDValue V2 = SVOp->getOperand(1);
5814 unsigned NumElems = VT.getVectorNumElements();
5815 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5817 switch (VT.getSimpleVT().SimpleTy) {
5818 default: assert(false && "Unexpected!");
5819 case MVT::v4f32: NewVT = MVT::v2f64; break;
5820 case MVT::v4i32: NewVT = MVT::v2i64; break;
5821 case MVT::v8i16: NewVT = MVT::v4i32; break;
5822 case MVT::v16i8: NewVT = MVT::v4i32; break;
5825 int Scale = NumElems / NewWidth;
5826 SmallVector<int, 8> MaskVec;
5827 for (unsigned i = 0; i < NumElems; i += Scale) {
5829 for (int j = 0; j < Scale; ++j) {
5830 int EltIdx = SVOp->getMaskElt(i+j);
5834 StartIdx = EltIdx - (EltIdx % Scale);
5835 if (EltIdx != StartIdx + j)
5839 MaskVec.push_back(-1);
5841 MaskVec.push_back(StartIdx / Scale);
5844 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5845 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5846 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5849 /// getVZextMovL - Return a zero-extending vector move low node.
5851 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5852 SDValue SrcOp, SelectionDAG &DAG,
5853 const X86Subtarget *Subtarget, DebugLoc dl) {
5854 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5855 LoadSDNode *LD = NULL;
5856 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5857 LD = dyn_cast<LoadSDNode>(SrcOp);
5859 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5861 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5862 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5863 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5864 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5865 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5867 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5868 return DAG.getNode(ISD::BITCAST, dl, VT,
5869 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5870 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5878 return DAG.getNode(ISD::BITCAST, dl, VT,
5879 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5880 DAG.getNode(ISD::BITCAST, dl,
5884 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5885 /// shuffle node referes to only one lane in the sources.
5886 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5887 EVT VT = SVOp->getValueType(0);
5888 int NumElems = VT.getVectorNumElements();
5889 int HalfSize = NumElems/2;
5890 SmallVector<int, 16> M;
5892 bool MatchA = false, MatchB = false;
5894 for (int l = 0; l < NumElems*2; l += HalfSize) {
5895 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5901 for (int l = 0; l < NumElems*2; l += HalfSize) {
5902 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5908 return MatchA && MatchB;
5911 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5912 /// which could not be matched by any known target speficic shuffle
5914 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5915 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5916 // If each half of a vector shuffle node referes to only one lane in the
5917 // source vectors, extract each used 128-bit lane and shuffle them using
5918 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5919 // the work to the legalizer.
5920 DebugLoc dl = SVOp->getDebugLoc();
5921 EVT VT = SVOp->getValueType(0);
5922 int NumElems = VT.getVectorNumElements();
5923 int HalfSize = NumElems/2;
5925 // Extract the reference for each half
5926 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5927 int FstVecOpNum = 0, SndVecOpNum = 0;
5928 for (int i = 0; i < HalfSize; ++i) {
5929 int Elt = SVOp->getMaskElt(i);
5930 if (SVOp->getMaskElt(i) < 0)
5932 FstVecOpNum = Elt/NumElems;
5933 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5936 for (int i = HalfSize; i < NumElems; ++i) {
5937 int Elt = SVOp->getMaskElt(i);
5938 if (SVOp->getMaskElt(i) < 0)
5940 SndVecOpNum = Elt/NumElems;
5941 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5945 // Extract the subvectors
5946 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5947 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5948 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5949 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5951 // Generate 128-bit shuffles
5952 SmallVector<int, 16> MaskV1, MaskV2;
5953 for (int i = 0; i < HalfSize; ++i) {
5954 int Elt = SVOp->getMaskElt(i);
5955 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5957 for (int i = HalfSize; i < NumElems; ++i) {
5958 int Elt = SVOp->getMaskElt(i);
5959 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5962 EVT NVT = V1.getValueType();
5963 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5964 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5966 // Concatenate the result back
5967 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5968 DAG.getConstant(0, MVT::i32), DAG, dl);
5969 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5976 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5977 /// 4 elements, and match them with several different shuffle types.
5979 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5980 SDValue V1 = SVOp->getOperand(0);
5981 SDValue V2 = SVOp->getOperand(1);
5982 DebugLoc dl = SVOp->getDebugLoc();
5983 EVT VT = SVOp->getValueType(0);
5985 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5987 SmallVector<std::pair<int, int>, 8> Locs;
5989 SmallVector<int, 8> Mask1(4U, -1);
5990 SmallVector<int, 8> PermMask;
5991 SVOp->getMask(PermMask);
5995 for (unsigned i = 0; i != 4; ++i) {
5996 int Idx = PermMask[i];
5998 Locs[i] = std::make_pair(-1, -1);
6000 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6002 Locs[i] = std::make_pair(0, NumLo);
6006 Locs[i] = std::make_pair(1, NumHi);
6008 Mask1[2+NumHi] = Idx;
6014 if (NumLo <= 2 && NumHi <= 2) {
6015 // If no more than two elements come from either vector. This can be
6016 // implemented with two shuffles. First shuffle gather the elements.
6017 // The second shuffle, which takes the first shuffle as both of its
6018 // vector operands, put the elements into the right order.
6019 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6021 SmallVector<int, 8> Mask2(4U, -1);
6023 for (unsigned i = 0; i != 4; ++i) {
6024 if (Locs[i].first == -1)
6027 unsigned Idx = (i < 2) ? 0 : 4;
6028 Idx += Locs[i].first * 2 + Locs[i].second;
6033 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6034 } else if (NumLo == 3 || NumHi == 3) {
6035 // Otherwise, we must have three elements from one vector, call it X, and
6036 // one element from the other, call it Y. First, use a shufps to build an
6037 // intermediate vector with the one element from Y and the element from X
6038 // that will be in the same half in the final destination (the indexes don't
6039 // matter). Then, use a shufps to build the final vector, taking the half
6040 // containing the element from Y from the intermediate, and the other half
6043 // Normalize it so the 3 elements come from V1.
6044 CommuteVectorShuffleMask(PermMask, VT);
6048 // Find the element from V2.
6050 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6051 int Val = PermMask[HiIndex];
6058 Mask1[0] = PermMask[HiIndex];
6060 Mask1[2] = PermMask[HiIndex^1];
6062 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6065 Mask1[0] = PermMask[0];
6066 Mask1[1] = PermMask[1];
6067 Mask1[2] = HiIndex & 1 ? 6 : 4;
6068 Mask1[3] = HiIndex & 1 ? 4 : 6;
6069 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6071 Mask1[0] = HiIndex & 1 ? 2 : 0;
6072 Mask1[1] = HiIndex & 1 ? 0 : 2;
6073 Mask1[2] = PermMask[2];
6074 Mask1[3] = PermMask[3];
6079 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6083 // Break it into (shuffle shuffle_hi, shuffle_lo).
6086 SmallVector<int,8> LoMask(4U, -1);
6087 SmallVector<int,8> HiMask(4U, -1);
6089 SmallVector<int,8> *MaskPtr = &LoMask;
6090 unsigned MaskIdx = 0;
6093 for (unsigned i = 0; i != 4; ++i) {
6100 int Idx = PermMask[i];
6102 Locs[i] = std::make_pair(-1, -1);
6103 } else if (Idx < 4) {
6104 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6105 (*MaskPtr)[LoIdx] = Idx;
6108 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6109 (*MaskPtr)[HiIdx] = Idx;
6114 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6115 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6116 SmallVector<int, 8> MaskOps;
6117 for (unsigned i = 0; i != 4; ++i) {
6118 if (Locs[i].first == -1) {
6119 MaskOps.push_back(-1);
6121 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6122 MaskOps.push_back(Idx);
6125 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6128 static bool MayFoldVectorLoad(SDValue V) {
6129 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6130 V = V.getOperand(0);
6131 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6132 V = V.getOperand(0);
6138 // FIXME: the version above should always be used. Since there's
6139 // a bug where several vector shuffles can't be folded because the
6140 // DAG is not updated during lowering and a node claims to have two
6141 // uses while it only has one, use this version, and let isel match
6142 // another instruction if the load really happens to have more than
6143 // one use. Remove this version after this bug get fixed.
6144 // rdar://8434668, PR8156
6145 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6146 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6147 V = V.getOperand(0);
6148 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6149 V = V.getOperand(0);
6150 if (ISD::isNormalLoad(V.getNode()))
6155 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6156 /// a vector extract, and if both can be later optimized into a single load.
6157 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6158 /// here because otherwise a target specific shuffle node is going to be
6159 /// emitted for this shuffle, and the optimization not done.
6160 /// FIXME: This is probably not the best approach, but fix the problem
6161 /// until the right path is decided.
6163 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6164 const TargetLowering &TLI) {
6165 EVT VT = V.getValueType();
6166 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6168 // Be sure that the vector shuffle is present in a pattern like this:
6169 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6173 SDNode *N = *V.getNode()->use_begin();
6174 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6177 SDValue EltNo = N->getOperand(1);
6178 if (!isa<ConstantSDNode>(EltNo))
6181 // If the bit convert changed the number of elements, it is unsafe
6182 // to examine the mask.
6183 bool HasShuffleIntoBitcast = false;
6184 if (V.getOpcode() == ISD::BITCAST) {
6185 EVT SrcVT = V.getOperand(0).getValueType();
6186 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6188 V = V.getOperand(0);
6189 HasShuffleIntoBitcast = true;
6192 // Select the input vector, guarding against out of range extract vector.
6193 unsigned NumElems = VT.getVectorNumElements();
6194 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6195 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6196 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6198 // Skip one more bit_convert if necessary
6199 if (V.getOpcode() == ISD::BITCAST)
6200 V = V.getOperand(0);
6202 if (ISD::isNormalLoad(V.getNode())) {
6203 // Is the original load suitable?
6204 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6206 // FIXME: avoid the multi-use bug that is preventing lots of
6207 // of foldings to be detected, this is still wrong of course, but
6208 // give the temporary desired behavior, and if it happens that
6209 // the load has real more uses, during isel it will not fold, and
6210 // will generate poor code.
6211 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6214 if (!HasShuffleIntoBitcast)
6217 // If there's a bitcast before the shuffle, check if the load type and
6218 // alignment is valid.
6219 unsigned Align = LN0->getAlignment();
6221 TLI.getTargetData()->getABITypeAlignment(
6222 VT.getTypeForEVT(*DAG.getContext()));
6224 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6232 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6233 EVT VT = Op.getValueType();
6235 // Canonizalize to v2f64.
6236 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6237 return DAG.getNode(ISD::BITCAST, dl, VT,
6238 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6243 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6245 SDValue V1 = Op.getOperand(0);
6246 SDValue V2 = Op.getOperand(1);
6247 EVT VT = Op.getValueType();
6249 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6251 if (HasSSE2 && VT == MVT::v2f64)
6252 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6254 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6255 return DAG.getNode(ISD::BITCAST, dl, VT,
6256 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6257 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6258 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6262 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6263 SDValue V1 = Op.getOperand(0);
6264 SDValue V2 = Op.getOperand(1);
6265 EVT VT = Op.getValueType();
6267 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6268 "unsupported shuffle type");
6270 if (V2.getOpcode() == ISD::UNDEF)
6274 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6277 static inline unsigned getSHUFPOpcode(EVT VT) {
6278 switch(VT.getSimpleVT().SimpleTy) {
6279 case MVT::v8i32: // Use fp unit for int unpack.
6281 case MVT::v4i32: // Use fp unit for int unpack.
6282 case MVT::v4f32: return X86ISD::SHUFPS;
6283 case MVT::v4i64: // Use fp unit for int unpack.
6285 case MVT::v2i64: // Use fp unit for int unpack.
6286 case MVT::v2f64: return X86ISD::SHUFPD;
6288 llvm_unreachable("Unknown type for shufp*");
6294 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6295 SDValue V1 = Op.getOperand(0);
6296 SDValue V2 = Op.getOperand(1);
6297 EVT VT = Op.getValueType();
6298 unsigned NumElems = VT.getVectorNumElements();
6300 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6301 // operand of these instructions is only memory, so check if there's a
6302 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6304 bool CanFoldLoad = false;
6306 // Trivial case, when V2 comes from a load.
6307 if (MayFoldVectorLoad(V2))
6310 // When V1 is a load, it can be folded later into a store in isel, example:
6311 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6313 // (MOVLPSmr addr:$src1, VR128:$src2)
6314 // So, recognize this potential and also use MOVLPS or MOVLPD
6315 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6318 // Both of them can't be memory operations though.
6319 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6320 CanFoldLoad = false;
6323 if (HasSSE2 && NumElems == 2)
6324 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6327 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6330 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6331 // movl and movlp will both match v2i64, but v2i64 is never matched by
6332 // movl earlier because we make it strict to avoid messing with the movlp load
6333 // folding logic (see the code above getMOVLP call). Match it here then,
6334 // this is horrible, but will stay like this until we move all shuffle
6335 // matching to x86 specific nodes. Note that for the 1st condition all
6336 // types are matched with movsd.
6339 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6340 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6343 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6345 // Invert the operand order and use SHUFPS to match it.
6346 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6347 X86::getShuffleSHUFImmediate(SVOp), DAG);
6350 static inline unsigned getUNPCKLOpcode(EVT VT) {
6351 switch(VT.getSimpleVT().SimpleTy) {
6352 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6353 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6354 case MVT::v4f32: return X86ISD::UNPCKLPS;
6355 case MVT::v2f64: return X86ISD::UNPCKLPD;
6356 case MVT::v8i32: // Use fp unit for int unpack.
6357 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6358 case MVT::v4i64: // Use fp unit for int unpack.
6359 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6360 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6361 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6363 llvm_unreachable("Unknown type for unpckl");
6368 static inline unsigned getUNPCKHOpcode(EVT VT) {
6369 switch(VT.getSimpleVT().SimpleTy) {
6370 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6371 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6372 case MVT::v4f32: return X86ISD::UNPCKHPS;
6373 case MVT::v2f64: return X86ISD::UNPCKHPD;
6374 case MVT::v8i32: // Use fp unit for int unpack.
6375 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6376 case MVT::v4i64: // Use fp unit for int unpack.
6377 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6378 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6379 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6381 llvm_unreachable("Unknown type for unpckh");
6386 static inline unsigned getVPERMILOpcode(EVT VT) {
6387 switch(VT.getSimpleVT().SimpleTy) {
6389 case MVT::v4f32: return X86ISD::VPERMILPS;
6391 case MVT::v2f64: return X86ISD::VPERMILPD;
6393 case MVT::v8f32: return X86ISD::VPERMILPSY;
6395 case MVT::v4f64: return X86ISD::VPERMILPDY;
6397 llvm_unreachable("Unknown type for vpermil");
6402 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6403 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6404 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6405 static bool isVectorBroadcast(SDValue &Op) {
6406 EVT VT = Op.getValueType();
6407 bool Is256 = VT.getSizeInBits() == 256;
6409 assert((VT.getSizeInBits() == 128 || Is256) &&
6410 "Unsupported type for vbroadcast node");
6413 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6414 V = V.getOperand(0);
6416 if (Is256 && !(V.hasOneUse() &&
6417 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6418 V.getOperand(0).getOpcode() == ISD::UNDEF))
6422 V = V.getOperand(1);
6427 // Check the source scalar_to_vector type. 256-bit broadcasts are
6428 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6429 // for 32-bit scalars.
6430 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6433 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6434 if (ScalarSize != 32 && ScalarSize != 64)
6436 if (!Is256 && ScalarSize == 64)
6439 V = V.getOperand(0);
6440 if (!MayFoldLoad(V))
6443 // Return the load node
6449 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6450 const TargetLowering &TLI,
6451 const X86Subtarget *Subtarget) {
6452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6453 EVT VT = Op.getValueType();
6454 DebugLoc dl = Op.getDebugLoc();
6455 SDValue V1 = Op.getOperand(0);
6456 SDValue V2 = Op.getOperand(1);
6458 if (isZeroShuffle(SVOp))
6459 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6461 // Handle splat operations
6462 if (SVOp->isSplat()) {
6463 unsigned NumElem = VT.getVectorNumElements();
6464 int Size = VT.getSizeInBits();
6465 // Special case, this is the only place now where it's allowed to return
6466 // a vector_shuffle operation without using a target specific node, because
6467 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6468 // this be moved to DAGCombine instead?
6469 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6472 // Use vbroadcast whenever the splat comes from a foldable load
6473 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6474 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6476 // Handle splats by matching through known shuffle masks
6477 if ((Size == 128 && NumElem <= 4) ||
6478 (Size == 256 && NumElem < 8))
6481 // All remaning splats are promoted to target supported vector shuffles.
6482 return PromoteSplat(SVOp, DAG);
6485 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6487 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6488 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6489 if (NewOp.getNode())
6490 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6491 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6492 // FIXME: Figure out a cleaner way to do this.
6493 // Try to make use of movq to zero out the top part.
6494 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6495 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6496 if (NewOp.getNode()) {
6497 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6498 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6499 DAG, Subtarget, dl);
6501 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6502 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6503 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6504 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6505 DAG, Subtarget, dl);
6512 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6513 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6514 SDValue V1 = Op.getOperand(0);
6515 SDValue V2 = Op.getOperand(1);
6516 EVT VT = Op.getValueType();
6517 DebugLoc dl = Op.getDebugLoc();
6518 unsigned NumElems = VT.getVectorNumElements();
6519 bool isMMX = VT.getSizeInBits() == 64;
6520 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6521 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6522 bool V1IsSplat = false;
6523 bool V2IsSplat = false;
6524 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6525 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6526 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6527 MachineFunction &MF = DAG.getMachineFunction();
6528 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6530 // Shuffle operations on MMX not supported.
6534 // Vector shuffle lowering takes 3 steps:
6536 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6537 // narrowing and commutation of operands should be handled.
6538 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6540 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6541 // so the shuffle can be broken into other shuffles and the legalizer can
6542 // try the lowering again.
6544 // The general ideia is that no vector_shuffle operation should be left to
6545 // be matched during isel, all of them must be converted to a target specific
6548 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6549 // narrowing and commutation of operands should be handled. The actual code
6550 // doesn't include all of those, work in progress...
6551 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6552 if (NewOp.getNode())
6555 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6556 // unpckh_undef). Only use pshufd if speed is more important than size.
6557 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6558 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6559 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6560 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6562 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6563 RelaxedMayFoldVectorLoad(V1))
6564 return getMOVDDup(Op, dl, V1, DAG);
6566 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6567 return getMOVHighToLow(Op, dl, DAG);
6569 // Use to match splats
6570 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6571 (VT == MVT::v2f64 || VT == MVT::v2i64))
6572 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6574 if (X86::isPSHUFDMask(SVOp)) {
6575 // The actual implementation will match the mask in the if above and then
6576 // during isel it can match several different instructions, not only pshufd
6577 // as its name says, sad but true, emulate the behavior for now...
6578 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6579 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6581 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6583 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6584 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6586 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6590 // Check if this can be converted into a logical shift.
6591 bool isLeft = false;
6594 bool isShift = getSubtarget()->hasSSE2() &&
6595 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6596 if (isShift && ShVal.hasOneUse()) {
6597 // If the shifted value has multiple uses, it may be cheaper to use
6598 // v_set0 + movlhps or movhlps, etc.
6599 EVT EltVT = VT.getVectorElementType();
6600 ShAmt *= EltVT.getSizeInBits();
6601 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6604 if (X86::isMOVLMask(SVOp)) {
6607 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6608 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6609 if (!X86::isMOVLPMask(SVOp)) {
6610 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6611 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6613 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6614 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6618 // FIXME: fold these into legal mask.
6619 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6620 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6622 if (X86::isMOVHLPSMask(SVOp))
6623 return getMOVHighToLow(Op, dl, DAG);
6625 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6626 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6628 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6629 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6631 if (X86::isMOVLPMask(SVOp))
6632 return getMOVLP(Op, dl, DAG, HasSSE2);
6634 if (ShouldXformToMOVHLPS(SVOp) ||
6635 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6636 return CommuteVectorShuffle(SVOp, DAG);
6639 // No better options. Use a vshl / vsrl.
6640 EVT EltVT = VT.getVectorElementType();
6641 ShAmt *= EltVT.getSizeInBits();
6642 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6645 bool Commuted = false;
6646 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6647 // 1,1,1,1 -> v8i16 though.
6648 V1IsSplat = isSplatVector(V1.getNode());
6649 V2IsSplat = isSplatVector(V2.getNode());
6651 // Canonicalize the splat or undef, if present, to be on the RHS.
6652 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6653 Op = CommuteVectorShuffle(SVOp, DAG);
6654 SVOp = cast<ShuffleVectorSDNode>(Op);
6655 V1 = SVOp->getOperand(0);
6656 V2 = SVOp->getOperand(1);
6657 std::swap(V1IsSplat, V2IsSplat);
6658 std::swap(V1IsUndef, V2IsUndef);
6662 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6663 // Shuffling low element of v1 into undef, just return v1.
6666 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6667 // the instruction selector will not match, so get a canonical MOVL with
6668 // swapped operands to undo the commute.
6669 return getMOVL(DAG, dl, VT, V2, V1);
6672 if (X86::isUNPCKLMask(SVOp))
6673 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6675 if (X86::isUNPCKHMask(SVOp))
6676 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6679 // Normalize mask so all entries that point to V2 points to its first
6680 // element then try to match unpck{h|l} again. If match, return a
6681 // new vector_shuffle with the corrected mask.
6682 SDValue NewMask = NormalizeMask(SVOp, DAG);
6683 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6684 if (NSVOp != SVOp) {
6685 if (X86::isUNPCKLMask(NSVOp, true)) {
6687 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6694 // Commute is back and try unpck* again.
6695 // FIXME: this seems wrong.
6696 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6697 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6699 if (X86::isUNPCKLMask(NewSVOp))
6700 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6702 if (X86::isUNPCKHMask(NewSVOp))
6703 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6706 // Normalize the node to match x86 shuffle ops if needed
6707 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6708 return CommuteVectorShuffle(SVOp, DAG);
6710 // The checks below are all present in isShuffleMaskLegal, but they are
6711 // inlined here right now to enable us to directly emit target specific
6712 // nodes, and remove one by one until they don't return Op anymore.
6713 SmallVector<int, 16> M;
6716 if (isPALIGNRMask(M, VT, HasSSSE3))
6717 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6718 X86::getShufflePALIGNRImmediate(SVOp),
6721 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6722 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6723 if (VT == MVT::v2f64)
6724 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6725 if (VT == MVT::v2i64)
6726 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6729 if (isPSHUFHWMask(M, VT))
6730 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6731 X86::getShufflePSHUFHWImmediate(SVOp),
6734 if (isPSHUFLWMask(M, VT))
6735 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6736 X86::getShufflePSHUFLWImmediate(SVOp),
6739 if (isSHUFPMask(M, VT))
6740 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6741 X86::getShuffleSHUFImmediate(SVOp), DAG);
6743 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6744 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6745 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6746 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6748 //===--------------------------------------------------------------------===//
6749 // Generate target specific nodes for 128 or 256-bit shuffles only
6750 // supported in the AVX instruction set.
6753 // Handle VMOVDDUPY permutations
6754 if (isMOVDDUPYMask(SVOp, Subtarget))
6755 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6757 // Handle VPERMILPS* permutations
6758 if (isVPERMILPSMask(M, VT, Subtarget))
6759 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6760 getShuffleVPERMILPSImmediate(SVOp), DAG);
6762 // Handle VPERMILPD* permutations
6763 if (isVPERMILPDMask(M, VT, Subtarget))
6764 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6765 getShuffleVPERMILPDImmediate(SVOp), DAG);
6767 // Handle VPERM2F128 permutations
6768 if (isVPERM2F128Mask(M, VT, Subtarget))
6769 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6770 getShuffleVPERM2F128Immediate(SVOp), DAG);
6772 // Handle VSHUFPSY permutations
6773 if (isVSHUFPSYMask(M, VT, Subtarget))
6774 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6775 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6777 // Handle VSHUFPDY permutations
6778 if (isVSHUFPDYMask(M, VT, Subtarget))
6779 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6780 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6782 //===--------------------------------------------------------------------===//
6783 // Since no target specific shuffle was selected for this generic one,
6784 // lower it into other known shuffles. FIXME: this isn't true yet, but
6785 // this is the plan.
6788 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6789 if (VT == MVT::v8i16) {
6790 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6791 if (NewOp.getNode())
6795 if (VT == MVT::v16i8) {
6796 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6797 if (NewOp.getNode())
6801 // Handle all 128-bit wide vectors with 4 elements, and match them with
6802 // several different shuffle types.
6803 if (NumElems == 4 && VT.getSizeInBits() == 128)
6804 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6806 // Handle general 256-bit shuffles
6807 if (VT.is256BitVector())
6808 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6814 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6815 SelectionDAG &DAG) const {
6816 EVT VT = Op.getValueType();
6817 DebugLoc dl = Op.getDebugLoc();
6819 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6822 if (VT.getSizeInBits() == 8) {
6823 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6824 Op.getOperand(0), Op.getOperand(1));
6825 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6826 DAG.getValueType(VT));
6827 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6828 } else if (VT.getSizeInBits() == 16) {
6829 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6830 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6832 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6833 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6834 DAG.getNode(ISD::BITCAST, dl,
6838 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6839 Op.getOperand(0), Op.getOperand(1));
6840 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6841 DAG.getValueType(VT));
6842 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6843 } else if (VT == MVT::f32) {
6844 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6845 // the result back to FR32 register. It's only worth matching if the
6846 // result has a single use which is a store or a bitcast to i32. And in
6847 // the case of a store, it's not worth it if the index is a constant 0,
6848 // because a MOVSSmr can be used instead, which is smaller and faster.
6849 if (!Op.hasOneUse())
6851 SDNode *User = *Op.getNode()->use_begin();
6852 if ((User->getOpcode() != ISD::STORE ||
6853 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6854 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6855 (User->getOpcode() != ISD::BITCAST ||
6856 User->getValueType(0) != MVT::i32))
6858 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6859 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6862 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6863 } else if (VT == MVT::i32) {
6864 // ExtractPS works with constant index.
6865 if (isa<ConstantSDNode>(Op.getOperand(1)))
6873 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6874 SelectionDAG &DAG) const {
6875 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6878 SDValue Vec = Op.getOperand(0);
6879 EVT VecVT = Vec.getValueType();
6881 // If this is a 256-bit vector result, first extract the 128-bit vector and
6882 // then extract the element from the 128-bit vector.
6883 if (VecVT.getSizeInBits() == 256) {
6884 DebugLoc dl = Op.getNode()->getDebugLoc();
6885 unsigned NumElems = VecVT.getVectorNumElements();
6886 SDValue Idx = Op.getOperand(1);
6887 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6889 // Get the 128-bit vector.
6890 bool Upper = IdxVal >= NumElems/2;
6891 Vec = Extract128BitVector(Vec,
6892 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6894 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6895 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6898 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6900 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6901 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6906 EVT VT = Op.getValueType();
6907 DebugLoc dl = Op.getDebugLoc();
6908 // TODO: handle v16i8.
6909 if (VT.getSizeInBits() == 16) {
6910 SDValue Vec = Op.getOperand(0);
6911 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6913 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6914 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6915 DAG.getNode(ISD::BITCAST, dl,
6918 // Transform it so it match pextrw which produces a 32-bit result.
6919 EVT EltVT = MVT::i32;
6920 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6921 Op.getOperand(0), Op.getOperand(1));
6922 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6923 DAG.getValueType(VT));
6924 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6925 } else if (VT.getSizeInBits() == 32) {
6926 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6930 // SHUFPS the element to the lowest double word, then movss.
6931 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6932 EVT VVT = Op.getOperand(0).getValueType();
6933 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6934 DAG.getUNDEF(VVT), Mask);
6935 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6936 DAG.getIntPtrConstant(0));
6937 } else if (VT.getSizeInBits() == 64) {
6938 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6939 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6940 // to match extract_elt for f64.
6941 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6945 // UNPCKHPD the element to the lowest double word, then movsd.
6946 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6947 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6948 int Mask[2] = { 1, -1 };
6949 EVT VVT = Op.getOperand(0).getValueType();
6950 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6951 DAG.getUNDEF(VVT), Mask);
6952 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6953 DAG.getIntPtrConstant(0));
6960 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6961 SelectionDAG &DAG) const {
6962 EVT VT = Op.getValueType();
6963 EVT EltVT = VT.getVectorElementType();
6964 DebugLoc dl = Op.getDebugLoc();
6966 SDValue N0 = Op.getOperand(0);
6967 SDValue N1 = Op.getOperand(1);
6968 SDValue N2 = Op.getOperand(2);
6970 if (VT.getSizeInBits() == 256)
6973 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6974 isa<ConstantSDNode>(N2)) {
6976 if (VT == MVT::v8i16)
6977 Opc = X86ISD::PINSRW;
6978 else if (VT == MVT::v16i8)
6979 Opc = X86ISD::PINSRB;
6981 Opc = X86ISD::PINSRB;
6983 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6985 if (N1.getValueType() != MVT::i32)
6986 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6987 if (N2.getValueType() != MVT::i32)
6988 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6989 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6990 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6991 // Bits [7:6] of the constant are the source select. This will always be
6992 // zero here. The DAG Combiner may combine an extract_elt index into these
6993 // bits. For example (insert (extract, 3), 2) could be matched by putting
6994 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6995 // Bits [5:4] of the constant are the destination select. This is the
6996 // value of the incoming immediate.
6997 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6998 // combine either bitwise AND or insert of float 0.0 to set these bits.
6999 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7000 // Create this as a scalar to vector..
7001 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7002 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7003 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
7004 // PINSR* works with constant index.
7011 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7012 EVT VT = Op.getValueType();
7013 EVT EltVT = VT.getVectorElementType();
7015 DebugLoc dl = Op.getDebugLoc();
7016 SDValue N0 = Op.getOperand(0);
7017 SDValue N1 = Op.getOperand(1);
7018 SDValue N2 = Op.getOperand(2);
7020 // If this is a 256-bit vector result, first extract the 128-bit vector,
7021 // insert the element into the extracted half and then place it back.
7022 if (VT.getSizeInBits() == 256) {
7023 if (!isa<ConstantSDNode>(N2))
7026 // Get the desired 128-bit vector half.
7027 unsigned NumElems = VT.getVectorNumElements();
7028 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7029 bool Upper = IdxVal >= NumElems/2;
7030 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
7031 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
7033 // Insert the element into the desired half.
7034 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
7035 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
7037 // Insert the changed part back to the 256-bit vector
7038 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
7041 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
7042 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7044 if (EltVT == MVT::i8)
7047 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7048 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7049 // as its second argument.
7050 if (N1.getValueType() != MVT::i32)
7051 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7052 if (N2.getValueType() != MVT::i32)
7053 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7054 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7060 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7061 LLVMContext *Context = DAG.getContext();
7062 DebugLoc dl = Op.getDebugLoc();
7063 EVT OpVT = Op.getValueType();
7065 // If this is a 256-bit vector result, first insert into a 128-bit
7066 // vector and then insert into the 256-bit vector.
7067 if (OpVT.getSizeInBits() > 128) {
7068 // Insert into a 128-bit vector.
7069 EVT VT128 = EVT::getVectorVT(*Context,
7070 OpVT.getVectorElementType(),
7071 OpVT.getVectorNumElements() / 2);
7073 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7075 // Insert the 128-bit vector.
7076 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7077 DAG.getConstant(0, MVT::i32),
7081 if (Op.getValueType() == MVT::v1i64 &&
7082 Op.getOperand(0).getValueType() == MVT::i64)
7083 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7085 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7086 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7087 "Expected an SSE type!");
7088 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7089 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7092 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7093 // a simple subregister reference or explicit instructions to grab
7094 // upper bits of a vector.
7096 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7097 if (Subtarget->hasAVX()) {
7098 DebugLoc dl = Op.getNode()->getDebugLoc();
7099 SDValue Vec = Op.getNode()->getOperand(0);
7100 SDValue Idx = Op.getNode()->getOperand(1);
7102 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7103 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7104 return Extract128BitVector(Vec, Idx, DAG, dl);
7110 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7111 // simple superregister reference or explicit instructions to insert
7112 // the upper bits of a vector.
7114 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7115 if (Subtarget->hasAVX()) {
7116 DebugLoc dl = Op.getNode()->getDebugLoc();
7117 SDValue Vec = Op.getNode()->getOperand(0);
7118 SDValue SubVec = Op.getNode()->getOperand(1);
7119 SDValue Idx = Op.getNode()->getOperand(2);
7121 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7122 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7123 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7129 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7130 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7131 // one of the above mentioned nodes. It has to be wrapped because otherwise
7132 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7133 // be used to form addressing mode. These wrapped nodes will be selected
7136 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7137 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7139 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7141 unsigned char OpFlag = 0;
7142 unsigned WrapperKind = X86ISD::Wrapper;
7143 CodeModel::Model M = getTargetMachine().getCodeModel();
7145 if (Subtarget->isPICStyleRIPRel() &&
7146 (M == CodeModel::Small || M == CodeModel::Kernel))
7147 WrapperKind = X86ISD::WrapperRIP;
7148 else if (Subtarget->isPICStyleGOT())
7149 OpFlag = X86II::MO_GOTOFF;
7150 else if (Subtarget->isPICStyleStubPIC())
7151 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7153 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7155 CP->getOffset(), OpFlag);
7156 DebugLoc DL = CP->getDebugLoc();
7157 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7158 // With PIC, the address is actually $g + Offset.
7160 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7161 DAG.getNode(X86ISD::GlobalBaseReg,
7162 DebugLoc(), getPointerTy()),
7169 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7170 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7172 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7174 unsigned char OpFlag = 0;
7175 unsigned WrapperKind = X86ISD::Wrapper;
7176 CodeModel::Model M = getTargetMachine().getCodeModel();
7178 if (Subtarget->isPICStyleRIPRel() &&
7179 (M == CodeModel::Small || M == CodeModel::Kernel))
7180 WrapperKind = X86ISD::WrapperRIP;
7181 else if (Subtarget->isPICStyleGOT())
7182 OpFlag = X86II::MO_GOTOFF;
7183 else if (Subtarget->isPICStyleStubPIC())
7184 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7186 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7188 DebugLoc DL = JT->getDebugLoc();
7189 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7191 // With PIC, the address is actually $g + Offset.
7193 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7194 DAG.getNode(X86ISD::GlobalBaseReg,
7195 DebugLoc(), getPointerTy()),
7202 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7203 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7205 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7207 unsigned char OpFlag = 0;
7208 unsigned WrapperKind = X86ISD::Wrapper;
7209 CodeModel::Model M = getTargetMachine().getCodeModel();
7211 if (Subtarget->isPICStyleRIPRel() &&
7212 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7213 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7214 OpFlag = X86II::MO_GOTPCREL;
7215 WrapperKind = X86ISD::WrapperRIP;
7216 } else if (Subtarget->isPICStyleGOT()) {
7217 OpFlag = X86II::MO_GOT;
7218 } else if (Subtarget->isPICStyleStubPIC()) {
7219 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7220 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7221 OpFlag = X86II::MO_DARWIN_NONLAZY;
7224 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7226 DebugLoc DL = Op.getDebugLoc();
7227 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7230 // With PIC, the address is actually $g + Offset.
7231 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7232 !Subtarget->is64Bit()) {
7233 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7234 DAG.getNode(X86ISD::GlobalBaseReg,
7235 DebugLoc(), getPointerTy()),
7239 // For symbols that require a load from a stub to get the address, emit the
7241 if (isGlobalStubReference(OpFlag))
7242 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7243 MachinePointerInfo::getGOT(), false, false, 0);
7249 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7250 // Create the TargetBlockAddressAddress node.
7251 unsigned char OpFlags =
7252 Subtarget->ClassifyBlockAddressReference();
7253 CodeModel::Model M = getTargetMachine().getCodeModel();
7254 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7255 DebugLoc dl = Op.getDebugLoc();
7256 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7257 /*isTarget=*/true, OpFlags);
7259 if (Subtarget->isPICStyleRIPRel() &&
7260 (M == CodeModel::Small || M == CodeModel::Kernel))
7261 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7263 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7265 // With PIC, the address is actually $g + Offset.
7266 if (isGlobalRelativeToPICBase(OpFlags)) {
7267 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7268 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7276 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7278 SelectionDAG &DAG) const {
7279 // Create the TargetGlobalAddress node, folding in the constant
7280 // offset if it is legal.
7281 unsigned char OpFlags =
7282 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7283 CodeModel::Model M = getTargetMachine().getCodeModel();
7285 if (OpFlags == X86II::MO_NO_FLAG &&
7286 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7287 // A direct static reference to a global.
7288 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7291 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7294 if (Subtarget->isPICStyleRIPRel() &&
7295 (M == CodeModel::Small || M == CodeModel::Kernel))
7296 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7298 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7300 // With PIC, the address is actually $g + Offset.
7301 if (isGlobalRelativeToPICBase(OpFlags)) {
7302 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7303 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7307 // For globals that require a load from a stub to get the address, emit the
7309 if (isGlobalStubReference(OpFlags))
7310 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7311 MachinePointerInfo::getGOT(), false, false, 0);
7313 // If there was a non-zero offset that we didn't fold, create an explicit
7316 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7317 DAG.getConstant(Offset, getPointerTy()));
7323 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7324 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7325 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7326 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7330 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7331 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7332 unsigned char OperandFlags) {
7333 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7334 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7335 DebugLoc dl = GA->getDebugLoc();
7336 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7337 GA->getValueType(0),
7341 SDValue Ops[] = { Chain, TGA, *InFlag };
7342 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7344 SDValue Ops[] = { Chain, TGA };
7345 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7348 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7349 MFI->setAdjustsStack(true);
7351 SDValue Flag = Chain.getValue(1);
7352 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7355 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7357 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7360 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7361 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7362 DAG.getNode(X86ISD::GlobalBaseReg,
7363 DebugLoc(), PtrVT), InFlag);
7364 InFlag = Chain.getValue(1);
7366 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7369 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7371 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7373 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7374 X86::RAX, X86II::MO_TLSGD);
7377 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7378 // "local exec" model.
7379 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7380 const EVT PtrVT, TLSModel::Model model,
7382 DebugLoc dl = GA->getDebugLoc();
7384 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7385 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7386 is64Bit ? 257 : 256));
7388 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7389 DAG.getIntPtrConstant(0),
7390 MachinePointerInfo(Ptr), false, false, 0);
7392 unsigned char OperandFlags = 0;
7393 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7395 unsigned WrapperKind = X86ISD::Wrapper;
7396 if (model == TLSModel::LocalExec) {
7397 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7398 } else if (is64Bit) {
7399 assert(model == TLSModel::InitialExec);
7400 OperandFlags = X86II::MO_GOTTPOFF;
7401 WrapperKind = X86ISD::WrapperRIP;
7403 assert(model == TLSModel::InitialExec);
7404 OperandFlags = X86II::MO_INDNTPOFF;
7407 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7409 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7410 GA->getValueType(0),
7411 GA->getOffset(), OperandFlags);
7412 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7414 if (model == TLSModel::InitialExec)
7415 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7416 MachinePointerInfo::getGOT(), false, false, 0);
7418 // The address of the thread local variable is the add of the thread
7419 // pointer with the offset of the variable.
7420 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7424 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7426 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7427 const GlobalValue *GV = GA->getGlobal();
7429 if (Subtarget->isTargetELF()) {
7430 // TODO: implement the "local dynamic" model
7431 // TODO: implement the "initial exec"model for pic executables
7433 // If GV is an alias then use the aliasee for determining
7434 // thread-localness.
7435 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7436 GV = GA->resolveAliasedGlobal(false);
7438 TLSModel::Model model
7439 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7442 case TLSModel::GeneralDynamic:
7443 case TLSModel::LocalDynamic: // not implemented
7444 if (Subtarget->is64Bit())
7445 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7446 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7448 case TLSModel::InitialExec:
7449 case TLSModel::LocalExec:
7450 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7451 Subtarget->is64Bit());
7453 } else if (Subtarget->isTargetDarwin()) {
7454 // Darwin only has one model of TLS. Lower to that.
7455 unsigned char OpFlag = 0;
7456 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7457 X86ISD::WrapperRIP : X86ISD::Wrapper;
7459 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7461 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7462 !Subtarget->is64Bit();
7464 OpFlag = X86II::MO_TLVP_PIC_BASE;
7466 OpFlag = X86II::MO_TLVP;
7467 DebugLoc DL = Op.getDebugLoc();
7468 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7469 GA->getValueType(0),
7470 GA->getOffset(), OpFlag);
7471 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7473 // With PIC32, the address is actually $g + Offset.
7475 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7476 DAG.getNode(X86ISD::GlobalBaseReg,
7477 DebugLoc(), getPointerTy()),
7480 // Lowering the machine isd will make sure everything is in the right
7482 SDValue Chain = DAG.getEntryNode();
7483 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7484 SDValue Args[] = { Chain, Offset };
7485 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7487 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7488 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7489 MFI->setAdjustsStack(true);
7491 // And our return value (tls address) is in the standard call return value
7493 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7494 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7498 "TLS not implemented for this target.");
7500 llvm_unreachable("Unreachable");
7505 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7506 /// take a 2 x i32 value to shift plus a shift amount.
7507 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7508 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7509 EVT VT = Op.getValueType();
7510 unsigned VTBits = VT.getSizeInBits();
7511 DebugLoc dl = Op.getDebugLoc();
7512 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7513 SDValue ShOpLo = Op.getOperand(0);
7514 SDValue ShOpHi = Op.getOperand(1);
7515 SDValue ShAmt = Op.getOperand(2);
7516 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7517 DAG.getConstant(VTBits - 1, MVT::i8))
7518 : DAG.getConstant(0, VT);
7521 if (Op.getOpcode() == ISD::SHL_PARTS) {
7522 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7523 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7525 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7526 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7529 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7530 DAG.getConstant(VTBits, MVT::i8));
7531 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7532 AndNode, DAG.getConstant(0, MVT::i8));
7535 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7536 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7537 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7539 if (Op.getOpcode() == ISD::SHL_PARTS) {
7540 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7541 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7543 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7544 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7547 SDValue Ops[2] = { Lo, Hi };
7548 return DAG.getMergeValues(Ops, 2, dl);
7551 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7552 SelectionDAG &DAG) const {
7553 EVT SrcVT = Op.getOperand(0).getValueType();
7555 if (SrcVT.isVector())
7558 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7559 "Unknown SINT_TO_FP to lower!");
7561 // These are really Legal; return the operand so the caller accepts it as
7563 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7565 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7566 Subtarget->is64Bit()) {
7570 DebugLoc dl = Op.getDebugLoc();
7571 unsigned Size = SrcVT.getSizeInBits()/8;
7572 MachineFunction &MF = DAG.getMachineFunction();
7573 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7574 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7575 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7577 MachinePointerInfo::getFixedStack(SSFI),
7579 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7582 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7584 SelectionDAG &DAG) const {
7586 DebugLoc DL = Op.getDebugLoc();
7588 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7590 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7592 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7594 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7596 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7597 MachineMemOperand *MMO;
7599 int SSFI = FI->getIndex();
7601 DAG.getMachineFunction()
7602 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7603 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7605 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7606 StackSlot = StackSlot.getOperand(1);
7608 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7609 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7611 Tys, Ops, array_lengthof(Ops),
7615 Chain = Result.getValue(1);
7616 SDValue InFlag = Result.getValue(2);
7618 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7619 // shouldn't be necessary except that RFP cannot be live across
7620 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7621 MachineFunction &MF = DAG.getMachineFunction();
7622 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7623 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7624 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7625 Tys = DAG.getVTList(MVT::Other);
7627 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7629 MachineMemOperand *MMO =
7630 DAG.getMachineFunction()
7631 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7632 MachineMemOperand::MOStore, SSFISize, SSFISize);
7634 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7635 Ops, array_lengthof(Ops),
7636 Op.getValueType(), MMO);
7637 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7638 MachinePointerInfo::getFixedStack(SSFI),
7645 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7646 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7647 SelectionDAG &DAG) const {
7648 // This algorithm is not obvious. Here it is in C code, more or less:
7650 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7651 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7652 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7654 // Copy ints to xmm registers.
7655 __m128i xh = _mm_cvtsi32_si128( hi );
7656 __m128i xl = _mm_cvtsi32_si128( lo );
7658 // Combine into low half of a single xmm register.
7659 __m128i x = _mm_unpacklo_epi32( xh, xl );
7663 // Merge in appropriate exponents to give the integer bits the right
7665 x = _mm_unpacklo_epi32( x, exp );
7667 // Subtract away the biases to deal with the IEEE-754 double precision
7669 d = _mm_sub_pd( (__m128d) x, bias );
7671 // All conversions up to here are exact. The correctly rounded result is
7672 // calculated using the current rounding mode using the following
7674 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7675 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7676 // store doesn't really need to be here (except
7677 // maybe to zero the other double)
7682 DebugLoc dl = Op.getDebugLoc();
7683 LLVMContext *Context = DAG.getContext();
7685 // Build some magic constants.
7686 std::vector<Constant*> CV0;
7687 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7688 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7689 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7690 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7691 Constant *C0 = ConstantVector::get(CV0);
7692 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7694 std::vector<Constant*> CV1;
7696 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7698 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7699 Constant *C1 = ConstantVector::get(CV1);
7700 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7702 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7703 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7705 DAG.getIntPtrConstant(1)));
7706 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7707 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7709 DAG.getIntPtrConstant(0)));
7710 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7711 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7712 MachinePointerInfo::getConstantPool(),
7714 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7715 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7716 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7717 MachinePointerInfo::getConstantPool(),
7719 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7721 // Add the halves; easiest way is to swap them into another reg first.
7722 int ShufMask[2] = { 1, -1 };
7723 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7724 DAG.getUNDEF(MVT::v2f64), ShufMask);
7725 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7726 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7727 DAG.getIntPtrConstant(0));
7730 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7731 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7732 SelectionDAG &DAG) const {
7733 DebugLoc dl = Op.getDebugLoc();
7734 // FP constant to bias correct the final result.
7735 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7738 // Load the 32-bit value into an XMM register.
7739 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7742 // Zero out the upper parts of the register.
7743 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasSSE2(), DAG);
7745 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7746 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7747 DAG.getIntPtrConstant(0));
7749 // Or the load with the bias.
7750 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7751 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7752 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7754 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7755 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7756 MVT::v2f64, Bias)));
7757 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7758 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7759 DAG.getIntPtrConstant(0));
7761 // Subtract the bias.
7762 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7764 // Handle final rounding.
7765 EVT DestVT = Op.getValueType();
7767 if (DestVT.bitsLT(MVT::f64)) {
7768 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7769 DAG.getIntPtrConstant(0));
7770 } else if (DestVT.bitsGT(MVT::f64)) {
7771 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7774 // Handle final rounding.
7778 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7779 SelectionDAG &DAG) const {
7780 SDValue N0 = Op.getOperand(0);
7781 DebugLoc dl = Op.getDebugLoc();
7783 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7784 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7785 // the optimization here.
7786 if (DAG.SignBitIsZero(N0))
7787 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7789 EVT SrcVT = N0.getValueType();
7790 EVT DstVT = Op.getValueType();
7791 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7792 return LowerUINT_TO_FP_i64(Op, DAG);
7793 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7794 return LowerUINT_TO_FP_i32(Op, DAG);
7796 // Make a 64-bit buffer, and use it to build an FILD.
7797 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7798 if (SrcVT == MVT::i32) {
7799 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7800 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7801 getPointerTy(), StackSlot, WordOff);
7802 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7803 StackSlot, MachinePointerInfo(),
7805 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7806 OffsetSlot, MachinePointerInfo(),
7808 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7812 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7813 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7814 StackSlot, MachinePointerInfo(),
7816 // For i64 source, we need to add the appropriate power of 2 if the input
7817 // was negative. This is the same as the optimization in
7818 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7819 // we must be careful to do the computation in x87 extended precision, not
7820 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7821 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7822 MachineMemOperand *MMO =
7823 DAG.getMachineFunction()
7824 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7825 MachineMemOperand::MOLoad, 8, 8);
7827 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7828 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7829 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7832 APInt FF(32, 0x5F800000ULL);
7834 // Check whether the sign bit is set.
7835 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7836 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7839 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7840 SDValue FudgePtr = DAG.getConstantPool(
7841 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7844 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7845 SDValue Zero = DAG.getIntPtrConstant(0);
7846 SDValue Four = DAG.getIntPtrConstant(4);
7847 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7849 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7851 // Load the value out, extending it from f32 to f80.
7852 // FIXME: Avoid the extend by constructing the right constant pool?
7853 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7854 FudgePtr, MachinePointerInfo::getConstantPool(),
7855 MVT::f32, false, false, 4);
7856 // Extend everything to 80 bits to force it to be done on x87.
7857 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7858 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7861 std::pair<SDValue,SDValue> X86TargetLowering::
7862 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7863 DebugLoc DL = Op.getDebugLoc();
7865 EVT DstTy = Op.getValueType();
7868 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7872 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7873 DstTy.getSimpleVT() >= MVT::i16 &&
7874 "Unknown FP_TO_SINT to lower!");
7876 // These are really Legal.
7877 if (DstTy == MVT::i32 &&
7878 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7879 return std::make_pair(SDValue(), SDValue());
7880 if (Subtarget->is64Bit() &&
7881 DstTy == MVT::i64 &&
7882 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7883 return std::make_pair(SDValue(), SDValue());
7885 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7887 MachineFunction &MF = DAG.getMachineFunction();
7888 unsigned MemSize = DstTy.getSizeInBits()/8;
7889 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7890 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7895 switch (DstTy.getSimpleVT().SimpleTy) {
7896 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7897 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7898 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7899 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7902 SDValue Chain = DAG.getEntryNode();
7903 SDValue Value = Op.getOperand(0);
7904 EVT TheVT = Op.getOperand(0).getValueType();
7905 if (isScalarFPTypeInSSEReg(TheVT)) {
7906 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7907 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7908 MachinePointerInfo::getFixedStack(SSFI),
7910 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7912 Chain, StackSlot, DAG.getValueType(TheVT)
7915 MachineMemOperand *MMO =
7916 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7917 MachineMemOperand::MOLoad, MemSize, MemSize);
7918 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7920 Chain = Value.getValue(1);
7921 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7922 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7925 MachineMemOperand *MMO =
7926 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7927 MachineMemOperand::MOStore, MemSize, MemSize);
7929 // Build the FP_TO_INT*_IN_MEM
7930 SDValue Ops[] = { Chain, Value, StackSlot };
7931 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7932 Ops, 3, DstTy, MMO);
7934 return std::make_pair(FIST, StackSlot);
7937 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7938 SelectionDAG &DAG) const {
7939 if (Op.getValueType().isVector())
7942 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7943 SDValue FIST = Vals.first, StackSlot = Vals.second;
7944 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7945 if (FIST.getNode() == 0) return Op;
7948 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7949 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7952 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7953 SelectionDAG &DAG) const {
7954 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7955 SDValue FIST = Vals.first, StackSlot = Vals.second;
7956 assert(FIST.getNode() && "Unexpected failure");
7959 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7960 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7963 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7964 SelectionDAG &DAG) const {
7965 LLVMContext *Context = DAG.getContext();
7966 DebugLoc dl = Op.getDebugLoc();
7967 EVT VT = Op.getValueType();
7970 EltVT = VT.getVectorElementType();
7971 std::vector<Constant*> CV;
7972 if (EltVT == MVT::f64) {
7973 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7977 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7983 Constant *C = ConstantVector::get(CV);
7984 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7985 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7986 MachinePointerInfo::getConstantPool(),
7988 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7991 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7992 LLVMContext *Context = DAG.getContext();
7993 DebugLoc dl = Op.getDebugLoc();
7994 EVT VT = Op.getValueType();
7997 EltVT = VT.getVectorElementType();
7998 std::vector<Constant*> CV;
7999 if (EltVT == MVT::f64) {
8000 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8004 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8010 Constant *C = ConstantVector::get(CV);
8011 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8012 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8013 MachinePointerInfo::getConstantPool(),
8015 if (VT.isVector()) {
8016 return DAG.getNode(ISD::BITCAST, dl, VT,
8017 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
8018 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8020 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
8022 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8026 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8027 LLVMContext *Context = DAG.getContext();
8028 SDValue Op0 = Op.getOperand(0);
8029 SDValue Op1 = Op.getOperand(1);
8030 DebugLoc dl = Op.getDebugLoc();
8031 EVT VT = Op.getValueType();
8032 EVT SrcVT = Op1.getValueType();
8034 // If second operand is smaller, extend it first.
8035 if (SrcVT.bitsLT(VT)) {
8036 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8039 // And if it is bigger, shrink it first.
8040 if (SrcVT.bitsGT(VT)) {
8041 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8045 // At this point the operands and the result should have the same
8046 // type, and that won't be f80 since that is not custom lowered.
8048 // First get the sign bit of second operand.
8049 std::vector<Constant*> CV;
8050 if (SrcVT == MVT::f64) {
8051 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8052 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8054 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8055 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8056 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8057 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8059 Constant *C = ConstantVector::get(CV);
8060 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8061 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8062 MachinePointerInfo::getConstantPool(),
8064 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8066 // Shift sign bit right or left if the two operands have different types.
8067 if (SrcVT.bitsGT(VT)) {
8068 // Op0 is MVT::f32, Op1 is MVT::f64.
8069 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8070 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8071 DAG.getConstant(32, MVT::i32));
8072 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8073 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8074 DAG.getIntPtrConstant(0));
8077 // Clear first operand sign bit.
8079 if (VT == MVT::f64) {
8080 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8081 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8083 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8084 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8085 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8086 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8088 C = ConstantVector::get(CV);
8089 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8090 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8091 MachinePointerInfo::getConstantPool(),
8093 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8095 // Or the value with the sign bit.
8096 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8099 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8100 SDValue N0 = Op.getOperand(0);
8101 DebugLoc dl = Op.getDebugLoc();
8102 EVT VT = Op.getValueType();
8104 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8105 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8106 DAG.getConstant(1, VT));
8107 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8110 /// Emit nodes that will be selected as "test Op0,Op0", or something
8112 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8113 SelectionDAG &DAG) const {
8114 DebugLoc dl = Op.getDebugLoc();
8116 // CF and OF aren't always set the way we want. Determine which
8117 // of these we need.
8118 bool NeedCF = false;
8119 bool NeedOF = false;
8122 case X86::COND_A: case X86::COND_AE:
8123 case X86::COND_B: case X86::COND_BE:
8126 case X86::COND_G: case X86::COND_GE:
8127 case X86::COND_L: case X86::COND_LE:
8128 case X86::COND_O: case X86::COND_NO:
8133 // See if we can use the EFLAGS value from the operand instead of
8134 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8135 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8136 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8137 // Emit a CMP with 0, which is the TEST pattern.
8138 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8139 DAG.getConstant(0, Op.getValueType()));
8141 unsigned Opcode = 0;
8142 unsigned NumOperands = 0;
8143 switch (Op.getNode()->getOpcode()) {
8145 // Due to an isel shortcoming, be conservative if this add is likely to be
8146 // selected as part of a load-modify-store instruction. When the root node
8147 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8148 // uses of other nodes in the match, such as the ADD in this case. This
8149 // leads to the ADD being left around and reselected, with the result being
8150 // two adds in the output. Alas, even if none our users are stores, that
8151 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8152 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8153 // climbing the DAG back to the root, and it doesn't seem to be worth the
8155 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8156 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8157 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8160 if (ConstantSDNode *C =
8161 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8162 // An add of one will be selected as an INC.
8163 if (C->getAPIntValue() == 1) {
8164 Opcode = X86ISD::INC;
8169 // An add of negative one (subtract of one) will be selected as a DEC.
8170 if (C->getAPIntValue().isAllOnesValue()) {
8171 Opcode = X86ISD::DEC;
8177 // Otherwise use a regular EFLAGS-setting add.
8178 Opcode = X86ISD::ADD;
8182 // If the primary and result isn't used, don't bother using X86ISD::AND,
8183 // because a TEST instruction will be better.
8184 bool NonFlagUse = false;
8185 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8186 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8188 unsigned UOpNo = UI.getOperandNo();
8189 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8190 // Look pass truncate.
8191 UOpNo = User->use_begin().getOperandNo();
8192 User = *User->use_begin();
8195 if (User->getOpcode() != ISD::BRCOND &&
8196 User->getOpcode() != ISD::SETCC &&
8197 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8210 // Due to the ISEL shortcoming noted above, be conservative if this op is
8211 // likely to be selected as part of a load-modify-store instruction.
8212 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8213 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8214 if (UI->getOpcode() == ISD::STORE)
8217 // Otherwise use a regular EFLAGS-setting instruction.
8218 switch (Op.getNode()->getOpcode()) {
8219 default: llvm_unreachable("unexpected operator!");
8220 case ISD::SUB: Opcode = X86ISD::SUB; break;
8221 case ISD::OR: Opcode = X86ISD::OR; break;
8222 case ISD::XOR: Opcode = X86ISD::XOR; break;
8223 case ISD::AND: Opcode = X86ISD::AND; break;
8235 return SDValue(Op.getNode(), 1);
8242 // Emit a CMP with 0, which is the TEST pattern.
8243 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8244 DAG.getConstant(0, Op.getValueType()));
8246 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8247 SmallVector<SDValue, 4> Ops;
8248 for (unsigned i = 0; i != NumOperands; ++i)
8249 Ops.push_back(Op.getOperand(i));
8251 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8252 DAG.ReplaceAllUsesWith(Op, New);
8253 return SDValue(New.getNode(), 1);
8256 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8258 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8259 SelectionDAG &DAG) const {
8260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8261 if (C->getAPIntValue() == 0)
8262 return EmitTest(Op0, X86CC, DAG);
8264 DebugLoc dl = Op0.getDebugLoc();
8265 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8268 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8269 /// if it's possible.
8270 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8271 DebugLoc dl, SelectionDAG &DAG) const {
8272 SDValue Op0 = And.getOperand(0);
8273 SDValue Op1 = And.getOperand(1);
8274 if (Op0.getOpcode() == ISD::TRUNCATE)
8275 Op0 = Op0.getOperand(0);
8276 if (Op1.getOpcode() == ISD::TRUNCATE)
8277 Op1 = Op1.getOperand(0);
8280 if (Op1.getOpcode() == ISD::SHL)
8281 std::swap(Op0, Op1);
8282 if (Op0.getOpcode() == ISD::SHL) {
8283 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8284 if (And00C->getZExtValue() == 1) {
8285 // If we looked past a truncate, check that it's only truncating away
8287 unsigned BitWidth = Op0.getValueSizeInBits();
8288 unsigned AndBitWidth = And.getValueSizeInBits();
8289 if (BitWidth > AndBitWidth) {
8290 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8291 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8292 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8296 RHS = Op0.getOperand(1);
8298 } else if (Op1.getOpcode() == ISD::Constant) {
8299 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8300 SDValue AndLHS = Op0;
8301 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8302 LHS = AndLHS.getOperand(0);
8303 RHS = AndLHS.getOperand(1);
8307 if (LHS.getNode()) {
8308 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8309 // instruction. Since the shift amount is in-range-or-undefined, we know
8310 // that doing a bittest on the i32 value is ok. We extend to i32 because
8311 // the encoding for the i16 version is larger than the i32 version.
8312 // Also promote i16 to i32 for performance / code size reason.
8313 if (LHS.getValueType() == MVT::i8 ||
8314 LHS.getValueType() == MVT::i16)
8315 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8317 // If the operand types disagree, extend the shift amount to match. Since
8318 // BT ignores high bits (like shifts) we can use anyextend.
8319 if (LHS.getValueType() != RHS.getValueType())
8320 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8322 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8323 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8324 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8325 DAG.getConstant(Cond, MVT::i8), BT);
8331 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8333 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8335 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8336 SDValue Op0 = Op.getOperand(0);
8337 SDValue Op1 = Op.getOperand(1);
8338 DebugLoc dl = Op.getDebugLoc();
8339 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8341 // Optimize to BT if possible.
8342 // Lower (X & (1 << N)) == 0 to BT(X, N).
8343 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8344 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8345 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8346 Op1.getOpcode() == ISD::Constant &&
8347 cast<ConstantSDNode>(Op1)->isNullValue() &&
8348 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8349 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8350 if (NewSetCC.getNode())
8354 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8356 if (Op1.getOpcode() == ISD::Constant &&
8357 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8358 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8359 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8361 // If the input is a setcc, then reuse the input setcc or use a new one with
8362 // the inverted condition.
8363 if (Op0.getOpcode() == X86ISD::SETCC) {
8364 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8365 bool Invert = (CC == ISD::SETNE) ^
8366 cast<ConstantSDNode>(Op1)->isNullValue();
8367 if (!Invert) return Op0;
8369 CCode = X86::GetOppositeBranchCondition(CCode);
8370 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8371 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8375 bool isFP = Op1.getValueType().isFloatingPoint();
8376 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8377 if (X86CC == X86::COND_INVALID)
8380 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8381 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8382 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8385 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8386 // ones, and then concatenate the result back.
8387 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8388 EVT VT = Op.getValueType();
8390 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8391 "Unsupported value type for operation");
8393 int NumElems = VT.getVectorNumElements();
8394 DebugLoc dl = Op.getDebugLoc();
8395 SDValue CC = Op.getOperand(2);
8396 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8397 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8399 // Extract the LHS vectors
8400 SDValue LHS = Op.getOperand(0);
8401 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8402 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8404 // Extract the RHS vectors
8405 SDValue RHS = Op.getOperand(1);
8406 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8407 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8409 // Issue the operation on the smaller types and concatenate the result back
8410 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8411 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8412 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8413 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8414 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8418 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8420 SDValue Op0 = Op.getOperand(0);
8421 SDValue Op1 = Op.getOperand(1);
8422 SDValue CC = Op.getOperand(2);
8423 EVT VT = Op.getValueType();
8424 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8425 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8426 DebugLoc dl = Op.getDebugLoc();
8430 EVT EltVT = Op0.getValueType().getVectorElementType();
8431 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8433 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8436 switch (SetCCOpcode) {
8439 case ISD::SETEQ: SSECC = 0; break;
8441 case ISD::SETGT: Swap = true; // Fallthrough
8443 case ISD::SETOLT: SSECC = 1; break;
8445 case ISD::SETGE: Swap = true; // Fallthrough
8447 case ISD::SETOLE: SSECC = 2; break;
8448 case ISD::SETUO: SSECC = 3; break;
8450 case ISD::SETNE: SSECC = 4; break;
8451 case ISD::SETULE: Swap = true;
8452 case ISD::SETUGE: SSECC = 5; break;
8453 case ISD::SETULT: Swap = true;
8454 case ISD::SETUGT: SSECC = 6; break;
8455 case ISD::SETO: SSECC = 7; break;
8458 std::swap(Op0, Op1);
8460 // In the two special cases we can't handle, emit two comparisons.
8462 if (SetCCOpcode == ISD::SETUEQ) {
8464 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8465 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8466 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8468 else if (SetCCOpcode == ISD::SETONE) {
8470 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8471 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8472 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8474 llvm_unreachable("Illegal FP comparison");
8476 // Handle all other FP comparisons here.
8477 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8480 // Break 256-bit integer vector compare into smaller ones.
8481 if (!isFP && VT.getSizeInBits() == 256)
8482 return Lower256IntVETCC(Op, DAG);
8484 // We are handling one of the integer comparisons here. Since SSE only has
8485 // GT and EQ comparisons for integer, swapping operands and multiple
8486 // operations may be required for some comparisons.
8487 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8488 bool Swap = false, Invert = false, FlipSigns = false;
8490 switch (VT.getSimpleVT().SimpleTy) {
8492 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8493 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8494 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8495 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8498 switch (SetCCOpcode) {
8500 case ISD::SETNE: Invert = true;
8501 case ISD::SETEQ: Opc = EQOpc; break;
8502 case ISD::SETLT: Swap = true;
8503 case ISD::SETGT: Opc = GTOpc; break;
8504 case ISD::SETGE: Swap = true;
8505 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8506 case ISD::SETULT: Swap = true;
8507 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8508 case ISD::SETUGE: Swap = true;
8509 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8512 std::swap(Op0, Op1);
8514 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8515 // bits of the inputs before performing those operations.
8517 EVT EltVT = VT.getVectorElementType();
8518 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8520 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8521 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8523 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8524 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8527 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8529 // If the logical-not of the result is required, perform that now.
8531 Result = DAG.getNOT(dl, Result, VT);
8536 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8537 static bool isX86LogicalCmp(SDValue Op) {
8538 unsigned Opc = Op.getNode()->getOpcode();
8539 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8541 if (Op.getResNo() == 1 &&
8542 (Opc == X86ISD::ADD ||
8543 Opc == X86ISD::SUB ||
8544 Opc == X86ISD::ADC ||
8545 Opc == X86ISD::SBB ||
8546 Opc == X86ISD::SMUL ||
8547 Opc == X86ISD::UMUL ||
8548 Opc == X86ISD::INC ||
8549 Opc == X86ISD::DEC ||
8550 Opc == X86ISD::OR ||
8551 Opc == X86ISD::XOR ||
8552 Opc == X86ISD::AND))
8555 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8561 static bool isZero(SDValue V) {
8562 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8563 return C && C->isNullValue();
8566 static bool isAllOnes(SDValue V) {
8567 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8568 return C && C->isAllOnesValue();
8571 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8572 bool addTest = true;
8573 SDValue Cond = Op.getOperand(0);
8574 SDValue Op1 = Op.getOperand(1);
8575 SDValue Op2 = Op.getOperand(2);
8576 DebugLoc DL = Op.getDebugLoc();
8579 if (Cond.getOpcode() == ISD::SETCC) {
8580 SDValue NewCond = LowerSETCC(Cond, DAG);
8581 if (NewCond.getNode())
8585 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8586 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8587 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8588 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8589 if (Cond.getOpcode() == X86ISD::SETCC &&
8590 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8591 isZero(Cond.getOperand(1).getOperand(1))) {
8592 SDValue Cmp = Cond.getOperand(1);
8594 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8596 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8597 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8598 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8600 SDValue CmpOp0 = Cmp.getOperand(0);
8601 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8602 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8604 SDValue Res = // Res = 0 or -1.
8605 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8606 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8608 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8609 Res = DAG.getNOT(DL, Res, Res.getValueType());
8611 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8612 if (N2C == 0 || !N2C->isNullValue())
8613 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8618 // Look past (and (setcc_carry (cmp ...)), 1).
8619 if (Cond.getOpcode() == ISD::AND &&
8620 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8622 if (C && C->getAPIntValue() == 1)
8623 Cond = Cond.getOperand(0);
8626 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8627 // setting operand in place of the X86ISD::SETCC.
8628 if (Cond.getOpcode() == X86ISD::SETCC ||
8629 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8630 CC = Cond.getOperand(0);
8632 SDValue Cmp = Cond.getOperand(1);
8633 unsigned Opc = Cmp.getOpcode();
8634 EVT VT = Op.getValueType();
8636 bool IllegalFPCMov = false;
8637 if (VT.isFloatingPoint() && !VT.isVector() &&
8638 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8639 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8641 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8642 Opc == X86ISD::BT) { // FIXME
8649 // Look pass the truncate.
8650 if (Cond.getOpcode() == ISD::TRUNCATE)
8651 Cond = Cond.getOperand(0);
8653 // We know the result of AND is compared against zero. Try to match
8655 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8656 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8657 if (NewSetCC.getNode()) {
8658 CC = NewSetCC.getOperand(0);
8659 Cond = NewSetCC.getOperand(1);
8666 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8667 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8670 // a < b ? -1 : 0 -> RES = ~setcc_carry
8671 // a < b ? 0 : -1 -> RES = setcc_carry
8672 // a >= b ? -1 : 0 -> RES = setcc_carry
8673 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8674 if (Cond.getOpcode() == X86ISD::CMP) {
8675 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8677 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8678 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8679 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8680 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8681 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8682 return DAG.getNOT(DL, Res, Res.getValueType());
8687 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8688 // condition is true.
8689 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8690 SDValue Ops[] = { Op2, Op1, CC, Cond };
8691 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8694 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
8695 SDValue Cond = Op.getOperand(0);
8696 SDValue Op1 = Op.getOperand(1);
8697 SDValue Op2 = Op.getOperand(2);
8698 DebugLoc DL = Op.getDebugLoc();
8700 SDValue Ops[] = {Cond, Op1, Op2};
8702 assert(Op1.getValueType().isVector() && "Op1 must be a vector");
8703 assert(Op2.getValueType().isVector() && "Op2 must be a vector");
8704 assert(Cond.getValueType().isVector() && "Cond must be a vector");
8705 assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
8707 switch (Op1.getValueType().getSimpleVT().SimpleTy) {
8709 case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
8710 case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
8711 case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
8712 case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
8713 case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
8720 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8721 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8722 // from the AND / OR.
8723 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8724 Opc = Op.getOpcode();
8725 if (Opc != ISD::OR && Opc != ISD::AND)
8727 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8728 Op.getOperand(0).hasOneUse() &&
8729 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8730 Op.getOperand(1).hasOneUse());
8733 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8734 // 1 and that the SETCC node has a single use.
8735 static bool isXor1OfSetCC(SDValue Op) {
8736 if (Op.getOpcode() != ISD::XOR)
8738 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8739 if (N1C && N1C->getAPIntValue() == 1) {
8740 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8741 Op.getOperand(0).hasOneUse();
8746 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8747 bool addTest = true;
8748 SDValue Chain = Op.getOperand(0);
8749 SDValue Cond = Op.getOperand(1);
8750 SDValue Dest = Op.getOperand(2);
8751 DebugLoc dl = Op.getDebugLoc();
8754 if (Cond.getOpcode() == ISD::SETCC) {
8755 SDValue NewCond = LowerSETCC(Cond, DAG);
8756 if (NewCond.getNode())
8760 // FIXME: LowerXALUO doesn't handle these!!
8761 else if (Cond.getOpcode() == X86ISD::ADD ||
8762 Cond.getOpcode() == X86ISD::SUB ||
8763 Cond.getOpcode() == X86ISD::SMUL ||
8764 Cond.getOpcode() == X86ISD::UMUL)
8765 Cond = LowerXALUO(Cond, DAG);
8768 // Look pass (and (setcc_carry (cmp ...)), 1).
8769 if (Cond.getOpcode() == ISD::AND &&
8770 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8771 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8772 if (C && C->getAPIntValue() == 1)
8773 Cond = Cond.getOperand(0);
8776 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8777 // setting operand in place of the X86ISD::SETCC.
8778 if (Cond.getOpcode() == X86ISD::SETCC ||
8779 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8780 CC = Cond.getOperand(0);
8782 SDValue Cmp = Cond.getOperand(1);
8783 unsigned Opc = Cmp.getOpcode();
8784 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8785 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8789 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8793 // These can only come from an arithmetic instruction with overflow,
8794 // e.g. SADDO, UADDO.
8795 Cond = Cond.getNode()->getOperand(1);
8802 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8803 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8804 if (CondOpc == ISD::OR) {
8805 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8806 // two branches instead of an explicit OR instruction with a
8808 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8809 isX86LogicalCmp(Cmp)) {
8810 CC = Cond.getOperand(0).getOperand(0);
8811 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8812 Chain, Dest, CC, Cmp);
8813 CC = Cond.getOperand(1).getOperand(0);
8817 } else { // ISD::AND
8818 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8819 // two branches instead of an explicit AND instruction with a
8820 // separate test. However, we only do this if this block doesn't
8821 // have a fall-through edge, because this requires an explicit
8822 // jmp when the condition is false.
8823 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8824 isX86LogicalCmp(Cmp) &&
8825 Op.getNode()->hasOneUse()) {
8826 X86::CondCode CCode =
8827 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8828 CCode = X86::GetOppositeBranchCondition(CCode);
8829 CC = DAG.getConstant(CCode, MVT::i8);
8830 SDNode *User = *Op.getNode()->use_begin();
8831 // Look for an unconditional branch following this conditional branch.
8832 // We need this because we need to reverse the successors in order
8833 // to implement FCMP_OEQ.
8834 if (User->getOpcode() == ISD::BR) {
8835 SDValue FalseBB = User->getOperand(1);
8837 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8838 assert(NewBR == User);
8842 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8843 Chain, Dest, CC, Cmp);
8844 X86::CondCode CCode =
8845 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8846 CCode = X86::GetOppositeBranchCondition(CCode);
8847 CC = DAG.getConstant(CCode, MVT::i8);
8853 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8854 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8855 // It should be transformed during dag combiner except when the condition
8856 // is set by a arithmetics with overflow node.
8857 X86::CondCode CCode =
8858 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8859 CCode = X86::GetOppositeBranchCondition(CCode);
8860 CC = DAG.getConstant(CCode, MVT::i8);
8861 Cond = Cond.getOperand(0).getOperand(1);
8867 // Look pass the truncate.
8868 if (Cond.getOpcode() == ISD::TRUNCATE)
8869 Cond = Cond.getOperand(0);
8871 // We know the result of AND is compared against zero. Try to match
8873 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8874 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8875 if (NewSetCC.getNode()) {
8876 CC = NewSetCC.getOperand(0);
8877 Cond = NewSetCC.getOperand(1);
8884 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8885 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8887 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8888 Chain, Dest, CC, Cond);
8892 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8893 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8894 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8895 // that the guard pages used by the OS virtual memory manager are allocated in
8896 // correct sequence.
8898 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8899 SelectionDAG &DAG) const {
8900 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8901 EnableSegmentedStacks) &&
8902 "This should be used only on Windows targets or when segmented stacks "
8904 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8905 DebugLoc dl = Op.getDebugLoc();
8908 SDValue Chain = Op.getOperand(0);
8909 SDValue Size = Op.getOperand(1);
8910 // FIXME: Ensure alignment here
8912 bool Is64Bit = Subtarget->is64Bit();
8913 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8915 if (EnableSegmentedStacks) {
8916 MachineFunction &MF = DAG.getMachineFunction();
8917 MachineRegisterInfo &MRI = MF.getRegInfo();
8920 // The 64 bit implementation of segmented stacks needs to clobber both r10
8921 // r11. This makes it impossible to use it along with nested parameters.
8922 const Function *F = MF.getFunction();
8924 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8926 if (I->hasNestAttr())
8927 report_fatal_error("Cannot use segmented stacks with functions that "
8928 "have nested arguments.");
8931 const TargetRegisterClass *AddrRegClass =
8932 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8933 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8934 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8935 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8936 DAG.getRegister(Vreg, SPTy));
8937 SDValue Ops1[2] = { Value, Chain };
8938 return DAG.getMergeValues(Ops1, 2, dl);
8941 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8943 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8944 Flag = Chain.getValue(1);
8945 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8947 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8948 Flag = Chain.getValue(1);
8950 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8952 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8953 return DAG.getMergeValues(Ops1, 2, dl);
8957 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8958 MachineFunction &MF = DAG.getMachineFunction();
8959 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8961 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8962 DebugLoc DL = Op.getDebugLoc();
8964 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8965 // vastart just stores the address of the VarArgsFrameIndex slot into the
8966 // memory location argument.
8967 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8969 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8970 MachinePointerInfo(SV), false, false, 0);
8974 // gp_offset (0 - 6 * 8)
8975 // fp_offset (48 - 48 + 8 * 16)
8976 // overflow_arg_area (point to parameters coming in memory).
8978 SmallVector<SDValue, 8> MemOps;
8979 SDValue FIN = Op.getOperand(1);
8981 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8982 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8984 FIN, MachinePointerInfo(SV), false, false, 0);
8985 MemOps.push_back(Store);
8988 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8989 FIN, DAG.getIntPtrConstant(4));
8990 Store = DAG.getStore(Op.getOperand(0), DL,
8991 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8993 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8994 MemOps.push_back(Store);
8996 // Store ptr to overflow_arg_area
8997 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8998 FIN, DAG.getIntPtrConstant(4));
8999 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9001 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9002 MachinePointerInfo(SV, 8),
9004 MemOps.push_back(Store);
9006 // Store ptr to reg_save_area.
9007 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9008 FIN, DAG.getIntPtrConstant(8));
9009 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9011 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9012 MachinePointerInfo(SV, 16), false, false, 0);
9013 MemOps.push_back(Store);
9014 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9015 &MemOps[0], MemOps.size());
9018 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9019 assert(Subtarget->is64Bit() &&
9020 "LowerVAARG only handles 64-bit va_arg!");
9021 assert((Subtarget->isTargetLinux() ||
9022 Subtarget->isTargetDarwin()) &&
9023 "Unhandled target in LowerVAARG");
9024 assert(Op.getNode()->getNumOperands() == 4);
9025 SDValue Chain = Op.getOperand(0);
9026 SDValue SrcPtr = Op.getOperand(1);
9027 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9028 unsigned Align = Op.getConstantOperandVal(3);
9029 DebugLoc dl = Op.getDebugLoc();
9031 EVT ArgVT = Op.getNode()->getValueType(0);
9032 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9033 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9036 // Decide which area this value should be read from.
9037 // TODO: Implement the AMD64 ABI in its entirety. This simple
9038 // selection mechanism works only for the basic types.
9039 if (ArgVT == MVT::f80) {
9040 llvm_unreachable("va_arg for f80 not yet implemented");
9041 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9042 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9043 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9044 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9046 llvm_unreachable("Unhandled argument type in LowerVAARG");
9050 // Sanity Check: Make sure using fp_offset makes sense.
9051 assert(!UseSoftFloat &&
9052 !(DAG.getMachineFunction()
9053 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9054 Subtarget->hasXMM());
9057 // Insert VAARG_64 node into the DAG
9058 // VAARG_64 returns two values: Variable Argument Address, Chain
9059 SmallVector<SDValue, 11> InstOps;
9060 InstOps.push_back(Chain);
9061 InstOps.push_back(SrcPtr);
9062 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9063 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9064 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9065 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9066 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9067 VTs, &InstOps[0], InstOps.size(),
9069 MachinePointerInfo(SV),
9074 Chain = VAARG.getValue(1);
9076 // Load the next argument and return it
9077 return DAG.getLoad(ArgVT, dl,
9080 MachinePointerInfo(),
9084 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9085 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9086 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9087 SDValue Chain = Op.getOperand(0);
9088 SDValue DstPtr = Op.getOperand(1);
9089 SDValue SrcPtr = Op.getOperand(2);
9090 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9091 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9092 DebugLoc DL = Op.getDebugLoc();
9094 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9095 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9097 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9101 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9102 DebugLoc dl = Op.getDebugLoc();
9103 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9105 default: return SDValue(); // Don't custom lower most intrinsics.
9106 // Comparison intrinsics.
9107 case Intrinsic::x86_sse_comieq_ss:
9108 case Intrinsic::x86_sse_comilt_ss:
9109 case Intrinsic::x86_sse_comile_ss:
9110 case Intrinsic::x86_sse_comigt_ss:
9111 case Intrinsic::x86_sse_comige_ss:
9112 case Intrinsic::x86_sse_comineq_ss:
9113 case Intrinsic::x86_sse_ucomieq_ss:
9114 case Intrinsic::x86_sse_ucomilt_ss:
9115 case Intrinsic::x86_sse_ucomile_ss:
9116 case Intrinsic::x86_sse_ucomigt_ss:
9117 case Intrinsic::x86_sse_ucomige_ss:
9118 case Intrinsic::x86_sse_ucomineq_ss:
9119 case Intrinsic::x86_sse2_comieq_sd:
9120 case Intrinsic::x86_sse2_comilt_sd:
9121 case Intrinsic::x86_sse2_comile_sd:
9122 case Intrinsic::x86_sse2_comigt_sd:
9123 case Intrinsic::x86_sse2_comige_sd:
9124 case Intrinsic::x86_sse2_comineq_sd:
9125 case Intrinsic::x86_sse2_ucomieq_sd:
9126 case Intrinsic::x86_sse2_ucomilt_sd:
9127 case Intrinsic::x86_sse2_ucomile_sd:
9128 case Intrinsic::x86_sse2_ucomigt_sd:
9129 case Intrinsic::x86_sse2_ucomige_sd:
9130 case Intrinsic::x86_sse2_ucomineq_sd: {
9132 ISD::CondCode CC = ISD::SETCC_INVALID;
9135 case Intrinsic::x86_sse_comieq_ss:
9136 case Intrinsic::x86_sse2_comieq_sd:
9140 case Intrinsic::x86_sse_comilt_ss:
9141 case Intrinsic::x86_sse2_comilt_sd:
9145 case Intrinsic::x86_sse_comile_ss:
9146 case Intrinsic::x86_sse2_comile_sd:
9150 case Intrinsic::x86_sse_comigt_ss:
9151 case Intrinsic::x86_sse2_comigt_sd:
9155 case Intrinsic::x86_sse_comige_ss:
9156 case Intrinsic::x86_sse2_comige_sd:
9160 case Intrinsic::x86_sse_comineq_ss:
9161 case Intrinsic::x86_sse2_comineq_sd:
9165 case Intrinsic::x86_sse_ucomieq_ss:
9166 case Intrinsic::x86_sse2_ucomieq_sd:
9167 Opc = X86ISD::UCOMI;
9170 case Intrinsic::x86_sse_ucomilt_ss:
9171 case Intrinsic::x86_sse2_ucomilt_sd:
9172 Opc = X86ISD::UCOMI;
9175 case Intrinsic::x86_sse_ucomile_ss:
9176 case Intrinsic::x86_sse2_ucomile_sd:
9177 Opc = X86ISD::UCOMI;
9180 case Intrinsic::x86_sse_ucomigt_ss:
9181 case Intrinsic::x86_sse2_ucomigt_sd:
9182 Opc = X86ISD::UCOMI;
9185 case Intrinsic::x86_sse_ucomige_ss:
9186 case Intrinsic::x86_sse2_ucomige_sd:
9187 Opc = X86ISD::UCOMI;
9190 case Intrinsic::x86_sse_ucomineq_ss:
9191 case Intrinsic::x86_sse2_ucomineq_sd:
9192 Opc = X86ISD::UCOMI;
9197 SDValue LHS = Op.getOperand(1);
9198 SDValue RHS = Op.getOperand(2);
9199 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9200 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9201 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9202 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9203 DAG.getConstant(X86CC, MVT::i8), Cond);
9204 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9206 // ptest and testp intrinsics. The intrinsic these come from are designed to
9207 // return an integer value, not just an instruction so lower it to the ptest
9208 // or testp pattern and a setcc for the result.
9209 case Intrinsic::x86_sse41_ptestz:
9210 case Intrinsic::x86_sse41_ptestc:
9211 case Intrinsic::x86_sse41_ptestnzc:
9212 case Intrinsic::x86_avx_ptestz_256:
9213 case Intrinsic::x86_avx_ptestc_256:
9214 case Intrinsic::x86_avx_ptestnzc_256:
9215 case Intrinsic::x86_avx_vtestz_ps:
9216 case Intrinsic::x86_avx_vtestc_ps:
9217 case Intrinsic::x86_avx_vtestnzc_ps:
9218 case Intrinsic::x86_avx_vtestz_pd:
9219 case Intrinsic::x86_avx_vtestc_pd:
9220 case Intrinsic::x86_avx_vtestnzc_pd:
9221 case Intrinsic::x86_avx_vtestz_ps_256:
9222 case Intrinsic::x86_avx_vtestc_ps_256:
9223 case Intrinsic::x86_avx_vtestnzc_ps_256:
9224 case Intrinsic::x86_avx_vtestz_pd_256:
9225 case Intrinsic::x86_avx_vtestc_pd_256:
9226 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9227 bool IsTestPacked = false;
9230 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9231 case Intrinsic::x86_avx_vtestz_ps:
9232 case Intrinsic::x86_avx_vtestz_pd:
9233 case Intrinsic::x86_avx_vtestz_ps_256:
9234 case Intrinsic::x86_avx_vtestz_pd_256:
9235 IsTestPacked = true; // Fallthrough
9236 case Intrinsic::x86_sse41_ptestz:
9237 case Intrinsic::x86_avx_ptestz_256:
9239 X86CC = X86::COND_E;
9241 case Intrinsic::x86_avx_vtestc_ps:
9242 case Intrinsic::x86_avx_vtestc_pd:
9243 case Intrinsic::x86_avx_vtestc_ps_256:
9244 case Intrinsic::x86_avx_vtestc_pd_256:
9245 IsTestPacked = true; // Fallthrough
9246 case Intrinsic::x86_sse41_ptestc:
9247 case Intrinsic::x86_avx_ptestc_256:
9249 X86CC = X86::COND_B;
9251 case Intrinsic::x86_avx_vtestnzc_ps:
9252 case Intrinsic::x86_avx_vtestnzc_pd:
9253 case Intrinsic::x86_avx_vtestnzc_ps_256:
9254 case Intrinsic::x86_avx_vtestnzc_pd_256:
9255 IsTestPacked = true; // Fallthrough
9256 case Intrinsic::x86_sse41_ptestnzc:
9257 case Intrinsic::x86_avx_ptestnzc_256:
9259 X86CC = X86::COND_A;
9263 SDValue LHS = Op.getOperand(1);
9264 SDValue RHS = Op.getOperand(2);
9265 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9266 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9267 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9268 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9269 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9272 // Fix vector shift instructions where the last operand is a non-immediate
9274 case Intrinsic::x86_sse2_pslli_w:
9275 case Intrinsic::x86_sse2_pslli_d:
9276 case Intrinsic::x86_sse2_pslli_q:
9277 case Intrinsic::x86_sse2_psrli_w:
9278 case Intrinsic::x86_sse2_psrli_d:
9279 case Intrinsic::x86_sse2_psrli_q:
9280 case Intrinsic::x86_sse2_psrai_w:
9281 case Intrinsic::x86_sse2_psrai_d:
9282 case Intrinsic::x86_mmx_pslli_w:
9283 case Intrinsic::x86_mmx_pslli_d:
9284 case Intrinsic::x86_mmx_pslli_q:
9285 case Intrinsic::x86_mmx_psrli_w:
9286 case Intrinsic::x86_mmx_psrli_d:
9287 case Intrinsic::x86_mmx_psrli_q:
9288 case Intrinsic::x86_mmx_psrai_w:
9289 case Intrinsic::x86_mmx_psrai_d: {
9290 SDValue ShAmt = Op.getOperand(2);
9291 if (isa<ConstantSDNode>(ShAmt))
9294 unsigned NewIntNo = 0;
9295 EVT ShAmtVT = MVT::v4i32;
9297 case Intrinsic::x86_sse2_pslli_w:
9298 NewIntNo = Intrinsic::x86_sse2_psll_w;
9300 case Intrinsic::x86_sse2_pslli_d:
9301 NewIntNo = Intrinsic::x86_sse2_psll_d;
9303 case Intrinsic::x86_sse2_pslli_q:
9304 NewIntNo = Intrinsic::x86_sse2_psll_q;
9306 case Intrinsic::x86_sse2_psrli_w:
9307 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9309 case Intrinsic::x86_sse2_psrli_d:
9310 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9312 case Intrinsic::x86_sse2_psrli_q:
9313 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9315 case Intrinsic::x86_sse2_psrai_w:
9316 NewIntNo = Intrinsic::x86_sse2_psra_w;
9318 case Intrinsic::x86_sse2_psrai_d:
9319 NewIntNo = Intrinsic::x86_sse2_psra_d;
9322 ShAmtVT = MVT::v2i32;
9324 case Intrinsic::x86_mmx_pslli_w:
9325 NewIntNo = Intrinsic::x86_mmx_psll_w;
9327 case Intrinsic::x86_mmx_pslli_d:
9328 NewIntNo = Intrinsic::x86_mmx_psll_d;
9330 case Intrinsic::x86_mmx_pslli_q:
9331 NewIntNo = Intrinsic::x86_mmx_psll_q;
9333 case Intrinsic::x86_mmx_psrli_w:
9334 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9336 case Intrinsic::x86_mmx_psrli_d:
9337 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9339 case Intrinsic::x86_mmx_psrli_q:
9340 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9342 case Intrinsic::x86_mmx_psrai_w:
9343 NewIntNo = Intrinsic::x86_mmx_psra_w;
9345 case Intrinsic::x86_mmx_psrai_d:
9346 NewIntNo = Intrinsic::x86_mmx_psra_d;
9348 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9354 // The vector shift intrinsics with scalars uses 32b shift amounts but
9355 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9359 ShOps[1] = DAG.getConstant(0, MVT::i32);
9360 if (ShAmtVT == MVT::v4i32) {
9361 ShOps[2] = DAG.getUNDEF(MVT::i32);
9362 ShOps[3] = DAG.getUNDEF(MVT::i32);
9363 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9365 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9366 // FIXME this must be lowered to get rid of the invalid type.
9369 EVT VT = Op.getValueType();
9370 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9371 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9372 DAG.getConstant(NewIntNo, MVT::i32),
9373 Op.getOperand(1), ShAmt);
9378 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9379 SelectionDAG &DAG) const {
9380 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9381 MFI->setReturnAddressIsTaken(true);
9383 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9384 DebugLoc dl = Op.getDebugLoc();
9387 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9389 DAG.getConstant(TD->getPointerSize(),
9390 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9391 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9392 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9394 MachinePointerInfo(), false, false, 0);
9397 // Just load the return address.
9398 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9399 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9400 RetAddrFI, MachinePointerInfo(), false, false, 0);
9403 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9404 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9405 MFI->setFrameAddressIsTaken(true);
9407 EVT VT = Op.getValueType();
9408 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9409 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9410 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9411 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9413 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9414 MachinePointerInfo(),
9419 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9420 SelectionDAG &DAG) const {
9421 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9424 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9425 MachineFunction &MF = DAG.getMachineFunction();
9426 SDValue Chain = Op.getOperand(0);
9427 SDValue Offset = Op.getOperand(1);
9428 SDValue Handler = Op.getOperand(2);
9429 DebugLoc dl = Op.getDebugLoc();
9431 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9432 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9434 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9436 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9437 DAG.getIntPtrConstant(TD->getPointerSize()));
9438 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9439 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9441 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9442 MF.getRegInfo().addLiveOut(StoreAddrReg);
9444 return DAG.getNode(X86ISD::EH_RETURN, dl,
9446 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9449 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9450 SelectionDAG &DAG) const {
9451 return Op.getOperand(0);
9454 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9455 SelectionDAG &DAG) const {
9456 SDValue Root = Op.getOperand(0);
9457 SDValue Trmp = Op.getOperand(1); // trampoline
9458 SDValue FPtr = Op.getOperand(2); // nested function
9459 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9460 DebugLoc dl = Op.getDebugLoc();
9462 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9464 if (Subtarget->is64Bit()) {
9465 SDValue OutChains[6];
9467 // Large code-model.
9468 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9469 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9471 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9472 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9474 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9476 // Load the pointer to the nested function into R11.
9477 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9478 SDValue Addr = Trmp;
9479 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9480 Addr, MachinePointerInfo(TrmpAddr),
9483 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9484 DAG.getConstant(2, MVT::i64));
9485 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9486 MachinePointerInfo(TrmpAddr, 2),
9489 // Load the 'nest' parameter value into R10.
9490 // R10 is specified in X86CallingConv.td
9491 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9492 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9493 DAG.getConstant(10, MVT::i64));
9494 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9495 Addr, MachinePointerInfo(TrmpAddr, 10),
9498 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9499 DAG.getConstant(12, MVT::i64));
9500 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9501 MachinePointerInfo(TrmpAddr, 12),
9504 // Jump to the nested function.
9505 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9506 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9507 DAG.getConstant(20, MVT::i64));
9508 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9509 Addr, MachinePointerInfo(TrmpAddr, 20),
9512 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9513 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9514 DAG.getConstant(22, MVT::i64));
9515 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9516 MachinePointerInfo(TrmpAddr, 22),
9519 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9521 const Function *Func =
9522 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9523 CallingConv::ID CC = Func->getCallingConv();
9528 llvm_unreachable("Unsupported calling convention");
9529 case CallingConv::C:
9530 case CallingConv::X86_StdCall: {
9531 // Pass 'nest' parameter in ECX.
9532 // Must be kept in sync with X86CallingConv.td
9535 // Check that ECX wasn't needed by an 'inreg' parameter.
9536 FunctionType *FTy = Func->getFunctionType();
9537 const AttrListPtr &Attrs = Func->getAttributes();
9539 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9540 unsigned InRegCount = 0;
9543 for (FunctionType::param_iterator I = FTy->param_begin(),
9544 E = FTy->param_end(); I != E; ++I, ++Idx)
9545 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9546 // FIXME: should only count parameters that are lowered to integers.
9547 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9549 if (InRegCount > 2) {
9550 report_fatal_error("Nest register in use - reduce number of inreg"
9556 case CallingConv::X86_FastCall:
9557 case CallingConv::X86_ThisCall:
9558 case CallingConv::Fast:
9559 // Pass 'nest' parameter in EAX.
9560 // Must be kept in sync with X86CallingConv.td
9565 SDValue OutChains[4];
9568 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9569 DAG.getConstant(10, MVT::i32));
9570 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9572 // This is storing the opcode for MOV32ri.
9573 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9574 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9575 OutChains[0] = DAG.getStore(Root, dl,
9576 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9577 Trmp, MachinePointerInfo(TrmpAddr),
9580 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9581 DAG.getConstant(1, MVT::i32));
9582 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9583 MachinePointerInfo(TrmpAddr, 1),
9586 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9587 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9588 DAG.getConstant(5, MVT::i32));
9589 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9590 MachinePointerInfo(TrmpAddr, 5),
9593 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9594 DAG.getConstant(6, MVT::i32));
9595 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9596 MachinePointerInfo(TrmpAddr, 6),
9599 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9603 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9604 SelectionDAG &DAG) const {
9606 The rounding mode is in bits 11:10 of FPSR, and has the following
9613 FLT_ROUNDS, on the other hand, expects the following:
9620 To perform the conversion, we do:
9621 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9624 MachineFunction &MF = DAG.getMachineFunction();
9625 const TargetMachine &TM = MF.getTarget();
9626 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9627 unsigned StackAlignment = TFI.getStackAlignment();
9628 EVT VT = Op.getValueType();
9629 DebugLoc DL = Op.getDebugLoc();
9631 // Save FP Control Word to stack slot
9632 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9633 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9636 MachineMemOperand *MMO =
9637 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9638 MachineMemOperand::MOStore, 2, 2);
9640 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9641 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9642 DAG.getVTList(MVT::Other),
9643 Ops, 2, MVT::i16, MMO);
9645 // Load FP Control Word from stack slot
9646 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9647 MachinePointerInfo(), false, false, 0);
9649 // Transform as necessary
9651 DAG.getNode(ISD::SRL, DL, MVT::i16,
9652 DAG.getNode(ISD::AND, DL, MVT::i16,
9653 CWD, DAG.getConstant(0x800, MVT::i16)),
9654 DAG.getConstant(11, MVT::i8));
9656 DAG.getNode(ISD::SRL, DL, MVT::i16,
9657 DAG.getNode(ISD::AND, DL, MVT::i16,
9658 CWD, DAG.getConstant(0x400, MVT::i16)),
9659 DAG.getConstant(9, MVT::i8));
9662 DAG.getNode(ISD::AND, DL, MVT::i16,
9663 DAG.getNode(ISD::ADD, DL, MVT::i16,
9664 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9665 DAG.getConstant(1, MVT::i16)),
9666 DAG.getConstant(3, MVT::i16));
9669 return DAG.getNode((VT.getSizeInBits() < 16 ?
9670 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9673 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9674 EVT VT = Op.getValueType();
9676 unsigned NumBits = VT.getSizeInBits();
9677 DebugLoc dl = Op.getDebugLoc();
9679 Op = Op.getOperand(0);
9680 if (VT == MVT::i8) {
9681 // Zero extend to i32 since there is not an i8 bsr.
9683 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9686 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9687 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9688 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9690 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9693 DAG.getConstant(NumBits+NumBits-1, OpVT),
9694 DAG.getConstant(X86::COND_E, MVT::i8),
9697 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9699 // Finally xor with NumBits-1.
9700 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9703 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9707 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9708 EVT VT = Op.getValueType();
9710 unsigned NumBits = VT.getSizeInBits();
9711 DebugLoc dl = Op.getDebugLoc();
9713 Op = Op.getOperand(0);
9714 if (VT == MVT::i8) {
9716 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9719 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9720 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9721 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9723 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9726 DAG.getConstant(NumBits, OpVT),
9727 DAG.getConstant(X86::COND_E, MVT::i8),
9730 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9733 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9737 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9738 // ones, and then concatenate the result back.
9739 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9740 EVT VT = Op.getValueType();
9742 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9743 "Unsupported value type for operation");
9745 int NumElems = VT.getVectorNumElements();
9746 DebugLoc dl = Op.getDebugLoc();
9747 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9748 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9750 // Extract the LHS vectors
9751 SDValue LHS = Op.getOperand(0);
9752 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9753 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9755 // Extract the RHS vectors
9756 SDValue RHS = Op.getOperand(1);
9757 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9758 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9760 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9761 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9763 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9764 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9765 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9768 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9769 assert(Op.getValueType().getSizeInBits() == 256 &&
9770 Op.getValueType().isInteger() &&
9771 "Only handle AVX 256-bit vector integer operation");
9772 return Lower256IntArith(Op, DAG);
9775 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9776 assert(Op.getValueType().getSizeInBits() == 256 &&
9777 Op.getValueType().isInteger() &&
9778 "Only handle AVX 256-bit vector integer operation");
9779 return Lower256IntArith(Op, DAG);
9782 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9783 EVT VT = Op.getValueType();
9785 // Decompose 256-bit ops into smaller 128-bit ops.
9786 if (VT.getSizeInBits() == 256)
9787 return Lower256IntArith(Op, DAG);
9789 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9790 DebugLoc dl = Op.getDebugLoc();
9792 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9793 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9794 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9795 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9796 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9798 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9799 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9800 // return AloBlo + AloBhi + AhiBlo;
9802 SDValue A = Op.getOperand(0);
9803 SDValue B = Op.getOperand(1);
9805 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9806 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9807 A, DAG.getConstant(32, MVT::i32));
9808 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9809 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9810 B, DAG.getConstant(32, MVT::i32));
9811 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9812 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9814 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9815 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9817 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9818 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9820 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9821 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9822 AloBhi, DAG.getConstant(32, MVT::i32));
9823 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9824 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9825 AhiBlo, DAG.getConstant(32, MVT::i32));
9826 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9827 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9831 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9833 EVT VT = Op.getValueType();
9834 DebugLoc dl = Op.getDebugLoc();
9835 SDValue R = Op.getOperand(0);
9836 SDValue Amt = Op.getOperand(1);
9837 LLVMContext *Context = DAG.getContext();
9839 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9842 // Decompose 256-bit shifts into smaller 128-bit shifts.
9843 if (VT.getSizeInBits() == 256) {
9844 int NumElems = VT.getVectorNumElements();
9845 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9846 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9848 // Extract the two vectors
9849 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9850 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9853 // Recreate the shift amount vectors
9855 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9856 // Constant shift amount
9857 SmallVector<SDValue, 4> Amt1Csts;
9858 SmallVector<SDValue, 4> Amt2Csts;
9859 for (int i = 0; i < NumElems/2; ++i)
9860 Amt1Csts.push_back(Amt->getOperand(i));
9861 for (int i = NumElems/2; i < NumElems; ++i)
9862 Amt2Csts.push_back(Amt->getOperand(i));
9864 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9865 &Amt1Csts[0], NumElems/2);
9866 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9867 &Amt2Csts[0], NumElems/2);
9869 // Variable shift amount
9870 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9871 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9875 // Issue new vector shifts for the smaller types
9876 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9877 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9879 // Concatenate the result back
9880 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9883 // Optimize shl/srl/sra with constant shift amount.
9884 if (isSplatVector(Amt.getNode())) {
9885 SDValue SclrAmt = Amt->getOperand(0);
9886 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9887 uint64_t ShiftAmt = C->getZExtValue();
9889 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9890 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9891 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9892 R, DAG.getConstant(ShiftAmt, MVT::i32));
9894 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9895 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9896 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9897 R, DAG.getConstant(ShiftAmt, MVT::i32));
9899 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9900 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9901 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9902 R, DAG.getConstant(ShiftAmt, MVT::i32));
9904 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9905 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9906 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9907 R, DAG.getConstant(ShiftAmt, MVT::i32));
9909 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9910 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9911 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9912 R, DAG.getConstant(ShiftAmt, MVT::i32));
9914 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9915 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9916 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9917 R, DAG.getConstant(ShiftAmt, MVT::i32));
9919 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9920 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9921 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9922 R, DAG.getConstant(ShiftAmt, MVT::i32));
9924 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9925 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9926 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9927 R, DAG.getConstant(ShiftAmt, MVT::i32));
9931 // Lower SHL with variable shift amount.
9932 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9933 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9934 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9935 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9937 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9939 std::vector<Constant*> CV(4, CI);
9940 Constant *C = ConstantVector::get(CV);
9941 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9942 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9943 MachinePointerInfo::getConstantPool(),
9946 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9947 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9948 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9949 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9951 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9953 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9954 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9955 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9957 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9958 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9960 std::vector<Constant*> CVM1(16, CM1);
9961 std::vector<Constant*> CVM2(16, CM2);
9962 Constant *C = ConstantVector::get(CVM1);
9963 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9964 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9965 MachinePointerInfo::getConstantPool(),
9968 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9969 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9970 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9971 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9972 DAG.getConstant(4, MVT::i32));
9973 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9975 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9977 C = ConstantVector::get(CVM2);
9978 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9979 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9980 MachinePointerInfo::getConstantPool(),
9983 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9984 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9985 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9986 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9987 DAG.getConstant(2, MVT::i32));
9988 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9990 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9992 // return pblendv(r, r+r, a);
9993 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9994 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
10000 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10001 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10002 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10003 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10004 // has only one use.
10005 SDNode *N = Op.getNode();
10006 SDValue LHS = N->getOperand(0);
10007 SDValue RHS = N->getOperand(1);
10008 unsigned BaseOp = 0;
10010 DebugLoc DL = Op.getDebugLoc();
10011 switch (Op.getOpcode()) {
10012 default: llvm_unreachable("Unknown ovf instruction!");
10014 // A subtract of one will be selected as a INC. Note that INC doesn't
10015 // set CF, so we can't do this for UADDO.
10016 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10018 BaseOp = X86ISD::INC;
10019 Cond = X86::COND_O;
10022 BaseOp = X86ISD::ADD;
10023 Cond = X86::COND_O;
10026 BaseOp = X86ISD::ADD;
10027 Cond = X86::COND_B;
10030 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10031 // set CF, so we can't do this for USUBO.
10032 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10034 BaseOp = X86ISD::DEC;
10035 Cond = X86::COND_O;
10038 BaseOp = X86ISD::SUB;
10039 Cond = X86::COND_O;
10042 BaseOp = X86ISD::SUB;
10043 Cond = X86::COND_B;
10046 BaseOp = X86ISD::SMUL;
10047 Cond = X86::COND_O;
10049 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10050 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10052 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10055 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10056 DAG.getConstant(X86::COND_O, MVT::i32),
10057 SDValue(Sum.getNode(), 2));
10059 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10063 // Also sets EFLAGS.
10064 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10065 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10068 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10069 DAG.getConstant(Cond, MVT::i32),
10070 SDValue(Sum.getNode(), 1));
10072 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10075 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
10076 DebugLoc dl = Op.getDebugLoc();
10077 SDNode* Node = Op.getNode();
10078 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
10079 EVT VT = Node->getValueType(0);
10080 if (Subtarget->hasSSE2() && VT.isVector()) {
10081 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10082 ExtraVT.getScalarType().getSizeInBits();
10083 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10085 unsigned SHLIntrinsicsID = 0;
10086 unsigned SRAIntrinsicsID = 0;
10087 switch (VT.getSimpleVT().SimpleTy) {
10091 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
10092 SRAIntrinsicsID = 0;
10096 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10097 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10101 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10102 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10107 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10108 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10109 Node->getOperand(0), ShAmt);
10111 // In case of 1 bit sext, no need to shr
10112 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
10114 if (SRAIntrinsicsID) {
10115 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10116 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10126 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10127 DebugLoc dl = Op.getDebugLoc();
10129 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10130 // There isn't any reason to disable it if the target processor supports it.
10131 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10132 SDValue Chain = Op.getOperand(0);
10133 SDValue Zero = DAG.getConstant(0, MVT::i32);
10135 DAG.getRegister(X86::ESP, MVT::i32), // Base
10136 DAG.getTargetConstant(1, MVT::i8), // Scale
10137 DAG.getRegister(0, MVT::i32), // Index
10138 DAG.getTargetConstant(0, MVT::i32), // Disp
10139 DAG.getRegister(0, MVT::i32), // Segment.
10144 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10145 array_lengthof(Ops));
10146 return SDValue(Res, 0);
10149 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10151 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10153 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10154 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10155 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10156 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10158 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10159 if (!Op1 && !Op2 && !Op3 && Op4)
10160 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10162 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10163 if (Op1 && !Op2 && !Op3 && !Op4)
10164 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10166 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10168 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10171 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10172 SelectionDAG &DAG) const {
10173 DebugLoc dl = Op.getDebugLoc();
10174 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10175 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10176 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10177 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10179 // The only fence that needs an instruction is a sequentially-consistent
10180 // cross-thread fence.
10181 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10182 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10183 // no-sse2). There isn't any reason to disable it if the target processor
10185 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10186 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10188 SDValue Chain = Op.getOperand(0);
10189 SDValue Zero = DAG.getConstant(0, MVT::i32);
10191 DAG.getRegister(X86::ESP, MVT::i32), // Base
10192 DAG.getTargetConstant(1, MVT::i8), // Scale
10193 DAG.getRegister(0, MVT::i32), // Index
10194 DAG.getTargetConstant(0, MVT::i32), // Disp
10195 DAG.getRegister(0, MVT::i32), // Segment.
10200 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10201 array_lengthof(Ops));
10202 return SDValue(Res, 0);
10205 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10206 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10210 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10211 EVT T = Op.getValueType();
10212 DebugLoc DL = Op.getDebugLoc();
10215 switch(T.getSimpleVT().SimpleTy) {
10217 assert(false && "Invalid value type!");
10218 case MVT::i8: Reg = X86::AL; size = 1; break;
10219 case MVT::i16: Reg = X86::AX; size = 2; break;
10220 case MVT::i32: Reg = X86::EAX; size = 4; break;
10222 assert(Subtarget->is64Bit() && "Node not type legal!");
10223 Reg = X86::RAX; size = 8;
10226 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10227 Op.getOperand(2), SDValue());
10228 SDValue Ops[] = { cpIn.getValue(0),
10231 DAG.getTargetConstant(size, MVT::i8),
10232 cpIn.getValue(1) };
10233 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10234 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10235 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10238 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10242 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10243 SelectionDAG &DAG) const {
10244 assert(Subtarget->is64Bit() && "Result not type legalized?");
10245 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10246 SDValue TheChain = Op.getOperand(0);
10247 DebugLoc dl = Op.getDebugLoc();
10248 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10249 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10250 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10252 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10253 DAG.getConstant(32, MVT::i8));
10255 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10258 return DAG.getMergeValues(Ops, 2, dl);
10261 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10262 SelectionDAG &DAG) const {
10263 EVT SrcVT = Op.getOperand(0).getValueType();
10264 EVT DstVT = Op.getValueType();
10265 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10266 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10267 assert((DstVT == MVT::i64 ||
10268 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10269 "Unexpected custom BITCAST");
10270 // i64 <=> MMX conversions are Legal.
10271 if (SrcVT==MVT::i64 && DstVT.isVector())
10273 if (DstVT==MVT::i64 && SrcVT.isVector())
10275 // MMX <=> MMX conversions are Legal.
10276 if (SrcVT.isVector() && DstVT.isVector())
10278 // All other conversions need to be expanded.
10282 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10283 SDNode *Node = Op.getNode();
10284 DebugLoc dl = Node->getDebugLoc();
10285 EVT T = Node->getValueType(0);
10286 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10287 DAG.getConstant(0, T), Node->getOperand(2));
10288 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10289 cast<AtomicSDNode>(Node)->getMemoryVT(),
10290 Node->getOperand(0),
10291 Node->getOperand(1), negOp,
10292 cast<AtomicSDNode>(Node)->getSrcValue(),
10293 cast<AtomicSDNode>(Node)->getAlignment(),
10294 cast<AtomicSDNode>(Node)->getOrdering(),
10295 cast<AtomicSDNode>(Node)->getSynchScope());
10298 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10299 SDNode *Node = Op.getNode();
10300 DebugLoc dl = Node->getDebugLoc();
10301 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10303 // Convert seq_cst store -> xchg
10304 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10305 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10306 // (The only way to get a 16-byte store is cmpxchg16b)
10307 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10308 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10309 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10310 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10311 cast<AtomicSDNode>(Node)->getMemoryVT(),
10312 Node->getOperand(0),
10313 Node->getOperand(1), Node->getOperand(2),
10314 cast<AtomicSDNode>(Node)->getMemOperand(),
10315 cast<AtomicSDNode>(Node)->getOrdering(),
10316 cast<AtomicSDNode>(Node)->getSynchScope());
10317 return Swap.getValue(1);
10319 // Other atomic stores have a simple pattern.
10323 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10324 EVT VT = Op.getNode()->getValueType(0);
10326 // Let legalize expand this if it isn't a legal type yet.
10327 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10330 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10333 bool ExtraOp = false;
10334 switch (Op.getOpcode()) {
10335 default: assert(0 && "Invalid code");
10336 case ISD::ADDC: Opc = X86ISD::ADD; break;
10337 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10338 case ISD::SUBC: Opc = X86ISD::SUB; break;
10339 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10343 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10345 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10346 Op.getOperand(1), Op.getOperand(2));
10349 /// LowerOperation - Provide custom lowering hooks for some operations.
10351 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10352 switch (Op.getOpcode()) {
10353 default: llvm_unreachable("Should not custom lower this!");
10354 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10355 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10356 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10357 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10358 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10359 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10360 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10361 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10362 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10363 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10364 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10365 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10366 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10367 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10368 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10369 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10370 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10371 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10372 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10373 case ISD::SHL_PARTS:
10374 case ISD::SRA_PARTS:
10375 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10376 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10377 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10378 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10379 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10380 case ISD::FABS: return LowerFABS(Op, DAG);
10381 case ISD::FNEG: return LowerFNEG(Op, DAG);
10382 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10383 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10384 case ISD::SETCC: return LowerSETCC(Op, DAG);
10385 case ISD::SELECT: return LowerSELECT(Op, DAG);
10386 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
10387 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10388 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10389 case ISD::VASTART: return LowerVASTART(Op, DAG);
10390 case ISD::VAARG: return LowerVAARG(Op, DAG);
10391 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10392 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10393 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10394 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10395 case ISD::FRAME_TO_ARGS_OFFSET:
10396 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10397 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10398 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10399 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10400 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10401 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10402 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10403 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10404 case ISD::MUL: return LowerMUL(Op, DAG);
10407 case ISD::SHL: return LowerShift(Op, DAG);
10413 case ISD::UMULO: return LowerXALUO(Op, DAG);
10414 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10415 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10419 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10420 case ISD::ADD: return LowerADD(Op, DAG);
10421 case ISD::SUB: return LowerSUB(Op, DAG);
10425 static void ReplaceATOMIC_LOAD(SDNode *Node,
10426 SmallVectorImpl<SDValue> &Results,
10427 SelectionDAG &DAG) {
10428 DebugLoc dl = Node->getDebugLoc();
10429 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10431 // Convert wide load -> cmpxchg8b/cmpxchg16b
10432 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10433 // (The only way to get a 16-byte load is cmpxchg16b)
10434 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10435 SDValue Zero = DAG.getConstant(0, VT);
10436 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10437 Node->getOperand(0),
10438 Node->getOperand(1), Zero, Zero,
10439 cast<AtomicSDNode>(Node)->getMemOperand(),
10440 cast<AtomicSDNode>(Node)->getOrdering(),
10441 cast<AtomicSDNode>(Node)->getSynchScope());
10442 Results.push_back(Swap.getValue(0));
10443 Results.push_back(Swap.getValue(1));
10446 void X86TargetLowering::
10447 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10448 SelectionDAG &DAG, unsigned NewOp) const {
10449 EVT T = Node->getValueType(0);
10450 DebugLoc dl = Node->getDebugLoc();
10451 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10453 SDValue Chain = Node->getOperand(0);
10454 SDValue In1 = Node->getOperand(1);
10455 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10456 Node->getOperand(2), DAG.getIntPtrConstant(0));
10457 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10458 Node->getOperand(2), DAG.getIntPtrConstant(1));
10459 SDValue Ops[] = { Chain, In1, In2L, In2H };
10460 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10462 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10463 cast<MemSDNode>(Node)->getMemOperand());
10464 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10465 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10466 Results.push_back(Result.getValue(2));
10469 /// ReplaceNodeResults - Replace a node with an illegal result type
10470 /// with a new node built out of custom code.
10471 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10472 SmallVectorImpl<SDValue>&Results,
10473 SelectionDAG &DAG) const {
10474 DebugLoc dl = N->getDebugLoc();
10475 switch (N->getOpcode()) {
10477 assert(false && "Do not know how to custom type legalize this operation!");
10479 case ISD::SIGN_EXTEND_INREG:
10484 // We don't want to expand or promote these.
10486 case ISD::FP_TO_SINT: {
10487 std::pair<SDValue,SDValue> Vals =
10488 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10489 SDValue FIST = Vals.first, StackSlot = Vals.second;
10490 if (FIST.getNode() != 0) {
10491 EVT VT = N->getValueType(0);
10492 // Return a load from the stack slot.
10493 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10494 MachinePointerInfo(), false, false, 0));
10498 case ISD::READCYCLECOUNTER: {
10499 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10500 SDValue TheChain = N->getOperand(0);
10501 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10502 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10504 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10506 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10507 SDValue Ops[] = { eax, edx };
10508 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10509 Results.push_back(edx.getValue(1));
10512 case ISD::ATOMIC_CMP_SWAP: {
10513 EVT T = N->getValueType(0);
10514 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10515 bool Regs64bit = T == MVT::i128;
10516 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10517 SDValue cpInL, cpInH;
10518 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10519 DAG.getConstant(0, HalfT));
10520 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10521 DAG.getConstant(1, HalfT));
10522 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10523 Regs64bit ? X86::RAX : X86::EAX,
10525 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10526 Regs64bit ? X86::RDX : X86::EDX,
10527 cpInH, cpInL.getValue(1));
10528 SDValue swapInL, swapInH;
10529 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10530 DAG.getConstant(0, HalfT));
10531 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10532 DAG.getConstant(1, HalfT));
10533 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10534 Regs64bit ? X86::RBX : X86::EBX,
10535 swapInL, cpInH.getValue(1));
10536 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10537 Regs64bit ? X86::RCX : X86::ECX,
10538 swapInH, swapInL.getValue(1));
10539 SDValue Ops[] = { swapInH.getValue(0),
10541 swapInH.getValue(1) };
10542 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10543 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10544 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10545 X86ISD::LCMPXCHG8_DAG;
10546 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10548 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10549 Regs64bit ? X86::RAX : X86::EAX,
10550 HalfT, Result.getValue(1));
10551 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10552 Regs64bit ? X86::RDX : X86::EDX,
10553 HalfT, cpOutL.getValue(2));
10554 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10555 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10556 Results.push_back(cpOutH.getValue(1));
10559 case ISD::ATOMIC_LOAD_ADD:
10560 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10562 case ISD::ATOMIC_LOAD_AND:
10563 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10565 case ISD::ATOMIC_LOAD_NAND:
10566 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10568 case ISD::ATOMIC_LOAD_OR:
10569 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10571 case ISD::ATOMIC_LOAD_SUB:
10572 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10574 case ISD::ATOMIC_LOAD_XOR:
10575 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10577 case ISD::ATOMIC_SWAP:
10578 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10580 case ISD::ATOMIC_LOAD:
10581 ReplaceATOMIC_LOAD(N, Results, DAG);
10585 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10587 default: return NULL;
10588 case X86ISD::BSF: return "X86ISD::BSF";
10589 case X86ISD::BSR: return "X86ISD::BSR";
10590 case X86ISD::SHLD: return "X86ISD::SHLD";
10591 case X86ISD::SHRD: return "X86ISD::SHRD";
10592 case X86ISD::FAND: return "X86ISD::FAND";
10593 case X86ISD::FOR: return "X86ISD::FOR";
10594 case X86ISD::FXOR: return "X86ISD::FXOR";
10595 case X86ISD::FSRL: return "X86ISD::FSRL";
10596 case X86ISD::FILD: return "X86ISD::FILD";
10597 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10598 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10599 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10600 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10601 case X86ISD::FLD: return "X86ISD::FLD";
10602 case X86ISD::FST: return "X86ISD::FST";
10603 case X86ISD::CALL: return "X86ISD::CALL";
10604 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10605 case X86ISD::BT: return "X86ISD::BT";
10606 case X86ISD::CMP: return "X86ISD::CMP";
10607 case X86ISD::COMI: return "X86ISD::COMI";
10608 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10609 case X86ISD::SETCC: return "X86ISD::SETCC";
10610 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10611 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10612 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10613 case X86ISD::CMOV: return "X86ISD::CMOV";
10614 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10615 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10616 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10617 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10618 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10619 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10620 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10621 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10622 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10623 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10624 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10625 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10626 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10627 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10628 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10629 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10630 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10631 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10632 case X86ISD::FMAX: return "X86ISD::FMAX";
10633 case X86ISD::FMIN: return "X86ISD::FMIN";
10634 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10635 case X86ISD::FRCP: return "X86ISD::FRCP";
10636 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10637 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10638 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10639 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10640 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10641 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10642 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10643 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10644 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10645 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10646 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10647 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10648 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10649 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10650 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10651 case X86ISD::VSHL: return "X86ISD::VSHL";
10652 case X86ISD::VSRL: return "X86ISD::VSRL";
10653 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10654 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10655 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10656 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10657 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10658 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10659 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10660 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10661 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10662 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10663 case X86ISD::ADD: return "X86ISD::ADD";
10664 case X86ISD::SUB: return "X86ISD::SUB";
10665 case X86ISD::ADC: return "X86ISD::ADC";
10666 case X86ISD::SBB: return "X86ISD::SBB";
10667 case X86ISD::SMUL: return "X86ISD::SMUL";
10668 case X86ISD::UMUL: return "X86ISD::UMUL";
10669 case X86ISD::INC: return "X86ISD::INC";
10670 case X86ISD::DEC: return "X86ISD::DEC";
10671 case X86ISD::OR: return "X86ISD::OR";
10672 case X86ISD::XOR: return "X86ISD::XOR";
10673 case X86ISD::AND: return "X86ISD::AND";
10674 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10675 case X86ISD::PTEST: return "X86ISD::PTEST";
10676 case X86ISD::TESTP: return "X86ISD::TESTP";
10677 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10678 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10679 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10680 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10681 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10682 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10683 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10684 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10685 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10686 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10687 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10688 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10689 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10690 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10691 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10692 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10693 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10694 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10695 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10696 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10697 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10698 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10699 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10700 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10701 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10702 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10703 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10704 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10705 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10706 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10707 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10708 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10709 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10710 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10711 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10712 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10713 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10714 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10715 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10716 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10717 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10718 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10719 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10720 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10721 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10725 // isLegalAddressingMode - Return true if the addressing mode represented
10726 // by AM is legal for this target, for a load/store of the specified type.
10727 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10729 // X86 supports extremely general addressing modes.
10730 CodeModel::Model M = getTargetMachine().getCodeModel();
10731 Reloc::Model R = getTargetMachine().getRelocationModel();
10733 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10734 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10739 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10741 // If a reference to this global requires an extra load, we can't fold it.
10742 if (isGlobalStubReference(GVFlags))
10745 // If BaseGV requires a register for the PIC base, we cannot also have a
10746 // BaseReg specified.
10747 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10750 // If lower 4G is not available, then we must use rip-relative addressing.
10751 if ((M != CodeModel::Small || R != Reloc::Static) &&
10752 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10756 switch (AM.Scale) {
10762 // These scales always work.
10767 // These scales are formed with basereg+scalereg. Only accept if there is
10772 default: // Other stuff never works.
10780 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10781 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10783 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10784 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10785 if (NumBits1 <= NumBits2)
10790 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10791 if (!VT1.isInteger() || !VT2.isInteger())
10793 unsigned NumBits1 = VT1.getSizeInBits();
10794 unsigned NumBits2 = VT2.getSizeInBits();
10795 if (NumBits1 <= NumBits2)
10800 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10801 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10802 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10805 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10806 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10807 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10810 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10811 // i16 instructions are longer (0x66 prefix) and potentially slower.
10812 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10815 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10816 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10817 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10818 /// are assumed to be legal.
10820 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10822 // Very little shuffling can be done for 64-bit vectors right now.
10823 if (VT.getSizeInBits() == 64)
10824 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10826 // FIXME: pshufb, blends, shifts.
10827 return (VT.getVectorNumElements() == 2 ||
10828 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10829 isMOVLMask(M, VT) ||
10830 isSHUFPMask(M, VT) ||
10831 isPSHUFDMask(M, VT) ||
10832 isPSHUFHWMask(M, VT) ||
10833 isPSHUFLWMask(M, VT) ||
10834 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10835 isUNPCKLMask(M, VT) ||
10836 isUNPCKHMask(M, VT) ||
10837 isUNPCKL_v_undef_Mask(M, VT) ||
10838 isUNPCKH_v_undef_Mask(M, VT));
10842 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10844 unsigned NumElts = VT.getVectorNumElements();
10845 // FIXME: This collection of masks seems suspect.
10848 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10849 return (isMOVLMask(Mask, VT) ||
10850 isCommutedMOVLMask(Mask, VT, true) ||
10851 isSHUFPMask(Mask, VT) ||
10852 isCommutedSHUFPMask(Mask, VT));
10857 //===----------------------------------------------------------------------===//
10858 // X86 Scheduler Hooks
10859 //===----------------------------------------------------------------------===//
10861 // private utility function
10862 MachineBasicBlock *
10863 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10864 MachineBasicBlock *MBB,
10871 TargetRegisterClass *RC,
10872 bool invSrc) const {
10873 // For the atomic bitwise operator, we generate
10876 // ld t1 = [bitinstr.addr]
10877 // op t2 = t1, [bitinstr.val]
10879 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10881 // fallthrough -->nextMBB
10882 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10883 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10884 MachineFunction::iterator MBBIter = MBB;
10887 /// First build the CFG
10888 MachineFunction *F = MBB->getParent();
10889 MachineBasicBlock *thisMBB = MBB;
10890 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10891 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10892 F->insert(MBBIter, newMBB);
10893 F->insert(MBBIter, nextMBB);
10895 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10896 nextMBB->splice(nextMBB->begin(), thisMBB,
10897 llvm::next(MachineBasicBlock::iterator(bInstr)),
10899 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10901 // Update thisMBB to fall through to newMBB
10902 thisMBB->addSuccessor(newMBB);
10904 // newMBB jumps to itself and fall through to nextMBB
10905 newMBB->addSuccessor(nextMBB);
10906 newMBB->addSuccessor(newMBB);
10908 // Insert instructions into newMBB based on incoming instruction
10909 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10910 "unexpected number of operands");
10911 DebugLoc dl = bInstr->getDebugLoc();
10912 MachineOperand& destOper = bInstr->getOperand(0);
10913 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10914 int numArgs = bInstr->getNumOperands() - 1;
10915 for (int i=0; i < numArgs; ++i)
10916 argOpers[i] = &bInstr->getOperand(i+1);
10918 // x86 address has 4 operands: base, index, scale, and displacement
10919 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10920 int valArgIndx = lastAddrIndx + 1;
10922 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10923 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10924 for (int i=0; i <= lastAddrIndx; ++i)
10925 (*MIB).addOperand(*argOpers[i]);
10927 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10929 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10934 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10935 assert((argOpers[valArgIndx]->isReg() ||
10936 argOpers[valArgIndx]->isImm()) &&
10937 "invalid operand");
10938 if (argOpers[valArgIndx]->isReg())
10939 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10941 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10943 (*MIB).addOperand(*argOpers[valArgIndx]);
10945 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10948 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10949 for (int i=0; i <= lastAddrIndx; ++i)
10950 (*MIB).addOperand(*argOpers[i]);
10952 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10953 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10954 bInstr->memoperands_end());
10956 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10957 MIB.addReg(EAXreg);
10960 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10962 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10966 // private utility function: 64 bit atomics on 32 bit host.
10967 MachineBasicBlock *
10968 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10969 MachineBasicBlock *MBB,
10974 bool invSrc) const {
10975 // For the atomic bitwise operator, we generate
10976 // thisMBB (instructions are in pairs, except cmpxchg8b)
10977 // ld t1,t2 = [bitinstr.addr]
10979 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10980 // op t5, t6 <- out1, out2, [bitinstr.val]
10981 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10982 // mov ECX, EBX <- t5, t6
10983 // mov EAX, EDX <- t1, t2
10984 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10985 // mov t3, t4 <- EAX, EDX
10987 // result in out1, out2
10988 // fallthrough -->nextMBB
10990 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10991 const unsigned LoadOpc = X86::MOV32rm;
10992 const unsigned NotOpc = X86::NOT32r;
10993 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10994 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10995 MachineFunction::iterator MBBIter = MBB;
10998 /// First build the CFG
10999 MachineFunction *F = MBB->getParent();
11000 MachineBasicBlock *thisMBB = MBB;
11001 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11002 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11003 F->insert(MBBIter, newMBB);
11004 F->insert(MBBIter, nextMBB);
11006 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11007 nextMBB->splice(nextMBB->begin(), thisMBB,
11008 llvm::next(MachineBasicBlock::iterator(bInstr)),
11010 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11012 // Update thisMBB to fall through to newMBB
11013 thisMBB->addSuccessor(newMBB);
11015 // newMBB jumps to itself and fall through to nextMBB
11016 newMBB->addSuccessor(nextMBB);
11017 newMBB->addSuccessor(newMBB);
11019 DebugLoc dl = bInstr->getDebugLoc();
11020 // Insert instructions into newMBB based on incoming instruction
11021 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11022 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11023 "unexpected number of operands");
11024 MachineOperand& dest1Oper = bInstr->getOperand(0);
11025 MachineOperand& dest2Oper = bInstr->getOperand(1);
11026 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11027 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11028 argOpers[i] = &bInstr->getOperand(i+2);
11030 // We use some of the operands multiple times, so conservatively just
11031 // clear any kill flags that might be present.
11032 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11033 argOpers[i]->setIsKill(false);
11036 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11037 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11039 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11040 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11041 for (int i=0; i <= lastAddrIndx; ++i)
11042 (*MIB).addOperand(*argOpers[i]);
11043 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11044 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11045 // add 4 to displacement.
11046 for (int i=0; i <= lastAddrIndx-2; ++i)
11047 (*MIB).addOperand(*argOpers[i]);
11048 MachineOperand newOp3 = *(argOpers[3]);
11049 if (newOp3.isImm())
11050 newOp3.setImm(newOp3.getImm()+4);
11052 newOp3.setOffset(newOp3.getOffset()+4);
11053 (*MIB).addOperand(newOp3);
11054 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11056 // t3/4 are defined later, at the bottom of the loop
11057 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11058 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11059 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11060 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11061 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11062 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11064 // The subsequent operations should be using the destination registers of
11065 //the PHI instructions.
11067 t1 = F->getRegInfo().createVirtualRegister(RC);
11068 t2 = F->getRegInfo().createVirtualRegister(RC);
11069 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11070 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11072 t1 = dest1Oper.getReg();
11073 t2 = dest2Oper.getReg();
11076 int valArgIndx = lastAddrIndx + 1;
11077 assert((argOpers[valArgIndx]->isReg() ||
11078 argOpers[valArgIndx]->isImm()) &&
11079 "invalid operand");
11080 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11081 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11082 if (argOpers[valArgIndx]->isReg())
11083 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11085 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11086 if (regOpcL != X86::MOV32rr)
11088 (*MIB).addOperand(*argOpers[valArgIndx]);
11089 assert(argOpers[valArgIndx + 1]->isReg() ==
11090 argOpers[valArgIndx]->isReg());
11091 assert(argOpers[valArgIndx + 1]->isImm() ==
11092 argOpers[valArgIndx]->isImm());
11093 if (argOpers[valArgIndx + 1]->isReg())
11094 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11096 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11097 if (regOpcH != X86::MOV32rr)
11099 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11101 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11103 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11106 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11108 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11111 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11112 for (int i=0; i <= lastAddrIndx; ++i)
11113 (*MIB).addOperand(*argOpers[i]);
11115 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11116 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11117 bInstr->memoperands_end());
11119 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11120 MIB.addReg(X86::EAX);
11121 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11122 MIB.addReg(X86::EDX);
11125 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11127 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11131 // private utility function
11132 MachineBasicBlock *
11133 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11134 MachineBasicBlock *MBB,
11135 unsigned cmovOpc) const {
11136 // For the atomic min/max operator, we generate
11139 // ld t1 = [min/max.addr]
11140 // mov t2 = [min/max.val]
11142 // cmov[cond] t2 = t1
11144 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11146 // fallthrough -->nextMBB
11148 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11149 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11150 MachineFunction::iterator MBBIter = MBB;
11153 /// First build the CFG
11154 MachineFunction *F = MBB->getParent();
11155 MachineBasicBlock *thisMBB = MBB;
11156 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11157 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11158 F->insert(MBBIter, newMBB);
11159 F->insert(MBBIter, nextMBB);
11161 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11162 nextMBB->splice(nextMBB->begin(), thisMBB,
11163 llvm::next(MachineBasicBlock::iterator(mInstr)),
11165 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11167 // Update thisMBB to fall through to newMBB
11168 thisMBB->addSuccessor(newMBB);
11170 // newMBB jumps to newMBB and fall through to nextMBB
11171 newMBB->addSuccessor(nextMBB);
11172 newMBB->addSuccessor(newMBB);
11174 DebugLoc dl = mInstr->getDebugLoc();
11175 // Insert instructions into newMBB based on incoming instruction
11176 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11177 "unexpected number of operands");
11178 MachineOperand& destOper = mInstr->getOperand(0);
11179 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11180 int numArgs = mInstr->getNumOperands() - 1;
11181 for (int i=0; i < numArgs; ++i)
11182 argOpers[i] = &mInstr->getOperand(i+1);
11184 // x86 address has 4 operands: base, index, scale, and displacement
11185 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11186 int valArgIndx = lastAddrIndx + 1;
11188 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11189 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11190 for (int i=0; i <= lastAddrIndx; ++i)
11191 (*MIB).addOperand(*argOpers[i]);
11193 // We only support register and immediate values
11194 assert((argOpers[valArgIndx]->isReg() ||
11195 argOpers[valArgIndx]->isImm()) &&
11196 "invalid operand");
11198 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11199 if (argOpers[valArgIndx]->isReg())
11200 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11202 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11203 (*MIB).addOperand(*argOpers[valArgIndx]);
11205 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11208 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11213 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11214 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11218 // Cmp and exchange if none has modified the memory location
11219 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11220 for (int i=0; i <= lastAddrIndx; ++i)
11221 (*MIB).addOperand(*argOpers[i]);
11223 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11224 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11225 mInstr->memoperands_end());
11227 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11228 MIB.addReg(X86::EAX);
11231 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11233 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11237 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11238 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11239 // in the .td file.
11240 MachineBasicBlock *
11241 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11242 unsigned numArgs, bool memArg) const {
11243 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11244 "Target must have SSE4.2 or AVX features enabled");
11246 DebugLoc dl = MI->getDebugLoc();
11247 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11249 if (!Subtarget->hasAVX()) {
11251 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11253 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11256 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11258 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11261 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11262 for (unsigned i = 0; i < numArgs; ++i) {
11263 MachineOperand &Op = MI->getOperand(i+1);
11264 if (!(Op.isReg() && Op.isImplicit()))
11265 MIB.addOperand(Op);
11267 BuildMI(*BB, MI, dl,
11268 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11269 MI->getOperand(0).getReg())
11270 .addReg(X86::XMM0);
11272 MI->eraseFromParent();
11276 MachineBasicBlock *
11277 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11278 DebugLoc dl = MI->getDebugLoc();
11279 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11281 // Address into RAX/EAX, other two args into ECX, EDX.
11282 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11283 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11284 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11285 for (int i = 0; i < X86::AddrNumOperands; ++i)
11286 MIB.addOperand(MI->getOperand(i));
11288 unsigned ValOps = X86::AddrNumOperands;
11289 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11290 .addReg(MI->getOperand(ValOps).getReg());
11291 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11292 .addReg(MI->getOperand(ValOps+1).getReg());
11294 // The instruction doesn't actually take any operands though.
11295 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11297 MI->eraseFromParent(); // The pseudo is gone now.
11301 MachineBasicBlock *
11302 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11303 DebugLoc dl = MI->getDebugLoc();
11304 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11306 // First arg in ECX, the second in EAX.
11307 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11308 .addReg(MI->getOperand(0).getReg());
11309 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11310 .addReg(MI->getOperand(1).getReg());
11312 // The instruction doesn't actually take any operands though.
11313 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11315 MI->eraseFromParent(); // The pseudo is gone now.
11319 MachineBasicBlock *
11320 X86TargetLowering::EmitVAARG64WithCustomInserter(
11322 MachineBasicBlock *MBB) const {
11323 // Emit va_arg instruction on X86-64.
11325 // Operands to this pseudo-instruction:
11326 // 0 ) Output : destination address (reg)
11327 // 1-5) Input : va_list address (addr, i64mem)
11328 // 6 ) ArgSize : Size (in bytes) of vararg type
11329 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11330 // 8 ) Align : Alignment of type
11331 // 9 ) EFLAGS (implicit-def)
11333 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11334 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11336 unsigned DestReg = MI->getOperand(0).getReg();
11337 MachineOperand &Base = MI->getOperand(1);
11338 MachineOperand &Scale = MI->getOperand(2);
11339 MachineOperand &Index = MI->getOperand(3);
11340 MachineOperand &Disp = MI->getOperand(4);
11341 MachineOperand &Segment = MI->getOperand(5);
11342 unsigned ArgSize = MI->getOperand(6).getImm();
11343 unsigned ArgMode = MI->getOperand(7).getImm();
11344 unsigned Align = MI->getOperand(8).getImm();
11346 // Memory Reference
11347 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11348 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11349 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11351 // Machine Information
11352 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11353 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11354 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11355 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11356 DebugLoc DL = MI->getDebugLoc();
11358 // struct va_list {
11361 // i64 overflow_area (address)
11362 // i64 reg_save_area (address)
11364 // sizeof(va_list) = 24
11365 // alignment(va_list) = 8
11367 unsigned TotalNumIntRegs = 6;
11368 unsigned TotalNumXMMRegs = 8;
11369 bool UseGPOffset = (ArgMode == 1);
11370 bool UseFPOffset = (ArgMode == 2);
11371 unsigned MaxOffset = TotalNumIntRegs * 8 +
11372 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11374 /* Align ArgSize to a multiple of 8 */
11375 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11376 bool NeedsAlign = (Align > 8);
11378 MachineBasicBlock *thisMBB = MBB;
11379 MachineBasicBlock *overflowMBB;
11380 MachineBasicBlock *offsetMBB;
11381 MachineBasicBlock *endMBB;
11383 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11384 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11385 unsigned OffsetReg = 0;
11387 if (!UseGPOffset && !UseFPOffset) {
11388 // If we only pull from the overflow region, we don't create a branch.
11389 // We don't need to alter control flow.
11390 OffsetDestReg = 0; // unused
11391 OverflowDestReg = DestReg;
11394 overflowMBB = thisMBB;
11397 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11398 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11399 // If not, pull from overflow_area. (branch to overflowMBB)
11404 // offsetMBB overflowMBB
11409 // Registers for the PHI in endMBB
11410 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11411 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11413 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11414 MachineFunction *MF = MBB->getParent();
11415 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11416 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11417 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11419 MachineFunction::iterator MBBIter = MBB;
11422 // Insert the new basic blocks
11423 MF->insert(MBBIter, offsetMBB);
11424 MF->insert(MBBIter, overflowMBB);
11425 MF->insert(MBBIter, endMBB);
11427 // Transfer the remainder of MBB and its successor edges to endMBB.
11428 endMBB->splice(endMBB->begin(), thisMBB,
11429 llvm::next(MachineBasicBlock::iterator(MI)),
11431 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11433 // Make offsetMBB and overflowMBB successors of thisMBB
11434 thisMBB->addSuccessor(offsetMBB);
11435 thisMBB->addSuccessor(overflowMBB);
11437 // endMBB is a successor of both offsetMBB and overflowMBB
11438 offsetMBB->addSuccessor(endMBB);
11439 overflowMBB->addSuccessor(endMBB);
11441 // Load the offset value into a register
11442 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11443 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11447 .addDisp(Disp, UseFPOffset ? 4 : 0)
11448 .addOperand(Segment)
11449 .setMemRefs(MMOBegin, MMOEnd);
11451 // Check if there is enough room left to pull this argument.
11452 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11454 .addImm(MaxOffset + 8 - ArgSizeA8);
11456 // Branch to "overflowMBB" if offset >= max
11457 // Fall through to "offsetMBB" otherwise
11458 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11459 .addMBB(overflowMBB);
11462 // In offsetMBB, emit code to use the reg_save_area.
11464 assert(OffsetReg != 0);
11466 // Read the reg_save_area address.
11467 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11468 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11473 .addOperand(Segment)
11474 .setMemRefs(MMOBegin, MMOEnd);
11476 // Zero-extend the offset
11477 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11478 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11481 .addImm(X86::sub_32bit);
11483 // Add the offset to the reg_save_area to get the final address.
11484 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11485 .addReg(OffsetReg64)
11486 .addReg(RegSaveReg);
11488 // Compute the offset for the next argument
11489 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11490 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11492 .addImm(UseFPOffset ? 16 : 8);
11494 // Store it back into the va_list.
11495 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11499 .addDisp(Disp, UseFPOffset ? 4 : 0)
11500 .addOperand(Segment)
11501 .addReg(NextOffsetReg)
11502 .setMemRefs(MMOBegin, MMOEnd);
11505 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11510 // Emit code to use overflow area
11513 // Load the overflow_area address into a register.
11514 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11515 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11520 .addOperand(Segment)
11521 .setMemRefs(MMOBegin, MMOEnd);
11523 // If we need to align it, do so. Otherwise, just copy the address
11524 // to OverflowDestReg.
11526 // Align the overflow address
11527 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11528 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11530 // aligned_addr = (addr + (align-1)) & ~(align-1)
11531 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11532 .addReg(OverflowAddrReg)
11535 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11537 .addImm(~(uint64_t)(Align-1));
11539 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11540 .addReg(OverflowAddrReg);
11543 // Compute the next overflow address after this argument.
11544 // (the overflow address should be kept 8-byte aligned)
11545 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11546 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11547 .addReg(OverflowDestReg)
11548 .addImm(ArgSizeA8);
11550 // Store the new overflow address.
11551 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11556 .addOperand(Segment)
11557 .addReg(NextAddrReg)
11558 .setMemRefs(MMOBegin, MMOEnd);
11560 // If we branched, emit the PHI to the front of endMBB.
11562 BuildMI(*endMBB, endMBB->begin(), DL,
11563 TII->get(X86::PHI), DestReg)
11564 .addReg(OffsetDestReg).addMBB(offsetMBB)
11565 .addReg(OverflowDestReg).addMBB(overflowMBB);
11568 // Erase the pseudo instruction
11569 MI->eraseFromParent();
11574 MachineBasicBlock *
11575 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11577 MachineBasicBlock *MBB) const {
11578 // Emit code to save XMM registers to the stack. The ABI says that the
11579 // number of registers to save is given in %al, so it's theoretically
11580 // possible to do an indirect jump trick to avoid saving all of them,
11581 // however this code takes a simpler approach and just executes all
11582 // of the stores if %al is non-zero. It's less code, and it's probably
11583 // easier on the hardware branch predictor, and stores aren't all that
11584 // expensive anyway.
11586 // Create the new basic blocks. One block contains all the XMM stores,
11587 // and one block is the final destination regardless of whether any
11588 // stores were performed.
11589 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11590 MachineFunction *F = MBB->getParent();
11591 MachineFunction::iterator MBBIter = MBB;
11593 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11594 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11595 F->insert(MBBIter, XMMSaveMBB);
11596 F->insert(MBBIter, EndMBB);
11598 // Transfer the remainder of MBB and its successor edges to EndMBB.
11599 EndMBB->splice(EndMBB->begin(), MBB,
11600 llvm::next(MachineBasicBlock::iterator(MI)),
11602 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11604 // The original block will now fall through to the XMM save block.
11605 MBB->addSuccessor(XMMSaveMBB);
11606 // The XMMSaveMBB will fall through to the end block.
11607 XMMSaveMBB->addSuccessor(EndMBB);
11609 // Now add the instructions.
11610 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11611 DebugLoc DL = MI->getDebugLoc();
11613 unsigned CountReg = MI->getOperand(0).getReg();
11614 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11615 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11617 if (!Subtarget->isTargetWin64()) {
11618 // If %al is 0, branch around the XMM save block.
11619 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11620 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11621 MBB->addSuccessor(EndMBB);
11624 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11625 // In the XMM save block, save all the XMM argument registers.
11626 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11627 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11628 MachineMemOperand *MMO =
11629 F->getMachineMemOperand(
11630 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11631 MachineMemOperand::MOStore,
11632 /*Size=*/16, /*Align=*/16);
11633 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11634 .addFrameIndex(RegSaveFrameIndex)
11635 .addImm(/*Scale=*/1)
11636 .addReg(/*IndexReg=*/0)
11637 .addImm(/*Disp=*/Offset)
11638 .addReg(/*Segment=*/0)
11639 .addReg(MI->getOperand(i).getReg())
11640 .addMemOperand(MMO);
11643 MI->eraseFromParent(); // The pseudo instruction is gone now.
11648 MachineBasicBlock *
11649 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11650 MachineBasicBlock *BB) const {
11651 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11652 DebugLoc DL = MI->getDebugLoc();
11654 // To "insert" a SELECT_CC instruction, we actually have to insert the
11655 // diamond control-flow pattern. The incoming instruction knows the
11656 // destination vreg to set, the condition code register to branch on, the
11657 // true/false values to select between, and a branch opcode to use.
11658 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11659 MachineFunction::iterator It = BB;
11665 // cmpTY ccX, r1, r2
11667 // fallthrough --> copy0MBB
11668 MachineBasicBlock *thisMBB = BB;
11669 MachineFunction *F = BB->getParent();
11670 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11671 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11672 F->insert(It, copy0MBB);
11673 F->insert(It, sinkMBB);
11675 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11676 // live into the sink and copy blocks.
11677 if (!MI->killsRegister(X86::EFLAGS)) {
11678 copy0MBB->addLiveIn(X86::EFLAGS);
11679 sinkMBB->addLiveIn(X86::EFLAGS);
11682 // Transfer the remainder of BB and its successor edges to sinkMBB.
11683 sinkMBB->splice(sinkMBB->begin(), BB,
11684 llvm::next(MachineBasicBlock::iterator(MI)),
11686 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11688 // Add the true and fallthrough blocks as its successors.
11689 BB->addSuccessor(copy0MBB);
11690 BB->addSuccessor(sinkMBB);
11692 // Create the conditional branch instruction.
11694 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11695 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11698 // %FalseValue = ...
11699 // # fallthrough to sinkMBB
11700 copy0MBB->addSuccessor(sinkMBB);
11703 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11705 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11706 TII->get(X86::PHI), MI->getOperand(0).getReg())
11707 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11708 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11710 MI->eraseFromParent(); // The pseudo instruction is gone now.
11714 MachineBasicBlock *
11715 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11716 bool Is64Bit) const {
11717 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11718 DebugLoc DL = MI->getDebugLoc();
11719 MachineFunction *MF = BB->getParent();
11720 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11722 assert(EnableSegmentedStacks);
11724 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11725 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11728 // ... [Till the alloca]
11729 // If stacklet is not large enough, jump to mallocMBB
11732 // Allocate by subtracting from RSP
11733 // Jump to continueMBB
11736 // Allocate by call to runtime
11740 // [rest of original BB]
11743 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11744 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11745 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11747 MachineRegisterInfo &MRI = MF->getRegInfo();
11748 const TargetRegisterClass *AddrRegClass =
11749 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
11751 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11752 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11753 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
11754 sizeVReg = MI->getOperand(1).getReg(),
11755 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
11757 MachineFunction::iterator MBBIter = BB;
11760 MF->insert(MBBIter, bumpMBB);
11761 MF->insert(MBBIter, mallocMBB);
11762 MF->insert(MBBIter, continueMBB);
11764 continueMBB->splice(continueMBB->begin(), BB, llvm::next
11765 (MachineBasicBlock::iterator(MI)), BB->end());
11766 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
11768 // Add code to the main basic block to check if the stack limit has been hit,
11769 // and if so, jump to mallocMBB otherwise to bumpMBB.
11770 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
11771 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
11772 .addReg(tmpSPVReg).addReg(sizeVReg);
11773 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
11774 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
11775 .addReg(tmpSPVReg);
11776 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
11778 // bumpMBB simply decreases the stack pointer, since we know the current
11779 // stacklet has enough space.
11780 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
11781 .addReg(tmpSPVReg);
11782 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
11783 .addReg(tmpSPVReg);
11784 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11786 // Calls into a routine in libgcc to allocate more space from the heap.
11788 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
11790 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
11791 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
11793 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
11795 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
11796 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
11797 .addExternalSymbol("__morestack_allocate_stack_space");
11801 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
11804 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
11805 .addReg(Is64Bit ? X86::RAX : X86::EAX);
11806 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11808 // Set up the CFG correctly.
11809 BB->addSuccessor(bumpMBB);
11810 BB->addSuccessor(mallocMBB);
11811 mallocMBB->addSuccessor(continueMBB);
11812 bumpMBB->addSuccessor(continueMBB);
11814 // Take care of the PHI nodes.
11815 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
11816 MI->getOperand(0).getReg())
11817 .addReg(mallocPtrVReg).addMBB(mallocMBB)
11818 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
11820 // Delete the original pseudo instruction.
11821 MI->eraseFromParent();
11824 return continueMBB;
11827 MachineBasicBlock *
11828 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11829 MachineBasicBlock *BB) const {
11830 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11831 DebugLoc DL = MI->getDebugLoc();
11833 assert(!Subtarget->isTargetEnvMacho());
11835 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11836 // non-trivial part is impdef of ESP.
11838 if (Subtarget->isTargetWin64()) {
11839 if (Subtarget->isTargetCygMing()) {
11840 // ___chkstk(Mingw64):
11841 // Clobbers R10, R11, RAX and EFLAGS.
11843 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11844 .addExternalSymbol("___chkstk")
11845 .addReg(X86::RAX, RegState::Implicit)
11846 .addReg(X86::RSP, RegState::Implicit)
11847 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11848 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11849 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11851 // __chkstk(MSVCRT): does not update stack pointer.
11852 // Clobbers R10, R11 and EFLAGS.
11853 // FIXME: RAX(allocated size) might be reused and not killed.
11854 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11855 .addExternalSymbol("__chkstk")
11856 .addReg(X86::RAX, RegState::Implicit)
11857 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11858 // RAX has the offset to subtracted from RSP.
11859 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11864 const char *StackProbeSymbol =
11865 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11867 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11868 .addExternalSymbol(StackProbeSymbol)
11869 .addReg(X86::EAX, RegState::Implicit)
11870 .addReg(X86::ESP, RegState::Implicit)
11871 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11872 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11873 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11876 MI->eraseFromParent(); // The pseudo instruction is gone now.
11880 MachineBasicBlock *
11881 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11882 MachineBasicBlock *BB) const {
11883 // This is pretty easy. We're taking the value that we received from
11884 // our load from the relocation, sticking it in either RDI (x86-64)
11885 // or EAX and doing an indirect call. The return value will then
11886 // be in the normal return register.
11887 const X86InstrInfo *TII
11888 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11889 DebugLoc DL = MI->getDebugLoc();
11890 MachineFunction *F = BB->getParent();
11892 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11893 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11895 if (Subtarget->is64Bit()) {
11896 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11897 TII->get(X86::MOV64rm), X86::RDI)
11899 .addImm(0).addReg(0)
11900 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11901 MI->getOperand(3).getTargetFlags())
11903 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11904 addDirectMem(MIB, X86::RDI);
11905 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11906 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11907 TII->get(X86::MOV32rm), X86::EAX)
11909 .addImm(0).addReg(0)
11910 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11911 MI->getOperand(3).getTargetFlags())
11913 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11914 addDirectMem(MIB, X86::EAX);
11916 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11917 TII->get(X86::MOV32rm), X86::EAX)
11918 .addReg(TII->getGlobalBaseReg(F))
11919 .addImm(0).addReg(0)
11920 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11921 MI->getOperand(3).getTargetFlags())
11923 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11924 addDirectMem(MIB, X86::EAX);
11927 MI->eraseFromParent(); // The pseudo instruction is gone now.
11931 MachineBasicBlock *
11932 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11933 MachineBasicBlock *BB) const {
11934 switch (MI->getOpcode()) {
11935 default: assert(false && "Unexpected instr type to insert");
11936 case X86::TAILJMPd64:
11937 case X86::TAILJMPr64:
11938 case X86::TAILJMPm64:
11939 assert(!"TAILJMP64 would not be touched here.");
11940 case X86::TCRETURNdi64:
11941 case X86::TCRETURNri64:
11942 case X86::TCRETURNmi64:
11943 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11944 // On AMD64, additional defs should be added before register allocation.
11945 if (!Subtarget->isTargetWin64()) {
11946 MI->addRegisterDefined(X86::RSI);
11947 MI->addRegisterDefined(X86::RDI);
11948 MI->addRegisterDefined(X86::XMM6);
11949 MI->addRegisterDefined(X86::XMM7);
11950 MI->addRegisterDefined(X86::XMM8);
11951 MI->addRegisterDefined(X86::XMM9);
11952 MI->addRegisterDefined(X86::XMM10);
11953 MI->addRegisterDefined(X86::XMM11);
11954 MI->addRegisterDefined(X86::XMM12);
11955 MI->addRegisterDefined(X86::XMM13);
11956 MI->addRegisterDefined(X86::XMM14);
11957 MI->addRegisterDefined(X86::XMM15);
11960 case X86::WIN_ALLOCA:
11961 return EmitLoweredWinAlloca(MI, BB);
11962 case X86::SEG_ALLOCA_32:
11963 return EmitLoweredSegAlloca(MI, BB, false);
11964 case X86::SEG_ALLOCA_64:
11965 return EmitLoweredSegAlloca(MI, BB, true);
11966 case X86::TLSCall_32:
11967 case X86::TLSCall_64:
11968 return EmitLoweredTLSCall(MI, BB);
11969 case X86::CMOV_GR8:
11970 case X86::CMOV_FR32:
11971 case X86::CMOV_FR64:
11972 case X86::CMOV_V4F32:
11973 case X86::CMOV_V2F64:
11974 case X86::CMOV_V2I64:
11975 case X86::CMOV_V8F32:
11976 case X86::CMOV_V4F64:
11977 case X86::CMOV_V4I64:
11978 case X86::CMOV_GR16:
11979 case X86::CMOV_GR32:
11980 case X86::CMOV_RFP32:
11981 case X86::CMOV_RFP64:
11982 case X86::CMOV_RFP80:
11983 return EmitLoweredSelect(MI, BB);
11985 case X86::FP32_TO_INT16_IN_MEM:
11986 case X86::FP32_TO_INT32_IN_MEM:
11987 case X86::FP32_TO_INT64_IN_MEM:
11988 case X86::FP64_TO_INT16_IN_MEM:
11989 case X86::FP64_TO_INT32_IN_MEM:
11990 case X86::FP64_TO_INT64_IN_MEM:
11991 case X86::FP80_TO_INT16_IN_MEM:
11992 case X86::FP80_TO_INT32_IN_MEM:
11993 case X86::FP80_TO_INT64_IN_MEM: {
11994 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11995 DebugLoc DL = MI->getDebugLoc();
11997 // Change the floating point control register to use "round towards zero"
11998 // mode when truncating to an integer value.
11999 MachineFunction *F = BB->getParent();
12000 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12001 addFrameReference(BuildMI(*BB, MI, DL,
12002 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12004 // Load the old value of the high byte of the control word...
12006 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12007 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12010 // Set the high part to be round to zero...
12011 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12014 // Reload the modified control word now...
12015 addFrameReference(BuildMI(*BB, MI, DL,
12016 TII->get(X86::FLDCW16m)), CWFrameIdx);
12018 // Restore the memory image of control word to original value
12019 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12022 // Get the X86 opcode to use.
12024 switch (MI->getOpcode()) {
12025 default: llvm_unreachable("illegal opcode!");
12026 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12027 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12028 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12029 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12030 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12031 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12032 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12033 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12034 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12038 MachineOperand &Op = MI->getOperand(0);
12040 AM.BaseType = X86AddressMode::RegBase;
12041 AM.Base.Reg = Op.getReg();
12043 AM.BaseType = X86AddressMode::FrameIndexBase;
12044 AM.Base.FrameIndex = Op.getIndex();
12046 Op = MI->getOperand(1);
12048 AM.Scale = Op.getImm();
12049 Op = MI->getOperand(2);
12051 AM.IndexReg = Op.getImm();
12052 Op = MI->getOperand(3);
12053 if (Op.isGlobal()) {
12054 AM.GV = Op.getGlobal();
12056 AM.Disp = Op.getImm();
12058 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12059 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12061 // Reload the original control word now.
12062 addFrameReference(BuildMI(*BB, MI, DL,
12063 TII->get(X86::FLDCW16m)), CWFrameIdx);
12065 MI->eraseFromParent(); // The pseudo instruction is gone now.
12068 // String/text processing lowering.
12069 case X86::PCMPISTRM128REG:
12070 case X86::VPCMPISTRM128REG:
12071 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12072 case X86::PCMPISTRM128MEM:
12073 case X86::VPCMPISTRM128MEM:
12074 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12075 case X86::PCMPESTRM128REG:
12076 case X86::VPCMPESTRM128REG:
12077 return EmitPCMP(MI, BB, 5, false /* in mem */);
12078 case X86::PCMPESTRM128MEM:
12079 case X86::VPCMPESTRM128MEM:
12080 return EmitPCMP(MI, BB, 5, true /* in mem */);
12082 // Thread synchronization.
12084 return EmitMonitor(MI, BB);
12086 return EmitMwait(MI, BB);
12088 // Atomic Lowering.
12089 case X86::ATOMAND32:
12090 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12091 X86::AND32ri, X86::MOV32rm,
12093 X86::NOT32r, X86::EAX,
12094 X86::GR32RegisterClass);
12095 case X86::ATOMOR32:
12096 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12097 X86::OR32ri, X86::MOV32rm,
12099 X86::NOT32r, X86::EAX,
12100 X86::GR32RegisterClass);
12101 case X86::ATOMXOR32:
12102 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12103 X86::XOR32ri, X86::MOV32rm,
12105 X86::NOT32r, X86::EAX,
12106 X86::GR32RegisterClass);
12107 case X86::ATOMNAND32:
12108 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12109 X86::AND32ri, X86::MOV32rm,
12111 X86::NOT32r, X86::EAX,
12112 X86::GR32RegisterClass, true);
12113 case X86::ATOMMIN32:
12114 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12115 case X86::ATOMMAX32:
12116 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12117 case X86::ATOMUMIN32:
12118 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12119 case X86::ATOMUMAX32:
12120 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12122 case X86::ATOMAND16:
12123 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12124 X86::AND16ri, X86::MOV16rm,
12126 X86::NOT16r, X86::AX,
12127 X86::GR16RegisterClass);
12128 case X86::ATOMOR16:
12129 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12130 X86::OR16ri, X86::MOV16rm,
12132 X86::NOT16r, X86::AX,
12133 X86::GR16RegisterClass);
12134 case X86::ATOMXOR16:
12135 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12136 X86::XOR16ri, X86::MOV16rm,
12138 X86::NOT16r, X86::AX,
12139 X86::GR16RegisterClass);
12140 case X86::ATOMNAND16:
12141 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12142 X86::AND16ri, X86::MOV16rm,
12144 X86::NOT16r, X86::AX,
12145 X86::GR16RegisterClass, true);
12146 case X86::ATOMMIN16:
12147 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12148 case X86::ATOMMAX16:
12149 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12150 case X86::ATOMUMIN16:
12151 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12152 case X86::ATOMUMAX16:
12153 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12155 case X86::ATOMAND8:
12156 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12157 X86::AND8ri, X86::MOV8rm,
12159 X86::NOT8r, X86::AL,
12160 X86::GR8RegisterClass);
12162 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12163 X86::OR8ri, X86::MOV8rm,
12165 X86::NOT8r, X86::AL,
12166 X86::GR8RegisterClass);
12167 case X86::ATOMXOR8:
12168 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12169 X86::XOR8ri, X86::MOV8rm,
12171 X86::NOT8r, X86::AL,
12172 X86::GR8RegisterClass);
12173 case X86::ATOMNAND8:
12174 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12175 X86::AND8ri, X86::MOV8rm,
12177 X86::NOT8r, X86::AL,
12178 X86::GR8RegisterClass, true);
12179 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12180 // This group is for 64-bit host.
12181 case X86::ATOMAND64:
12182 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12183 X86::AND64ri32, X86::MOV64rm,
12185 X86::NOT64r, X86::RAX,
12186 X86::GR64RegisterClass);
12187 case X86::ATOMOR64:
12188 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12189 X86::OR64ri32, X86::MOV64rm,
12191 X86::NOT64r, X86::RAX,
12192 X86::GR64RegisterClass);
12193 case X86::ATOMXOR64:
12194 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12195 X86::XOR64ri32, X86::MOV64rm,
12197 X86::NOT64r, X86::RAX,
12198 X86::GR64RegisterClass);
12199 case X86::ATOMNAND64:
12200 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12201 X86::AND64ri32, X86::MOV64rm,
12203 X86::NOT64r, X86::RAX,
12204 X86::GR64RegisterClass, true);
12205 case X86::ATOMMIN64:
12206 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12207 case X86::ATOMMAX64:
12208 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12209 case X86::ATOMUMIN64:
12210 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12211 case X86::ATOMUMAX64:
12212 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12214 // This group does 64-bit operations on a 32-bit host.
12215 case X86::ATOMAND6432:
12216 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12217 X86::AND32rr, X86::AND32rr,
12218 X86::AND32ri, X86::AND32ri,
12220 case X86::ATOMOR6432:
12221 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12222 X86::OR32rr, X86::OR32rr,
12223 X86::OR32ri, X86::OR32ri,
12225 case X86::ATOMXOR6432:
12226 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12227 X86::XOR32rr, X86::XOR32rr,
12228 X86::XOR32ri, X86::XOR32ri,
12230 case X86::ATOMNAND6432:
12231 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12232 X86::AND32rr, X86::AND32rr,
12233 X86::AND32ri, X86::AND32ri,
12235 case X86::ATOMADD6432:
12236 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12237 X86::ADD32rr, X86::ADC32rr,
12238 X86::ADD32ri, X86::ADC32ri,
12240 case X86::ATOMSUB6432:
12241 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12242 X86::SUB32rr, X86::SBB32rr,
12243 X86::SUB32ri, X86::SBB32ri,
12245 case X86::ATOMSWAP6432:
12246 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12247 X86::MOV32rr, X86::MOV32rr,
12248 X86::MOV32ri, X86::MOV32ri,
12250 case X86::VASTART_SAVE_XMM_REGS:
12251 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12253 case X86::VAARG_64:
12254 return EmitVAARG64WithCustomInserter(MI, BB);
12258 //===----------------------------------------------------------------------===//
12259 // X86 Optimization Hooks
12260 //===----------------------------------------------------------------------===//
12262 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12266 const SelectionDAG &DAG,
12267 unsigned Depth) const {
12268 unsigned Opc = Op.getOpcode();
12269 assert((Opc >= ISD::BUILTIN_OP_END ||
12270 Opc == ISD::INTRINSIC_WO_CHAIN ||
12271 Opc == ISD::INTRINSIC_W_CHAIN ||
12272 Opc == ISD::INTRINSIC_VOID) &&
12273 "Should use MaskedValueIsZero if you don't know whether Op"
12274 " is a target node!");
12276 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12290 // These nodes' second result is a boolean.
12291 if (Op.getResNo() == 0)
12294 case X86ISD::SETCC:
12295 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12296 Mask.getBitWidth() - 1);
12301 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12302 unsigned Depth) const {
12303 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12304 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12305 return Op.getValueType().getScalarType().getSizeInBits();
12311 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12312 /// node is a GlobalAddress + offset.
12313 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12314 const GlobalValue* &GA,
12315 int64_t &Offset) const {
12316 if (N->getOpcode() == X86ISD::Wrapper) {
12317 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12318 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12319 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12323 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12326 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12327 /// same as extracting the high 128-bit part of 256-bit vector and then
12328 /// inserting the result into the low part of a new 256-bit vector
12329 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12330 EVT VT = SVOp->getValueType(0);
12331 int NumElems = VT.getVectorNumElements();
12333 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12334 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12335 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12336 SVOp->getMaskElt(j) >= 0)
12342 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12343 /// same as extracting the low 128-bit part of 256-bit vector and then
12344 /// inserting the result into the high part of a new 256-bit vector
12345 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12346 EVT VT = SVOp->getValueType(0);
12347 int NumElems = VT.getVectorNumElements();
12349 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12350 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12351 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12352 SVOp->getMaskElt(j) >= 0)
12358 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12359 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12360 TargetLowering::DAGCombinerInfo &DCI) {
12361 DebugLoc dl = N->getDebugLoc();
12362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12363 SDValue V1 = SVOp->getOperand(0);
12364 SDValue V2 = SVOp->getOperand(1);
12365 EVT VT = SVOp->getValueType(0);
12366 int NumElems = VT.getVectorNumElements();
12368 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12369 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12373 // V UNDEF BUILD_VECTOR UNDEF
12375 // CONCAT_VECTOR CONCAT_VECTOR
12378 // RESULT: V + zero extended
12380 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12381 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12382 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12385 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12388 // To match the shuffle mask, the first half of the mask should
12389 // be exactly the first vector, and all the rest a splat with the
12390 // first element of the second one.
12391 for (int i = 0; i < NumElems/2; ++i)
12392 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12393 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12396 // Emit a zeroed vector and insert the desired subvector on its
12398 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
12399 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12400 DAG.getConstant(0, MVT::i32), DAG, dl);
12401 return DCI.CombineTo(N, InsV);
12404 //===--------------------------------------------------------------------===//
12405 // Combine some shuffles into subvector extracts and inserts:
12408 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12409 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12410 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12412 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12413 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12414 return DCI.CombineTo(N, InsV);
12417 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12418 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12419 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12420 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12421 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12422 return DCI.CombineTo(N, InsV);
12428 /// PerformShuffleCombine - Performs several different shuffle combines.
12429 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12430 TargetLowering::DAGCombinerInfo &DCI,
12431 const X86Subtarget *Subtarget) {
12432 DebugLoc dl = N->getDebugLoc();
12433 EVT VT = N->getValueType(0);
12435 // Don't create instructions with illegal types after legalize types has run.
12436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12437 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12440 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12441 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12442 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12443 return PerformShuffleCombine256(N, DAG, DCI);
12445 // Only handle 128 wide vector from here on.
12446 if (VT.getSizeInBits() != 128)
12449 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12450 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12451 // consecutive, non-overlapping, and in the right order.
12452 SmallVector<SDValue, 16> Elts;
12453 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12454 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12456 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12459 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12460 /// generation and convert it from being a bunch of shuffles and extracts
12461 /// to a simple store and scalar loads to extract the elements.
12462 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12463 const TargetLowering &TLI) {
12464 SDValue InputVector = N->getOperand(0);
12466 // Only operate on vectors of 4 elements, where the alternative shuffling
12467 // gets to be more expensive.
12468 if (InputVector.getValueType() != MVT::v4i32)
12471 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12472 // single use which is a sign-extend or zero-extend, and all elements are
12474 SmallVector<SDNode *, 4> Uses;
12475 unsigned ExtractedElements = 0;
12476 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12477 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12478 if (UI.getUse().getResNo() != InputVector.getResNo())
12481 SDNode *Extract = *UI;
12482 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12485 if (Extract->getValueType(0) != MVT::i32)
12487 if (!Extract->hasOneUse())
12489 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12490 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12492 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12495 // Record which element was extracted.
12496 ExtractedElements |=
12497 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12499 Uses.push_back(Extract);
12502 // If not all the elements were used, this may not be worthwhile.
12503 if (ExtractedElements != 15)
12506 // Ok, we've now decided to do the transformation.
12507 DebugLoc dl = InputVector.getDebugLoc();
12509 // Store the value to a temporary stack slot.
12510 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12511 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12512 MachinePointerInfo(), false, false, 0);
12514 // Replace each use (extract) with a load of the appropriate element.
12515 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12516 UE = Uses.end(); UI != UE; ++UI) {
12517 SDNode *Extract = *UI;
12519 // cOMpute the element's address.
12520 SDValue Idx = Extract->getOperand(1);
12522 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12523 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12524 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12526 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12527 StackPtr, OffsetVal);
12529 // Load the scalar.
12530 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12531 ScalarAddr, MachinePointerInfo(),
12534 // Replace the exact with the load.
12535 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12538 // The replacement was made in place; don't return anything.
12542 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12543 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12544 const X86Subtarget *Subtarget) {
12545 DebugLoc DL = N->getDebugLoc();
12546 SDValue Cond = N->getOperand(0);
12547 // Get the LHS/RHS of the select.
12548 SDValue LHS = N->getOperand(1);
12549 SDValue RHS = N->getOperand(2);
12551 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12552 // instructions match the semantics of the common C idiom x<y?x:y but not
12553 // x<=y?x:y, because of how they handle negative zero (which can be
12554 // ignored in unsafe-math mode).
12555 if (Subtarget->hasSSE2() &&
12556 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12557 Cond.getOpcode() == ISD::SETCC) {
12558 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12560 unsigned Opcode = 0;
12561 // Check for x CC y ? x : y.
12562 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12563 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12567 // Converting this to a min would handle NaNs incorrectly, and swapping
12568 // the operands would cause it to handle comparisons between positive
12569 // and negative zero incorrectly.
12570 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12571 if (!UnsafeFPMath &&
12572 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12574 std::swap(LHS, RHS);
12576 Opcode = X86ISD::FMIN;
12579 // Converting this to a min would handle comparisons between positive
12580 // and negative zero incorrectly.
12581 if (!UnsafeFPMath &&
12582 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12584 Opcode = X86ISD::FMIN;
12587 // Converting this to a min would handle both negative zeros and NaNs
12588 // incorrectly, but we can swap the operands to fix both.
12589 std::swap(LHS, RHS);
12593 Opcode = X86ISD::FMIN;
12597 // Converting this to a max would handle comparisons between positive
12598 // and negative zero incorrectly.
12599 if (!UnsafeFPMath &&
12600 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12602 Opcode = X86ISD::FMAX;
12605 // Converting this to a max would handle NaNs incorrectly, and swapping
12606 // the operands would cause it to handle comparisons between positive
12607 // and negative zero incorrectly.
12608 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12609 if (!UnsafeFPMath &&
12610 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12612 std::swap(LHS, RHS);
12614 Opcode = X86ISD::FMAX;
12617 // Converting this to a max would handle both negative zeros and NaNs
12618 // incorrectly, but we can swap the operands to fix both.
12619 std::swap(LHS, RHS);
12623 Opcode = X86ISD::FMAX;
12626 // Check for x CC y ? y : x -- a min/max with reversed arms.
12627 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12628 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12632 // Converting this to a min would handle comparisons between positive
12633 // and negative zero incorrectly, and swapping the operands would
12634 // cause it to handle NaNs incorrectly.
12635 if (!UnsafeFPMath &&
12636 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12637 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12639 std::swap(LHS, RHS);
12641 Opcode = X86ISD::FMIN;
12644 // Converting this to a min would handle NaNs incorrectly.
12645 if (!UnsafeFPMath &&
12646 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12648 Opcode = X86ISD::FMIN;
12651 // Converting this to a min would handle both negative zeros and NaNs
12652 // incorrectly, but we can swap the operands to fix both.
12653 std::swap(LHS, RHS);
12657 Opcode = X86ISD::FMIN;
12661 // Converting this to a max would handle NaNs incorrectly.
12662 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12664 Opcode = X86ISD::FMAX;
12667 // Converting this to a max would handle comparisons between positive
12668 // and negative zero incorrectly, and swapping the operands would
12669 // cause it to handle NaNs incorrectly.
12670 if (!UnsafeFPMath &&
12671 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12672 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12674 std::swap(LHS, RHS);
12676 Opcode = X86ISD::FMAX;
12679 // Converting this to a max would handle both negative zeros and NaNs
12680 // incorrectly, but we can swap the operands to fix both.
12681 std::swap(LHS, RHS);
12685 Opcode = X86ISD::FMAX;
12691 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12694 // If this is a select between two integer constants, try to do some
12696 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12697 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12698 // Don't do this for crazy integer types.
12699 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12700 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12701 // so that TrueC (the true value) is larger than FalseC.
12702 bool NeedsCondInvert = false;
12704 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12705 // Efficiently invertible.
12706 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12707 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12708 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12709 NeedsCondInvert = true;
12710 std::swap(TrueC, FalseC);
12713 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12714 if (FalseC->getAPIntValue() == 0 &&
12715 TrueC->getAPIntValue().isPowerOf2()) {
12716 if (NeedsCondInvert) // Invert the condition if needed.
12717 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12718 DAG.getConstant(1, Cond.getValueType()));
12720 // Zero extend the condition if needed.
12721 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12723 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12724 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12725 DAG.getConstant(ShAmt, MVT::i8));
12728 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12729 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12730 if (NeedsCondInvert) // Invert the condition if needed.
12731 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12732 DAG.getConstant(1, Cond.getValueType()));
12734 // Zero extend the condition if needed.
12735 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12736 FalseC->getValueType(0), Cond);
12737 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12738 SDValue(FalseC, 0));
12741 // Optimize cases that will turn into an LEA instruction. This requires
12742 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12743 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12744 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12745 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12747 bool isFastMultiplier = false;
12749 switch ((unsigned char)Diff) {
12751 case 1: // result = add base, cond
12752 case 2: // result = lea base( , cond*2)
12753 case 3: // result = lea base(cond, cond*2)
12754 case 4: // result = lea base( , cond*4)
12755 case 5: // result = lea base(cond, cond*4)
12756 case 8: // result = lea base( , cond*8)
12757 case 9: // result = lea base(cond, cond*8)
12758 isFastMultiplier = true;
12763 if (isFastMultiplier) {
12764 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12765 if (NeedsCondInvert) // Invert the condition if needed.
12766 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12767 DAG.getConstant(1, Cond.getValueType()));
12769 // Zero extend the condition if needed.
12770 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12772 // Scale the condition by the difference.
12774 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12775 DAG.getConstant(Diff, Cond.getValueType()));
12777 // Add the base if non-zero.
12778 if (FalseC->getAPIntValue() != 0)
12779 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12780 SDValue(FalseC, 0));
12790 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12791 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12792 TargetLowering::DAGCombinerInfo &DCI) {
12793 DebugLoc DL = N->getDebugLoc();
12795 // If the flag operand isn't dead, don't touch this CMOV.
12796 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12799 SDValue FalseOp = N->getOperand(0);
12800 SDValue TrueOp = N->getOperand(1);
12801 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12802 SDValue Cond = N->getOperand(3);
12803 if (CC == X86::COND_E || CC == X86::COND_NE) {
12804 switch (Cond.getOpcode()) {
12808 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12809 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12810 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12814 // If this is a select between two integer constants, try to do some
12815 // optimizations. Note that the operands are ordered the opposite of SELECT
12817 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12818 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12819 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12820 // larger than FalseC (the false value).
12821 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12822 CC = X86::GetOppositeBranchCondition(CC);
12823 std::swap(TrueC, FalseC);
12826 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12827 // This is efficient for any integer data type (including i8/i16) and
12829 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12830 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12831 DAG.getConstant(CC, MVT::i8), Cond);
12833 // Zero extend the condition if needed.
12834 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12836 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12837 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12838 DAG.getConstant(ShAmt, MVT::i8));
12839 if (N->getNumValues() == 2) // Dead flag value?
12840 return DCI.CombineTo(N, Cond, SDValue());
12844 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12845 // for any integer data type, including i8/i16.
12846 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12847 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12848 DAG.getConstant(CC, MVT::i8), Cond);
12850 // Zero extend the condition if needed.
12851 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12852 FalseC->getValueType(0), Cond);
12853 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12854 SDValue(FalseC, 0));
12856 if (N->getNumValues() == 2) // Dead flag value?
12857 return DCI.CombineTo(N, Cond, SDValue());
12861 // Optimize cases that will turn into an LEA instruction. This requires
12862 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12863 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12864 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12865 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12867 bool isFastMultiplier = false;
12869 switch ((unsigned char)Diff) {
12871 case 1: // result = add base, cond
12872 case 2: // result = lea base( , cond*2)
12873 case 3: // result = lea base(cond, cond*2)
12874 case 4: // result = lea base( , cond*4)
12875 case 5: // result = lea base(cond, cond*4)
12876 case 8: // result = lea base( , cond*8)
12877 case 9: // result = lea base(cond, cond*8)
12878 isFastMultiplier = true;
12883 if (isFastMultiplier) {
12884 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12885 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12886 DAG.getConstant(CC, MVT::i8), Cond);
12887 // Zero extend the condition if needed.
12888 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12890 // Scale the condition by the difference.
12892 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12893 DAG.getConstant(Diff, Cond.getValueType()));
12895 // Add the base if non-zero.
12896 if (FalseC->getAPIntValue() != 0)
12897 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12898 SDValue(FalseC, 0));
12899 if (N->getNumValues() == 2) // Dead flag value?
12900 return DCI.CombineTo(N, Cond, SDValue());
12910 /// PerformMulCombine - Optimize a single multiply with constant into two
12911 /// in order to implement it with two cheaper instructions, e.g.
12912 /// LEA + SHL, LEA + LEA.
12913 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12914 TargetLowering::DAGCombinerInfo &DCI) {
12915 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12918 EVT VT = N->getValueType(0);
12919 if (VT != MVT::i64)
12922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12925 uint64_t MulAmt = C->getZExtValue();
12926 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12929 uint64_t MulAmt1 = 0;
12930 uint64_t MulAmt2 = 0;
12931 if ((MulAmt % 9) == 0) {
12933 MulAmt2 = MulAmt / 9;
12934 } else if ((MulAmt % 5) == 0) {
12936 MulAmt2 = MulAmt / 5;
12937 } else if ((MulAmt % 3) == 0) {
12939 MulAmt2 = MulAmt / 3;
12942 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12943 DebugLoc DL = N->getDebugLoc();
12945 if (isPowerOf2_64(MulAmt2) &&
12946 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12947 // If second multiplifer is pow2, issue it first. We want the multiply by
12948 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12950 std::swap(MulAmt1, MulAmt2);
12953 if (isPowerOf2_64(MulAmt1))
12954 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12955 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12957 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12958 DAG.getConstant(MulAmt1, VT));
12960 if (isPowerOf2_64(MulAmt2))
12961 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12962 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12964 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12965 DAG.getConstant(MulAmt2, VT));
12967 // Do not add new nodes to DAG combiner worklist.
12968 DCI.CombineTo(N, NewMul, false);
12973 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12974 SDValue N0 = N->getOperand(0);
12975 SDValue N1 = N->getOperand(1);
12976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12977 EVT VT = N0.getValueType();
12979 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12980 // since the result of setcc_c is all zero's or all ones.
12981 if (N1C && N0.getOpcode() == ISD::AND &&
12982 N0.getOperand(1).getOpcode() == ISD::Constant) {
12983 SDValue N00 = N0.getOperand(0);
12984 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12985 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12986 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12987 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12988 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12989 APInt ShAmt = N1C->getAPIntValue();
12990 Mask = Mask.shl(ShAmt);
12992 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12993 N00, DAG.getConstant(Mask, VT));
13000 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13002 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13003 const X86Subtarget *Subtarget) {
13004 EVT VT = N->getValueType(0);
13005 if (!VT.isVector() && VT.isInteger() &&
13006 N->getOpcode() == ISD::SHL)
13007 return PerformSHLCombine(N, DAG);
13009 // On X86 with SSE2 support, we can transform this to a vector shift if
13010 // all elements are shifted by the same amount. We can't do this in legalize
13011 // because the a constant vector is typically transformed to a constant pool
13012 // so we have no knowledge of the shift amount.
13013 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
13016 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13019 SDValue ShAmtOp = N->getOperand(1);
13020 EVT EltVT = VT.getVectorElementType();
13021 DebugLoc DL = N->getDebugLoc();
13022 SDValue BaseShAmt = SDValue();
13023 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13024 unsigned NumElts = VT.getVectorNumElements();
13026 for (; i != NumElts; ++i) {
13027 SDValue Arg = ShAmtOp.getOperand(i);
13028 if (Arg.getOpcode() == ISD::UNDEF) continue;
13032 for (; i != NumElts; ++i) {
13033 SDValue Arg = ShAmtOp.getOperand(i);
13034 if (Arg.getOpcode() == ISD::UNDEF) continue;
13035 if (Arg != BaseShAmt) {
13039 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13040 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13041 SDValue InVec = ShAmtOp.getOperand(0);
13042 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13043 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13045 for (; i != NumElts; ++i) {
13046 SDValue Arg = InVec.getOperand(i);
13047 if (Arg.getOpcode() == ISD::UNDEF) continue;
13051 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13053 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13054 if (C->getZExtValue() == SplatIdx)
13055 BaseShAmt = InVec.getOperand(1);
13058 if (BaseShAmt.getNode() == 0)
13059 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13060 DAG.getIntPtrConstant(0));
13064 // The shift amount is an i32.
13065 if (EltVT.bitsGT(MVT::i32))
13066 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13067 else if (EltVT.bitsLT(MVT::i32))
13068 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13070 // The shift amount is identical so we can do a vector shift.
13071 SDValue ValOp = N->getOperand(0);
13072 switch (N->getOpcode()) {
13074 llvm_unreachable("Unknown shift opcode!");
13077 if (VT == MVT::v2i64)
13078 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13079 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13081 if (VT == MVT::v4i32)
13082 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13083 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13085 if (VT == MVT::v8i16)
13086 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13087 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13091 if (VT == MVT::v4i32)
13092 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13093 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13095 if (VT == MVT::v8i16)
13096 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13097 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13101 if (VT == MVT::v2i64)
13102 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13103 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13105 if (VT == MVT::v4i32)
13106 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13107 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13109 if (VT == MVT::v8i16)
13110 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13111 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13119 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13120 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13121 // and friends. Likewise for OR -> CMPNEQSS.
13122 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13123 TargetLowering::DAGCombinerInfo &DCI,
13124 const X86Subtarget *Subtarget) {
13127 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13128 // we're requiring SSE2 for both.
13129 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13130 SDValue N0 = N->getOperand(0);
13131 SDValue N1 = N->getOperand(1);
13132 SDValue CMP0 = N0->getOperand(1);
13133 SDValue CMP1 = N1->getOperand(1);
13134 DebugLoc DL = N->getDebugLoc();
13136 // The SETCCs should both refer to the same CMP.
13137 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13140 SDValue CMP00 = CMP0->getOperand(0);
13141 SDValue CMP01 = CMP0->getOperand(1);
13142 EVT VT = CMP00.getValueType();
13144 if (VT == MVT::f32 || VT == MVT::f64) {
13145 bool ExpectingFlags = false;
13146 // Check for any users that want flags:
13147 for (SDNode::use_iterator UI = N->use_begin(),
13149 !ExpectingFlags && UI != UE; ++UI)
13150 switch (UI->getOpcode()) {
13155 ExpectingFlags = true;
13157 case ISD::CopyToReg:
13158 case ISD::SIGN_EXTEND:
13159 case ISD::ZERO_EXTEND:
13160 case ISD::ANY_EXTEND:
13164 if (!ExpectingFlags) {
13165 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13166 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13168 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13169 X86::CondCode tmp = cc0;
13174 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13175 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13176 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13177 X86ISD::NodeType NTOperator = is64BitFP ?
13178 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13179 // FIXME: need symbolic constants for these magic numbers.
13180 // See X86ATTInstPrinter.cpp:printSSECC().
13181 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13182 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13183 DAG.getConstant(x86cc, MVT::i8));
13184 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13186 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13187 DAG.getConstant(1, MVT::i32));
13188 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13189 return OneBitOfTruth;
13197 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13198 /// so it can be folded inside ANDNP.
13199 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13200 EVT VT = N->getValueType(0);
13202 // Match direct AllOnes for 128 and 256-bit vectors
13203 if (ISD::isBuildVectorAllOnes(N))
13206 // Look through a bit convert.
13207 if (N->getOpcode() == ISD::BITCAST)
13208 N = N->getOperand(0).getNode();
13210 // Sometimes the operand may come from a insert_subvector building a 256-bit
13212 if (VT.getSizeInBits() == 256 &&
13213 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13214 SDValue V1 = N->getOperand(0);
13215 SDValue V2 = N->getOperand(1);
13217 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13218 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13219 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13220 ISD::isBuildVectorAllOnes(V2.getNode()))
13227 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13228 TargetLowering::DAGCombinerInfo &DCI,
13229 const X86Subtarget *Subtarget) {
13230 if (DCI.isBeforeLegalizeOps())
13233 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13237 // Want to form ANDNP nodes:
13238 // 1) In the hopes of then easily combining them with OR and AND nodes
13239 // to form PBLEND/PSIGN.
13240 // 2) To match ANDN packed intrinsics
13241 EVT VT = N->getValueType(0);
13242 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13245 SDValue N0 = N->getOperand(0);
13246 SDValue N1 = N->getOperand(1);
13247 DebugLoc DL = N->getDebugLoc();
13249 // Check LHS for vnot
13250 if (N0.getOpcode() == ISD::XOR &&
13251 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13252 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13253 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13255 // Check RHS for vnot
13256 if (N1.getOpcode() == ISD::XOR &&
13257 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13258 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13259 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13264 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13265 TargetLowering::DAGCombinerInfo &DCI,
13266 const X86Subtarget *Subtarget) {
13267 if (DCI.isBeforeLegalizeOps())
13270 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13274 EVT VT = N->getValueType(0);
13275 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13278 SDValue N0 = N->getOperand(0);
13279 SDValue N1 = N->getOperand(1);
13281 // look for psign/blend
13282 if (Subtarget->hasSSSE3()) {
13283 if (VT == MVT::v2i64) {
13284 // Canonicalize pandn to RHS
13285 if (N0.getOpcode() == X86ISD::ANDNP)
13287 // or (and (m, x), (pandn m, y))
13288 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13289 SDValue Mask = N1.getOperand(0);
13290 SDValue X = N1.getOperand(1);
13292 if (N0.getOperand(0) == Mask)
13293 Y = N0.getOperand(1);
13294 if (N0.getOperand(1) == Mask)
13295 Y = N0.getOperand(0);
13297 // Check to see if the mask appeared in both the AND and ANDNP and
13301 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13302 if (Mask.getOpcode() != ISD::BITCAST ||
13303 X.getOpcode() != ISD::BITCAST ||
13304 Y.getOpcode() != ISD::BITCAST)
13307 // Look through mask bitcast.
13308 Mask = Mask.getOperand(0);
13309 EVT MaskVT = Mask.getValueType();
13311 // Validate that the Mask operand is a vector sra node. The sra node
13312 // will be an intrinsic.
13313 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13316 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13317 // there is no psrai.b
13318 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13319 case Intrinsic::x86_sse2_psrai_w:
13320 case Intrinsic::x86_sse2_psrai_d:
13322 default: return SDValue();
13325 // Check that the SRA is all signbits.
13326 SDValue SraC = Mask.getOperand(2);
13327 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13328 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13329 if ((SraAmt + 1) != EltBits)
13332 DebugLoc DL = N->getDebugLoc();
13334 // Now we know we at least have a plendvb with the mask val. See if
13335 // we can form a psignb/w/d.
13336 // psign = x.type == y.type == mask.type && y = sub(0, x);
13337 X = X.getOperand(0);
13338 Y = Y.getOperand(0);
13339 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13340 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13341 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13344 case 8: Opc = X86ISD::PSIGNB; break;
13345 case 16: Opc = X86ISD::PSIGNW; break;
13346 case 32: Opc = X86ISD::PSIGND; break;
13350 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13351 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13354 // PBLENDVB only available on SSE 4.1
13355 if (!Subtarget->hasSSE41())
13358 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13359 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13360 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13361 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
13362 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13367 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13368 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13370 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13372 if (!N0.hasOneUse() || !N1.hasOneUse())
13375 SDValue ShAmt0 = N0.getOperand(1);
13376 if (ShAmt0.getValueType() != MVT::i8)
13378 SDValue ShAmt1 = N1.getOperand(1);
13379 if (ShAmt1.getValueType() != MVT::i8)
13381 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13382 ShAmt0 = ShAmt0.getOperand(0);
13383 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13384 ShAmt1 = ShAmt1.getOperand(0);
13386 DebugLoc DL = N->getDebugLoc();
13387 unsigned Opc = X86ISD::SHLD;
13388 SDValue Op0 = N0.getOperand(0);
13389 SDValue Op1 = N1.getOperand(0);
13390 if (ShAmt0.getOpcode() == ISD::SUB) {
13391 Opc = X86ISD::SHRD;
13392 std::swap(Op0, Op1);
13393 std::swap(ShAmt0, ShAmt1);
13396 unsigned Bits = VT.getSizeInBits();
13397 if (ShAmt1.getOpcode() == ISD::SUB) {
13398 SDValue Sum = ShAmt1.getOperand(0);
13399 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13400 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13401 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13402 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13403 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13404 return DAG.getNode(Opc, DL, VT,
13406 DAG.getNode(ISD::TRUNCATE, DL,
13409 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13410 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13412 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13413 return DAG.getNode(Opc, DL, VT,
13414 N0.getOperand(0), N1.getOperand(0),
13415 DAG.getNode(ISD::TRUNCATE, DL,
13422 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13423 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13424 const X86Subtarget *Subtarget) {
13425 StoreSDNode *St = cast<StoreSDNode>(N);
13426 EVT VT = St->getValue().getValueType();
13427 EVT StVT = St->getMemoryVT();
13428 DebugLoc dl = St->getDebugLoc();
13429 SDValue StoredVal = St->getOperand(1);
13430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13432 // If we are saving a concatination of two XMM registers, perform two stores.
13433 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13434 // 128-bit ones. If in the future the cost becomes only one memory access the
13435 // first version would be better.
13436 if (VT.getSizeInBits() == 256 &&
13437 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13438 StoredVal.getNumOperands() == 2) {
13440 SDValue Value0 = StoredVal.getOperand(0);
13441 SDValue Value1 = StoredVal.getOperand(1);
13443 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13444 SDValue Ptr0 = St->getBasePtr();
13445 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13447 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13448 St->getPointerInfo(), St->isVolatile(),
13449 St->isNonTemporal(), St->getAlignment());
13450 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13451 St->getPointerInfo(), St->isVolatile(),
13452 St->isNonTemporal(), St->getAlignment());
13453 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13456 // Optimize trunc store (of multiple scalars) to shuffle and store.
13457 // First, pack all of the elements in one place. Next, store to memory
13458 // in fewer chunks.
13459 if (St->isTruncatingStore() && VT.isVector()) {
13460 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13461 unsigned NumElems = VT.getVectorNumElements();
13462 assert(StVT != VT && "Cannot truncate to the same type");
13463 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13464 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13466 // From, To sizes and ElemCount must be pow of two
13467 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13468 // We are going to use the original vector elt for storing.
13469 // accumulated smaller vector elements must be a multiple of bigger size.
13470 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
13471 unsigned SizeRatio = FromSz / ToSz;
13473 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13475 // Create a type on which we perform the shuffle
13476 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13477 StVT.getScalarType(), NumElems*SizeRatio);
13479 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13481 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13482 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13483 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13485 // Can't shuffle using an illegal type
13486 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13488 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13489 DAG.getUNDEF(WideVec.getValueType()),
13490 ShuffleVec.data());
13491 // At this point all of the data is stored at the bottom of the
13492 // register. We now need to save it to mem.
13494 // Find the largest store unit
13495 MVT StoreType = MVT::i8;
13496 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13497 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13498 MVT Tp = (MVT::SimpleValueType)tp;
13499 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13503 // Bitcast the original vector into a vector of store-size units
13504 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13505 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13506 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13507 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13508 SmallVector<SDValue, 8> Chains;
13509 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13510 TLI.getPointerTy());
13511 SDValue Ptr = St->getBasePtr();
13513 // Perform one or more big stores into memory.
13514 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13515 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13516 StoreType, ShuffWide,
13517 DAG.getIntPtrConstant(i));
13518 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13519 St->getPointerInfo(), St->isVolatile(),
13520 St->isNonTemporal(), St->getAlignment());
13521 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13522 Chains.push_back(Ch);
13525 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13530 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13531 // the FP state in cases where an emms may be missing.
13532 // A preferable solution to the general problem is to figure out the right
13533 // places to insert EMMS. This qualifies as a quick hack.
13535 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13536 if (VT.getSizeInBits() != 64)
13539 const Function *F = DAG.getMachineFunction().getFunction();
13540 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13541 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13542 && Subtarget->hasSSE2();
13543 if ((VT.isVector() ||
13544 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13545 isa<LoadSDNode>(St->getValue()) &&
13546 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13547 St->getChain().hasOneUse() && !St->isVolatile()) {
13548 SDNode* LdVal = St->getValue().getNode();
13549 LoadSDNode *Ld = 0;
13550 int TokenFactorIndex = -1;
13551 SmallVector<SDValue, 8> Ops;
13552 SDNode* ChainVal = St->getChain().getNode();
13553 // Must be a store of a load. We currently handle two cases: the load
13554 // is a direct child, and it's under an intervening TokenFactor. It is
13555 // possible to dig deeper under nested TokenFactors.
13556 if (ChainVal == LdVal)
13557 Ld = cast<LoadSDNode>(St->getChain());
13558 else if (St->getValue().hasOneUse() &&
13559 ChainVal->getOpcode() == ISD::TokenFactor) {
13560 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13561 if (ChainVal->getOperand(i).getNode() == LdVal) {
13562 TokenFactorIndex = i;
13563 Ld = cast<LoadSDNode>(St->getValue());
13565 Ops.push_back(ChainVal->getOperand(i));
13569 if (!Ld || !ISD::isNormalLoad(Ld))
13572 // If this is not the MMX case, i.e. we are just turning i64 load/store
13573 // into f64 load/store, avoid the transformation if there are multiple
13574 // uses of the loaded value.
13575 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13578 DebugLoc LdDL = Ld->getDebugLoc();
13579 DebugLoc StDL = N->getDebugLoc();
13580 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13581 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13583 if (Subtarget->is64Bit() || F64IsLegal) {
13584 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13585 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13586 Ld->getPointerInfo(), Ld->isVolatile(),
13587 Ld->isNonTemporal(), Ld->getAlignment());
13588 SDValue NewChain = NewLd.getValue(1);
13589 if (TokenFactorIndex != -1) {
13590 Ops.push_back(NewChain);
13591 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13594 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13595 St->getPointerInfo(),
13596 St->isVolatile(), St->isNonTemporal(),
13597 St->getAlignment());
13600 // Otherwise, lower to two pairs of 32-bit loads / stores.
13601 SDValue LoAddr = Ld->getBasePtr();
13602 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13603 DAG.getConstant(4, MVT::i32));
13605 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13606 Ld->getPointerInfo(),
13607 Ld->isVolatile(), Ld->isNonTemporal(),
13608 Ld->getAlignment());
13609 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13610 Ld->getPointerInfo().getWithOffset(4),
13611 Ld->isVolatile(), Ld->isNonTemporal(),
13612 MinAlign(Ld->getAlignment(), 4));
13614 SDValue NewChain = LoLd.getValue(1);
13615 if (TokenFactorIndex != -1) {
13616 Ops.push_back(LoLd);
13617 Ops.push_back(HiLd);
13618 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13622 LoAddr = St->getBasePtr();
13623 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13624 DAG.getConstant(4, MVT::i32));
13626 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13627 St->getPointerInfo(),
13628 St->isVolatile(), St->isNonTemporal(),
13629 St->getAlignment());
13630 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13631 St->getPointerInfo().getWithOffset(4),
13633 St->isNonTemporal(),
13634 MinAlign(St->getAlignment(), 4));
13635 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13640 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13641 /// X86ISD::FXOR nodes.
13642 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13643 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13644 // F[X]OR(0.0, x) -> x
13645 // F[X]OR(x, 0.0) -> x
13646 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13647 if (C->getValueAPF().isPosZero())
13648 return N->getOperand(1);
13649 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13650 if (C->getValueAPF().isPosZero())
13651 return N->getOperand(0);
13655 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13656 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13657 // FAND(0.0, x) -> 0.0
13658 // FAND(x, 0.0) -> 0.0
13659 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13660 if (C->getValueAPF().isPosZero())
13661 return N->getOperand(0);
13662 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13663 if (C->getValueAPF().isPosZero())
13664 return N->getOperand(1);
13668 static SDValue PerformBTCombine(SDNode *N,
13670 TargetLowering::DAGCombinerInfo &DCI) {
13671 // BT ignores high bits in the bit index operand.
13672 SDValue Op1 = N->getOperand(1);
13673 if (Op1.hasOneUse()) {
13674 unsigned BitWidth = Op1.getValueSizeInBits();
13675 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13676 APInt KnownZero, KnownOne;
13677 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13678 !DCI.isBeforeLegalizeOps());
13679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13680 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13681 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13682 DCI.CommitTargetLoweringOpt(TLO);
13687 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13688 SDValue Op = N->getOperand(0);
13689 if (Op.getOpcode() == ISD::BITCAST)
13690 Op = Op.getOperand(0);
13691 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13692 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13693 VT.getVectorElementType().getSizeInBits() ==
13694 OpVT.getVectorElementType().getSizeInBits()) {
13695 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13700 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13701 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13702 // (and (i32 x86isd::setcc_carry), 1)
13703 // This eliminates the zext. This transformation is necessary because
13704 // ISD::SETCC is always legalized to i8.
13705 DebugLoc dl = N->getDebugLoc();
13706 SDValue N0 = N->getOperand(0);
13707 EVT VT = N->getValueType(0);
13708 if (N0.getOpcode() == ISD::AND &&
13710 N0.getOperand(0).hasOneUse()) {
13711 SDValue N00 = N0.getOperand(0);
13712 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13714 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13715 if (!C || C->getZExtValue() != 1)
13717 return DAG.getNode(ISD::AND, dl, VT,
13718 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13719 N00.getOperand(0), N00.getOperand(1)),
13720 DAG.getConstant(1, VT));
13726 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13727 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13728 unsigned X86CC = N->getConstantOperandVal(0);
13729 SDValue EFLAG = N->getOperand(1);
13730 DebugLoc DL = N->getDebugLoc();
13732 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13733 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13735 if (X86CC == X86::COND_B)
13736 return DAG.getNode(ISD::AND, DL, MVT::i8,
13737 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13738 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13739 DAG.getConstant(1, MVT::i8));
13744 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13745 const X86TargetLowering *XTLI) {
13746 SDValue Op0 = N->getOperand(0);
13747 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13748 // a 32-bit target where SSE doesn't support i64->FP operations.
13749 if (Op0.getOpcode() == ISD::LOAD) {
13750 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13751 EVT VT = Ld->getValueType(0);
13752 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13753 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13754 !XTLI->getSubtarget()->is64Bit() &&
13755 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13756 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13757 Ld->getChain(), Op0, DAG);
13758 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13765 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13766 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13767 X86TargetLowering::DAGCombinerInfo &DCI) {
13768 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13769 // the result is either zero or one (depending on the input carry bit).
13770 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13771 if (X86::isZeroNode(N->getOperand(0)) &&
13772 X86::isZeroNode(N->getOperand(1)) &&
13773 // We don't have a good way to replace an EFLAGS use, so only do this when
13775 SDValue(N, 1).use_empty()) {
13776 DebugLoc DL = N->getDebugLoc();
13777 EVT VT = N->getValueType(0);
13778 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13779 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13780 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13781 DAG.getConstant(X86::COND_B,MVT::i8),
13783 DAG.getConstant(1, VT));
13784 return DCI.CombineTo(N, Res1, CarryOut);
13790 // fold (add Y, (sete X, 0)) -> adc 0, Y
13791 // (add Y, (setne X, 0)) -> sbb -1, Y
13792 // (sub (sete X, 0), Y) -> sbb 0, Y
13793 // (sub (setne X, 0), Y) -> adc -1, Y
13794 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13795 DebugLoc DL = N->getDebugLoc();
13797 // Look through ZExts.
13798 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13799 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13802 SDValue SetCC = Ext.getOperand(0);
13803 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13806 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13807 if (CC != X86::COND_E && CC != X86::COND_NE)
13810 SDValue Cmp = SetCC.getOperand(1);
13811 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13812 !X86::isZeroNode(Cmp.getOperand(1)) ||
13813 !Cmp.getOperand(0).getValueType().isInteger())
13816 SDValue CmpOp0 = Cmp.getOperand(0);
13817 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13818 DAG.getConstant(1, CmpOp0.getValueType()));
13820 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13821 if (CC == X86::COND_NE)
13822 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13823 DL, OtherVal.getValueType(), OtherVal,
13824 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13825 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13826 DL, OtherVal.getValueType(), OtherVal,
13827 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13830 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13831 SDValue Op0 = N->getOperand(0);
13832 SDValue Op1 = N->getOperand(1);
13834 // X86 can't encode an immediate LHS of a sub. See if we can push the
13835 // negation into a preceding instruction.
13836 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13837 // If the RHS of the sub is a XOR with one use and a constant, invert the
13838 // immediate. Then add one to the LHS of the sub so we can turn
13839 // X-Y -> X+~Y+1, saving one register.
13840 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13841 isa<ConstantSDNode>(Op1.getOperand(1))) {
13842 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13843 EVT VT = Op0.getValueType();
13844 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13846 DAG.getConstant(~XorC, VT));
13847 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13848 DAG.getConstant(C->getAPIntValue()+1, VT));
13852 return OptimizeConditionalInDecrement(N, DAG);
13855 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13856 DAGCombinerInfo &DCI) const {
13857 SelectionDAG &DAG = DCI.DAG;
13858 switch (N->getOpcode()) {
13860 case ISD::EXTRACT_VECTOR_ELT:
13861 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13862 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13863 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13864 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13865 case ISD::SUB: return PerformSubCombine(N, DAG);
13866 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13867 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13870 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13871 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13872 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13873 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13874 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13876 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13877 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13878 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13879 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13880 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13881 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13882 case X86ISD::SHUFPS: // Handle all target specific shuffles
13883 case X86ISD::SHUFPD:
13884 case X86ISD::PALIGN:
13885 case X86ISD::PUNPCKHBW:
13886 case X86ISD::PUNPCKHWD:
13887 case X86ISD::PUNPCKHDQ:
13888 case X86ISD::PUNPCKHQDQ:
13889 case X86ISD::UNPCKHPS:
13890 case X86ISD::UNPCKHPD:
13891 case X86ISD::VUNPCKHPSY:
13892 case X86ISD::VUNPCKHPDY:
13893 case X86ISD::PUNPCKLBW:
13894 case X86ISD::PUNPCKLWD:
13895 case X86ISD::PUNPCKLDQ:
13896 case X86ISD::PUNPCKLQDQ:
13897 case X86ISD::UNPCKLPS:
13898 case X86ISD::UNPCKLPD:
13899 case X86ISD::VUNPCKLPSY:
13900 case X86ISD::VUNPCKLPDY:
13901 case X86ISD::MOVHLPS:
13902 case X86ISD::MOVLHPS:
13903 case X86ISD::PSHUFD:
13904 case X86ISD::PSHUFHW:
13905 case X86ISD::PSHUFLW:
13906 case X86ISD::MOVSS:
13907 case X86ISD::MOVSD:
13908 case X86ISD::VPERMILPS:
13909 case X86ISD::VPERMILPSY:
13910 case X86ISD::VPERMILPD:
13911 case X86ISD::VPERMILPDY:
13912 case X86ISD::VPERM2F128:
13913 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13919 /// isTypeDesirableForOp - Return true if the target has native support for
13920 /// the specified value type and it is 'desirable' to use the type for the
13921 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13922 /// instruction encodings are longer and some i16 instructions are slow.
13923 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13924 if (!isTypeLegal(VT))
13926 if (VT != MVT::i16)
13933 case ISD::SIGN_EXTEND:
13934 case ISD::ZERO_EXTEND:
13935 case ISD::ANY_EXTEND:
13948 /// IsDesirableToPromoteOp - This method query the target whether it is
13949 /// beneficial for dag combiner to promote the specified node. If true, it
13950 /// should return the desired promotion type by reference.
13951 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13952 EVT VT = Op.getValueType();
13953 if (VT != MVT::i16)
13956 bool Promote = false;
13957 bool Commute = false;
13958 switch (Op.getOpcode()) {
13961 LoadSDNode *LD = cast<LoadSDNode>(Op);
13962 // If the non-extending load has a single use and it's not live out, then it
13963 // might be folded.
13964 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13965 Op.hasOneUse()*/) {
13966 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13967 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13968 // The only case where we'd want to promote LOAD (rather then it being
13969 // promoted as an operand is when it's only use is liveout.
13970 if (UI->getOpcode() != ISD::CopyToReg)
13977 case ISD::SIGN_EXTEND:
13978 case ISD::ZERO_EXTEND:
13979 case ISD::ANY_EXTEND:
13984 SDValue N0 = Op.getOperand(0);
13985 // Look out for (store (shl (load), x)).
13986 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13999 SDValue N0 = Op.getOperand(0);
14000 SDValue N1 = Op.getOperand(1);
14001 if (!Commute && MayFoldLoad(N1))
14003 // Avoid disabling potential load folding opportunities.
14004 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14006 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14016 //===----------------------------------------------------------------------===//
14017 // X86 Inline Assembly Support
14018 //===----------------------------------------------------------------------===//
14020 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14021 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14023 std::string AsmStr = IA->getAsmString();
14025 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14026 SmallVector<StringRef, 4> AsmPieces;
14027 SplitString(AsmStr, AsmPieces, ";\n");
14029 switch (AsmPieces.size()) {
14030 default: return false;
14032 AsmStr = AsmPieces[0];
14034 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
14036 // FIXME: this should verify that we are targeting a 486 or better. If not,
14037 // we will turn this bswap into something that will be lowered to logical ops
14038 // instead of emitting the bswap asm. For now, we don't support 486 or lower
14039 // so don't worry about this.
14041 if (AsmPieces.size() == 2 &&
14042 (AsmPieces[0] == "bswap" ||
14043 AsmPieces[0] == "bswapq" ||
14044 AsmPieces[0] == "bswapl") &&
14045 (AsmPieces[1] == "$0" ||
14046 AsmPieces[1] == "${0:q}")) {
14047 // No need to check constraints, nothing other than the equivalent of
14048 // "=r,0" would be valid here.
14049 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14050 if (!Ty || Ty->getBitWidth() % 16 != 0)
14052 return IntrinsicLowering::LowerToByteSwap(CI);
14054 // rorw $$8, ${0:w} --> llvm.bswap.i16
14055 if (CI->getType()->isIntegerTy(16) &&
14056 AsmPieces.size() == 3 &&
14057 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
14058 AsmPieces[1] == "$$8," &&
14059 AsmPieces[2] == "${0:w}" &&
14060 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14062 const std::string &ConstraintsStr = IA->getConstraintString();
14063 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14064 std::sort(AsmPieces.begin(), AsmPieces.end());
14065 if (AsmPieces.size() == 4 &&
14066 AsmPieces[0] == "~{cc}" &&
14067 AsmPieces[1] == "~{dirflag}" &&
14068 AsmPieces[2] == "~{flags}" &&
14069 AsmPieces[3] == "~{fpsr}") {
14070 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14071 if (!Ty || Ty->getBitWidth() % 16 != 0)
14073 return IntrinsicLowering::LowerToByteSwap(CI);
14078 if (CI->getType()->isIntegerTy(32) &&
14079 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14080 SmallVector<StringRef, 4> Words;
14081 SplitString(AsmPieces[0], Words, " \t,");
14082 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14083 Words[2] == "${0:w}") {
14085 SplitString(AsmPieces[1], Words, " \t,");
14086 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
14087 Words[2] == "$0") {
14089 SplitString(AsmPieces[2], Words, " \t,");
14090 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14091 Words[2] == "${0:w}") {
14093 const std::string &ConstraintsStr = IA->getConstraintString();
14094 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14095 std::sort(AsmPieces.begin(), AsmPieces.end());
14096 if (AsmPieces.size() == 4 &&
14097 AsmPieces[0] == "~{cc}" &&
14098 AsmPieces[1] == "~{dirflag}" &&
14099 AsmPieces[2] == "~{flags}" &&
14100 AsmPieces[3] == "~{fpsr}") {
14101 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14102 if (!Ty || Ty->getBitWidth() % 16 != 0)
14104 return IntrinsicLowering::LowerToByteSwap(CI);
14111 if (CI->getType()->isIntegerTy(64)) {
14112 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14113 if (Constraints.size() >= 2 &&
14114 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14115 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14116 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14117 SmallVector<StringRef, 4> Words;
14118 SplitString(AsmPieces[0], Words, " \t");
14119 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
14121 SplitString(AsmPieces[1], Words, " \t");
14122 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
14124 SplitString(AsmPieces[2], Words, " \t,");
14125 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
14126 Words[2] == "%edx") {
14127 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14128 if (!Ty || Ty->getBitWidth() % 16 != 0)
14130 return IntrinsicLowering::LowerToByteSwap(CI);
14143 /// getConstraintType - Given a constraint letter, return the type of
14144 /// constraint it is for this target.
14145 X86TargetLowering::ConstraintType
14146 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14147 if (Constraint.size() == 1) {
14148 switch (Constraint[0]) {
14159 return C_RegisterClass;
14183 return TargetLowering::getConstraintType(Constraint);
14186 /// Examine constraint type and operand type and determine a weight value.
14187 /// This object must already have been set up with the operand type
14188 /// and the current alternative constraint selected.
14189 TargetLowering::ConstraintWeight
14190 X86TargetLowering::getSingleConstraintMatchWeight(
14191 AsmOperandInfo &info, const char *constraint) const {
14192 ConstraintWeight weight = CW_Invalid;
14193 Value *CallOperandVal = info.CallOperandVal;
14194 // If we don't have a value, we can't do a match,
14195 // but allow it at the lowest weight.
14196 if (CallOperandVal == NULL)
14198 Type *type = CallOperandVal->getType();
14199 // Look at the constraint type.
14200 switch (*constraint) {
14202 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14213 if (CallOperandVal->getType()->isIntegerTy())
14214 weight = CW_SpecificReg;
14219 if (type->isFloatingPointTy())
14220 weight = CW_SpecificReg;
14223 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14224 weight = CW_SpecificReg;
14228 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14229 weight = CW_Register;
14232 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14233 if (C->getZExtValue() <= 31)
14234 weight = CW_Constant;
14238 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14239 if (C->getZExtValue() <= 63)
14240 weight = CW_Constant;
14244 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14245 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14246 weight = CW_Constant;
14250 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14251 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14252 weight = CW_Constant;
14256 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14257 if (C->getZExtValue() <= 3)
14258 weight = CW_Constant;
14262 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14263 if (C->getZExtValue() <= 0xff)
14264 weight = CW_Constant;
14269 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14270 weight = CW_Constant;
14274 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14275 if ((C->getSExtValue() >= -0x80000000LL) &&
14276 (C->getSExtValue() <= 0x7fffffffLL))
14277 weight = CW_Constant;
14281 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14282 if (C->getZExtValue() <= 0xffffffff)
14283 weight = CW_Constant;
14290 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14291 /// with another that has more specific requirements based on the type of the
14292 /// corresponding operand.
14293 const char *X86TargetLowering::
14294 LowerXConstraint(EVT ConstraintVT) const {
14295 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14296 // 'f' like normal targets.
14297 if (ConstraintVT.isFloatingPoint()) {
14298 if (Subtarget->hasXMMInt())
14300 if (Subtarget->hasXMM())
14304 return TargetLowering::LowerXConstraint(ConstraintVT);
14307 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14308 /// vector. If it is invalid, don't add anything to Ops.
14309 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14310 std::string &Constraint,
14311 std::vector<SDValue>&Ops,
14312 SelectionDAG &DAG) const {
14313 SDValue Result(0, 0);
14315 // Only support length 1 constraints for now.
14316 if (Constraint.length() > 1) return;
14318 char ConstraintLetter = Constraint[0];
14319 switch (ConstraintLetter) {
14322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14323 if (C->getZExtValue() <= 31) {
14324 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14330 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14331 if (C->getZExtValue() <= 63) {
14332 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14339 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14340 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14346 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14347 if (C->getZExtValue() <= 255) {
14348 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14354 // 32-bit signed value
14355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14356 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14357 C->getSExtValue())) {
14358 // Widen to 64 bits here to get it sign extended.
14359 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14362 // FIXME gcc accepts some relocatable values here too, but only in certain
14363 // memory models; it's complicated.
14368 // 32-bit unsigned value
14369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14370 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14371 C->getZExtValue())) {
14372 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14376 // FIXME gcc accepts some relocatable values here too, but only in certain
14377 // memory models; it's complicated.
14381 // Literal immediates are always ok.
14382 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14383 // Widen to 64 bits here to get it sign extended.
14384 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14388 // In any sort of PIC mode addresses need to be computed at runtime by
14389 // adding in a register or some sort of table lookup. These can't
14390 // be used as immediates.
14391 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14394 // If we are in non-pic codegen mode, we allow the address of a global (with
14395 // an optional displacement) to be used with 'i'.
14396 GlobalAddressSDNode *GA = 0;
14397 int64_t Offset = 0;
14399 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14401 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14402 Offset += GA->getOffset();
14404 } else if (Op.getOpcode() == ISD::ADD) {
14405 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14406 Offset += C->getZExtValue();
14407 Op = Op.getOperand(0);
14410 } else if (Op.getOpcode() == ISD::SUB) {
14411 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14412 Offset += -C->getZExtValue();
14413 Op = Op.getOperand(0);
14418 // Otherwise, this isn't something we can handle, reject it.
14422 const GlobalValue *GV = GA->getGlobal();
14423 // If we require an extra load to get this address, as in PIC mode, we
14424 // can't accept it.
14425 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14426 getTargetMachine())))
14429 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14430 GA->getValueType(0), Offset);
14435 if (Result.getNode()) {
14436 Ops.push_back(Result);
14439 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14442 std::pair<unsigned, const TargetRegisterClass*>
14443 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14445 // First, see if this is a constraint that directly corresponds to an LLVM
14447 if (Constraint.size() == 1) {
14448 // GCC Constraint Letters
14449 switch (Constraint[0]) {
14451 // TODO: Slight differences here in allocation order and leaving
14452 // RIP in the class. Do they matter any more here than they do
14453 // in the normal allocation?
14454 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14455 if (Subtarget->is64Bit()) {
14456 if (VT == MVT::i32 || VT == MVT::f32)
14457 return std::make_pair(0U, X86::GR32RegisterClass);
14458 else if (VT == MVT::i16)
14459 return std::make_pair(0U, X86::GR16RegisterClass);
14460 else if (VT == MVT::i8 || VT == MVT::i1)
14461 return std::make_pair(0U, X86::GR8RegisterClass);
14462 else if (VT == MVT::i64 || VT == MVT::f64)
14463 return std::make_pair(0U, X86::GR64RegisterClass);
14466 // 32-bit fallthrough
14467 case 'Q': // Q_REGS
14468 if (VT == MVT::i32 || VT == MVT::f32)
14469 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14470 else if (VT == MVT::i16)
14471 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14472 else if (VT == MVT::i8 || VT == MVT::i1)
14473 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14474 else if (VT == MVT::i64)
14475 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14477 case 'r': // GENERAL_REGS
14478 case 'l': // INDEX_REGS
14479 if (VT == MVT::i8 || VT == MVT::i1)
14480 return std::make_pair(0U, X86::GR8RegisterClass);
14481 if (VT == MVT::i16)
14482 return std::make_pair(0U, X86::GR16RegisterClass);
14483 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14484 return std::make_pair(0U, X86::GR32RegisterClass);
14485 return std::make_pair(0U, X86::GR64RegisterClass);
14486 case 'R': // LEGACY_REGS
14487 if (VT == MVT::i8 || VT == MVT::i1)
14488 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14489 if (VT == MVT::i16)
14490 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14491 if (VT == MVT::i32 || !Subtarget->is64Bit())
14492 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14493 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14494 case 'f': // FP Stack registers.
14495 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14496 // value to the correct fpstack register class.
14497 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14498 return std::make_pair(0U, X86::RFP32RegisterClass);
14499 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14500 return std::make_pair(0U, X86::RFP64RegisterClass);
14501 return std::make_pair(0U, X86::RFP80RegisterClass);
14502 case 'y': // MMX_REGS if MMX allowed.
14503 if (!Subtarget->hasMMX()) break;
14504 return std::make_pair(0U, X86::VR64RegisterClass);
14505 case 'Y': // SSE_REGS if SSE2 allowed
14506 if (!Subtarget->hasXMMInt()) break;
14508 case 'x': // SSE_REGS if SSE1 allowed
14509 if (!Subtarget->hasXMM()) break;
14511 switch (VT.getSimpleVT().SimpleTy) {
14513 // Scalar SSE types.
14516 return std::make_pair(0U, X86::FR32RegisterClass);
14519 return std::make_pair(0U, X86::FR64RegisterClass);
14527 return std::make_pair(0U, X86::VR128RegisterClass);
14533 // Use the default implementation in TargetLowering to convert the register
14534 // constraint into a member of a register class.
14535 std::pair<unsigned, const TargetRegisterClass*> Res;
14536 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14538 // Not found as a standard register?
14539 if (Res.second == 0) {
14540 // Map st(0) -> st(7) -> ST0
14541 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14542 tolower(Constraint[1]) == 's' &&
14543 tolower(Constraint[2]) == 't' &&
14544 Constraint[3] == '(' &&
14545 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14546 Constraint[5] == ')' &&
14547 Constraint[6] == '}') {
14549 Res.first = X86::ST0+Constraint[4]-'0';
14550 Res.second = X86::RFP80RegisterClass;
14554 // GCC allows "st(0)" to be called just plain "st".
14555 if (StringRef("{st}").equals_lower(Constraint)) {
14556 Res.first = X86::ST0;
14557 Res.second = X86::RFP80RegisterClass;
14562 if (StringRef("{flags}").equals_lower(Constraint)) {
14563 Res.first = X86::EFLAGS;
14564 Res.second = X86::CCRRegisterClass;
14568 // 'A' means EAX + EDX.
14569 if (Constraint == "A") {
14570 Res.first = X86::EAX;
14571 Res.second = X86::GR32_ADRegisterClass;
14577 // Otherwise, check to see if this is a register class of the wrong value
14578 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14579 // turn into {ax},{dx}.
14580 if (Res.second->hasType(VT))
14581 return Res; // Correct type already, nothing to do.
14583 // All of the single-register GCC register classes map their values onto
14584 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14585 // really want an 8-bit or 32-bit register, map to the appropriate register
14586 // class and return the appropriate register.
14587 if (Res.second == X86::GR16RegisterClass) {
14588 if (VT == MVT::i8) {
14589 unsigned DestReg = 0;
14590 switch (Res.first) {
14592 case X86::AX: DestReg = X86::AL; break;
14593 case X86::DX: DestReg = X86::DL; break;
14594 case X86::CX: DestReg = X86::CL; break;
14595 case X86::BX: DestReg = X86::BL; break;
14598 Res.first = DestReg;
14599 Res.second = X86::GR8RegisterClass;
14601 } else if (VT == MVT::i32) {
14602 unsigned DestReg = 0;
14603 switch (Res.first) {
14605 case X86::AX: DestReg = X86::EAX; break;
14606 case X86::DX: DestReg = X86::EDX; break;
14607 case X86::CX: DestReg = X86::ECX; break;
14608 case X86::BX: DestReg = X86::EBX; break;
14609 case X86::SI: DestReg = X86::ESI; break;
14610 case X86::DI: DestReg = X86::EDI; break;
14611 case X86::BP: DestReg = X86::EBP; break;
14612 case X86::SP: DestReg = X86::ESP; break;
14615 Res.first = DestReg;
14616 Res.second = X86::GR32RegisterClass;
14618 } else if (VT == MVT::i64) {
14619 unsigned DestReg = 0;
14620 switch (Res.first) {
14622 case X86::AX: DestReg = X86::RAX; break;
14623 case X86::DX: DestReg = X86::RDX; break;
14624 case X86::CX: DestReg = X86::RCX; break;
14625 case X86::BX: DestReg = X86::RBX; break;
14626 case X86::SI: DestReg = X86::RSI; break;
14627 case X86::DI: DestReg = X86::RDI; break;
14628 case X86::BP: DestReg = X86::RBP; break;
14629 case X86::SP: DestReg = X86::RSP; break;
14632 Res.first = DestReg;
14633 Res.second = X86::GR64RegisterClass;
14636 } else if (Res.second == X86::FR32RegisterClass ||
14637 Res.second == X86::FR64RegisterClass ||
14638 Res.second == X86::VR128RegisterClass) {
14639 // Handle references to XMM physical registers that got mapped into the
14640 // wrong class. This can happen with constraints like {xmm0} where the
14641 // target independent register mapper will just pick the first match it can
14642 // find, ignoring the required type.
14643 if (VT == MVT::f32)
14644 Res.second = X86::FR32RegisterClass;
14645 else if (VT == MVT::f64)
14646 Res.second = X86::FR64RegisterClass;
14647 else if (X86::VR128RegisterClass->hasType(VT))
14648 Res.second = X86::VR128RegisterClass;