1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<bool> ExperimentalVectorShuffleLegality(
75 "x86-experimental-vector-shuffle-legality", cl::init(false),
76 cl::desc("Enable experimental shuffle legality based on the experimental "
77 "shuffle lowering. Should only be used with the experimental "
81 static cl::opt<int> ReciprocalEstimateRefinementSteps(
82 "x86-recip-refinement-steps", cl::init(1),
83 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
84 "result of the hardware reciprocal estimate instruction."),
87 // Forward declarations.
88 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
91 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
92 SelectionDAG &DAG, SDLoc dl,
93 unsigned vectorWidth) {
94 assert((vectorWidth == 128 || vectorWidth == 256) &&
95 "Unsupported vector width");
96 EVT VT = Vec.getValueType();
97 EVT ElVT = VT.getVectorElementType();
98 unsigned Factor = VT.getSizeInBits()/vectorWidth;
99 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
100 VT.getVectorNumElements()/Factor);
102 // Extract from UNDEF is UNDEF.
103 if (Vec.getOpcode() == ISD::UNDEF)
104 return DAG.getUNDEF(ResultVT);
106 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
107 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
109 // This is the index of the first element of the vectorWidth-bit chunk
111 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
114 // If the input is a buildvector just emit a smaller one.
115 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
116 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
117 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
120 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
121 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
124 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
125 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
126 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
127 /// instructions or a simple subregister reference. Idx is an index in the
128 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
129 /// lowering EXTRACT_VECTOR_ELT operations easier.
130 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
131 SelectionDAG &DAG, SDLoc dl) {
132 assert((Vec.getValueType().is256BitVector() ||
133 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
137 /// Generate a DAG to grab 256-bits from a 512-bit vector.
138 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
139 SelectionDAG &DAG, SDLoc dl) {
140 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
141 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
144 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
145 unsigned IdxVal, SelectionDAG &DAG,
146 SDLoc dl, unsigned vectorWidth) {
147 assert((vectorWidth == 128 || vectorWidth == 256) &&
148 "Unsupported vector width");
149 // Inserting UNDEF is Result
150 if (Vec.getOpcode() == ISD::UNDEF)
152 EVT VT = Vec.getValueType();
153 EVT ElVT = VT.getVectorElementType();
154 EVT ResultVT = Result.getValueType();
156 // Insert the relevant vectorWidth bits.
157 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
159 // This is the index of the first element of the vectorWidth-bit chunk
161 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
164 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
165 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
168 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
169 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
170 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
171 /// simple superregister reference. Idx is an index in the 128 bits
172 /// we want. It need not be aligned to a 128-bit boundary. That makes
173 /// lowering INSERT_VECTOR_ELT operations easier.
174 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
175 SelectionDAG &DAG,SDLoc dl) {
176 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
177 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
180 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
181 SelectionDAG &DAG, SDLoc dl) {
182 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
183 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
186 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
187 /// instructions. This is used because creating CONCAT_VECTOR nodes of
188 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
189 /// large BUILD_VECTORS.
190 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
197 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
198 unsigned NumElems, SelectionDAG &DAG,
200 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
201 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
204 // FIXME: This should stop caching the target machine as soon as
205 // we can remove resetOperationActions et al.
206 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
207 : TargetLowering(TM) {
208 Subtarget = &TM.getSubtarget<X86Subtarget>();
209 X86ScalarSSEf64 = Subtarget->hasSSE2();
210 X86ScalarSSEf32 = Subtarget->hasSSE1();
211 TD = getDataLayout();
213 resetOperationActions();
216 void X86TargetLowering::resetOperationActions() {
217 const TargetMachine &TM = getTargetMachine();
218 static bool FirstTimeThrough = true;
220 // If none of the target options have changed, then we don't need to reset the
221 // operation actions.
222 if (!FirstTimeThrough && TO == TM.Options) return;
224 if (!FirstTimeThrough) {
225 // Reinitialize the actions.
227 FirstTimeThrough = false;
232 // Set up the TargetLowering object.
233 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
235 // X86 is weird. It always uses i8 for shift amounts and setcc results.
236 setBooleanContents(ZeroOrOneBooleanContent);
237 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
238 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
240 // For 64-bit, since we have so many registers, use the ILP scheduler.
241 // For 32-bit, use the register pressure specific scheduling.
242 // For Atom, always use ILP scheduling.
243 if (Subtarget->isAtom())
244 setSchedulingPreference(Sched::ILP);
245 else if (Subtarget->is64Bit())
246 setSchedulingPreference(Sched::ILP);
248 setSchedulingPreference(Sched::RegPressure);
249 const X86RegisterInfo *RegInfo =
250 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
251 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
253 // Bypass expensive divides on Atom when compiling with O2.
254 if (TM.getOptLevel() >= CodeGenOpt::Default) {
255 if (Subtarget->hasSlowDivide32())
256 addBypassSlowDiv(32, 8);
257 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
258 addBypassSlowDiv(64, 16);
261 if (Subtarget->isTargetKnownWindowsMSVC()) {
262 // Setup Windows compiler runtime calls.
263 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
264 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
265 setLibcallName(RTLIB::SREM_I64, "_allrem");
266 setLibcallName(RTLIB::UREM_I64, "_aullrem");
267 setLibcallName(RTLIB::MUL_I64, "_allmul");
268 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
271 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
272 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
274 // The _ftol2 runtime function has an unusual calling conv, which
275 // is modeled by a special pseudo-instruction.
276 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
278 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
279 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
282 if (Subtarget->isTargetDarwin()) {
283 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
284 setUseUnderscoreSetJmp(false);
285 setUseUnderscoreLongJmp(false);
286 } else if (Subtarget->isTargetWindowsGNU()) {
287 // MS runtime is weird: it exports _setjmp, but longjmp!
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(false);
291 setUseUnderscoreSetJmp(true);
292 setUseUnderscoreLongJmp(true);
295 // Set up the register classes.
296 addRegisterClass(MVT::i8, &X86::GR8RegClass);
297 addRegisterClass(MVT::i16, &X86::GR16RegClass);
298 addRegisterClass(MVT::i32, &X86::GR32RegClass);
299 if (Subtarget->is64Bit())
300 addRegisterClass(MVT::i64, &X86::GR64RegClass);
302 for (MVT VT : MVT::integer_valuetypes())
303 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
305 // We don't accept any truncstore of integer registers.
306 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
307 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
308 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
309 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
310 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
311 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 // SETOEQ and SETUNE require checking two conditions.
316 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
319 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
320 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
321 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
323 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
325 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
329 if (Subtarget->is64Bit()) {
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 } else if (!TM.Options.UseSoftFloat) {
333 // We have an algorithm for SSE2->double, and we turn this into a
334 // 64-bit FILD followed by conditional FADD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 // We have an algorithm for SSE2, and we turn this into a 64-bit
337 // FILD for other targets.
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
341 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
343 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
346 if (!TM.Options.UseSoftFloat) {
347 // SSE has no i16 to fp conversion, only i32
348 if (X86ScalarSSEf32) {
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 // f32 and f64 cases are Legal, f80 case is not
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
361 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
362 // are Legal, f80 is custom lowered.
363 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
364 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
366 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
368 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
371 if (X86ScalarSSEf32) {
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
373 // f32 and f64 cases are Legal, f80 case is not
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 // Handle FP_TO_UINT by promoting the destination to a larger signed
382 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
386 if (Subtarget->is64Bit()) {
387 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
389 } else if (!TM.Options.UseSoftFloat) {
390 // Since AVX is a superset of SSE3, only check for SSE here.
391 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
392 // Expand FP_TO_UINT into a select.
393 // FIXME: We would like to use a Custom expander here eventually to do
394 // the optimal thing for SSE vs. the default expansion in the legalizer.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
397 // With SSE3 we can use fisttpll to convert to a signed i64; without
398 // SSE, we're stuck with a fistpll.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
402 if (isTargetFTOL()) {
403 // Use the _ftol2 runtime function, which has a pseudo-instruction
404 // to handle its weird calling convention.
405 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
408 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
409 if (!X86ScalarSSEf64) {
410 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
411 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
412 if (Subtarget->is64Bit()) {
413 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
414 // Without SSE, i64->f64 goes through memory.
415 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
419 // Scalar integer divide and remainder are lowered to use operations that
420 // produce two results, to match the available instructions. This exposes
421 // the two-result form to trivial CSE, which is able to combine x/y and x%y
422 // into a single instruction.
424 // Scalar integer multiply-high is also lowered to use two-result
425 // operations, to match the available instructions. However, plain multiply
426 // (low) operations are left as Legal, as there are single-result
427 // instructions for this in x86. Using the two-result multiply instructions
428 // when both high and low results are needed must be arranged by dagcombine.
429 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
431 setOperationAction(ISD::MULHS, VT, Expand);
432 setOperationAction(ISD::MULHU, VT, Expand);
433 setOperationAction(ISD::SDIV, VT, Expand);
434 setOperationAction(ISD::UDIV, VT, Expand);
435 setOperationAction(ISD::SREM, VT, Expand);
436 setOperationAction(ISD::UREM, VT, Expand);
438 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
439 setOperationAction(ISD::ADDC, VT, Custom);
440 setOperationAction(ISD::ADDE, VT, Custom);
441 setOperationAction(ISD::SUBC, VT, Custom);
442 setOperationAction(ISD::SUBE, VT, Custom);
445 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
446 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
447 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
449 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
451 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
452 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
453 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
463 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
466 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
467 setOperationAction(ISD::FREM , MVT::f32 , Expand);
468 setOperationAction(ISD::FREM , MVT::f64 , Expand);
469 setOperationAction(ISD::FREM , MVT::f80 , Expand);
470 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
472 // Promote the i8 variants and force them on up to i32 which has a shorter
474 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
478 if (Subtarget->hasBMI()) {
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
486 if (Subtarget->is64Bit())
487 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
490 if (Subtarget->hasLZCNT()) {
491 // When promoting the i8 variants, force them to i32 for a shorter
493 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
494 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
496 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
499 if (Subtarget->is64Bit())
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
502 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
508 if (Subtarget->is64Bit()) {
509 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
514 // Special handling for half-precision floating point conversions.
515 // If we don't have F16C support, then lower half float conversions
516 // into library calls.
517 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
518 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
519 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
522 // There's never any support for operations beyond MVT::f32.
523 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
524 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
525 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
526 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
528 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
529 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
530 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
531 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
532 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
535 if (Subtarget->hasPOPCNT()) {
536 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
538 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
539 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
540 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
541 if (Subtarget->is64Bit())
542 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
545 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
547 if (!Subtarget->hasMOVBE())
548 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
550 // These should be promoted to a larger select which is supported.
551 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
552 // X86 wants to expand cmov itself.
553 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
554 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
555 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
556 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
557 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
559 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
562 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
563 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
565 if (Subtarget->is64Bit()) {
566 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
569 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
570 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
571 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
572 // support continuation, user-level threading, and etc.. As a result, no
573 // other SjLj exception interfaces are implemented and please don't build
574 // your own exception handling based on them.
575 // LLVM/Clang supports zero-cost DWARF exception handling.
576 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
577 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
580 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
583 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
584 if (Subtarget->is64Bit())
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
586 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
588 if (Subtarget->is64Bit()) {
589 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
590 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
591 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
592 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
595 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
596 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
597 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
598 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
599 if (Subtarget->is64Bit()) {
600 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
601 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
602 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
605 if (Subtarget->hasSSE1())
606 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
608 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
610 // Expand certain atomics
611 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
614 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
615 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
618 if (Subtarget->hasCmpxchg16b()) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
622 // FIXME - use subtarget debug flags
623 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
624 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
625 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
628 if (Subtarget->is64Bit()) {
629 setExceptionPointerRegister(X86::RAX);
630 setExceptionSelectorRegister(X86::RDX);
632 setExceptionPointerRegister(X86::EAX);
633 setExceptionSelectorRegister(X86::EDX);
635 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
636 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
638 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
639 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::TRAP, MVT::Other, Legal);
642 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
644 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
645 setOperationAction(ISD::VASTART , MVT::Other, Custom);
646 setOperationAction(ISD::VAEND , MVT::Other, Expand);
647 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
648 // TargetInfo::X86_64ABIBuiltinVaList
649 setOperationAction(ISD::VAARG , MVT::Other, Custom);
650 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
652 // TargetInfo::CharPtrBuiltinVaList
653 setOperationAction(ISD::VAARG , MVT::Other, Expand);
654 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
657 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
658 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
660 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
662 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
663 // f32 and f64 use SSE.
664 // Set up the FP register classes.
665 addRegisterClass(MVT::f32, &X86::FR32RegClass);
666 addRegisterClass(MVT::f64, &X86::FR64RegClass);
668 // Use ANDPD to simulate FABS.
669 setOperationAction(ISD::FABS , MVT::f64, Custom);
670 setOperationAction(ISD::FABS , MVT::f32, Custom);
672 // Use XORP to simulate FNEG.
673 setOperationAction(ISD::FNEG , MVT::f64, Custom);
674 setOperationAction(ISD::FNEG , MVT::f32, Custom);
676 // Use ANDPD and ORPD to simulate FCOPYSIGN.
677 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
678 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
680 // Lower this to FGETSIGNx86 plus an AND.
681 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
682 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
684 // We don't support sin/cos/fmod
685 setOperationAction(ISD::FSIN , MVT::f64, Expand);
686 setOperationAction(ISD::FCOS , MVT::f64, Expand);
687 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
688 setOperationAction(ISD::FSIN , MVT::f32, Expand);
689 setOperationAction(ISD::FCOS , MVT::f32, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
692 // Expand FP immediates into loads from the stack, except for the special
694 addLegalFPImmediate(APFloat(+0.0)); // xorpd
695 addLegalFPImmediate(APFloat(+0.0f)); // xorps
696 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
697 // Use SSE for f32, x87 for f64.
698 // Set up the FP register classes.
699 addRegisterClass(MVT::f32, &X86::FR32RegClass);
700 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
702 // Use ANDPS to simulate FABS.
703 setOperationAction(ISD::FABS , MVT::f32, Custom);
705 // Use XORP to simulate FNEG.
706 setOperationAction(ISD::FNEG , MVT::f32, Custom);
708 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
710 // Use ANDPS and ORPS to simulate FCOPYSIGN.
711 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
712 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
714 // We don't support sin/cos/fmod
715 setOperationAction(ISD::FSIN , MVT::f32, Expand);
716 setOperationAction(ISD::FCOS , MVT::f32, Expand);
717 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
719 // Special cases we handle for FP constants.
720 addLegalFPImmediate(APFloat(+0.0f)); // xorps
721 addLegalFPImmediate(APFloat(+0.0)); // FLD0
722 addLegalFPImmediate(APFloat(+1.0)); // FLD1
723 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
724 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 } else if (!TM.Options.UseSoftFloat) {
732 // f32 and f64 in x87.
733 // Set up the FP register classes.
734 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
735 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
737 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
738 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
739 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
740 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
742 if (!TM.Options.UnsafeFPMath) {
743 setOperationAction(ISD::FSIN , MVT::f64, Expand);
744 setOperationAction(ISD::FSIN , MVT::f32, Expand);
745 setOperationAction(ISD::FCOS , MVT::f64, Expand);
746 setOperationAction(ISD::FCOS , MVT::f32, Expand);
747 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
748 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
750 addLegalFPImmediate(APFloat(+0.0)); // FLD0
751 addLegalFPImmediate(APFloat(+1.0)); // FLD1
752 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
753 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
754 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
755 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
756 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
757 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
760 // We don't support FMA.
761 setOperationAction(ISD::FMA, MVT::f64, Expand);
762 setOperationAction(ISD::FMA, MVT::f32, Expand);
764 // Long double always uses X87.
765 if (!TM.Options.UseSoftFloat) {
766 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
767 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
768 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
770 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
771 addLegalFPImmediate(TmpFlt); // FLD0
773 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
776 APFloat TmpFlt2(+1.0);
777 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
779 addLegalFPImmediate(TmpFlt2); // FLD1
780 TmpFlt2.changeSign();
781 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
784 if (!TM.Options.UnsafeFPMath) {
785 setOperationAction(ISD::FSIN , MVT::f80, Expand);
786 setOperationAction(ISD::FCOS , MVT::f80, Expand);
787 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
790 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
791 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
792 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
793 setOperationAction(ISD::FRINT, MVT::f80, Expand);
794 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
795 setOperationAction(ISD::FMA, MVT::f80, Expand);
798 // Always use a library call for pow.
799 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
800 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
801 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
803 setOperationAction(ISD::FLOG, MVT::f80, Expand);
804 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
805 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
806 setOperationAction(ISD::FEXP, MVT::f80, Expand);
807 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
808 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
809 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (MVT VT : MVT::vector_valuetypes()) {
815 setOperationAction(ISD::ADD , VT, Expand);
816 setOperationAction(ISD::SUB , VT, Expand);
817 setOperationAction(ISD::FADD, VT, Expand);
818 setOperationAction(ISD::FNEG, VT, Expand);
819 setOperationAction(ISD::FSUB, VT, Expand);
820 setOperationAction(ISD::MUL , VT, Expand);
821 setOperationAction(ISD::FMUL, VT, Expand);
822 setOperationAction(ISD::SDIV, VT, Expand);
823 setOperationAction(ISD::UDIV, VT, Expand);
824 setOperationAction(ISD::FDIV, VT, Expand);
825 setOperationAction(ISD::SREM, VT, Expand);
826 setOperationAction(ISD::UREM, VT, Expand);
827 setOperationAction(ISD::LOAD, VT, Expand);
828 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
830 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
831 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
832 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
833 setOperationAction(ISD::FABS, VT, Expand);
834 setOperationAction(ISD::FSIN, VT, Expand);
835 setOperationAction(ISD::FSINCOS, VT, Expand);
836 setOperationAction(ISD::FCOS, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FREM, VT, Expand);
839 setOperationAction(ISD::FMA, VT, Expand);
840 setOperationAction(ISD::FPOWI, VT, Expand);
841 setOperationAction(ISD::FSQRT, VT, Expand);
842 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
843 setOperationAction(ISD::FFLOOR, VT, Expand);
844 setOperationAction(ISD::FCEIL, VT, Expand);
845 setOperationAction(ISD::FTRUNC, VT, Expand);
846 setOperationAction(ISD::FRINT, VT, Expand);
847 setOperationAction(ISD::FNEARBYINT, VT, Expand);
848 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
849 setOperationAction(ISD::MULHS, VT, Expand);
850 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHU, VT, Expand);
852 setOperationAction(ISD::SDIVREM, VT, Expand);
853 setOperationAction(ISD::UDIVREM, VT, Expand);
854 setOperationAction(ISD::FPOW, VT, Expand);
855 setOperationAction(ISD::CTPOP, VT, Expand);
856 setOperationAction(ISD::CTTZ, VT, Expand);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
858 setOperationAction(ISD::CTLZ, VT, Expand);
859 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::SHL, VT, Expand);
861 setOperationAction(ISD::SRA, VT, Expand);
862 setOperationAction(ISD::SRL, VT, Expand);
863 setOperationAction(ISD::ROTL, VT, Expand);
864 setOperationAction(ISD::ROTR, VT, Expand);
865 setOperationAction(ISD::BSWAP, VT, Expand);
866 setOperationAction(ISD::SETCC, VT, Expand);
867 setOperationAction(ISD::FLOG, VT, Expand);
868 setOperationAction(ISD::FLOG2, VT, Expand);
869 setOperationAction(ISD::FLOG10, VT, Expand);
870 setOperationAction(ISD::FEXP, VT, Expand);
871 setOperationAction(ISD::FEXP2, VT, Expand);
872 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
873 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
874 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
875 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
876 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
877 setOperationAction(ISD::TRUNCATE, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
879 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
880 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
881 setOperationAction(ISD::VSELECT, VT, Expand);
882 setOperationAction(ISD::SELECT_CC, VT, Expand);
883 for (MVT InnerVT : MVT::vector_valuetypes()) {
884 setTruncStoreAction(InnerVT, VT, Expand);
886 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
887 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
889 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
890 // types, we have to deal with them whether we ask for Expansion or not.
891 // Setting Expand causes its own optimisation problems though, so leave
893 if (VT.getVectorElementType() == MVT::i1)
894 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
898 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
899 // with -msoft-float, disable use of MMX as well.
900 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
901 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
902 // No operations on x86mmx supported, everything uses intrinsics.
905 // MMX-sized vectors (other than x86mmx) are expected to be expanded
906 // into smaller operations.
907 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
908 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
909 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
910 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
911 setOperationAction(ISD::AND, MVT::v8i8, Expand);
912 setOperationAction(ISD::AND, MVT::v4i16, Expand);
913 setOperationAction(ISD::AND, MVT::v2i32, Expand);
914 setOperationAction(ISD::AND, MVT::v1i64, Expand);
915 setOperationAction(ISD::OR, MVT::v8i8, Expand);
916 setOperationAction(ISD::OR, MVT::v4i16, Expand);
917 setOperationAction(ISD::OR, MVT::v2i32, Expand);
918 setOperationAction(ISD::OR, MVT::v1i64, Expand);
919 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
927 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
928 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
929 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
930 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
931 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
932 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
937 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
938 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
940 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
941 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
942 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
943 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
944 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
945 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
946 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
947 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
948 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
949 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
951 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
952 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Only provide customized ctpop vector bit twiddling for vector types we
1000 // know to perform better than using the popcnt instructions on each vector
1001 // element. If popcnt isn't supported, always provide the custom version.
1002 if (!Subtarget->hasPOPCNT()) {
1003 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
1004 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
1007 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1008 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1009 MVT VT = (MVT::SimpleValueType)i;
1010 // Do not attempt to custom lower non-power-of-2 vectors
1011 if (!isPowerOf2_32(VT.getVectorNumElements()))
1013 // Do not attempt to custom lower non-128-bit vectors
1014 if (!VT.is128BitVector())
1016 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1017 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1021 // We support custom legalizing of sext and anyext loads for specific
1022 // memory vector types which we can load as a scalar (or sequence of
1023 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1024 // loads these must work with a single scalar load.
1025 for (MVT VT : MVT::integer_vector_valuetypes()) {
1026 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
1027 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
1028 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
1030 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1032 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1033 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1037 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1038 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1039 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1040 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1044 if (Subtarget->is64Bit()) {
1045 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1046 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1049 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1050 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1051 MVT VT = (MVT::SimpleValueType)i;
1053 // Do not attempt to promote non-128-bit vectors
1054 if (!VT.is128BitVector())
1057 setOperationAction(ISD::AND, VT, Promote);
1058 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1059 setOperationAction(ISD::OR, VT, Promote);
1060 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1061 setOperationAction(ISD::XOR, VT, Promote);
1062 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1063 setOperationAction(ISD::LOAD, VT, Promote);
1064 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1065 setOperationAction(ISD::SELECT, VT, Promote);
1066 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1069 // Custom lower v2i64 and v2f64 selects.
1070 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1071 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1072 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1073 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1075 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1076 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1078 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1079 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1080 // As there is no 64-bit GPR available, we need build a special custom
1081 // sequence to convert from v2i32 to v2f32.
1082 if (!Subtarget->is64Bit())
1083 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1085 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1086 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1088 for (MVT VT : MVT::fp_vector_valuetypes())
1089 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1091 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1092 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1093 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1096 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1097 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1100 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1102 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1103 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1104 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1105 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1106 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1108 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1109 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1110 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1111 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1112 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1113 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1114 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1115 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1116 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1119 // FIXME: Do we need to handle scalar-to-vector here?
1120 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1122 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1123 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1124 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1125 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1127 // There is no BLENDI for byte vectors. We don't need to custom lower
1128 // some vselects for now.
1129 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1131 // SSE41 brings specific instructions for doing vector sign extend even in
1132 // cases where we don't have SRA.
1133 for (MVT VT : MVT::integer_vector_valuetypes()) {
1134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1139 // i8 and i16 vectors are custom because the source register and source
1140 // source memory operand types are not the same width. f32 vectors are
1141 // custom since the immediate controlling the insert encodes additional
1143 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1144 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1145 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1153 // FIXME: these should be Legal, but that's only for the case where
1154 // the index is constant. For now custom expand to deal with that.
1155 if (Subtarget->is64Bit()) {
1156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1157 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1161 if (Subtarget->hasSSE2()) {
1162 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1163 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1165 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1166 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1168 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1169 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1171 // In the customized shift lowering, the legal cases in AVX2 will be
1173 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1174 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1176 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1177 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1179 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1182 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1183 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1184 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1185 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1186 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1187 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1188 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1190 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1191 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1192 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1194 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1197 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1198 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1199 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1200 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1201 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1202 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1204 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1205 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1207 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1210 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1211 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1212 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1213 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1214 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1215 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1216 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1217 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1218 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1220 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1221 // even though v8i16 is a legal type.
1222 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1223 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1224 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1226 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1227 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1228 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1230 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1231 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1233 for (MVT VT : MVT::fp_vector_valuetypes())
1234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1236 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1240 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1242 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1243 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1245 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1246 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1247 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1251 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1254 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1255 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1256 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1257 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1259 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1260 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1261 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1262 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1263 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1264 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1265 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1266 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1267 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1268 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1269 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1270 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1272 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1273 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1274 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1275 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1276 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1277 setOperationAction(ISD::FMA, MVT::f32, Legal);
1278 setOperationAction(ISD::FMA, MVT::f64, Legal);
1281 if (Subtarget->hasInt256()) {
1282 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1283 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1284 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1285 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1287 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1288 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1289 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1290 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1292 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1293 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1294 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1295 // Don't lower v32i8 because there is no 128-bit byte mul
1297 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1299 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1300 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1302 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1303 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1305 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1306 // when we have a 256bit-wide blend with immediate.
1307 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1309 // Only provide customized ctpop vector bit twiddling for vector types we
1310 // know to perform better than using the popcnt instructions on each
1311 // vector element. If popcnt isn't supported, always provide the custom
1313 if (!Subtarget->hasPOPCNT())
1314 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1316 // Custom CTPOP always performs better on natively supported v8i32
1317 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1319 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1320 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1321 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1322 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1324 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1325 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1326 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1327 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1329 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1330 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1331 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1332 // Don't lower v32i8 because there is no 128-bit byte mul
1335 // In the customized shift lowering, the legal cases in AVX2 will be
1337 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1338 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1340 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1341 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1343 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1345 // Custom lower several nodes for 256-bit types.
1346 for (MVT VT : MVT::vector_valuetypes()) {
1347 if (VT.getScalarSizeInBits() >= 32) {
1348 setOperationAction(ISD::MLOAD, VT, Legal);
1349 setOperationAction(ISD::MSTORE, VT, Legal);
1351 // Extract subvector is special because the value type
1352 // (result) is 128-bit but the source is 256-bit wide.
1353 if (VT.is128BitVector()) {
1354 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1356 // Do not attempt to custom lower other non-256-bit vectors
1357 if (!VT.is256BitVector())
1360 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1361 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1362 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1363 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1364 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1365 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1366 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1369 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1370 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1371 MVT VT = (MVT::SimpleValueType)i;
1373 // Do not attempt to promote non-256-bit vectors
1374 if (!VT.is256BitVector())
1377 setOperationAction(ISD::AND, VT, Promote);
1378 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1379 setOperationAction(ISD::OR, VT, Promote);
1380 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1381 setOperationAction(ISD::XOR, VT, Promote);
1382 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1383 setOperationAction(ISD::LOAD, VT, Promote);
1384 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1385 setOperationAction(ISD::SELECT, VT, Promote);
1386 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1390 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1391 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1392 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1393 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1394 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1396 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1397 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1398 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1400 for (MVT VT : MVT::fp_vector_valuetypes())
1401 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1403 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1404 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1405 setOperationAction(ISD::XOR, MVT::i1, Legal);
1406 setOperationAction(ISD::OR, MVT::i1, Legal);
1407 setOperationAction(ISD::AND, MVT::i1, Legal);
1408 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1409 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1410 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1411 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1412 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1414 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1415 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1417 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1418 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1419 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1421 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1422 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1423 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1424 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1425 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1426 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1427 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1428 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1430 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1431 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1433 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1434 if (Subtarget->is64Bit()) {
1435 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1436 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1438 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1440 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1441 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1442 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1443 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1444 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1445 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1446 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1447 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1448 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1449 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1450 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1451 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1452 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1453 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1455 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1456 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1457 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1458 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1459 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1460 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1461 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1462 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1463 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1464 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1465 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1466 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1467 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1473 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1474 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1476 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1477 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1479 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1481 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1482 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1484 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1486 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1491 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1492 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1494 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1495 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1497 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1499 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1500 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1502 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1503 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1505 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1506 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1508 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1509 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1510 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1511 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1512 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1513 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1515 if (Subtarget->hasCDI()) {
1516 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1517 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1520 // Custom lower several nodes.
1521 for (MVT VT : MVT::vector_valuetypes()) {
1522 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1523 // Extract subvector is special because the value type
1524 // (result) is 256/128-bit but the source is 512-bit wide.
1525 if (VT.is128BitVector() || VT.is256BitVector()) {
1526 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1528 if (VT.getVectorElementType() == MVT::i1)
1529 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1531 // Do not attempt to custom lower other non-512-bit vectors
1532 if (!VT.is512BitVector())
1535 if ( EltSize >= 32) {
1536 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1537 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1538 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1539 setOperationAction(ISD::VSELECT, VT, Legal);
1540 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1541 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1542 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1543 setOperationAction(ISD::MLOAD, VT, Legal);
1544 setOperationAction(ISD::MSTORE, VT, Legal);
1547 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1548 MVT VT = (MVT::SimpleValueType)i;
1550 // Do not attempt to promote non-512-bit vectors.
1551 if (!VT.is512BitVector())
1554 setOperationAction(ISD::SELECT, VT, Promote);
1555 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1559 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1560 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1561 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1563 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1564 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1566 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1567 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1568 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1569 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1570 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1571 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1572 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1573 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1574 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 const MVT VT = (MVT::SimpleValueType)i;
1579 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1581 // Do not attempt to promote non-512-bit vectors.
1582 if (!VT.is512BitVector())
1586 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1587 setOperationAction(ISD::VSELECT, VT, Legal);
1592 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1593 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1594 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1596 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1597 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1598 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1600 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1601 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1602 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1603 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1604 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1605 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1608 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1609 // of this type with custom code.
1610 for (MVT VT : MVT::vector_valuetypes())
1611 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
1613 // We want to custom lower some of our intrinsics.
1614 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1615 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1616 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1617 if (!Subtarget->is64Bit())
1618 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1620 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1621 // handle type legalization for these operations here.
1623 // FIXME: We really should do custom legalization for addition and
1624 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1625 // than generic legalization for 64-bit multiplication-with-overflow, though.
1626 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1627 // Add/Sub/Mul with overflow operations are custom lowered.
1629 setOperationAction(ISD::SADDO, VT, Custom);
1630 setOperationAction(ISD::UADDO, VT, Custom);
1631 setOperationAction(ISD::SSUBO, VT, Custom);
1632 setOperationAction(ISD::USUBO, VT, Custom);
1633 setOperationAction(ISD::SMULO, VT, Custom);
1634 setOperationAction(ISD::UMULO, VT, Custom);
1638 if (!Subtarget->is64Bit()) {
1639 // These libcalls are not available in 32-bit.
1640 setLibcallName(RTLIB::SHL_I128, nullptr);
1641 setLibcallName(RTLIB::SRL_I128, nullptr);
1642 setLibcallName(RTLIB::SRA_I128, nullptr);
1645 // Combine sin / cos into one node or libcall if possible.
1646 if (Subtarget->hasSinCos()) {
1647 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1648 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1649 if (Subtarget->isTargetDarwin()) {
1650 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1651 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1652 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1653 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1657 if (Subtarget->isTargetWin64()) {
1658 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1659 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1660 setOperationAction(ISD::SREM, MVT::i128, Custom);
1661 setOperationAction(ISD::UREM, MVT::i128, Custom);
1662 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1663 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1666 // We have target-specific dag combine patterns for the following nodes:
1667 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1668 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1669 setTargetDAGCombine(ISD::VSELECT);
1670 setTargetDAGCombine(ISD::SELECT);
1671 setTargetDAGCombine(ISD::SHL);
1672 setTargetDAGCombine(ISD::SRA);
1673 setTargetDAGCombine(ISD::SRL);
1674 setTargetDAGCombine(ISD::OR);
1675 setTargetDAGCombine(ISD::AND);
1676 setTargetDAGCombine(ISD::ADD);
1677 setTargetDAGCombine(ISD::FADD);
1678 setTargetDAGCombine(ISD::FSUB);
1679 setTargetDAGCombine(ISD::FMA);
1680 setTargetDAGCombine(ISD::SUB);
1681 setTargetDAGCombine(ISD::LOAD);
1682 setTargetDAGCombine(ISD::STORE);
1683 setTargetDAGCombine(ISD::ZERO_EXTEND);
1684 setTargetDAGCombine(ISD::ANY_EXTEND);
1685 setTargetDAGCombine(ISD::SIGN_EXTEND);
1686 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1687 setTargetDAGCombine(ISD::TRUNCATE);
1688 setTargetDAGCombine(ISD::SINT_TO_FP);
1689 setTargetDAGCombine(ISD::SETCC);
1690 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1691 setTargetDAGCombine(ISD::BUILD_VECTOR);
1692 if (Subtarget->is64Bit())
1693 setTargetDAGCombine(ISD::MUL);
1694 setTargetDAGCombine(ISD::XOR);
1696 computeRegisterProperties();
1698 // On Darwin, -Os means optimize for size without hurting performance,
1699 // do not reduce the limit.
1700 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1701 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1702 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1703 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1704 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1705 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1706 setPrefLoopAlignment(4); // 2^4 bytes.
1708 // Predictable cmov don't hurt on atom because it's in-order.
1709 PredictableSelectIsExpensive = !Subtarget->isAtom();
1710 EnableExtLdPromotion = true;
1711 setPrefFunctionAlignment(4); // 2^4 bytes.
1713 verifyIntrinsicTables();
1716 // This has so far only been implemented for 64-bit MachO.
1717 bool X86TargetLowering::useLoadStackGuardNode() const {
1718 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1721 TargetLoweringBase::LegalizeTypeAction
1722 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1723 if (ExperimentalVectorWideningLegalization &&
1724 VT.getVectorNumElements() != 1 &&
1725 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1726 return TypeWidenVector;
1728 return TargetLoweringBase::getPreferredVectorAction(VT);
1731 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1733 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1735 const unsigned NumElts = VT.getVectorNumElements();
1736 const EVT EltVT = VT.getVectorElementType();
1737 if (VT.is512BitVector()) {
1738 if (Subtarget->hasAVX512())
1739 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1740 EltVT == MVT::f32 || EltVT == MVT::f64)
1742 case 8: return MVT::v8i1;
1743 case 16: return MVT::v16i1;
1745 if (Subtarget->hasBWI())
1746 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1748 case 32: return MVT::v32i1;
1749 case 64: return MVT::v64i1;
1753 if (VT.is256BitVector() || VT.is128BitVector()) {
1754 if (Subtarget->hasVLX())
1755 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1756 EltVT == MVT::f32 || EltVT == MVT::f64)
1758 case 2: return MVT::v2i1;
1759 case 4: return MVT::v4i1;
1760 case 8: return MVT::v8i1;
1762 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1763 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1765 case 8: return MVT::v8i1;
1766 case 16: return MVT::v16i1;
1767 case 32: return MVT::v32i1;
1771 return VT.changeVectorElementTypeToInteger();
1774 /// Helper for getByValTypeAlignment to determine
1775 /// the desired ByVal argument alignment.
1776 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1779 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1780 if (VTy->getBitWidth() == 128)
1782 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1783 unsigned EltAlign = 0;
1784 getMaxByValAlign(ATy->getElementType(), EltAlign);
1785 if (EltAlign > MaxAlign)
1786 MaxAlign = EltAlign;
1787 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1788 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1789 unsigned EltAlign = 0;
1790 getMaxByValAlign(STy->getElementType(i), EltAlign);
1791 if (EltAlign > MaxAlign)
1792 MaxAlign = EltAlign;
1799 /// Return the desired alignment for ByVal aggregate
1800 /// function arguments in the caller parameter area. For X86, aggregates
1801 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1802 /// are at 4-byte boundaries.
1803 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1804 if (Subtarget->is64Bit()) {
1805 // Max of 8 and alignment of type.
1806 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1813 if (Subtarget->hasSSE1())
1814 getMaxByValAlign(Ty, Align);
1818 /// Returns the target specific optimal type for load
1819 /// and store operations as a result of memset, memcpy, and memmove
1820 /// lowering. If DstAlign is zero that means it's safe to destination
1821 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1822 /// means there isn't a need to check it against alignment requirement,
1823 /// probably because the source does not need to be loaded. If 'IsMemset' is
1824 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1825 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1826 /// source is constant so it does not need to be loaded.
1827 /// It returns EVT::Other if the type should be determined using generic
1828 /// target-independent logic.
1830 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1831 unsigned DstAlign, unsigned SrcAlign,
1832 bool IsMemset, bool ZeroMemset,
1834 MachineFunction &MF) const {
1835 const Function *F = MF.getFunction();
1836 if ((!IsMemset || ZeroMemset) &&
1837 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1838 Attribute::NoImplicitFloat)) {
1840 (Subtarget->isUnalignedMemAccessFast() ||
1841 ((DstAlign == 0 || DstAlign >= 16) &&
1842 (SrcAlign == 0 || SrcAlign >= 16)))) {
1844 if (Subtarget->hasInt256())
1846 if (Subtarget->hasFp256())
1849 if (Subtarget->hasSSE2())
1851 if (Subtarget->hasSSE1())
1853 } else if (!MemcpyStrSrc && Size >= 8 &&
1854 !Subtarget->is64Bit() &&
1855 Subtarget->hasSSE2()) {
1856 // Do not use f64 to lower memcpy if source is string constant. It's
1857 // better to use i32 to avoid the loads.
1861 if (Subtarget->is64Bit() && Size >= 8)
1866 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1868 return X86ScalarSSEf32;
1869 else if (VT == MVT::f64)
1870 return X86ScalarSSEf64;
1875 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1880 *Fast = Subtarget->isUnalignedMemAccessFast();
1884 /// Return the entry encoding for a jump table in the
1885 /// current function. The returned value is a member of the
1886 /// MachineJumpTableInfo::JTEntryKind enum.
1887 unsigned X86TargetLowering::getJumpTableEncoding() const {
1888 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1890 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1891 Subtarget->isPICStyleGOT())
1892 return MachineJumpTableInfo::EK_Custom32;
1894 // Otherwise, use the normal jump table encoding heuristics.
1895 return TargetLowering::getJumpTableEncoding();
1899 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1900 const MachineBasicBlock *MBB,
1901 unsigned uid,MCContext &Ctx) const{
1902 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1903 Subtarget->isPICStyleGOT());
1904 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1906 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1907 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1910 /// Returns relocation base for the given PIC jumptable.
1911 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1912 SelectionDAG &DAG) const {
1913 if (!Subtarget->is64Bit())
1914 // This doesn't have SDLoc associated with it, but is not really the
1915 // same as a Register.
1916 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1920 /// This returns the relocation base for the given PIC jumptable,
1921 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1922 const MCExpr *X86TargetLowering::
1923 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1924 MCContext &Ctx) const {
1925 // X86-64 uses RIP relative addressing based on the jump table label.
1926 if (Subtarget->isPICStyleRIPRel())
1927 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1929 // Otherwise, the reference is relative to the PIC base.
1930 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1933 // FIXME: Why this routine is here? Move to RegInfo!
1934 std::pair<const TargetRegisterClass*, uint8_t>
1935 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1936 const TargetRegisterClass *RRC = nullptr;
1938 switch (VT.SimpleTy) {
1940 return TargetLowering::findRepresentativeClass(VT);
1941 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1942 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1945 RRC = &X86::VR64RegClass;
1947 case MVT::f32: case MVT::f64:
1948 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1949 case MVT::v4f32: case MVT::v2f64:
1950 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1952 RRC = &X86::VR128RegClass;
1955 return std::make_pair(RRC, Cost);
1958 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1959 unsigned &Offset) const {
1960 if (!Subtarget->isTargetLinux())
1963 if (Subtarget->is64Bit()) {
1964 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1966 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1978 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1979 unsigned DestAS) const {
1980 assert(SrcAS != DestAS && "Expected different address spaces!");
1982 return SrcAS < 256 && DestAS < 256;
1985 //===----------------------------------------------------------------------===//
1986 // Return Value Calling Convention Implementation
1987 //===----------------------------------------------------------------------===//
1989 #include "X86GenCallingConv.inc"
1992 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1993 MachineFunction &MF, bool isVarArg,
1994 const SmallVectorImpl<ISD::OutputArg> &Outs,
1995 LLVMContext &Context) const {
1996 SmallVector<CCValAssign, 16> RVLocs;
1997 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1998 return CCInfo.CheckReturn(Outs, RetCC_X86);
2001 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2002 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2007 X86TargetLowering::LowerReturn(SDValue Chain,
2008 CallingConv::ID CallConv, bool isVarArg,
2009 const SmallVectorImpl<ISD::OutputArg> &Outs,
2010 const SmallVectorImpl<SDValue> &OutVals,
2011 SDLoc dl, SelectionDAG &DAG) const {
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2015 SmallVector<CCValAssign, 16> RVLocs;
2016 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2017 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2020 SmallVector<SDValue, 6> RetOps;
2021 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2022 // Operand #1 = Bytes To Pop
2023 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2026 // Copy the result values into the output registers.
2027 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2028 CCValAssign &VA = RVLocs[i];
2029 assert(VA.isRegLoc() && "Can only return in registers!");
2030 SDValue ValToCopy = OutVals[i];
2031 EVT ValVT = ValToCopy.getValueType();
2033 // Promote values to the appropriate types.
2034 if (VA.getLocInfo() == CCValAssign::SExt)
2035 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2036 else if (VA.getLocInfo() == CCValAssign::ZExt)
2037 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2038 else if (VA.getLocInfo() == CCValAssign::AExt)
2039 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2040 else if (VA.getLocInfo() == CCValAssign::BCvt)
2041 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2043 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2044 "Unexpected FP-extend for return value.");
2046 // If this is x86-64, and we disabled SSE, we can't return FP values,
2047 // or SSE or MMX vectors.
2048 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2049 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2050 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2051 report_fatal_error("SSE register return with SSE disabled");
2053 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2054 // llvm-gcc has never done it right and no one has noticed, so this
2055 // should be OK for now.
2056 if (ValVT == MVT::f64 &&
2057 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2058 report_fatal_error("SSE2 register return with SSE2 disabled");
2060 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2061 // the RET instruction and handled by the FP Stackifier.
2062 if (VA.getLocReg() == X86::FP0 ||
2063 VA.getLocReg() == X86::FP1) {
2064 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2065 // change the value to the FP stack register class.
2066 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2067 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2068 RetOps.push_back(ValToCopy);
2069 // Don't emit a copytoreg.
2073 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2074 // which is returned in RAX / RDX.
2075 if (Subtarget->is64Bit()) {
2076 if (ValVT == MVT::x86mmx) {
2077 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2078 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2079 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2081 // If we don't have SSE2 available, convert to v4f32 so the generated
2082 // register is legal.
2083 if (!Subtarget->hasSSE2())
2084 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2089 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2090 Flag = Chain.getValue(1);
2091 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2094 // The x86-64 ABIs require that for returning structs by value we copy
2095 // the sret argument into %rax/%eax (depending on ABI) for the return.
2096 // Win32 requires us to put the sret argument to %eax as well.
2097 // We saved the argument into a virtual register in the entry block,
2098 // so now we copy the value out and into %rax/%eax.
2099 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2100 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2101 MachineFunction &MF = DAG.getMachineFunction();
2102 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2103 unsigned Reg = FuncInfo->getSRetReturnReg();
2105 "SRetReturnReg should have been set in LowerFormalArguments().");
2106 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2109 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2110 X86::RAX : X86::EAX;
2111 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2112 Flag = Chain.getValue(1);
2114 // RAX/EAX now acts like a return value.
2115 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2118 RetOps[0] = Chain; // Update chain.
2120 // Add the flag if we have it.
2122 RetOps.push_back(Flag);
2124 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2127 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2128 if (N->getNumValues() != 1)
2130 if (!N->hasNUsesOfValue(1, 0))
2133 SDValue TCChain = Chain;
2134 SDNode *Copy = *N->use_begin();
2135 if (Copy->getOpcode() == ISD::CopyToReg) {
2136 // If the copy has a glue operand, we conservatively assume it isn't safe to
2137 // perform a tail call.
2138 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2140 TCChain = Copy->getOperand(0);
2141 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2144 bool HasRet = false;
2145 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2147 if (UI->getOpcode() != X86ISD::RET_FLAG)
2149 // If we are returning more than one value, we can definitely
2150 // not make a tail call see PR19530
2151 if (UI->getNumOperands() > 4)
2153 if (UI->getNumOperands() == 4 &&
2154 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2167 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2168 ISD::NodeType ExtendKind) const {
2170 // TODO: Is this also valid on 32-bit?
2171 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2172 ReturnMVT = MVT::i8;
2174 ReturnMVT = MVT::i32;
2176 EVT MinVT = getRegisterType(Context, ReturnMVT);
2177 return VT.bitsLT(MinVT) ? MinVT : VT;
2180 /// Lower the result values of a call into the
2181 /// appropriate copies out of appropriate physical registers.
2184 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2185 CallingConv::ID CallConv, bool isVarArg,
2186 const SmallVectorImpl<ISD::InputArg> &Ins,
2187 SDLoc dl, SelectionDAG &DAG,
2188 SmallVectorImpl<SDValue> &InVals) const {
2190 // Assign locations to each value returned by this call.
2191 SmallVector<CCValAssign, 16> RVLocs;
2192 bool Is64Bit = Subtarget->is64Bit();
2193 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2195 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2197 // Copy all of the result registers out of their specified physreg.
2198 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2199 CCValAssign &VA = RVLocs[i];
2200 EVT CopyVT = VA.getValVT();
2202 // If this is x86-64, and we disabled SSE, we can't return FP values
2203 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2204 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2205 report_fatal_error("SSE register return with SSE disabled");
2208 // If we prefer to use the value in xmm registers, copy it out as f80 and
2209 // use a truncate to move it from fp stack reg to xmm reg.
2210 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2211 isScalarFPTypeInSSEReg(VA.getValVT()))
2214 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2215 CopyVT, InFlag).getValue(1);
2216 SDValue Val = Chain.getValue(0);
2218 if (CopyVT != VA.getValVT())
2219 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2220 // This truncation won't change the value.
2221 DAG.getIntPtrConstant(1));
2223 InFlag = Chain.getValue(2);
2224 InVals.push_back(Val);
2230 //===----------------------------------------------------------------------===//
2231 // C & StdCall & Fast Calling Convention implementation
2232 //===----------------------------------------------------------------------===//
2233 // StdCall calling convention seems to be standard for many Windows' API
2234 // routines and around. It differs from C calling convention just a little:
2235 // callee should clean up the stack, not caller. Symbols should be also
2236 // decorated in some fancy way :) It doesn't support any vector arguments.
2237 // For info on fast calling convention see Fast Calling Convention (tail call)
2238 // implementation LowerX86_32FastCCCallTo.
2240 /// CallIsStructReturn - Determines whether a call uses struct return
2242 enum StructReturnType {
2247 static StructReturnType
2248 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2250 return NotStructReturn;
2252 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2253 if (!Flags.isSRet())
2254 return NotStructReturn;
2255 if (Flags.isInReg())
2256 return RegStructReturn;
2257 return StackStructReturn;
2260 /// Determines whether a function uses struct return semantics.
2261 static StructReturnType
2262 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2264 return NotStructReturn;
2266 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2267 if (!Flags.isSRet())
2268 return NotStructReturn;
2269 if (Flags.isInReg())
2270 return RegStructReturn;
2271 return StackStructReturn;
2274 /// Make a copy of an aggregate at address specified by "Src" to address
2275 /// "Dst" with size and alignment information specified by the specific
2276 /// parameter attribute. The copy will be passed as a byval function parameter.
2278 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2279 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2281 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2283 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2284 /*isVolatile*/false, /*AlwaysInline=*/true,
2285 MachinePointerInfo(), MachinePointerInfo());
2288 /// Return true if the calling convention is one that
2289 /// supports tail call optimization.
2290 static bool IsTailCallConvention(CallingConv::ID CC) {
2291 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2292 CC == CallingConv::HiPE);
2295 /// \brief Return true if the calling convention is a C calling convention.
2296 static bool IsCCallConvention(CallingConv::ID CC) {
2297 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2298 CC == CallingConv::X86_64_SysV);
2301 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2302 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2306 CallingConv::ID CalleeCC = CS.getCallingConv();
2307 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2313 /// Return true if the function is being made into
2314 /// a tailcall target by changing its ABI.
2315 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2316 bool GuaranteedTailCallOpt) {
2317 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2321 X86TargetLowering::LowerMemArgument(SDValue Chain,
2322 CallingConv::ID CallConv,
2323 const SmallVectorImpl<ISD::InputArg> &Ins,
2324 SDLoc dl, SelectionDAG &DAG,
2325 const CCValAssign &VA,
2326 MachineFrameInfo *MFI,
2328 // Create the nodes corresponding to a load from this parameter slot.
2329 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2330 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2331 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2332 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2335 // If value is passed by pointer we have address passed instead of the value
2337 if (VA.getLocInfo() == CCValAssign::Indirect)
2338 ValVT = VA.getLocVT();
2340 ValVT = VA.getValVT();
2342 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2343 // changed with more analysis.
2344 // In case of tail call optimization mark all arguments mutable. Since they
2345 // could be overwritten by lowering of arguments in case of a tail call.
2346 if (Flags.isByVal()) {
2347 unsigned Bytes = Flags.getByValSize();
2348 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2349 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2350 return DAG.getFrameIndex(FI, getPointerTy());
2352 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2353 VA.getLocMemOffset(), isImmutable);
2354 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2355 return DAG.getLoad(ValVT, dl, Chain, FIN,
2356 MachinePointerInfo::getFixedStack(FI),
2357 false, false, false, 0);
2361 // FIXME: Get this from tablegen.
2362 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2363 const X86Subtarget *Subtarget) {
2364 assert(Subtarget->is64Bit());
2366 if (Subtarget->isCallingConvWin64(CallConv)) {
2367 static const MCPhysReg GPR64ArgRegsWin64[] = {
2368 X86::RCX, X86::RDX, X86::R8, X86::R9
2370 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2373 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2374 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2376 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2379 // FIXME: Get this from tablegen.
2380 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2381 CallingConv::ID CallConv,
2382 const X86Subtarget *Subtarget) {
2383 assert(Subtarget->is64Bit());
2384 if (Subtarget->isCallingConvWin64(CallConv)) {
2385 // The XMM registers which might contain var arg parameters are shadowed
2386 // in their paired GPR. So we only need to save the GPR to their home
2388 // TODO: __vectorcall will change this.
2392 const Function *Fn = MF.getFunction();
2393 bool NoImplicitFloatOps = Fn->getAttributes().
2394 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2395 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2396 "SSE register cannot be used when SSE is disabled!");
2397 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2398 !Subtarget->hasSSE1())
2399 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2403 static const MCPhysReg XMMArgRegs64Bit[] = {
2404 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2405 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2407 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2411 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2412 CallingConv::ID CallConv,
2414 const SmallVectorImpl<ISD::InputArg> &Ins,
2417 SmallVectorImpl<SDValue> &InVals)
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2422 const Function* Fn = MF.getFunction();
2423 if (Fn->hasExternalLinkage() &&
2424 Subtarget->isTargetCygMing() &&
2425 Fn->getName() == "main")
2426 FuncInfo->setForceFramePointer(true);
2428 MachineFrameInfo *MFI = MF.getFrameInfo();
2429 bool Is64Bit = Subtarget->is64Bit();
2430 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2432 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2433 "Var args not supported with calling convention fastcc, ghc or hipe");
2435 // Assign locations to all of the incoming arguments.
2436 SmallVector<CCValAssign, 16> ArgLocs;
2437 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2439 // Allocate shadow area for Win64
2441 CCInfo.AllocateStack(32, 8);
2443 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2445 unsigned LastVal = ~0U;
2447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2448 CCValAssign &VA = ArgLocs[i];
2449 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2451 assert(VA.getValNo() != LastVal &&
2452 "Don't support value assigned to multiple locs yet");
2454 LastVal = VA.getValNo();
2456 if (VA.isRegLoc()) {
2457 EVT RegVT = VA.getLocVT();
2458 const TargetRegisterClass *RC;
2459 if (RegVT == MVT::i32)
2460 RC = &X86::GR32RegClass;
2461 else if (Is64Bit && RegVT == MVT::i64)
2462 RC = &X86::GR64RegClass;
2463 else if (RegVT == MVT::f32)
2464 RC = &X86::FR32RegClass;
2465 else if (RegVT == MVT::f64)
2466 RC = &X86::FR64RegClass;
2467 else if (RegVT.is512BitVector())
2468 RC = &X86::VR512RegClass;
2469 else if (RegVT.is256BitVector())
2470 RC = &X86::VR256RegClass;
2471 else if (RegVT.is128BitVector())
2472 RC = &X86::VR128RegClass;
2473 else if (RegVT == MVT::x86mmx)
2474 RC = &X86::VR64RegClass;
2475 else if (RegVT == MVT::i1)
2476 RC = &X86::VK1RegClass;
2477 else if (RegVT == MVT::v8i1)
2478 RC = &X86::VK8RegClass;
2479 else if (RegVT == MVT::v16i1)
2480 RC = &X86::VK16RegClass;
2481 else if (RegVT == MVT::v32i1)
2482 RC = &X86::VK32RegClass;
2483 else if (RegVT == MVT::v64i1)
2484 RC = &X86::VK64RegClass;
2486 llvm_unreachable("Unknown argument type!");
2488 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2489 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2491 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2492 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2494 if (VA.getLocInfo() == CCValAssign::SExt)
2495 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2496 DAG.getValueType(VA.getValVT()));
2497 else if (VA.getLocInfo() == CCValAssign::ZExt)
2498 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2499 DAG.getValueType(VA.getValVT()));
2500 else if (VA.getLocInfo() == CCValAssign::BCvt)
2501 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2503 if (VA.isExtInLoc()) {
2504 // Handle MMX values passed in XMM regs.
2505 if (RegVT.isVector())
2506 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2508 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2511 assert(VA.isMemLoc());
2512 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2515 // If value is passed via pointer - do a load.
2516 if (VA.getLocInfo() == CCValAssign::Indirect)
2517 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2518 MachinePointerInfo(), false, false, false, 0);
2520 InVals.push_back(ArgValue);
2523 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2524 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2525 // The x86-64 ABIs require that for returning structs by value we copy
2526 // the sret argument into %rax/%eax (depending on ABI) for the return.
2527 // Win32 requires us to put the sret argument to %eax as well.
2528 // Save the argument into a virtual register so that we can access it
2529 // from the return points.
2530 if (Ins[i].Flags.isSRet()) {
2531 unsigned Reg = FuncInfo->getSRetReturnReg();
2533 MVT PtrTy = getPointerTy();
2534 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2535 FuncInfo->setSRetReturnReg(Reg);
2537 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2544 unsigned StackSize = CCInfo.getNextStackOffset();
2545 // Align stack specially for tail calls.
2546 if (FuncIsMadeTailCallSafe(CallConv,
2547 MF.getTarget().Options.GuaranteedTailCallOpt))
2548 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2550 // If the function takes variable number of arguments, make a frame index for
2551 // the start of the first vararg value... for expansion of llvm.va_start. We
2552 // can skip this if there are no va_start calls.
2553 if (MFI->hasVAStart() &&
2554 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2555 CallConv != CallingConv::X86_ThisCall))) {
2556 FuncInfo->setVarArgsFrameIndex(
2557 MFI->CreateFixedObject(1, StackSize, true));
2560 // Figure out if XMM registers are in use.
2561 assert(!(MF.getTarget().Options.UseSoftFloat &&
2562 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2563 Attribute::NoImplicitFloat)) &&
2564 "SSE register cannot be used when SSE is disabled!");
2566 // 64-bit calling conventions support varargs and register parameters, so we
2567 // have to do extra work to spill them in the prologue.
2568 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2569 // Find the first unallocated argument registers.
2570 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2571 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2572 unsigned NumIntRegs =
2573 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2574 unsigned NumXMMRegs =
2575 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2576 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2577 "SSE register cannot be used when SSE is disabled!");
2579 // Gather all the live in physical registers.
2580 SmallVector<SDValue, 6> LiveGPRs;
2581 SmallVector<SDValue, 8> LiveXMMRegs;
2583 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2584 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2586 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2588 if (!ArgXMMs.empty()) {
2589 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2590 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2591 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2592 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2593 LiveXMMRegs.push_back(
2594 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2599 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2600 // Get to the caller-allocated home save location. Add 8 to account
2601 // for the return address.
2602 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2603 FuncInfo->setRegSaveFrameIndex(
2604 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2605 // Fixup to set vararg frame on shadow area (4 x i64).
2607 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2609 // For X86-64, if there are vararg parameters that are passed via
2610 // registers, then we must store them to their spots on the stack so
2611 // they may be loaded by deferencing the result of va_next.
2612 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2613 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2614 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2615 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2618 // Store the integer parameter registers.
2619 SmallVector<SDValue, 8> MemOps;
2620 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2622 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2623 for (SDValue Val : LiveGPRs) {
2624 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2625 DAG.getIntPtrConstant(Offset));
2627 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2628 MachinePointerInfo::getFixedStack(
2629 FuncInfo->getRegSaveFrameIndex(), Offset),
2631 MemOps.push_back(Store);
2635 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2636 // Now store the XMM (fp + vector) parameter registers.
2637 SmallVector<SDValue, 12> SaveXMMOps;
2638 SaveXMMOps.push_back(Chain);
2639 SaveXMMOps.push_back(ALVal);
2640 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2641 FuncInfo->getRegSaveFrameIndex()));
2642 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2643 FuncInfo->getVarArgsFPOffset()));
2644 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2646 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2647 MVT::Other, SaveXMMOps));
2650 if (!MemOps.empty())
2651 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2654 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2655 // Find the largest legal vector type.
2656 MVT VecVT = MVT::Other;
2657 // FIXME: Only some x86_32 calling conventions support AVX512.
2658 if (Subtarget->hasAVX512() &&
2659 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2660 CallConv == CallingConv::Intel_OCL_BI)))
2661 VecVT = MVT::v16f32;
2662 else if (Subtarget->hasAVX())
2664 else if (Subtarget->hasSSE2())
2667 // We forward some GPRs and some vector types.
2668 SmallVector<MVT, 2> RegParmTypes;
2669 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2670 RegParmTypes.push_back(IntVT);
2671 if (VecVT != MVT::Other)
2672 RegParmTypes.push_back(VecVT);
2674 // Compute the set of forwarded registers. The rest are scratch.
2675 SmallVectorImpl<ForwardedRegister> &Forwards =
2676 FuncInfo->getForwardedMustTailRegParms();
2677 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2679 // Conservatively forward AL on x86_64, since it might be used for varargs.
2680 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2681 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2682 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2685 // Copy all forwards from physical to virtual registers.
2686 for (ForwardedRegister &F : Forwards) {
2687 // FIXME: Can we use a less constrained schedule?
2688 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2689 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2690 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2694 // Some CCs need callee pop.
2695 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2696 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2697 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2699 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2700 // If this is an sret function, the return should pop the hidden pointer.
2701 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2702 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2703 argsAreStructReturn(Ins) == StackStructReturn)
2704 FuncInfo->setBytesToPopOnReturn(4);
2708 // RegSaveFrameIndex is X86-64 only.
2709 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2710 if (CallConv == CallingConv::X86_FastCall ||
2711 CallConv == CallingConv::X86_ThisCall)
2712 // fastcc functions can't have varargs.
2713 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2716 FuncInfo->setArgumentStackSize(StackSize);
2722 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2723 SDValue StackPtr, SDValue Arg,
2724 SDLoc dl, SelectionDAG &DAG,
2725 const CCValAssign &VA,
2726 ISD::ArgFlagsTy Flags) const {
2727 unsigned LocMemOffset = VA.getLocMemOffset();
2728 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2729 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2730 if (Flags.isByVal())
2731 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2733 return DAG.getStore(Chain, dl, Arg, PtrOff,
2734 MachinePointerInfo::getStack(LocMemOffset),
2738 /// Emit a load of return address if tail call
2739 /// optimization is performed and it is required.
2741 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2742 SDValue &OutRetAddr, SDValue Chain,
2743 bool IsTailCall, bool Is64Bit,
2744 int FPDiff, SDLoc dl) const {
2745 // Adjust the Return address stack slot.
2746 EVT VT = getPointerTy();
2747 OutRetAddr = getReturnAddressFrameIndex(DAG);
2749 // Load the "old" Return address.
2750 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2751 false, false, false, 0);
2752 return SDValue(OutRetAddr.getNode(), 1);
2755 /// Emit a store of the return address if tail call
2756 /// optimization is performed and it is required (FPDiff!=0).
2757 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2758 SDValue Chain, SDValue RetAddrFrIdx,
2759 EVT PtrVT, unsigned SlotSize,
2760 int FPDiff, SDLoc dl) {
2761 // Store the return address to the appropriate stack slot.
2762 if (!FPDiff) return Chain;
2763 // Calculate the new stack slot for the return address.
2764 int NewReturnAddrFI =
2765 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2767 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2768 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2769 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2775 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2776 SmallVectorImpl<SDValue> &InVals) const {
2777 SelectionDAG &DAG = CLI.DAG;
2779 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2780 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2781 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2782 SDValue Chain = CLI.Chain;
2783 SDValue Callee = CLI.Callee;
2784 CallingConv::ID CallConv = CLI.CallConv;
2785 bool &isTailCall = CLI.IsTailCall;
2786 bool isVarArg = CLI.IsVarArg;
2788 MachineFunction &MF = DAG.getMachineFunction();
2789 bool Is64Bit = Subtarget->is64Bit();
2790 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2791 StructReturnType SR = callIsStructReturn(Outs);
2792 bool IsSibcall = false;
2793 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2795 if (MF.getTarget().Options.DisableTailCalls)
2798 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2800 // Force this to be a tail call. The verifier rules are enough to ensure
2801 // that we can lower this successfully without moving the return address
2804 } else if (isTailCall) {
2805 // Check if it's really possible to do a tail call.
2806 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2807 isVarArg, SR != NotStructReturn,
2808 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2809 Outs, OutVals, Ins, DAG);
2811 // Sibcalls are automatically detected tailcalls which do not require
2813 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2820 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2821 "Var args not supported with calling convention fastcc, ghc or hipe");
2823 // Analyze operands of the call, assigning locations to each operand.
2824 SmallVector<CCValAssign, 16> ArgLocs;
2825 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2827 // Allocate shadow area for Win64
2829 CCInfo.AllocateStack(32, 8);
2831 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2833 // Get a count of how many bytes are to be pushed on the stack.
2834 unsigned NumBytes = CCInfo.getNextStackOffset();
2836 // This is a sibcall. The memory operands are available in caller's
2837 // own caller's stack.
2839 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2840 IsTailCallConvention(CallConv))
2841 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2844 if (isTailCall && !IsSibcall && !IsMustTail) {
2845 // Lower arguments at fp - stackoffset + fpdiff.
2846 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2848 FPDiff = NumBytesCallerPushed - NumBytes;
2850 // Set the delta of movement of the returnaddr stackslot.
2851 // But only set if delta is greater than previous delta.
2852 if (FPDiff < X86Info->getTCReturnAddrDelta())
2853 X86Info->setTCReturnAddrDelta(FPDiff);
2856 unsigned NumBytesToPush = NumBytes;
2857 unsigned NumBytesToPop = NumBytes;
2859 // If we have an inalloca argument, all stack space has already been allocated
2860 // for us and be right at the top of the stack. We don't support multiple
2861 // arguments passed in memory when using inalloca.
2862 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2864 if (!ArgLocs.back().isMemLoc())
2865 report_fatal_error("cannot use inalloca attribute on a register "
2867 if (ArgLocs.back().getLocMemOffset() != 0)
2868 report_fatal_error("any parameter with the inalloca attribute must be "
2869 "the only memory argument");
2873 Chain = DAG.getCALLSEQ_START(
2874 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2876 SDValue RetAddrFrIdx;
2877 // Load return address for tail calls.
2878 if (isTailCall && FPDiff)
2879 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2880 Is64Bit, FPDiff, dl);
2882 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2883 SmallVector<SDValue, 8> MemOpChains;
2886 // Walk the register/memloc assignments, inserting copies/loads. In the case
2887 // of tail call optimization arguments are handle later.
2888 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2889 DAG.getSubtarget().getRegisterInfo());
2890 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2891 // Skip inalloca arguments, they have already been written.
2892 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2893 if (Flags.isInAlloca())
2896 CCValAssign &VA = ArgLocs[i];
2897 EVT RegVT = VA.getLocVT();
2898 SDValue Arg = OutVals[i];
2899 bool isByVal = Flags.isByVal();
2901 // Promote the value if needed.
2902 switch (VA.getLocInfo()) {
2903 default: llvm_unreachable("Unknown loc info!");
2904 case CCValAssign::Full: break;
2905 case CCValAssign::SExt:
2906 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2908 case CCValAssign::ZExt:
2909 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2911 case CCValAssign::AExt:
2912 if (RegVT.is128BitVector()) {
2913 // Special case: passing MMX values in XMM registers.
2914 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2915 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2916 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2918 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2920 case CCValAssign::BCvt:
2921 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2923 case CCValAssign::Indirect: {
2924 // Store the argument.
2925 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2926 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2927 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2928 MachinePointerInfo::getFixedStack(FI),
2935 if (VA.isRegLoc()) {
2936 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2937 if (isVarArg && IsWin64) {
2938 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2939 // shadow reg if callee is a varargs function.
2940 unsigned ShadowReg = 0;
2941 switch (VA.getLocReg()) {
2942 case X86::XMM0: ShadowReg = X86::RCX; break;
2943 case X86::XMM1: ShadowReg = X86::RDX; break;
2944 case X86::XMM2: ShadowReg = X86::R8; break;
2945 case X86::XMM3: ShadowReg = X86::R9; break;
2948 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2950 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2951 assert(VA.isMemLoc());
2952 if (!StackPtr.getNode())
2953 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2955 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2956 dl, DAG, VA, Flags));
2960 if (!MemOpChains.empty())
2961 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2963 if (Subtarget->isPICStyleGOT()) {
2964 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2967 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2968 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2970 // If we are tail calling and generating PIC/GOT style code load the
2971 // address of the callee into ECX. The value in ecx is used as target of
2972 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2973 // for tail calls on PIC/GOT architectures. Normally we would just put the
2974 // address of GOT into ebx and then call target@PLT. But for tail calls
2975 // ebx would be restored (since ebx is callee saved) before jumping to the
2978 // Note: The actual moving to ECX is done further down.
2979 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2980 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2981 !G->getGlobal()->hasProtectedVisibility())
2982 Callee = LowerGlobalAddress(Callee, DAG);
2983 else if (isa<ExternalSymbolSDNode>(Callee))
2984 Callee = LowerExternalSymbol(Callee, DAG);
2988 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2989 // From AMD64 ABI document:
2990 // For calls that may call functions that use varargs or stdargs
2991 // (prototype-less calls or calls to functions containing ellipsis (...) in
2992 // the declaration) %al is used as hidden argument to specify the number
2993 // of SSE registers used. The contents of %al do not need to match exactly
2994 // the number of registers, but must be an ubound on the number of SSE
2995 // registers used and is in the range 0 - 8 inclusive.
2997 // Count the number of XMM registers allocated.
2998 static const MCPhysReg XMMArgRegs[] = {
2999 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3000 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3002 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
3003 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3004 && "SSE registers cannot be used when SSE is disabled");
3006 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3007 DAG.getConstant(NumXMMRegs, MVT::i8)));
3010 if (isVarArg && IsMustTail) {
3011 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3012 for (const auto &F : Forwards) {
3013 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3014 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3018 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3019 // don't need this because the eligibility check rejects calls that require
3020 // shuffling arguments passed in memory.
3021 if (!IsSibcall && isTailCall) {
3022 // Force all the incoming stack arguments to be loaded from the stack
3023 // before any new outgoing arguments are stored to the stack, because the
3024 // outgoing stack slots may alias the incoming argument stack slots, and
3025 // the alias isn't otherwise explicit. This is slightly more conservative
3026 // than necessary, because it means that each store effectively depends
3027 // on every argument instead of just those arguments it would clobber.
3028 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3030 SmallVector<SDValue, 8> MemOpChains2;
3033 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3034 CCValAssign &VA = ArgLocs[i];
3037 assert(VA.isMemLoc());
3038 SDValue Arg = OutVals[i];
3039 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3040 // Skip inalloca arguments. They don't require any work.
3041 if (Flags.isInAlloca())
3043 // Create frame index.
3044 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3045 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3046 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3047 FIN = DAG.getFrameIndex(FI, getPointerTy());
3049 if (Flags.isByVal()) {
3050 // Copy relative to framepointer.
3051 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3052 if (!StackPtr.getNode())
3053 StackPtr = DAG.getCopyFromReg(Chain, dl,
3054 RegInfo->getStackRegister(),
3056 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3058 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3062 // Store relative to framepointer.
3063 MemOpChains2.push_back(
3064 DAG.getStore(ArgChain, dl, Arg, FIN,
3065 MachinePointerInfo::getFixedStack(FI),
3070 if (!MemOpChains2.empty())
3071 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3073 // Store the return address to the appropriate stack slot.
3074 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3075 getPointerTy(), RegInfo->getSlotSize(),
3079 // Build a sequence of copy-to-reg nodes chained together with token chain
3080 // and flag operands which copy the outgoing args into registers.
3082 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3083 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3084 RegsToPass[i].second, InFlag);
3085 InFlag = Chain.getValue(1);
3088 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3089 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3090 // In the 64-bit large code model, we have to make all calls
3091 // through a register, since the call instruction's 32-bit
3092 // pc-relative offset may not be large enough to hold the whole
3094 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3095 // If the callee is a GlobalAddress node (quite common, every direct call
3096 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3098 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3100 // We should use extra load for direct calls to dllimported functions in
3102 const GlobalValue *GV = G->getGlobal();
3103 if (!GV->hasDLLImportStorageClass()) {
3104 unsigned char OpFlags = 0;
3105 bool ExtraLoad = false;
3106 unsigned WrapperKind = ISD::DELETED_NODE;
3108 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3109 // external symbols most go through the PLT in PIC mode. If the symbol
3110 // has hidden or protected visibility, or if it is static or local, then
3111 // we don't need to use the PLT - we can directly call it.
3112 if (Subtarget->isTargetELF() &&
3113 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3114 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3115 OpFlags = X86II::MO_PLT;
3116 } else if (Subtarget->isPICStyleStubAny() &&
3117 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3118 (!Subtarget->getTargetTriple().isMacOSX() ||
3119 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3120 // PC-relative references to external symbols should go through $stub,
3121 // unless we're building with the leopard linker or later, which
3122 // automatically synthesizes these stubs.
3123 OpFlags = X86II::MO_DARWIN_STUB;
3124 } else if (Subtarget->isPICStyleRIPRel() &&
3125 isa<Function>(GV) &&
3126 cast<Function>(GV)->getAttributes().
3127 hasAttribute(AttributeSet::FunctionIndex,
3128 Attribute::NonLazyBind)) {
3129 // If the function is marked as non-lazy, generate an indirect call
3130 // which loads from the GOT directly. This avoids runtime overhead
3131 // at the cost of eager binding (and one extra byte of encoding).
3132 OpFlags = X86II::MO_GOTPCREL;
3133 WrapperKind = X86ISD::WrapperRIP;
3137 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3138 G->getOffset(), OpFlags);
3140 // Add a wrapper if needed.
3141 if (WrapperKind != ISD::DELETED_NODE)
3142 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3143 // Add extra indirection if needed.
3145 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3146 MachinePointerInfo::getGOT(),
3147 false, false, false, 0);
3149 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3150 unsigned char OpFlags = 0;
3152 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3153 // external symbols should go through the PLT.
3154 if (Subtarget->isTargetELF() &&
3155 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3156 OpFlags = X86II::MO_PLT;
3157 } else if (Subtarget->isPICStyleStubAny() &&
3158 (!Subtarget->getTargetTriple().isMacOSX() ||
3159 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3160 // PC-relative references to external symbols should go through $stub,
3161 // unless we're building with the leopard linker or later, which
3162 // automatically synthesizes these stubs.
3163 OpFlags = X86II::MO_DARWIN_STUB;
3166 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3168 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3169 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3170 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3173 // Returns a chain & a flag for retval copy to use.
3174 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3175 SmallVector<SDValue, 8> Ops;
3177 if (!IsSibcall && isTailCall) {
3178 Chain = DAG.getCALLSEQ_END(Chain,
3179 DAG.getIntPtrConstant(NumBytesToPop, true),
3180 DAG.getIntPtrConstant(0, true), InFlag, dl);
3181 InFlag = Chain.getValue(1);
3184 Ops.push_back(Chain);
3185 Ops.push_back(Callee);
3188 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3190 // Add argument registers to the end of the list so that they are known live
3192 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3193 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3194 RegsToPass[i].second.getValueType()));
3196 // Add a register mask operand representing the call-preserved registers.
3197 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3198 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3199 assert(Mask && "Missing call preserved mask for calling convention");
3200 Ops.push_back(DAG.getRegisterMask(Mask));
3202 if (InFlag.getNode())
3203 Ops.push_back(InFlag);
3207 //// If this is the first return lowered for this function, add the regs
3208 //// to the liveout set for the function.
3209 // This isn't right, although it's probably harmless on x86; liveouts
3210 // should be computed from returns not tail calls. Consider a void
3211 // function making a tail call to a function returning int.
3212 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3215 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3216 InFlag = Chain.getValue(1);
3218 // Create the CALLSEQ_END node.
3219 unsigned NumBytesForCalleeToPop;
3220 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3221 DAG.getTarget().Options.GuaranteedTailCallOpt))
3222 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3223 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3224 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3225 SR == StackStructReturn)
3226 // If this is a call to a struct-return function, the callee
3227 // pops the hidden struct pointer, so we have to push it back.
3228 // This is common for Darwin/X86, Linux & Mingw32 targets.
3229 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3230 NumBytesForCalleeToPop = 4;
3232 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3234 // Returns a flag for retval copy to use.
3236 Chain = DAG.getCALLSEQ_END(Chain,
3237 DAG.getIntPtrConstant(NumBytesToPop, true),
3238 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3241 InFlag = Chain.getValue(1);
3244 // Handle result values, copying them out of physregs into vregs that we
3246 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3247 Ins, dl, DAG, InVals);
3250 //===----------------------------------------------------------------------===//
3251 // Fast Calling Convention (tail call) implementation
3252 //===----------------------------------------------------------------------===//
3254 // Like std call, callee cleans arguments, convention except that ECX is
3255 // reserved for storing the tail called function address. Only 2 registers are
3256 // free for argument passing (inreg). Tail call optimization is performed
3258 // * tailcallopt is enabled
3259 // * caller/callee are fastcc
3260 // On X86_64 architecture with GOT-style position independent code only local
3261 // (within module) calls are supported at the moment.
3262 // To keep the stack aligned according to platform abi the function
3263 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3264 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3265 // If a tail called function callee has more arguments than the caller the
3266 // caller needs to make sure that there is room to move the RETADDR to. This is
3267 // achieved by reserving an area the size of the argument delta right after the
3268 // original RETADDR, but before the saved framepointer or the spilled registers
3269 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3281 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3282 /// for a 16 byte align requirement.
3284 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3285 SelectionDAG& DAG) const {
3286 MachineFunction &MF = DAG.getMachineFunction();
3287 const TargetMachine &TM = MF.getTarget();
3288 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3289 TM.getSubtargetImpl()->getRegisterInfo());
3290 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3291 unsigned StackAlignment = TFI.getStackAlignment();
3292 uint64_t AlignMask = StackAlignment - 1;
3293 int64_t Offset = StackSize;
3294 unsigned SlotSize = RegInfo->getSlotSize();
3295 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3296 // Number smaller than 12 so just add the difference.
3297 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3299 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3300 Offset = ((~AlignMask) & Offset) + StackAlignment +
3301 (StackAlignment-SlotSize);
3306 /// MatchingStackOffset - Return true if the given stack call argument is
3307 /// already available in the same position (relatively) of the caller's
3308 /// incoming argument stack.
3310 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3311 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3312 const X86InstrInfo *TII) {
3313 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3315 if (Arg.getOpcode() == ISD::CopyFromReg) {
3316 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3317 if (!TargetRegisterInfo::isVirtualRegister(VR))
3319 MachineInstr *Def = MRI->getVRegDef(VR);
3322 if (!Flags.isByVal()) {
3323 if (!TII->isLoadFromStackSlot(Def, FI))
3326 unsigned Opcode = Def->getOpcode();
3327 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3328 Def->getOperand(1).isFI()) {
3329 FI = Def->getOperand(1).getIndex();
3330 Bytes = Flags.getByValSize();
3334 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3335 if (Flags.isByVal())
3336 // ByVal argument is passed in as a pointer but it's now being
3337 // dereferenced. e.g.
3338 // define @foo(%struct.X* %A) {
3339 // tail call @bar(%struct.X* byval %A)
3342 SDValue Ptr = Ld->getBasePtr();
3343 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3346 FI = FINode->getIndex();
3347 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3348 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3349 FI = FINode->getIndex();
3350 Bytes = Flags.getByValSize();
3354 assert(FI != INT_MAX);
3355 if (!MFI->isFixedObjectIndex(FI))
3357 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3360 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3361 /// for tail call optimization. Targets which want to do tail call
3362 /// optimization should implement this function.
3364 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3365 CallingConv::ID CalleeCC,
3367 bool isCalleeStructRet,
3368 bool isCallerStructRet,
3370 const SmallVectorImpl<ISD::OutputArg> &Outs,
3371 const SmallVectorImpl<SDValue> &OutVals,
3372 const SmallVectorImpl<ISD::InputArg> &Ins,
3373 SelectionDAG &DAG) const {
3374 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3377 // If -tailcallopt is specified, make fastcc functions tail-callable.
3378 const MachineFunction &MF = DAG.getMachineFunction();
3379 const Function *CallerF = MF.getFunction();
3381 // If the function return type is x86_fp80 and the callee return type is not,
3382 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3383 // perform a tailcall optimization here.
3384 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3387 CallingConv::ID CallerCC = CallerF->getCallingConv();
3388 bool CCMatch = CallerCC == CalleeCC;
3389 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3390 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3392 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3393 if (IsTailCallConvention(CalleeCC) && CCMatch)
3398 // Look for obvious safe cases to perform tail call optimization that do not
3399 // require ABI changes. This is what gcc calls sibcall.
3401 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3402 // emit a special epilogue.
3403 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3404 DAG.getSubtarget().getRegisterInfo());
3405 if (RegInfo->needsStackRealignment(MF))
3408 // Also avoid sibcall optimization if either caller or callee uses struct
3409 // return semantics.
3410 if (isCalleeStructRet || isCallerStructRet)
3413 // An stdcall/thiscall caller is expected to clean up its arguments; the
3414 // callee isn't going to do that.
3415 // FIXME: this is more restrictive than needed. We could produce a tailcall
3416 // when the stack adjustment matches. For example, with a thiscall that takes
3417 // only one argument.
3418 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3419 CallerCC == CallingConv::X86_ThisCall))
3422 // Do not sibcall optimize vararg calls unless all arguments are passed via
3424 if (isVarArg && !Outs.empty()) {
3426 // Optimizing for varargs on Win64 is unlikely to be safe without
3427 // additional testing.
3428 if (IsCalleeWin64 || IsCallerWin64)
3431 SmallVector<CCValAssign, 16> ArgLocs;
3432 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3435 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3436 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3437 if (!ArgLocs[i].isRegLoc())
3441 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3442 // stack. Therefore, if it's not used by the call it is not safe to optimize
3443 // this into a sibcall.
3444 bool Unused = false;
3445 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3452 SmallVector<CCValAssign, 16> RVLocs;
3453 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3455 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3456 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3457 CCValAssign &VA = RVLocs[i];
3458 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3463 // If the calling conventions do not match, then we'd better make sure the
3464 // results are returned in the same way as what the caller expects.
3466 SmallVector<CCValAssign, 16> RVLocs1;
3467 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3469 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3471 SmallVector<CCValAssign, 16> RVLocs2;
3472 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3474 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3476 if (RVLocs1.size() != RVLocs2.size())
3478 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3479 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3481 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3483 if (RVLocs1[i].isRegLoc()) {
3484 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3487 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3493 // If the callee takes no arguments then go on to check the results of the
3495 if (!Outs.empty()) {
3496 // Check if stack adjustment is needed. For now, do not do this if any
3497 // argument is passed on the stack.
3498 SmallVector<CCValAssign, 16> ArgLocs;
3499 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3502 // Allocate shadow area for Win64
3504 CCInfo.AllocateStack(32, 8);
3506 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3507 if (CCInfo.getNextStackOffset()) {
3508 MachineFunction &MF = DAG.getMachineFunction();
3509 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3512 // Check if the arguments are already laid out in the right way as
3513 // the caller's fixed stack objects.
3514 MachineFrameInfo *MFI = MF.getFrameInfo();
3515 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3516 const X86InstrInfo *TII =
3517 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3518 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3519 CCValAssign &VA = ArgLocs[i];
3520 SDValue Arg = OutVals[i];
3521 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3522 if (VA.getLocInfo() == CCValAssign::Indirect)
3524 if (!VA.isRegLoc()) {
3525 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3532 // If the tailcall address may be in a register, then make sure it's
3533 // possible to register allocate for it. In 32-bit, the call address can
3534 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3535 // callee-saved registers are restored. These happen to be the same
3536 // registers used to pass 'inreg' arguments so watch out for those.
3537 if (!Subtarget->is64Bit() &&
3538 ((!isa<GlobalAddressSDNode>(Callee) &&
3539 !isa<ExternalSymbolSDNode>(Callee)) ||
3540 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3541 unsigned NumInRegs = 0;
3542 // In PIC we need an extra register to formulate the address computation
3544 unsigned MaxInRegs =
3545 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3547 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3548 CCValAssign &VA = ArgLocs[i];
3551 unsigned Reg = VA.getLocReg();
3554 case X86::EAX: case X86::EDX: case X86::ECX:
3555 if (++NumInRegs == MaxInRegs)
3567 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3568 const TargetLibraryInfo *libInfo) const {
3569 return X86::createFastISel(funcInfo, libInfo);
3572 //===----------------------------------------------------------------------===//
3573 // Other Lowering Hooks
3574 //===----------------------------------------------------------------------===//
3576 static bool MayFoldLoad(SDValue Op) {
3577 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3580 static bool MayFoldIntoStore(SDValue Op) {
3581 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3584 static bool isTargetShuffle(unsigned Opcode) {
3586 default: return false;
3587 case X86ISD::BLENDI:
3588 case X86ISD::PSHUFB:
3589 case X86ISD::PSHUFD:
3590 case X86ISD::PSHUFHW:
3591 case X86ISD::PSHUFLW:
3593 case X86ISD::PALIGNR:
3594 case X86ISD::MOVLHPS:
3595 case X86ISD::MOVLHPD:
3596 case X86ISD::MOVHLPS:
3597 case X86ISD::MOVLPS:
3598 case X86ISD::MOVLPD:
3599 case X86ISD::MOVSHDUP:
3600 case X86ISD::MOVSLDUP:
3601 case X86ISD::MOVDDUP:
3604 case X86ISD::UNPCKL:
3605 case X86ISD::UNPCKH:
3606 case X86ISD::VPERMILPI:
3607 case X86ISD::VPERM2X128:
3608 case X86ISD::VPERMI:
3613 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3614 SDValue V1, SelectionDAG &DAG) {
3616 default: llvm_unreachable("Unknown x86 shuffle node");
3617 case X86ISD::MOVSHDUP:
3618 case X86ISD::MOVSLDUP:
3619 case X86ISD::MOVDDUP:
3620 return DAG.getNode(Opc, dl, VT, V1);
3624 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3625 SDValue V1, unsigned TargetMask,
3626 SelectionDAG &DAG) {
3628 default: llvm_unreachable("Unknown x86 shuffle node");
3629 case X86ISD::PSHUFD:
3630 case X86ISD::PSHUFHW:
3631 case X86ISD::PSHUFLW:
3632 case X86ISD::VPERMILPI:
3633 case X86ISD::VPERMI:
3634 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3638 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3639 SDValue V1, SDValue V2, unsigned TargetMask,
3640 SelectionDAG &DAG) {
3642 default: llvm_unreachable("Unknown x86 shuffle node");
3643 case X86ISD::PALIGNR:
3644 case X86ISD::VALIGN:
3646 case X86ISD::VPERM2X128:
3647 return DAG.getNode(Opc, dl, VT, V1, V2,
3648 DAG.getConstant(TargetMask, MVT::i8));
3652 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3653 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3655 default: llvm_unreachable("Unknown x86 shuffle node");
3656 case X86ISD::MOVLHPS:
3657 case X86ISD::MOVLHPD:
3658 case X86ISD::MOVHLPS:
3659 case X86ISD::MOVLPS:
3660 case X86ISD::MOVLPD:
3663 case X86ISD::UNPCKL:
3664 case X86ISD::UNPCKH:
3665 return DAG.getNode(Opc, dl, VT, V1, V2);
3669 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3670 MachineFunction &MF = DAG.getMachineFunction();
3671 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3672 DAG.getSubtarget().getRegisterInfo());
3673 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3674 int ReturnAddrIndex = FuncInfo->getRAIndex();
3676 if (ReturnAddrIndex == 0) {
3677 // Set up a frame object for the return address.
3678 unsigned SlotSize = RegInfo->getSlotSize();
3679 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3682 FuncInfo->setRAIndex(ReturnAddrIndex);
3685 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3688 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3689 bool hasSymbolicDisplacement) {
3690 // Offset should fit into 32 bit immediate field.
3691 if (!isInt<32>(Offset))
3694 // If we don't have a symbolic displacement - we don't have any extra
3696 if (!hasSymbolicDisplacement)
3699 // FIXME: Some tweaks might be needed for medium code model.
3700 if (M != CodeModel::Small && M != CodeModel::Kernel)
3703 // For small code model we assume that latest object is 16MB before end of 31
3704 // bits boundary. We may also accept pretty large negative constants knowing
3705 // that all objects are in the positive half of address space.
3706 if (M == CodeModel::Small && Offset < 16*1024*1024)
3709 // For kernel code model we know that all object resist in the negative half
3710 // of 32bits address space. We may not accept negative offsets, since they may
3711 // be just off and we may accept pretty large positive ones.
3712 if (M == CodeModel::Kernel && Offset >= 0)
3718 /// isCalleePop - Determines whether the callee is required to pop its
3719 /// own arguments. Callee pop is necessary to support tail calls.
3720 bool X86::isCalleePop(CallingConv::ID CallingConv,
3721 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3722 switch (CallingConv) {
3725 case CallingConv::X86_StdCall:
3726 case CallingConv::X86_FastCall:
3727 case CallingConv::X86_ThisCall:
3729 case CallingConv::Fast:
3730 case CallingConv::GHC:
3731 case CallingConv::HiPE:
3738 /// \brief Return true if the condition is an unsigned comparison operation.
3739 static bool isX86CCUnsigned(unsigned X86CC) {
3741 default: llvm_unreachable("Invalid integer condition!");
3742 case X86::COND_E: return true;
3743 case X86::COND_G: return false;
3744 case X86::COND_GE: return false;
3745 case X86::COND_L: return false;
3746 case X86::COND_LE: return false;
3747 case X86::COND_NE: return true;
3748 case X86::COND_B: return true;
3749 case X86::COND_A: return true;
3750 case X86::COND_BE: return true;
3751 case X86::COND_AE: return true;
3753 llvm_unreachable("covered switch fell through?!");
3756 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3757 /// specific condition code, returning the condition code and the LHS/RHS of the
3758 /// comparison to make.
3759 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3760 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3762 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3763 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3764 // X > -1 -> X == 0, jump !sign.
3765 RHS = DAG.getConstant(0, RHS.getValueType());
3766 return X86::COND_NS;
3768 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3769 // X < 0 -> X == 0, jump on sign.
3772 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3774 RHS = DAG.getConstant(0, RHS.getValueType());
3775 return X86::COND_LE;
3779 switch (SetCCOpcode) {
3780 default: llvm_unreachable("Invalid integer condition!");
3781 case ISD::SETEQ: return X86::COND_E;
3782 case ISD::SETGT: return X86::COND_G;
3783 case ISD::SETGE: return X86::COND_GE;
3784 case ISD::SETLT: return X86::COND_L;
3785 case ISD::SETLE: return X86::COND_LE;
3786 case ISD::SETNE: return X86::COND_NE;
3787 case ISD::SETULT: return X86::COND_B;
3788 case ISD::SETUGT: return X86::COND_A;
3789 case ISD::SETULE: return X86::COND_BE;
3790 case ISD::SETUGE: return X86::COND_AE;
3794 // First determine if it is required or is profitable to flip the operands.
3796 // If LHS is a foldable load, but RHS is not, flip the condition.
3797 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3798 !ISD::isNON_EXTLoad(RHS.getNode())) {
3799 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3800 std::swap(LHS, RHS);
3803 switch (SetCCOpcode) {
3809 std::swap(LHS, RHS);
3813 // On a floating point condition, the flags are set as follows:
3815 // 0 | 0 | 0 | X > Y
3816 // 0 | 0 | 1 | X < Y
3817 // 1 | 0 | 0 | X == Y
3818 // 1 | 1 | 1 | unordered
3819 switch (SetCCOpcode) {
3820 default: llvm_unreachable("Condcode should be pre-legalized away");
3822 case ISD::SETEQ: return X86::COND_E;
3823 case ISD::SETOLT: // flipped
3825 case ISD::SETGT: return X86::COND_A;
3826 case ISD::SETOLE: // flipped
3828 case ISD::SETGE: return X86::COND_AE;
3829 case ISD::SETUGT: // flipped
3831 case ISD::SETLT: return X86::COND_B;
3832 case ISD::SETUGE: // flipped
3834 case ISD::SETLE: return X86::COND_BE;
3836 case ISD::SETNE: return X86::COND_NE;
3837 case ISD::SETUO: return X86::COND_P;
3838 case ISD::SETO: return X86::COND_NP;
3840 case ISD::SETUNE: return X86::COND_INVALID;
3844 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3845 /// code. Current x86 isa includes the following FP cmov instructions:
3846 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3847 static bool hasFPCMov(unsigned X86CC) {
3863 /// isFPImmLegal - Returns true if the target can instruction select the
3864 /// specified FP immediate natively. If false, the legalizer will
3865 /// materialize the FP immediate as a load from a constant pool.
3866 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3867 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3868 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3874 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3875 ISD::LoadExtType ExtTy,
3877 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3878 // relocation target a movq or addq instruction: don't let the load shrink.
3879 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3880 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3881 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3882 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3886 /// \brief Returns true if it is beneficial to convert a load of a constant
3887 /// to just the constant itself.
3888 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3890 assert(Ty->isIntegerTy());
3892 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3893 if (BitSize == 0 || BitSize > 64)
3898 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3899 unsigned Index) const {
3900 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3903 return (Index == 0 || Index == ResVT.getVectorNumElements());
3906 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3907 // Speculate cttz only if we can directly use TZCNT.
3908 return Subtarget->hasBMI();
3911 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3912 // Speculate ctlz only if we can directly use LZCNT.
3913 return Subtarget->hasLZCNT();
3916 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3917 /// the specified range (L, H].
3918 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3919 return (Val < 0) || (Val >= Low && Val < Hi);
3922 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3923 /// specified value.
3924 static bool isUndefOrEqual(int Val, int CmpVal) {
3925 return (Val < 0 || Val == CmpVal);
3928 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3929 /// from position Pos and ending in Pos+Size, falls within the specified
3930 /// sequential range (Low, Low+Size]. or is undef.
3931 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3932 unsigned Pos, unsigned Size, int Low) {
3933 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3934 if (!isUndefOrEqual(Mask[i], Low))
3939 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3940 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3941 /// operand - by default will match for first operand.
3942 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3943 bool TestSecondOperand = false) {
3944 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3945 VT != MVT::v2f64 && VT != MVT::v2i64)
3948 unsigned NumElems = VT.getVectorNumElements();
3949 unsigned Lo = TestSecondOperand ? NumElems : 0;
3950 unsigned Hi = Lo + NumElems;
3952 for (unsigned i = 0; i < NumElems; ++i)
3953 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3959 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3960 /// is suitable for input to PSHUFHW.
3961 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3962 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3965 // Lower quadword copied in order or undef.
3966 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3969 // Upper quadword shuffled.
3970 for (unsigned i = 4; i != 8; ++i)
3971 if (!isUndefOrInRange(Mask[i], 4, 8))
3974 if (VT == MVT::v16i16) {
3975 // Lower quadword copied in order or undef.
3976 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3979 // Upper quadword shuffled.
3980 for (unsigned i = 12; i != 16; ++i)
3981 if (!isUndefOrInRange(Mask[i], 12, 16))
3988 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3989 /// is suitable for input to PSHUFLW.
3990 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3991 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3994 // Upper quadword copied in order.
3995 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3998 // Lower quadword shuffled.
3999 for (unsigned i = 0; i != 4; ++i)
4000 if (!isUndefOrInRange(Mask[i], 0, 4))
4003 if (VT == MVT::v16i16) {
4004 // Upper quadword copied in order.
4005 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
4008 // Lower quadword shuffled.
4009 for (unsigned i = 8; i != 12; ++i)
4010 if (!isUndefOrInRange(Mask[i], 8, 12))
4017 /// \brief Return true if the mask specifies a shuffle of elements that is
4018 /// suitable for input to intralane (palignr) or interlane (valign) vector
4020 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4021 unsigned NumElts = VT.getVectorNumElements();
4022 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4023 unsigned NumLaneElts = NumElts/NumLanes;
4025 // Do not handle 64-bit element shuffles with palignr.
4026 if (NumLaneElts == 2)
4029 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4031 for (i = 0; i != NumLaneElts; ++i) {
4036 // Lane is all undef, go to next lane
4037 if (i == NumLaneElts)
4040 int Start = Mask[i+l];
4042 // Make sure its in this lane in one of the sources
4043 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4044 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4047 // If not lane 0, then we must match lane 0
4048 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4051 // Correct second source to be contiguous with first source
4052 if (Start >= (int)NumElts)
4053 Start -= NumElts - NumLaneElts;
4055 // Make sure we're shifting in the right direction.
4056 if (Start <= (int)(i+l))
4061 // Check the rest of the elements to see if they are consecutive.
4062 for (++i; i != NumLaneElts; ++i) {
4063 int Idx = Mask[i+l];
4065 // Make sure its in this lane
4066 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4067 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4070 // If not lane 0, then we must match lane 0
4071 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4074 if (Idx >= (int)NumElts)
4075 Idx -= NumElts - NumLaneElts;
4077 if (!isUndefOrEqual(Idx, Start+i))
4086 /// \brief Return true if the node specifies a shuffle of elements that is
4087 /// suitable for input to PALIGNR.
4088 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4089 const X86Subtarget *Subtarget) {
4090 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4091 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4092 VT.is512BitVector())
4093 // FIXME: Add AVX512BW.
4096 return isAlignrMask(Mask, VT, false);
4099 /// \brief Return true if the node specifies a shuffle of elements that is
4100 /// suitable for input to VALIGN.
4101 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4102 const X86Subtarget *Subtarget) {
4103 // FIXME: Add AVX512VL.
4104 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4106 return isAlignrMask(Mask, VT, true);
4109 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4110 /// the two vector operands have swapped position.
4111 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4112 unsigned NumElems) {
4113 for (unsigned i = 0; i != NumElems; ++i) {
4117 else if (idx < (int)NumElems)
4118 Mask[i] = idx + NumElems;
4120 Mask[i] = idx - NumElems;
4124 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4125 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4126 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4127 /// reverse of what x86 shuffles want.
4128 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4130 unsigned NumElems = VT.getVectorNumElements();
4131 unsigned NumLanes = VT.getSizeInBits()/128;
4132 unsigned NumLaneElems = NumElems/NumLanes;
4134 if (NumLaneElems != 2 && NumLaneElems != 4)
4137 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4138 bool symetricMaskRequired =
4139 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4141 // VSHUFPSY divides the resulting vector into 4 chunks.
4142 // The sources are also splitted into 4 chunks, and each destination
4143 // chunk must come from a different source chunk.
4145 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4146 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4148 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4149 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4151 // VSHUFPDY divides the resulting vector into 4 chunks.
4152 // The sources are also splitted into 4 chunks, and each destination
4153 // chunk must come from a different source chunk.
4155 // SRC1 => X3 X2 X1 X0
4156 // SRC2 => Y3 Y2 Y1 Y0
4158 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4160 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4161 unsigned HalfLaneElems = NumLaneElems/2;
4162 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4163 for (unsigned i = 0; i != NumLaneElems; ++i) {
4164 int Idx = Mask[i+l];
4165 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4166 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4168 // For VSHUFPSY, the mask of the second half must be the same as the
4169 // first but with the appropriate offsets. This works in the same way as
4170 // VPERMILPS works with masks.
4171 if (!symetricMaskRequired || Idx < 0)
4173 if (MaskVal[i] < 0) {
4174 MaskVal[i] = Idx - l;
4177 if ((signed)(Idx - l) != MaskVal[i])
4185 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4186 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4187 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4188 if (!VT.is128BitVector())
4191 unsigned NumElems = VT.getVectorNumElements();
4196 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4197 return isUndefOrEqual(Mask[0], 6) &&
4198 isUndefOrEqual(Mask[1], 7) &&
4199 isUndefOrEqual(Mask[2], 2) &&
4200 isUndefOrEqual(Mask[3], 3);
4203 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4204 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4206 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4207 if (!VT.is128BitVector())
4210 unsigned NumElems = VT.getVectorNumElements();
4215 return isUndefOrEqual(Mask[0], 2) &&
4216 isUndefOrEqual(Mask[1], 3) &&
4217 isUndefOrEqual(Mask[2], 2) &&
4218 isUndefOrEqual(Mask[3], 3);
4221 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4222 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4223 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4224 if (!VT.is128BitVector())
4227 unsigned NumElems = VT.getVectorNumElements();
4229 if (NumElems != 2 && NumElems != 4)
4232 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4233 if (!isUndefOrEqual(Mask[i], i + NumElems))
4236 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4237 if (!isUndefOrEqual(Mask[i], i))
4243 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4244 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4245 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4246 if (!VT.is128BitVector())
4249 unsigned NumElems = VT.getVectorNumElements();
4251 if (NumElems != 2 && NumElems != 4)
4254 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4255 if (!isUndefOrEqual(Mask[i], i))
4258 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4259 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4265 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4266 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4267 /// i. e: If all but one element come from the same vector.
4268 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4269 // TODO: Deal with AVX's VINSERTPS
4270 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4273 unsigned CorrectPosV1 = 0;
4274 unsigned CorrectPosV2 = 0;
4275 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4276 if (Mask[i] == -1) {
4284 else if (Mask[i] == i + 4)
4288 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4289 // We have 3 elements (undefs count as elements from any vector) from one
4290 // vector, and one from another.
4297 // Some special combinations that can be optimized.
4300 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4301 SelectionDAG &DAG) {
4302 MVT VT = SVOp->getSimpleValueType(0);
4305 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4308 ArrayRef<int> Mask = SVOp->getMask();
4310 // These are the special masks that may be optimized.
4311 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4312 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4313 bool MatchEvenMask = true;
4314 bool MatchOddMask = true;
4315 for (int i=0; i<8; ++i) {
4316 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4317 MatchEvenMask = false;
4318 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4319 MatchOddMask = false;
4322 if (!MatchEvenMask && !MatchOddMask)
4325 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4327 SDValue Op0 = SVOp->getOperand(0);
4328 SDValue Op1 = SVOp->getOperand(1);
4330 if (MatchEvenMask) {
4331 // Shift the second operand right to 32 bits.
4332 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4333 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4335 // Shift the first operand left to 32 bits.
4336 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4337 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4339 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4340 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4343 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4344 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4345 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4346 bool HasInt256, bool V2IsSplat = false) {
4348 assert(VT.getSizeInBits() >= 128 &&
4349 "Unsupported vector type for unpckl");
4351 unsigned NumElts = VT.getVectorNumElements();
4352 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4353 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4356 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4357 "Unsupported vector type for unpckh");
4359 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, NumElts))
4373 if (!isUndefOrEqual(BitI1, j + NumElts))
4382 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4383 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4384 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4385 bool HasInt256, bool V2IsSplat = false) {
4386 assert(VT.getSizeInBits() >= 128 &&
4387 "Unsupported vector type for unpckh");
4389 unsigned NumElts = VT.getVectorNumElements();
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4395 "Unsupported vector type for unpckh");
4397 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4398 unsigned NumLanes = VT.getSizeInBits()/128;
4399 unsigned NumLaneElts = NumElts/NumLanes;
4401 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4402 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4403 int BitI = Mask[l+i];
4404 int BitI1 = Mask[l+i+1];
4405 if (!isUndefOrEqual(BitI, j))
4408 if (isUndefOrEqual(BitI1, NumElts))
4411 if (!isUndefOrEqual(BitI1, j+NumElts))
4419 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4420 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4422 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4423 unsigned NumElts = VT.getVectorNumElements();
4424 bool Is256BitVec = VT.is256BitVector();
4426 if (VT.is512BitVector())
4428 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4429 "Unsupported vector type for unpckh");
4431 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4432 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4435 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4436 // FIXME: Need a better way to get rid of this, there's no latency difference
4437 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4438 // the former later. We should also remove the "_undef" special mask.
4439 if (NumElts == 4 && Is256BitVec)
4442 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4443 // independently on 128-bit lanes.
4444 unsigned NumLanes = VT.getSizeInBits()/128;
4445 unsigned NumLaneElts = NumElts/NumLanes;
4447 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4448 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4449 int BitI = Mask[l+i];
4450 int BitI1 = Mask[l+i+1];
4452 if (!isUndefOrEqual(BitI, j))
4454 if (!isUndefOrEqual(BitI1, j))
4462 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4463 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4465 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4466 unsigned NumElts = VT.getVectorNumElements();
4468 if (VT.is512BitVector())
4471 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4472 "Unsupported vector type for unpckh");
4474 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4475 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4478 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4479 // independently on 128-bit lanes.
4480 unsigned NumLanes = VT.getSizeInBits()/128;
4481 unsigned NumLaneElts = NumElts/NumLanes;
4483 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4484 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4485 int BitI = Mask[l+i];
4486 int BitI1 = Mask[l+i+1];
4487 if (!isUndefOrEqual(BitI, j))
4489 if (!isUndefOrEqual(BitI1, j))
4496 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4497 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4498 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4499 if (!VT.is512BitVector())
4502 unsigned NumElts = VT.getVectorNumElements();
4503 unsigned HalfSize = NumElts/2;
4504 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4505 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4510 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4511 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4519 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4520 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4521 /// MOVSD, and MOVD, i.e. setting the lowest element.
4522 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4523 if (VT.getVectorElementType().getSizeInBits() < 32)
4525 if (!VT.is128BitVector())
4528 unsigned NumElts = VT.getVectorNumElements();
4530 if (!isUndefOrEqual(Mask[0], NumElts))
4533 for (unsigned i = 1; i != NumElts; ++i)
4534 if (!isUndefOrEqual(Mask[i], i))
4540 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4541 /// as permutations between 128-bit chunks or halves. As an example: this
4543 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4544 /// The first half comes from the second half of V1 and the second half from the
4545 /// the second half of V2.
4546 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4547 if (!HasFp256 || !VT.is256BitVector())
4550 // The shuffle result is divided into half A and half B. In total the two
4551 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4552 // B must come from C, D, E or F.
4553 unsigned HalfSize = VT.getVectorNumElements()/2;
4554 bool MatchA = false, MatchB = false;
4556 // Check if A comes from one of C, D, E, F.
4557 for (unsigned Half = 0; Half != 4; ++Half) {
4558 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4564 // Check if B comes from one of C, D, E, F.
4565 for (unsigned Half = 0; Half != 4; ++Half) {
4566 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4572 return MatchA && MatchB;
4575 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4576 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4577 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4578 MVT VT = SVOp->getSimpleValueType(0);
4580 unsigned HalfSize = VT.getVectorNumElements()/2;
4582 unsigned FstHalf = 0, SndHalf = 0;
4583 for (unsigned i = 0; i < HalfSize; ++i) {
4584 if (SVOp->getMaskElt(i) > 0) {
4585 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4589 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4590 if (SVOp->getMaskElt(i) > 0) {
4591 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4596 return (FstHalf | (SndHalf << 4));
4599 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4600 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4601 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4605 unsigned NumElts = VT.getVectorNumElements();
4607 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4608 for (unsigned i = 0; i != NumElts; ++i) {
4611 Imm8 |= Mask[i] << (i*2);
4616 unsigned LaneSize = 4;
4617 SmallVector<int, 4> MaskVal(LaneSize, -1);
4619 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4620 for (unsigned i = 0; i != LaneSize; ++i) {
4621 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4625 if (MaskVal[i] < 0) {
4626 MaskVal[i] = Mask[i+l] - l;
4627 Imm8 |= MaskVal[i] << (i*2);
4630 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4637 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4639 /// Note that VPERMIL mask matching is different depending whether theunderlying
4640 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4641 /// to the same elements of the low, but to the higher half of the source.
4642 /// In VPERMILPD the two lanes could be shuffled independently of each other
4643 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4644 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4645 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4646 if (VT.getSizeInBits() < 256 || EltSize < 32)
4648 bool symetricMaskRequired = (EltSize == 32);
4649 unsigned NumElts = VT.getVectorNumElements();
4651 unsigned NumLanes = VT.getSizeInBits()/128;
4652 unsigned LaneSize = NumElts/NumLanes;
4653 // 2 or 4 elements in one lane
4655 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4656 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4657 for (unsigned i = 0; i != LaneSize; ++i) {
4658 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4660 if (symetricMaskRequired) {
4661 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4662 ExpectedMaskVal[i] = Mask[i+l] - l;
4665 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4673 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4674 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4675 /// element of vector 2 and the other elements to come from vector 1 in order.
4676 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4677 bool V2IsSplat = false, bool V2IsUndef = false) {
4678 if (!VT.is128BitVector())
4681 unsigned NumOps = VT.getVectorNumElements();
4682 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4685 if (!isUndefOrEqual(Mask[0], 0))
4688 for (unsigned i = 1; i != NumOps; ++i)
4689 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4690 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4691 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4697 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4698 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4699 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4700 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4701 const X86Subtarget *Subtarget) {
4702 if (!Subtarget->hasSSE3())
4705 unsigned NumElems = VT.getVectorNumElements();
4707 if ((VT.is128BitVector() && NumElems != 4) ||
4708 (VT.is256BitVector() && NumElems != 8) ||
4709 (VT.is512BitVector() && NumElems != 16))
4712 // "i+1" is the value the indexed mask element must have
4713 for (unsigned i = 0; i != NumElems; i += 2)
4714 if (!isUndefOrEqual(Mask[i], i+1) ||
4715 !isUndefOrEqual(Mask[i+1], i+1))
4721 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4722 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4723 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4724 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4725 const X86Subtarget *Subtarget) {
4726 if (!Subtarget->hasSSE3())
4729 unsigned NumElems = VT.getVectorNumElements();
4731 if ((VT.is128BitVector() && NumElems != 4) ||
4732 (VT.is256BitVector() && NumElems != 8) ||
4733 (VT.is512BitVector() && NumElems != 16))
4736 // "i" is the value the indexed mask element must have
4737 for (unsigned i = 0; i != NumElems; i += 2)
4738 if (!isUndefOrEqual(Mask[i], i) ||
4739 !isUndefOrEqual(Mask[i+1], i))
4745 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4746 /// specifies a shuffle of elements that is suitable for input to 256-bit
4747 /// version of MOVDDUP.
4748 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4749 if (!HasFp256 || !VT.is256BitVector())
4752 unsigned NumElts = VT.getVectorNumElements();
4756 for (unsigned i = 0; i != NumElts/2; ++i)
4757 if (!isUndefOrEqual(Mask[i], 0))
4759 for (unsigned i = NumElts/2; i != NumElts; ++i)
4760 if (!isUndefOrEqual(Mask[i], NumElts/2))
4765 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4766 /// specifies a shuffle of elements that is suitable for input to 128-bit
4767 /// version of MOVDDUP.
4768 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4769 if (!VT.is128BitVector())
4772 unsigned e = VT.getVectorNumElements() / 2;
4773 for (unsigned i = 0; i != e; ++i)
4774 if (!isUndefOrEqual(Mask[i], i))
4776 for (unsigned i = 0; i != e; ++i)
4777 if (!isUndefOrEqual(Mask[e+i], i))
4782 /// isVEXTRACTIndex - Return true if the specified
4783 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4784 /// suitable for instruction that extract 128 or 256 bit vectors
4785 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4786 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4787 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4790 // The index should be aligned on a vecWidth-bit boundary.
4792 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4794 MVT VT = N->getSimpleValueType(0);
4795 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4796 bool Result = (Index * ElSize) % vecWidth == 0;
4801 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4802 /// operand specifies a subvector insert that is suitable for input to
4803 /// insertion of 128 or 256-bit subvectors
4804 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4805 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4806 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4808 // The index should be aligned on a vecWidth-bit boundary.
4810 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4812 MVT VT = N->getSimpleValueType(0);
4813 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4814 bool Result = (Index * ElSize) % vecWidth == 0;
4819 bool X86::isVINSERT128Index(SDNode *N) {
4820 return isVINSERTIndex(N, 128);
4823 bool X86::isVINSERT256Index(SDNode *N) {
4824 return isVINSERTIndex(N, 256);
4827 bool X86::isVEXTRACT128Index(SDNode *N) {
4828 return isVEXTRACTIndex(N, 128);
4831 bool X86::isVEXTRACT256Index(SDNode *N) {
4832 return isVEXTRACTIndex(N, 256);
4835 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4836 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4837 /// Handles 128-bit and 256-bit.
4838 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4839 MVT VT = N->getSimpleValueType(0);
4841 assert((VT.getSizeInBits() >= 128) &&
4842 "Unsupported vector type for PSHUF/SHUFP");
4844 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4845 // independently on 128-bit lanes.
4846 unsigned NumElts = VT.getVectorNumElements();
4847 unsigned NumLanes = VT.getSizeInBits()/128;
4848 unsigned NumLaneElts = NumElts/NumLanes;
4850 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4851 "Only supports 2, 4 or 8 elements per lane");
4853 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4855 for (unsigned i = 0; i != NumElts; ++i) {
4856 int Elt = N->getMaskElt(i);
4857 if (Elt < 0) continue;
4858 Elt &= NumLaneElts - 1;
4859 unsigned ShAmt = (i << Shift) % 8;
4860 Mask |= Elt << ShAmt;
4866 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4867 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4868 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4869 MVT VT = N->getSimpleValueType(0);
4871 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4872 "Unsupported vector type for PSHUFHW");
4874 unsigned NumElts = VT.getVectorNumElements();
4877 for (unsigned l = 0; l != NumElts; l += 8) {
4878 // 8 nodes per lane, but we only care about the last 4.
4879 for (unsigned i = 0; i < 4; ++i) {
4880 int Elt = N->getMaskElt(l+i+4);
4881 if (Elt < 0) continue;
4882 Elt &= 0x3; // only 2-bits.
4883 Mask |= Elt << (i * 2);
4890 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4891 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4892 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4893 MVT VT = N->getSimpleValueType(0);
4895 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4896 "Unsupported vector type for PSHUFHW");
4898 unsigned NumElts = VT.getVectorNumElements();
4901 for (unsigned l = 0; l != NumElts; l += 8) {
4902 // 8 nodes per lane, but we only care about the first 4.
4903 for (unsigned i = 0; i < 4; ++i) {
4904 int Elt = N->getMaskElt(l+i);
4905 if (Elt < 0) continue;
4906 Elt &= 0x3; // only 2-bits
4907 Mask |= Elt << (i * 2);
4914 /// \brief Return the appropriate immediate to shuffle the specified
4915 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4916 /// VALIGN (if Interlane is true) instructions.
4917 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4919 MVT VT = SVOp->getSimpleValueType(0);
4920 unsigned EltSize = InterLane ? 1 :
4921 VT.getVectorElementType().getSizeInBits() >> 3;
4923 unsigned NumElts = VT.getVectorNumElements();
4924 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4925 unsigned NumLaneElts = NumElts/NumLanes;
4929 for (i = 0; i != NumElts; ++i) {
4930 Val = SVOp->getMaskElt(i);
4934 if (Val >= (int)NumElts)
4935 Val -= NumElts - NumLaneElts;
4937 assert(Val - i > 0 && "PALIGNR imm should be positive");
4938 return (Val - i) * EltSize;
4941 /// \brief Return the appropriate immediate to shuffle the specified
4942 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4943 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4944 return getShuffleAlignrImmediate(SVOp, false);
4947 /// \brief Return the appropriate immediate to shuffle the specified
4948 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4949 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4950 return getShuffleAlignrImmediate(SVOp, true);
4954 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4955 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4956 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4957 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4960 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4962 MVT VecVT = N->getOperand(0).getSimpleValueType();
4963 MVT ElVT = VecVT.getVectorElementType();
4965 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4966 return Index / NumElemsPerChunk;
4969 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4970 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4971 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4972 llvm_unreachable("Illegal insert subvector for VINSERT");
4975 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4977 MVT VecVT = N->getSimpleValueType(0);
4978 MVT ElVT = VecVT.getVectorElementType();
4980 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4981 return Index / NumElemsPerChunk;
4984 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4985 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4986 /// and VINSERTI128 instructions.
4987 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4988 return getExtractVEXTRACTImmediate(N, 128);
4991 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4992 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4993 /// and VINSERTI64x4 instructions.
4994 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4995 return getExtractVEXTRACTImmediate(N, 256);
4998 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4999 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
5000 /// and VINSERTI128 instructions.
5001 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
5002 return getInsertVINSERTImmediate(N, 128);
5005 /// getInsertVINSERT256Immediate - Return the appropriate immediate
5006 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
5007 /// and VINSERTI64x4 instructions.
5008 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
5009 return getInsertVINSERTImmediate(N, 256);
5012 /// isZero - Returns true if Elt is a constant integer zero
5013 static bool isZero(SDValue V) {
5014 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
5015 return C && C->isNullValue();
5018 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
5020 bool X86::isZeroNode(SDValue Elt) {
5023 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5024 return CFP->getValueAPF().isPosZero();
5028 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5029 /// match movhlps. The lower half elements should come from upper half of
5030 /// V1 (and in order), and the upper half elements should come from the upper
5031 /// half of V2 (and in order).
5032 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5033 if (!VT.is128BitVector())
5035 if (VT.getVectorNumElements() != 4)
5037 for (unsigned i = 0, e = 2; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i+2))
5040 for (unsigned i = 2; i != 4; ++i)
5041 if (!isUndefOrEqual(Mask[i], i+4))
5046 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5047 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5049 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5050 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5052 N = N->getOperand(0).getNode();
5053 if (!ISD::isNON_EXTLoad(N))
5056 *LD = cast<LoadSDNode>(N);
5060 // Test whether the given value is a vector value which will be legalized
5062 static bool WillBeConstantPoolLoad(SDNode *N) {
5063 if (N->getOpcode() != ISD::BUILD_VECTOR)
5066 // Check for any non-constant elements.
5067 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5068 switch (N->getOperand(i).getNode()->getOpcode()) {
5070 case ISD::ConstantFP:
5077 // Vectors of all-zeros and all-ones are materialized with special
5078 // instructions rather than being loaded.
5079 return !ISD::isBuildVectorAllZeros(N) &&
5080 !ISD::isBuildVectorAllOnes(N);
5083 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5084 /// match movlp{s|d}. The lower half elements should come from lower half of
5085 /// V1 (and in order), and the upper half elements should come from the upper
5086 /// half of V2 (and in order). And since V1 will become the source of the
5087 /// MOVLP, it must be either a vector load or a scalar load to vector.
5088 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5089 ArrayRef<int> Mask, MVT VT) {
5090 if (!VT.is128BitVector())
5093 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5095 // Is V2 is a vector load, don't do this transformation. We will try to use
5096 // load folding shufps op.
5097 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5100 unsigned NumElems = VT.getVectorNumElements();
5102 if (NumElems != 2 && NumElems != 4)
5104 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5105 if (!isUndefOrEqual(Mask[i], i))
5107 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5108 if (!isUndefOrEqual(Mask[i], i+NumElems))
5113 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5114 /// to an zero vector.
5115 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5116 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5117 SDValue V1 = N->getOperand(0);
5118 SDValue V2 = N->getOperand(1);
5119 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5120 for (unsigned i = 0; i != NumElems; ++i) {
5121 int Idx = N->getMaskElt(i);
5122 if (Idx >= (int)NumElems) {
5123 unsigned Opc = V2.getOpcode();
5124 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5126 if (Opc != ISD::BUILD_VECTOR ||
5127 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5129 } else if (Idx >= 0) {
5130 unsigned Opc = V1.getOpcode();
5131 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5133 if (Opc != ISD::BUILD_VECTOR ||
5134 !X86::isZeroNode(V1.getOperand(Idx)))
5141 /// getZeroVector - Returns a vector of specified type with all zero elements.
5143 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5144 SelectionDAG &DAG, SDLoc dl) {
5145 assert(VT.isVector() && "Expected a vector type");
5147 // Always build SSE zero vectors as <4 x i32> bitcasted
5148 // to their dest type. This ensures they get CSE'd.
5150 if (VT.is128BitVector()) { // SSE
5151 if (Subtarget->hasSSE2()) { // SSE2
5152 SDValue Cst = DAG.getConstant(0, MVT::i32);
5153 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5155 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5158 } else if (VT.is256BitVector()) { // AVX
5159 if (Subtarget->hasInt256()) { // AVX2
5160 SDValue Cst = DAG.getConstant(0, MVT::i32);
5161 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5162 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5164 // 256-bit logic and arithmetic instructions in AVX are all
5165 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5166 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5167 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5168 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5170 } else if (VT.is512BitVector()) { // AVX-512
5171 SDValue Cst = DAG.getConstant(0, MVT::i32);
5172 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5173 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5175 } else if (VT.getScalarType() == MVT::i1) {
5176 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5177 SDValue Cst = DAG.getConstant(0, MVT::i1);
5178 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5179 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5181 llvm_unreachable("Unexpected vector type");
5183 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5186 /// getOnesVector - Returns a vector of specified type with all bits set.
5187 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5188 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5189 /// Then bitcast to their original type, ensuring they get CSE'd.
5190 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5192 assert(VT.isVector() && "Expected a vector type");
5194 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5196 if (VT.is256BitVector()) {
5197 if (HasInt256) { // AVX2
5198 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5199 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5201 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5202 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5204 } else if (VT.is128BitVector()) {
5205 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5207 llvm_unreachable("Unexpected vector type");
5209 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5212 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5213 /// that point to V2 points to its first element.
5214 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5215 for (unsigned i = 0; i != NumElems; ++i) {
5216 if (Mask[i] > (int)NumElems) {
5222 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5223 /// operation of specified width.
5224 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5226 unsigned NumElems = VT.getVectorNumElements();
5227 SmallVector<int, 8> Mask;
5228 Mask.push_back(NumElems);
5229 for (unsigned i = 1; i != NumElems; ++i)
5231 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5234 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5235 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5237 unsigned NumElems = VT.getVectorNumElements();
5238 SmallVector<int, 8> Mask;
5239 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5241 Mask.push_back(i + NumElems);
5243 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5246 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5247 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5249 unsigned NumElems = VT.getVectorNumElements();
5250 SmallVector<int, 8> Mask;
5251 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5252 Mask.push_back(i + Half);
5253 Mask.push_back(i + NumElems + Half);
5255 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5258 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5259 // a generic shuffle instruction because the target has no such instructions.
5260 // Generate shuffles which repeat i16 and i8 several times until they can be
5261 // represented by v4f32 and then be manipulated by target suported shuffles.
5262 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5263 MVT VT = V.getSimpleValueType();
5264 int NumElems = VT.getVectorNumElements();
5267 while (NumElems > 4) {
5268 if (EltNo < NumElems/2) {
5269 V = getUnpackl(DAG, dl, VT, V, V);
5271 V = getUnpackh(DAG, dl, VT, V, V);
5272 EltNo -= NumElems/2;
5279 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5280 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5281 MVT VT = V.getSimpleValueType();
5284 if (VT.is128BitVector()) {
5285 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5286 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5287 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5289 } else if (VT.is256BitVector()) {
5290 // To use VPERMILPS to splat scalars, the second half of indicies must
5291 // refer to the higher part, which is a duplication of the lower one,
5292 // because VPERMILPS can only handle in-lane permutations.
5293 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5294 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5296 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5297 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5300 llvm_unreachable("Vector size not supported");
5302 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5305 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5306 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5307 MVT SrcVT = SV->getSimpleValueType(0);
5308 SDValue V1 = SV->getOperand(0);
5311 int EltNo = SV->getSplatIndex();
5312 int NumElems = SrcVT.getVectorNumElements();
5313 bool Is256BitVec = SrcVT.is256BitVector();
5315 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5316 "Unknown how to promote splat for type");
5318 // Extract the 128-bit part containing the splat element and update
5319 // the splat element index when it refers to the higher register.
5321 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5322 if (EltNo >= NumElems/2)
5323 EltNo -= NumElems/2;
5326 // All i16 and i8 vector types can't be used directly by a generic shuffle
5327 // instruction because the target has no such instruction. Generate shuffles
5328 // which repeat i16 and i8 several times until they fit in i32, and then can
5329 // be manipulated by target suported shuffles.
5330 MVT EltVT = SrcVT.getVectorElementType();
5331 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5332 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5334 // Recreate the 256-bit vector and place the same 128-bit vector
5335 // into the low and high part. This is necessary because we want
5336 // to use VPERM* to shuffle the vectors
5338 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5341 return getLegalSplat(DAG, V1, EltNo);
5344 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5345 /// vector of zero or undef vector. This produces a shuffle where the low
5346 /// element of V2 is swizzled into the zero/undef vector, landing at element
5347 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5348 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5350 const X86Subtarget *Subtarget,
5351 SelectionDAG &DAG) {
5352 MVT VT = V2.getSimpleValueType();
5354 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5355 unsigned NumElems = VT.getVectorNumElements();
5356 SmallVector<int, 16> MaskVec;
5357 for (unsigned i = 0; i != NumElems; ++i)
5358 // If this is the insertion idx, put the low elt of V2 here.
5359 MaskVec.push_back(i == Idx ? NumElems : i);
5360 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5363 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5364 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5365 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5366 /// shuffles which use a single input multiple times, and in those cases it will
5367 /// adjust the mask to only have indices within that single input.
5368 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5369 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5370 unsigned NumElems = VT.getVectorNumElements();
5374 bool IsFakeUnary = false;
5375 switch(N->getOpcode()) {
5376 case X86ISD::BLENDI:
5377 ImmN = N->getOperand(N->getNumOperands()-1);
5378 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5381 ImmN = N->getOperand(N->getNumOperands()-1);
5382 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5383 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5385 case X86ISD::UNPCKH:
5386 DecodeUNPCKHMask(VT, Mask);
5387 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5389 case X86ISD::UNPCKL:
5390 DecodeUNPCKLMask(VT, Mask);
5391 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5393 case X86ISD::MOVHLPS:
5394 DecodeMOVHLPSMask(NumElems, Mask);
5395 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5397 case X86ISD::MOVLHPS:
5398 DecodeMOVLHPSMask(NumElems, Mask);
5399 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5401 case X86ISD::PALIGNR:
5402 ImmN = N->getOperand(N->getNumOperands()-1);
5403 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5405 case X86ISD::PSHUFD:
5406 case X86ISD::VPERMILPI:
5407 ImmN = N->getOperand(N->getNumOperands()-1);
5408 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5411 case X86ISD::PSHUFHW:
5412 ImmN = N->getOperand(N->getNumOperands()-1);
5413 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5416 case X86ISD::PSHUFLW:
5417 ImmN = N->getOperand(N->getNumOperands()-1);
5418 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5421 case X86ISD::PSHUFB: {
5423 SDValue MaskNode = N->getOperand(1);
5424 while (MaskNode->getOpcode() == ISD::BITCAST)
5425 MaskNode = MaskNode->getOperand(0);
5427 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5428 // If we have a build-vector, then things are easy.
5429 EVT VT = MaskNode.getValueType();
5430 assert(VT.isVector() &&
5431 "Can't produce a non-vector with a build_vector!");
5432 if (!VT.isInteger())
5435 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5437 SmallVector<uint64_t, 32> RawMask;
5438 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5439 SDValue Op = MaskNode->getOperand(i);
5440 if (Op->getOpcode() == ISD::UNDEF) {
5441 RawMask.push_back((uint64_t)SM_SentinelUndef);
5444 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5447 APInt MaskElement = CN->getAPIntValue();
5449 // We now have to decode the element which could be any integer size and
5450 // extract each byte of it.
5451 for (int j = 0; j < NumBytesPerElement; ++j) {
5452 // Note that this is x86 and so always little endian: the low byte is
5453 // the first byte of the mask.
5454 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5455 MaskElement = MaskElement.lshr(8);
5458 DecodePSHUFBMask(RawMask, Mask);
5462 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5466 SDValue Ptr = MaskLoad->getBasePtr();
5467 if (Ptr->getOpcode() == X86ISD::Wrapper)
5468 Ptr = Ptr->getOperand(0);
5470 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5471 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5474 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5475 DecodePSHUFBMask(C, Mask);
5481 case X86ISD::VPERMI:
5482 ImmN = N->getOperand(N->getNumOperands()-1);
5483 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5487 case X86ISD::MOVSD: {
5488 // The index 0 always comes from the first element of the second source,
5489 // this is why MOVSS and MOVSD are used in the first place. The other
5490 // elements come from the other positions of the first source vector
5491 Mask.push_back(NumElems);
5492 for (unsigned i = 1; i != NumElems; ++i) {
5497 case X86ISD::VPERM2X128:
5498 ImmN = N->getOperand(N->getNumOperands()-1);
5499 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5500 if (Mask.empty()) return false;
5502 case X86ISD::MOVSLDUP:
5503 DecodeMOVSLDUPMask(VT, Mask);
5505 case X86ISD::MOVSHDUP:
5506 DecodeMOVSHDUPMask(VT, Mask);
5508 case X86ISD::MOVDDUP:
5509 case X86ISD::MOVLHPD:
5510 case X86ISD::MOVLPD:
5511 case X86ISD::MOVLPS:
5512 // Not yet implemented
5514 default: llvm_unreachable("unknown target shuffle node");
5517 // If we have a fake unary shuffle, the shuffle mask is spread across two
5518 // inputs that are actually the same node. Re-map the mask to always point
5519 // into the first input.
5522 if (M >= (int)Mask.size())
5528 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5529 /// element of the result of the vector shuffle.
5530 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5533 return SDValue(); // Limit search depth.
5535 SDValue V = SDValue(N, 0);
5536 EVT VT = V.getValueType();
5537 unsigned Opcode = V.getOpcode();
5539 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5540 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5541 int Elt = SV->getMaskElt(Index);
5544 return DAG.getUNDEF(VT.getVectorElementType());
5546 unsigned NumElems = VT.getVectorNumElements();
5547 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5548 : SV->getOperand(1);
5549 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5552 // Recurse into target specific vector shuffles to find scalars.
5553 if (isTargetShuffle(Opcode)) {
5554 MVT ShufVT = V.getSimpleValueType();
5555 unsigned NumElems = ShufVT.getVectorNumElements();
5556 SmallVector<int, 16> ShuffleMask;
5559 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5562 int Elt = ShuffleMask[Index];
5564 return DAG.getUNDEF(ShufVT.getVectorElementType());
5566 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5568 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5572 // Actual nodes that may contain scalar elements
5573 if (Opcode == ISD::BITCAST) {
5574 V = V.getOperand(0);
5575 EVT SrcVT = V.getValueType();
5576 unsigned NumElems = VT.getVectorNumElements();
5578 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5582 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5583 return (Index == 0) ? V.getOperand(0)
5584 : DAG.getUNDEF(VT.getVectorElementType());
5586 if (V.getOpcode() == ISD::BUILD_VECTOR)
5587 return V.getOperand(Index);
5592 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5593 /// shuffle operation which come from a consecutively from a zero. The
5594 /// search can start in two different directions, from left or right.
5595 /// We count undefs as zeros until PreferredNum is reached.
5596 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5597 unsigned NumElems, bool ZerosFromLeft,
5599 unsigned PreferredNum = -1U) {
5600 unsigned NumZeros = 0;
5601 for (unsigned i = 0; i != NumElems; ++i) {
5602 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5603 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5607 if (X86::isZeroNode(Elt))
5609 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5610 NumZeros = std::min(NumZeros + 1, PreferredNum);
5618 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5619 /// correspond consecutively to elements from one of the vector operands,
5620 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5622 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5623 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5624 unsigned NumElems, unsigned &OpNum) {
5625 bool SeenV1 = false;
5626 bool SeenV2 = false;
5628 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5629 int Idx = SVOp->getMaskElt(i);
5630 // Ignore undef indicies
5634 if (Idx < (int)NumElems)
5639 // Only accept consecutive elements from the same vector
5640 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5644 OpNum = SeenV1 ? 0 : 1;
5648 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5649 /// logical left shift of a vector.
5650 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5651 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5653 SVOp->getSimpleValueType(0).getVectorNumElements();
5654 unsigned NumZeros = getNumOfConsecutiveZeros(
5655 SVOp, NumElems, false /* check zeros from right */, DAG,
5656 SVOp->getMaskElt(0));
5662 // Considering the elements in the mask that are not consecutive zeros,
5663 // check if they consecutively come from only one of the source vectors.
5665 // V1 = {X, A, B, C} 0
5667 // vector_shuffle V1, V2 <1, 2, 3, X>
5669 if (!isShuffleMaskConsecutive(SVOp,
5670 0, // Mask Start Index
5671 NumElems-NumZeros, // Mask End Index(exclusive)
5672 NumZeros, // Where to start looking in the src vector
5673 NumElems, // Number of elements in vector
5674 OpSrc)) // Which source operand ?
5679 ShVal = SVOp->getOperand(OpSrc);
5683 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5684 /// logical left shift of a vector.
5685 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5686 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5688 SVOp->getSimpleValueType(0).getVectorNumElements();
5689 unsigned NumZeros = getNumOfConsecutiveZeros(
5690 SVOp, NumElems, true /* check zeros from left */, DAG,
5691 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5697 // Considering the elements in the mask that are not consecutive zeros,
5698 // check if they consecutively come from only one of the source vectors.
5700 // 0 { A, B, X, X } = V2
5702 // vector_shuffle V1, V2 <X, X, 4, 5>
5704 if (!isShuffleMaskConsecutive(SVOp,
5705 NumZeros, // Mask Start Index
5706 NumElems, // Mask End Index(exclusive)
5707 0, // Where to start looking in the src vector
5708 NumElems, // Number of elements in vector
5709 OpSrc)) // Which source operand ?
5714 ShVal = SVOp->getOperand(OpSrc);
5718 /// isVectorShift - Returns true if the shuffle can be implemented as a
5719 /// logical left or right shift of a vector.
5720 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5721 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5722 // Although the logic below support any bitwidth size, there are no
5723 // shift instructions which handle more than 128-bit vectors.
5724 if (!SVOp->getSimpleValueType(0).is128BitVector())
5727 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5728 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5734 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5736 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5737 unsigned NumNonZero, unsigned NumZero,
5739 const X86Subtarget* Subtarget,
5740 const TargetLowering &TLI) {
5747 for (unsigned i = 0; i < 16; ++i) {
5748 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5749 if (ThisIsNonZero && First) {
5751 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5753 V = DAG.getUNDEF(MVT::v8i16);
5758 SDValue ThisElt, LastElt;
5759 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5760 if (LastIsNonZero) {
5761 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5762 MVT::i16, Op.getOperand(i-1));
5764 if (ThisIsNonZero) {
5765 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5766 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5767 ThisElt, DAG.getConstant(8, MVT::i8));
5769 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5773 if (ThisElt.getNode())
5774 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5775 DAG.getIntPtrConstant(i/2));
5779 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5782 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5784 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5785 unsigned NumNonZero, unsigned NumZero,
5787 const X86Subtarget* Subtarget,
5788 const TargetLowering &TLI) {
5795 for (unsigned i = 0; i < 8; ++i) {
5796 bool isNonZero = (NonZeros & (1 << i)) != 0;
5800 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5802 V = DAG.getUNDEF(MVT::v8i16);
5805 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5806 MVT::v8i16, V, Op.getOperand(i),
5807 DAG.getIntPtrConstant(i));
5814 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5815 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5816 const X86Subtarget *Subtarget,
5817 const TargetLowering &TLI) {
5818 // Find all zeroable elements.
5820 for (int i=0; i < 4; ++i) {
5821 SDValue Elt = Op->getOperand(i);
5822 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5824 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5825 [](bool M) { return !M; }) > 1 &&
5826 "We expect at least two non-zero elements!");
5828 // We only know how to deal with build_vector nodes where elements are either
5829 // zeroable or extract_vector_elt with constant index.
5830 SDValue FirstNonZero;
5831 unsigned FirstNonZeroIdx;
5832 for (unsigned i=0; i < 4; ++i) {
5835 SDValue Elt = Op->getOperand(i);
5836 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5837 !isa<ConstantSDNode>(Elt.getOperand(1)))
5839 // Make sure that this node is extracting from a 128-bit vector.
5840 MVT VT = Elt.getOperand(0).getSimpleValueType();
5841 if (!VT.is128BitVector())
5843 if (!FirstNonZero.getNode()) {
5845 FirstNonZeroIdx = i;
5849 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5850 SDValue V1 = FirstNonZero.getOperand(0);
5851 MVT VT = V1.getSimpleValueType();
5853 // See if this build_vector can be lowered as a blend with zero.
5855 unsigned EltMaskIdx, EltIdx;
5857 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5858 if (Zeroable[EltIdx]) {
5859 // The zero vector will be on the right hand side.
5860 Mask[EltIdx] = EltIdx+4;
5864 Elt = Op->getOperand(EltIdx);
5865 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5866 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5867 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5869 Mask[EltIdx] = EltIdx;
5873 // Let the shuffle legalizer deal with blend operations.
5874 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5875 if (V1.getSimpleValueType() != VT)
5876 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5877 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5880 // See if we can lower this build_vector to a INSERTPS.
5881 if (!Subtarget->hasSSE41())
5884 SDValue V2 = Elt.getOperand(0);
5885 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5888 bool CanFold = true;
5889 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5893 SDValue Current = Op->getOperand(i);
5894 SDValue SrcVector = Current->getOperand(0);
5897 CanFold = SrcVector == V1 &&
5898 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5904 assert(V1.getNode() && "Expected at least two non-zero elements!");
5905 if (V1.getSimpleValueType() != MVT::v4f32)
5906 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5907 if (V2.getSimpleValueType() != MVT::v4f32)
5908 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5910 // Ok, we can emit an INSERTPS instruction.
5912 for (int i = 0; i < 4; ++i)
5916 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5917 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5918 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5919 DAG.getIntPtrConstant(InsertPSMask));
5920 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5923 /// getVShift - Return a vector logical shift node.
5925 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5926 unsigned NumBits, SelectionDAG &DAG,
5927 const TargetLowering &TLI, SDLoc dl) {
5928 assert(VT.is128BitVector() && "Unknown type for VShift");
5929 EVT ShVT = MVT::v2i64;
5930 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5931 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5932 return DAG.getNode(ISD::BITCAST, dl, VT,
5933 DAG.getNode(Opc, dl, ShVT, SrcOp,
5934 DAG.getConstant(NumBits,
5935 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5939 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5941 // Check if the scalar load can be widened into a vector load. And if
5942 // the address is "base + cst" see if the cst can be "absorbed" into
5943 // the shuffle mask.
5944 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5945 SDValue Ptr = LD->getBasePtr();
5946 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5948 EVT PVT = LD->getValueType(0);
5949 if (PVT != MVT::i32 && PVT != MVT::f32)
5954 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5955 FI = FINode->getIndex();
5957 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5958 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5959 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5960 Offset = Ptr.getConstantOperandVal(1);
5961 Ptr = Ptr.getOperand(0);
5966 // FIXME: 256-bit vector instructions don't require a strict alignment,
5967 // improve this code to support it better.
5968 unsigned RequiredAlign = VT.getSizeInBits()/8;
5969 SDValue Chain = LD->getChain();
5970 // Make sure the stack object alignment is at least 16 or 32.
5971 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5972 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5973 if (MFI->isFixedObjectIndex(FI)) {
5974 // Can't change the alignment. FIXME: It's possible to compute
5975 // the exact stack offset and reference FI + adjust offset instead.
5976 // If someone *really* cares about this. That's the way to implement it.
5979 MFI->setObjectAlignment(FI, RequiredAlign);
5983 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5984 // Ptr + (Offset & ~15).
5987 if ((Offset % RequiredAlign) & 3)
5989 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5991 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5992 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5994 int EltNo = (Offset - StartOffset) >> 2;
5995 unsigned NumElems = VT.getVectorNumElements();
5997 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5998 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5999 LD->getPointerInfo().getWithOffset(StartOffset),
6000 false, false, false, 0);
6002 SmallVector<int, 8> Mask;
6003 for (unsigned i = 0; i != NumElems; ++i)
6004 Mask.push_back(EltNo);
6006 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
6012 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
6013 /// vector of type 'VT', see if the elements can be replaced by a single large
6014 /// load which has the same value as a build_vector whose operands are 'elts'.
6016 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6018 /// FIXME: we'd also like to handle the case where the last elements are zero
6019 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6020 /// There's even a handy isZeroNode for that purpose.
6021 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6022 SDLoc &DL, SelectionDAG &DAG,
6023 bool isAfterLegalize) {
6024 EVT EltVT = VT.getVectorElementType();
6025 unsigned NumElems = Elts.size();
6027 LoadSDNode *LDBase = nullptr;
6028 unsigned LastLoadedElt = -1U;
6030 // For each element in the initializer, see if we've found a load or an undef.
6031 // If we don't find an initial load element, or later load elements are
6032 // non-consecutive, bail out.
6033 for (unsigned i = 0; i < NumElems; ++i) {
6034 SDValue Elt = Elts[i];
6036 if (!Elt.getNode() ||
6037 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6040 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6042 LDBase = cast<LoadSDNode>(Elt.getNode());
6046 if (Elt.getOpcode() == ISD::UNDEF)
6049 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6050 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6055 // If we have found an entire vector of loads and undefs, then return a large
6056 // load of the entire vector width starting at the base pointer. If we found
6057 // consecutive loads for the low half, generate a vzext_load node.
6058 if (LastLoadedElt == NumElems - 1) {
6060 if (isAfterLegalize &&
6061 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6064 SDValue NewLd = SDValue();
6066 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6067 LDBase->getPointerInfo(), LDBase->isVolatile(),
6068 LDBase->isNonTemporal(), LDBase->isInvariant(),
6069 LDBase->getAlignment());
6071 if (LDBase->hasAnyUseOfValue(1)) {
6072 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6074 SDValue(NewLd.getNode(), 1));
6075 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6076 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6077 SDValue(NewLd.getNode(), 1));
6083 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6084 //of a v4i32 / v4f32. It's probably worth generalizing.
6085 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6086 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6087 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6088 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6090 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6091 LDBase->getPointerInfo(),
6092 LDBase->getAlignment(),
6093 false/*isVolatile*/, true/*ReadMem*/,
6096 // Make sure the newly-created LOAD is in the same position as LDBase in
6097 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6098 // update uses of LDBase's output chain to use the TokenFactor.
6099 if (LDBase->hasAnyUseOfValue(1)) {
6100 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6101 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6102 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6103 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6104 SDValue(ResNode.getNode(), 1));
6107 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6112 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6113 /// to generate a splat value for the following cases:
6114 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6115 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6116 /// a scalar load, or a constant.
6117 /// The VBROADCAST node is returned when a pattern is found,
6118 /// or SDValue() otherwise.
6119 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6120 SelectionDAG &DAG) {
6121 // VBROADCAST requires AVX.
6122 // TODO: Splats could be generated for non-AVX CPUs using SSE
6123 // instructions, but there's less potential gain for only 128-bit vectors.
6124 if (!Subtarget->hasAVX())
6127 MVT VT = Op.getSimpleValueType();
6130 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6131 "Unsupported vector type for broadcast.");
6136 switch (Op.getOpcode()) {
6138 // Unknown pattern found.
6141 case ISD::BUILD_VECTOR: {
6142 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6143 BitVector UndefElements;
6144 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6146 // We need a splat of a single value to use broadcast, and it doesn't
6147 // make any sense if the value is only in one element of the vector.
6148 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6152 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6153 Ld.getOpcode() == ISD::ConstantFP);
6155 // Make sure that all of the users of a non-constant load are from the
6156 // BUILD_VECTOR node.
6157 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6162 case ISD::VECTOR_SHUFFLE: {
6163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6165 // Shuffles must have a splat mask where the first element is
6167 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6170 SDValue Sc = Op.getOperand(0);
6171 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6172 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6174 if (!Subtarget->hasInt256())
6177 // Use the register form of the broadcast instruction available on AVX2.
6178 if (VT.getSizeInBits() >= 256)
6179 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6180 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6183 Ld = Sc.getOperand(0);
6184 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6185 Ld.getOpcode() == ISD::ConstantFP);
6187 // The scalar_to_vector node and the suspected
6188 // load node must have exactly one user.
6189 // Constants may have multiple users.
6191 // AVX-512 has register version of the broadcast
6192 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6193 Ld.getValueType().getSizeInBits() >= 32;
6194 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6201 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6202 bool IsGE256 = (VT.getSizeInBits() >= 256);
6204 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6205 // instruction to save 8 or more bytes of constant pool data.
6206 // TODO: If multiple splats are generated to load the same constant,
6207 // it may be detrimental to overall size. There needs to be a way to detect
6208 // that condition to know if this is truly a size win.
6209 const Function *F = DAG.getMachineFunction().getFunction();
6210 bool OptForSize = F->getAttributes().
6211 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6213 // Handle broadcasting a single constant scalar from the constant pool
6215 // On Sandybridge (no AVX2), it is still better to load a constant vector
6216 // from the constant pool and not to broadcast it from a scalar.
6217 // But override that restriction when optimizing for size.
6218 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6219 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6220 EVT CVT = Ld.getValueType();
6221 assert(!CVT.isVector() && "Must not broadcast a vector type");
6223 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6224 // For size optimization, also splat v2f64 and v2i64, and for size opt
6225 // with AVX2, also splat i8 and i16.
6226 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6227 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6228 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6229 const Constant *C = nullptr;
6230 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6231 C = CI->getConstantIntValue();
6232 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6233 C = CF->getConstantFPValue();
6235 assert(C && "Invalid constant type");
6237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6238 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6239 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6240 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6241 MachinePointerInfo::getConstantPool(),
6242 false, false, false, Alignment);
6244 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6248 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6250 // Handle AVX2 in-register broadcasts.
6251 if (!IsLoad && Subtarget->hasInt256() &&
6252 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6253 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6255 // The scalar source must be a normal load.
6259 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6260 (Subtarget->hasVLX() && ScalarSize == 64))
6261 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6263 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6264 // double since there is no vbroadcastsd xmm
6265 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6266 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6267 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6270 // Unsupported broadcast.
6274 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6275 /// underlying vector and index.
6277 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6279 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6281 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6282 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6285 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6287 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6289 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6290 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6293 // In this case the vector is the extract_subvector expression and the index
6294 // is 2, as specified by the shuffle.
6295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6296 SDValue ShuffleVec = SVOp->getOperand(0);
6297 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6298 assert(ShuffleVecVT.getVectorElementType() ==
6299 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6301 int ShuffleIdx = SVOp->getMaskElt(Idx);
6302 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6303 ExtractedFromVec = ShuffleVec;
6309 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6310 MVT VT = Op.getSimpleValueType();
6312 // Skip if insert_vec_elt is not supported.
6313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6314 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6318 unsigned NumElems = Op.getNumOperands();
6322 SmallVector<unsigned, 4> InsertIndices;
6323 SmallVector<int, 8> Mask(NumElems, -1);
6325 for (unsigned i = 0; i != NumElems; ++i) {
6326 unsigned Opc = Op.getOperand(i).getOpcode();
6328 if (Opc == ISD::UNDEF)
6331 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6332 // Quit if more than 1 elements need inserting.
6333 if (InsertIndices.size() > 1)
6336 InsertIndices.push_back(i);
6340 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6341 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6342 // Quit if non-constant index.
6343 if (!isa<ConstantSDNode>(ExtIdx))
6345 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6347 // Quit if extracted from vector of different type.
6348 if (ExtractedFromVec.getValueType() != VT)
6351 if (!VecIn1.getNode())
6352 VecIn1 = ExtractedFromVec;
6353 else if (VecIn1 != ExtractedFromVec) {
6354 if (!VecIn2.getNode())
6355 VecIn2 = ExtractedFromVec;
6356 else if (VecIn2 != ExtractedFromVec)
6357 // Quit if more than 2 vectors to shuffle
6361 if (ExtractedFromVec == VecIn1)
6363 else if (ExtractedFromVec == VecIn2)
6364 Mask[i] = Idx + NumElems;
6367 if (!VecIn1.getNode())
6370 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6371 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6372 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6373 unsigned Idx = InsertIndices[i];
6374 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6375 DAG.getIntPtrConstant(Idx));
6381 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6383 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6385 MVT VT = Op.getSimpleValueType();
6386 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6387 "Unexpected type in LowerBUILD_VECTORvXi1!");
6390 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6391 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6392 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6393 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6396 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6397 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6398 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6399 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6402 bool AllContants = true;
6403 uint64_t Immediate = 0;
6404 int NonConstIdx = -1;
6405 bool IsSplat = true;
6406 unsigned NumNonConsts = 0;
6407 unsigned NumConsts = 0;
6408 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6409 SDValue In = Op.getOperand(idx);
6410 if (In.getOpcode() == ISD::UNDEF)
6412 if (!isa<ConstantSDNode>(In)) {
6413 AllContants = false;
6418 if (cast<ConstantSDNode>(In)->getZExtValue())
6419 Immediate |= (1ULL << idx);
6421 if (In != Op.getOperand(0))
6426 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6427 DAG.getConstant(Immediate, MVT::i16));
6428 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6429 DAG.getIntPtrConstant(0));
6432 if (NumNonConsts == 1 && NonConstIdx != 0) {
6435 SDValue VecAsImm = DAG.getConstant(Immediate,
6436 MVT::getIntegerVT(VT.getSizeInBits()));
6437 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6440 DstVec = DAG.getUNDEF(VT);
6441 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6442 Op.getOperand(NonConstIdx),
6443 DAG.getIntPtrConstant(NonConstIdx));
6445 if (!IsSplat && (NonConstIdx != 0))
6446 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6447 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6450 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6451 DAG.getConstant(-1, SelectVT),
6452 DAG.getConstant(0, SelectVT));
6454 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6455 DAG.getConstant((Immediate | 1), SelectVT),
6456 DAG.getConstant(Immediate, SelectVT));
6457 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6460 /// \brief Return true if \p N implements a horizontal binop and return the
6461 /// operands for the horizontal binop into V0 and V1.
6463 /// This is a helper function of PerformBUILD_VECTORCombine.
6464 /// This function checks that the build_vector \p N in input implements a
6465 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6466 /// operation to match.
6467 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6468 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6469 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6472 /// This function only analyzes elements of \p N whose indices are
6473 /// in range [BaseIdx, LastIdx).
6474 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6476 unsigned BaseIdx, unsigned LastIdx,
6477 SDValue &V0, SDValue &V1) {
6478 EVT VT = N->getValueType(0);
6480 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6481 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6482 "Invalid Vector in input!");
6484 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6485 bool CanFold = true;
6486 unsigned ExpectedVExtractIdx = BaseIdx;
6487 unsigned NumElts = LastIdx - BaseIdx;
6488 V0 = DAG.getUNDEF(VT);
6489 V1 = DAG.getUNDEF(VT);
6491 // Check if N implements a horizontal binop.
6492 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6493 SDValue Op = N->getOperand(i + BaseIdx);
6496 if (Op->getOpcode() == ISD::UNDEF) {
6497 // Update the expected vector extract index.
6498 if (i * 2 == NumElts)
6499 ExpectedVExtractIdx = BaseIdx;
6500 ExpectedVExtractIdx += 2;
6504 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6509 SDValue Op0 = Op.getOperand(0);
6510 SDValue Op1 = Op.getOperand(1);
6512 // Try to match the following pattern:
6513 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6514 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6515 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6516 Op0.getOperand(0) == Op1.getOperand(0) &&
6517 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6518 isa<ConstantSDNode>(Op1.getOperand(1)));
6522 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6523 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6525 if (i * 2 < NumElts) {
6526 if (V0.getOpcode() == ISD::UNDEF)
6527 V0 = Op0.getOperand(0);
6529 if (V1.getOpcode() == ISD::UNDEF)
6530 V1 = Op0.getOperand(0);
6531 if (i * 2 == NumElts)
6532 ExpectedVExtractIdx = BaseIdx;
6535 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6536 if (I0 == ExpectedVExtractIdx)
6537 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6538 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6539 // Try to match the following dag sequence:
6540 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6541 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6545 ExpectedVExtractIdx += 2;
6551 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6552 /// a concat_vector.
6554 /// This is a helper function of PerformBUILD_VECTORCombine.
6555 /// This function expects two 256-bit vectors called V0 and V1.
6556 /// At first, each vector is split into two separate 128-bit vectors.
6557 /// Then, the resulting 128-bit vectors are used to implement two
6558 /// horizontal binary operations.
6560 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6562 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6563 /// the two new horizontal binop.
6564 /// When Mode is set, the first horizontal binop dag node would take as input
6565 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6566 /// horizontal binop dag node would take as input the lower 128-bit of V1
6567 /// and the upper 128-bit of V1.
6569 /// HADD V0_LO, V0_HI
6570 /// HADD V1_LO, V1_HI
6572 /// Otherwise, the first horizontal binop dag node takes as input the lower
6573 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6574 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6576 /// HADD V0_LO, V1_LO
6577 /// HADD V0_HI, V1_HI
6579 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6580 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6581 /// the upper 128-bits of the result.
6582 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6583 SDLoc DL, SelectionDAG &DAG,
6584 unsigned X86Opcode, bool Mode,
6585 bool isUndefLO, bool isUndefHI) {
6586 EVT VT = V0.getValueType();
6587 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6588 "Invalid nodes in input!");
6590 unsigned NumElts = VT.getVectorNumElements();
6591 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6592 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6593 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6594 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6595 EVT NewVT = V0_LO.getValueType();
6597 SDValue LO = DAG.getUNDEF(NewVT);
6598 SDValue HI = DAG.getUNDEF(NewVT);
6601 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6602 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6603 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6604 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6605 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6607 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6608 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6609 V1_LO->getOpcode() != ISD::UNDEF))
6610 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6612 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6613 V1_HI->getOpcode() != ISD::UNDEF))
6614 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6617 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6620 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6621 /// sequence of 'vadd + vsub + blendi'.
6622 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6623 const X86Subtarget *Subtarget) {
6625 EVT VT = BV->getValueType(0);
6626 unsigned NumElts = VT.getVectorNumElements();
6627 SDValue InVec0 = DAG.getUNDEF(VT);
6628 SDValue InVec1 = DAG.getUNDEF(VT);
6630 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6631 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6633 // Odd-numbered elements in the input build vector are obtained from
6634 // adding two integer/float elements.
6635 // Even-numbered elements in the input build vector are obtained from
6636 // subtracting two integer/float elements.
6637 unsigned ExpectedOpcode = ISD::FSUB;
6638 unsigned NextExpectedOpcode = ISD::FADD;
6639 bool AddFound = false;
6640 bool SubFound = false;
6642 for (unsigned i = 0, e = NumElts; i != e; i++) {
6643 SDValue Op = BV->getOperand(i);
6645 // Skip 'undef' values.
6646 unsigned Opcode = Op.getOpcode();
6647 if (Opcode == ISD::UNDEF) {
6648 std::swap(ExpectedOpcode, NextExpectedOpcode);
6652 // Early exit if we found an unexpected opcode.
6653 if (Opcode != ExpectedOpcode)
6656 SDValue Op0 = Op.getOperand(0);
6657 SDValue Op1 = Op.getOperand(1);
6659 // Try to match the following pattern:
6660 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6661 // Early exit if we cannot match that sequence.
6662 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6663 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6664 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6665 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6666 Op0.getOperand(1) != Op1.getOperand(1))
6669 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6673 // We found a valid add/sub node. Update the information accordingly.
6679 // Update InVec0 and InVec1.
6680 if (InVec0.getOpcode() == ISD::UNDEF)
6681 InVec0 = Op0.getOperand(0);
6682 if (InVec1.getOpcode() == ISD::UNDEF)
6683 InVec1 = Op1.getOperand(0);
6685 // Make sure that operands in input to each add/sub node always
6686 // come from a same pair of vectors.
6687 if (InVec0 != Op0.getOperand(0)) {
6688 if (ExpectedOpcode == ISD::FSUB)
6691 // FADD is commutable. Try to commute the operands
6692 // and then test again.
6693 std::swap(Op0, Op1);
6694 if (InVec0 != Op0.getOperand(0))
6698 if (InVec1 != Op1.getOperand(0))
6701 // Update the pair of expected opcodes.
6702 std::swap(ExpectedOpcode, NextExpectedOpcode);
6705 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6706 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6707 InVec1.getOpcode() != ISD::UNDEF)
6708 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6713 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6714 const X86Subtarget *Subtarget) {
6716 EVT VT = N->getValueType(0);
6717 unsigned NumElts = VT.getVectorNumElements();
6718 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6719 SDValue InVec0, InVec1;
6721 // Try to match an ADDSUB.
6722 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6723 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6724 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6725 if (Value.getNode())
6729 // Try to match horizontal ADD/SUB.
6730 unsigned NumUndefsLO = 0;
6731 unsigned NumUndefsHI = 0;
6732 unsigned Half = NumElts/2;
6734 // Count the number of UNDEF operands in the build_vector in input.
6735 for (unsigned i = 0, e = Half; i != e; ++i)
6736 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6739 for (unsigned i = Half, e = NumElts; i != e; ++i)
6740 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6743 // Early exit if this is either a build_vector of all UNDEFs or all the
6744 // operands but one are UNDEF.
6745 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6748 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6749 // Try to match an SSE3 float HADD/HSUB.
6750 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6751 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6753 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6754 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6755 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6756 // Try to match an SSSE3 integer HADD/HSUB.
6757 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6758 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6760 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6761 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6764 if (!Subtarget->hasAVX())
6767 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6768 // Try to match an AVX horizontal add/sub of packed single/double
6769 // precision floating point values from 256-bit vectors.
6770 SDValue InVec2, InVec3;
6771 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6772 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6773 ((InVec0.getOpcode() == ISD::UNDEF ||
6774 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6775 ((InVec1.getOpcode() == ISD::UNDEF ||
6776 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6777 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6779 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6780 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6781 ((InVec0.getOpcode() == ISD::UNDEF ||
6782 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6783 ((InVec1.getOpcode() == ISD::UNDEF ||
6784 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6785 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6786 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6787 // Try to match an AVX2 horizontal add/sub of signed integers.
6788 SDValue InVec2, InVec3;
6790 bool CanFold = true;
6792 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6793 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6794 ((InVec0.getOpcode() == ISD::UNDEF ||
6795 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6796 ((InVec1.getOpcode() == ISD::UNDEF ||
6797 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6798 X86Opcode = X86ISD::HADD;
6799 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6800 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6801 ((InVec0.getOpcode() == ISD::UNDEF ||
6802 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6803 ((InVec1.getOpcode() == ISD::UNDEF ||
6804 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6805 X86Opcode = X86ISD::HSUB;
6810 // Fold this build_vector into a single horizontal add/sub.
6811 // Do this only if the target has AVX2.
6812 if (Subtarget->hasAVX2())
6813 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6815 // Do not try to expand this build_vector into a pair of horizontal
6816 // add/sub if we can emit a pair of scalar add/sub.
6817 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6820 // Convert this build_vector into a pair of horizontal binop followed by
6822 bool isUndefLO = NumUndefsLO == Half;
6823 bool isUndefHI = NumUndefsHI == Half;
6824 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6825 isUndefLO, isUndefHI);
6829 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6830 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6832 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6833 X86Opcode = X86ISD::HADD;
6834 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6835 X86Opcode = X86ISD::HSUB;
6836 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6837 X86Opcode = X86ISD::FHADD;
6838 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6839 X86Opcode = X86ISD::FHSUB;
6843 // Don't try to expand this build_vector into a pair of horizontal add/sub
6844 // if we can simply emit a pair of scalar add/sub.
6845 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6848 // Convert this build_vector into two horizontal add/sub followed by
6850 bool isUndefLO = NumUndefsLO == Half;
6851 bool isUndefHI = NumUndefsHI == Half;
6852 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6853 isUndefLO, isUndefHI);
6860 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6863 MVT VT = Op.getSimpleValueType();
6864 MVT ExtVT = VT.getVectorElementType();
6865 unsigned NumElems = Op.getNumOperands();
6867 // Generate vectors for predicate vectors.
6868 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6869 return LowerBUILD_VECTORvXi1(Op, DAG);
6871 // Vectors containing all zeros can be matched by pxor and xorps later
6872 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6873 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6874 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6875 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6878 return getZeroVector(VT, Subtarget, DAG, dl);
6881 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6882 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6883 // vpcmpeqd on 256-bit vectors.
6884 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6885 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6888 if (!VT.is512BitVector())
6889 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6892 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6893 if (Broadcast.getNode())
6896 unsigned EVTBits = ExtVT.getSizeInBits();
6898 unsigned NumZero = 0;
6899 unsigned NumNonZero = 0;
6900 unsigned NonZeros = 0;
6901 bool IsAllConstants = true;
6902 SmallSet<SDValue, 8> Values;
6903 for (unsigned i = 0; i < NumElems; ++i) {
6904 SDValue Elt = Op.getOperand(i);
6905 if (Elt.getOpcode() == ISD::UNDEF)
6908 if (Elt.getOpcode() != ISD::Constant &&
6909 Elt.getOpcode() != ISD::ConstantFP)
6910 IsAllConstants = false;
6911 if (X86::isZeroNode(Elt))
6914 NonZeros |= (1 << i);
6919 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6920 if (NumNonZero == 0)
6921 return DAG.getUNDEF(VT);
6923 // Special case for single non-zero, non-undef, element.
6924 if (NumNonZero == 1) {
6925 unsigned Idx = countTrailingZeros(NonZeros);
6926 SDValue Item = Op.getOperand(Idx);
6928 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6929 // the value are obviously zero, truncate the value to i32 and do the
6930 // insertion that way. Only do this if the value is non-constant or if the
6931 // value is a constant being inserted into element 0. It is cheaper to do
6932 // a constant pool load than it is to do a movd + shuffle.
6933 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6934 (!IsAllConstants || Idx == 0)) {
6935 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6937 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6938 EVT VecVT = MVT::v4i32;
6939 unsigned VecElts = 4;
6941 // Truncate the value (which may itself be a constant) to i32, and
6942 // convert it to a vector with movd (S2V+shuffle to zero extend).
6943 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6944 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6946 // If using the new shuffle lowering, just directly insert this.
6947 if (ExperimentalVectorShuffleLowering)
6949 ISD::BITCAST, dl, VT,
6950 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6952 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6954 // Now we have our 32-bit value zero extended in the low element of
6955 // a vector. If Idx != 0, swizzle it into place.
6957 SmallVector<int, 4> Mask;
6958 Mask.push_back(Idx);
6959 for (unsigned i = 1; i != VecElts; ++i)
6961 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6964 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6968 // If we have a constant or non-constant insertion into the low element of
6969 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6970 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6971 // depending on what the source datatype is.
6974 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6976 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6977 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6978 if (VT.is256BitVector() || VT.is512BitVector()) {
6979 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6980 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6981 Item, DAG.getIntPtrConstant(0));
6983 assert(VT.is128BitVector() && "Expected an SSE value type!");
6984 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6985 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6986 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6989 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6990 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6991 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6992 if (VT.is256BitVector()) {
6993 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6994 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6996 assert(VT.is128BitVector() && "Expected an SSE value type!");
6997 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6999 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
7003 // Is it a vector logical left shift?
7004 if (NumElems == 2 && Idx == 1 &&
7005 X86::isZeroNode(Op.getOperand(0)) &&
7006 !X86::isZeroNode(Op.getOperand(1))) {
7007 unsigned NumBits = VT.getSizeInBits();
7008 return getVShift(true, VT,
7009 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7010 VT, Op.getOperand(1)),
7011 NumBits/2, DAG, *this, dl);
7014 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7017 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7018 // is a non-constant being inserted into an element other than the low one,
7019 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7020 // movd/movss) to move this into the low element, then shuffle it into
7022 if (EVTBits == 32) {
7023 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7025 // If using the new shuffle lowering, just directly insert this.
7026 if (ExperimentalVectorShuffleLowering)
7027 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7029 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7030 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7031 SmallVector<int, 8> MaskVec;
7032 for (unsigned i = 0; i != NumElems; ++i)
7033 MaskVec.push_back(i == Idx ? 0 : 1);
7034 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7038 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7039 if (Values.size() == 1) {
7040 if (EVTBits == 32) {
7041 // Instead of a shuffle like this:
7042 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7043 // Check if it's possible to issue this instead.
7044 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7045 unsigned Idx = countTrailingZeros(NonZeros);
7046 SDValue Item = Op.getOperand(Idx);
7047 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7048 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7053 // A vector full of immediates; various special cases are already
7054 // handled, so this is best done with a single constant-pool load.
7058 // For AVX-length vectors, see if we can use a vector load to get all of the
7059 // elements, otherwise build the individual 128-bit pieces and use
7060 // shuffles to put them in place.
7061 if (VT.is256BitVector() || VT.is512BitVector()) {
7062 SmallVector<SDValue, 64> V;
7063 for (unsigned i = 0; i != NumElems; ++i)
7064 V.push_back(Op.getOperand(i));
7066 // Check for a build vector of consecutive loads.
7067 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7070 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7072 // Build both the lower and upper subvector.
7073 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7074 makeArrayRef(&V[0], NumElems/2));
7075 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7076 makeArrayRef(&V[NumElems / 2], NumElems/2));
7078 // Recreate the wider vector with the lower and upper part.
7079 if (VT.is256BitVector())
7080 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7081 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7084 // Let legalizer expand 2-wide build_vectors.
7085 if (EVTBits == 64) {
7086 if (NumNonZero == 1) {
7087 // One half is zero or undef.
7088 unsigned Idx = countTrailingZeros(NonZeros);
7089 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7090 Op.getOperand(Idx));
7091 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7096 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7097 if (EVTBits == 8 && NumElems == 16) {
7098 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7100 if (V.getNode()) return V;
7103 if (EVTBits == 16 && NumElems == 8) {
7104 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7106 if (V.getNode()) return V;
7109 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7110 if (EVTBits == 32 && NumElems == 4) {
7111 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7116 // If element VT is == 32 bits, turn it into a number of shuffles.
7117 SmallVector<SDValue, 8> V(NumElems);
7118 if (NumElems == 4 && NumZero > 0) {
7119 for (unsigned i = 0; i < 4; ++i) {
7120 bool isZero = !(NonZeros & (1 << i));
7122 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7124 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7127 for (unsigned i = 0; i < 2; ++i) {
7128 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7131 V[i] = V[i*2]; // Must be a zero vector.
7134 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7137 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7140 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7145 bool Reverse1 = (NonZeros & 0x3) == 2;
7146 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7150 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7151 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7153 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7156 if (Values.size() > 1 && VT.is128BitVector()) {
7157 // Check for a build vector of consecutive loads.
7158 for (unsigned i = 0; i < NumElems; ++i)
7159 V[i] = Op.getOperand(i);
7161 // Check for elements which are consecutive loads.
7162 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7166 // Check for a build vector from mostly shuffle plus few inserting.
7167 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7171 // For SSE 4.1, use insertps to put the high elements into the low element.
7172 if (getSubtarget()->hasSSE41()) {
7174 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7175 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7177 Result = DAG.getUNDEF(VT);
7179 for (unsigned i = 1; i < NumElems; ++i) {
7180 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7181 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7182 Op.getOperand(i), DAG.getIntPtrConstant(i));
7187 // Otherwise, expand into a number of unpckl*, start by extending each of
7188 // our (non-undef) elements to the full vector width with the element in the
7189 // bottom slot of the vector (which generates no code for SSE).
7190 for (unsigned i = 0; i < NumElems; ++i) {
7191 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7192 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7194 V[i] = DAG.getUNDEF(VT);
7197 // Next, we iteratively mix elements, e.g. for v4f32:
7198 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7199 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7200 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7201 unsigned EltStride = NumElems >> 1;
7202 while (EltStride != 0) {
7203 for (unsigned i = 0; i < EltStride; ++i) {
7204 // If V[i+EltStride] is undef and this is the first round of mixing,
7205 // then it is safe to just drop this shuffle: V[i] is already in the
7206 // right place, the one element (since it's the first round) being
7207 // inserted as undef can be dropped. This isn't safe for successive
7208 // rounds because they will permute elements within both vectors.
7209 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7210 EltStride == NumElems/2)
7213 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7222 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7223 // to create 256-bit vectors from two other 128-bit ones.
7224 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7226 MVT ResVT = Op.getSimpleValueType();
7228 assert((ResVT.is256BitVector() ||
7229 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7231 SDValue V1 = Op.getOperand(0);
7232 SDValue V2 = Op.getOperand(1);
7233 unsigned NumElems = ResVT.getVectorNumElements();
7234 if(ResVT.is256BitVector())
7235 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7237 if (Op.getNumOperands() == 4) {
7238 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7239 ResVT.getVectorNumElements()/2);
7240 SDValue V3 = Op.getOperand(2);
7241 SDValue V4 = Op.getOperand(3);
7242 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7243 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7245 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7248 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7249 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7250 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7251 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7252 Op.getNumOperands() == 4)));
7254 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7255 // from two other 128-bit ones.
7257 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7258 return LowerAVXCONCAT_VECTORS(Op, DAG);
7262 //===----------------------------------------------------------------------===//
7263 // Vector shuffle lowering
7265 // This is an experimental code path for lowering vector shuffles on x86. It is
7266 // designed to handle arbitrary vector shuffles and blends, gracefully
7267 // degrading performance as necessary. It works hard to recognize idiomatic
7268 // shuffles and lower them to optimal instruction patterns without leaving
7269 // a framework that allows reasonably efficient handling of all vector shuffle
7271 //===----------------------------------------------------------------------===//
7273 /// \brief Tiny helper function to identify a no-op mask.
7275 /// This is a somewhat boring predicate function. It checks whether the mask
7276 /// array input, which is assumed to be a single-input shuffle mask of the kind
7277 /// used by the X86 shuffle instructions (not a fully general
7278 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7279 /// in-place shuffle are 'no-op's.
7280 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7281 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7282 if (Mask[i] != -1 && Mask[i] != i)
7287 /// \brief Helper function to classify a mask as a single-input mask.
7289 /// This isn't a generic single-input test because in the vector shuffle
7290 /// lowering we canonicalize single inputs to be the first input operand. This
7291 /// means we can more quickly test for a single input by only checking whether
7292 /// an input from the second operand exists. We also assume that the size of
7293 /// mask corresponds to the size of the input vectors which isn't true in the
7294 /// fully general case.
7295 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7297 if (M >= (int)Mask.size())
7302 /// \brief Test whether there are elements crossing 128-bit lanes in this
7305 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7306 /// and we routinely test for these.
7307 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7308 int LaneSize = 128 / VT.getScalarSizeInBits();
7309 int Size = Mask.size();
7310 for (int i = 0; i < Size; ++i)
7311 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7316 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7318 /// This checks a shuffle mask to see if it is performing the same
7319 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7320 /// that it is also not lane-crossing. It may however involve a blend from the
7321 /// same lane of a second vector.
7323 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7324 /// non-trivial to compute in the face of undef lanes. The representation is
7325 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7326 /// entries from both V1 and V2 inputs to the wider mask.
7328 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7329 SmallVectorImpl<int> &RepeatedMask) {
7330 int LaneSize = 128 / VT.getScalarSizeInBits();
7331 RepeatedMask.resize(LaneSize, -1);
7332 int Size = Mask.size();
7333 for (int i = 0; i < Size; ++i) {
7336 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7337 // This entry crosses lanes, so there is no way to model this shuffle.
7340 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7341 if (RepeatedMask[i % LaneSize] == -1)
7342 // This is the first non-undef entry in this slot of a 128-bit lane.
7343 RepeatedMask[i % LaneSize] =
7344 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7345 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7346 // Found a mismatch with the repeated mask.
7352 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7353 // 2013 will allow us to use it as a non-type template parameter.
7356 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7358 /// See its documentation for details.
7359 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7360 if (Mask.size() != Args.size())
7362 for (int i = 0, e = Mask.size(); i < e; ++i) {
7363 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7364 if (Mask[i] != -1 && Mask[i] != *Args[i])
7372 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7375 /// This is a fast way to test a shuffle mask against a fixed pattern:
7377 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7379 /// It returns true if the mask is exactly as wide as the argument list, and
7380 /// each element of the mask is either -1 (signifying undef) or the value given
7381 /// in the argument.
7382 static const VariadicFunction1<
7383 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7385 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7387 /// This helper function produces an 8-bit shuffle immediate corresponding to
7388 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7389 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7392 /// NB: We rely heavily on "undef" masks preserving the input lane.
7393 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7394 SelectionDAG &DAG) {
7395 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7396 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7397 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7398 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7399 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7402 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7403 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7404 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7405 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7406 return DAG.getConstant(Imm, MVT::i8);
7409 /// \brief Try to emit a blend instruction for a shuffle.
7411 /// This doesn't do any checks for the availability of instructions for blending
7412 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7413 /// be matched in the backend with the type given. What it does check for is
7414 /// that the shuffle mask is in fact a blend.
7415 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7416 SDValue V2, ArrayRef<int> Mask,
7417 const X86Subtarget *Subtarget,
7418 SelectionDAG &DAG) {
7420 unsigned BlendMask = 0;
7421 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7422 if (Mask[i] >= Size) {
7423 if (Mask[i] != i + Size)
7424 return SDValue(); // Shuffled V2 input!
7425 BlendMask |= 1u << i;
7428 if (Mask[i] >= 0 && Mask[i] != i)
7429 return SDValue(); // Shuffled V1 input!
7431 switch (VT.SimpleTy) {
7436 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7437 DAG.getConstant(BlendMask, MVT::i8));
7441 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7445 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7446 // that instruction.
7447 if (Subtarget->hasAVX2()) {
7448 // Scale the blend by the number of 32-bit dwords per element.
7449 int Scale = VT.getScalarSizeInBits() / 32;
7451 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7452 if (Mask[i] >= Size)
7453 for (int j = 0; j < Scale; ++j)
7454 BlendMask |= 1u << (i * Scale + j);
7456 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7457 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7458 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7459 return DAG.getNode(ISD::BITCAST, DL, VT,
7460 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7461 DAG.getConstant(BlendMask, MVT::i8)));
7465 // For integer shuffles we need to expand the mask and cast the inputs to
7466 // v8i16s prior to blending.
7467 int Scale = 8 / VT.getVectorNumElements();
7469 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7470 if (Mask[i] >= Size)
7471 for (int j = 0; j < Scale; ++j)
7472 BlendMask |= 1u << (i * Scale + j);
7474 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7475 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7476 return DAG.getNode(ISD::BITCAST, DL, VT,
7477 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7478 DAG.getConstant(BlendMask, MVT::i8)));
7482 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7483 SmallVector<int, 8> RepeatedMask;
7484 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7485 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7486 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7488 for (int i = 0; i < 8; ++i)
7489 if (RepeatedMask[i] >= 16)
7490 BlendMask |= 1u << i;
7491 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7492 DAG.getConstant(BlendMask, MVT::i8));
7497 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7498 // Scale the blend by the number of bytes per element.
7499 int Scale = VT.getScalarSizeInBits() / 8;
7500 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7502 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7503 // mix of LLVM's code generator and the x86 backend. We tell the code
7504 // generator that boolean values in the elements of an x86 vector register
7505 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7506 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7507 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7508 // of the element (the remaining are ignored) and 0 in that high bit would
7509 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7510 // the LLVM model for boolean values in vector elements gets the relevant
7511 // bit set, it is set backwards and over constrained relative to x86's
7513 SDValue VSELECTMask[32];
7514 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7515 for (int j = 0; j < Scale; ++j)
7516 VSELECTMask[Scale * i + j] =
7517 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7518 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7520 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7521 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7523 ISD::BITCAST, DL, VT,
7524 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7525 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7530 llvm_unreachable("Not a supported integer vector type!");
7534 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7535 /// unblended shuffles followed by an unshuffled blend.
7537 /// This matches the extremely common pattern for handling combined
7538 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7540 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7544 SelectionDAG &DAG) {
7545 // Shuffle the input elements into the desired positions in V1 and V2 and
7546 // blend them together.
7547 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7548 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7549 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7550 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7551 if (Mask[i] >= 0 && Mask[i] < Size) {
7552 V1Mask[i] = Mask[i];
7554 } else if (Mask[i] >= Size) {
7555 V2Mask[i] = Mask[i] - Size;
7556 BlendMask[i] = i + Size;
7559 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7560 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7561 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7564 /// \brief Try to lower a vector shuffle as a byte rotation.
7566 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7567 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7568 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7569 /// try to generically lower a vector shuffle through such an pattern. It
7570 /// does not check for the profitability of lowering either as PALIGNR or
7571 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7572 /// This matches shuffle vectors that look like:
7574 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7576 /// Essentially it concatenates V1 and V2, shifts right by some number of
7577 /// elements, and takes the low elements as the result. Note that while this is
7578 /// specified as a *right shift* because x86 is little-endian, it is a *left
7579 /// rotate* of the vector lanes.
7581 /// Note that this only handles 128-bit vector widths currently.
7582 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7585 const X86Subtarget *Subtarget,
7586 SelectionDAG &DAG) {
7587 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7589 // We need to detect various ways of spelling a rotation:
7590 // [11, 12, 13, 14, 15, 0, 1, 2]
7591 // [-1, 12, 13, 14, -1, -1, 1, -1]
7592 // [-1, -1, -1, -1, -1, -1, 1, 2]
7593 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7594 // [-1, 4, 5, 6, -1, -1, 9, -1]
7595 // [-1, 4, 5, 6, -1, -1, -1, -1]
7598 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7601 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7603 // Based on the mod-Size value of this mask element determine where
7604 // a rotated vector would have started.
7605 int StartIdx = i - (Mask[i] % Size);
7607 // The identity rotation isn't interesting, stop.
7610 // If we found the tail of a vector the rotation must be the missing
7611 // front. If we found the head of a vector, it must be how much of the head.
7612 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7615 Rotation = CandidateRotation;
7616 else if (Rotation != CandidateRotation)
7617 // The rotations don't match, so we can't match this mask.
7620 // Compute which value this mask is pointing at.
7621 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7623 // Compute which of the two target values this index should be assigned to.
7624 // This reflects whether the high elements are remaining or the low elements
7626 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7628 // Either set up this value if we've not encountered it before, or check
7629 // that it remains consistent.
7632 else if (TargetV != MaskV)
7633 // This may be a rotation, but it pulls from the inputs in some
7634 // unsupported interleaving.
7638 // Check that we successfully analyzed the mask, and normalize the results.
7639 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7640 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7646 assert(VT.getSizeInBits() == 128 &&
7647 "Rotate-based lowering only supports 128-bit lowering!");
7648 assert(Mask.size() <= 16 &&
7649 "Can shuffle at most 16 bytes in a 128-bit vector!");
7651 // The actual rotate instruction rotates bytes, so we need to scale the
7652 // rotation based on how many bytes are in the vector.
7653 int Scale = 16 / Mask.size();
7655 // SSSE3 targets can use the palignr instruction
7656 if (Subtarget->hasSSSE3()) {
7657 // Cast the inputs to v16i8 to match PALIGNR.
7658 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7659 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7661 return DAG.getNode(ISD::BITCAST, DL, VT,
7662 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7663 DAG.getConstant(Rotation * Scale, MVT::i8)));
7666 // Default SSE2 implementation
7667 int LoByteShift = 16 - Rotation * Scale;
7668 int HiByteShift = Rotation * Scale;
7670 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7671 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7672 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7674 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7675 DAG.getConstant(8 * LoByteShift, MVT::i8));
7676 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7677 DAG.getConstant(8 * HiByteShift, MVT::i8));
7678 return DAG.getNode(ISD::BITCAST, DL, VT,
7679 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7682 /// \brief Compute whether each element of a shuffle is zeroable.
7684 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7685 /// Either it is an undef element in the shuffle mask, the element of the input
7686 /// referenced is undef, or the element of the input referenced is known to be
7687 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7688 /// as many lanes with this technique as possible to simplify the remaining
7690 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7691 SDValue V1, SDValue V2) {
7692 SmallBitVector Zeroable(Mask.size(), false);
7694 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7695 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7697 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7699 // Handle the easy cases.
7700 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7705 // If this is an index into a build_vector node, dig out the input value and
7707 SDValue V = M < Size ? V1 : V2;
7708 if (V.getOpcode() != ISD::BUILD_VECTOR)
7711 SDValue Input = V.getOperand(M % Size);
7712 // The UNDEF opcode check really should be dead code here, but not quite
7713 // worth asserting on (it isn't invalid, just unexpected).
7714 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7721 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7723 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7724 /// byte-shift instructions. The mask must consist of a shifted sequential
7725 /// shuffle from one of the input vectors and zeroable elements for the
7726 /// remaining 'shifted in' elements.
7728 /// Note that this only handles 128-bit vector widths currently.
7729 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7730 SDValue V2, ArrayRef<int> Mask,
7731 SelectionDAG &DAG) {
7732 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7734 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7736 int Size = Mask.size();
7737 int Scale = 16 / Size;
7739 for (int Shift = 1; Shift < Size; Shift++) {
7740 int ByteShift = Shift * Scale;
7742 // PSRLDQ : (little-endian) right byte shift
7743 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7744 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7745 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7746 bool ZeroableRight = true;
7747 for (int i = Size - Shift; i < Size; i++) {
7748 ZeroableRight &= Zeroable[i];
7751 if (ZeroableRight) {
7752 bool ValidShiftRight1 =
7753 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Shift);
7754 bool ValidShiftRight2 =
7755 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Size + Shift);
7757 if (ValidShiftRight1 || ValidShiftRight2) {
7758 // Cast the inputs to v2i64 to match PSRLDQ.
7759 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7760 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7761 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7762 DAG.getConstant(ByteShift * 8, MVT::i8));
7763 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7767 // PSLLDQ : (little-endian) left byte shift
7768 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7769 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7770 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7771 bool ZeroableLeft = true;
7772 for (int i = 0; i < Shift; i++) {
7773 ZeroableLeft &= Zeroable[i];
7777 bool ValidShiftLeft1 =
7778 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, 0);
7779 bool ValidShiftLeft2 =
7780 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, Size);
7782 if (ValidShiftLeft1 || ValidShiftLeft2) {
7783 // Cast the inputs to v2i64 to match PSLLDQ.
7784 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7785 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7786 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7787 DAG.getConstant(ByteShift * 8, MVT::i8));
7788 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7796 /// \brief Lower a vector shuffle as a zero or any extension.
7798 /// Given a specific number of elements, element bit width, and extension
7799 /// stride, produce either a zero or any extension based on the available
7800 /// features of the subtarget.
7801 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7802 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7803 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7804 assert(Scale > 1 && "Need a scale to extend.");
7805 int EltBits = VT.getSizeInBits() / NumElements;
7806 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7807 "Only 8, 16, and 32 bit elements can be extended.");
7808 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7810 // Found a valid zext mask! Try various lowering strategies based on the
7811 // input type and available ISA extensions.
7812 if (Subtarget->hasSSE41()) {
7813 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7814 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7815 NumElements / Scale);
7816 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7817 return DAG.getNode(ISD::BITCAST, DL, VT,
7818 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7821 // For any extends we can cheat for larger element sizes and use shuffle
7822 // instructions that can fold with a load and/or copy.
7823 if (AnyExt && EltBits == 32) {
7824 int PSHUFDMask[4] = {0, -1, 1, -1};
7826 ISD::BITCAST, DL, VT,
7827 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7828 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7829 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7831 if (AnyExt && EltBits == 16 && Scale > 2) {
7832 int PSHUFDMask[4] = {0, -1, 0, -1};
7833 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7834 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7835 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7836 int PSHUFHWMask[4] = {1, -1, -1, -1};
7838 ISD::BITCAST, DL, VT,
7839 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7840 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7841 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7844 // If this would require more than 2 unpack instructions to expand, use
7845 // pshufb when available. We can only use more than 2 unpack instructions
7846 // when zero extending i8 elements which also makes it easier to use pshufb.
7847 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7848 assert(NumElements == 16 && "Unexpected byte vector width!");
7849 SDValue PSHUFBMask[16];
7850 for (int i = 0; i < 16; ++i)
7852 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7853 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7854 return DAG.getNode(ISD::BITCAST, DL, VT,
7855 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7856 DAG.getNode(ISD::BUILD_VECTOR, DL,
7857 MVT::v16i8, PSHUFBMask)));
7860 // Otherwise emit a sequence of unpacks.
7862 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7863 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7864 : getZeroVector(InputVT, Subtarget, DAG, DL);
7865 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7866 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7870 } while (Scale > 1);
7871 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7874 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7876 /// This routine will try to do everything in its power to cleverly lower
7877 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7878 /// check for the profitability of this lowering, it tries to aggressively
7879 /// match this pattern. It will use all of the micro-architectural details it
7880 /// can to emit an efficient lowering. It handles both blends with all-zero
7881 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7882 /// masking out later).
7884 /// The reason we have dedicated lowering for zext-style shuffles is that they
7885 /// are both incredibly common and often quite performance sensitive.
7886 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7887 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7888 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7889 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7891 int Bits = VT.getSizeInBits();
7892 int NumElements = Mask.size();
7894 // Define a helper function to check a particular ext-scale and lower to it if
7896 auto Lower = [&](int Scale) -> SDValue {
7899 for (int i = 0; i < NumElements; ++i) {
7901 continue; // Valid anywhere but doesn't tell us anything.
7902 if (i % Scale != 0) {
7903 // Each of the extend elements needs to be zeroable.
7907 // We no lorger are in the anyext case.
7912 // Each of the base elements needs to be consecutive indices into the
7913 // same input vector.
7914 SDValue V = Mask[i] < NumElements ? V1 : V2;
7917 else if (InputV != V)
7918 return SDValue(); // Flip-flopping inputs.
7920 if (Mask[i] % NumElements != i / Scale)
7921 return SDValue(); // Non-consecutive strided elemenst.
7924 // If we fail to find an input, we have a zero-shuffle which should always
7925 // have already been handled.
7926 // FIXME: Maybe handle this here in case during blending we end up with one?
7930 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7931 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7934 // The widest scale possible for extending is to a 64-bit integer.
7935 assert(Bits % 64 == 0 &&
7936 "The number of bits in a vector must be divisible by 64 on x86!");
7937 int NumExtElements = Bits / 64;
7939 // Each iteration, try extending the elements half as much, but into twice as
7941 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7942 assert(NumElements % NumExtElements == 0 &&
7943 "The input vector size must be divisble by the extended size.");
7944 if (SDValue V = Lower(NumElements / NumExtElements))
7948 // No viable ext lowering found.
7952 /// \brief Try to get a scalar value for a specific element of a vector.
7954 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7955 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7956 SelectionDAG &DAG) {
7957 MVT VT = V.getSimpleValueType();
7958 MVT EltVT = VT.getVectorElementType();
7959 while (V.getOpcode() == ISD::BITCAST)
7960 V = V.getOperand(0);
7961 // If the bitcasts shift the element size, we can't extract an equivalent
7963 MVT NewVT = V.getSimpleValueType();
7964 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7967 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7968 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7969 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7974 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7976 /// This is particularly important because the set of instructions varies
7977 /// significantly based on whether the operand is a load or not.
7978 static bool isShuffleFoldableLoad(SDValue V) {
7979 while (V.getOpcode() == ISD::BITCAST)
7980 V = V.getOperand(0);
7982 return ISD::isNON_EXTLoad(V.getNode());
7985 /// \brief Try to lower insertion of a single element into a zero vector.
7987 /// This is a common pattern that we have especially efficient patterns to lower
7988 /// across all subtarget feature sets.
7989 static SDValue lowerVectorShuffleAsElementInsertion(
7990 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7991 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7992 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7994 MVT EltVT = VT.getVectorElementType();
7996 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7997 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7999 bool IsV1Zeroable = true;
8000 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8001 if (i != V2Index && !Zeroable[i]) {
8002 IsV1Zeroable = false;
8006 // Check for a single input from a SCALAR_TO_VECTOR node.
8007 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
8008 // all the smarts here sunk into that routine. However, the current
8009 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8010 // vector shuffle lowering is dead.
8011 if (SDValue V2S = getScalarValueForVectorElement(
8012 V2, Mask[V2Index] - Mask.size(), DAG)) {
8013 // We need to zext the scalar if it is smaller than an i32.
8014 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8015 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8016 // Using zext to expand a narrow element won't work for non-zero
8021 // Zero-extend directly to i32.
8023 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8025 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8026 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8027 EltVT == MVT::i16) {
8028 // Either not inserting from the low element of the input or the input
8029 // element size is too small to use VZEXT_MOVL to clear the high bits.
8033 if (!IsV1Zeroable) {
8034 // If V1 can't be treated as a zero vector we have fewer options to lower
8035 // this. We can't support integer vectors or non-zero targets cheaply, and
8036 // the V1 elements can't be permuted in any way.
8037 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8038 if (!VT.isFloatingPoint() || V2Index != 0)
8040 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8041 V1Mask[V2Index] = -1;
8042 if (!isNoopShuffleMask(V1Mask))
8044 // This is essentially a special case blend operation, but if we have
8045 // general purpose blend operations, they are always faster. Bail and let
8046 // the rest of the lowering handle these as blends.
8047 if (Subtarget->hasSSE41())
8050 // Otherwise, use MOVSD or MOVSS.
8051 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8052 "Only two types of floating point element types to handle!");
8053 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8057 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8059 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8062 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8063 // the desired position. Otherwise it is more efficient to do a vector
8064 // shift left. We know that we can do a vector shift left because all
8065 // the inputs are zero.
8066 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8067 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8068 V2Shuffle[V2Index] = 0;
8069 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8071 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8073 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8075 V2Index * EltVT.getSizeInBits(),
8076 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8077 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8083 /// \brief Try to lower broadcast of a single element.
8085 /// For convenience, this code also bundles all of the subtarget feature set
8086 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8087 /// a convenient way to factor it out.
8088 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8090 const X86Subtarget *Subtarget,
8091 SelectionDAG &DAG) {
8092 if (!Subtarget->hasAVX())
8094 if (VT.isInteger() && !Subtarget->hasAVX2())
8097 // Check that the mask is a broadcast.
8098 int BroadcastIdx = -1;
8100 if (M >= 0 && BroadcastIdx == -1)
8102 else if (M >= 0 && M != BroadcastIdx)
8105 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8106 "a sorted mask where the broadcast "
8109 // Go up the chain of (vector) values to try and find a scalar load that
8110 // we can combine with the broadcast.
8112 switch (V.getOpcode()) {
8113 case ISD::CONCAT_VECTORS: {
8114 int OperandSize = Mask.size() / V.getNumOperands();
8115 V = V.getOperand(BroadcastIdx / OperandSize);
8116 BroadcastIdx %= OperandSize;
8120 case ISD::INSERT_SUBVECTOR: {
8121 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8122 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8126 int BeginIdx = (int)ConstantIdx->getZExtValue();
8128 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8129 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8130 BroadcastIdx -= BeginIdx;
8141 // Check if this is a broadcast of a scalar. We special case lowering
8142 // for scalars so that we can more effectively fold with loads.
8143 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8144 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8145 V = V.getOperand(BroadcastIdx);
8147 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8149 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8151 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8152 // We can't broadcast from a vector register w/o AVX2, and we can only
8153 // broadcast from the zero-element of a vector register.
8157 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8160 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8161 // INSERTPS when the V1 elements are already in the correct locations
8162 // because otherwise we can just always use two SHUFPS instructions which
8163 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8164 // perform INSERTPS if a single V1 element is out of place and all V2
8165 // elements are zeroable.
8166 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8168 SelectionDAG &DAG) {
8169 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8170 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8171 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8172 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8174 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8177 int V1DstIndex = -1;
8178 int V2DstIndex = -1;
8179 bool V1UsedInPlace = false;
8181 for (int i = 0; i < 4; i++) {
8182 // Synthesize a zero mask from the zeroable elements (includes undefs).
8188 // Flag if we use any V1 inputs in place.
8190 V1UsedInPlace = true;
8194 // We can only insert a single non-zeroable element.
8195 if (V1DstIndex != -1 || V2DstIndex != -1)
8199 // V1 input out of place for insertion.
8202 // V2 input for insertion.
8207 // Don't bother if we have no (non-zeroable) element for insertion.
8208 if (V1DstIndex == -1 && V2DstIndex == -1)
8211 // Determine element insertion src/dst indices. The src index is from the
8212 // start of the inserted vector, not the start of the concatenated vector.
8213 unsigned V2SrcIndex = 0;
8214 if (V1DstIndex != -1) {
8215 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8216 // and don't use the original V2 at all.
8217 V2SrcIndex = Mask[V1DstIndex];
8218 V2DstIndex = V1DstIndex;
8221 V2SrcIndex = Mask[V2DstIndex] - 4;
8224 // If no V1 inputs are used in place, then the result is created only from
8225 // the zero mask and the V2 insertion - so remove V1 dependency.
8227 V1 = DAG.getUNDEF(MVT::v4f32);
8229 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8230 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8232 // Insert the V2 element into the desired position.
8234 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8235 DAG.getConstant(InsertPSMask, MVT::i8));
8238 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8240 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8241 /// support for floating point shuffles but not integer shuffles. These
8242 /// instructions will incur a domain crossing penalty on some chips though so
8243 /// it is better to avoid lowering through this for integer vectors where
8245 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8246 const X86Subtarget *Subtarget,
8247 SelectionDAG &DAG) {
8249 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8250 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8251 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8252 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8253 ArrayRef<int> Mask = SVOp->getMask();
8254 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8256 if (isSingleInputShuffleMask(Mask)) {
8257 // Straight shuffle of a single input vector. Simulate this by using the
8258 // single input as both of the "inputs" to this instruction..
8259 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8261 if (Subtarget->hasAVX()) {
8262 // If we have AVX, we can use VPERMILPS which will allow folding a load
8263 // into the shuffle.
8264 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8265 DAG.getConstant(SHUFPDMask, MVT::i8));
8268 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8269 DAG.getConstant(SHUFPDMask, MVT::i8));
8271 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8272 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8274 // Use dedicated unpack instructions for masks that match their pattern.
8275 if (isShuffleEquivalent(Mask, 0, 2))
8276 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8277 if (isShuffleEquivalent(Mask, 1, 3))
8278 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8280 // If we have a single input, insert that into V1 if we can do so cheaply.
8281 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8282 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8283 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8285 // Try inverting the insertion since for v2 masks it is easy to do and we
8286 // can't reliably sort the mask one way or the other.
8287 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8288 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8289 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8290 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8294 // Try to use one of the special instruction patterns to handle two common
8295 // blend patterns if a zero-blend above didn't work.
8296 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8297 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8298 // We can either use a special instruction to load over the low double or
8299 // to move just the low double.
8301 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8303 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8305 if (Subtarget->hasSSE41())
8306 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8310 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8311 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8312 DAG.getConstant(SHUFPDMask, MVT::i8));
8315 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8317 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8318 /// the integer unit to minimize domain crossing penalties. However, for blends
8319 /// it falls back to the floating point shuffle operation with appropriate bit
8321 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8322 const X86Subtarget *Subtarget,
8323 SelectionDAG &DAG) {
8325 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8326 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8327 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8329 ArrayRef<int> Mask = SVOp->getMask();
8330 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8332 if (isSingleInputShuffleMask(Mask)) {
8333 // Check for being able to broadcast a single element.
8334 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8335 Mask, Subtarget, DAG))
8338 // Straight shuffle of a single input vector. For everything from SSE2
8339 // onward this has a single fast instruction with no scary immediates.
8340 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8341 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8342 int WidenedMask[4] = {
8343 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8344 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8346 ISD::BITCAST, DL, MVT::v2i64,
8347 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8348 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8351 // Try to use byte shift instructions.
8352 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8353 DL, MVT::v2i64, V1, V2, Mask, DAG))
8356 // If we have a single input from V2 insert that into V1 if we can do so
8358 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8359 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8360 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8362 // Try inverting the insertion since for v2 masks it is easy to do and we
8363 // can't reliably sort the mask one way or the other.
8364 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8365 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8366 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8367 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8371 // Use dedicated unpack instructions for masks that match their pattern.
8372 if (isShuffleEquivalent(Mask, 0, 2))
8373 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8374 if (isShuffleEquivalent(Mask, 1, 3))
8375 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8377 if (Subtarget->hasSSE41())
8378 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8382 // Try to use byte rotation instructions.
8383 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8384 if (Subtarget->hasSSSE3())
8385 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8386 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8389 // We implement this with SHUFPD which is pretty lame because it will likely
8390 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8391 // However, all the alternatives are still more cycles and newer chips don't
8392 // have this problem. It would be really nice if x86 had better shuffles here.
8393 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8394 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8395 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8396 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8399 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8401 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8402 /// It makes no assumptions about whether this is the *best* lowering, it simply
8404 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8405 ArrayRef<int> Mask, SDValue V1,
8406 SDValue V2, SelectionDAG &DAG) {
8407 SDValue LowV = V1, HighV = V2;
8408 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8411 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8413 if (NumV2Elements == 1) {
8415 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8418 // Compute the index adjacent to V2Index and in the same half by toggling
8420 int V2AdjIndex = V2Index ^ 1;
8422 if (Mask[V2AdjIndex] == -1) {
8423 // Handles all the cases where we have a single V2 element and an undef.
8424 // This will only ever happen in the high lanes because we commute the
8425 // vector otherwise.
8427 std::swap(LowV, HighV);
8428 NewMask[V2Index] -= 4;
8430 // Handle the case where the V2 element ends up adjacent to a V1 element.
8431 // To make this work, blend them together as the first step.
8432 int V1Index = V2AdjIndex;
8433 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8434 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8435 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8437 // Now proceed to reconstruct the final blend as we have the necessary
8438 // high or low half formed.
8445 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8446 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8448 } else if (NumV2Elements == 2) {
8449 if (Mask[0] < 4 && Mask[1] < 4) {
8450 // Handle the easy case where we have V1 in the low lanes and V2 in the
8454 } else if (Mask[2] < 4 && Mask[3] < 4) {
8455 // We also handle the reversed case because this utility may get called
8456 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8457 // arrange things in the right direction.
8463 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8464 // trying to place elements directly, just blend them and set up the final
8465 // shuffle to place them.
8467 // The first two blend mask elements are for V1, the second two are for
8469 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8470 Mask[2] < 4 ? Mask[2] : Mask[3],
8471 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8472 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8473 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8474 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8476 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8479 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8480 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8481 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8482 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8485 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8486 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8489 /// \brief Lower 4-lane 32-bit floating point shuffles.
8491 /// Uses instructions exclusively from the floating point unit to minimize
8492 /// domain crossing penalties, as these are sufficient to implement all v4f32
8494 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8495 const X86Subtarget *Subtarget,
8496 SelectionDAG &DAG) {
8498 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8499 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8500 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8502 ArrayRef<int> Mask = SVOp->getMask();
8503 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8506 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8508 if (NumV2Elements == 0) {
8509 // Check for being able to broadcast a single element.
8510 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8511 Mask, Subtarget, DAG))
8514 if (Subtarget->hasAVX()) {
8515 // If we have AVX, we can use VPERMILPS which will allow folding a load
8516 // into the shuffle.
8517 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8518 getV4X86ShuffleImm8ForMask(Mask, DAG));
8521 // Otherwise, use a straight shuffle of a single input vector. We pass the
8522 // input vector to both operands to simulate this with a SHUFPS.
8523 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8524 getV4X86ShuffleImm8ForMask(Mask, DAG));
8527 // Use dedicated unpack instructions for masks that match their pattern.
8528 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8529 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8530 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8531 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8533 // There are special ways we can lower some single-element blends. However, we
8534 // have custom ways we can lower more complex single-element blends below that
8535 // we defer to if both this and BLENDPS fail to match, so restrict this to
8536 // when the V2 input is targeting element 0 of the mask -- that is the fast
8538 if (NumV2Elements == 1 && Mask[0] >= 4)
8539 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8540 Mask, Subtarget, DAG))
8543 if (Subtarget->hasSSE41()) {
8544 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8548 // Use INSERTPS if we can complete the shuffle efficiently.
8549 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8553 // Otherwise fall back to a SHUFPS lowering strategy.
8554 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8557 /// \brief Lower 4-lane i32 vector shuffles.
8559 /// We try to handle these with integer-domain shuffles where we can, but for
8560 /// blends we use the floating point domain blend instructions.
8561 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8562 const X86Subtarget *Subtarget,
8563 SelectionDAG &DAG) {
8565 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8566 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8567 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8568 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8569 ArrayRef<int> Mask = SVOp->getMask();
8570 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8572 // Whenever we can lower this as a zext, that instruction is strictly faster
8573 // than any alternative. It also allows us to fold memory operands into the
8574 // shuffle in many cases.
8575 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8576 Mask, Subtarget, DAG))
8580 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8582 if (NumV2Elements == 0) {
8583 // Check for being able to broadcast a single element.
8584 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8585 Mask, Subtarget, DAG))
8588 // Straight shuffle of a single input vector. For everything from SSE2
8589 // onward this has a single fast instruction with no scary immediates.
8590 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8591 // but we aren't actually going to use the UNPCK instruction because doing
8592 // so prevents folding a load into this instruction or making a copy.
8593 const int UnpackLoMask[] = {0, 0, 1, 1};
8594 const int UnpackHiMask[] = {2, 2, 3, 3};
8595 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8596 Mask = UnpackLoMask;
8597 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8598 Mask = UnpackHiMask;
8600 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8601 getV4X86ShuffleImm8ForMask(Mask, DAG));
8604 // Try to use byte shift instructions.
8605 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8606 DL, MVT::v4i32, V1, V2, Mask, DAG))
8609 // There are special ways we can lower some single-element blends.
8610 if (NumV2Elements == 1)
8611 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8612 Mask, Subtarget, DAG))
8615 // Use dedicated unpack instructions for masks that match their pattern.
8616 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8617 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8618 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8619 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8621 if (Subtarget->hasSSE41())
8622 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8626 // Try to use byte rotation instructions.
8627 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8628 if (Subtarget->hasSSSE3())
8629 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8630 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8633 // We implement this with SHUFPS because it can blend from two vectors.
8634 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8635 // up the inputs, bypassing domain shift penalties that we would encur if we
8636 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8638 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8639 DAG.getVectorShuffle(
8641 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8642 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8645 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8646 /// shuffle lowering, and the most complex part.
8648 /// The lowering strategy is to try to form pairs of input lanes which are
8649 /// targeted at the same half of the final vector, and then use a dword shuffle
8650 /// to place them onto the right half, and finally unpack the paired lanes into
8651 /// their final position.
8653 /// The exact breakdown of how to form these dword pairs and align them on the
8654 /// correct sides is really tricky. See the comments within the function for
8655 /// more of the details.
8656 static SDValue lowerV8I16SingleInputVectorShuffle(
8657 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8658 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8659 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8660 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8661 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8663 SmallVector<int, 4> LoInputs;
8664 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8665 [](int M) { return M >= 0; });
8666 std::sort(LoInputs.begin(), LoInputs.end());
8667 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8668 SmallVector<int, 4> HiInputs;
8669 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8670 [](int M) { return M >= 0; });
8671 std::sort(HiInputs.begin(), HiInputs.end());
8672 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8674 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8675 int NumHToL = LoInputs.size() - NumLToL;
8677 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8678 int NumHToH = HiInputs.size() - NumLToH;
8679 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8680 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8681 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8682 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8684 // Check for being able to broadcast a single element.
8685 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8686 Mask, Subtarget, DAG))
8689 // Try to use byte shift instructions.
8690 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8691 DL, MVT::v8i16, V, V, Mask, DAG))
8694 // Use dedicated unpack instructions for masks that match their pattern.
8695 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8696 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8697 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8698 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8700 // Try to use byte rotation instructions.
8701 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8702 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8705 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8706 // such inputs we can swap two of the dwords across the half mark and end up
8707 // with <=2 inputs to each half in each half. Once there, we can fall through
8708 // to the generic code below. For example:
8710 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8711 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8713 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8714 // and an existing 2-into-2 on the other half. In this case we may have to
8715 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8716 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8717 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8718 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8719 // half than the one we target for fixing) will be fixed when we re-enter this
8720 // path. We will also combine away any sequence of PSHUFD instructions that
8721 // result into a single instruction. Here is an example of the tricky case:
8723 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8724 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8726 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8728 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8729 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8731 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8732 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8734 // The result is fine to be handled by the generic logic.
8735 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8736 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8737 int AOffset, int BOffset) {
8738 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8739 "Must call this with A having 3 or 1 inputs from the A half.");
8740 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8741 "Must call this with B having 1 or 3 inputs from the B half.");
8742 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8743 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8745 // Compute the index of dword with only one word among the three inputs in
8746 // a half by taking the sum of the half with three inputs and subtracting
8747 // the sum of the actual three inputs. The difference is the remaining
8750 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8751 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8752 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8753 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8754 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8755 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8756 int TripleNonInputIdx =
8757 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8758 TripleDWord = TripleNonInputIdx / 2;
8760 // We use xor with one to compute the adjacent DWord to whichever one the
8762 OneInputDWord = (OneInput / 2) ^ 1;
8764 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8765 // and BToA inputs. If there is also such a problem with the BToB and AToB
8766 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8767 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8768 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8769 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8770 // Compute how many inputs will be flipped by swapping these DWords. We
8772 // to balance this to ensure we don't form a 3-1 shuffle in the other
8774 int NumFlippedAToBInputs =
8775 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8776 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8777 int NumFlippedBToBInputs =
8778 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8779 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8780 if ((NumFlippedAToBInputs == 1 &&
8781 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8782 (NumFlippedBToBInputs == 1 &&
8783 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8784 // We choose whether to fix the A half or B half based on whether that
8785 // half has zero flipped inputs. At zero, we may not be able to fix it
8786 // with that half. We also bias towards fixing the B half because that
8787 // will more commonly be the high half, and we have to bias one way.
8788 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8789 ArrayRef<int> Inputs) {
8790 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8791 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8792 PinnedIdx ^ 1) != Inputs.end();
8793 // Determine whether the free index is in the flipped dword or the
8794 // unflipped dword based on where the pinned index is. We use this bit
8795 // in an xor to conditionally select the adjacent dword.
8796 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8797 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8798 FixFreeIdx) != Inputs.end();
8799 if (IsFixIdxInput == IsFixFreeIdxInput)
8801 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8802 FixFreeIdx) != Inputs.end();
8803 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8804 "We need to be changing the number of flipped inputs!");
8805 int PSHUFHalfMask[] = {0, 1, 2, 3};
8806 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8807 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8809 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8812 if (M != -1 && M == FixIdx)
8814 else if (M != -1 && M == FixFreeIdx)
8817 if (NumFlippedBToBInputs != 0) {
8819 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8820 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8822 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8824 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8825 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8830 int PSHUFDMask[] = {0, 1, 2, 3};
8831 PSHUFDMask[ADWord] = BDWord;
8832 PSHUFDMask[BDWord] = ADWord;
8833 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8834 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8835 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8836 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8838 // Adjust the mask to match the new locations of A and B.
8840 if (M != -1 && M/2 == ADWord)
8841 M = 2 * BDWord + M % 2;
8842 else if (M != -1 && M/2 == BDWord)
8843 M = 2 * ADWord + M % 2;
8845 // Recurse back into this routine to re-compute state now that this isn't
8846 // a 3 and 1 problem.
8847 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8850 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8851 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8852 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8853 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8855 // At this point there are at most two inputs to the low and high halves from
8856 // each half. That means the inputs can always be grouped into dwords and
8857 // those dwords can then be moved to the correct half with a dword shuffle.
8858 // We use at most one low and one high word shuffle to collect these paired
8859 // inputs into dwords, and finally a dword shuffle to place them.
8860 int PSHUFLMask[4] = {-1, -1, -1, -1};
8861 int PSHUFHMask[4] = {-1, -1, -1, -1};
8862 int PSHUFDMask[4] = {-1, -1, -1, -1};
8864 // First fix the masks for all the inputs that are staying in their
8865 // original halves. This will then dictate the targets of the cross-half
8867 auto fixInPlaceInputs =
8868 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8869 MutableArrayRef<int> SourceHalfMask,
8870 MutableArrayRef<int> HalfMask, int HalfOffset) {
8871 if (InPlaceInputs.empty())
8873 if (InPlaceInputs.size() == 1) {
8874 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8875 InPlaceInputs[0] - HalfOffset;
8876 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8879 if (IncomingInputs.empty()) {
8880 // Just fix all of the in place inputs.
8881 for (int Input : InPlaceInputs) {
8882 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8883 PSHUFDMask[Input / 2] = Input / 2;
8888 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8889 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8890 InPlaceInputs[0] - HalfOffset;
8891 // Put the second input next to the first so that they are packed into
8892 // a dword. We find the adjacent index by toggling the low bit.
8893 int AdjIndex = InPlaceInputs[0] ^ 1;
8894 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8895 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8896 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8898 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8899 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8901 // Now gather the cross-half inputs and place them into a free dword of
8902 // their target half.
8903 // FIXME: This operation could almost certainly be simplified dramatically to
8904 // look more like the 3-1 fixing operation.
8905 auto moveInputsToRightHalf = [&PSHUFDMask](
8906 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8907 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8908 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8910 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8911 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8913 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8915 int LowWord = Word & ~1;
8916 int HighWord = Word | 1;
8917 return isWordClobbered(SourceHalfMask, LowWord) ||
8918 isWordClobbered(SourceHalfMask, HighWord);
8921 if (IncomingInputs.empty())
8924 if (ExistingInputs.empty()) {
8925 // Map any dwords with inputs from them into the right half.
8926 for (int Input : IncomingInputs) {
8927 // If the source half mask maps over the inputs, turn those into
8928 // swaps and use the swapped lane.
8929 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8930 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8931 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8932 Input - SourceOffset;
8933 // We have to swap the uses in our half mask in one sweep.
8934 for (int &M : HalfMask)
8935 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8937 else if (M == Input)
8938 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8940 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8941 Input - SourceOffset &&
8942 "Previous placement doesn't match!");
8944 // Note that this correctly re-maps both when we do a swap and when
8945 // we observe the other side of the swap above. We rely on that to
8946 // avoid swapping the members of the input list directly.
8947 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8950 // Map the input's dword into the correct half.
8951 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8952 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8954 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8956 "Previous placement doesn't match!");
8959 // And just directly shift any other-half mask elements to be same-half
8960 // as we will have mirrored the dword containing the element into the
8961 // same position within that half.
8962 for (int &M : HalfMask)
8963 if (M >= SourceOffset && M < SourceOffset + 4) {
8964 M = M - SourceOffset + DestOffset;
8965 assert(M >= 0 && "This should never wrap below zero!");
8970 // Ensure we have the input in a viable dword of its current half. This
8971 // is particularly tricky because the original position may be clobbered
8972 // by inputs being moved and *staying* in that half.
8973 if (IncomingInputs.size() == 1) {
8974 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8975 int InputFixed = std::find(std::begin(SourceHalfMask),
8976 std::end(SourceHalfMask), -1) -
8977 std::begin(SourceHalfMask) + SourceOffset;
8978 SourceHalfMask[InputFixed - SourceOffset] =
8979 IncomingInputs[0] - SourceOffset;
8980 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8982 IncomingInputs[0] = InputFixed;
8984 } else if (IncomingInputs.size() == 2) {
8985 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8986 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8987 // We have two non-adjacent or clobbered inputs we need to extract from
8988 // the source half. To do this, we need to map them into some adjacent
8989 // dword slot in the source mask.
8990 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8991 IncomingInputs[1] - SourceOffset};
8993 // If there is a free slot in the source half mask adjacent to one of
8994 // the inputs, place the other input in it. We use (Index XOR 1) to
8995 // compute an adjacent index.
8996 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8997 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8998 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8999 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9000 InputsFixed[1] = InputsFixed[0] ^ 1;
9001 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9002 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9003 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9004 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9005 InputsFixed[0] = InputsFixed[1] ^ 1;
9006 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9007 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9008 // The two inputs are in the same DWord but it is clobbered and the
9009 // adjacent DWord isn't used at all. Move both inputs to the free
9011 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9012 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9013 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9014 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9016 // The only way we hit this point is if there is no clobbering
9017 // (because there are no off-half inputs to this half) and there is no
9018 // free slot adjacent to one of the inputs. In this case, we have to
9019 // swap an input with a non-input.
9020 for (int i = 0; i < 4; ++i)
9021 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9022 "We can't handle any clobbers here!");
9023 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9024 "Cannot have adjacent inputs here!");
9026 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9027 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9029 // We also have to update the final source mask in this case because
9030 // it may need to undo the above swap.
9031 for (int &M : FinalSourceHalfMask)
9032 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9033 M = InputsFixed[1] + SourceOffset;
9034 else if (M == InputsFixed[1] + SourceOffset)
9035 M = (InputsFixed[0] ^ 1) + SourceOffset;
9037 InputsFixed[1] = InputsFixed[0] ^ 1;
9040 // Point everything at the fixed inputs.
9041 for (int &M : HalfMask)
9042 if (M == IncomingInputs[0])
9043 M = InputsFixed[0] + SourceOffset;
9044 else if (M == IncomingInputs[1])
9045 M = InputsFixed[1] + SourceOffset;
9047 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9048 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9051 llvm_unreachable("Unhandled input size!");
9054 // Now hoist the DWord down to the right half.
9055 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9056 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9057 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9058 for (int &M : HalfMask)
9059 for (int Input : IncomingInputs)
9061 M = FreeDWord * 2 + Input % 2;
9063 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9064 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9065 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9066 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9068 // Now enact all the shuffles we've computed to move the inputs into their
9070 if (!isNoopShuffleMask(PSHUFLMask))
9071 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9072 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9073 if (!isNoopShuffleMask(PSHUFHMask))
9074 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9075 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9076 if (!isNoopShuffleMask(PSHUFDMask))
9077 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9078 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9079 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9080 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9082 // At this point, each half should contain all its inputs, and we can then
9083 // just shuffle them into their final position.
9084 assert(std::count_if(LoMask.begin(), LoMask.end(),
9085 [](int M) { return M >= 4; }) == 0 &&
9086 "Failed to lift all the high half inputs to the low mask!");
9087 assert(std::count_if(HiMask.begin(), HiMask.end(),
9088 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9089 "Failed to lift all the low half inputs to the high mask!");
9091 // Do a half shuffle for the low mask.
9092 if (!isNoopShuffleMask(LoMask))
9093 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9094 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9096 // Do a half shuffle with the high mask after shifting its values down.
9097 for (int &M : HiMask)
9100 if (!isNoopShuffleMask(HiMask))
9101 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9102 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9107 /// \brief Detect whether the mask pattern should be lowered through
9110 /// This essentially tests whether viewing the mask as an interleaving of two
9111 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9112 /// lowering it through interleaving is a significantly better strategy.
9113 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9114 int NumEvenInputs[2] = {0, 0};
9115 int NumOddInputs[2] = {0, 0};
9116 int NumLoInputs[2] = {0, 0};
9117 int NumHiInputs[2] = {0, 0};
9118 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9122 int InputIdx = Mask[i] >= Size;
9125 ++NumLoInputs[InputIdx];
9127 ++NumHiInputs[InputIdx];
9130 ++NumEvenInputs[InputIdx];
9132 ++NumOddInputs[InputIdx];
9135 // The minimum number of cross-input results for both the interleaved and
9136 // split cases. If interleaving results in fewer cross-input results, return
9138 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9139 NumEvenInputs[0] + NumOddInputs[1]);
9140 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9141 NumLoInputs[0] + NumHiInputs[1]);
9142 return InterleavedCrosses < SplitCrosses;
9145 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9147 /// This strategy only works when the inputs from each vector fit into a single
9148 /// half of that vector, and generally there are not so many inputs as to leave
9149 /// the in-place shuffles required highly constrained (and thus expensive). It
9150 /// shifts all the inputs into a single side of both input vectors and then
9151 /// uses an unpack to interleave these inputs in a single vector. At that
9152 /// point, we will fall back on the generic single input shuffle lowering.
9153 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9155 MutableArrayRef<int> Mask,
9156 const X86Subtarget *Subtarget,
9157 SelectionDAG &DAG) {
9158 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9159 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9160 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9161 for (int i = 0; i < 8; ++i)
9162 if (Mask[i] >= 0 && Mask[i] < 4)
9163 LoV1Inputs.push_back(i);
9164 else if (Mask[i] >= 4 && Mask[i] < 8)
9165 HiV1Inputs.push_back(i);
9166 else if (Mask[i] >= 8 && Mask[i] < 12)
9167 LoV2Inputs.push_back(i);
9168 else if (Mask[i] >= 12)
9169 HiV2Inputs.push_back(i);
9171 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9172 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9175 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9176 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9177 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9179 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9180 HiV1Inputs.size() + HiV2Inputs.size();
9182 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9183 ArrayRef<int> HiInputs, bool MoveToLo,
9185 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9186 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9187 if (BadInputs.empty())
9190 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9191 int MoveOffset = MoveToLo ? 0 : 4;
9193 if (GoodInputs.empty()) {
9194 for (int BadInput : BadInputs) {
9195 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9196 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9199 if (GoodInputs.size() == 2) {
9200 // If the low inputs are spread across two dwords, pack them into
9202 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9203 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9204 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9205 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9207 // Otherwise pin the good inputs.
9208 for (int GoodInput : GoodInputs)
9209 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9212 if (BadInputs.size() == 2) {
9213 // If we have two bad inputs then there may be either one or two good
9214 // inputs fixed in place. Find a fixed input, and then find the *other*
9215 // two adjacent indices by using modular arithmetic.
9217 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9218 [](int M) { return M >= 0; }) -
9219 std::begin(MoveMask);
9221 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9222 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9223 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9224 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9225 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9226 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9227 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9229 assert(BadInputs.size() == 1 && "All sizes handled");
9230 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9231 std::end(MoveMask), -1) -
9232 std::begin(MoveMask);
9233 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9234 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9238 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9241 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9243 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9246 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9247 // cross-half traffic in the final shuffle.
9249 // Munge the mask to be a single-input mask after the unpack merges the
9253 M = 2 * (M % 4) + (M / 8);
9255 return DAG.getVectorShuffle(
9256 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9257 DL, MVT::v8i16, V1, V2),
9258 DAG.getUNDEF(MVT::v8i16), Mask);
9261 /// \brief Generic lowering of 8-lane i16 shuffles.
9263 /// This handles both single-input shuffles and combined shuffle/blends with
9264 /// two inputs. The single input shuffles are immediately delegated to
9265 /// a dedicated lowering routine.
9267 /// The blends are lowered in one of three fundamental ways. If there are few
9268 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9269 /// of the input is significantly cheaper when lowered as an interleaving of
9270 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9271 /// halves of the inputs separately (making them have relatively few inputs)
9272 /// and then concatenate them.
9273 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9274 const X86Subtarget *Subtarget,
9275 SelectionDAG &DAG) {
9277 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9278 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9279 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9281 ArrayRef<int> OrigMask = SVOp->getMask();
9282 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9283 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9284 MutableArrayRef<int> Mask(MaskStorage);
9286 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9288 // Whenever we can lower this as a zext, that instruction is strictly faster
9289 // than any alternative.
9290 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9291 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9294 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9295 auto isV2 = [](int M) { return M >= 8; };
9297 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9298 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9300 if (NumV2Inputs == 0)
9301 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9303 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9304 "to be V1-input shuffles.");
9306 // Try to use byte shift instructions.
9307 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9308 DL, MVT::v8i16, V1, V2, Mask, DAG))
9311 // There are special ways we can lower some single-element blends.
9312 if (NumV2Inputs == 1)
9313 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9314 Mask, Subtarget, DAG))
9317 // Use dedicated unpack instructions for masks that match their pattern.
9318 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9319 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9320 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9321 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9323 if (Subtarget->hasSSE41())
9324 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9328 // Try to use byte rotation instructions.
9329 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9330 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9333 if (NumV1Inputs + NumV2Inputs <= 4)
9334 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9336 // Check whether an interleaving lowering is likely to be more efficient.
9337 // This isn't perfect but it is a strong heuristic that tends to work well on
9338 // the kinds of shuffles that show up in practice.
9340 // FIXME: Handle 1x, 2x, and 4x interleaving.
9341 if (shouldLowerAsInterleaving(Mask)) {
9342 // FIXME: Figure out whether we should pack these into the low or high
9345 int EMask[8], OMask[8];
9346 for (int i = 0; i < 4; ++i) {
9347 EMask[i] = Mask[2*i];
9348 OMask[i] = Mask[2*i + 1];
9353 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9354 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9356 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9359 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9360 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9362 for (int i = 0; i < 4; ++i) {
9363 LoBlendMask[i] = Mask[i];
9364 HiBlendMask[i] = Mask[i + 4];
9367 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9368 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9369 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9370 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9372 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9373 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9376 /// \brief Check whether a compaction lowering can be done by dropping even
9377 /// elements and compute how many times even elements must be dropped.
9379 /// This handles shuffles which take every Nth element where N is a power of
9380 /// two. Example shuffle masks:
9382 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9383 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9384 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9385 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9386 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9387 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9389 /// Any of these lanes can of course be undef.
9391 /// This routine only supports N <= 3.
9392 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9395 /// \returns N above, or the number of times even elements must be dropped if
9396 /// there is such a number. Otherwise returns zero.
9397 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9398 // Figure out whether we're looping over two inputs or just one.
9399 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9401 // The modulus for the shuffle vector entries is based on whether this is
9402 // a single input or not.
9403 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9404 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9405 "We should only be called with masks with a power-of-2 size!");
9407 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9409 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9410 // and 2^3 simultaneously. This is because we may have ambiguity with
9411 // partially undef inputs.
9412 bool ViableForN[3] = {true, true, true};
9414 for (int i = 0, e = Mask.size(); i < e; ++i) {
9415 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9420 bool IsAnyViable = false;
9421 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9422 if (ViableForN[j]) {
9425 // The shuffle mask must be equal to (i * 2^N) % M.
9426 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9429 ViableForN[j] = false;
9431 // Early exit if we exhaust the possible powers of two.
9436 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9440 // Return 0 as there is no viable power of two.
9444 /// \brief Generic lowering of v16i8 shuffles.
9446 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9447 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9448 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9449 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9451 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9452 const X86Subtarget *Subtarget,
9453 SelectionDAG &DAG) {
9455 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9456 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9457 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9459 ArrayRef<int> OrigMask = SVOp->getMask();
9460 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9462 // Try to use byte shift instructions.
9463 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9464 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9467 // Try to use byte rotation instructions.
9468 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9469 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9472 // Try to use a zext lowering.
9473 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9474 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9477 int MaskStorage[16] = {
9478 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9479 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9480 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9481 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9482 MutableArrayRef<int> Mask(MaskStorage);
9483 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9484 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9487 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9489 // For single-input shuffles, there are some nicer lowering tricks we can use.
9490 if (NumV2Elements == 0) {
9491 // Check for being able to broadcast a single element.
9492 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9493 Mask, Subtarget, DAG))
9496 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9497 // Notably, this handles splat and partial-splat shuffles more efficiently.
9498 // However, it only makes sense if the pre-duplication shuffle simplifies
9499 // things significantly. Currently, this means we need to be able to
9500 // express the pre-duplication shuffle as an i16 shuffle.
9502 // FIXME: We should check for other patterns which can be widened into an
9503 // i16 shuffle as well.
9504 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9505 for (int i = 0; i < 16; i += 2)
9506 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9511 auto tryToWidenViaDuplication = [&]() -> SDValue {
9512 if (!canWidenViaDuplication(Mask))
9514 SmallVector<int, 4> LoInputs;
9515 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9516 [](int M) { return M >= 0 && M < 8; });
9517 std::sort(LoInputs.begin(), LoInputs.end());
9518 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9520 SmallVector<int, 4> HiInputs;
9521 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9522 [](int M) { return M >= 8; });
9523 std::sort(HiInputs.begin(), HiInputs.end());
9524 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9527 bool TargetLo = LoInputs.size() >= HiInputs.size();
9528 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9529 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9531 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9532 SmallDenseMap<int, int, 8> LaneMap;
9533 for (int I : InPlaceInputs) {
9534 PreDupI16Shuffle[I/2] = I/2;
9537 int j = TargetLo ? 0 : 4, je = j + 4;
9538 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9539 // Check if j is already a shuffle of this input. This happens when
9540 // there are two adjacent bytes after we move the low one.
9541 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9542 // If we haven't yet mapped the input, search for a slot into which
9544 while (j < je && PreDupI16Shuffle[j] != -1)
9548 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9551 // Map this input with the i16 shuffle.
9552 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9555 // Update the lane map based on the mapping we ended up with.
9556 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9559 ISD::BITCAST, DL, MVT::v16i8,
9560 DAG.getVectorShuffle(MVT::v8i16, DL,
9561 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9562 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9564 // Unpack the bytes to form the i16s that will be shuffled into place.
9565 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9566 MVT::v16i8, V1, V1);
9568 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9569 for (int i = 0; i < 16; ++i)
9570 if (Mask[i] != -1) {
9571 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9572 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9573 if (PostDupI16Shuffle[i / 2] == -1)
9574 PostDupI16Shuffle[i / 2] = MappedMask;
9576 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9577 "Conflicting entrties in the original shuffle!");
9580 ISD::BITCAST, DL, MVT::v16i8,
9581 DAG.getVectorShuffle(MVT::v8i16, DL,
9582 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9583 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9585 if (SDValue V = tryToWidenViaDuplication())
9589 // Check whether an interleaving lowering is likely to be more efficient.
9590 // This isn't perfect but it is a strong heuristic that tends to work well on
9591 // the kinds of shuffles that show up in practice.
9593 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9594 if (shouldLowerAsInterleaving(Mask)) {
9595 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9596 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9598 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9599 return (M >= 8 && M < 16) || M >= 24;
9601 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9602 -1, -1, -1, -1, -1, -1, -1, -1};
9603 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9604 -1, -1, -1, -1, -1, -1, -1, -1};
9605 bool UnpackLo = NumLoHalf >= NumHiHalf;
9606 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9607 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9608 for (int i = 0; i < 8; ++i) {
9609 TargetEMask[i] = Mask[2 * i];
9610 TargetOMask[i] = Mask[2 * i + 1];
9613 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9614 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9616 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9617 MVT::v16i8, Evens, Odds);
9620 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9621 // with PSHUFB. It is important to do this before we attempt to generate any
9622 // blends but after all of the single-input lowerings. If the single input
9623 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9624 // want to preserve that and we can DAG combine any longer sequences into
9625 // a PSHUFB in the end. But once we start blending from multiple inputs,
9626 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9627 // and there are *very* few patterns that would actually be faster than the
9628 // PSHUFB approach because of its ability to zero lanes.
9630 // FIXME: The only exceptions to the above are blends which are exact
9631 // interleavings with direct instructions supporting them. We currently don't
9632 // handle those well here.
9633 if (Subtarget->hasSSSE3()) {
9636 bool V1InUse = false;
9637 bool V2InUse = false;
9638 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9640 for (int i = 0; i < 16; ++i) {
9641 if (Mask[i] == -1) {
9642 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9644 const int ZeroMask = 0x80;
9645 int V1Idx = (Mask[i] < 16 ? Mask[i] : ZeroMask);
9646 int V2Idx = (Mask[i] < 16 ? ZeroMask : Mask[i] - 16);
9648 V1Idx = V2Idx = ZeroMask;
9649 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
9650 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
9651 V1InUse |= (ZeroMask != V1Idx);
9652 V2InUse |= (ZeroMask != V2Idx);
9657 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9658 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9660 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9661 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9663 // If we need shuffled inputs from both, blend the two.
9664 if (V1InUse && V2InUse)
9665 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9667 return V1; // Single inputs are easy.
9669 return V2; // Single inputs are easy.
9670 // Shuffling to a zeroable vector.
9671 return getZeroVector(MVT::v16i8, Subtarget, DAG, DL);
9674 // There are special ways we can lower some single-element blends.
9675 if (NumV2Elements == 1)
9676 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9677 Mask, Subtarget, DAG))
9680 // Check whether a compaction lowering can be done. This handles shuffles
9681 // which take every Nth element for some even N. See the helper function for
9684 // We special case these as they can be particularly efficiently handled with
9685 // the PACKUSB instruction on x86 and they show up in common patterns of
9686 // rearranging bytes to truncate wide elements.
9687 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9688 // NumEvenDrops is the power of two stride of the elements. Another way of
9689 // thinking about it is that we need to drop the even elements this many
9690 // times to get the original input.
9691 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9693 // First we need to zero all the dropped bytes.
9694 assert(NumEvenDrops <= 3 &&
9695 "No support for dropping even elements more than 3 times.");
9696 // We use the mask type to pick which bytes are preserved based on how many
9697 // elements are dropped.
9698 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9699 SDValue ByteClearMask =
9700 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9701 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9702 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9704 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9706 // Now pack things back together.
9707 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9708 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9709 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9710 for (int i = 1; i < NumEvenDrops; ++i) {
9711 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9712 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9718 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9719 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9720 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9721 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9723 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9724 MutableArrayRef<int> V1HalfBlendMask,
9725 MutableArrayRef<int> V2HalfBlendMask) {
9726 for (int i = 0; i < 8; ++i)
9727 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9728 V1HalfBlendMask[i] = HalfMask[i];
9730 } else if (HalfMask[i] >= 16) {
9731 V2HalfBlendMask[i] = HalfMask[i] - 16;
9732 HalfMask[i] = i + 8;
9735 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9736 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9738 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9740 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9741 MutableArrayRef<int> HiBlendMask) {
9743 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9744 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9746 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9747 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9748 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9749 [](int M) { return M >= 0 && M % 2 == 1; })) {
9750 // Use a mask to drop the high bytes.
9751 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9752 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9753 DAG.getConstant(0x00FF, MVT::v8i16));
9755 // This will be a single vector shuffle instead of a blend so nuke V2.
9756 V2 = DAG.getUNDEF(MVT::v8i16);
9758 // Squash the masks to point directly into V1.
9759 for (int &M : LoBlendMask)
9762 for (int &M : HiBlendMask)
9766 // Otherwise just unpack the low half of V into V1 and the high half into
9767 // V2 so that we can blend them as i16s.
9768 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9769 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9770 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9771 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9774 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9775 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9776 return std::make_pair(BlendedLo, BlendedHi);
9778 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9779 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9780 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9782 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9783 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9785 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9788 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9790 /// This routine breaks down the specific type of 128-bit shuffle and
9791 /// dispatches to the lowering routines accordingly.
9792 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9793 MVT VT, const X86Subtarget *Subtarget,
9794 SelectionDAG &DAG) {
9795 switch (VT.SimpleTy) {
9797 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9799 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9801 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9803 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9805 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9807 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9810 llvm_unreachable("Unimplemented!");
9814 /// \brief Helper function to test whether a shuffle mask could be
9815 /// simplified by widening the elements being shuffled.
9817 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9818 /// leaves it in an unspecified state.
9820 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9821 /// shuffle masks. The latter have the special property of a '-2' representing
9822 /// a zero-ed lane of a vector.
9823 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9824 SmallVectorImpl<int> &WidenedMask) {
9825 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9826 // If both elements are undef, its trivial.
9827 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9828 WidenedMask.push_back(SM_SentinelUndef);
9832 // Check for an undef mask and a mask value properly aligned to fit with
9833 // a pair of values. If we find such a case, use the non-undef mask's value.
9834 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9835 WidenedMask.push_back(Mask[i + 1] / 2);
9838 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9839 WidenedMask.push_back(Mask[i] / 2);
9843 // When zeroing, we need to spread the zeroing across both lanes to widen.
9844 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9845 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9846 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9847 WidenedMask.push_back(SM_SentinelZero);
9853 // Finally check if the two mask values are adjacent and aligned with
9855 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9856 WidenedMask.push_back(Mask[i] / 2);
9860 // Otherwise we can't safely widen the elements used in this shuffle.
9863 assert(WidenedMask.size() == Mask.size() / 2 &&
9864 "Incorrect size of mask after widening the elements!");
9869 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9871 /// This routine just extracts two subvectors, shuffles them independently, and
9872 /// then concatenates them back together. This should work effectively with all
9873 /// AVX vector shuffle types.
9874 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9875 SDValue V2, ArrayRef<int> Mask,
9876 SelectionDAG &DAG) {
9877 assert(VT.getSizeInBits() >= 256 &&
9878 "Only for 256-bit or wider vector shuffles!");
9879 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9880 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9882 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9883 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9885 int NumElements = VT.getVectorNumElements();
9886 int SplitNumElements = NumElements / 2;
9887 MVT ScalarVT = VT.getScalarType();
9888 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9890 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9891 DAG.getIntPtrConstant(0));
9892 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9893 DAG.getIntPtrConstant(SplitNumElements));
9894 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9895 DAG.getIntPtrConstant(0));
9896 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9897 DAG.getIntPtrConstant(SplitNumElements));
9899 // Now create two 4-way blends of these half-width vectors.
9900 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9901 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9902 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9903 for (int i = 0; i < SplitNumElements; ++i) {
9904 int M = HalfMask[i];
9905 if (M >= NumElements) {
9906 if (M >= NumElements + SplitNumElements)
9910 V2BlendMask.push_back(M - NumElements);
9911 V1BlendMask.push_back(-1);
9912 BlendMask.push_back(SplitNumElements + i);
9913 } else if (M >= 0) {
9914 if (M >= SplitNumElements)
9918 V2BlendMask.push_back(-1);
9919 V1BlendMask.push_back(M);
9920 BlendMask.push_back(i);
9922 V2BlendMask.push_back(-1);
9923 V1BlendMask.push_back(-1);
9924 BlendMask.push_back(-1);
9928 // Because the lowering happens after all combining takes place, we need to
9929 // manually combine these blend masks as much as possible so that we create
9930 // a minimal number of high-level vector shuffle nodes.
9932 // First try just blending the halves of V1 or V2.
9933 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9934 return DAG.getUNDEF(SplitVT);
9935 if (!UseLoV2 && !UseHiV2)
9936 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9937 if (!UseLoV1 && !UseHiV1)
9938 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9940 SDValue V1Blend, V2Blend;
9941 if (UseLoV1 && UseHiV1) {
9943 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9945 // We only use half of V1 so map the usage down into the final blend mask.
9946 V1Blend = UseLoV1 ? LoV1 : HiV1;
9947 for (int i = 0; i < SplitNumElements; ++i)
9948 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9949 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9951 if (UseLoV2 && UseHiV2) {
9953 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9955 // We only use half of V2 so map the usage down into the final blend mask.
9956 V2Blend = UseLoV2 ? LoV2 : HiV2;
9957 for (int i = 0; i < SplitNumElements; ++i)
9958 if (BlendMask[i] >= SplitNumElements)
9959 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9961 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9963 SDValue Lo = HalfBlend(LoMask);
9964 SDValue Hi = HalfBlend(HiMask);
9965 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9968 /// \brief Either split a vector in halves or decompose the shuffles and the
9971 /// This is provided as a good fallback for many lowerings of non-single-input
9972 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9973 /// between splitting the shuffle into 128-bit components and stitching those
9974 /// back together vs. extracting the single-input shuffles and blending those
9976 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9977 SDValue V2, ArrayRef<int> Mask,
9978 SelectionDAG &DAG) {
9979 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9980 "lower single-input shuffles as it "
9981 "could then recurse on itself.");
9982 int Size = Mask.size();
9984 // If this can be modeled as a broadcast of two elements followed by a blend,
9985 // prefer that lowering. This is especially important because broadcasts can
9986 // often fold with memory operands.
9987 auto DoBothBroadcast = [&] {
9988 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9991 if (V2BroadcastIdx == -1)
9992 V2BroadcastIdx = M - Size;
9993 else if (M - Size != V2BroadcastIdx)
9995 } else if (M >= 0) {
9996 if (V1BroadcastIdx == -1)
9998 else if (M != V1BroadcastIdx)
10003 if (DoBothBroadcast())
10004 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10007 // If the inputs all stem from a single 128-bit lane of each input, then we
10008 // split them rather than blending because the split will decompose to
10009 // unusually few instructions.
10010 int LaneCount = VT.getSizeInBits() / 128;
10011 int LaneSize = Size / LaneCount;
10012 SmallBitVector LaneInputs[2];
10013 LaneInputs[0].resize(LaneCount, false);
10014 LaneInputs[1].resize(LaneCount, false);
10015 for (int i = 0; i < Size; ++i)
10017 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10018 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10019 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10021 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10022 // that the decomposed single-input shuffles don't end up here.
10023 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10026 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10027 /// a permutation and blend of those lanes.
10029 /// This essentially blends the out-of-lane inputs to each lane into the lane
10030 /// from a permuted copy of the vector. This lowering strategy results in four
10031 /// instructions in the worst case for a single-input cross lane shuffle which
10032 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10033 /// of. Special cases for each particular shuffle pattern should be handled
10034 /// prior to trying this lowering.
10035 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10036 SDValue V1, SDValue V2,
10037 ArrayRef<int> Mask,
10038 SelectionDAG &DAG) {
10039 // FIXME: This should probably be generalized for 512-bit vectors as well.
10040 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
10041 int LaneSize = Mask.size() / 2;
10043 // If there are only inputs from one 128-bit lane, splitting will in fact be
10044 // less expensive. The flags track wether the given lane contains an element
10045 // that crosses to another lane.
10046 bool LaneCrossing[2] = {false, false};
10047 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10048 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10049 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10050 if (!LaneCrossing[0] || !LaneCrossing[1])
10051 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10053 if (isSingleInputShuffleMask(Mask)) {
10054 SmallVector<int, 32> FlippedBlendMask;
10055 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10056 FlippedBlendMask.push_back(
10057 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10059 : Mask[i] % LaneSize +
10060 (i / LaneSize) * LaneSize + Size));
10062 // Flip the vector, and blend the results which should now be in-lane. The
10063 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10064 // 5 for the high source. The value 3 selects the high half of source 2 and
10065 // the value 2 selects the low half of source 2. We only use source 2 to
10066 // allow folding it into a memory operand.
10067 unsigned PERMMask = 3 | 2 << 4;
10068 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10069 V1, DAG.getConstant(PERMMask, MVT::i8));
10070 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10073 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10074 // will be handled by the above logic and a blend of the results, much like
10075 // other patterns in AVX.
10076 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10079 /// \brief Handle lowering 2-lane 128-bit shuffles.
10080 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10081 SDValue V2, ArrayRef<int> Mask,
10082 const X86Subtarget *Subtarget,
10083 SelectionDAG &DAG) {
10084 // Blends are faster and handle all the non-lane-crossing cases.
10085 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10089 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10090 VT.getVectorNumElements() / 2);
10091 // Check for patterns which can be matched with a single insert of a 128-bit
10093 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10094 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10095 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10096 DAG.getIntPtrConstant(0));
10097 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10098 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10099 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10101 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10102 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10103 DAG.getIntPtrConstant(0));
10104 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10105 DAG.getIntPtrConstant(2));
10106 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10109 // Otherwise form a 128-bit permutation.
10110 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10111 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10112 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10113 DAG.getConstant(PermMask, MVT::i8));
10116 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10117 /// shuffling each lane.
10119 /// This will only succeed when the result of fixing the 128-bit lanes results
10120 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10121 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10122 /// the lane crosses early and then use simpler shuffles within each lane.
10124 /// FIXME: It might be worthwhile at some point to support this without
10125 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10126 /// in x86 only floating point has interesting non-repeating shuffles, and even
10127 /// those are still *marginally* more expensive.
10128 static SDValue lowerVectorShuffleByMerging128BitLanes(
10129 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10130 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10131 assert(!isSingleInputShuffleMask(Mask) &&
10132 "This is only useful with multiple inputs.");
10134 int Size = Mask.size();
10135 int LaneSize = 128 / VT.getScalarSizeInBits();
10136 int NumLanes = Size / LaneSize;
10137 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10139 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10140 // check whether the in-128-bit lane shuffles share a repeating pattern.
10141 SmallVector<int, 4> Lanes;
10142 Lanes.resize(NumLanes, -1);
10143 SmallVector<int, 4> InLaneMask;
10144 InLaneMask.resize(LaneSize, -1);
10145 for (int i = 0; i < Size; ++i) {
10149 int j = i / LaneSize;
10151 if (Lanes[j] < 0) {
10152 // First entry we've seen for this lane.
10153 Lanes[j] = Mask[i] / LaneSize;
10154 } else if (Lanes[j] != Mask[i] / LaneSize) {
10155 // This doesn't match the lane selected previously!
10159 // Check that within each lane we have a consistent shuffle mask.
10160 int k = i % LaneSize;
10161 if (InLaneMask[k] < 0) {
10162 InLaneMask[k] = Mask[i] % LaneSize;
10163 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10164 // This doesn't fit a repeating in-lane mask.
10169 // First shuffle the lanes into place.
10170 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10171 VT.getSizeInBits() / 64);
10172 SmallVector<int, 8> LaneMask;
10173 LaneMask.resize(NumLanes * 2, -1);
10174 for (int i = 0; i < NumLanes; ++i)
10175 if (Lanes[i] >= 0) {
10176 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10177 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10180 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10181 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10182 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10184 // Cast it back to the type we actually want.
10185 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10187 // Now do a simple shuffle that isn't lane crossing.
10188 SmallVector<int, 8> NewMask;
10189 NewMask.resize(Size, -1);
10190 for (int i = 0; i < Size; ++i)
10192 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10193 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10194 "Must not introduce lane crosses at this point!");
10196 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10199 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10202 /// This returns true if the elements from a particular input are already in the
10203 /// slot required by the given mask and require no permutation.
10204 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10205 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10206 int Size = Mask.size();
10207 for (int i = 0; i < Size; ++i)
10208 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10214 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10216 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10217 /// isn't available.
10218 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10219 const X86Subtarget *Subtarget,
10220 SelectionDAG &DAG) {
10222 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10223 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10224 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10225 ArrayRef<int> Mask = SVOp->getMask();
10226 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10228 SmallVector<int, 4> WidenedMask;
10229 if (canWidenShuffleElements(Mask, WidenedMask))
10230 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10233 if (isSingleInputShuffleMask(Mask)) {
10234 // Check for being able to broadcast a single element.
10235 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10236 Mask, Subtarget, DAG))
10239 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10240 // Non-half-crossing single input shuffles can be lowerid with an
10241 // interleaved permutation.
10242 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10243 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10244 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10245 DAG.getConstant(VPERMILPMask, MVT::i8));
10248 // With AVX2 we have direct support for this permutation.
10249 if (Subtarget->hasAVX2())
10250 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10251 getV4X86ShuffleImm8ForMask(Mask, DAG));
10253 // Otherwise, fall back.
10254 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10258 // X86 has dedicated unpack instructions that can handle specific blend
10259 // operations: UNPCKH and UNPCKL.
10260 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10261 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10262 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10263 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10265 // If we have a single input to the zero element, insert that into V1 if we
10266 // can do so cheaply.
10267 int NumV2Elements =
10268 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10269 if (NumV2Elements == 1 && Mask[0] >= 4)
10270 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10271 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10274 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10278 // Check if the blend happens to exactly fit that of SHUFPD.
10279 if ((Mask[0] == -1 || Mask[0] < 2) &&
10280 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10281 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10282 (Mask[3] == -1 || Mask[3] >= 6)) {
10283 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10284 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10285 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10286 DAG.getConstant(SHUFPDMask, MVT::i8));
10288 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10289 (Mask[1] == -1 || Mask[1] < 2) &&
10290 (Mask[2] == -1 || Mask[2] >= 6) &&
10291 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10292 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10293 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10294 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10295 DAG.getConstant(SHUFPDMask, MVT::i8));
10298 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10299 // shuffle. However, if we have AVX2 and either inputs are already in place,
10300 // we will be able to shuffle even across lanes the other input in a single
10301 // instruction so skip this pattern.
10302 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10303 isShuffleMaskInputInPlace(1, Mask))))
10304 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10305 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10308 // If we have AVX2 then we always want to lower with a blend because an v4 we
10309 // can fully permute the elements.
10310 if (Subtarget->hasAVX2())
10311 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10314 // Otherwise fall back on generic lowering.
10315 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10318 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10320 /// This routine is only called when we have AVX2 and thus a reasonable
10321 /// instruction set for v4i64 shuffling..
10322 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10323 const X86Subtarget *Subtarget,
10324 SelectionDAG &DAG) {
10326 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10327 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10329 ArrayRef<int> Mask = SVOp->getMask();
10330 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10331 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10333 SmallVector<int, 4> WidenedMask;
10334 if (canWidenShuffleElements(Mask, WidenedMask))
10335 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10338 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10342 // Check for being able to broadcast a single element.
10343 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10344 Mask, Subtarget, DAG))
10347 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10348 // use lower latency instructions that will operate on both 128-bit lanes.
10349 SmallVector<int, 2> RepeatedMask;
10350 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10351 if (isSingleInputShuffleMask(Mask)) {
10352 int PSHUFDMask[] = {-1, -1, -1, -1};
10353 for (int i = 0; i < 2; ++i)
10354 if (RepeatedMask[i] >= 0) {
10355 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10356 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10358 return DAG.getNode(
10359 ISD::BITCAST, DL, MVT::v4i64,
10360 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10361 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10362 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10365 // Use dedicated unpack instructions for masks that match their pattern.
10366 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10367 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10368 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10369 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10372 // AVX2 provides a direct instruction for permuting a single input across
10374 if (isSingleInputShuffleMask(Mask))
10375 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10376 getV4X86ShuffleImm8ForMask(Mask, DAG));
10378 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10379 // shuffle. However, if we have AVX2 and either inputs are already in place,
10380 // we will be able to shuffle even across lanes the other input in a single
10381 // instruction so skip this pattern.
10382 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10383 isShuffleMaskInputInPlace(1, Mask))))
10384 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10385 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10388 // Otherwise fall back on generic blend lowering.
10389 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10393 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10395 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10396 /// isn't available.
10397 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10398 const X86Subtarget *Subtarget,
10399 SelectionDAG &DAG) {
10401 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10402 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10403 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10404 ArrayRef<int> Mask = SVOp->getMask();
10405 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10407 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10411 // Check for being able to broadcast a single element.
10412 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10413 Mask, Subtarget, DAG))
10416 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10417 // options to efficiently lower the shuffle.
10418 SmallVector<int, 4> RepeatedMask;
10419 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10420 assert(RepeatedMask.size() == 4 &&
10421 "Repeated masks must be half the mask width!");
10422 if (isSingleInputShuffleMask(Mask))
10423 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10424 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10426 // Use dedicated unpack instructions for masks that match their pattern.
10427 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10428 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10429 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10430 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10432 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10433 // have already handled any direct blends. We also need to squash the
10434 // repeated mask into a simulated v4f32 mask.
10435 for (int i = 0; i < 4; ++i)
10436 if (RepeatedMask[i] >= 8)
10437 RepeatedMask[i] -= 4;
10438 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10441 // If we have a single input shuffle with different shuffle patterns in the
10442 // two 128-bit lanes use the variable mask to VPERMILPS.
10443 if (isSingleInputShuffleMask(Mask)) {
10444 SDValue VPermMask[8];
10445 for (int i = 0; i < 8; ++i)
10446 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10447 : DAG.getConstant(Mask[i], MVT::i32);
10448 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10449 return DAG.getNode(
10450 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10451 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10453 if (Subtarget->hasAVX2())
10454 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10455 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10456 DAG.getNode(ISD::BUILD_VECTOR, DL,
10457 MVT::v8i32, VPermMask)),
10460 // Otherwise, fall back.
10461 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10465 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10467 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10468 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10471 // If we have AVX2 then we always want to lower with a blend because at v8 we
10472 // can fully permute the elements.
10473 if (Subtarget->hasAVX2())
10474 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10477 // Otherwise fall back on generic lowering.
10478 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10481 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10483 /// This routine is only called when we have AVX2 and thus a reasonable
10484 /// instruction set for v8i32 shuffling..
10485 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10486 const X86Subtarget *Subtarget,
10487 SelectionDAG &DAG) {
10489 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10490 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10491 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10492 ArrayRef<int> Mask = SVOp->getMask();
10493 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10494 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10496 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10500 // Check for being able to broadcast a single element.
10501 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10502 Mask, Subtarget, DAG))
10505 // If the shuffle mask is repeated in each 128-bit lane we can use more
10506 // efficient instructions that mirror the shuffles across the two 128-bit
10508 SmallVector<int, 4> RepeatedMask;
10509 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10510 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10511 if (isSingleInputShuffleMask(Mask))
10512 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10513 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10515 // Use dedicated unpack instructions for masks that match their pattern.
10516 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10517 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10518 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10519 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10522 // If the shuffle patterns aren't repeated but it is a single input, directly
10523 // generate a cross-lane VPERMD instruction.
10524 if (isSingleInputShuffleMask(Mask)) {
10525 SDValue VPermMask[8];
10526 for (int i = 0; i < 8; ++i)
10527 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10528 : DAG.getConstant(Mask[i], MVT::i32);
10529 return DAG.getNode(
10530 X86ISD::VPERMV, DL, MVT::v8i32,
10531 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10534 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10536 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10537 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10540 // Otherwise fall back on generic blend lowering.
10541 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10545 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10547 /// This routine is only called when we have AVX2 and thus a reasonable
10548 /// instruction set for v16i16 shuffling..
10549 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10550 const X86Subtarget *Subtarget,
10551 SelectionDAG &DAG) {
10553 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10554 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10555 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10556 ArrayRef<int> Mask = SVOp->getMask();
10557 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10558 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10560 // Check for being able to broadcast a single element.
10561 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10562 Mask, Subtarget, DAG))
10565 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10569 // Use dedicated unpack instructions for masks that match their pattern.
10570 if (isShuffleEquivalent(Mask,
10571 // First 128-bit lane:
10572 0, 16, 1, 17, 2, 18, 3, 19,
10573 // Second 128-bit lane:
10574 8, 24, 9, 25, 10, 26, 11, 27))
10575 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10576 if (isShuffleEquivalent(Mask,
10577 // First 128-bit lane:
10578 4, 20, 5, 21, 6, 22, 7, 23,
10579 // Second 128-bit lane:
10580 12, 28, 13, 29, 14, 30, 15, 31))
10581 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10583 if (isSingleInputShuffleMask(Mask)) {
10584 // There are no generalized cross-lane shuffle operations available on i16
10586 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10587 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10590 SDValue PSHUFBMask[32];
10591 for (int i = 0; i < 16; ++i) {
10592 if (Mask[i] == -1) {
10593 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10597 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10598 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10599 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10600 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10602 return DAG.getNode(
10603 ISD::BITCAST, DL, MVT::v16i16,
10605 X86ISD::PSHUFB, DL, MVT::v32i8,
10606 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10607 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10610 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10612 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10613 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10616 // Otherwise fall back on generic lowering.
10617 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10620 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10622 /// This routine is only called when we have AVX2 and thus a reasonable
10623 /// instruction set for v32i8 shuffling..
10624 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10625 const X86Subtarget *Subtarget,
10626 SelectionDAG &DAG) {
10628 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10629 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10630 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10631 ArrayRef<int> Mask = SVOp->getMask();
10632 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10633 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10635 // Check for being able to broadcast a single element.
10636 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10637 Mask, Subtarget, DAG))
10640 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10644 // Use dedicated unpack instructions for masks that match their pattern.
10645 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10647 if (isShuffleEquivalent(
10649 // First 128-bit lane:
10650 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10651 // Second 128-bit lane:
10652 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10653 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10654 if (isShuffleEquivalent(
10656 // First 128-bit lane:
10657 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10658 // Second 128-bit lane:
10659 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10660 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10662 if (isSingleInputShuffleMask(Mask)) {
10663 // There are no generalized cross-lane shuffle operations available on i8
10665 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10666 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10669 SDValue PSHUFBMask[32];
10670 for (int i = 0; i < 32; ++i)
10673 ? DAG.getUNDEF(MVT::i8)
10674 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10676 return DAG.getNode(
10677 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10678 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10681 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10683 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10684 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10687 // Otherwise fall back on generic lowering.
10688 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10691 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10693 /// This routine either breaks down the specific type of a 256-bit x86 vector
10694 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10695 /// together based on the available instructions.
10696 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10697 MVT VT, const X86Subtarget *Subtarget,
10698 SelectionDAG &DAG) {
10700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10701 ArrayRef<int> Mask = SVOp->getMask();
10703 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10704 // check for those subtargets here and avoid much of the subtarget querying in
10705 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10706 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10707 // floating point types there eventually, just immediately cast everything to
10708 // a float and operate entirely in that domain.
10709 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10710 int ElementBits = VT.getScalarSizeInBits();
10711 if (ElementBits < 32)
10712 // No floating point type available, decompose into 128-bit vectors.
10713 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10715 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10716 VT.getVectorNumElements());
10717 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10718 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10719 return DAG.getNode(ISD::BITCAST, DL, VT,
10720 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10723 switch (VT.SimpleTy) {
10725 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10727 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10729 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10731 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10733 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10735 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10738 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10742 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10743 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10744 const X86Subtarget *Subtarget,
10745 SelectionDAG &DAG) {
10747 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10748 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10749 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10750 ArrayRef<int> Mask = SVOp->getMask();
10751 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10753 // FIXME: Implement direct support for this type!
10754 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10757 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10758 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10759 const X86Subtarget *Subtarget,
10760 SelectionDAG &DAG) {
10762 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10763 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10765 ArrayRef<int> Mask = SVOp->getMask();
10766 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10768 // FIXME: Implement direct support for this type!
10769 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10772 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10773 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10774 const X86Subtarget *Subtarget,
10775 SelectionDAG &DAG) {
10777 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10778 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10779 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10780 ArrayRef<int> Mask = SVOp->getMask();
10781 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10783 // FIXME: Implement direct support for this type!
10784 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10787 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10788 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10789 const X86Subtarget *Subtarget,
10790 SelectionDAG &DAG) {
10792 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10793 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10794 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10795 ArrayRef<int> Mask = SVOp->getMask();
10796 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10798 // FIXME: Implement direct support for this type!
10799 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10802 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10803 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10804 const X86Subtarget *Subtarget,
10805 SelectionDAG &DAG) {
10807 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10808 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10809 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10810 ArrayRef<int> Mask = SVOp->getMask();
10811 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10812 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10814 // FIXME: Implement direct support for this type!
10815 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10818 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10819 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10820 const X86Subtarget *Subtarget,
10821 SelectionDAG &DAG) {
10823 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10824 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10825 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10826 ArrayRef<int> Mask = SVOp->getMask();
10827 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10828 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10830 // FIXME: Implement direct support for this type!
10831 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10834 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10836 /// This routine either breaks down the specific type of a 512-bit x86 vector
10837 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10838 /// together based on the available instructions.
10839 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10840 MVT VT, const X86Subtarget *Subtarget,
10841 SelectionDAG &DAG) {
10843 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10844 ArrayRef<int> Mask = SVOp->getMask();
10845 assert(Subtarget->hasAVX512() &&
10846 "Cannot lower 512-bit vectors w/ basic ISA!");
10848 // Check for being able to broadcast a single element.
10849 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10850 Mask, Subtarget, DAG))
10853 // Dispatch to each element type for lowering. If we don't have supprot for
10854 // specific element type shuffles at 512 bits, immediately split them and
10855 // lower them. Each lowering routine of a given type is allowed to assume that
10856 // the requisite ISA extensions for that element type are available.
10857 switch (VT.SimpleTy) {
10859 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10861 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10863 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10865 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10867 if (Subtarget->hasBWI())
10868 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 if (Subtarget->hasBWI())
10872 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10876 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10879 // Otherwise fall back on splitting.
10880 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10883 /// \brief Top-level lowering for x86 vector shuffles.
10885 /// This handles decomposition, canonicalization, and lowering of all x86
10886 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10887 /// above in helper routines. The canonicalization attempts to widen shuffles
10888 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10889 /// s.t. only one of the two inputs needs to be tested, etc.
10890 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10891 SelectionDAG &DAG) {
10892 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10893 ArrayRef<int> Mask = SVOp->getMask();
10894 SDValue V1 = Op.getOperand(0);
10895 SDValue V2 = Op.getOperand(1);
10896 MVT VT = Op.getSimpleValueType();
10897 int NumElements = VT.getVectorNumElements();
10900 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10902 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10903 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10904 if (V1IsUndef && V2IsUndef)
10905 return DAG.getUNDEF(VT);
10907 // When we create a shuffle node we put the UNDEF node to second operand,
10908 // but in some cases the first operand may be transformed to UNDEF.
10909 // In this case we should just commute the node.
10911 return DAG.getCommutedVectorShuffle(*SVOp);
10913 // Check for non-undef masks pointing at an undef vector and make the masks
10914 // undef as well. This makes it easier to match the shuffle based solely on
10918 if (M >= NumElements) {
10919 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10920 for (int &M : NewMask)
10921 if (M >= NumElements)
10923 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10926 // Try to collapse shuffles into using a vector type with fewer elements but
10927 // wider element types. We cap this to not form integers or floating point
10928 // elements wider than 64 bits, but it might be interesting to form i128
10929 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10930 SmallVector<int, 16> WidenedMask;
10931 if (VT.getScalarSizeInBits() < 64 &&
10932 canWidenShuffleElements(Mask, WidenedMask)) {
10933 MVT NewEltVT = VT.isFloatingPoint()
10934 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10935 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10936 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10937 // Make sure that the new vector type is legal. For example, v2f64 isn't
10939 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10940 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10941 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10942 return DAG.getNode(ISD::BITCAST, dl, VT,
10943 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10947 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10948 for (int M : SVOp->getMask())
10950 ++NumUndefElements;
10951 else if (M < NumElements)
10956 // Commute the shuffle as needed such that more elements come from V1 than
10957 // V2. This allows us to match the shuffle pattern strictly on how many
10958 // elements come from V1 without handling the symmetric cases.
10959 if (NumV2Elements > NumV1Elements)
10960 return DAG.getCommutedVectorShuffle(*SVOp);
10962 // When the number of V1 and V2 elements are the same, try to minimize the
10963 // number of uses of V2 in the low half of the vector. When that is tied,
10964 // ensure that the sum of indices for V1 is equal to or lower than the sum
10965 // indices for V2. When those are equal, try to ensure that the number of odd
10966 // indices for V1 is lower than the number of odd indices for V2.
10967 if (NumV1Elements == NumV2Elements) {
10968 int LowV1Elements = 0, LowV2Elements = 0;
10969 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10970 if (M >= NumElements)
10974 if (LowV2Elements > LowV1Elements) {
10975 return DAG.getCommutedVectorShuffle(*SVOp);
10976 } else if (LowV2Elements == LowV1Elements) {
10977 int SumV1Indices = 0, SumV2Indices = 0;
10978 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10979 if (SVOp->getMask()[i] >= NumElements)
10981 else if (SVOp->getMask()[i] >= 0)
10983 if (SumV2Indices < SumV1Indices) {
10984 return DAG.getCommutedVectorShuffle(*SVOp);
10985 } else if (SumV2Indices == SumV1Indices) {
10986 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10987 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10988 if (SVOp->getMask()[i] >= NumElements)
10989 NumV2OddIndices += i % 2;
10990 else if (SVOp->getMask()[i] >= 0)
10991 NumV1OddIndices += i % 2;
10992 if (NumV2OddIndices < NumV1OddIndices)
10993 return DAG.getCommutedVectorShuffle(*SVOp);
10998 // For each vector width, delegate to a specialized lowering routine.
10999 if (VT.getSizeInBits() == 128)
11000 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11002 if (VT.getSizeInBits() == 256)
11003 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11005 // Force AVX-512 vectors to be scalarized for now.
11006 // FIXME: Implement AVX-512 support!
11007 if (VT.getSizeInBits() == 512)
11008 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11010 llvm_unreachable("Unimplemented!");
11014 //===----------------------------------------------------------------------===//
11015 // Legacy vector shuffle lowering
11017 // This code is the legacy code handling vector shuffles until the above
11018 // replaces its functionality and performance.
11019 //===----------------------------------------------------------------------===//
11021 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
11022 bool hasInt256, unsigned *MaskOut = nullptr) {
11023 MVT EltVT = VT.getVectorElementType();
11025 // There is no blend with immediate in AVX-512.
11026 if (VT.is512BitVector())
11029 if (!hasSSE41 || EltVT == MVT::i8)
11031 if (!hasInt256 && VT == MVT::v16i16)
11034 unsigned MaskValue = 0;
11035 unsigned NumElems = VT.getVectorNumElements();
11036 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11037 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11038 unsigned NumElemsInLane = NumElems / NumLanes;
11040 // Blend for v16i16 should be symetric for the both lanes.
11041 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11043 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
11044 int EltIdx = MaskVals[i];
11046 if ((EltIdx < 0 || EltIdx == (int)i) &&
11047 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
11050 if (((unsigned)EltIdx == (i + NumElems)) &&
11051 (SndLaneEltIdx < 0 ||
11052 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
11053 MaskValue |= (1 << i);
11059 *MaskOut = MaskValue;
11063 // Try to lower a shuffle node into a simple blend instruction.
11064 // This function assumes isBlendMask returns true for this
11065 // SuffleVectorSDNode
11066 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
11067 unsigned MaskValue,
11068 const X86Subtarget *Subtarget,
11069 SelectionDAG &DAG) {
11070 MVT VT = SVOp->getSimpleValueType(0);
11071 MVT EltVT = VT.getVectorElementType();
11072 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11073 Subtarget->hasInt256() && "Trying to lower a "
11074 "VECTOR_SHUFFLE to a Blend but "
11075 "with the wrong mask"));
11076 SDValue V1 = SVOp->getOperand(0);
11077 SDValue V2 = SVOp->getOperand(1);
11079 unsigned NumElems = VT.getVectorNumElements();
11081 // Convert i32 vectors to floating point if it is not AVX2.
11082 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11084 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11085 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11087 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11088 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11091 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11092 DAG.getConstant(MaskValue, MVT::i32));
11093 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11096 /// In vector type \p VT, return true if the element at index \p InputIdx
11097 /// falls on a different 128-bit lane than \p OutputIdx.
11098 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11099 unsigned OutputIdx) {
11100 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11101 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11104 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11105 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11106 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11107 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11109 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11110 SelectionDAG &DAG) {
11111 MVT VT = V1.getSimpleValueType();
11112 assert(VT.is128BitVector() || VT.is256BitVector());
11114 MVT EltVT = VT.getVectorElementType();
11115 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11116 unsigned NumElts = VT.getVectorNumElements();
11118 SmallVector<SDValue, 32> PshufbMask;
11119 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11120 int InputIdx = MaskVals[OutputIdx];
11121 unsigned InputByteIdx;
11123 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11124 InputByteIdx = 0x80;
11126 // Cross lane is not allowed.
11127 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11129 InputByteIdx = InputIdx * EltSizeInBytes;
11130 // Index is an byte offset within the 128-bit lane.
11131 InputByteIdx &= 0xf;
11134 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11135 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11136 if (InputByteIdx != 0x80)
11141 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11143 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11144 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11145 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11148 // v8i16 shuffles - Prefer shuffles in the following order:
11149 // 1. [all] pshuflw, pshufhw, optional move
11150 // 2. [ssse3] 1 x pshufb
11151 // 3. [ssse3] 2 x pshufb + 1 x por
11152 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11154 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11155 SelectionDAG &DAG) {
11156 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11157 SDValue V1 = SVOp->getOperand(0);
11158 SDValue V2 = SVOp->getOperand(1);
11160 SmallVector<int, 8> MaskVals;
11162 // Determine if more than 1 of the words in each of the low and high quadwords
11163 // of the result come from the same quadword of one of the two inputs. Undef
11164 // mask values count as coming from any quadword, for better codegen.
11166 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11167 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11168 unsigned LoQuad[] = { 0, 0, 0, 0 };
11169 unsigned HiQuad[] = { 0, 0, 0, 0 };
11170 // Indices of quads used.
11171 std::bitset<4> InputQuads;
11172 for (unsigned i = 0; i < 8; ++i) {
11173 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11174 int EltIdx = SVOp->getMaskElt(i);
11175 MaskVals.push_back(EltIdx);
11183 ++Quad[EltIdx / 4];
11184 InputQuads.set(EltIdx / 4);
11187 int BestLoQuad = -1;
11188 unsigned MaxQuad = 1;
11189 for (unsigned i = 0; i < 4; ++i) {
11190 if (LoQuad[i] > MaxQuad) {
11192 MaxQuad = LoQuad[i];
11196 int BestHiQuad = -1;
11198 for (unsigned i = 0; i < 4; ++i) {
11199 if (HiQuad[i] > MaxQuad) {
11201 MaxQuad = HiQuad[i];
11205 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11206 // of the two input vectors, shuffle them into one input vector so only a
11207 // single pshufb instruction is necessary. If there are more than 2 input
11208 // quads, disable the next transformation since it does not help SSSE3.
11209 bool V1Used = InputQuads[0] || InputQuads[1];
11210 bool V2Used = InputQuads[2] || InputQuads[3];
11211 if (Subtarget->hasSSSE3()) {
11212 if (InputQuads.count() == 2 && V1Used && V2Used) {
11213 BestLoQuad = InputQuads[0] ? 0 : 1;
11214 BestHiQuad = InputQuads[2] ? 2 : 3;
11216 if (InputQuads.count() > 2) {
11222 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11223 // the shuffle mask. If a quad is scored as -1, that means that it contains
11224 // words from all 4 input quadwords.
11226 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11228 BestLoQuad < 0 ? 0 : BestLoQuad,
11229 BestHiQuad < 0 ? 1 : BestHiQuad
11231 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11232 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11233 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11234 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11236 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11237 // source words for the shuffle, to aid later transformations.
11238 bool AllWordsInNewV = true;
11239 bool InOrder[2] = { true, true };
11240 for (unsigned i = 0; i != 8; ++i) {
11241 int idx = MaskVals[i];
11243 InOrder[i/4] = false;
11244 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11246 AllWordsInNewV = false;
11250 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11251 if (AllWordsInNewV) {
11252 for (int i = 0; i != 8; ++i) {
11253 int idx = MaskVals[i];
11256 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11257 if ((idx != i) && idx < 4)
11259 if ((idx != i) && idx > 3)
11268 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11269 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11270 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11271 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11272 unsigned TargetMask = 0;
11273 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11274 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11275 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11276 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11277 getShufflePSHUFLWImmediate(SVOp);
11278 V1 = NewV.getOperand(0);
11279 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11283 // Promote splats to a larger type which usually leads to more efficient code.
11284 // FIXME: Is this true if pshufb is available?
11285 if (SVOp->isSplat())
11286 return PromoteSplat(SVOp, DAG);
11288 // If we have SSSE3, and all words of the result are from 1 input vector,
11289 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11290 // is present, fall back to case 4.
11291 if (Subtarget->hasSSSE3()) {
11292 SmallVector<SDValue,16> pshufbMask;
11294 // If we have elements from both input vectors, set the high bit of the
11295 // shuffle mask element to zero out elements that come from V2 in the V1
11296 // mask, and elements that come from V1 in the V2 mask, so that the two
11297 // results can be OR'd together.
11298 bool TwoInputs = V1Used && V2Used;
11299 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11301 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11303 // Calculate the shuffle mask for the second input, shuffle it, and
11304 // OR it with the first shuffled input.
11305 CommuteVectorShuffleMask(MaskVals, 8);
11306 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11307 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11308 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11311 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11312 // and update MaskVals with new element order.
11313 std::bitset<8> InOrder;
11314 if (BestLoQuad >= 0) {
11315 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11316 for (int i = 0; i != 4; ++i) {
11317 int idx = MaskVals[i];
11320 } else if ((idx / 4) == BestLoQuad) {
11321 MaskV[i] = idx & 3;
11325 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11328 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11330 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11331 NewV.getOperand(0),
11332 getShufflePSHUFLWImmediate(SVOp), DAG);
11336 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11337 // and update MaskVals with the new element order.
11338 if (BestHiQuad >= 0) {
11339 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11340 for (unsigned i = 4; i != 8; ++i) {
11341 int idx = MaskVals[i];
11344 } else if ((idx / 4) == BestHiQuad) {
11345 MaskV[i] = (idx & 3) + 4;
11349 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11352 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11354 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11355 NewV.getOperand(0),
11356 getShufflePSHUFHWImmediate(SVOp), DAG);
11360 // In case BestHi & BestLo were both -1, which means each quadword has a word
11361 // from each of the four input quadwords, calculate the InOrder bitvector now
11362 // before falling through to the insert/extract cleanup.
11363 if (BestLoQuad == -1 && BestHiQuad == -1) {
11365 for (int i = 0; i != 8; ++i)
11366 if (MaskVals[i] < 0 || MaskVals[i] == i)
11370 // The other elements are put in the right place using pextrw and pinsrw.
11371 for (unsigned i = 0; i != 8; ++i) {
11374 int EltIdx = MaskVals[i];
11377 SDValue ExtOp = (EltIdx < 8) ?
11378 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11379 DAG.getIntPtrConstant(EltIdx)) :
11380 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11381 DAG.getIntPtrConstant(EltIdx - 8));
11382 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11383 DAG.getIntPtrConstant(i));
11388 /// \brief v16i16 shuffles
11390 /// FIXME: We only support generation of a single pshufb currently. We can
11391 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11392 /// well (e.g 2 x pshufb + 1 x por).
11394 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11395 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11396 SDValue V1 = SVOp->getOperand(0);
11397 SDValue V2 = SVOp->getOperand(1);
11400 if (V2.getOpcode() != ISD::UNDEF)
11403 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11404 return getPSHUFB(MaskVals, V1, dl, DAG);
11407 // v16i8 shuffles - Prefer shuffles in the following order:
11408 // 1. [ssse3] 1 x pshufb
11409 // 2. [ssse3] 2 x pshufb + 1 x por
11410 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11411 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11412 const X86Subtarget* Subtarget,
11413 SelectionDAG &DAG) {
11414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11415 SDValue V1 = SVOp->getOperand(0);
11416 SDValue V2 = SVOp->getOperand(1);
11418 ArrayRef<int> MaskVals = SVOp->getMask();
11420 // Promote splats to a larger type which usually leads to more efficient code.
11421 // FIXME: Is this true if pshufb is available?
11422 if (SVOp->isSplat())
11423 return PromoteSplat(SVOp, DAG);
11425 // If we have SSSE3, case 1 is generated when all result bytes come from
11426 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11427 // present, fall back to case 3.
11429 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11430 if (Subtarget->hasSSSE3()) {
11431 SmallVector<SDValue,16> pshufbMask;
11433 // If all result elements are from one input vector, then only translate
11434 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11436 // Otherwise, we have elements from both input vectors, and must zero out
11437 // elements that come from V2 in the first mask, and V1 in the second mask
11438 // so that we can OR them together.
11439 for (unsigned i = 0; i != 16; ++i) {
11440 int EltIdx = MaskVals[i];
11441 if (EltIdx < 0 || EltIdx >= 16)
11443 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11445 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11446 DAG.getNode(ISD::BUILD_VECTOR, dl,
11447 MVT::v16i8, pshufbMask));
11449 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11450 // the 2nd operand if it's undefined or zero.
11451 if (V2.getOpcode() == ISD::UNDEF ||
11452 ISD::isBuildVectorAllZeros(V2.getNode()))
11455 // Calculate the shuffle mask for the second input, shuffle it, and
11456 // OR it with the first shuffled input.
11457 pshufbMask.clear();
11458 for (unsigned i = 0; i != 16; ++i) {
11459 int EltIdx = MaskVals[i];
11460 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11461 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11463 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11464 DAG.getNode(ISD::BUILD_VECTOR, dl,
11465 MVT::v16i8, pshufbMask));
11466 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11469 // No SSSE3 - Calculate in place words and then fix all out of place words
11470 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11471 // the 16 different words that comprise the two doublequadword input vectors.
11472 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11473 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11475 for (int i = 0; i != 8; ++i) {
11476 int Elt0 = MaskVals[i*2];
11477 int Elt1 = MaskVals[i*2+1];
11479 // This word of the result is all undef, skip it.
11480 if (Elt0 < 0 && Elt1 < 0)
11483 // This word of the result is already in the correct place, skip it.
11484 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11487 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11488 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11491 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11492 // using a single extract together, load it and store it.
11493 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11494 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11495 DAG.getIntPtrConstant(Elt1 / 2));
11496 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11497 DAG.getIntPtrConstant(i));
11501 // If Elt1 is defined, extract it from the appropriate source. If the
11502 // source byte is not also odd, shift the extracted word left 8 bits
11503 // otherwise clear the bottom 8 bits if we need to do an or.
11505 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11506 DAG.getIntPtrConstant(Elt1 / 2));
11507 if ((Elt1 & 1) == 0)
11508 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11510 TLI.getShiftAmountTy(InsElt.getValueType())));
11511 else if (Elt0 >= 0)
11512 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11513 DAG.getConstant(0xFF00, MVT::i16));
11515 // If Elt0 is defined, extract it from the appropriate source. If the
11516 // source byte is not also even, shift the extracted word right 8 bits. If
11517 // Elt1 was also defined, OR the extracted values together before
11518 // inserting them in the result.
11520 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11521 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11522 if ((Elt0 & 1) != 0)
11523 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11525 TLI.getShiftAmountTy(InsElt0.getValueType())));
11526 else if (Elt1 >= 0)
11527 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11528 DAG.getConstant(0x00FF, MVT::i16));
11529 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11532 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11533 DAG.getIntPtrConstant(i));
11535 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11538 // v32i8 shuffles - Translate to VPSHUFB if possible.
11540 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11541 const X86Subtarget *Subtarget,
11542 SelectionDAG &DAG) {
11543 MVT VT = SVOp->getSimpleValueType(0);
11544 SDValue V1 = SVOp->getOperand(0);
11545 SDValue V2 = SVOp->getOperand(1);
11547 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11549 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11550 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11551 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11553 // VPSHUFB may be generated if
11554 // (1) one of input vector is undefined or zeroinitializer.
11555 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11556 // And (2) the mask indexes don't cross the 128-bit lane.
11557 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11558 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11561 if (V1IsAllZero && !V2IsAllZero) {
11562 CommuteVectorShuffleMask(MaskVals, 32);
11565 return getPSHUFB(MaskVals, V1, dl, DAG);
11568 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11569 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11570 /// done when every pair / quad of shuffle mask elements point to elements in
11571 /// the right sequence. e.g.
11572 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11574 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11575 SelectionDAG &DAG) {
11576 MVT VT = SVOp->getSimpleValueType(0);
11578 unsigned NumElems = VT.getVectorNumElements();
11581 switch (VT.SimpleTy) {
11582 default: llvm_unreachable("Unexpected!");
11585 return SDValue(SVOp, 0);
11586 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11587 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11588 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11589 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11590 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11591 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11594 SmallVector<int, 8> MaskVec;
11595 for (unsigned i = 0; i != NumElems; i += Scale) {
11597 for (unsigned j = 0; j != Scale; ++j) {
11598 int EltIdx = SVOp->getMaskElt(i+j);
11602 StartIdx = (EltIdx / Scale);
11603 if (EltIdx != (int)(StartIdx*Scale + j))
11606 MaskVec.push_back(StartIdx);
11609 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11610 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11611 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11614 /// getVZextMovL - Return a zero-extending vector move low node.
11616 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11617 SDValue SrcOp, SelectionDAG &DAG,
11618 const X86Subtarget *Subtarget, SDLoc dl) {
11619 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11620 LoadSDNode *LD = nullptr;
11621 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11622 LD = dyn_cast<LoadSDNode>(SrcOp);
11624 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11626 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11627 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11628 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11629 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11630 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11632 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11633 return DAG.getNode(ISD::BITCAST, dl, VT,
11634 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11635 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11637 SrcOp.getOperand(0)
11643 return DAG.getNode(ISD::BITCAST, dl, VT,
11644 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11645 DAG.getNode(ISD::BITCAST, dl,
11649 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11650 /// which could not be matched by any known target speficic shuffle
11652 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11654 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11655 if (NewOp.getNode())
11658 MVT VT = SVOp->getSimpleValueType(0);
11660 unsigned NumElems = VT.getVectorNumElements();
11661 unsigned NumLaneElems = NumElems / 2;
11664 MVT EltVT = VT.getVectorElementType();
11665 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11668 SmallVector<int, 16> Mask;
11669 for (unsigned l = 0; l < 2; ++l) {
11670 // Build a shuffle mask for the output, discovering on the fly which
11671 // input vectors to use as shuffle operands (recorded in InputUsed).
11672 // If building a suitable shuffle vector proves too hard, then bail
11673 // out with UseBuildVector set.
11674 bool UseBuildVector = false;
11675 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11676 unsigned LaneStart = l * NumLaneElems;
11677 for (unsigned i = 0; i != NumLaneElems; ++i) {
11678 // The mask element. This indexes into the input.
11679 int Idx = SVOp->getMaskElt(i+LaneStart);
11681 // the mask element does not index into any input vector.
11682 Mask.push_back(-1);
11686 // The input vector this mask element indexes into.
11687 int Input = Idx / NumLaneElems;
11689 // Turn the index into an offset from the start of the input vector.
11690 Idx -= Input * NumLaneElems;
11692 // Find or create a shuffle vector operand to hold this input.
11694 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11695 if (InputUsed[OpNo] == Input)
11696 // This input vector is already an operand.
11698 if (InputUsed[OpNo] < 0) {
11699 // Create a new operand for this input vector.
11700 InputUsed[OpNo] = Input;
11705 if (OpNo >= array_lengthof(InputUsed)) {
11706 // More than two input vectors used! Give up on trying to create a
11707 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11708 UseBuildVector = true;
11712 // Add the mask index for the new shuffle vector.
11713 Mask.push_back(Idx + OpNo * NumLaneElems);
11716 if (UseBuildVector) {
11717 SmallVector<SDValue, 16> SVOps;
11718 for (unsigned i = 0; i != NumLaneElems; ++i) {
11719 // The mask element. This indexes into the input.
11720 int Idx = SVOp->getMaskElt(i+LaneStart);
11722 SVOps.push_back(DAG.getUNDEF(EltVT));
11726 // The input vector this mask element indexes into.
11727 int Input = Idx / NumElems;
11729 // Turn the index into an offset from the start of the input vector.
11730 Idx -= Input * NumElems;
11732 // Extract the vector element by hand.
11733 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11734 SVOp->getOperand(Input),
11735 DAG.getIntPtrConstant(Idx)));
11738 // Construct the output using a BUILD_VECTOR.
11739 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11740 } else if (InputUsed[0] < 0) {
11741 // No input vectors were used! The result is undefined.
11742 Output[l] = DAG.getUNDEF(NVT);
11744 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11745 (InputUsed[0] % 2) * NumLaneElems,
11747 // If only one input was used, use an undefined vector for the other.
11748 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11749 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11750 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11751 // At least one input vector was used. Create a new shuffle vector.
11752 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11758 // Concatenate the result back
11759 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11762 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11763 /// 4 elements, and match them with several different shuffle types.
11765 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11766 SDValue V1 = SVOp->getOperand(0);
11767 SDValue V2 = SVOp->getOperand(1);
11769 MVT VT = SVOp->getSimpleValueType(0);
11771 assert(VT.is128BitVector() && "Unsupported vector size");
11773 std::pair<int, int> Locs[4];
11774 int Mask1[] = { -1, -1, -1, -1 };
11775 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11777 unsigned NumHi = 0;
11778 unsigned NumLo = 0;
11779 for (unsigned i = 0; i != 4; ++i) {
11780 int Idx = PermMask[i];
11782 Locs[i] = std::make_pair(-1, -1);
11784 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11786 Locs[i] = std::make_pair(0, NumLo);
11787 Mask1[NumLo] = Idx;
11790 Locs[i] = std::make_pair(1, NumHi);
11792 Mask1[2+NumHi] = Idx;
11798 if (NumLo <= 2 && NumHi <= 2) {
11799 // If no more than two elements come from either vector. This can be
11800 // implemented with two shuffles. First shuffle gather the elements.
11801 // The second shuffle, which takes the first shuffle as both of its
11802 // vector operands, put the elements into the right order.
11803 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11805 int Mask2[] = { -1, -1, -1, -1 };
11807 for (unsigned i = 0; i != 4; ++i)
11808 if (Locs[i].first != -1) {
11809 unsigned Idx = (i < 2) ? 0 : 4;
11810 Idx += Locs[i].first * 2 + Locs[i].second;
11814 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11817 if (NumLo == 3 || NumHi == 3) {
11818 // Otherwise, we must have three elements from one vector, call it X, and
11819 // one element from the other, call it Y. First, use a shufps to build an
11820 // intermediate vector with the one element from Y and the element from X
11821 // that will be in the same half in the final destination (the indexes don't
11822 // matter). Then, use a shufps to build the final vector, taking the half
11823 // containing the element from Y from the intermediate, and the other half
11826 // Normalize it so the 3 elements come from V1.
11827 CommuteVectorShuffleMask(PermMask, 4);
11831 // Find the element from V2.
11833 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11834 int Val = PermMask[HiIndex];
11841 Mask1[0] = PermMask[HiIndex];
11843 Mask1[2] = PermMask[HiIndex^1];
11845 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11847 if (HiIndex >= 2) {
11848 Mask1[0] = PermMask[0];
11849 Mask1[1] = PermMask[1];
11850 Mask1[2] = HiIndex & 1 ? 6 : 4;
11851 Mask1[3] = HiIndex & 1 ? 4 : 6;
11852 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11855 Mask1[0] = HiIndex & 1 ? 2 : 0;
11856 Mask1[1] = HiIndex & 1 ? 0 : 2;
11857 Mask1[2] = PermMask[2];
11858 Mask1[3] = PermMask[3];
11863 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11866 // Break it into (shuffle shuffle_hi, shuffle_lo).
11867 int LoMask[] = { -1, -1, -1, -1 };
11868 int HiMask[] = { -1, -1, -1, -1 };
11870 int *MaskPtr = LoMask;
11871 unsigned MaskIdx = 0;
11872 unsigned LoIdx = 0;
11873 unsigned HiIdx = 2;
11874 for (unsigned i = 0; i != 4; ++i) {
11881 int Idx = PermMask[i];
11883 Locs[i] = std::make_pair(-1, -1);
11884 } else if (Idx < 4) {
11885 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11886 MaskPtr[LoIdx] = Idx;
11889 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11890 MaskPtr[HiIdx] = Idx;
11895 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11896 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11897 int MaskOps[] = { -1, -1, -1, -1 };
11898 for (unsigned i = 0; i != 4; ++i)
11899 if (Locs[i].first != -1)
11900 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11901 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11904 static bool MayFoldVectorLoad(SDValue V) {
11905 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11906 V = V.getOperand(0);
11908 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11909 V = V.getOperand(0);
11910 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11911 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11912 // BUILD_VECTOR (load), undef
11913 V = V.getOperand(0);
11915 return MayFoldLoad(V);
11919 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11920 MVT VT = Op.getSimpleValueType();
11922 // Canonizalize to v2f64.
11923 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11924 return DAG.getNode(ISD::BITCAST, dl, VT,
11925 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11930 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11932 SDValue V1 = Op.getOperand(0);
11933 SDValue V2 = Op.getOperand(1);
11934 MVT VT = Op.getSimpleValueType();
11936 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11938 if (HasSSE2 && VT == MVT::v2f64)
11939 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11941 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11942 return DAG.getNode(ISD::BITCAST, dl, VT,
11943 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11944 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11945 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11949 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11950 SDValue V1 = Op.getOperand(0);
11951 SDValue V2 = Op.getOperand(1);
11952 MVT VT = Op.getSimpleValueType();
11954 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11955 "unsupported shuffle type");
11957 if (V2.getOpcode() == ISD::UNDEF)
11961 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11965 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11966 SDValue V1 = Op.getOperand(0);
11967 SDValue V2 = Op.getOperand(1);
11968 MVT VT = Op.getSimpleValueType();
11969 unsigned NumElems = VT.getVectorNumElements();
11971 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11972 // operand of these instructions is only memory, so check if there's a
11973 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11975 bool CanFoldLoad = false;
11977 // Trivial case, when V2 comes from a load.
11978 if (MayFoldVectorLoad(V2))
11979 CanFoldLoad = true;
11981 // When V1 is a load, it can be folded later into a store in isel, example:
11982 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11984 // (MOVLPSmr addr:$src1, VR128:$src2)
11985 // So, recognize this potential and also use MOVLPS or MOVLPD
11986 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11987 CanFoldLoad = true;
11989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11991 if (HasSSE2 && NumElems == 2)
11992 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11995 // If we don't care about the second element, proceed to use movss.
11996 if (SVOp->getMaskElt(1) != -1)
11997 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
12000 // movl and movlp will both match v2i64, but v2i64 is never matched by
12001 // movl earlier because we make it strict to avoid messing with the movlp load
12002 // folding logic (see the code above getMOVLP call). Match it here then,
12003 // this is horrible, but will stay like this until we move all shuffle
12004 // matching to x86 specific nodes. Note that for the 1st condition all
12005 // types are matched with movsd.
12007 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
12008 // as to remove this logic from here, as much as possible
12009 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
12010 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12011 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12014 assert(VT != MVT::v4i32 && "unsupported shuffle type");
12016 // Invert the operand order and use SHUFPS to match it.
12017 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
12018 getShuffleSHUFImmediate(SVOp), DAG);
12021 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
12022 SelectionDAG &DAG) {
12024 MVT VT = Load->getSimpleValueType(0);
12025 MVT EVT = VT.getVectorElementType();
12026 SDValue Addr = Load->getOperand(1);
12027 SDValue NewAddr = DAG.getNode(
12028 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
12029 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
12032 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
12033 DAG.getMachineFunction().getMachineMemOperand(
12034 Load->getMemOperand(), 0, EVT.getStoreSize()));
12038 // It is only safe to call this function if isINSERTPSMask is true for
12039 // this shufflevector mask.
12040 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
12041 SelectionDAG &DAG) {
12042 // Generate an insertps instruction when inserting an f32 from memory onto a
12043 // v4f32 or when copying a member from one v4f32 to another.
12044 // We also use it for transferring i32 from one register to another,
12045 // since it simply copies the same bits.
12046 // If we're transferring an i32 from memory to a specific element in a
12047 // register, we output a generic DAG that will match the PINSRD
12049 MVT VT = SVOp->getSimpleValueType(0);
12050 MVT EVT = VT.getVectorElementType();
12051 SDValue V1 = SVOp->getOperand(0);
12052 SDValue V2 = SVOp->getOperand(1);
12053 auto Mask = SVOp->getMask();
12054 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
12055 "unsupported vector type for insertps/pinsrd");
12057 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
12058 auto FromV2Predicate = [](const int &i) { return i >= 4; };
12059 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
12063 unsigned DestIndex;
12067 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12070 // If we have 1 element from each vector, we have to check if we're
12071 // changing V1's element's place. If so, we're done. Otherwise, we
12072 // should assume we're changing V2's element's place and behave
12074 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12075 assert(DestIndex <= INT32_MAX && "truncated destination index");
12076 if (FromV1 == FromV2 &&
12077 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12081 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12084 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12085 "More than one element from V1 and from V2, or no elements from one "
12086 "of the vectors. This case should not have returned true from "
12091 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12094 // Get an index into the source vector in the range [0,4) (the mask is
12095 // in the range [0,8) because it can address V1 and V2)
12096 unsigned SrcIndex = Mask[DestIndex] % 4;
12097 if (MayFoldLoad(From)) {
12098 // Trivial case, when From comes from a load and is only used by the
12099 // shuffle. Make it use insertps from the vector that we need from that
12102 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12103 if (!NewLoad.getNode())
12106 if (EVT == MVT::f32) {
12107 // Create this as a scalar to vector to match the instruction pattern.
12108 SDValue LoadScalarToVector =
12109 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12110 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12111 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12113 } else { // EVT == MVT::i32
12114 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12115 // instruction, to match the PINSRD instruction, which loads an i32 to a
12116 // certain vector element.
12117 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12118 DAG.getConstant(DestIndex, MVT::i32));
12122 // Vector-element-to-vector
12123 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12124 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12127 // Reduce a vector shuffle to zext.
12128 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12129 SelectionDAG &DAG) {
12130 // PMOVZX is only available from SSE41.
12131 if (!Subtarget->hasSSE41())
12134 MVT VT = Op.getSimpleValueType();
12136 // Only AVX2 support 256-bit vector integer extending.
12137 if (!Subtarget->hasInt256() && VT.is256BitVector())
12140 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12142 SDValue V1 = Op.getOperand(0);
12143 SDValue V2 = Op.getOperand(1);
12144 unsigned NumElems = VT.getVectorNumElements();
12146 // Extending is an unary operation and the element type of the source vector
12147 // won't be equal to or larger than i64.
12148 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12149 VT.getVectorElementType() == MVT::i64)
12152 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12153 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12154 while ((1U << Shift) < NumElems) {
12155 if (SVOp->getMaskElt(1U << Shift) == 1)
12158 // The maximal ratio is 8, i.e. from i8 to i64.
12163 // Check the shuffle mask.
12164 unsigned Mask = (1U << Shift) - 1;
12165 for (unsigned i = 0; i != NumElems; ++i) {
12166 int EltIdx = SVOp->getMaskElt(i);
12167 if ((i & Mask) != 0 && EltIdx != -1)
12169 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12173 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12174 MVT NeVT = MVT::getIntegerVT(NBits);
12175 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12177 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12180 return DAG.getNode(ISD::BITCAST, DL, VT,
12181 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12184 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12185 SelectionDAG &DAG) {
12186 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12187 MVT VT = Op.getSimpleValueType();
12189 SDValue V1 = Op.getOperand(0);
12190 SDValue V2 = Op.getOperand(1);
12192 if (isZeroShuffle(SVOp))
12193 return getZeroVector(VT, Subtarget, DAG, dl);
12195 // Handle splat operations
12196 if (SVOp->isSplat()) {
12197 // Use vbroadcast whenever the splat comes from a foldable load
12198 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12199 if (Broadcast.getNode())
12203 // Check integer expanding shuffles.
12204 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12205 if (NewOp.getNode())
12208 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12210 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12211 VT == MVT::v32i8) {
12212 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12213 if (NewOp.getNode())
12214 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12215 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12216 // FIXME: Figure out a cleaner way to do this.
12217 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12218 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12219 if (NewOp.getNode()) {
12220 MVT NewVT = NewOp.getSimpleValueType();
12221 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12222 NewVT, true, false))
12223 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12226 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12227 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12228 if (NewOp.getNode()) {
12229 MVT NewVT = NewOp.getSimpleValueType();
12230 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12231 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12240 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12241 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12242 SDValue V1 = Op.getOperand(0);
12243 SDValue V2 = Op.getOperand(1);
12244 MVT VT = Op.getSimpleValueType();
12246 unsigned NumElems = VT.getVectorNumElements();
12247 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12248 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12249 bool V1IsSplat = false;
12250 bool V2IsSplat = false;
12251 bool HasSSE2 = Subtarget->hasSSE2();
12252 bool HasFp256 = Subtarget->hasFp256();
12253 bool HasInt256 = Subtarget->hasInt256();
12254 MachineFunction &MF = DAG.getMachineFunction();
12255 bool OptForSize = MF.getFunction()->getAttributes().
12256 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12258 // Check if we should use the experimental vector shuffle lowering. If so,
12259 // delegate completely to that code path.
12260 if (ExperimentalVectorShuffleLowering)
12261 return lowerVectorShuffle(Op, Subtarget, DAG);
12263 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12265 if (V1IsUndef && V2IsUndef)
12266 return DAG.getUNDEF(VT);
12268 // When we create a shuffle node we put the UNDEF node to second operand,
12269 // but in some cases the first operand may be transformed to UNDEF.
12270 // In this case we should just commute the node.
12272 return DAG.getCommutedVectorShuffle(*SVOp);
12274 // Vector shuffle lowering takes 3 steps:
12276 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12277 // narrowing and commutation of operands should be handled.
12278 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12280 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12281 // so the shuffle can be broken into other shuffles and the legalizer can
12282 // try the lowering again.
12284 // The general idea is that no vector_shuffle operation should be left to
12285 // be matched during isel, all of them must be converted to a target specific
12288 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12289 // narrowing and commutation of operands should be handled. The actual code
12290 // doesn't include all of those, work in progress...
12291 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12292 if (NewOp.getNode())
12295 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12297 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12298 // unpckh_undef). Only use pshufd if speed is more important than size.
12299 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12300 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12301 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12302 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12304 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12305 V2IsUndef && MayFoldVectorLoad(V1))
12306 return getMOVDDup(Op, dl, V1, DAG);
12308 if (isMOVHLPS_v_undef_Mask(M, VT))
12309 return getMOVHighToLow(Op, dl, DAG);
12311 // Use to match splats
12312 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12313 (VT == MVT::v2f64 || VT == MVT::v2i64))
12314 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12316 if (isPSHUFDMask(M, VT)) {
12317 // The actual implementation will match the mask in the if above and then
12318 // during isel it can match several different instructions, not only pshufd
12319 // as its name says, sad but true, emulate the behavior for now...
12320 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12321 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12323 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12325 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12326 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12328 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12329 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12332 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12336 if (isPALIGNRMask(M, VT, Subtarget))
12337 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12338 getShufflePALIGNRImmediate(SVOp),
12341 if (isVALIGNMask(M, VT, Subtarget))
12342 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12343 getShuffleVALIGNImmediate(SVOp),
12346 // Check if this can be converted into a logical shift.
12347 bool isLeft = false;
12348 unsigned ShAmt = 0;
12350 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12351 if (isShift && ShVal.hasOneUse()) {
12352 // If the shifted value has multiple uses, it may be cheaper to use
12353 // v_set0 + movlhps or movhlps, etc.
12354 MVT EltVT = VT.getVectorElementType();
12355 ShAmt *= EltVT.getSizeInBits();
12356 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12359 if (isMOVLMask(M, VT)) {
12360 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12361 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12362 if (!isMOVLPMask(M, VT)) {
12363 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12364 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12366 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12367 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12371 // FIXME: fold these into legal mask.
12372 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12373 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12375 if (isMOVHLPSMask(M, VT))
12376 return getMOVHighToLow(Op, dl, DAG);
12378 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12379 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12381 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12382 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12384 if (isMOVLPMask(M, VT))
12385 return getMOVLP(Op, dl, DAG, HasSSE2);
12387 if (ShouldXformToMOVHLPS(M, VT) ||
12388 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12389 return DAG.getCommutedVectorShuffle(*SVOp);
12392 // No better options. Use a vshldq / vsrldq.
12393 MVT EltVT = VT.getVectorElementType();
12394 ShAmt *= EltVT.getSizeInBits();
12395 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12398 bool Commuted = false;
12399 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12400 // 1,1,1,1 -> v8i16 though.
12401 BitVector UndefElements;
12402 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12403 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12405 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12406 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12409 // Canonicalize the splat or undef, if present, to be on the RHS.
12410 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12411 CommuteVectorShuffleMask(M, NumElems);
12413 std::swap(V1IsSplat, V2IsSplat);
12417 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12418 // Shuffling low element of v1 into undef, just return v1.
12421 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12422 // the instruction selector will not match, so get a canonical MOVL with
12423 // swapped operands to undo the commute.
12424 return getMOVL(DAG, dl, VT, V2, V1);
12427 if (isUNPCKLMask(M, VT, HasInt256))
12428 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12430 if (isUNPCKHMask(M, VT, HasInt256))
12431 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12434 // Normalize mask so all entries that point to V2 points to its first
12435 // element then try to match unpck{h|l} again. If match, return a
12436 // new vector_shuffle with the corrected mask.p
12437 SmallVector<int, 8> NewMask(M.begin(), M.end());
12438 NormalizeMask(NewMask, NumElems);
12439 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12440 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12441 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12442 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12446 // Commute is back and try unpck* again.
12447 // FIXME: this seems wrong.
12448 CommuteVectorShuffleMask(M, NumElems);
12450 std::swap(V1IsSplat, V2IsSplat);
12452 if (isUNPCKLMask(M, VT, HasInt256))
12453 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12455 if (isUNPCKHMask(M, VT, HasInt256))
12456 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12459 // Normalize the node to match x86 shuffle ops if needed
12460 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12461 return DAG.getCommutedVectorShuffle(*SVOp);
12463 // The checks below are all present in isShuffleMaskLegal, but they are
12464 // inlined here right now to enable us to directly emit target specific
12465 // nodes, and remove one by one until they don't return Op anymore.
12467 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12468 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12469 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12470 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12473 if (isPSHUFHWMask(M, VT, HasInt256))
12474 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12475 getShufflePSHUFHWImmediate(SVOp),
12478 if (isPSHUFLWMask(M, VT, HasInt256))
12479 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12480 getShufflePSHUFLWImmediate(SVOp),
12483 unsigned MaskValue;
12484 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12486 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12488 if (isSHUFPMask(M, VT))
12489 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12490 getShuffleSHUFImmediate(SVOp), DAG);
12492 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12493 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12494 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12495 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12497 //===--------------------------------------------------------------------===//
12498 // Generate target specific nodes for 128 or 256-bit shuffles only
12499 // supported in the AVX instruction set.
12502 // Handle VMOVDDUPY permutations
12503 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12504 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12506 // Handle VPERMILPS/D* permutations
12507 if (isVPERMILPMask(M, VT)) {
12508 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12509 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12510 getShuffleSHUFImmediate(SVOp), DAG);
12511 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12512 getShuffleSHUFImmediate(SVOp), DAG);
12516 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12517 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12518 Idx*(NumElems/2), DAG, dl);
12520 // Handle VPERM2F128/VPERM2I128 permutations
12521 if (isVPERM2X128Mask(M, VT, HasFp256))
12522 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12523 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12525 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12526 return getINSERTPS(SVOp, dl, DAG);
12529 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12530 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12532 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12533 VT.is512BitVector()) {
12534 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12535 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12536 SmallVector<SDValue, 16> permclMask;
12537 for (unsigned i = 0; i != NumElems; ++i) {
12538 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12541 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12543 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12544 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12545 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12546 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12547 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12550 //===--------------------------------------------------------------------===//
12551 // Since no target specific shuffle was selected for this generic one,
12552 // lower it into other known shuffles. FIXME: this isn't true yet, but
12553 // this is the plan.
12556 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12557 if (VT == MVT::v8i16) {
12558 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12559 if (NewOp.getNode())
12563 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12564 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12565 if (NewOp.getNode())
12569 if (VT == MVT::v16i8) {
12570 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12571 if (NewOp.getNode())
12575 if (VT == MVT::v32i8) {
12576 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12577 if (NewOp.getNode())
12581 // Handle all 128-bit wide vectors with 4 elements, and match them with
12582 // several different shuffle types.
12583 if (NumElems == 4 && VT.is128BitVector())
12584 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12586 // Handle general 256-bit shuffles
12587 if (VT.is256BitVector())
12588 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12593 // This function assumes its argument is a BUILD_VECTOR of constants or
12594 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12596 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12597 unsigned &MaskValue) {
12599 unsigned NumElems = BuildVector->getNumOperands();
12600 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12601 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12602 unsigned NumElemsInLane = NumElems / NumLanes;
12604 // Blend for v16i16 should be symetric for the both lanes.
12605 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12606 SDValue EltCond = BuildVector->getOperand(i);
12607 SDValue SndLaneEltCond =
12608 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12610 int Lane1Cond = -1, Lane2Cond = -1;
12611 if (isa<ConstantSDNode>(EltCond))
12612 Lane1Cond = !isZero(EltCond);
12613 if (isa<ConstantSDNode>(SndLaneEltCond))
12614 Lane2Cond = !isZero(SndLaneEltCond);
12616 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12617 // Lane1Cond != 0, means we want the first argument.
12618 // Lane1Cond == 0, means we want the second argument.
12619 // The encoding of this argument is 0 for the first argument, 1
12620 // for the second. Therefore, invert the condition.
12621 MaskValue |= !Lane1Cond << i;
12622 else if (Lane1Cond < 0)
12623 MaskValue |= !Lane2Cond << i;
12630 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12632 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12633 SelectionDAG &DAG) {
12634 SDValue Cond = Op.getOperand(0);
12635 SDValue LHS = Op.getOperand(1);
12636 SDValue RHS = Op.getOperand(2);
12638 MVT VT = Op.getSimpleValueType();
12639 MVT EltVT = VT.getVectorElementType();
12640 unsigned NumElems = VT.getVectorNumElements();
12642 // There is no blend with immediate in AVX-512.
12643 if (VT.is512BitVector())
12646 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12648 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12651 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12654 // Check the mask for BLEND and build the value.
12655 unsigned MaskValue = 0;
12656 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12659 // Convert i32 vectors to floating point if it is not AVX2.
12660 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12662 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12663 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12665 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12666 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12669 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12670 DAG.getConstant(MaskValue, MVT::i32));
12671 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12674 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12675 // A vselect where all conditions and data are constants can be optimized into
12676 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12677 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12678 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12679 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12682 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12683 if (BlendOp.getNode())
12686 // Some types for vselect were previously set to Expand, not Legal or
12687 // Custom. Return an empty SDValue so we fall-through to Expand, after
12688 // the Custom lowering phase.
12689 MVT VT = Op.getSimpleValueType();
12690 switch (VT.SimpleTy) {
12695 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12700 // We couldn't create a "Blend with immediate" node.
12701 // This node should still be legal, but we'll have to emit a blendv*
12706 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12707 MVT VT = Op.getSimpleValueType();
12710 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12713 if (VT.getSizeInBits() == 8) {
12714 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12715 Op.getOperand(0), Op.getOperand(1));
12716 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12717 DAG.getValueType(VT));
12718 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12721 if (VT.getSizeInBits() == 16) {
12722 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12723 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12725 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12726 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12727 DAG.getNode(ISD::BITCAST, dl,
12730 Op.getOperand(1)));
12731 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12732 Op.getOperand(0), Op.getOperand(1));
12733 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12734 DAG.getValueType(VT));
12735 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12738 if (VT == MVT::f32) {
12739 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12740 // the result back to FR32 register. It's only worth matching if the
12741 // result has a single use which is a store or a bitcast to i32. And in
12742 // the case of a store, it's not worth it if the index is a constant 0,
12743 // because a MOVSSmr can be used instead, which is smaller and faster.
12744 if (!Op.hasOneUse())
12746 SDNode *User = *Op.getNode()->use_begin();
12747 if ((User->getOpcode() != ISD::STORE ||
12748 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12749 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12750 (User->getOpcode() != ISD::BITCAST ||
12751 User->getValueType(0) != MVT::i32))
12753 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12754 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12757 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12760 if (VT == MVT::i32 || VT == MVT::i64) {
12761 // ExtractPS/pextrq works with constant index.
12762 if (isa<ConstantSDNode>(Op.getOperand(1)))
12768 /// Extract one bit from mask vector, like v16i1 or v8i1.
12769 /// AVX-512 feature.
12771 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12772 SDValue Vec = Op.getOperand(0);
12774 MVT VecVT = Vec.getSimpleValueType();
12775 SDValue Idx = Op.getOperand(1);
12776 MVT EltVT = Op.getSimpleValueType();
12778 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12780 // variable index can't be handled in mask registers,
12781 // extend vector to VR512
12782 if (!isa<ConstantSDNode>(Idx)) {
12783 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12784 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12785 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12786 ExtVT.getVectorElementType(), Ext, Idx);
12787 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12790 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12791 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12792 unsigned MaxSift = rc->getSize()*8 - 1;
12793 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12794 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12795 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12796 DAG.getConstant(MaxSift, MVT::i8));
12797 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12798 DAG.getIntPtrConstant(0));
12802 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12803 SelectionDAG &DAG) const {
12805 SDValue Vec = Op.getOperand(0);
12806 MVT VecVT = Vec.getSimpleValueType();
12807 SDValue Idx = Op.getOperand(1);
12809 if (Op.getSimpleValueType() == MVT::i1)
12810 return ExtractBitFromMaskVector(Op, DAG);
12812 if (!isa<ConstantSDNode>(Idx)) {
12813 if (VecVT.is512BitVector() ||
12814 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12815 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12818 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12819 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12820 MaskEltVT.getSizeInBits());
12822 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12823 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12824 getZeroVector(MaskVT, Subtarget, DAG, dl),
12825 Idx, DAG.getConstant(0, getPointerTy()));
12826 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12828 Perm, DAG.getConstant(0, getPointerTy()));
12833 // If this is a 256-bit vector result, first extract the 128-bit vector and
12834 // then extract the element from the 128-bit vector.
12835 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12837 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12838 // Get the 128-bit vector.
12839 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12840 MVT EltVT = VecVT.getVectorElementType();
12842 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12844 //if (IdxVal >= NumElems/2)
12845 // IdxVal -= NumElems/2;
12846 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12847 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12848 DAG.getConstant(IdxVal, MVT::i32));
12851 assert(VecVT.is128BitVector() && "Unexpected vector length");
12853 if (Subtarget->hasSSE41()) {
12854 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12859 MVT VT = Op.getSimpleValueType();
12860 // TODO: handle v16i8.
12861 if (VT.getSizeInBits() == 16) {
12862 SDValue Vec = Op.getOperand(0);
12863 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12865 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12866 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12867 DAG.getNode(ISD::BITCAST, dl,
12869 Op.getOperand(1)));
12870 // Transform it so it match pextrw which produces a 32-bit result.
12871 MVT EltVT = MVT::i32;
12872 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12873 Op.getOperand(0), Op.getOperand(1));
12874 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12875 DAG.getValueType(VT));
12876 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12879 if (VT.getSizeInBits() == 32) {
12880 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12884 // SHUFPS the element to the lowest double word, then movss.
12885 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12886 MVT VVT = Op.getOperand(0).getSimpleValueType();
12887 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12888 DAG.getUNDEF(VVT), Mask);
12889 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12890 DAG.getIntPtrConstant(0));
12893 if (VT.getSizeInBits() == 64) {
12894 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12895 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12896 // to match extract_elt for f64.
12897 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12901 // UNPCKHPD the element to the lowest double word, then movsd.
12902 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12903 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12904 int Mask[2] = { 1, -1 };
12905 MVT VVT = Op.getOperand(0).getSimpleValueType();
12906 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12907 DAG.getUNDEF(VVT), Mask);
12908 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12909 DAG.getIntPtrConstant(0));
12915 /// Insert one bit to mask vector, like v16i1 or v8i1.
12916 /// AVX-512 feature.
12918 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12920 SDValue Vec = Op.getOperand(0);
12921 SDValue Elt = Op.getOperand(1);
12922 SDValue Idx = Op.getOperand(2);
12923 MVT VecVT = Vec.getSimpleValueType();
12925 if (!isa<ConstantSDNode>(Idx)) {
12926 // Non constant index. Extend source and destination,
12927 // insert element and then truncate the result.
12928 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12929 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12930 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12931 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12932 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12933 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12936 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12937 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12938 if (Vec.getOpcode() == ISD::UNDEF)
12939 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12940 DAG.getConstant(IdxVal, MVT::i8));
12941 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12942 unsigned MaxSift = rc->getSize()*8 - 1;
12943 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12944 DAG.getConstant(MaxSift, MVT::i8));
12945 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12946 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12947 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12950 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12951 SelectionDAG &DAG) const {
12952 MVT VT = Op.getSimpleValueType();
12953 MVT EltVT = VT.getVectorElementType();
12955 if (EltVT == MVT::i1)
12956 return InsertBitToMaskVector(Op, DAG);
12959 SDValue N0 = Op.getOperand(0);
12960 SDValue N1 = Op.getOperand(1);
12961 SDValue N2 = Op.getOperand(2);
12962 if (!isa<ConstantSDNode>(N2))
12964 auto *N2C = cast<ConstantSDNode>(N2);
12965 unsigned IdxVal = N2C->getZExtValue();
12967 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12968 // into that, and then insert the subvector back into the result.
12969 if (VT.is256BitVector() || VT.is512BitVector()) {
12970 // Get the desired 128-bit vector half.
12971 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12973 // Insert the element into the desired half.
12974 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12975 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12977 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12978 DAG.getConstant(IdxIn128, MVT::i32));
12980 // Insert the changed part back to the 256-bit vector
12981 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12983 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12985 if (Subtarget->hasSSE41()) {
12986 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12988 if (VT == MVT::v8i16) {
12989 Opc = X86ISD::PINSRW;
12991 assert(VT == MVT::v16i8);
12992 Opc = X86ISD::PINSRB;
12995 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12997 if (N1.getValueType() != MVT::i32)
12998 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12999 if (N2.getValueType() != MVT::i32)
13000 N2 = DAG.getIntPtrConstant(IdxVal);
13001 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
13004 if (EltVT == MVT::f32) {
13005 // Bits [7:6] of the constant are the source select. This will always be
13006 // zero here. The DAG Combiner may combine an extract_elt index into
13008 // bits. For example (insert (extract, 3), 2) could be matched by
13010 // the '3' into bits [7:6] of X86ISD::INSERTPS.
13011 // Bits [5:4] of the constant are the destination select. This is the
13012 // value of the incoming immediate.
13013 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
13014 // combine either bitwise AND or insert of float 0.0 to set these bits.
13015 N2 = DAG.getIntPtrConstant(IdxVal << 4);
13016 // Create this as a scalar to vector..
13017 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
13018 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
13021 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
13022 // PINSR* works with constant index.
13027 if (EltVT == MVT::i8)
13030 if (EltVT.getSizeInBits() == 16) {
13031 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
13032 // as its second argument.
13033 if (N1.getValueType() != MVT::i32)
13034 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
13035 if (N2.getValueType() != MVT::i32)
13036 N2 = DAG.getIntPtrConstant(IdxVal);
13037 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
13042 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
13044 MVT OpVT = Op.getSimpleValueType();
13046 // If this is a 256-bit vector result, first insert into a 128-bit
13047 // vector and then insert into the 256-bit vector.
13048 if (!OpVT.is128BitVector()) {
13049 // Insert into a 128-bit vector.
13050 unsigned SizeFactor = OpVT.getSizeInBits()/128;
13051 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
13052 OpVT.getVectorNumElements() / SizeFactor);
13054 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
13056 // Insert the 128-bit vector.
13057 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
13060 if (OpVT == MVT::v1i64 &&
13061 Op.getOperand(0).getValueType() == MVT::i64)
13062 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
13064 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
13065 assert(OpVT.is128BitVector() && "Expected an SSE type!");
13066 return DAG.getNode(ISD::BITCAST, dl, OpVT,
13067 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13070 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13071 // a simple subregister reference or explicit instructions to grab
13072 // upper bits of a vector.
13073 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13074 SelectionDAG &DAG) {
13076 SDValue In = Op.getOperand(0);
13077 SDValue Idx = Op.getOperand(1);
13078 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13079 MVT ResVT = Op.getSimpleValueType();
13080 MVT InVT = In.getSimpleValueType();
13082 if (Subtarget->hasFp256()) {
13083 if (ResVT.is128BitVector() &&
13084 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13085 isa<ConstantSDNode>(Idx)) {
13086 return Extract128BitVector(In, IdxVal, DAG, dl);
13088 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13089 isa<ConstantSDNode>(Idx)) {
13090 return Extract256BitVector(In, IdxVal, DAG, dl);
13096 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13097 // simple superregister reference or explicit instructions to insert
13098 // the upper bits of a vector.
13099 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13100 SelectionDAG &DAG) {
13101 if (Subtarget->hasFp256()) {
13102 SDLoc dl(Op.getNode());
13103 SDValue Vec = Op.getNode()->getOperand(0);
13104 SDValue SubVec = Op.getNode()->getOperand(1);
13105 SDValue Idx = Op.getNode()->getOperand(2);
13107 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13108 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13109 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13110 isa<ConstantSDNode>(Idx)) {
13111 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13112 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13115 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13116 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13117 isa<ConstantSDNode>(Idx)) {
13118 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13119 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13125 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13126 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13127 // one of the above mentioned nodes. It has to be wrapped because otherwise
13128 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13129 // be used to form addressing mode. These wrapped nodes will be selected
13132 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13133 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13135 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13136 // global base reg.
13137 unsigned char OpFlag = 0;
13138 unsigned WrapperKind = X86ISD::Wrapper;
13139 CodeModel::Model M = DAG.getTarget().getCodeModel();
13141 if (Subtarget->isPICStyleRIPRel() &&
13142 (M == CodeModel::Small || M == CodeModel::Kernel))
13143 WrapperKind = X86ISD::WrapperRIP;
13144 else if (Subtarget->isPICStyleGOT())
13145 OpFlag = X86II::MO_GOTOFF;
13146 else if (Subtarget->isPICStyleStubPIC())
13147 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13149 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13150 CP->getAlignment(),
13151 CP->getOffset(), OpFlag);
13153 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13154 // With PIC, the address is actually $g + Offset.
13156 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13157 DAG.getNode(X86ISD::GlobalBaseReg,
13158 SDLoc(), getPointerTy()),
13165 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13166 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13168 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13169 // global base reg.
13170 unsigned char OpFlag = 0;
13171 unsigned WrapperKind = X86ISD::Wrapper;
13172 CodeModel::Model M = DAG.getTarget().getCodeModel();
13174 if (Subtarget->isPICStyleRIPRel() &&
13175 (M == CodeModel::Small || M == CodeModel::Kernel))
13176 WrapperKind = X86ISD::WrapperRIP;
13177 else if (Subtarget->isPICStyleGOT())
13178 OpFlag = X86II::MO_GOTOFF;
13179 else if (Subtarget->isPICStyleStubPIC())
13180 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13182 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13185 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13187 // With PIC, the address is actually $g + Offset.
13189 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13190 DAG.getNode(X86ISD::GlobalBaseReg,
13191 SDLoc(), getPointerTy()),
13198 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13199 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13201 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13202 // global base reg.
13203 unsigned char OpFlag = 0;
13204 unsigned WrapperKind = X86ISD::Wrapper;
13205 CodeModel::Model M = DAG.getTarget().getCodeModel();
13207 if (Subtarget->isPICStyleRIPRel() &&
13208 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13209 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13210 OpFlag = X86II::MO_GOTPCREL;
13211 WrapperKind = X86ISD::WrapperRIP;
13212 } else if (Subtarget->isPICStyleGOT()) {
13213 OpFlag = X86II::MO_GOT;
13214 } else if (Subtarget->isPICStyleStubPIC()) {
13215 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13216 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13217 OpFlag = X86II::MO_DARWIN_NONLAZY;
13220 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13223 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13225 // With PIC, the address is actually $g + Offset.
13226 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13227 !Subtarget->is64Bit()) {
13228 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13229 DAG.getNode(X86ISD::GlobalBaseReg,
13230 SDLoc(), getPointerTy()),
13234 // For symbols that require a load from a stub to get the address, emit the
13236 if (isGlobalStubReference(OpFlag))
13237 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13238 MachinePointerInfo::getGOT(), false, false, false, 0);
13244 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13245 // Create the TargetBlockAddressAddress node.
13246 unsigned char OpFlags =
13247 Subtarget->ClassifyBlockAddressReference();
13248 CodeModel::Model M = DAG.getTarget().getCodeModel();
13249 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13250 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13252 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13255 if (Subtarget->isPICStyleRIPRel() &&
13256 (M == CodeModel::Small || M == CodeModel::Kernel))
13257 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13259 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13261 // With PIC, the address is actually $g + Offset.
13262 if (isGlobalRelativeToPICBase(OpFlags)) {
13263 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13264 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13272 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13273 int64_t Offset, SelectionDAG &DAG) const {
13274 // Create the TargetGlobalAddress node, folding in the constant
13275 // offset if it is legal.
13276 unsigned char OpFlags =
13277 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13278 CodeModel::Model M = DAG.getTarget().getCodeModel();
13280 if (OpFlags == X86II::MO_NO_FLAG &&
13281 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13282 // A direct static reference to a global.
13283 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13286 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13289 if (Subtarget->isPICStyleRIPRel() &&
13290 (M == CodeModel::Small || M == CodeModel::Kernel))
13291 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13293 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13295 // With PIC, the address is actually $g + Offset.
13296 if (isGlobalRelativeToPICBase(OpFlags)) {
13297 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13298 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13302 // For globals that require a load from a stub to get the address, emit the
13304 if (isGlobalStubReference(OpFlags))
13305 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13306 MachinePointerInfo::getGOT(), false, false, false, 0);
13308 // If there was a non-zero offset that we didn't fold, create an explicit
13309 // addition for it.
13311 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13312 DAG.getConstant(Offset, getPointerTy()));
13318 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13319 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13320 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13321 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13325 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13326 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13327 unsigned char OperandFlags, bool LocalDynamic = false) {
13328 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13329 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13331 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13332 GA->getValueType(0),
13336 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13340 SDValue Ops[] = { Chain, TGA, *InFlag };
13341 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13343 SDValue Ops[] = { Chain, TGA };
13344 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13347 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13348 MFI->setAdjustsStack(true);
13349 MFI->setHasCalls(true);
13351 SDValue Flag = Chain.getValue(1);
13352 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13355 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13357 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13360 SDLoc dl(GA); // ? function entry point might be better
13361 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13362 DAG.getNode(X86ISD::GlobalBaseReg,
13363 SDLoc(), PtrVT), InFlag);
13364 InFlag = Chain.getValue(1);
13366 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13369 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13371 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13373 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13374 X86::RAX, X86II::MO_TLSGD);
13377 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13383 // Get the start address of the TLS block for this module.
13384 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13385 .getInfo<X86MachineFunctionInfo>();
13386 MFI->incNumLocalDynamicTLSAccesses();
13390 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13391 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13394 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13395 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13396 InFlag = Chain.getValue(1);
13397 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13398 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13401 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13405 unsigned char OperandFlags = X86II::MO_DTPOFF;
13406 unsigned WrapperKind = X86ISD::Wrapper;
13407 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13408 GA->getValueType(0),
13409 GA->getOffset(), OperandFlags);
13410 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13412 // Add x@dtpoff with the base.
13413 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13416 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13417 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13418 const EVT PtrVT, TLSModel::Model model,
13419 bool is64Bit, bool isPIC) {
13422 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13423 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13424 is64Bit ? 257 : 256));
13426 SDValue ThreadPointer =
13427 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13428 MachinePointerInfo(Ptr), false, false, false, 0);
13430 unsigned char OperandFlags = 0;
13431 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13433 unsigned WrapperKind = X86ISD::Wrapper;
13434 if (model == TLSModel::LocalExec) {
13435 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13436 } else if (model == TLSModel::InitialExec) {
13438 OperandFlags = X86II::MO_GOTTPOFF;
13439 WrapperKind = X86ISD::WrapperRIP;
13441 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13444 llvm_unreachable("Unexpected model");
13447 // emit "addl x@ntpoff,%eax" (local exec)
13448 // or "addl x@indntpoff,%eax" (initial exec)
13449 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13451 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13452 GA->getOffset(), OperandFlags);
13453 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13455 if (model == TLSModel::InitialExec) {
13456 if (isPIC && !is64Bit) {
13457 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13458 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13462 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13463 MachinePointerInfo::getGOT(), false, false, false, 0);
13466 // The address of the thread local variable is the add of the thread
13467 // pointer with the offset of the variable.
13468 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13472 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13474 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13475 const GlobalValue *GV = GA->getGlobal();
13477 if (Subtarget->isTargetELF()) {
13478 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13481 case TLSModel::GeneralDynamic:
13482 if (Subtarget->is64Bit())
13483 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13484 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13485 case TLSModel::LocalDynamic:
13486 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13487 Subtarget->is64Bit());
13488 case TLSModel::InitialExec:
13489 case TLSModel::LocalExec:
13490 return LowerToTLSExecModel(
13491 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13492 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13494 llvm_unreachable("Unknown TLS model.");
13497 if (Subtarget->isTargetDarwin()) {
13498 // Darwin only has one model of TLS. Lower to that.
13499 unsigned char OpFlag = 0;
13500 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13501 X86ISD::WrapperRIP : X86ISD::Wrapper;
13503 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13504 // global base reg.
13505 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13506 !Subtarget->is64Bit();
13508 OpFlag = X86II::MO_TLVP_PIC_BASE;
13510 OpFlag = X86II::MO_TLVP;
13512 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13513 GA->getValueType(0),
13514 GA->getOffset(), OpFlag);
13515 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13517 // With PIC32, the address is actually $g + Offset.
13519 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13520 DAG.getNode(X86ISD::GlobalBaseReg,
13521 SDLoc(), getPointerTy()),
13524 // Lowering the machine isd will make sure everything is in the right
13526 SDValue Chain = DAG.getEntryNode();
13527 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13528 SDValue Args[] = { Chain, Offset };
13529 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13531 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13532 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13533 MFI->setAdjustsStack(true);
13535 // And our return value (tls address) is in the standard call return value
13537 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13538 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13539 Chain.getValue(1));
13542 if (Subtarget->isTargetKnownWindowsMSVC() ||
13543 Subtarget->isTargetWindowsGNU()) {
13544 // Just use the implicit TLS architecture
13545 // Need to generate someting similar to:
13546 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13548 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13549 // mov rcx, qword [rdx+rcx*8]
13550 // mov eax, .tls$:tlsvar
13551 // [rax+rcx] contains the address
13552 // Windows 64bit: gs:0x58
13553 // Windows 32bit: fs:__tls_array
13556 SDValue Chain = DAG.getEntryNode();
13558 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13559 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13560 // use its literal value of 0x2C.
13561 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13562 ? Type::getInt8PtrTy(*DAG.getContext(),
13564 : Type::getInt32PtrTy(*DAG.getContext(),
13568 Subtarget->is64Bit()
13569 ? DAG.getIntPtrConstant(0x58)
13570 : (Subtarget->isTargetWindowsGNU()
13571 ? DAG.getIntPtrConstant(0x2C)
13572 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13574 SDValue ThreadPointer =
13575 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13576 MachinePointerInfo(Ptr), false, false, false, 0);
13578 // Load the _tls_index variable
13579 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13580 if (Subtarget->is64Bit())
13581 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13582 IDX, MachinePointerInfo(), MVT::i32,
13583 false, false, false, 0);
13585 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13586 false, false, false, 0);
13588 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13590 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13592 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13593 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13594 false, false, false, 0);
13596 // Get the offset of start of .tls section
13597 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13598 GA->getValueType(0),
13599 GA->getOffset(), X86II::MO_SECREL);
13600 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13602 // The address of the thread local variable is the add of the thread
13603 // pointer with the offset of the variable.
13604 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13607 llvm_unreachable("TLS not implemented for this target.");
13610 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13611 /// and take a 2 x i32 value to shift plus a shift amount.
13612 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13613 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13614 MVT VT = Op.getSimpleValueType();
13615 unsigned VTBits = VT.getSizeInBits();
13617 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13618 SDValue ShOpLo = Op.getOperand(0);
13619 SDValue ShOpHi = Op.getOperand(1);
13620 SDValue ShAmt = Op.getOperand(2);
13621 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13622 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13624 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13625 DAG.getConstant(VTBits - 1, MVT::i8));
13626 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13627 DAG.getConstant(VTBits - 1, MVT::i8))
13628 : DAG.getConstant(0, VT);
13630 SDValue Tmp2, Tmp3;
13631 if (Op.getOpcode() == ISD::SHL_PARTS) {
13632 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13633 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13635 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13636 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13639 // If the shift amount is larger or equal than the width of a part we can't
13640 // rely on the results of shld/shrd. Insert a test and select the appropriate
13641 // values for large shift amounts.
13642 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13643 DAG.getConstant(VTBits, MVT::i8));
13644 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13645 AndNode, DAG.getConstant(0, MVT::i8));
13648 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13649 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13650 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13652 if (Op.getOpcode() == ISD::SHL_PARTS) {
13653 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13654 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13656 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13657 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13660 SDValue Ops[2] = { Lo, Hi };
13661 return DAG.getMergeValues(Ops, dl);
13664 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13665 SelectionDAG &DAG) const {
13666 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13669 if (SrcVT.isVector()) {
13670 if (SrcVT.getVectorElementType() == MVT::i1) {
13671 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13672 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13673 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13674 Op.getOperand(0)));
13679 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13680 "Unknown SINT_TO_FP to lower!");
13682 // These are really Legal; return the operand so the caller accepts it as
13684 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13686 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13687 Subtarget->is64Bit()) {
13691 unsigned Size = SrcVT.getSizeInBits()/8;
13692 MachineFunction &MF = DAG.getMachineFunction();
13693 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13694 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13695 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13697 MachinePointerInfo::getFixedStack(SSFI),
13699 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13702 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13704 SelectionDAG &DAG) const {
13708 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13710 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13712 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13714 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13716 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13717 MachineMemOperand *MMO;
13719 int SSFI = FI->getIndex();
13721 DAG.getMachineFunction()
13722 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13723 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13725 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13726 StackSlot = StackSlot.getOperand(1);
13728 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13729 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13731 Tys, Ops, SrcVT, MMO);
13734 Chain = Result.getValue(1);
13735 SDValue InFlag = Result.getValue(2);
13737 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13738 // shouldn't be necessary except that RFP cannot be live across
13739 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13740 MachineFunction &MF = DAG.getMachineFunction();
13741 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13742 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13743 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13744 Tys = DAG.getVTList(MVT::Other);
13746 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13748 MachineMemOperand *MMO =
13749 DAG.getMachineFunction()
13750 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13751 MachineMemOperand::MOStore, SSFISize, SSFISize);
13753 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13754 Ops, Op.getValueType(), MMO);
13755 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13756 MachinePointerInfo::getFixedStack(SSFI),
13757 false, false, false, 0);
13763 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13764 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13765 SelectionDAG &DAG) const {
13766 // This algorithm is not obvious. Here it is what we're trying to output:
13769 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13770 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13772 haddpd %xmm0, %xmm0
13774 pshufd $0x4e, %xmm0, %xmm1
13780 LLVMContext *Context = DAG.getContext();
13782 // Build some magic constants.
13783 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13784 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13785 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13787 SmallVector<Constant*,2> CV1;
13789 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13790 APInt(64, 0x4330000000000000ULL))));
13792 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13793 APInt(64, 0x4530000000000000ULL))));
13794 Constant *C1 = ConstantVector::get(CV1);
13795 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13797 // Load the 64-bit value into an XMM register.
13798 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13800 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13801 MachinePointerInfo::getConstantPool(),
13802 false, false, false, 16);
13803 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13804 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13807 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13808 MachinePointerInfo::getConstantPool(),
13809 false, false, false, 16);
13810 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13811 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13814 if (Subtarget->hasSSE3()) {
13815 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13816 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13818 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13819 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13821 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13822 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13826 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13827 DAG.getIntPtrConstant(0));
13830 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13831 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13832 SelectionDAG &DAG) const {
13834 // FP constant to bias correct the final result.
13835 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13838 // Load the 32-bit value into an XMM register.
13839 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13842 // Zero out the upper parts of the register.
13843 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13845 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13846 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13847 DAG.getIntPtrConstant(0));
13849 // Or the load with the bias.
13850 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13851 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13852 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13853 MVT::v2f64, Load)),
13854 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13855 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13856 MVT::v2f64, Bias)));
13857 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13858 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13859 DAG.getIntPtrConstant(0));
13861 // Subtract the bias.
13862 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13864 // Handle final rounding.
13865 EVT DestVT = Op.getValueType();
13867 if (DestVT.bitsLT(MVT::f64))
13868 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13869 DAG.getIntPtrConstant(0));
13870 if (DestVT.bitsGT(MVT::f64))
13871 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13873 // Handle final rounding.
13877 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13878 const X86Subtarget &Subtarget) {
13879 // The algorithm is the following:
13880 // #ifdef __SSE4_1__
13881 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13882 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13883 // (uint4) 0x53000000, 0xaa);
13885 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13886 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13888 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13889 // return (float4) lo + fhi;
13892 SDValue V = Op->getOperand(0);
13893 EVT VecIntVT = V.getValueType();
13894 bool Is128 = VecIntVT == MVT::v4i32;
13895 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13896 // If we convert to something else than the supported type, e.g., to v4f64,
13898 if (VecFloatVT != Op->getValueType(0))
13901 unsigned NumElts = VecIntVT.getVectorNumElements();
13902 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13903 "Unsupported custom type");
13904 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13906 // In the #idef/#else code, we have in common:
13907 // - The vector of constants:
13913 // Create the splat vector for 0x4b000000.
13914 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13915 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13916 CstLow, CstLow, CstLow, CstLow};
13917 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13918 makeArrayRef(&CstLowArray[0], NumElts));
13919 // Create the splat vector for 0x53000000.
13920 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13921 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13922 CstHigh, CstHigh, CstHigh, CstHigh};
13923 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13924 makeArrayRef(&CstHighArray[0], NumElts));
13926 // Create the right shift.
13927 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13928 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13929 CstShift, CstShift, CstShift, CstShift};
13930 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13931 makeArrayRef(&CstShiftArray[0], NumElts));
13932 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13935 if (Subtarget.hasSSE41()) {
13936 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13937 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13938 SDValue VecCstLowBitcast =
13939 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13940 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13941 // Low will be bitcasted right away, so do not bother bitcasting back to its
13943 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13944 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13945 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13946 // (uint4) 0x53000000, 0xaa);
13947 SDValue VecCstHighBitcast =
13948 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13949 SDValue VecShiftBitcast =
13950 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13951 // High will be bitcasted right away, so do not bother bitcasting back to
13952 // its original type.
13953 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13954 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13956 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13957 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13958 CstMask, CstMask, CstMask);
13959 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13960 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13961 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13963 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13964 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13967 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13968 SDValue CstFAdd = DAG.getConstantFP(
13969 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13970 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13971 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13972 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13973 makeArrayRef(&CstFAddArray[0], NumElts));
13975 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13976 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13978 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13979 // return (float4) lo + fhi;
13980 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13981 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13984 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13985 SelectionDAG &DAG) const {
13986 SDValue N0 = Op.getOperand(0);
13987 MVT SVT = N0.getSimpleValueType();
13990 switch (SVT.SimpleTy) {
13992 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13997 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13998 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13999 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
14003 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
14005 llvm_unreachable(nullptr);
14008 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
14009 SelectionDAG &DAG) const {
14010 SDValue N0 = Op.getOperand(0);
14013 if (Op.getValueType().isVector())
14014 return lowerUINT_TO_FP_vec(Op, DAG);
14016 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
14017 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
14018 // the optimization here.
14019 if (DAG.SignBitIsZero(N0))
14020 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
14022 MVT SrcVT = N0.getSimpleValueType();
14023 MVT DstVT = Op.getSimpleValueType();
14024 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
14025 return LowerUINT_TO_FP_i64(Op, DAG);
14026 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
14027 return LowerUINT_TO_FP_i32(Op, DAG);
14028 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
14031 // Make a 64-bit buffer, and use it to build an FILD.
14032 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
14033 if (SrcVT == MVT::i32) {
14034 SDValue WordOff = DAG.getConstant(4, getPointerTy());
14035 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
14036 getPointerTy(), StackSlot, WordOff);
14037 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
14038 StackSlot, MachinePointerInfo(),
14040 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
14041 OffsetSlot, MachinePointerInfo(),
14043 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
14047 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
14048 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
14049 StackSlot, MachinePointerInfo(),
14051 // For i64 source, we need to add the appropriate power of 2 if the input
14052 // was negative. This is the same as the optimization in
14053 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
14054 // we must be careful to do the computation in x87 extended precision, not
14055 // in SSE. (The generic code can't know it's OK to do this, or how to.)
14056 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
14057 MachineMemOperand *MMO =
14058 DAG.getMachineFunction()
14059 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14060 MachineMemOperand::MOLoad, 8, 8);
14062 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
14063 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
14064 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
14067 APInt FF(32, 0x5F800000ULL);
14069 // Check whether the sign bit is set.
14070 SDValue SignSet = DAG.getSetCC(dl,
14071 getSetCCResultType(*DAG.getContext(), MVT::i64),
14072 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14075 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14076 SDValue FudgePtr = DAG.getConstantPool(
14077 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14080 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14081 SDValue Zero = DAG.getIntPtrConstant(0);
14082 SDValue Four = DAG.getIntPtrConstant(4);
14083 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14085 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14087 // Load the value out, extending it from f32 to f80.
14088 // FIXME: Avoid the extend by constructing the right constant pool?
14089 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14090 FudgePtr, MachinePointerInfo::getConstantPool(),
14091 MVT::f32, false, false, false, 4);
14092 // Extend everything to 80 bits to force it to be done on x87.
14093 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14094 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14097 std::pair<SDValue,SDValue>
14098 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14099 bool IsSigned, bool IsReplace) const {
14102 EVT DstTy = Op.getValueType();
14104 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14105 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14109 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14110 DstTy.getSimpleVT() >= MVT::i16 &&
14111 "Unknown FP_TO_INT to lower!");
14113 // These are really Legal.
14114 if (DstTy == MVT::i32 &&
14115 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14116 return std::make_pair(SDValue(), SDValue());
14117 if (Subtarget->is64Bit() &&
14118 DstTy == MVT::i64 &&
14119 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14120 return std::make_pair(SDValue(), SDValue());
14122 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14123 // stack slot, or into the FTOL runtime function.
14124 MachineFunction &MF = DAG.getMachineFunction();
14125 unsigned MemSize = DstTy.getSizeInBits()/8;
14126 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14127 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14130 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14131 Opc = X86ISD::WIN_FTOL;
14133 switch (DstTy.getSimpleVT().SimpleTy) {
14134 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14135 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14136 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14137 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14140 SDValue Chain = DAG.getEntryNode();
14141 SDValue Value = Op.getOperand(0);
14142 EVT TheVT = Op.getOperand(0).getValueType();
14143 // FIXME This causes a redundant load/store if the SSE-class value is already
14144 // in memory, such as if it is on the callstack.
14145 if (isScalarFPTypeInSSEReg(TheVT)) {
14146 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14147 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14148 MachinePointerInfo::getFixedStack(SSFI),
14150 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14152 Chain, StackSlot, DAG.getValueType(TheVT)
14155 MachineMemOperand *MMO =
14156 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14157 MachineMemOperand::MOLoad, MemSize, MemSize);
14158 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14159 Chain = Value.getValue(1);
14160 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14161 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14164 MachineMemOperand *MMO =
14165 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14166 MachineMemOperand::MOStore, MemSize, MemSize);
14168 if (Opc != X86ISD::WIN_FTOL) {
14169 // Build the FP_TO_INT*_IN_MEM
14170 SDValue Ops[] = { Chain, Value, StackSlot };
14171 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14173 return std::make_pair(FIST, StackSlot);
14175 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14176 DAG.getVTList(MVT::Other, MVT::Glue),
14178 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14179 MVT::i32, ftol.getValue(1));
14180 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14181 MVT::i32, eax.getValue(2));
14182 SDValue Ops[] = { eax, edx };
14183 SDValue pair = IsReplace
14184 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14185 : DAG.getMergeValues(Ops, DL);
14186 return std::make_pair(pair, SDValue());
14190 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14191 const X86Subtarget *Subtarget) {
14192 MVT VT = Op->getSimpleValueType(0);
14193 SDValue In = Op->getOperand(0);
14194 MVT InVT = In.getSimpleValueType();
14197 // Optimize vectors in AVX mode:
14200 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14201 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14202 // Concat upper and lower parts.
14205 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14206 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14207 // Concat upper and lower parts.
14210 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14211 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14212 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14215 if (Subtarget->hasInt256())
14216 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14218 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14219 SDValue Undef = DAG.getUNDEF(InVT);
14220 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14221 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14222 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14224 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14225 VT.getVectorNumElements()/2);
14227 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14228 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14230 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14233 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14234 SelectionDAG &DAG) {
14235 MVT VT = Op->getSimpleValueType(0);
14236 SDValue In = Op->getOperand(0);
14237 MVT InVT = In.getSimpleValueType();
14239 unsigned int NumElts = VT.getVectorNumElements();
14240 if (NumElts != 8 && NumElts != 16)
14243 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14244 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14246 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14247 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14248 // Now we have only mask extension
14249 assert(InVT.getVectorElementType() == MVT::i1);
14250 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14251 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14252 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14253 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14254 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14255 MachinePointerInfo::getConstantPool(),
14256 false, false, false, Alignment);
14258 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14259 if (VT.is512BitVector())
14261 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14264 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14265 SelectionDAG &DAG) {
14266 if (Subtarget->hasFp256()) {
14267 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14275 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14276 SelectionDAG &DAG) {
14278 MVT VT = Op.getSimpleValueType();
14279 SDValue In = Op.getOperand(0);
14280 MVT SVT = In.getSimpleValueType();
14282 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14283 return LowerZERO_EXTEND_AVX512(Op, DAG);
14285 if (Subtarget->hasFp256()) {
14286 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14291 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14292 VT.getVectorNumElements() != SVT.getVectorNumElements());
14296 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14298 MVT VT = Op.getSimpleValueType();
14299 SDValue In = Op.getOperand(0);
14300 MVT InVT = In.getSimpleValueType();
14302 if (VT == MVT::i1) {
14303 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14304 "Invalid scalar TRUNCATE operation");
14305 if (InVT.getSizeInBits() >= 32)
14307 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14308 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14310 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14311 "Invalid TRUNCATE operation");
14313 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14314 if (VT.getVectorElementType().getSizeInBits() >=8)
14315 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14317 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14318 unsigned NumElts = InVT.getVectorNumElements();
14319 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14320 if (InVT.getSizeInBits() < 512) {
14321 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14322 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14326 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14327 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14328 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14329 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14330 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14331 MachinePointerInfo::getConstantPool(),
14332 false, false, false, Alignment);
14333 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14334 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14335 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14338 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14339 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14340 if (Subtarget->hasInt256()) {
14341 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14342 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14343 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14345 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14346 DAG.getIntPtrConstant(0));
14349 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14350 DAG.getIntPtrConstant(0));
14351 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14352 DAG.getIntPtrConstant(2));
14353 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14354 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14355 static const int ShufMask[] = {0, 2, 4, 6};
14356 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14359 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14360 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14361 if (Subtarget->hasInt256()) {
14362 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14364 SmallVector<SDValue,32> pshufbMask;
14365 for (unsigned i = 0; i < 2; ++i) {
14366 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14367 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14368 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14369 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14370 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14371 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14372 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14373 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14374 for (unsigned j = 0; j < 8; ++j)
14375 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14377 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14378 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14379 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14381 static const int ShufMask[] = {0, 2, -1, -1};
14382 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14384 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14385 DAG.getIntPtrConstant(0));
14386 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14389 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14390 DAG.getIntPtrConstant(0));
14392 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14393 DAG.getIntPtrConstant(4));
14395 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14396 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14398 // The PSHUFB mask:
14399 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14400 -1, -1, -1, -1, -1, -1, -1, -1};
14402 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14403 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14404 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14406 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14407 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14409 // The MOVLHPS Mask:
14410 static const int ShufMask2[] = {0, 1, 4, 5};
14411 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14412 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14415 // Handle truncation of V256 to V128 using shuffles.
14416 if (!VT.is128BitVector() || !InVT.is256BitVector())
14419 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14421 unsigned NumElems = VT.getVectorNumElements();
14422 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14424 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14425 // Prepare truncation shuffle mask
14426 for (unsigned i = 0; i != NumElems; ++i)
14427 MaskVec[i] = i * 2;
14428 SDValue V = DAG.getVectorShuffle(NVT, DL,
14429 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14430 DAG.getUNDEF(NVT), &MaskVec[0]);
14431 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14432 DAG.getIntPtrConstant(0));
14435 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14436 SelectionDAG &DAG) const {
14437 assert(!Op.getSimpleValueType().isVector());
14439 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14440 /*IsSigned=*/ true, /*IsReplace=*/ false);
14441 SDValue FIST = Vals.first, StackSlot = Vals.second;
14442 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14443 if (!FIST.getNode()) return Op;
14445 if (StackSlot.getNode())
14446 // Load the result.
14447 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14448 FIST, StackSlot, MachinePointerInfo(),
14449 false, false, false, 0);
14451 // The node is the result.
14455 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14456 SelectionDAG &DAG) const {
14457 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14458 /*IsSigned=*/ false, /*IsReplace=*/ false);
14459 SDValue FIST = Vals.first, StackSlot = Vals.second;
14460 assert(FIST.getNode() && "Unexpected failure");
14462 if (StackSlot.getNode())
14463 // Load the result.
14464 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14465 FIST, StackSlot, MachinePointerInfo(),
14466 false, false, false, 0);
14468 // The node is the result.
14472 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14474 MVT VT = Op.getSimpleValueType();
14475 SDValue In = Op.getOperand(0);
14476 MVT SVT = In.getSimpleValueType();
14478 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14480 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14481 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14482 In, DAG.getUNDEF(SVT)));
14485 /// The only differences between FABS and FNEG are the mask and the logic op.
14486 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14487 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14488 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14489 "Wrong opcode for lowering FABS or FNEG.");
14491 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14493 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14494 // into an FNABS. We'll lower the FABS after that if it is still in use.
14496 for (SDNode *User : Op->uses())
14497 if (User->getOpcode() == ISD::FNEG)
14500 SDValue Op0 = Op.getOperand(0);
14501 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14504 MVT VT = Op.getSimpleValueType();
14505 // Assume scalar op for initialization; update for vector if needed.
14506 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14507 // generate a 16-byte vector constant and logic op even for the scalar case.
14508 // Using a 16-byte mask allows folding the load of the mask with
14509 // the logic op, so it can save (~4 bytes) on code size.
14511 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14512 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14513 // decide if we should generate a 16-byte constant mask when we only need 4 or
14514 // 8 bytes for the scalar case.
14515 if (VT.isVector()) {
14516 EltVT = VT.getVectorElementType();
14517 NumElts = VT.getVectorNumElements();
14520 unsigned EltBits = EltVT.getSizeInBits();
14521 LLVMContext *Context = DAG.getContext();
14522 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14524 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14525 Constant *C = ConstantInt::get(*Context, MaskElt);
14526 C = ConstantVector::getSplat(NumElts, C);
14527 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14528 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14529 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14530 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14531 MachinePointerInfo::getConstantPool(),
14532 false, false, false, Alignment);
14534 if (VT.isVector()) {
14535 // For a vector, cast operands to a vector type, perform the logic op,
14536 // and cast the result back to the original value type.
14537 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14538 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14539 SDValue Operand = IsFNABS ?
14540 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14541 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14542 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14543 return DAG.getNode(ISD::BITCAST, dl, VT,
14544 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14547 // If not vector, then scalar.
14548 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14549 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14550 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14553 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14554 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14555 LLVMContext *Context = DAG.getContext();
14556 SDValue Op0 = Op.getOperand(0);
14557 SDValue Op1 = Op.getOperand(1);
14559 MVT VT = Op.getSimpleValueType();
14560 MVT SrcVT = Op1.getSimpleValueType();
14562 // If second operand is smaller, extend it first.
14563 if (SrcVT.bitsLT(VT)) {
14564 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14567 // And if it is bigger, shrink it first.
14568 if (SrcVT.bitsGT(VT)) {
14569 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14573 // At this point the operands and the result should have the same
14574 // type, and that won't be f80 since that is not custom lowered.
14576 const fltSemantics &Sem =
14577 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14578 const unsigned SizeInBits = VT.getSizeInBits();
14580 SmallVector<Constant *, 4> CV(
14581 VT == MVT::f64 ? 2 : 4,
14582 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14584 // First, clear all bits but the sign bit from the second operand (sign).
14585 CV[0] = ConstantFP::get(*Context,
14586 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14587 Constant *C = ConstantVector::get(CV);
14588 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14589 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14590 MachinePointerInfo::getConstantPool(),
14591 false, false, false, 16);
14592 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14594 // Next, clear the sign bit from the first operand (magnitude).
14595 // If it's a constant, we can clear it here.
14596 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
14597 APFloat APF = Op0CN->getValueAPF();
14598 // If the magnitude is a positive zero, the sign bit alone is enough.
14599 if (APF.isPosZero())
14602 CV[0] = ConstantFP::get(*Context, APF);
14604 CV[0] = ConstantFP::get(
14606 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14608 C = ConstantVector::get(CV);
14609 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14610 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14611 MachinePointerInfo::getConstantPool(),
14612 false, false, false, 16);
14613 // If the magnitude operand wasn't a constant, we need to AND out the sign.
14614 if (!isa<ConstantFPSDNode>(Op0))
14615 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
14617 // OR the magnitude value with the sign bit.
14618 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14621 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14622 SDValue N0 = Op.getOperand(0);
14624 MVT VT = Op.getSimpleValueType();
14626 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14627 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14628 DAG.getConstant(1, VT));
14629 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14632 // Check whether an OR'd tree is PTEST-able.
14633 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14634 SelectionDAG &DAG) {
14635 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14637 if (!Subtarget->hasSSE41())
14640 if (!Op->hasOneUse())
14643 SDNode *N = Op.getNode();
14646 SmallVector<SDValue, 8> Opnds;
14647 DenseMap<SDValue, unsigned> VecInMap;
14648 SmallVector<SDValue, 8> VecIns;
14649 EVT VT = MVT::Other;
14651 // Recognize a special case where a vector is casted into wide integer to
14653 Opnds.push_back(N->getOperand(0));
14654 Opnds.push_back(N->getOperand(1));
14656 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14657 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14658 // BFS traverse all OR'd operands.
14659 if (I->getOpcode() == ISD::OR) {
14660 Opnds.push_back(I->getOperand(0));
14661 Opnds.push_back(I->getOperand(1));
14662 // Re-evaluate the number of nodes to be traversed.
14663 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14667 // Quit if a non-EXTRACT_VECTOR_ELT
14668 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14671 // Quit if without a constant index.
14672 SDValue Idx = I->getOperand(1);
14673 if (!isa<ConstantSDNode>(Idx))
14676 SDValue ExtractedFromVec = I->getOperand(0);
14677 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14678 if (M == VecInMap.end()) {
14679 VT = ExtractedFromVec.getValueType();
14680 // Quit if not 128/256-bit vector.
14681 if (!VT.is128BitVector() && !VT.is256BitVector())
14683 // Quit if not the same type.
14684 if (VecInMap.begin() != VecInMap.end() &&
14685 VT != VecInMap.begin()->first.getValueType())
14687 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14688 VecIns.push_back(ExtractedFromVec);
14690 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14693 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14694 "Not extracted from 128-/256-bit vector.");
14696 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14698 for (DenseMap<SDValue, unsigned>::const_iterator
14699 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14700 // Quit if not all elements are used.
14701 if (I->second != FullMask)
14705 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14707 // Cast all vectors into TestVT for PTEST.
14708 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14709 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14711 // If more than one full vectors are evaluated, OR them first before PTEST.
14712 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14713 // Each iteration will OR 2 nodes and append the result until there is only
14714 // 1 node left, i.e. the final OR'd value of all vectors.
14715 SDValue LHS = VecIns[Slot];
14716 SDValue RHS = VecIns[Slot + 1];
14717 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14720 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14721 VecIns.back(), VecIns.back());
14724 /// \brief return true if \c Op has a use that doesn't just read flags.
14725 static bool hasNonFlagsUse(SDValue Op) {
14726 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14728 SDNode *User = *UI;
14729 unsigned UOpNo = UI.getOperandNo();
14730 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14731 // Look pass truncate.
14732 UOpNo = User->use_begin().getOperandNo();
14733 User = *User->use_begin();
14736 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14737 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14743 /// Emit nodes that will be selected as "test Op0,Op0", or something
14745 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14746 SelectionDAG &DAG) const {
14747 if (Op.getValueType() == MVT::i1)
14748 // KORTEST instruction should be selected
14749 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14750 DAG.getConstant(0, Op.getValueType()));
14752 // CF and OF aren't always set the way we want. Determine which
14753 // of these we need.
14754 bool NeedCF = false;
14755 bool NeedOF = false;
14758 case X86::COND_A: case X86::COND_AE:
14759 case X86::COND_B: case X86::COND_BE:
14762 case X86::COND_G: case X86::COND_GE:
14763 case X86::COND_L: case X86::COND_LE:
14764 case X86::COND_O: case X86::COND_NO: {
14765 // Check if we really need to set the
14766 // Overflow flag. If NoSignedWrap is present
14767 // that is not actually needed.
14768 switch (Op->getOpcode()) {
14773 const BinaryWithFlagsSDNode *BinNode =
14774 cast<BinaryWithFlagsSDNode>(Op.getNode());
14775 if (BinNode->hasNoSignedWrap())
14785 // See if we can use the EFLAGS value from the operand instead of
14786 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14787 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14788 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14789 // Emit a CMP with 0, which is the TEST pattern.
14790 //if (Op.getValueType() == MVT::i1)
14791 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14792 // DAG.getConstant(0, MVT::i1));
14793 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14794 DAG.getConstant(0, Op.getValueType()));
14796 unsigned Opcode = 0;
14797 unsigned NumOperands = 0;
14799 // Truncate operations may prevent the merge of the SETCC instruction
14800 // and the arithmetic instruction before it. Attempt to truncate the operands
14801 // of the arithmetic instruction and use a reduced bit-width instruction.
14802 bool NeedTruncation = false;
14803 SDValue ArithOp = Op;
14804 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14805 SDValue Arith = Op->getOperand(0);
14806 // Both the trunc and the arithmetic op need to have one user each.
14807 if (Arith->hasOneUse())
14808 switch (Arith.getOpcode()) {
14815 NeedTruncation = true;
14821 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14822 // which may be the result of a CAST. We use the variable 'Op', which is the
14823 // non-casted variable when we check for possible users.
14824 switch (ArithOp.getOpcode()) {
14826 // Due to an isel shortcoming, be conservative if this add is likely to be
14827 // selected as part of a load-modify-store instruction. When the root node
14828 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14829 // uses of other nodes in the match, such as the ADD in this case. This
14830 // leads to the ADD being left around and reselected, with the result being
14831 // two adds in the output. Alas, even if none our users are stores, that
14832 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14833 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14834 // climbing the DAG back to the root, and it doesn't seem to be worth the
14836 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14837 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14838 if (UI->getOpcode() != ISD::CopyToReg &&
14839 UI->getOpcode() != ISD::SETCC &&
14840 UI->getOpcode() != ISD::STORE)
14843 if (ConstantSDNode *C =
14844 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14845 // An add of one will be selected as an INC.
14846 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14847 Opcode = X86ISD::INC;
14852 // An add of negative one (subtract of one) will be selected as a DEC.
14853 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14854 Opcode = X86ISD::DEC;
14860 // Otherwise use a regular EFLAGS-setting add.
14861 Opcode = X86ISD::ADD;
14866 // If we have a constant logical shift that's only used in a comparison
14867 // against zero turn it into an equivalent AND. This allows turning it into
14868 // a TEST instruction later.
14869 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14870 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14871 EVT VT = Op.getValueType();
14872 unsigned BitWidth = VT.getSizeInBits();
14873 unsigned ShAmt = Op->getConstantOperandVal(1);
14874 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14876 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14877 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14878 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14879 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14881 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14882 DAG.getConstant(Mask, VT));
14883 DAG.ReplaceAllUsesWith(Op, New);
14889 // If the primary and result isn't used, don't bother using X86ISD::AND,
14890 // because a TEST instruction will be better.
14891 if (!hasNonFlagsUse(Op))
14897 // Due to the ISEL shortcoming noted above, be conservative if this op is
14898 // likely to be selected as part of a load-modify-store instruction.
14899 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14900 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14901 if (UI->getOpcode() == ISD::STORE)
14904 // Otherwise use a regular EFLAGS-setting instruction.
14905 switch (ArithOp.getOpcode()) {
14906 default: llvm_unreachable("unexpected operator!");
14907 case ISD::SUB: Opcode = X86ISD::SUB; break;
14908 case ISD::XOR: Opcode = X86ISD::XOR; break;
14909 case ISD::AND: Opcode = X86ISD::AND; break;
14911 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14912 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14913 if (EFLAGS.getNode())
14916 Opcode = X86ISD::OR;
14930 return SDValue(Op.getNode(), 1);
14936 // If we found that truncation is beneficial, perform the truncation and
14938 if (NeedTruncation) {
14939 EVT VT = Op.getValueType();
14940 SDValue WideVal = Op->getOperand(0);
14941 EVT WideVT = WideVal.getValueType();
14942 unsigned ConvertedOp = 0;
14943 // Use a target machine opcode to prevent further DAGCombine
14944 // optimizations that may separate the arithmetic operations
14945 // from the setcc node.
14946 switch (WideVal.getOpcode()) {
14948 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14949 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14950 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14951 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14952 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14956 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14957 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14958 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14959 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14960 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14966 // Emit a CMP with 0, which is the TEST pattern.
14967 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14968 DAG.getConstant(0, Op.getValueType()));
14970 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14971 SmallVector<SDValue, 4> Ops;
14972 for (unsigned i = 0; i != NumOperands; ++i)
14973 Ops.push_back(Op.getOperand(i));
14975 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14976 DAG.ReplaceAllUsesWith(Op, New);
14977 return SDValue(New.getNode(), 1);
14980 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14982 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14983 SDLoc dl, SelectionDAG &DAG) const {
14984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14985 if (C->getAPIntValue() == 0)
14986 return EmitTest(Op0, X86CC, dl, DAG);
14988 if (Op0.getValueType() == MVT::i1)
14989 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14992 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14993 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14994 // Do the comparison at i32 if it's smaller, besides the Atom case.
14995 // This avoids subregister aliasing issues. Keep the smaller reference
14996 // if we're optimizing for size, however, as that'll allow better folding
14997 // of memory operations.
14998 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14999 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
15000 AttributeSet::FunctionIndex, Attribute::MinSize) &&
15001 !Subtarget->isAtom()) {
15002 unsigned ExtendOp =
15003 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
15004 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
15005 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
15007 // Use SUB instead of CMP to enable CSE between SUB and CMP.
15008 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
15009 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
15011 return SDValue(Sub.getNode(), 1);
15013 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
15016 /// Convert a comparison if required by the subtarget.
15017 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
15018 SelectionDAG &DAG) const {
15019 // If the subtarget does not support the FUCOMI instruction, floating-point
15020 // comparisons have to be converted.
15021 if (Subtarget->hasCMov() ||
15022 Cmp.getOpcode() != X86ISD::CMP ||
15023 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
15024 !Cmp.getOperand(1).getValueType().isFloatingPoint())
15027 // The instruction selector will select an FUCOM instruction instead of
15028 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
15029 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
15030 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
15032 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
15033 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
15034 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
15035 DAG.getConstant(8, MVT::i8));
15036 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
15037 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
15040 /// The minimum architected relative accuracy is 2^-12. We need one
15041 /// Newton-Raphson step to have a good float result (24 bits of precision).
15042 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
15043 DAGCombinerInfo &DCI,
15044 unsigned &RefinementSteps,
15045 bool &UseOneConstNR) const {
15046 // FIXME: We should use instruction latency models to calculate the cost of
15047 // each potential sequence, but this is very hard to do reliably because
15048 // at least Intel's Core* chips have variable timing based on the number of
15049 // significant digits in the divisor and/or sqrt operand.
15050 if (!Subtarget->useSqrtEst())
15053 EVT VT = Op.getValueType();
15055 // SSE1 has rsqrtss and rsqrtps.
15056 // TODO: Add support for AVX512 (v16f32).
15057 // It is likely not profitable to do this for f64 because a double-precision
15058 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
15059 // instructions: convert to single, rsqrtss, convert back to double, refine
15060 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
15061 // along with FMA, this could be a throughput win.
15062 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15063 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15064 RefinementSteps = 1;
15065 UseOneConstNR = false;
15066 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
15071 /// The minimum architected relative accuracy is 2^-12. We need one
15072 /// Newton-Raphson step to have a good float result (24 bits of precision).
15073 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
15074 DAGCombinerInfo &DCI,
15075 unsigned &RefinementSteps) const {
15076 // FIXME: We should use instruction latency models to calculate the cost of
15077 // each potential sequence, but this is very hard to do reliably because
15078 // at least Intel's Core* chips have variable timing based on the number of
15079 // significant digits in the divisor.
15080 if (!Subtarget->useReciprocalEst())
15083 EVT VT = Op.getValueType();
15085 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15086 // TODO: Add support for AVX512 (v16f32).
15087 // It is likely not profitable to do this for f64 because a double-precision
15088 // reciprocal estimate with refinement on x86 prior to FMA requires
15089 // 15 instructions: convert to single, rcpss, convert back to double, refine
15090 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15091 // along with FMA, this could be a throughput win.
15092 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15093 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15094 RefinementSteps = ReciprocalEstimateRefinementSteps;
15095 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15100 static bool isAllOnes(SDValue V) {
15101 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15102 return C && C->isAllOnesValue();
15105 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15106 /// if it's possible.
15107 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15108 SDLoc dl, SelectionDAG &DAG) const {
15109 SDValue Op0 = And.getOperand(0);
15110 SDValue Op1 = And.getOperand(1);
15111 if (Op0.getOpcode() == ISD::TRUNCATE)
15112 Op0 = Op0.getOperand(0);
15113 if (Op1.getOpcode() == ISD::TRUNCATE)
15114 Op1 = Op1.getOperand(0);
15117 if (Op1.getOpcode() == ISD::SHL)
15118 std::swap(Op0, Op1);
15119 if (Op0.getOpcode() == ISD::SHL) {
15120 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15121 if (And00C->getZExtValue() == 1) {
15122 // If we looked past a truncate, check that it's only truncating away
15124 unsigned BitWidth = Op0.getValueSizeInBits();
15125 unsigned AndBitWidth = And.getValueSizeInBits();
15126 if (BitWidth > AndBitWidth) {
15128 DAG.computeKnownBits(Op0, Zeros, Ones);
15129 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15133 RHS = Op0.getOperand(1);
15135 } else if (Op1.getOpcode() == ISD::Constant) {
15136 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15137 uint64_t AndRHSVal = AndRHS->getZExtValue();
15138 SDValue AndLHS = Op0;
15140 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15141 LHS = AndLHS.getOperand(0);
15142 RHS = AndLHS.getOperand(1);
15145 // Use BT if the immediate can't be encoded in a TEST instruction.
15146 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15148 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15152 if (LHS.getNode()) {
15153 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15154 // instruction. Since the shift amount is in-range-or-undefined, we know
15155 // that doing a bittest on the i32 value is ok. We extend to i32 because
15156 // the encoding for the i16 version is larger than the i32 version.
15157 // Also promote i16 to i32 for performance / code size reason.
15158 if (LHS.getValueType() == MVT::i8 ||
15159 LHS.getValueType() == MVT::i16)
15160 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15162 // If the operand types disagree, extend the shift amount to match. Since
15163 // BT ignores high bits (like shifts) we can use anyextend.
15164 if (LHS.getValueType() != RHS.getValueType())
15165 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15167 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15168 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15169 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15170 DAG.getConstant(Cond, MVT::i8), BT);
15176 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15178 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15183 // SSE Condition code mapping:
15192 switch (SetCCOpcode) {
15193 default: llvm_unreachable("Unexpected SETCC condition");
15195 case ISD::SETEQ: SSECC = 0; break;
15197 case ISD::SETGT: Swap = true; // Fallthrough
15199 case ISD::SETOLT: SSECC = 1; break;
15201 case ISD::SETGE: Swap = true; // Fallthrough
15203 case ISD::SETOLE: SSECC = 2; break;
15204 case ISD::SETUO: SSECC = 3; break;
15206 case ISD::SETNE: SSECC = 4; break;
15207 case ISD::SETULE: Swap = true; // Fallthrough
15208 case ISD::SETUGE: SSECC = 5; break;
15209 case ISD::SETULT: Swap = true; // Fallthrough
15210 case ISD::SETUGT: SSECC = 6; break;
15211 case ISD::SETO: SSECC = 7; break;
15213 case ISD::SETONE: SSECC = 8; break;
15216 std::swap(Op0, Op1);
15221 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15222 // ones, and then concatenate the result back.
15223 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15224 MVT VT = Op.getSimpleValueType();
15226 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15227 "Unsupported value type for operation");
15229 unsigned NumElems = VT.getVectorNumElements();
15231 SDValue CC = Op.getOperand(2);
15233 // Extract the LHS vectors
15234 SDValue LHS = Op.getOperand(0);
15235 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15236 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15238 // Extract the RHS vectors
15239 SDValue RHS = Op.getOperand(1);
15240 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15241 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15243 // Issue the operation on the smaller types and concatenate the result back
15244 MVT EltVT = VT.getVectorElementType();
15245 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15246 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15247 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15248 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15251 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15252 const X86Subtarget *Subtarget) {
15253 SDValue Op0 = Op.getOperand(0);
15254 SDValue Op1 = Op.getOperand(1);
15255 SDValue CC = Op.getOperand(2);
15256 MVT VT = Op.getSimpleValueType();
15259 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15260 Op.getValueType().getScalarType() == MVT::i1 &&
15261 "Cannot set masked compare for this operation");
15263 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15265 bool Unsigned = false;
15268 switch (SetCCOpcode) {
15269 default: llvm_unreachable("Unexpected SETCC condition");
15270 case ISD::SETNE: SSECC = 4; break;
15271 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15272 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15273 case ISD::SETLT: Swap = true; //fall-through
15274 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15275 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15276 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15277 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15278 case ISD::SETULE: Unsigned = true; //fall-through
15279 case ISD::SETLE: SSECC = 2; break;
15283 std::swap(Op0, Op1);
15285 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15286 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15287 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15288 DAG.getConstant(SSECC, MVT::i8));
15291 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15292 /// operand \p Op1. If non-trivial (for example because it's not constant)
15293 /// return an empty value.
15294 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15296 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15300 MVT VT = Op1.getSimpleValueType();
15301 MVT EVT = VT.getVectorElementType();
15302 unsigned n = VT.getVectorNumElements();
15303 SmallVector<SDValue, 8> ULTOp1;
15305 for (unsigned i = 0; i < n; ++i) {
15306 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15307 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15310 // Avoid underflow.
15311 APInt Val = Elt->getAPIntValue();
15315 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15318 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15321 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15322 SelectionDAG &DAG) {
15323 SDValue Op0 = Op.getOperand(0);
15324 SDValue Op1 = Op.getOperand(1);
15325 SDValue CC = Op.getOperand(2);
15326 MVT VT = Op.getSimpleValueType();
15327 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15328 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15333 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15334 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15337 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15338 unsigned Opc = X86ISD::CMPP;
15339 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15340 assert(VT.getVectorNumElements() <= 16);
15341 Opc = X86ISD::CMPM;
15343 // In the two special cases we can't handle, emit two comparisons.
15346 unsigned CombineOpc;
15347 if (SetCCOpcode == ISD::SETUEQ) {
15348 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15350 assert(SetCCOpcode == ISD::SETONE);
15351 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15354 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15355 DAG.getConstant(CC0, MVT::i8));
15356 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15357 DAG.getConstant(CC1, MVT::i8));
15358 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15360 // Handle all other FP comparisons here.
15361 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15362 DAG.getConstant(SSECC, MVT::i8));
15365 // Break 256-bit integer vector compare into smaller ones.
15366 if (VT.is256BitVector() && !Subtarget->hasInt256())
15367 return Lower256IntVSETCC(Op, DAG);
15369 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15370 EVT OpVT = Op1.getValueType();
15371 if (Subtarget->hasAVX512()) {
15372 if (Op1.getValueType().is512BitVector() ||
15373 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15374 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15375 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15377 // In AVX-512 architecture setcc returns mask with i1 elements,
15378 // But there is no compare instruction for i8 and i16 elements in KNL.
15379 // We are not talking about 512-bit operands in this case, these
15380 // types are illegal.
15382 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15383 OpVT.getVectorElementType().getSizeInBits() >= 8))
15384 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15385 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15388 // We are handling one of the integer comparisons here. Since SSE only has
15389 // GT and EQ comparisons for integer, swapping operands and multiple
15390 // operations may be required for some comparisons.
15392 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15393 bool Subus = false;
15395 switch (SetCCOpcode) {
15396 default: llvm_unreachable("Unexpected SETCC condition");
15397 case ISD::SETNE: Invert = true;
15398 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15399 case ISD::SETLT: Swap = true;
15400 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15401 case ISD::SETGE: Swap = true;
15402 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15403 Invert = true; break;
15404 case ISD::SETULT: Swap = true;
15405 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15406 FlipSigns = true; break;
15407 case ISD::SETUGE: Swap = true;
15408 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15409 FlipSigns = true; Invert = true; break;
15412 // Special case: Use min/max operations for SETULE/SETUGE
15413 MVT VET = VT.getVectorElementType();
15415 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15416 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15419 switch (SetCCOpcode) {
15421 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15422 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15425 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15428 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15429 if (!MinMax && hasSubus) {
15430 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15432 // t = psubus Op0, Op1
15433 // pcmpeq t, <0..0>
15434 switch (SetCCOpcode) {
15436 case ISD::SETULT: {
15437 // If the comparison is against a constant we can turn this into a
15438 // setule. With psubus, setule does not require a swap. This is
15439 // beneficial because the constant in the register is no longer
15440 // destructed as the destination so it can be hoisted out of a loop.
15441 // Only do this pre-AVX since vpcmp* is no longer destructive.
15442 if (Subtarget->hasAVX())
15444 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15445 if (ULEOp1.getNode()) {
15447 Subus = true; Invert = false; Swap = false;
15451 // Psubus is better than flip-sign because it requires no inversion.
15452 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15453 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15457 Opc = X86ISD::SUBUS;
15463 std::swap(Op0, Op1);
15465 // Check that the operation in question is available (most are plain SSE2,
15466 // but PCMPGTQ and PCMPEQQ have different requirements).
15467 if (VT == MVT::v2i64) {
15468 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15469 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15471 // First cast everything to the right type.
15472 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15473 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15475 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15476 // bits of the inputs before performing those operations. The lower
15477 // compare is always unsigned.
15480 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15482 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15483 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15484 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15485 Sign, Zero, Sign, Zero);
15487 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15488 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15490 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15491 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15492 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15494 // Create masks for only the low parts/high parts of the 64 bit integers.
15495 static const int MaskHi[] = { 1, 1, 3, 3 };
15496 static const int MaskLo[] = { 0, 0, 2, 2 };
15497 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15498 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15499 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15501 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15502 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15505 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15507 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15510 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15511 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15512 // pcmpeqd + pshufd + pand.
15513 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15515 // First cast everything to the right type.
15516 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15517 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15520 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15522 // Make sure the lower and upper halves are both all-ones.
15523 static const int Mask[] = { 1, 0, 3, 2 };
15524 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15525 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15528 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15530 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15534 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15535 // bits of the inputs before performing those operations.
15537 EVT EltVT = VT.getVectorElementType();
15538 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15539 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15540 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15543 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15545 // If the logical-not of the result is required, perform that now.
15547 Result = DAG.getNOT(dl, Result, VT);
15550 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15553 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15554 getZeroVector(VT, Subtarget, DAG, dl));
15559 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15561 MVT VT = Op.getSimpleValueType();
15563 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15565 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15566 && "SetCC type must be 8-bit or 1-bit integer");
15567 SDValue Op0 = Op.getOperand(0);
15568 SDValue Op1 = Op.getOperand(1);
15570 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15572 // Optimize to BT if possible.
15573 // Lower (X & (1 << N)) == 0 to BT(X, N).
15574 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15575 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15576 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15577 Op1.getOpcode() == ISD::Constant &&
15578 cast<ConstantSDNode>(Op1)->isNullValue() &&
15579 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15580 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15581 if (NewSetCC.getNode()) {
15583 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15588 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15590 if (Op1.getOpcode() == ISD::Constant &&
15591 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15592 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15593 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15595 // If the input is a setcc, then reuse the input setcc or use a new one with
15596 // the inverted condition.
15597 if (Op0.getOpcode() == X86ISD::SETCC) {
15598 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15599 bool Invert = (CC == ISD::SETNE) ^
15600 cast<ConstantSDNode>(Op1)->isNullValue();
15604 CCode = X86::GetOppositeBranchCondition(CCode);
15605 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15606 DAG.getConstant(CCode, MVT::i8),
15607 Op0.getOperand(1));
15609 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15613 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15614 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15615 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15617 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15618 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15621 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15622 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15623 if (X86CC == X86::COND_INVALID)
15626 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15627 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15628 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15629 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15631 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15635 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15636 static bool isX86LogicalCmp(SDValue Op) {
15637 unsigned Opc = Op.getNode()->getOpcode();
15638 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15639 Opc == X86ISD::SAHF)
15641 if (Op.getResNo() == 1 &&
15642 (Opc == X86ISD::ADD ||
15643 Opc == X86ISD::SUB ||
15644 Opc == X86ISD::ADC ||
15645 Opc == X86ISD::SBB ||
15646 Opc == X86ISD::SMUL ||
15647 Opc == X86ISD::UMUL ||
15648 Opc == X86ISD::INC ||
15649 Opc == X86ISD::DEC ||
15650 Opc == X86ISD::OR ||
15651 Opc == X86ISD::XOR ||
15652 Opc == X86ISD::AND))
15655 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15661 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15662 if (V.getOpcode() != ISD::TRUNCATE)
15665 SDValue VOp0 = V.getOperand(0);
15666 unsigned InBits = VOp0.getValueSizeInBits();
15667 unsigned Bits = V.getValueSizeInBits();
15668 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15671 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15672 bool addTest = true;
15673 SDValue Cond = Op.getOperand(0);
15674 SDValue Op1 = Op.getOperand(1);
15675 SDValue Op2 = Op.getOperand(2);
15677 EVT VT = Op1.getValueType();
15680 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15681 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15682 // sequence later on.
15683 if (Cond.getOpcode() == ISD::SETCC &&
15684 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15685 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15686 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15687 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15688 int SSECC = translateX86FSETCC(
15689 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15692 if (Subtarget->hasAVX512()) {
15693 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15694 DAG.getConstant(SSECC, MVT::i8));
15695 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15697 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15698 DAG.getConstant(SSECC, MVT::i8));
15699 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15700 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15701 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15705 if (Cond.getOpcode() == ISD::SETCC) {
15706 SDValue NewCond = LowerSETCC(Cond, DAG);
15707 if (NewCond.getNode())
15711 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15712 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15713 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15714 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15715 if (Cond.getOpcode() == X86ISD::SETCC &&
15716 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15717 isZero(Cond.getOperand(1).getOperand(1))) {
15718 SDValue Cmp = Cond.getOperand(1);
15720 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15722 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15723 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15724 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15726 SDValue CmpOp0 = Cmp.getOperand(0);
15727 // Apply further optimizations for special cases
15728 // (select (x != 0), -1, 0) -> neg & sbb
15729 // (select (x == 0), 0, -1) -> neg & sbb
15730 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15731 if (YC->isNullValue() &&
15732 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15733 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15734 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15735 DAG.getConstant(0, CmpOp0.getValueType()),
15737 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15738 DAG.getConstant(X86::COND_B, MVT::i8),
15739 SDValue(Neg.getNode(), 1));
15743 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15744 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15745 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15747 SDValue Res = // Res = 0 or -1.
15748 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15749 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15751 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15752 Res = DAG.getNOT(DL, Res, Res.getValueType());
15754 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15755 if (!N2C || !N2C->isNullValue())
15756 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15761 // Look past (and (setcc_carry (cmp ...)), 1).
15762 if (Cond.getOpcode() == ISD::AND &&
15763 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15764 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15765 if (C && C->getAPIntValue() == 1)
15766 Cond = Cond.getOperand(0);
15769 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15770 // setting operand in place of the X86ISD::SETCC.
15771 unsigned CondOpcode = Cond.getOpcode();
15772 if (CondOpcode == X86ISD::SETCC ||
15773 CondOpcode == X86ISD::SETCC_CARRY) {
15774 CC = Cond.getOperand(0);
15776 SDValue Cmp = Cond.getOperand(1);
15777 unsigned Opc = Cmp.getOpcode();
15778 MVT VT = Op.getSimpleValueType();
15780 bool IllegalFPCMov = false;
15781 if (VT.isFloatingPoint() && !VT.isVector() &&
15782 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15783 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15785 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15786 Opc == X86ISD::BT) { // FIXME
15790 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15791 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15792 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15793 Cond.getOperand(0).getValueType() != MVT::i8)) {
15794 SDValue LHS = Cond.getOperand(0);
15795 SDValue RHS = Cond.getOperand(1);
15796 unsigned X86Opcode;
15799 switch (CondOpcode) {
15800 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15801 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15802 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15803 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15804 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15805 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15806 default: llvm_unreachable("unexpected overflowing operator");
15808 if (CondOpcode == ISD::UMULO)
15809 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15812 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15814 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15816 if (CondOpcode == ISD::UMULO)
15817 Cond = X86Op.getValue(2);
15819 Cond = X86Op.getValue(1);
15821 CC = DAG.getConstant(X86Cond, MVT::i8);
15826 // Look pass the truncate if the high bits are known zero.
15827 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15828 Cond = Cond.getOperand(0);
15830 // We know the result of AND is compared against zero. Try to match
15832 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15833 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15834 if (NewSetCC.getNode()) {
15835 CC = NewSetCC.getOperand(0);
15836 Cond = NewSetCC.getOperand(1);
15843 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15844 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15847 // a < b ? -1 : 0 -> RES = ~setcc_carry
15848 // a < b ? 0 : -1 -> RES = setcc_carry
15849 // a >= b ? -1 : 0 -> RES = setcc_carry
15850 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15851 if (Cond.getOpcode() == X86ISD::SUB) {
15852 Cond = ConvertCmpIfNecessary(Cond, DAG);
15853 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15855 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15856 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15857 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15858 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15859 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15860 return DAG.getNOT(DL, Res, Res.getValueType());
15865 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15866 // widen the cmov and push the truncate through. This avoids introducing a new
15867 // branch during isel and doesn't add any extensions.
15868 if (Op.getValueType() == MVT::i8 &&
15869 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15870 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15871 if (T1.getValueType() == T2.getValueType() &&
15872 // Blacklist CopyFromReg to avoid partial register stalls.
15873 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15874 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15875 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15876 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15880 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15881 // condition is true.
15882 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15883 SDValue Ops[] = { Op2, Op1, CC, Cond };
15884 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15887 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15888 SelectionDAG &DAG) {
15889 MVT VT = Op->getSimpleValueType(0);
15890 SDValue In = Op->getOperand(0);
15891 MVT InVT = In.getSimpleValueType();
15892 MVT VTElt = VT.getVectorElementType();
15893 MVT InVTElt = InVT.getVectorElementType();
15897 if ((InVTElt == MVT::i1) &&
15898 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15899 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15901 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15902 VTElt.getSizeInBits() <= 16)) ||
15904 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15905 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15907 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15908 VTElt.getSizeInBits() >= 32))))
15909 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15911 unsigned int NumElts = VT.getVectorNumElements();
15913 if (NumElts != 8 && NumElts != 16)
15916 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15917 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15918 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15919 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15922 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15923 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15925 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15926 Constant *C = ConstantInt::get(*DAG.getContext(),
15927 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15929 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15930 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15931 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15932 MachinePointerInfo::getConstantPool(),
15933 false, false, false, Alignment);
15934 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15935 if (VT.is512BitVector())
15937 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15940 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15941 SelectionDAG &DAG) {
15942 MVT VT = Op->getSimpleValueType(0);
15943 SDValue In = Op->getOperand(0);
15944 MVT InVT = In.getSimpleValueType();
15947 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15948 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15950 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15951 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15952 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15955 if (Subtarget->hasInt256())
15956 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15958 // Optimize vectors in AVX mode
15959 // Sign extend v8i16 to v8i32 and
15962 // Divide input vector into two parts
15963 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15964 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15965 // concat the vectors to original VT
15967 unsigned NumElems = InVT.getVectorNumElements();
15968 SDValue Undef = DAG.getUNDEF(InVT);
15970 SmallVector<int,8> ShufMask1(NumElems, -1);
15971 for (unsigned i = 0; i != NumElems/2; ++i)
15974 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15976 SmallVector<int,8> ShufMask2(NumElems, -1);
15977 for (unsigned i = 0; i != NumElems/2; ++i)
15978 ShufMask2[i] = i + NumElems/2;
15980 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15982 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15983 VT.getVectorNumElements()/2);
15985 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15986 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15988 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15991 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15992 // may emit an illegal shuffle but the expansion is still better than scalar
15993 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15994 // we'll emit a shuffle and a arithmetic shift.
15995 // TODO: It is possible to support ZExt by zeroing the undef values during
15996 // the shuffle phase or after the shuffle.
15997 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15998 SelectionDAG &DAG) {
15999 MVT RegVT = Op.getSimpleValueType();
16000 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
16001 assert(RegVT.isInteger() &&
16002 "We only custom lower integer vector sext loads.");
16004 // Nothing useful we can do without SSE2 shuffles.
16005 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
16007 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
16009 EVT MemVT = Ld->getMemoryVT();
16010 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16011 unsigned RegSz = RegVT.getSizeInBits();
16013 ISD::LoadExtType Ext = Ld->getExtensionType();
16015 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
16016 && "Only anyext and sext are currently implemented.");
16017 assert(MemVT != RegVT && "Cannot extend to the same type");
16018 assert(MemVT.isVector() && "Must load a vector from memory");
16020 unsigned NumElems = RegVT.getVectorNumElements();
16021 unsigned MemSz = MemVT.getSizeInBits();
16022 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16024 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
16025 // The only way in which we have a legal 256-bit vector result but not the
16026 // integer 256-bit operations needed to directly lower a sextload is if we
16027 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
16028 // a 128-bit vector and a normal sign_extend to 256-bits that should get
16029 // correctly legalized. We do this late to allow the canonical form of
16030 // sextload to persist throughout the rest of the DAG combiner -- it wants
16031 // to fold together any extensions it can, and so will fuse a sign_extend
16032 // of an sextload into a sextload targeting a wider value.
16034 if (MemSz == 128) {
16035 // Just switch this to a normal load.
16036 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
16037 "it must be a legal 128-bit vector "
16039 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
16040 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
16041 Ld->isInvariant(), Ld->getAlignment());
16043 assert(MemSz < 128 &&
16044 "Can't extend a type wider than 128 bits to a 256 bit vector!");
16045 // Do an sext load to a 128-bit vector type. We want to use the same
16046 // number of elements, but elements half as wide. This will end up being
16047 // recursively lowered by this routine, but will succeed as we definitely
16048 // have all the necessary features if we're using AVX1.
16050 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
16051 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
16053 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
16054 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
16055 Ld->isNonTemporal(), Ld->isInvariant(),
16056 Ld->getAlignment());
16059 // Replace chain users with the new chain.
16060 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
16061 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
16063 // Finally, do a normal sign-extend to the desired register.
16064 return DAG.getSExtOrTrunc(Load, dl, RegVT);
16067 // All sizes must be a power of two.
16068 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
16069 "Non-power-of-two elements are not custom lowered!");
16071 // Attempt to load the original value using scalar loads.
16072 // Find the largest scalar type that divides the total loaded size.
16073 MVT SclrLoadTy = MVT::i8;
16074 for (MVT Tp : MVT::integer_valuetypes()) {
16075 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16080 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16081 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16083 SclrLoadTy = MVT::f64;
16085 // Calculate the number of scalar loads that we need to perform
16086 // in order to load our vector from memory.
16087 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16089 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16090 "Can only lower sext loads with a single scalar load!");
16092 unsigned loadRegZize = RegSz;
16093 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16096 // Represent our vector as a sequence of elements which are the
16097 // largest scalar that we can load.
16098 EVT LoadUnitVecVT = EVT::getVectorVT(
16099 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16101 // Represent the data using the same element type that is stored in
16102 // memory. In practice, we ''widen'' MemVT.
16104 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16105 loadRegZize / MemVT.getScalarType().getSizeInBits());
16107 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16108 "Invalid vector type");
16110 // We can't shuffle using an illegal type.
16111 assert(TLI.isTypeLegal(WideVecVT) &&
16112 "We only lower types that form legal widened vector types");
16114 SmallVector<SDValue, 8> Chains;
16115 SDValue Ptr = Ld->getBasePtr();
16116 SDValue Increment =
16117 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16118 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16120 for (unsigned i = 0; i < NumLoads; ++i) {
16121 // Perform a single load.
16122 SDValue ScalarLoad =
16123 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16124 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16125 Ld->getAlignment());
16126 Chains.push_back(ScalarLoad.getValue(1));
16127 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16128 // another round of DAGCombining.
16130 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16132 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16133 ScalarLoad, DAG.getIntPtrConstant(i));
16135 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16138 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16140 // Bitcast the loaded value to a vector of the original element type, in
16141 // the size of the target vector type.
16142 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16143 unsigned SizeRatio = RegSz / MemSz;
16145 if (Ext == ISD::SEXTLOAD) {
16146 // If we have SSE4.1, we can directly emit a VSEXT node.
16147 if (Subtarget->hasSSE41()) {
16148 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16149 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16153 // Otherwise we'll shuffle the small elements in the high bits of the
16154 // larger type and perform an arithmetic shift. If the shift is not legal
16155 // it's better to scalarize.
16156 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16157 "We can't implement a sext load without an arithmetic right shift!");
16159 // Redistribute the loaded elements into the different locations.
16160 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16161 for (unsigned i = 0; i != NumElems; ++i)
16162 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16164 SDValue Shuff = DAG.getVectorShuffle(
16165 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16167 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16169 // Build the arithmetic shift.
16170 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16171 MemVT.getVectorElementType().getSizeInBits();
16173 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16175 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16179 // Redistribute the loaded elements into the different locations.
16180 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16181 for (unsigned i = 0; i != NumElems; ++i)
16182 ShuffleVec[i * SizeRatio] = i;
16184 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16185 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16187 // Bitcast to the requested type.
16188 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16189 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16193 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16194 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16195 // from the AND / OR.
16196 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16197 Opc = Op.getOpcode();
16198 if (Opc != ISD::OR && Opc != ISD::AND)
16200 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16201 Op.getOperand(0).hasOneUse() &&
16202 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16203 Op.getOperand(1).hasOneUse());
16206 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16207 // 1 and that the SETCC node has a single use.
16208 static bool isXor1OfSetCC(SDValue Op) {
16209 if (Op.getOpcode() != ISD::XOR)
16211 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16212 if (N1C && N1C->getAPIntValue() == 1) {
16213 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16214 Op.getOperand(0).hasOneUse();
16219 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16220 bool addTest = true;
16221 SDValue Chain = Op.getOperand(0);
16222 SDValue Cond = Op.getOperand(1);
16223 SDValue Dest = Op.getOperand(2);
16226 bool Inverted = false;
16228 if (Cond.getOpcode() == ISD::SETCC) {
16229 // Check for setcc([su]{add,sub,mul}o == 0).
16230 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16231 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16232 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16233 Cond.getOperand(0).getResNo() == 1 &&
16234 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16235 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16236 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16237 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16238 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16239 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16241 Cond = Cond.getOperand(0);
16243 SDValue NewCond = LowerSETCC(Cond, DAG);
16244 if (NewCond.getNode())
16249 // FIXME: LowerXALUO doesn't handle these!!
16250 else if (Cond.getOpcode() == X86ISD::ADD ||
16251 Cond.getOpcode() == X86ISD::SUB ||
16252 Cond.getOpcode() == X86ISD::SMUL ||
16253 Cond.getOpcode() == X86ISD::UMUL)
16254 Cond = LowerXALUO(Cond, DAG);
16257 // Look pass (and (setcc_carry (cmp ...)), 1).
16258 if (Cond.getOpcode() == ISD::AND &&
16259 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16260 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16261 if (C && C->getAPIntValue() == 1)
16262 Cond = Cond.getOperand(0);
16265 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16266 // setting operand in place of the X86ISD::SETCC.
16267 unsigned CondOpcode = Cond.getOpcode();
16268 if (CondOpcode == X86ISD::SETCC ||
16269 CondOpcode == X86ISD::SETCC_CARRY) {
16270 CC = Cond.getOperand(0);
16272 SDValue Cmp = Cond.getOperand(1);
16273 unsigned Opc = Cmp.getOpcode();
16274 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16275 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16279 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16283 // These can only come from an arithmetic instruction with overflow,
16284 // e.g. SADDO, UADDO.
16285 Cond = Cond.getNode()->getOperand(1);
16291 CondOpcode = Cond.getOpcode();
16292 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16293 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16294 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16295 Cond.getOperand(0).getValueType() != MVT::i8)) {
16296 SDValue LHS = Cond.getOperand(0);
16297 SDValue RHS = Cond.getOperand(1);
16298 unsigned X86Opcode;
16301 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16302 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16304 switch (CondOpcode) {
16305 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16309 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16312 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16313 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16315 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16317 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16320 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16321 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16322 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16323 default: llvm_unreachable("unexpected overflowing operator");
16326 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16327 if (CondOpcode == ISD::UMULO)
16328 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16331 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16333 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16335 if (CondOpcode == ISD::UMULO)
16336 Cond = X86Op.getValue(2);
16338 Cond = X86Op.getValue(1);
16340 CC = DAG.getConstant(X86Cond, MVT::i8);
16344 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16345 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16346 if (CondOpc == ISD::OR) {
16347 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16348 // two branches instead of an explicit OR instruction with a
16350 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16351 isX86LogicalCmp(Cmp)) {
16352 CC = Cond.getOperand(0).getOperand(0);
16353 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16354 Chain, Dest, CC, Cmp);
16355 CC = Cond.getOperand(1).getOperand(0);
16359 } else { // ISD::AND
16360 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16361 // two branches instead of an explicit AND instruction with a
16362 // separate test. However, we only do this if this block doesn't
16363 // have a fall-through edge, because this requires an explicit
16364 // jmp when the condition is false.
16365 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16366 isX86LogicalCmp(Cmp) &&
16367 Op.getNode()->hasOneUse()) {
16368 X86::CondCode CCode =
16369 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16370 CCode = X86::GetOppositeBranchCondition(CCode);
16371 CC = DAG.getConstant(CCode, MVT::i8);
16372 SDNode *User = *Op.getNode()->use_begin();
16373 // Look for an unconditional branch following this conditional branch.
16374 // We need this because we need to reverse the successors in order
16375 // to implement FCMP_OEQ.
16376 if (User->getOpcode() == ISD::BR) {
16377 SDValue FalseBB = User->getOperand(1);
16379 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16380 assert(NewBR == User);
16384 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16385 Chain, Dest, CC, Cmp);
16386 X86::CondCode CCode =
16387 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16388 CCode = X86::GetOppositeBranchCondition(CCode);
16389 CC = DAG.getConstant(CCode, MVT::i8);
16395 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16396 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16397 // It should be transformed during dag combiner except when the condition
16398 // is set by a arithmetics with overflow node.
16399 X86::CondCode CCode =
16400 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16401 CCode = X86::GetOppositeBranchCondition(CCode);
16402 CC = DAG.getConstant(CCode, MVT::i8);
16403 Cond = Cond.getOperand(0).getOperand(1);
16405 } else if (Cond.getOpcode() == ISD::SETCC &&
16406 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16407 // For FCMP_OEQ, we can emit
16408 // two branches instead of an explicit AND instruction with a
16409 // separate test. However, we only do this if this block doesn't
16410 // have a fall-through edge, because this requires an explicit
16411 // jmp when the condition is false.
16412 if (Op.getNode()->hasOneUse()) {
16413 SDNode *User = *Op.getNode()->use_begin();
16414 // Look for an unconditional branch following this conditional branch.
16415 // We need this because we need to reverse the successors in order
16416 // to implement FCMP_OEQ.
16417 if (User->getOpcode() == ISD::BR) {
16418 SDValue FalseBB = User->getOperand(1);
16420 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16421 assert(NewBR == User);
16425 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16426 Cond.getOperand(0), Cond.getOperand(1));
16427 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16428 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16429 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16430 Chain, Dest, CC, Cmp);
16431 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16436 } else if (Cond.getOpcode() == ISD::SETCC &&
16437 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16438 // For FCMP_UNE, we can emit
16439 // two branches instead of an explicit AND instruction with a
16440 // separate test. However, we only do this if this block doesn't
16441 // have a fall-through edge, because this requires an explicit
16442 // jmp when the condition is false.
16443 if (Op.getNode()->hasOneUse()) {
16444 SDNode *User = *Op.getNode()->use_begin();
16445 // Look for an unconditional branch following this conditional branch.
16446 // We need this because we need to reverse the successors in order
16447 // to implement FCMP_UNE.
16448 if (User->getOpcode() == ISD::BR) {
16449 SDValue FalseBB = User->getOperand(1);
16451 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16452 assert(NewBR == User);
16455 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16456 Cond.getOperand(0), Cond.getOperand(1));
16457 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16458 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16459 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16460 Chain, Dest, CC, Cmp);
16461 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16471 // Look pass the truncate if the high bits are known zero.
16472 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16473 Cond = Cond.getOperand(0);
16475 // We know the result of AND is compared against zero. Try to match
16477 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16478 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16479 if (NewSetCC.getNode()) {
16480 CC = NewSetCC.getOperand(0);
16481 Cond = NewSetCC.getOperand(1);
16488 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16489 CC = DAG.getConstant(X86Cond, MVT::i8);
16490 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16492 Cond = ConvertCmpIfNecessary(Cond, DAG);
16493 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16494 Chain, Dest, CC, Cond);
16497 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16498 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16499 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16500 // that the guard pages used by the OS virtual memory manager are allocated in
16501 // correct sequence.
16503 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16504 SelectionDAG &DAG) const {
16505 MachineFunction &MF = DAG.getMachineFunction();
16506 bool SplitStack = MF.shouldSplitStack();
16507 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16513 SDNode* Node = Op.getNode();
16515 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16516 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16517 " not tell us which reg is the stack pointer!");
16518 EVT VT = Node->getValueType(0);
16519 SDValue Tmp1 = SDValue(Node, 0);
16520 SDValue Tmp2 = SDValue(Node, 1);
16521 SDValue Tmp3 = Node->getOperand(2);
16522 SDValue Chain = Tmp1.getOperand(0);
16524 // Chain the dynamic stack allocation so that it doesn't modify the stack
16525 // pointer when other instructions are using the stack.
16526 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16529 SDValue Size = Tmp2.getOperand(1);
16530 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16531 Chain = SP.getValue(1);
16532 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16533 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16534 unsigned StackAlign = TFI.getStackAlignment();
16535 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16536 if (Align > StackAlign)
16537 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16538 DAG.getConstant(-(uint64_t)Align, VT));
16539 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16541 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16542 DAG.getIntPtrConstant(0, true), SDValue(),
16545 SDValue Ops[2] = { Tmp1, Tmp2 };
16546 return DAG.getMergeValues(Ops, dl);
16550 SDValue Chain = Op.getOperand(0);
16551 SDValue Size = Op.getOperand(1);
16552 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16553 EVT VT = Op.getNode()->getValueType(0);
16555 bool Is64Bit = Subtarget->is64Bit();
16556 EVT SPTy = getPointerTy();
16559 MachineRegisterInfo &MRI = MF.getRegInfo();
16562 // The 64 bit implementation of segmented stacks needs to clobber both r10
16563 // r11. This makes it impossible to use it along with nested parameters.
16564 const Function *F = MF.getFunction();
16566 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16568 if (I->hasNestAttr())
16569 report_fatal_error("Cannot use segmented stacks with functions that "
16570 "have nested arguments.");
16573 const TargetRegisterClass *AddrRegClass =
16574 getRegClassFor(getPointerTy());
16575 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16576 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16577 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16578 DAG.getRegister(Vreg, SPTy));
16579 SDValue Ops1[2] = { Value, Chain };
16580 return DAG.getMergeValues(Ops1, dl);
16583 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16585 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16586 Flag = Chain.getValue(1);
16587 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16589 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16591 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16592 DAG.getSubtarget().getRegisterInfo());
16593 unsigned SPReg = RegInfo->getStackRegister();
16594 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16595 Chain = SP.getValue(1);
16598 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16599 DAG.getConstant(-(uint64_t)Align, VT));
16600 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16603 SDValue Ops1[2] = { SP, Chain };
16604 return DAG.getMergeValues(Ops1, dl);
16608 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16609 MachineFunction &MF = DAG.getMachineFunction();
16610 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16612 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16615 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16616 // vastart just stores the address of the VarArgsFrameIndex slot into the
16617 // memory location argument.
16618 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16620 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16621 MachinePointerInfo(SV), false, false, 0);
16625 // gp_offset (0 - 6 * 8)
16626 // fp_offset (48 - 48 + 8 * 16)
16627 // overflow_arg_area (point to parameters coming in memory).
16629 SmallVector<SDValue, 8> MemOps;
16630 SDValue FIN = Op.getOperand(1);
16632 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16633 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16635 FIN, MachinePointerInfo(SV), false, false, 0);
16636 MemOps.push_back(Store);
16639 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16640 FIN, DAG.getIntPtrConstant(4));
16641 Store = DAG.getStore(Op.getOperand(0), DL,
16642 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16644 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16645 MemOps.push_back(Store);
16647 // Store ptr to overflow_arg_area
16648 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16649 FIN, DAG.getIntPtrConstant(4));
16650 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16652 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16653 MachinePointerInfo(SV, 8),
16655 MemOps.push_back(Store);
16657 // Store ptr to reg_save_area.
16658 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16659 FIN, DAG.getIntPtrConstant(8));
16660 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16662 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16663 MachinePointerInfo(SV, 16), false, false, 0);
16664 MemOps.push_back(Store);
16665 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16668 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16669 assert(Subtarget->is64Bit() &&
16670 "LowerVAARG only handles 64-bit va_arg!");
16671 assert((Subtarget->isTargetLinux() ||
16672 Subtarget->isTargetDarwin()) &&
16673 "Unhandled target in LowerVAARG");
16674 assert(Op.getNode()->getNumOperands() == 4);
16675 SDValue Chain = Op.getOperand(0);
16676 SDValue SrcPtr = Op.getOperand(1);
16677 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16678 unsigned Align = Op.getConstantOperandVal(3);
16681 EVT ArgVT = Op.getNode()->getValueType(0);
16682 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16683 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16686 // Decide which area this value should be read from.
16687 // TODO: Implement the AMD64 ABI in its entirety. This simple
16688 // selection mechanism works only for the basic types.
16689 if (ArgVT == MVT::f80) {
16690 llvm_unreachable("va_arg for f80 not yet implemented");
16691 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16692 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16693 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16694 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16696 llvm_unreachable("Unhandled argument type in LowerVAARG");
16699 if (ArgMode == 2) {
16700 // Sanity Check: Make sure using fp_offset makes sense.
16701 assert(!DAG.getTarget().Options.UseSoftFloat &&
16702 !(DAG.getMachineFunction()
16703 .getFunction()->getAttributes()
16704 .hasAttribute(AttributeSet::FunctionIndex,
16705 Attribute::NoImplicitFloat)) &&
16706 Subtarget->hasSSE1());
16709 // Insert VAARG_64 node into the DAG
16710 // VAARG_64 returns two values: Variable Argument Address, Chain
16711 SmallVector<SDValue, 11> InstOps;
16712 InstOps.push_back(Chain);
16713 InstOps.push_back(SrcPtr);
16714 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16715 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16716 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16717 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16718 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16719 VTs, InstOps, MVT::i64,
16720 MachinePointerInfo(SV),
16722 /*Volatile=*/false,
16724 /*WriteMem=*/true);
16725 Chain = VAARG.getValue(1);
16727 // Load the next argument and return it
16728 return DAG.getLoad(ArgVT, dl,
16731 MachinePointerInfo(),
16732 false, false, false, 0);
16735 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16736 SelectionDAG &DAG) {
16737 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16738 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16739 SDValue Chain = Op.getOperand(0);
16740 SDValue DstPtr = Op.getOperand(1);
16741 SDValue SrcPtr = Op.getOperand(2);
16742 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16743 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16746 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16747 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16749 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16752 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16753 // amount is a constant. Takes immediate version of shift as input.
16754 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16755 SDValue SrcOp, uint64_t ShiftAmt,
16756 SelectionDAG &DAG) {
16757 MVT ElementType = VT.getVectorElementType();
16759 // Fold this packed shift into its first operand if ShiftAmt is 0.
16763 // Check for ShiftAmt >= element width
16764 if (ShiftAmt >= ElementType.getSizeInBits()) {
16765 if (Opc == X86ISD::VSRAI)
16766 ShiftAmt = ElementType.getSizeInBits() - 1;
16768 return DAG.getConstant(0, VT);
16771 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16772 && "Unknown target vector shift-by-constant node");
16774 // Fold this packed vector shift into a build vector if SrcOp is a
16775 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16776 if (VT == SrcOp.getSimpleValueType() &&
16777 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16778 SmallVector<SDValue, 8> Elts;
16779 unsigned NumElts = SrcOp->getNumOperands();
16780 ConstantSDNode *ND;
16783 default: llvm_unreachable(nullptr);
16784 case X86ISD::VSHLI:
16785 for (unsigned i=0; i!=NumElts; ++i) {
16786 SDValue CurrentOp = SrcOp->getOperand(i);
16787 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16788 Elts.push_back(CurrentOp);
16791 ND = cast<ConstantSDNode>(CurrentOp);
16792 const APInt &C = ND->getAPIntValue();
16793 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16796 case X86ISD::VSRLI:
16797 for (unsigned i=0; i!=NumElts; ++i) {
16798 SDValue CurrentOp = SrcOp->getOperand(i);
16799 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16800 Elts.push_back(CurrentOp);
16803 ND = cast<ConstantSDNode>(CurrentOp);
16804 const APInt &C = ND->getAPIntValue();
16805 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16808 case X86ISD::VSRAI:
16809 for (unsigned i=0; i!=NumElts; ++i) {
16810 SDValue CurrentOp = SrcOp->getOperand(i);
16811 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16812 Elts.push_back(CurrentOp);
16815 ND = cast<ConstantSDNode>(CurrentOp);
16816 const APInt &C = ND->getAPIntValue();
16817 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16822 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16825 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16828 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16829 // may or may not be a constant. Takes immediate version of shift as input.
16830 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16831 SDValue SrcOp, SDValue ShAmt,
16832 SelectionDAG &DAG) {
16833 MVT SVT = ShAmt.getSimpleValueType();
16834 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16836 // Catch shift-by-constant.
16837 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16838 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16839 CShAmt->getZExtValue(), DAG);
16841 // Change opcode to non-immediate version
16843 default: llvm_unreachable("Unknown target vector shift node");
16844 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16845 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16846 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16849 const X86Subtarget &Subtarget =
16850 DAG.getTarget().getSubtarget<X86Subtarget>();
16851 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16852 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16853 // Let the shuffle legalizer expand this shift amount node.
16854 SDValue Op0 = ShAmt.getOperand(0);
16855 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16856 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16858 // Need to build a vector containing shift amount.
16859 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16860 SmallVector<SDValue, 4> ShOps;
16861 ShOps.push_back(ShAmt);
16862 if (SVT == MVT::i32) {
16863 ShOps.push_back(DAG.getConstant(0, SVT));
16864 ShOps.push_back(DAG.getUNDEF(SVT));
16866 ShOps.push_back(DAG.getUNDEF(SVT));
16868 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16869 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16872 // The return type has to be a 128-bit type with the same element
16873 // type as the input type.
16874 MVT EltVT = VT.getVectorElementType();
16875 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16877 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16878 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16881 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16882 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16883 /// necessary casting for \p Mask when lowering masking intrinsics.
16884 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16885 SDValue PreservedSrc,
16886 const X86Subtarget *Subtarget,
16887 SelectionDAG &DAG) {
16888 EVT VT = Op.getValueType();
16889 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16890 MVT::i1, VT.getVectorNumElements());
16891 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16892 Mask.getValueType().getSizeInBits());
16895 assert(MaskVT.isSimple() && "invalid mask type");
16897 if (isAllOnes(Mask))
16900 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16901 // are extracted by EXTRACT_SUBVECTOR.
16902 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16903 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16904 DAG.getIntPtrConstant(0));
16906 switch (Op.getOpcode()) {
16908 case X86ISD::PCMPEQM:
16909 case X86ISD::PCMPGTM:
16911 case X86ISD::CMPMU:
16912 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16914 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16915 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16916 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16919 /// \brief Creates an SDNode for a predicated scalar operation.
16920 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16921 /// The mask is comming as MVT::i8 and it should be truncated
16922 /// to MVT::i1 while lowering masking intrinsics.
16923 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16924 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16925 /// a scalar instruction.
16926 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16927 SDValue PreservedSrc,
16928 const X86Subtarget *Subtarget,
16929 SelectionDAG &DAG) {
16930 if (isAllOnes(Mask))
16933 EVT VT = Op.getValueType();
16935 // The mask should be of type MVT::i1
16936 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16938 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16939 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16940 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16943 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16945 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16946 case Intrinsic::x86_fma_vfmadd_ps:
16947 case Intrinsic::x86_fma_vfmadd_pd:
16948 case Intrinsic::x86_fma_vfmadd_ps_256:
16949 case Intrinsic::x86_fma_vfmadd_pd_256:
16950 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16951 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16952 return X86ISD::FMADD;
16953 case Intrinsic::x86_fma_vfmsub_ps:
16954 case Intrinsic::x86_fma_vfmsub_pd:
16955 case Intrinsic::x86_fma_vfmsub_ps_256:
16956 case Intrinsic::x86_fma_vfmsub_pd_256:
16957 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16958 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16959 return X86ISD::FMSUB;
16960 case Intrinsic::x86_fma_vfnmadd_ps:
16961 case Intrinsic::x86_fma_vfnmadd_pd:
16962 case Intrinsic::x86_fma_vfnmadd_ps_256:
16963 case Intrinsic::x86_fma_vfnmadd_pd_256:
16964 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16965 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16966 return X86ISD::FNMADD;
16967 case Intrinsic::x86_fma_vfnmsub_ps:
16968 case Intrinsic::x86_fma_vfnmsub_pd:
16969 case Intrinsic::x86_fma_vfnmsub_ps_256:
16970 case Intrinsic::x86_fma_vfnmsub_pd_256:
16971 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16972 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16973 return X86ISD::FNMSUB;
16974 case Intrinsic::x86_fma_vfmaddsub_ps:
16975 case Intrinsic::x86_fma_vfmaddsub_pd:
16976 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16977 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16978 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16979 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16980 return X86ISD::FMADDSUB;
16981 case Intrinsic::x86_fma_vfmsubadd_ps:
16982 case Intrinsic::x86_fma_vfmsubadd_pd:
16983 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16984 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16985 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16986 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16987 return X86ISD::FMSUBADD;
16991 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16992 SelectionDAG &DAG) {
16994 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16995 EVT VT = Op.getValueType();
16996 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16998 switch(IntrData->Type) {
16999 case INTR_TYPE_1OP:
17000 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
17001 case INTR_TYPE_2OP:
17002 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
17004 case INTR_TYPE_3OP:
17005 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
17006 Op.getOperand(2), Op.getOperand(3));
17007 case INTR_TYPE_1OP_MASK_RM: {
17008 SDValue Src = Op.getOperand(1);
17009 SDValue Src0 = Op.getOperand(2);
17010 SDValue Mask = Op.getOperand(3);
17011 SDValue RoundingMode = Op.getOperand(4);
17012 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
17014 Mask, Src0, Subtarget, DAG);
17016 case INTR_TYPE_SCALAR_MASK_RM: {
17017 SDValue Src1 = Op.getOperand(1);
17018 SDValue Src2 = Op.getOperand(2);
17019 SDValue Src0 = Op.getOperand(3);
17020 SDValue Mask = Op.getOperand(4);
17021 SDValue RoundingMode = Op.getOperand(5);
17022 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
17024 Mask, Src0, Subtarget, DAG);
17026 case INTR_TYPE_2OP_MASK: {
17027 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
17029 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
17032 case CMP_MASK_CC: {
17033 // Comparison intrinsics with masks.
17034 // Example of transformation:
17035 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
17036 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
17038 // (v8i1 (insert_subvector undef,
17039 // (v2i1 (and (PCMPEQM %a, %b),
17040 // (extract_subvector
17041 // (v8i1 (bitcast %mask)), 0))), 0))))
17042 EVT VT = Op.getOperand(1).getValueType();
17043 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17044 VT.getVectorNumElements());
17045 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
17046 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17047 Mask.getValueType().getSizeInBits());
17049 if (IntrData->Type == CMP_MASK_CC) {
17050 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
17051 Op.getOperand(2), Op.getOperand(3));
17053 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
17054 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
17057 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
17058 DAG.getTargetConstant(0, MaskVT),
17060 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
17061 DAG.getUNDEF(BitcastVT), CmpMask,
17062 DAG.getIntPtrConstant(0));
17063 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
17065 case COMI: { // Comparison intrinsics
17066 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
17067 SDValue LHS = Op.getOperand(1);
17068 SDValue RHS = Op.getOperand(2);
17069 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
17070 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
17071 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
17072 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17073 DAG.getConstant(X86CC, MVT::i8), Cond);
17074 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17077 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
17078 Op.getOperand(1), Op.getOperand(2), DAG);
17080 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17081 Op.getSimpleValueType(),
17083 Op.getOperand(2), DAG),
17084 Op.getOperand(4), Op.getOperand(3), Subtarget,
17086 case COMPRESS_EXPAND_IN_REG: {
17087 SDValue Mask = Op.getOperand(3);
17088 SDValue DataToCompress = Op.getOperand(1);
17089 SDValue PassThru = Op.getOperand(2);
17090 if (isAllOnes(Mask)) // return data as is
17091 return Op.getOperand(1);
17092 EVT VT = Op.getValueType();
17093 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17094 VT.getVectorNumElements());
17095 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17096 Mask.getValueType().getSizeInBits());
17098 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17099 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17100 DAG.getIntPtrConstant(0));
17102 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17106 SDValue Mask = Op.getOperand(3);
17107 EVT VT = Op.getValueType();
17108 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17109 VT.getVectorNumElements());
17110 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17111 Mask.getValueType().getSizeInBits());
17113 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17114 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17115 DAG.getIntPtrConstant(0));
17116 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17121 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17122 dl, Op.getValueType(),
17126 Op.getOperand(4), Op.getOperand(1),
17135 default: return SDValue(); // Don't custom lower most intrinsics.
17137 case Intrinsic::x86_avx512_mask_valign_q_512:
17138 case Intrinsic::x86_avx512_mask_valign_d_512:
17139 // Vector source operands are swapped.
17140 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17141 Op.getValueType(), Op.getOperand(2),
17144 Op.getOperand(5), Op.getOperand(4),
17147 // ptest and testp intrinsics. The intrinsic these come from are designed to
17148 // return an integer value, not just an instruction so lower it to the ptest
17149 // or testp pattern and a setcc for the result.
17150 case Intrinsic::x86_sse41_ptestz:
17151 case Intrinsic::x86_sse41_ptestc:
17152 case Intrinsic::x86_sse41_ptestnzc:
17153 case Intrinsic::x86_avx_ptestz_256:
17154 case Intrinsic::x86_avx_ptestc_256:
17155 case Intrinsic::x86_avx_ptestnzc_256:
17156 case Intrinsic::x86_avx_vtestz_ps:
17157 case Intrinsic::x86_avx_vtestc_ps:
17158 case Intrinsic::x86_avx_vtestnzc_ps:
17159 case Intrinsic::x86_avx_vtestz_pd:
17160 case Intrinsic::x86_avx_vtestc_pd:
17161 case Intrinsic::x86_avx_vtestnzc_pd:
17162 case Intrinsic::x86_avx_vtestz_ps_256:
17163 case Intrinsic::x86_avx_vtestc_ps_256:
17164 case Intrinsic::x86_avx_vtestnzc_ps_256:
17165 case Intrinsic::x86_avx_vtestz_pd_256:
17166 case Intrinsic::x86_avx_vtestc_pd_256:
17167 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17168 bool IsTestPacked = false;
17171 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17172 case Intrinsic::x86_avx_vtestz_ps:
17173 case Intrinsic::x86_avx_vtestz_pd:
17174 case Intrinsic::x86_avx_vtestz_ps_256:
17175 case Intrinsic::x86_avx_vtestz_pd_256:
17176 IsTestPacked = true; // Fallthrough
17177 case Intrinsic::x86_sse41_ptestz:
17178 case Intrinsic::x86_avx_ptestz_256:
17180 X86CC = X86::COND_E;
17182 case Intrinsic::x86_avx_vtestc_ps:
17183 case Intrinsic::x86_avx_vtestc_pd:
17184 case Intrinsic::x86_avx_vtestc_ps_256:
17185 case Intrinsic::x86_avx_vtestc_pd_256:
17186 IsTestPacked = true; // Fallthrough
17187 case Intrinsic::x86_sse41_ptestc:
17188 case Intrinsic::x86_avx_ptestc_256:
17190 X86CC = X86::COND_B;
17192 case Intrinsic::x86_avx_vtestnzc_ps:
17193 case Intrinsic::x86_avx_vtestnzc_pd:
17194 case Intrinsic::x86_avx_vtestnzc_ps_256:
17195 case Intrinsic::x86_avx_vtestnzc_pd_256:
17196 IsTestPacked = true; // Fallthrough
17197 case Intrinsic::x86_sse41_ptestnzc:
17198 case Intrinsic::x86_avx_ptestnzc_256:
17200 X86CC = X86::COND_A;
17204 SDValue LHS = Op.getOperand(1);
17205 SDValue RHS = Op.getOperand(2);
17206 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17207 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17208 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17209 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17210 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17212 case Intrinsic::x86_avx512_kortestz_w:
17213 case Intrinsic::x86_avx512_kortestc_w: {
17214 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17215 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17216 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17217 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17218 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17219 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17220 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17223 case Intrinsic::x86_sse42_pcmpistria128:
17224 case Intrinsic::x86_sse42_pcmpestria128:
17225 case Intrinsic::x86_sse42_pcmpistric128:
17226 case Intrinsic::x86_sse42_pcmpestric128:
17227 case Intrinsic::x86_sse42_pcmpistrio128:
17228 case Intrinsic::x86_sse42_pcmpestrio128:
17229 case Intrinsic::x86_sse42_pcmpistris128:
17230 case Intrinsic::x86_sse42_pcmpestris128:
17231 case Intrinsic::x86_sse42_pcmpistriz128:
17232 case Intrinsic::x86_sse42_pcmpestriz128: {
17236 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17237 case Intrinsic::x86_sse42_pcmpistria128:
17238 Opcode = X86ISD::PCMPISTRI;
17239 X86CC = X86::COND_A;
17241 case Intrinsic::x86_sse42_pcmpestria128:
17242 Opcode = X86ISD::PCMPESTRI;
17243 X86CC = X86::COND_A;
17245 case Intrinsic::x86_sse42_pcmpistric128:
17246 Opcode = X86ISD::PCMPISTRI;
17247 X86CC = X86::COND_B;
17249 case Intrinsic::x86_sse42_pcmpestric128:
17250 Opcode = X86ISD::PCMPESTRI;
17251 X86CC = X86::COND_B;
17253 case Intrinsic::x86_sse42_pcmpistrio128:
17254 Opcode = X86ISD::PCMPISTRI;
17255 X86CC = X86::COND_O;
17257 case Intrinsic::x86_sse42_pcmpestrio128:
17258 Opcode = X86ISD::PCMPESTRI;
17259 X86CC = X86::COND_O;
17261 case Intrinsic::x86_sse42_pcmpistris128:
17262 Opcode = X86ISD::PCMPISTRI;
17263 X86CC = X86::COND_S;
17265 case Intrinsic::x86_sse42_pcmpestris128:
17266 Opcode = X86ISD::PCMPESTRI;
17267 X86CC = X86::COND_S;
17269 case Intrinsic::x86_sse42_pcmpistriz128:
17270 Opcode = X86ISD::PCMPISTRI;
17271 X86CC = X86::COND_E;
17273 case Intrinsic::x86_sse42_pcmpestriz128:
17274 Opcode = X86ISD::PCMPESTRI;
17275 X86CC = X86::COND_E;
17278 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17279 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17280 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17281 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17282 DAG.getConstant(X86CC, MVT::i8),
17283 SDValue(PCMP.getNode(), 1));
17284 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17287 case Intrinsic::x86_sse42_pcmpistri128:
17288 case Intrinsic::x86_sse42_pcmpestri128: {
17290 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17291 Opcode = X86ISD::PCMPISTRI;
17293 Opcode = X86ISD::PCMPESTRI;
17295 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17296 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17297 return DAG.getNode(Opcode, dl, VTs, NewOps);
17300 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17301 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17302 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17303 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17304 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17305 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17306 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17307 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17308 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17309 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17310 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17311 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17312 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17313 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17314 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17315 dl, Op.getValueType(),
17319 Op.getOperand(4), Op.getOperand(1),
17325 case Intrinsic::x86_fma_vfmadd_ps:
17326 case Intrinsic::x86_fma_vfmadd_pd:
17327 case Intrinsic::x86_fma_vfmsub_ps:
17328 case Intrinsic::x86_fma_vfmsub_pd:
17329 case Intrinsic::x86_fma_vfnmadd_ps:
17330 case Intrinsic::x86_fma_vfnmadd_pd:
17331 case Intrinsic::x86_fma_vfnmsub_ps:
17332 case Intrinsic::x86_fma_vfnmsub_pd:
17333 case Intrinsic::x86_fma_vfmaddsub_ps:
17334 case Intrinsic::x86_fma_vfmaddsub_pd:
17335 case Intrinsic::x86_fma_vfmsubadd_ps:
17336 case Intrinsic::x86_fma_vfmsubadd_pd:
17337 case Intrinsic::x86_fma_vfmadd_ps_256:
17338 case Intrinsic::x86_fma_vfmadd_pd_256:
17339 case Intrinsic::x86_fma_vfmsub_ps_256:
17340 case Intrinsic::x86_fma_vfmsub_pd_256:
17341 case Intrinsic::x86_fma_vfnmadd_ps_256:
17342 case Intrinsic::x86_fma_vfnmadd_pd_256:
17343 case Intrinsic::x86_fma_vfnmsub_ps_256:
17344 case Intrinsic::x86_fma_vfnmsub_pd_256:
17345 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17346 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17347 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17348 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17349 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17350 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17354 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17355 SDValue Src, SDValue Mask, SDValue Base,
17356 SDValue Index, SDValue ScaleOp, SDValue Chain,
17357 const X86Subtarget * Subtarget) {
17359 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17360 assert(C && "Invalid scale type");
17361 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17362 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17363 Index.getSimpleValueType().getVectorNumElements());
17365 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17367 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17369 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17370 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17371 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17372 SDValue Segment = DAG.getRegister(0, MVT::i32);
17373 if (Src.getOpcode() == ISD::UNDEF)
17374 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17375 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17376 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17377 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17378 return DAG.getMergeValues(RetOps, dl);
17381 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17382 SDValue Src, SDValue Mask, SDValue Base,
17383 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17385 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17386 assert(C && "Invalid scale type");
17387 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17388 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17389 SDValue Segment = DAG.getRegister(0, MVT::i32);
17390 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17391 Index.getSimpleValueType().getVectorNumElements());
17393 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17395 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17397 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17398 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17399 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17400 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17401 return SDValue(Res, 1);
17404 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17405 SDValue Mask, SDValue Base, SDValue Index,
17406 SDValue ScaleOp, SDValue Chain) {
17408 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17409 assert(C && "Invalid scale type");
17410 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17411 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17412 SDValue Segment = DAG.getRegister(0, MVT::i32);
17414 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17416 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17418 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17420 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17421 //SDVTList VTs = DAG.getVTList(MVT::Other);
17422 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17423 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17424 return SDValue(Res, 0);
17427 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17428 // read performance monitor counters (x86_rdpmc).
17429 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17430 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17431 SmallVectorImpl<SDValue> &Results) {
17432 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17433 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17436 // The ECX register is used to select the index of the performance counter
17438 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17440 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17442 // Reads the content of a 64-bit performance counter and returns it in the
17443 // registers EDX:EAX.
17444 if (Subtarget->is64Bit()) {
17445 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17446 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17449 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17450 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17453 Chain = HI.getValue(1);
17455 if (Subtarget->is64Bit()) {
17456 // The EAX register is loaded with the low-order 32 bits. The EDX register
17457 // is loaded with the supported high-order bits of the counter.
17458 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17459 DAG.getConstant(32, MVT::i8));
17460 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17461 Results.push_back(Chain);
17465 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17466 SDValue Ops[] = { LO, HI };
17467 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17468 Results.push_back(Pair);
17469 Results.push_back(Chain);
17472 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17473 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17474 // also used to custom lower READCYCLECOUNTER nodes.
17475 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17476 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17477 SmallVectorImpl<SDValue> &Results) {
17478 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17479 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17482 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17483 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17484 // and the EAX register is loaded with the low-order 32 bits.
17485 if (Subtarget->is64Bit()) {
17486 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17487 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17490 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17491 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17494 SDValue Chain = HI.getValue(1);
17496 if (Opcode == X86ISD::RDTSCP_DAG) {
17497 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17499 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17500 // the ECX register. Add 'ecx' explicitly to the chain.
17501 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17503 // Explicitly store the content of ECX at the location passed in input
17504 // to the 'rdtscp' intrinsic.
17505 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17506 MachinePointerInfo(), false, false, 0);
17509 if (Subtarget->is64Bit()) {
17510 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17511 // the EAX register is loaded with the low-order 32 bits.
17512 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17513 DAG.getConstant(32, MVT::i8));
17514 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17515 Results.push_back(Chain);
17519 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17520 SDValue Ops[] = { LO, HI };
17521 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17522 Results.push_back(Pair);
17523 Results.push_back(Chain);
17526 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17527 SelectionDAG &DAG) {
17528 SmallVector<SDValue, 2> Results;
17530 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17532 return DAG.getMergeValues(Results, DL);
17536 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17537 SelectionDAG &DAG) {
17538 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17540 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17545 switch(IntrData->Type) {
17547 llvm_unreachable("Unknown Intrinsic Type");
17551 // Emit the node with the right value type.
17552 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17553 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17555 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17556 // Otherwise return the value from Rand, which is always 0, casted to i32.
17557 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17558 DAG.getConstant(1, Op->getValueType(1)),
17559 DAG.getConstant(X86::COND_B, MVT::i32),
17560 SDValue(Result.getNode(), 1) };
17561 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17562 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17565 // Return { result, isValid, chain }.
17566 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17567 SDValue(Result.getNode(), 2));
17570 //gather(v1, mask, index, base, scale);
17571 SDValue Chain = Op.getOperand(0);
17572 SDValue Src = Op.getOperand(2);
17573 SDValue Base = Op.getOperand(3);
17574 SDValue Index = Op.getOperand(4);
17575 SDValue Mask = Op.getOperand(5);
17576 SDValue Scale = Op.getOperand(6);
17577 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17581 //scatter(base, mask, index, v1, scale);
17582 SDValue Chain = Op.getOperand(0);
17583 SDValue Base = Op.getOperand(2);
17584 SDValue Mask = Op.getOperand(3);
17585 SDValue Index = Op.getOperand(4);
17586 SDValue Src = Op.getOperand(5);
17587 SDValue Scale = Op.getOperand(6);
17588 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17591 SDValue Hint = Op.getOperand(6);
17593 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17594 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17595 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17596 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17597 SDValue Chain = Op.getOperand(0);
17598 SDValue Mask = Op.getOperand(2);
17599 SDValue Index = Op.getOperand(3);
17600 SDValue Base = Op.getOperand(4);
17601 SDValue Scale = Op.getOperand(5);
17602 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17604 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17606 SmallVector<SDValue, 2> Results;
17607 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17608 return DAG.getMergeValues(Results, dl);
17610 // Read Performance Monitoring Counters.
17612 SmallVector<SDValue, 2> Results;
17613 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17614 return DAG.getMergeValues(Results, dl);
17616 // XTEST intrinsics.
17618 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17619 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17620 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17621 DAG.getConstant(X86::COND_NE, MVT::i8),
17623 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17624 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17625 Ret, SDValue(InTrans.getNode(), 1));
17629 SmallVector<SDValue, 2> Results;
17630 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17631 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17632 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17633 DAG.getConstant(-1, MVT::i8));
17634 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17635 Op.getOperand(4), GenCF.getValue(1));
17636 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17637 Op.getOperand(5), MachinePointerInfo(),
17639 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17640 DAG.getConstant(X86::COND_B, MVT::i8),
17642 Results.push_back(SetCC);
17643 Results.push_back(Store);
17644 return DAG.getMergeValues(Results, dl);
17646 case COMPRESS_TO_MEM: {
17648 SDValue Mask = Op.getOperand(4);
17649 SDValue DataToCompress = Op.getOperand(3);
17650 SDValue Addr = Op.getOperand(2);
17651 SDValue Chain = Op.getOperand(0);
17653 if (isAllOnes(Mask)) // return just a store
17654 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17655 MachinePointerInfo(), false, false, 0);
17657 EVT VT = DataToCompress.getValueType();
17658 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17659 VT.getVectorNumElements());
17660 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17661 Mask.getValueType().getSizeInBits());
17662 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17663 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17664 DAG.getIntPtrConstant(0));
17666 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17667 DataToCompress, DAG.getUNDEF(VT));
17668 return DAG.getStore(Chain, dl, Compressed, Addr,
17669 MachinePointerInfo(), false, false, 0);
17671 case EXPAND_FROM_MEM: {
17673 SDValue Mask = Op.getOperand(4);
17674 SDValue PathThru = Op.getOperand(3);
17675 SDValue Addr = Op.getOperand(2);
17676 SDValue Chain = Op.getOperand(0);
17677 EVT VT = Op.getValueType();
17679 if (isAllOnes(Mask)) // return just a load
17680 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17682 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17683 VT.getVectorNumElements());
17684 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17685 Mask.getValueType().getSizeInBits());
17686 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17687 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17688 DAG.getIntPtrConstant(0));
17690 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17691 false, false, false, 0);
17693 SmallVector<SDValue, 2> Results;
17694 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17696 Results.push_back(Chain);
17697 return DAG.getMergeValues(Results, dl);
17702 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17703 SelectionDAG &DAG) const {
17704 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17705 MFI->setReturnAddressIsTaken(true);
17707 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17710 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17712 EVT PtrVT = getPointerTy();
17715 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17716 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17717 DAG.getSubtarget().getRegisterInfo());
17718 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17719 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17720 DAG.getNode(ISD::ADD, dl, PtrVT,
17721 FrameAddr, Offset),
17722 MachinePointerInfo(), false, false, false, 0);
17725 // Just load the return address.
17726 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17727 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17728 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17731 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17732 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17733 MFI->setFrameAddressIsTaken(true);
17735 EVT VT = Op.getValueType();
17736 SDLoc dl(Op); // FIXME probably not meaningful
17737 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17738 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17739 DAG.getSubtarget().getRegisterInfo());
17740 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17741 DAG.getMachineFunction());
17742 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17743 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17744 "Invalid Frame Register!");
17745 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17747 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17748 MachinePointerInfo(),
17749 false, false, false, 0);
17753 // FIXME? Maybe this could be a TableGen attribute on some registers and
17754 // this table could be generated automatically from RegInfo.
17755 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17757 unsigned Reg = StringSwitch<unsigned>(RegName)
17758 .Case("esp", X86::ESP)
17759 .Case("rsp", X86::RSP)
17763 report_fatal_error("Invalid register name global variable");
17766 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17767 SelectionDAG &DAG) const {
17768 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17769 DAG.getSubtarget().getRegisterInfo());
17770 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17773 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17774 SDValue Chain = Op.getOperand(0);
17775 SDValue Offset = Op.getOperand(1);
17776 SDValue Handler = Op.getOperand(2);
17779 EVT PtrVT = getPointerTy();
17780 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17781 DAG.getSubtarget().getRegisterInfo());
17782 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17783 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17784 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17785 "Invalid Frame Register!");
17786 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17787 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17789 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17790 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17791 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17792 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17794 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17796 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17797 DAG.getRegister(StoreAddrReg, PtrVT));
17800 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17801 SelectionDAG &DAG) const {
17803 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17804 DAG.getVTList(MVT::i32, MVT::Other),
17805 Op.getOperand(0), Op.getOperand(1));
17808 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17809 SelectionDAG &DAG) const {
17811 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17812 Op.getOperand(0), Op.getOperand(1));
17815 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17816 return Op.getOperand(0);
17819 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17820 SelectionDAG &DAG) const {
17821 SDValue Root = Op.getOperand(0);
17822 SDValue Trmp = Op.getOperand(1); // trampoline
17823 SDValue FPtr = Op.getOperand(2); // nested function
17824 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17827 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17828 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17830 if (Subtarget->is64Bit()) {
17831 SDValue OutChains[6];
17833 // Large code-model.
17834 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17835 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17837 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17838 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17840 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17842 // Load the pointer to the nested function into R11.
17843 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17844 SDValue Addr = Trmp;
17845 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17846 Addr, MachinePointerInfo(TrmpAddr),
17849 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17850 DAG.getConstant(2, MVT::i64));
17851 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17852 MachinePointerInfo(TrmpAddr, 2),
17855 // Load the 'nest' parameter value into R10.
17856 // R10 is specified in X86CallingConv.td
17857 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17858 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17859 DAG.getConstant(10, MVT::i64));
17860 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17861 Addr, MachinePointerInfo(TrmpAddr, 10),
17864 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17865 DAG.getConstant(12, MVT::i64));
17866 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17867 MachinePointerInfo(TrmpAddr, 12),
17870 // Jump to the nested function.
17871 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17872 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17873 DAG.getConstant(20, MVT::i64));
17874 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17875 Addr, MachinePointerInfo(TrmpAddr, 20),
17878 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17879 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17880 DAG.getConstant(22, MVT::i64));
17881 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17882 MachinePointerInfo(TrmpAddr, 22),
17885 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17887 const Function *Func =
17888 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17889 CallingConv::ID CC = Func->getCallingConv();
17894 llvm_unreachable("Unsupported calling convention");
17895 case CallingConv::C:
17896 case CallingConv::X86_StdCall: {
17897 // Pass 'nest' parameter in ECX.
17898 // Must be kept in sync with X86CallingConv.td
17899 NestReg = X86::ECX;
17901 // Check that ECX wasn't needed by an 'inreg' parameter.
17902 FunctionType *FTy = Func->getFunctionType();
17903 const AttributeSet &Attrs = Func->getAttributes();
17905 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17906 unsigned InRegCount = 0;
17909 for (FunctionType::param_iterator I = FTy->param_begin(),
17910 E = FTy->param_end(); I != E; ++I, ++Idx)
17911 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17912 // FIXME: should only count parameters that are lowered to integers.
17913 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17915 if (InRegCount > 2) {
17916 report_fatal_error("Nest register in use - reduce number of inreg"
17922 case CallingConv::X86_FastCall:
17923 case CallingConv::X86_ThisCall:
17924 case CallingConv::Fast:
17925 // Pass 'nest' parameter in EAX.
17926 // Must be kept in sync with X86CallingConv.td
17927 NestReg = X86::EAX;
17931 SDValue OutChains[4];
17932 SDValue Addr, Disp;
17934 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17935 DAG.getConstant(10, MVT::i32));
17936 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17938 // This is storing the opcode for MOV32ri.
17939 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17940 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17941 OutChains[0] = DAG.getStore(Root, dl,
17942 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17943 Trmp, MachinePointerInfo(TrmpAddr),
17946 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17947 DAG.getConstant(1, MVT::i32));
17948 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17949 MachinePointerInfo(TrmpAddr, 1),
17952 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17953 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17954 DAG.getConstant(5, MVT::i32));
17955 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17956 MachinePointerInfo(TrmpAddr, 5),
17959 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17960 DAG.getConstant(6, MVT::i32));
17961 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17962 MachinePointerInfo(TrmpAddr, 6),
17965 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17969 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17970 SelectionDAG &DAG) const {
17972 The rounding mode is in bits 11:10 of FPSR, and has the following
17974 00 Round to nearest
17979 FLT_ROUNDS, on the other hand, expects the following:
17986 To perform the conversion, we do:
17987 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17990 MachineFunction &MF = DAG.getMachineFunction();
17991 const TargetMachine &TM = MF.getTarget();
17992 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17993 unsigned StackAlignment = TFI.getStackAlignment();
17994 MVT VT = Op.getSimpleValueType();
17997 // Save FP Control Word to stack slot
17998 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17999 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
18001 MachineMemOperand *MMO =
18002 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
18003 MachineMemOperand::MOStore, 2, 2);
18005 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
18006 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
18007 DAG.getVTList(MVT::Other),
18008 Ops, MVT::i16, MMO);
18010 // Load FP Control Word from stack slot
18011 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
18012 MachinePointerInfo(), false, false, false, 0);
18014 // Transform as necessary
18016 DAG.getNode(ISD::SRL, DL, MVT::i16,
18017 DAG.getNode(ISD::AND, DL, MVT::i16,
18018 CWD, DAG.getConstant(0x800, MVT::i16)),
18019 DAG.getConstant(11, MVT::i8));
18021 DAG.getNode(ISD::SRL, DL, MVT::i16,
18022 DAG.getNode(ISD::AND, DL, MVT::i16,
18023 CWD, DAG.getConstant(0x400, MVT::i16)),
18024 DAG.getConstant(9, MVT::i8));
18027 DAG.getNode(ISD::AND, DL, MVT::i16,
18028 DAG.getNode(ISD::ADD, DL, MVT::i16,
18029 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
18030 DAG.getConstant(1, MVT::i16)),
18031 DAG.getConstant(3, MVT::i16));
18033 return DAG.getNode((VT.getSizeInBits() < 16 ?
18034 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
18037 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
18038 MVT VT = Op.getSimpleValueType();
18040 unsigned NumBits = VT.getSizeInBits();
18043 Op = Op.getOperand(0);
18044 if (VT == MVT::i8) {
18045 // Zero extend to i32 since there is not an i8 bsr.
18047 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18050 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
18051 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18052 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18054 // If src is zero (i.e. bsr sets ZF), returns NumBits.
18057 DAG.getConstant(NumBits+NumBits-1, OpVT),
18058 DAG.getConstant(X86::COND_E, MVT::i8),
18061 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18063 // Finally xor with NumBits-1.
18064 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18067 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18071 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
18072 MVT VT = Op.getSimpleValueType();
18074 unsigned NumBits = VT.getSizeInBits();
18077 Op = Op.getOperand(0);
18078 if (VT == MVT::i8) {
18079 // Zero extend to i32 since there is not an i8 bsr.
18081 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18084 // Issue a bsr (scan bits in reverse).
18085 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18086 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18088 // And xor with NumBits-1.
18089 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18092 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18096 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18097 MVT VT = Op.getSimpleValueType();
18098 unsigned NumBits = VT.getSizeInBits();
18100 Op = Op.getOperand(0);
18102 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18103 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18104 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18106 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18109 DAG.getConstant(NumBits, VT),
18110 DAG.getConstant(X86::COND_E, MVT::i8),
18113 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18116 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18117 // ones, and then concatenate the result back.
18118 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18119 MVT VT = Op.getSimpleValueType();
18121 assert(VT.is256BitVector() && VT.isInteger() &&
18122 "Unsupported value type for operation");
18124 unsigned NumElems = VT.getVectorNumElements();
18127 // Extract the LHS vectors
18128 SDValue LHS = Op.getOperand(0);
18129 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18130 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18132 // Extract the RHS vectors
18133 SDValue RHS = Op.getOperand(1);
18134 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18135 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18137 MVT EltVT = VT.getVectorElementType();
18138 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18140 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18141 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18142 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18145 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18146 assert(Op.getSimpleValueType().is256BitVector() &&
18147 Op.getSimpleValueType().isInteger() &&
18148 "Only handle AVX 256-bit vector integer operation");
18149 return Lower256IntArith(Op, DAG);
18152 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18153 assert(Op.getSimpleValueType().is256BitVector() &&
18154 Op.getSimpleValueType().isInteger() &&
18155 "Only handle AVX 256-bit vector integer operation");
18156 return Lower256IntArith(Op, DAG);
18159 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18160 SelectionDAG &DAG) {
18162 MVT VT = Op.getSimpleValueType();
18164 // Decompose 256-bit ops into smaller 128-bit ops.
18165 if (VT.is256BitVector() && !Subtarget->hasInt256())
18166 return Lower256IntArith(Op, DAG);
18168 SDValue A = Op.getOperand(0);
18169 SDValue B = Op.getOperand(1);
18171 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18172 if (VT == MVT::v4i32) {
18173 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18174 "Should not custom lower when pmuldq is available!");
18176 // Extract the odd parts.
18177 static const int UnpackMask[] = { 1, -1, 3, -1 };
18178 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18179 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18181 // Multiply the even parts.
18182 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18183 // Now multiply odd parts.
18184 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18186 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18187 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18189 // Merge the two vectors back together with a shuffle. This expands into 2
18191 static const int ShufMask[] = { 0, 4, 2, 6 };
18192 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18195 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18196 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18198 // Ahi = psrlqi(a, 32);
18199 // Bhi = psrlqi(b, 32);
18201 // AloBlo = pmuludq(a, b);
18202 // AloBhi = pmuludq(a, Bhi);
18203 // AhiBlo = pmuludq(Ahi, b);
18205 // AloBhi = psllqi(AloBhi, 32);
18206 // AhiBlo = psllqi(AhiBlo, 32);
18207 // return AloBlo + AloBhi + AhiBlo;
18209 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18210 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18212 // Bit cast to 32-bit vectors for MULUDQ
18213 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18214 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18215 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18216 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18217 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18218 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18220 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18221 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18222 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18224 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18225 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18227 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18228 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18231 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18232 assert(Subtarget->isTargetWin64() && "Unexpected target");
18233 EVT VT = Op.getValueType();
18234 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18235 "Unexpected return type for lowering");
18239 switch (Op->getOpcode()) {
18240 default: llvm_unreachable("Unexpected request for libcall!");
18241 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18242 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18243 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18244 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18245 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18246 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18250 SDValue InChain = DAG.getEntryNode();
18252 TargetLowering::ArgListTy Args;
18253 TargetLowering::ArgListEntry Entry;
18254 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18255 EVT ArgVT = Op->getOperand(i).getValueType();
18256 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18257 "Unexpected argument type for lowering");
18258 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18259 Entry.Node = StackPtr;
18260 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18262 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18263 Entry.Ty = PointerType::get(ArgTy,0);
18264 Entry.isSExt = false;
18265 Entry.isZExt = false;
18266 Args.push_back(Entry);
18269 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18272 TargetLowering::CallLoweringInfo CLI(DAG);
18273 CLI.setDebugLoc(dl).setChain(InChain)
18274 .setCallee(getLibcallCallingConv(LC),
18275 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18276 Callee, std::move(Args), 0)
18277 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18279 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18280 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18283 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18284 SelectionDAG &DAG) {
18285 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18286 EVT VT = Op0.getValueType();
18289 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18290 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18292 // PMULxD operations multiply each even value (starting at 0) of LHS with
18293 // the related value of RHS and produce a widen result.
18294 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18295 // => <2 x i64> <ae|cg>
18297 // In other word, to have all the results, we need to perform two PMULxD:
18298 // 1. one with the even values.
18299 // 2. one with the odd values.
18300 // To achieve #2, with need to place the odd values at an even position.
18302 // Place the odd value at an even position (basically, shift all values 1
18303 // step to the left):
18304 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18305 // <a|b|c|d> => <b|undef|d|undef>
18306 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18307 // <e|f|g|h> => <f|undef|h|undef>
18308 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18310 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18312 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18313 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18315 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18316 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18317 // => <2 x i64> <ae|cg>
18318 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18319 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18320 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18321 // => <2 x i64> <bf|dh>
18322 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18323 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18325 // Shuffle it back into the right order.
18326 SDValue Highs, Lows;
18327 if (VT == MVT::v8i32) {
18328 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18329 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18330 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18331 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18333 const int HighMask[] = {1, 5, 3, 7};
18334 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18335 const int LowMask[] = {0, 4, 2, 6};
18336 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18339 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18340 // unsigned multiply.
18341 if (IsSigned && !Subtarget->hasSSE41()) {
18343 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18344 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18345 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18346 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18347 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18349 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18350 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18353 // The first result of MUL_LOHI is actually the low value, followed by the
18355 SDValue Ops[] = {Lows, Highs};
18356 return DAG.getMergeValues(Ops, dl);
18359 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18360 const X86Subtarget *Subtarget) {
18361 MVT VT = Op.getSimpleValueType();
18363 SDValue R = Op.getOperand(0);
18364 SDValue Amt = Op.getOperand(1);
18366 // Optimize shl/srl/sra with constant shift amount.
18367 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18368 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18369 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18371 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18372 (Subtarget->hasInt256() &&
18373 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18374 (Subtarget->hasAVX512() &&
18375 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18376 if (Op.getOpcode() == ISD::SHL)
18377 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18379 if (Op.getOpcode() == ISD::SRL)
18380 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18382 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18383 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18387 if (VT == MVT::v16i8) {
18388 if (Op.getOpcode() == ISD::SHL) {
18389 // Make a large shift.
18390 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18391 MVT::v8i16, R, ShiftAmt,
18393 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18394 // Zero out the rightmost bits.
18395 SmallVector<SDValue, 16> V(16,
18396 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18398 return DAG.getNode(ISD::AND, dl, VT, SHL,
18399 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18401 if (Op.getOpcode() == ISD::SRL) {
18402 // Make a large shift.
18403 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18404 MVT::v8i16, R, ShiftAmt,
18406 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18407 // Zero out the leftmost bits.
18408 SmallVector<SDValue, 16> V(16,
18409 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18411 return DAG.getNode(ISD::AND, dl, VT, SRL,
18412 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18414 if (Op.getOpcode() == ISD::SRA) {
18415 if (ShiftAmt == 7) {
18416 // R s>> 7 === R s< 0
18417 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18418 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18421 // R s>> a === ((R u>> a) ^ m) - m
18422 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18423 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18425 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18426 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18427 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18430 llvm_unreachable("Unknown shift opcode.");
18433 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18434 if (Op.getOpcode() == ISD::SHL) {
18435 // Make a large shift.
18436 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18437 MVT::v16i16, R, ShiftAmt,
18439 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18440 // Zero out the rightmost bits.
18441 SmallVector<SDValue, 32> V(32,
18442 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18444 return DAG.getNode(ISD::AND, dl, VT, SHL,
18445 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18447 if (Op.getOpcode() == ISD::SRL) {
18448 // Make a large shift.
18449 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18450 MVT::v16i16, R, ShiftAmt,
18452 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18453 // Zero out the leftmost bits.
18454 SmallVector<SDValue, 32> V(32,
18455 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18457 return DAG.getNode(ISD::AND, dl, VT, SRL,
18458 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18460 if (Op.getOpcode() == ISD::SRA) {
18461 if (ShiftAmt == 7) {
18462 // R s>> 7 === R s< 0
18463 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18464 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18467 // R s>> a === ((R u>> a) ^ m) - m
18468 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18469 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18471 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18472 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18473 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18476 llvm_unreachable("Unknown shift opcode.");
18481 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18482 if (!Subtarget->is64Bit() &&
18483 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18484 Amt.getOpcode() == ISD::BITCAST &&
18485 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18486 Amt = Amt.getOperand(0);
18487 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18488 VT.getVectorNumElements();
18489 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18490 uint64_t ShiftAmt = 0;
18491 for (unsigned i = 0; i != Ratio; ++i) {
18492 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18496 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18498 // Check remaining shift amounts.
18499 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18500 uint64_t ShAmt = 0;
18501 for (unsigned j = 0; j != Ratio; ++j) {
18502 ConstantSDNode *C =
18503 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18507 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18509 if (ShAmt != ShiftAmt)
18512 switch (Op.getOpcode()) {
18514 llvm_unreachable("Unknown shift opcode!");
18516 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18519 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18522 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18530 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18531 const X86Subtarget* Subtarget) {
18532 MVT VT = Op.getSimpleValueType();
18534 SDValue R = Op.getOperand(0);
18535 SDValue Amt = Op.getOperand(1);
18537 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18538 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18539 (Subtarget->hasInt256() &&
18540 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18541 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18542 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18544 EVT EltVT = VT.getVectorElementType();
18546 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18547 // Check if this build_vector node is doing a splat.
18548 // If so, then set BaseShAmt equal to the splat value.
18549 BaseShAmt = BV->getSplatValue();
18550 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18551 BaseShAmt = SDValue();
18553 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18554 Amt = Amt.getOperand(0);
18556 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18557 if (SVN && SVN->isSplat()) {
18558 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18559 SDValue InVec = Amt.getOperand(0);
18560 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18561 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18562 "Unexpected shuffle index found!");
18563 BaseShAmt = InVec.getOperand(SplatIdx);
18564 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18565 if (ConstantSDNode *C =
18566 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18567 if (C->getZExtValue() == SplatIdx)
18568 BaseShAmt = InVec.getOperand(1);
18573 // Avoid introducing an extract element from a shuffle.
18574 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18575 DAG.getIntPtrConstant(SplatIdx));
18579 if (BaseShAmt.getNode()) {
18580 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18581 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18582 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18583 else if (EltVT.bitsLT(MVT::i32))
18584 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18586 switch (Op.getOpcode()) {
18588 llvm_unreachable("Unknown shift opcode!");
18590 switch (VT.SimpleTy) {
18591 default: return SDValue();
18600 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18603 switch (VT.SimpleTy) {
18604 default: return SDValue();
18611 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18614 switch (VT.SimpleTy) {
18615 default: return SDValue();
18624 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18630 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18631 if (!Subtarget->is64Bit() &&
18632 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18633 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18634 Amt.getOpcode() == ISD::BITCAST &&
18635 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18636 Amt = Amt.getOperand(0);
18637 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18638 VT.getVectorNumElements();
18639 std::vector<SDValue> Vals(Ratio);
18640 for (unsigned i = 0; i != Ratio; ++i)
18641 Vals[i] = Amt.getOperand(i);
18642 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18643 for (unsigned j = 0; j != Ratio; ++j)
18644 if (Vals[j] != Amt.getOperand(i + j))
18647 switch (Op.getOpcode()) {
18649 llvm_unreachable("Unknown shift opcode!");
18651 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18653 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18655 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18662 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18663 SelectionDAG &DAG) {
18664 MVT VT = Op.getSimpleValueType();
18666 SDValue R = Op.getOperand(0);
18667 SDValue Amt = Op.getOperand(1);
18670 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18671 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18673 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18677 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18681 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18683 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18684 if (Subtarget->hasInt256()) {
18685 if (Op.getOpcode() == ISD::SRL &&
18686 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18687 VT == MVT::v4i64 || VT == MVT::v8i32))
18689 if (Op.getOpcode() == ISD::SHL &&
18690 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18691 VT == MVT::v4i64 || VT == MVT::v8i32))
18693 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18697 // If possible, lower this packed shift into a vector multiply instead of
18698 // expanding it into a sequence of scalar shifts.
18699 // Do this only if the vector shift count is a constant build_vector.
18700 if (Op.getOpcode() == ISD::SHL &&
18701 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18702 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18703 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18704 SmallVector<SDValue, 8> Elts;
18705 EVT SVT = VT.getScalarType();
18706 unsigned SVTBits = SVT.getSizeInBits();
18707 const APInt &One = APInt(SVTBits, 1);
18708 unsigned NumElems = VT.getVectorNumElements();
18710 for (unsigned i=0; i !=NumElems; ++i) {
18711 SDValue Op = Amt->getOperand(i);
18712 if (Op->getOpcode() == ISD::UNDEF) {
18713 Elts.push_back(Op);
18717 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18718 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18719 uint64_t ShAmt = C.getZExtValue();
18720 if (ShAmt >= SVTBits) {
18721 Elts.push_back(DAG.getUNDEF(SVT));
18724 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18726 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18727 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18730 // Lower SHL with variable shift amount.
18731 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18732 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18734 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18735 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18736 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18737 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18740 // If possible, lower this shift as a sequence of two shifts by
18741 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18743 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18745 // Could be rewritten as:
18746 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18748 // The advantage is that the two shifts from the example would be
18749 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18750 // the vector shift into four scalar shifts plus four pairs of vector
18752 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18753 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18754 unsigned TargetOpcode = X86ISD::MOVSS;
18755 bool CanBeSimplified;
18756 // The splat value for the first packed shift (the 'X' from the example).
18757 SDValue Amt1 = Amt->getOperand(0);
18758 // The splat value for the second packed shift (the 'Y' from the example).
18759 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18760 Amt->getOperand(2);
18762 // See if it is possible to replace this node with a sequence of
18763 // two shifts followed by a MOVSS/MOVSD
18764 if (VT == MVT::v4i32) {
18765 // Check if it is legal to use a MOVSS.
18766 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18767 Amt2 == Amt->getOperand(3);
18768 if (!CanBeSimplified) {
18769 // Otherwise, check if we can still simplify this node using a MOVSD.
18770 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18771 Amt->getOperand(2) == Amt->getOperand(3);
18772 TargetOpcode = X86ISD::MOVSD;
18773 Amt2 = Amt->getOperand(2);
18776 // Do similar checks for the case where the machine value type
18778 CanBeSimplified = Amt1 == Amt->getOperand(1);
18779 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18780 CanBeSimplified = Amt2 == Amt->getOperand(i);
18782 if (!CanBeSimplified) {
18783 TargetOpcode = X86ISD::MOVSD;
18784 CanBeSimplified = true;
18785 Amt2 = Amt->getOperand(4);
18786 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18787 CanBeSimplified = Amt1 == Amt->getOperand(i);
18788 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18789 CanBeSimplified = Amt2 == Amt->getOperand(j);
18793 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18794 isa<ConstantSDNode>(Amt2)) {
18795 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18796 EVT CastVT = MVT::v4i32;
18798 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18799 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18801 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18802 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18803 if (TargetOpcode == X86ISD::MOVSD)
18804 CastVT = MVT::v2i64;
18805 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18806 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18807 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18809 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18813 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18814 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18817 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18818 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18820 // Turn 'a' into a mask suitable for VSELECT
18821 SDValue VSelM = DAG.getConstant(0x80, VT);
18822 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18823 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18825 SDValue CM1 = DAG.getConstant(0x0f, VT);
18826 SDValue CM2 = DAG.getConstant(0x3f, VT);
18828 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18829 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18830 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18831 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18832 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18835 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18836 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18837 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18839 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18840 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18841 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18842 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18843 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18846 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18847 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18848 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18850 // return VSELECT(r, r+r, a);
18851 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18852 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18856 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18857 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18858 // solution better.
18859 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18860 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18862 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18863 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18864 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18865 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18866 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18869 // Decompose 256-bit shifts into smaller 128-bit shifts.
18870 if (VT.is256BitVector()) {
18871 unsigned NumElems = VT.getVectorNumElements();
18872 MVT EltVT = VT.getVectorElementType();
18873 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18875 // Extract the two vectors
18876 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18877 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18879 // Recreate the shift amount vectors
18880 SDValue Amt1, Amt2;
18881 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18882 // Constant shift amount
18883 SmallVector<SDValue, 4> Amt1Csts;
18884 SmallVector<SDValue, 4> Amt2Csts;
18885 for (unsigned i = 0; i != NumElems/2; ++i)
18886 Amt1Csts.push_back(Amt->getOperand(i));
18887 for (unsigned i = NumElems/2; i != NumElems; ++i)
18888 Amt2Csts.push_back(Amt->getOperand(i));
18890 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18891 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18893 // Variable shift amount
18894 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18895 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18898 // Issue new vector shifts for the smaller types
18899 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18900 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18902 // Concatenate the result back
18903 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18909 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18910 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18911 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18912 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18913 // has only one use.
18914 SDNode *N = Op.getNode();
18915 SDValue LHS = N->getOperand(0);
18916 SDValue RHS = N->getOperand(1);
18917 unsigned BaseOp = 0;
18920 switch (Op.getOpcode()) {
18921 default: llvm_unreachable("Unknown ovf instruction!");
18923 // A subtract of one will be selected as a INC. Note that INC doesn't
18924 // set CF, so we can't do this for UADDO.
18925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18927 BaseOp = X86ISD::INC;
18928 Cond = X86::COND_O;
18931 BaseOp = X86ISD::ADD;
18932 Cond = X86::COND_O;
18935 BaseOp = X86ISD::ADD;
18936 Cond = X86::COND_B;
18939 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18940 // set CF, so we can't do this for USUBO.
18941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18943 BaseOp = X86ISD::DEC;
18944 Cond = X86::COND_O;
18947 BaseOp = X86ISD::SUB;
18948 Cond = X86::COND_O;
18951 BaseOp = X86ISD::SUB;
18952 Cond = X86::COND_B;
18955 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18956 Cond = X86::COND_O;
18958 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18959 if (N->getValueType(0) == MVT::i8) {
18960 BaseOp = X86ISD::UMUL8;
18961 Cond = X86::COND_O;
18964 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18966 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18969 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18970 DAG.getConstant(X86::COND_O, MVT::i32),
18971 SDValue(Sum.getNode(), 2));
18973 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18977 // Also sets EFLAGS.
18978 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18979 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18982 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18983 DAG.getConstant(Cond, MVT::i32),
18984 SDValue(Sum.getNode(), 1));
18986 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18989 // Sign extension of the low part of vector elements. This may be used either
18990 // when sign extend instructions are not available or if the vector element
18991 // sizes already match the sign-extended size. If the vector elements are in
18992 // their pre-extended size and sign extend instructions are available, that will
18993 // be handled by LowerSIGN_EXTEND.
18994 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18995 SelectionDAG &DAG) const {
18997 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18998 MVT VT = Op.getSimpleValueType();
19000 if (!Subtarget->hasSSE2() || !VT.isVector())
19003 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
19004 ExtraVT.getScalarType().getSizeInBits();
19006 switch (VT.SimpleTy) {
19007 default: return SDValue();
19010 if (!Subtarget->hasFp256())
19012 if (!Subtarget->hasInt256()) {
19013 // needs to be split
19014 unsigned NumElems = VT.getVectorNumElements();
19016 // Extract the LHS vectors
19017 SDValue LHS = Op.getOperand(0);
19018 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
19019 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
19021 MVT EltVT = VT.getVectorElementType();
19022 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
19024 EVT ExtraEltVT = ExtraVT.getVectorElementType();
19025 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
19026 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
19028 SDValue Extra = DAG.getValueType(ExtraVT);
19030 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
19031 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
19033 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
19038 SDValue Op0 = Op.getOperand(0);
19040 // This is a sign extension of some low part of vector elements without
19041 // changing the size of the vector elements themselves:
19042 // Shift-Left + Shift-Right-Algebraic.
19043 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
19045 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
19051 /// Returns true if the operand type is exactly twice the native width, and
19052 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19053 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19054 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19055 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
19056 const X86Subtarget &Subtarget =
19057 getTargetMachine().getSubtarget<X86Subtarget>();
19058 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19061 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19062 else if (OpWidth == 128)
19063 return Subtarget.hasCmpxchg16b();
19068 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19069 return needsCmpXchgNb(SI->getValueOperand()->getType());
19072 // Note: this turns large loads into lock cmpxchg8b/16b.
19073 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19074 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19075 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19076 return needsCmpXchgNb(PTy->getElementType());
19079 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19080 const X86Subtarget &Subtarget =
19081 getTargetMachine().getSubtarget<X86Subtarget>();
19082 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19083 const Type *MemType = AI->getType();
19085 // If the operand is too big, we must see if cmpxchg8/16b is available
19086 // and default to library calls otherwise.
19087 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19088 return needsCmpXchgNb(MemType);
19090 AtomicRMWInst::BinOp Op = AI->getOperation();
19093 llvm_unreachable("Unknown atomic operation");
19094 case AtomicRMWInst::Xchg:
19095 case AtomicRMWInst::Add:
19096 case AtomicRMWInst::Sub:
19097 // It's better to use xadd, xsub or xchg for these in all cases.
19099 case AtomicRMWInst::Or:
19100 case AtomicRMWInst::And:
19101 case AtomicRMWInst::Xor:
19102 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19103 // prefix to a normal instruction for these operations.
19104 return !AI->use_empty();
19105 case AtomicRMWInst::Nand:
19106 case AtomicRMWInst::Max:
19107 case AtomicRMWInst::Min:
19108 case AtomicRMWInst::UMax:
19109 case AtomicRMWInst::UMin:
19110 // These always require a non-trivial set of data operations on x86. We must
19111 // use a cmpxchg loop.
19116 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19117 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19118 // no-sse2). There isn't any reason to disable it if the target processor
19120 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19124 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19125 const X86Subtarget &Subtarget =
19126 getTargetMachine().getSubtarget<X86Subtarget>();
19127 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19128 const Type *MemType = AI->getType();
19129 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19130 // there is no benefit in turning such RMWs into loads, and it is actually
19131 // harmful as it introduces a mfence.
19132 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19135 auto Builder = IRBuilder<>(AI);
19136 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19137 auto SynchScope = AI->getSynchScope();
19138 // We must restrict the ordering to avoid generating loads with Release or
19139 // ReleaseAcquire orderings.
19140 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19141 auto Ptr = AI->getPointerOperand();
19143 // Before the load we need a fence. Here is an example lifted from
19144 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19147 // x.store(1, relaxed);
19148 // r1 = y.fetch_add(0, release);
19150 // y.fetch_add(42, acquire);
19151 // r2 = x.load(relaxed);
19152 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19153 // lowered to just a load without a fence. A mfence flushes the store buffer,
19154 // making the optimization clearly correct.
19155 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19156 // otherwise, we might be able to be more agressive on relaxed idempotent
19157 // rmw. In practice, they do not look useful, so we don't try to be
19158 // especially clever.
19159 if (SynchScope == SingleThread) {
19160 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19161 // the IR level, so we must wrap it in an intrinsic.
19163 } else if (hasMFENCE(Subtarget)) {
19164 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19165 Intrinsic::x86_sse2_mfence);
19166 Builder.CreateCall(MFence);
19168 // FIXME: it might make sense to use a locked operation here but on a
19169 // different cache-line to prevent cache-line bouncing. In practice it
19170 // is probably a small win, and x86 processors without mfence are rare
19171 // enough that we do not bother.
19175 // Finally we can emit the atomic load.
19176 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19177 AI->getType()->getPrimitiveSizeInBits());
19178 Loaded->setAtomic(Order, SynchScope);
19179 AI->replaceAllUsesWith(Loaded);
19180 AI->eraseFromParent();
19184 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19185 SelectionDAG &DAG) {
19187 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19188 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19189 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19190 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19192 // The only fence that needs an instruction is a sequentially-consistent
19193 // cross-thread fence.
19194 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19195 if (hasMFENCE(*Subtarget))
19196 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19198 SDValue Chain = Op.getOperand(0);
19199 SDValue Zero = DAG.getConstant(0, MVT::i32);
19201 DAG.getRegister(X86::ESP, MVT::i32), // Base
19202 DAG.getTargetConstant(1, MVT::i8), // Scale
19203 DAG.getRegister(0, MVT::i32), // Index
19204 DAG.getTargetConstant(0, MVT::i32), // Disp
19205 DAG.getRegister(0, MVT::i32), // Segment.
19209 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19210 return SDValue(Res, 0);
19213 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19214 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19217 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19218 SelectionDAG &DAG) {
19219 MVT T = Op.getSimpleValueType();
19223 switch(T.SimpleTy) {
19224 default: llvm_unreachable("Invalid value type!");
19225 case MVT::i8: Reg = X86::AL; size = 1; break;
19226 case MVT::i16: Reg = X86::AX; size = 2; break;
19227 case MVT::i32: Reg = X86::EAX; size = 4; break;
19229 assert(Subtarget->is64Bit() && "Node not type legal!");
19230 Reg = X86::RAX; size = 8;
19233 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19234 Op.getOperand(2), SDValue());
19235 SDValue Ops[] = { cpIn.getValue(0),
19238 DAG.getTargetConstant(size, MVT::i8),
19239 cpIn.getValue(1) };
19240 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19241 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19242 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19246 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19247 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19248 MVT::i32, cpOut.getValue(2));
19249 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19250 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19252 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19253 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19254 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19258 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19259 SelectionDAG &DAG) {
19260 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19261 MVT DstVT = Op.getSimpleValueType();
19263 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19264 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19265 if (DstVT != MVT::f64)
19266 // This conversion needs to be expanded.
19269 SDValue InVec = Op->getOperand(0);
19271 unsigned NumElts = SrcVT.getVectorNumElements();
19272 EVT SVT = SrcVT.getVectorElementType();
19274 // Widen the vector in input in the case of MVT::v2i32.
19275 // Example: from MVT::v2i32 to MVT::v4i32.
19276 SmallVector<SDValue, 16> Elts;
19277 for (unsigned i = 0, e = NumElts; i != e; ++i)
19278 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19279 DAG.getIntPtrConstant(i)));
19281 // Explicitly mark the extra elements as Undef.
19282 SDValue Undef = DAG.getUNDEF(SVT);
19283 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19284 Elts.push_back(Undef);
19286 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19287 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19288 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19289 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19290 DAG.getIntPtrConstant(0));
19293 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19294 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19295 assert((DstVT == MVT::i64 ||
19296 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19297 "Unexpected custom BITCAST");
19298 // i64 <=> MMX conversions are Legal.
19299 if (SrcVT==MVT::i64 && DstVT.isVector())
19301 if (DstVT==MVT::i64 && SrcVT.isVector())
19303 // MMX <=> MMX conversions are Legal.
19304 if (SrcVT.isVector() && DstVT.isVector())
19306 // All other conversions need to be expanded.
19310 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19311 SelectionDAG &DAG) {
19312 SDNode *Node = Op.getNode();
19315 Op = Op.getOperand(0);
19316 EVT VT = Op.getValueType();
19317 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19318 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19320 unsigned NumElts = VT.getVectorNumElements();
19321 EVT EltVT = VT.getVectorElementType();
19322 unsigned Len = EltVT.getSizeInBits();
19324 // This is the vectorized version of the "best" algorithm from
19325 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19326 // with a minor tweak to use a series of adds + shifts instead of vector
19327 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19329 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19330 // v8i32 => Always profitable
19332 // FIXME: There a couple of possible improvements:
19334 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19335 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19337 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19338 "CTPOP not implemented for this vector element type.");
19340 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19341 // extra legalization.
19342 bool NeedsBitcast = EltVT == MVT::i32;
19343 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19345 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19346 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19347 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19349 // v = v - ((v >> 1) & 0x55555555...)
19350 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19351 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19352 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19354 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19356 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19357 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19359 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19361 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19362 if (VT != And.getValueType())
19363 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19364 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19366 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19367 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19368 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19369 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19370 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19372 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19373 if (NeedsBitcast) {
19374 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19375 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19376 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19379 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19380 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19381 if (VT != AndRHS.getValueType()) {
19382 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19383 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19385 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19387 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19388 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19389 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19390 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19391 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19393 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19394 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19395 if (NeedsBitcast) {
19396 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19397 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19399 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19400 if (VT != And.getValueType())
19401 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19403 // The algorithm mentioned above uses:
19404 // v = (v * 0x01010101...) >> (Len - 8)
19406 // Change it to use vector adds + vector shifts which yield faster results on
19407 // Haswell than using vector integer multiplication.
19409 // For i32 elements:
19410 // v = v + (v >> 8)
19411 // v = v + (v >> 16)
19413 // For i64 elements:
19414 // v = v + (v >> 8)
19415 // v = v + (v >> 16)
19416 // v = v + (v >> 32)
19419 SmallVector<SDValue, 8> Csts;
19420 for (unsigned i = 8; i <= Len/2; i *= 2) {
19421 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19422 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19423 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19424 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19428 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19429 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19430 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19431 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19432 if (NeedsBitcast) {
19433 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19434 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19436 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19437 if (VT != And.getValueType())
19438 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19443 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19444 SDNode *Node = Op.getNode();
19446 EVT T = Node->getValueType(0);
19447 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19448 DAG.getConstant(0, T), Node->getOperand(2));
19449 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19450 cast<AtomicSDNode>(Node)->getMemoryVT(),
19451 Node->getOperand(0),
19452 Node->getOperand(1), negOp,
19453 cast<AtomicSDNode>(Node)->getMemOperand(),
19454 cast<AtomicSDNode>(Node)->getOrdering(),
19455 cast<AtomicSDNode>(Node)->getSynchScope());
19458 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19459 SDNode *Node = Op.getNode();
19461 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19463 // Convert seq_cst store -> xchg
19464 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19465 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19466 // (The only way to get a 16-byte store is cmpxchg16b)
19467 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19468 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19469 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19470 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19471 cast<AtomicSDNode>(Node)->getMemoryVT(),
19472 Node->getOperand(0),
19473 Node->getOperand(1), Node->getOperand(2),
19474 cast<AtomicSDNode>(Node)->getMemOperand(),
19475 cast<AtomicSDNode>(Node)->getOrdering(),
19476 cast<AtomicSDNode>(Node)->getSynchScope());
19477 return Swap.getValue(1);
19479 // Other atomic stores have a simple pattern.
19483 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19484 EVT VT = Op.getNode()->getSimpleValueType(0);
19486 // Let legalize expand this if it isn't a legal type yet.
19487 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19490 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19493 bool ExtraOp = false;
19494 switch (Op.getOpcode()) {
19495 default: llvm_unreachable("Invalid code");
19496 case ISD::ADDC: Opc = X86ISD::ADD; break;
19497 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19498 case ISD::SUBC: Opc = X86ISD::SUB; break;
19499 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19503 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19505 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19506 Op.getOperand(1), Op.getOperand(2));
19509 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19510 SelectionDAG &DAG) {
19511 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19513 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19514 // which returns the values as { float, float } (in XMM0) or
19515 // { double, double } (which is returned in XMM0, XMM1).
19517 SDValue Arg = Op.getOperand(0);
19518 EVT ArgVT = Arg.getValueType();
19519 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19521 TargetLowering::ArgListTy Args;
19522 TargetLowering::ArgListEntry Entry;
19526 Entry.isSExt = false;
19527 Entry.isZExt = false;
19528 Args.push_back(Entry);
19530 bool isF64 = ArgVT == MVT::f64;
19531 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19532 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19533 // the results are returned via SRet in memory.
19534 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19536 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19538 Type *RetTy = isF64
19539 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19540 : (Type*)VectorType::get(ArgTy, 4);
19542 TargetLowering::CallLoweringInfo CLI(DAG);
19543 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19544 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19546 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19549 // Returned in xmm0 and xmm1.
19550 return CallResult.first;
19552 // Returned in bits 0:31 and 32:64 xmm0.
19553 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19554 CallResult.first, DAG.getIntPtrConstant(0));
19555 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19556 CallResult.first, DAG.getIntPtrConstant(1));
19557 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19558 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19561 /// LowerOperation - Provide custom lowering hooks for some operations.
19563 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19564 switch (Op.getOpcode()) {
19565 default: llvm_unreachable("Should not custom lower this!");
19566 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19567 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19568 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19569 return LowerCMP_SWAP(Op, Subtarget, DAG);
19570 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19571 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19572 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19573 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19574 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19575 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19576 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19577 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19578 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19579 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19580 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19581 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19582 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19583 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19584 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19585 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19586 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19587 case ISD::SHL_PARTS:
19588 case ISD::SRA_PARTS:
19589 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19590 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19591 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19592 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19593 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19594 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19595 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19596 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19597 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19598 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19599 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19601 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19602 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19603 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19604 case ISD::SETCC: return LowerSETCC(Op, DAG);
19605 case ISD::SELECT: return LowerSELECT(Op, DAG);
19606 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19607 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19608 case ISD::VASTART: return LowerVASTART(Op, DAG);
19609 case ISD::VAARG: return LowerVAARG(Op, DAG);
19610 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19611 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19612 case ISD::INTRINSIC_VOID:
19613 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19614 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19615 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19616 case ISD::FRAME_TO_ARGS_OFFSET:
19617 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19618 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19619 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19620 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19621 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19622 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19623 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19624 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19625 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19626 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19627 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19628 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19629 case ISD::UMUL_LOHI:
19630 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19633 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19639 case ISD::UMULO: return LowerXALUO(Op, DAG);
19640 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19641 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19645 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19646 case ISD::ADD: return LowerADD(Op, DAG);
19647 case ISD::SUB: return LowerSUB(Op, DAG);
19648 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19652 /// ReplaceNodeResults - Replace a node with an illegal result type
19653 /// with a new node built out of custom code.
19654 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19655 SmallVectorImpl<SDValue>&Results,
19656 SelectionDAG &DAG) const {
19658 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19659 switch (N->getOpcode()) {
19661 llvm_unreachable("Do not know how to custom type legalize this operation!");
19662 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19663 case X86ISD::FMINC:
19665 case X86ISD::FMAXC:
19666 case X86ISD::FMAX: {
19667 EVT VT = N->getValueType(0);
19668 if (VT != MVT::v2f32)
19669 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19670 SDValue UNDEF = DAG.getUNDEF(VT);
19671 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19672 N->getOperand(0), UNDEF);
19673 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19674 N->getOperand(1), UNDEF);
19675 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19678 case ISD::SIGN_EXTEND_INREG:
19683 // We don't want to expand or promote these.
19690 case ISD::UDIVREM: {
19691 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19692 Results.push_back(V);
19695 case ISD::FP_TO_SINT:
19696 case ISD::FP_TO_UINT: {
19697 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19699 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19702 std::pair<SDValue,SDValue> Vals =
19703 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19704 SDValue FIST = Vals.first, StackSlot = Vals.second;
19705 if (FIST.getNode()) {
19706 EVT VT = N->getValueType(0);
19707 // Return a load from the stack slot.
19708 if (StackSlot.getNode())
19709 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19710 MachinePointerInfo(),
19711 false, false, false, 0));
19713 Results.push_back(FIST);
19717 case ISD::UINT_TO_FP: {
19718 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19719 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19720 N->getValueType(0) != MVT::v2f32)
19722 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19724 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19726 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19727 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19728 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19729 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19730 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19731 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19734 case ISD::FP_ROUND: {
19735 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19737 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19738 Results.push_back(V);
19741 case ISD::INTRINSIC_W_CHAIN: {
19742 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19744 default : llvm_unreachable("Do not know how to custom type "
19745 "legalize this intrinsic operation!");
19746 case Intrinsic::x86_rdtsc:
19747 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19749 case Intrinsic::x86_rdtscp:
19750 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19752 case Intrinsic::x86_rdpmc:
19753 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19756 case ISD::READCYCLECOUNTER: {
19757 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19760 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19761 EVT T = N->getValueType(0);
19762 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19763 bool Regs64bit = T == MVT::i128;
19764 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19765 SDValue cpInL, cpInH;
19766 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19767 DAG.getConstant(0, HalfT));
19768 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19769 DAG.getConstant(1, HalfT));
19770 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19771 Regs64bit ? X86::RAX : X86::EAX,
19773 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19774 Regs64bit ? X86::RDX : X86::EDX,
19775 cpInH, cpInL.getValue(1));
19776 SDValue swapInL, swapInH;
19777 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19778 DAG.getConstant(0, HalfT));
19779 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19780 DAG.getConstant(1, HalfT));
19781 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19782 Regs64bit ? X86::RBX : X86::EBX,
19783 swapInL, cpInH.getValue(1));
19784 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19785 Regs64bit ? X86::RCX : X86::ECX,
19786 swapInH, swapInL.getValue(1));
19787 SDValue Ops[] = { swapInH.getValue(0),
19789 swapInH.getValue(1) };
19790 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19791 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19792 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19793 X86ISD::LCMPXCHG8_DAG;
19794 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19795 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19796 Regs64bit ? X86::RAX : X86::EAX,
19797 HalfT, Result.getValue(1));
19798 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19799 Regs64bit ? X86::RDX : X86::EDX,
19800 HalfT, cpOutL.getValue(2));
19801 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19803 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19804 MVT::i32, cpOutH.getValue(2));
19806 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19807 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19808 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19810 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19811 Results.push_back(Success);
19812 Results.push_back(EFLAGS.getValue(1));
19815 case ISD::ATOMIC_SWAP:
19816 case ISD::ATOMIC_LOAD_ADD:
19817 case ISD::ATOMIC_LOAD_SUB:
19818 case ISD::ATOMIC_LOAD_AND:
19819 case ISD::ATOMIC_LOAD_OR:
19820 case ISD::ATOMIC_LOAD_XOR:
19821 case ISD::ATOMIC_LOAD_NAND:
19822 case ISD::ATOMIC_LOAD_MIN:
19823 case ISD::ATOMIC_LOAD_MAX:
19824 case ISD::ATOMIC_LOAD_UMIN:
19825 case ISD::ATOMIC_LOAD_UMAX:
19826 case ISD::ATOMIC_LOAD: {
19827 // Delegate to generic TypeLegalization. Situations we can really handle
19828 // should have already been dealt with by AtomicExpandPass.cpp.
19831 case ISD::BITCAST: {
19832 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19833 EVT DstVT = N->getValueType(0);
19834 EVT SrcVT = N->getOperand(0)->getValueType(0);
19836 if (SrcVT != MVT::f64 ||
19837 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19840 unsigned NumElts = DstVT.getVectorNumElements();
19841 EVT SVT = DstVT.getVectorElementType();
19842 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19843 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19844 MVT::v2f64, N->getOperand(0));
19845 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19847 if (ExperimentalVectorWideningLegalization) {
19848 // If we are legalizing vectors by widening, we already have the desired
19849 // legal vector type, just return it.
19850 Results.push_back(ToVecInt);
19854 SmallVector<SDValue, 8> Elts;
19855 for (unsigned i = 0, e = NumElts; i != e; ++i)
19856 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19857 ToVecInt, DAG.getIntPtrConstant(i)));
19859 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19864 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19866 default: return nullptr;
19867 case X86ISD::BSF: return "X86ISD::BSF";
19868 case X86ISD::BSR: return "X86ISD::BSR";
19869 case X86ISD::SHLD: return "X86ISD::SHLD";
19870 case X86ISD::SHRD: return "X86ISD::SHRD";
19871 case X86ISD::FAND: return "X86ISD::FAND";
19872 case X86ISD::FANDN: return "X86ISD::FANDN";
19873 case X86ISD::FOR: return "X86ISD::FOR";
19874 case X86ISD::FXOR: return "X86ISD::FXOR";
19875 case X86ISD::FSRL: return "X86ISD::FSRL";
19876 case X86ISD::FILD: return "X86ISD::FILD";
19877 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19878 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19879 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19880 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19881 case X86ISD::FLD: return "X86ISD::FLD";
19882 case X86ISD::FST: return "X86ISD::FST";
19883 case X86ISD::CALL: return "X86ISD::CALL";
19884 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19885 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19886 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19887 case X86ISD::BT: return "X86ISD::BT";
19888 case X86ISD::CMP: return "X86ISD::CMP";
19889 case X86ISD::COMI: return "X86ISD::COMI";
19890 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19891 case X86ISD::CMPM: return "X86ISD::CMPM";
19892 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19893 case X86ISD::SETCC: return "X86ISD::SETCC";
19894 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19895 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19896 case X86ISD::CMOV: return "X86ISD::CMOV";
19897 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19898 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19899 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19900 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19901 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19902 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19903 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19904 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19905 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19906 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19907 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19908 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19909 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19910 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19911 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19912 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19913 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19914 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19915 case X86ISD::HADD: return "X86ISD::HADD";
19916 case X86ISD::HSUB: return "X86ISD::HSUB";
19917 case X86ISD::FHADD: return "X86ISD::FHADD";
19918 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19919 case X86ISD::UMAX: return "X86ISD::UMAX";
19920 case X86ISD::UMIN: return "X86ISD::UMIN";
19921 case X86ISD::SMAX: return "X86ISD::SMAX";
19922 case X86ISD::SMIN: return "X86ISD::SMIN";
19923 case X86ISD::FMAX: return "X86ISD::FMAX";
19924 case X86ISD::FMIN: return "X86ISD::FMIN";
19925 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19926 case X86ISD::FMINC: return "X86ISD::FMINC";
19927 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19928 case X86ISD::FRCP: return "X86ISD::FRCP";
19929 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19930 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19931 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19932 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19933 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19934 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19935 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19936 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19937 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19938 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19939 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19940 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19941 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19942 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19943 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19944 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19945 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19946 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19947 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19948 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19949 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19950 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19951 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19952 case X86ISD::VSHL: return "X86ISD::VSHL";
19953 case X86ISD::VSRL: return "X86ISD::VSRL";
19954 case X86ISD::VSRA: return "X86ISD::VSRA";
19955 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19956 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19957 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19958 case X86ISD::CMPP: return "X86ISD::CMPP";
19959 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19960 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19961 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19962 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19963 case X86ISD::ADD: return "X86ISD::ADD";
19964 case X86ISD::SUB: return "X86ISD::SUB";
19965 case X86ISD::ADC: return "X86ISD::ADC";
19966 case X86ISD::SBB: return "X86ISD::SBB";
19967 case X86ISD::SMUL: return "X86ISD::SMUL";
19968 case X86ISD::UMUL: return "X86ISD::UMUL";
19969 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19970 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19971 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19972 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19973 case X86ISD::INC: return "X86ISD::INC";
19974 case X86ISD::DEC: return "X86ISD::DEC";
19975 case X86ISD::OR: return "X86ISD::OR";
19976 case X86ISD::XOR: return "X86ISD::XOR";
19977 case X86ISD::AND: return "X86ISD::AND";
19978 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19979 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19980 case X86ISD::PTEST: return "X86ISD::PTEST";
19981 case X86ISD::TESTP: return "X86ISD::TESTP";
19982 case X86ISD::TESTM: return "X86ISD::TESTM";
19983 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19984 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19985 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19986 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19987 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19988 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19989 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19990 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19991 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19992 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19993 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19994 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19995 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19996 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19997 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19998 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19999 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20000 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20001 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20002 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20003 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20004 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20005 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20006 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20007 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20008 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20009 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20010 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20011 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20012 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20013 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20014 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20015 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20016 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20017 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20018 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20019 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20020 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20021 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
20022 case X86ISD::SAHF: return "X86ISD::SAHF";
20023 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20024 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20025 case X86ISD::FMADD: return "X86ISD::FMADD";
20026 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20027 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20028 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20029 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20030 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20031 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20032 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20033 case X86ISD::XTEST: return "X86ISD::XTEST";
20034 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20035 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20036 case X86ISD::SELECT: return "X86ISD::SELECT";
20040 // isLegalAddressingMode - Return true if the addressing mode represented
20041 // by AM is legal for this target, for a load/store of the specified type.
20042 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
20044 // X86 supports extremely general addressing modes.
20045 CodeModel::Model M = getTargetMachine().getCodeModel();
20046 Reloc::Model R = getTargetMachine().getRelocationModel();
20048 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20049 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20054 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20056 // If a reference to this global requires an extra load, we can't fold it.
20057 if (isGlobalStubReference(GVFlags))
20060 // If BaseGV requires a register for the PIC base, we cannot also have a
20061 // BaseReg specified.
20062 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20065 // If lower 4G is not available, then we must use rip-relative addressing.
20066 if ((M != CodeModel::Small || R != Reloc::Static) &&
20067 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20071 switch (AM.Scale) {
20077 // These scales always work.
20082 // These scales are formed with basereg+scalereg. Only accept if there is
20087 default: // Other stuff never works.
20094 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20095 unsigned Bits = Ty->getScalarSizeInBits();
20097 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20098 // particularly cheaper than those without.
20102 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20103 // variable shifts just as cheap as scalar ones.
20104 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20107 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20108 // fully general vector.
20112 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20113 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20115 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20116 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20117 return NumBits1 > NumBits2;
20120 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20121 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20124 if (!isTypeLegal(EVT::getEVT(Ty1)))
20127 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20129 // Assuming the caller doesn't have a zeroext or signext return parameter,
20130 // truncation all the way down to i1 is valid.
20134 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20135 return isInt<32>(Imm);
20138 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20139 // Can also use sub to handle negated immediates.
20140 return isInt<32>(Imm);
20143 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20144 if (!VT1.isInteger() || !VT2.isInteger())
20146 unsigned NumBits1 = VT1.getSizeInBits();
20147 unsigned NumBits2 = VT2.getSizeInBits();
20148 return NumBits1 > NumBits2;
20151 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20152 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20153 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20156 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20157 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20158 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20161 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20162 EVT VT1 = Val.getValueType();
20163 if (isZExtFree(VT1, VT2))
20166 if (Val.getOpcode() != ISD::LOAD)
20169 if (!VT1.isSimple() || !VT1.isInteger() ||
20170 !VT2.isSimple() || !VT2.isInteger())
20173 switch (VT1.getSimpleVT().SimpleTy) {
20178 // X86 has 8, 16, and 32-bit zero-extending loads.
20186 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20187 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20190 VT = VT.getScalarType();
20192 if (!VT.isSimple())
20195 switch (VT.getSimpleVT().SimpleTy) {
20206 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20207 // i16 instructions are longer (0x66 prefix) and potentially slower.
20208 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20211 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20212 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20213 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20214 /// are assumed to be legal.
20216 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20218 if (!VT.isSimple())
20221 MVT SVT = VT.getSimpleVT();
20223 // Very little shuffling can be done for 64-bit vectors right now.
20224 if (VT.getSizeInBits() == 64)
20227 // This is an experimental legality test that is tailored to match the
20228 // legality test of the experimental lowering more closely. They are gated
20229 // separately to ease testing of performance differences.
20230 if (ExperimentalVectorShuffleLegality)
20231 // We only care that the types being shuffled are legal. The lowering can
20232 // handle any possible shuffle mask that results.
20233 return isTypeLegal(SVT);
20235 // If this is a single-input shuffle with no 128 bit lane crossings we can
20236 // lower it into pshufb.
20237 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20238 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20239 bool isLegal = true;
20240 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20241 if (M[I] >= (int)SVT.getVectorNumElements() ||
20242 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20251 // FIXME: blends, shifts.
20252 return (SVT.getVectorNumElements() == 2 ||
20253 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20254 isMOVLMask(M, SVT) ||
20255 isCommutedMOVLMask(M, SVT) ||
20256 isMOVHLPSMask(M, SVT) ||
20257 isSHUFPMask(M, SVT) ||
20258 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20259 isPSHUFDMask(M, SVT) ||
20260 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20261 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20262 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20263 isPALIGNRMask(M, SVT, Subtarget) ||
20264 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20265 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20266 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20267 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20268 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20269 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20273 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20275 if (!VT.isSimple())
20278 MVT SVT = VT.getSimpleVT();
20280 // This is an experimental legality test that is tailored to match the
20281 // legality test of the experimental lowering more closely. They are gated
20282 // separately to ease testing of performance differences.
20283 if (ExperimentalVectorShuffleLegality)
20284 // The new vector shuffle lowering is very good at managing zero-inputs.
20285 return isShuffleMaskLegal(Mask, VT);
20287 unsigned NumElts = SVT.getVectorNumElements();
20288 // FIXME: This collection of masks seems suspect.
20291 if (NumElts == 4 && SVT.is128BitVector()) {
20292 return (isMOVLMask(Mask, SVT) ||
20293 isCommutedMOVLMask(Mask, SVT, true) ||
20294 isSHUFPMask(Mask, SVT) ||
20295 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20296 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20297 Subtarget->hasInt256()));
20302 //===----------------------------------------------------------------------===//
20303 // X86 Scheduler Hooks
20304 //===----------------------------------------------------------------------===//
20306 /// Utility function to emit xbegin specifying the start of an RTM region.
20307 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20308 const TargetInstrInfo *TII) {
20309 DebugLoc DL = MI->getDebugLoc();
20311 const BasicBlock *BB = MBB->getBasicBlock();
20312 MachineFunction::iterator I = MBB;
20315 // For the v = xbegin(), we generate
20326 MachineBasicBlock *thisMBB = MBB;
20327 MachineFunction *MF = MBB->getParent();
20328 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20329 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20330 MF->insert(I, mainMBB);
20331 MF->insert(I, sinkMBB);
20333 // Transfer the remainder of BB and its successor edges to sinkMBB.
20334 sinkMBB->splice(sinkMBB->begin(), MBB,
20335 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20336 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20340 // # fallthrough to mainMBB
20341 // # abortion to sinkMBB
20342 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20343 thisMBB->addSuccessor(mainMBB);
20344 thisMBB->addSuccessor(sinkMBB);
20348 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20349 mainMBB->addSuccessor(sinkMBB);
20352 // EAX is live into the sinkMBB
20353 sinkMBB->addLiveIn(X86::EAX);
20354 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20355 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20358 MI->eraseFromParent();
20362 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20363 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20364 // in the .td file.
20365 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20366 const TargetInstrInfo *TII) {
20368 switch (MI->getOpcode()) {
20369 default: llvm_unreachable("illegal opcode!");
20370 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20371 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20372 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20373 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20374 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20375 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20376 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20377 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20380 DebugLoc dl = MI->getDebugLoc();
20381 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20383 unsigned NumArgs = MI->getNumOperands();
20384 for (unsigned i = 1; i < NumArgs; ++i) {
20385 MachineOperand &Op = MI->getOperand(i);
20386 if (!(Op.isReg() && Op.isImplicit()))
20387 MIB.addOperand(Op);
20389 if (MI->hasOneMemOperand())
20390 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20392 BuildMI(*BB, MI, dl,
20393 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20394 .addReg(X86::XMM0);
20396 MI->eraseFromParent();
20400 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20401 // defs in an instruction pattern
20402 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20403 const TargetInstrInfo *TII) {
20405 switch (MI->getOpcode()) {
20406 default: llvm_unreachable("illegal opcode!");
20407 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20408 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20409 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20410 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20411 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20412 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20413 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20414 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20417 DebugLoc dl = MI->getDebugLoc();
20418 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20420 unsigned NumArgs = MI->getNumOperands(); // remove the results
20421 for (unsigned i = 1; i < NumArgs; ++i) {
20422 MachineOperand &Op = MI->getOperand(i);
20423 if (!(Op.isReg() && Op.isImplicit()))
20424 MIB.addOperand(Op);
20426 if (MI->hasOneMemOperand())
20427 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20429 BuildMI(*BB, MI, dl,
20430 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20433 MI->eraseFromParent();
20437 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20438 const TargetInstrInfo *TII,
20439 const X86Subtarget* Subtarget) {
20440 DebugLoc dl = MI->getDebugLoc();
20442 // Address into RAX/EAX, other two args into ECX, EDX.
20443 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20444 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20445 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20446 for (int i = 0; i < X86::AddrNumOperands; ++i)
20447 MIB.addOperand(MI->getOperand(i));
20449 unsigned ValOps = X86::AddrNumOperands;
20450 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20451 .addReg(MI->getOperand(ValOps).getReg());
20452 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20453 .addReg(MI->getOperand(ValOps+1).getReg());
20455 // The instruction doesn't actually take any operands though.
20456 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20458 MI->eraseFromParent(); // The pseudo is gone now.
20462 MachineBasicBlock *
20463 X86TargetLowering::EmitVAARG64WithCustomInserter(
20465 MachineBasicBlock *MBB) const {
20466 // Emit va_arg instruction on X86-64.
20468 // Operands to this pseudo-instruction:
20469 // 0 ) Output : destination address (reg)
20470 // 1-5) Input : va_list address (addr, i64mem)
20471 // 6 ) ArgSize : Size (in bytes) of vararg type
20472 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20473 // 8 ) Align : Alignment of type
20474 // 9 ) EFLAGS (implicit-def)
20476 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20477 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20479 unsigned DestReg = MI->getOperand(0).getReg();
20480 MachineOperand &Base = MI->getOperand(1);
20481 MachineOperand &Scale = MI->getOperand(2);
20482 MachineOperand &Index = MI->getOperand(3);
20483 MachineOperand &Disp = MI->getOperand(4);
20484 MachineOperand &Segment = MI->getOperand(5);
20485 unsigned ArgSize = MI->getOperand(6).getImm();
20486 unsigned ArgMode = MI->getOperand(7).getImm();
20487 unsigned Align = MI->getOperand(8).getImm();
20489 // Memory Reference
20490 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20491 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20492 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20494 // Machine Information
20495 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20496 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20497 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20498 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20499 DebugLoc DL = MI->getDebugLoc();
20501 // struct va_list {
20504 // i64 overflow_area (address)
20505 // i64 reg_save_area (address)
20507 // sizeof(va_list) = 24
20508 // alignment(va_list) = 8
20510 unsigned TotalNumIntRegs = 6;
20511 unsigned TotalNumXMMRegs = 8;
20512 bool UseGPOffset = (ArgMode == 1);
20513 bool UseFPOffset = (ArgMode == 2);
20514 unsigned MaxOffset = TotalNumIntRegs * 8 +
20515 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20517 /* Align ArgSize to a multiple of 8 */
20518 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20519 bool NeedsAlign = (Align > 8);
20521 MachineBasicBlock *thisMBB = MBB;
20522 MachineBasicBlock *overflowMBB;
20523 MachineBasicBlock *offsetMBB;
20524 MachineBasicBlock *endMBB;
20526 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20527 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20528 unsigned OffsetReg = 0;
20530 if (!UseGPOffset && !UseFPOffset) {
20531 // If we only pull from the overflow region, we don't create a branch.
20532 // We don't need to alter control flow.
20533 OffsetDestReg = 0; // unused
20534 OverflowDestReg = DestReg;
20536 offsetMBB = nullptr;
20537 overflowMBB = thisMBB;
20540 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20541 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20542 // If not, pull from overflow_area. (branch to overflowMBB)
20547 // offsetMBB overflowMBB
20552 // Registers for the PHI in endMBB
20553 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20554 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20556 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20557 MachineFunction *MF = MBB->getParent();
20558 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20559 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20560 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20562 MachineFunction::iterator MBBIter = MBB;
20565 // Insert the new basic blocks
20566 MF->insert(MBBIter, offsetMBB);
20567 MF->insert(MBBIter, overflowMBB);
20568 MF->insert(MBBIter, endMBB);
20570 // Transfer the remainder of MBB and its successor edges to endMBB.
20571 endMBB->splice(endMBB->begin(), thisMBB,
20572 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20573 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20575 // Make offsetMBB and overflowMBB successors of thisMBB
20576 thisMBB->addSuccessor(offsetMBB);
20577 thisMBB->addSuccessor(overflowMBB);
20579 // endMBB is a successor of both offsetMBB and overflowMBB
20580 offsetMBB->addSuccessor(endMBB);
20581 overflowMBB->addSuccessor(endMBB);
20583 // Load the offset value into a register
20584 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20585 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20589 .addDisp(Disp, UseFPOffset ? 4 : 0)
20590 .addOperand(Segment)
20591 .setMemRefs(MMOBegin, MMOEnd);
20593 // Check if there is enough room left to pull this argument.
20594 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20596 .addImm(MaxOffset + 8 - ArgSizeA8);
20598 // Branch to "overflowMBB" if offset >= max
20599 // Fall through to "offsetMBB" otherwise
20600 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20601 .addMBB(overflowMBB);
20604 // In offsetMBB, emit code to use the reg_save_area.
20606 assert(OffsetReg != 0);
20608 // Read the reg_save_area address.
20609 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20610 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20615 .addOperand(Segment)
20616 .setMemRefs(MMOBegin, MMOEnd);
20618 // Zero-extend the offset
20619 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20620 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20623 .addImm(X86::sub_32bit);
20625 // Add the offset to the reg_save_area to get the final address.
20626 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20627 .addReg(OffsetReg64)
20628 .addReg(RegSaveReg);
20630 // Compute the offset for the next argument
20631 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20632 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20634 .addImm(UseFPOffset ? 16 : 8);
20636 // Store it back into the va_list.
20637 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20641 .addDisp(Disp, UseFPOffset ? 4 : 0)
20642 .addOperand(Segment)
20643 .addReg(NextOffsetReg)
20644 .setMemRefs(MMOBegin, MMOEnd);
20647 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20652 // Emit code to use overflow area
20655 // Load the overflow_area address into a register.
20656 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20657 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20662 .addOperand(Segment)
20663 .setMemRefs(MMOBegin, MMOEnd);
20665 // If we need to align it, do so. Otherwise, just copy the address
20666 // to OverflowDestReg.
20668 // Align the overflow address
20669 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20670 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20672 // aligned_addr = (addr + (align-1)) & ~(align-1)
20673 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20674 .addReg(OverflowAddrReg)
20677 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20679 .addImm(~(uint64_t)(Align-1));
20681 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20682 .addReg(OverflowAddrReg);
20685 // Compute the next overflow address after this argument.
20686 // (the overflow address should be kept 8-byte aligned)
20687 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20688 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20689 .addReg(OverflowDestReg)
20690 .addImm(ArgSizeA8);
20692 // Store the new overflow address.
20693 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20698 .addOperand(Segment)
20699 .addReg(NextAddrReg)
20700 .setMemRefs(MMOBegin, MMOEnd);
20702 // If we branched, emit the PHI to the front of endMBB.
20704 BuildMI(*endMBB, endMBB->begin(), DL,
20705 TII->get(X86::PHI), DestReg)
20706 .addReg(OffsetDestReg).addMBB(offsetMBB)
20707 .addReg(OverflowDestReg).addMBB(overflowMBB);
20710 // Erase the pseudo instruction
20711 MI->eraseFromParent();
20716 MachineBasicBlock *
20717 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20719 MachineBasicBlock *MBB) const {
20720 // Emit code to save XMM registers to the stack. The ABI says that the
20721 // number of registers to save is given in %al, so it's theoretically
20722 // possible to do an indirect jump trick to avoid saving all of them,
20723 // however this code takes a simpler approach and just executes all
20724 // of the stores if %al is non-zero. It's less code, and it's probably
20725 // easier on the hardware branch predictor, and stores aren't all that
20726 // expensive anyway.
20728 // Create the new basic blocks. One block contains all the XMM stores,
20729 // and one block is the final destination regardless of whether any
20730 // stores were performed.
20731 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20732 MachineFunction *F = MBB->getParent();
20733 MachineFunction::iterator MBBIter = MBB;
20735 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20736 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20737 F->insert(MBBIter, XMMSaveMBB);
20738 F->insert(MBBIter, EndMBB);
20740 // Transfer the remainder of MBB and its successor edges to EndMBB.
20741 EndMBB->splice(EndMBB->begin(), MBB,
20742 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20743 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20745 // The original block will now fall through to the XMM save block.
20746 MBB->addSuccessor(XMMSaveMBB);
20747 // The XMMSaveMBB will fall through to the end block.
20748 XMMSaveMBB->addSuccessor(EndMBB);
20750 // Now add the instructions.
20751 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20752 DebugLoc DL = MI->getDebugLoc();
20754 unsigned CountReg = MI->getOperand(0).getReg();
20755 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20756 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20758 if (!Subtarget->isTargetWin64()) {
20759 // If %al is 0, branch around the XMM save block.
20760 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20761 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20762 MBB->addSuccessor(EndMBB);
20765 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20766 // that was just emitted, but clearly shouldn't be "saved".
20767 assert((MI->getNumOperands() <= 3 ||
20768 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20769 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20770 && "Expected last argument to be EFLAGS");
20771 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20772 // In the XMM save block, save all the XMM argument registers.
20773 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20774 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20775 MachineMemOperand *MMO =
20776 F->getMachineMemOperand(
20777 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20778 MachineMemOperand::MOStore,
20779 /*Size=*/16, /*Align=*/16);
20780 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20781 .addFrameIndex(RegSaveFrameIndex)
20782 .addImm(/*Scale=*/1)
20783 .addReg(/*IndexReg=*/0)
20784 .addImm(/*Disp=*/Offset)
20785 .addReg(/*Segment=*/0)
20786 .addReg(MI->getOperand(i).getReg())
20787 .addMemOperand(MMO);
20790 MI->eraseFromParent(); // The pseudo instruction is gone now.
20795 // The EFLAGS operand of SelectItr might be missing a kill marker
20796 // because there were multiple uses of EFLAGS, and ISel didn't know
20797 // which to mark. Figure out whether SelectItr should have had a
20798 // kill marker, and set it if it should. Returns the correct kill
20800 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20801 MachineBasicBlock* BB,
20802 const TargetRegisterInfo* TRI) {
20803 // Scan forward through BB for a use/def of EFLAGS.
20804 MachineBasicBlock::iterator miI(std::next(SelectItr));
20805 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20806 const MachineInstr& mi = *miI;
20807 if (mi.readsRegister(X86::EFLAGS))
20809 if (mi.definesRegister(X86::EFLAGS))
20810 break; // Should have kill-flag - update below.
20813 // If we hit the end of the block, check whether EFLAGS is live into a
20815 if (miI == BB->end()) {
20816 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20817 sEnd = BB->succ_end();
20818 sItr != sEnd; ++sItr) {
20819 MachineBasicBlock* succ = *sItr;
20820 if (succ->isLiveIn(X86::EFLAGS))
20825 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20826 // out. SelectMI should have a kill flag on EFLAGS.
20827 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20831 MachineBasicBlock *
20832 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20833 MachineBasicBlock *BB) const {
20834 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20835 DebugLoc DL = MI->getDebugLoc();
20837 // To "insert" a SELECT_CC instruction, we actually have to insert the
20838 // diamond control-flow pattern. The incoming instruction knows the
20839 // destination vreg to set, the condition code register to branch on, the
20840 // true/false values to select between, and a branch opcode to use.
20841 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20842 MachineFunction::iterator It = BB;
20848 // cmpTY ccX, r1, r2
20850 // fallthrough --> copy0MBB
20851 MachineBasicBlock *thisMBB = BB;
20852 MachineFunction *F = BB->getParent();
20853 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20854 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20855 F->insert(It, copy0MBB);
20856 F->insert(It, sinkMBB);
20858 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20859 // live into the sink and copy blocks.
20860 const TargetRegisterInfo *TRI =
20861 BB->getParent()->getSubtarget().getRegisterInfo();
20862 if (!MI->killsRegister(X86::EFLAGS) &&
20863 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20864 copy0MBB->addLiveIn(X86::EFLAGS);
20865 sinkMBB->addLiveIn(X86::EFLAGS);
20868 // Transfer the remainder of BB and its successor edges to sinkMBB.
20869 sinkMBB->splice(sinkMBB->begin(), BB,
20870 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20871 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20873 // Add the true and fallthrough blocks as its successors.
20874 BB->addSuccessor(copy0MBB);
20875 BB->addSuccessor(sinkMBB);
20877 // Create the conditional branch instruction.
20879 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20880 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20883 // %FalseValue = ...
20884 // # fallthrough to sinkMBB
20885 copy0MBB->addSuccessor(sinkMBB);
20888 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20890 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20891 TII->get(X86::PHI), MI->getOperand(0).getReg())
20892 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20893 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20895 MI->eraseFromParent(); // The pseudo instruction is gone now.
20899 MachineBasicBlock *
20900 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20901 MachineBasicBlock *BB) const {
20902 MachineFunction *MF = BB->getParent();
20903 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20904 DebugLoc DL = MI->getDebugLoc();
20905 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20907 assert(MF->shouldSplitStack());
20909 const bool Is64Bit = Subtarget->is64Bit();
20910 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20912 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20913 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20916 // ... [Till the alloca]
20917 // If stacklet is not large enough, jump to mallocMBB
20920 // Allocate by subtracting from RSP
20921 // Jump to continueMBB
20924 // Allocate by call to runtime
20928 // [rest of original BB]
20931 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20932 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20933 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20935 MachineRegisterInfo &MRI = MF->getRegInfo();
20936 const TargetRegisterClass *AddrRegClass =
20937 getRegClassFor(getPointerTy());
20939 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20940 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20941 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20942 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20943 sizeVReg = MI->getOperand(1).getReg(),
20944 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20946 MachineFunction::iterator MBBIter = BB;
20949 MF->insert(MBBIter, bumpMBB);
20950 MF->insert(MBBIter, mallocMBB);
20951 MF->insert(MBBIter, continueMBB);
20953 continueMBB->splice(continueMBB->begin(), BB,
20954 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20955 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20957 // Add code to the main basic block to check if the stack limit has been hit,
20958 // and if so, jump to mallocMBB otherwise to bumpMBB.
20959 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20960 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20961 .addReg(tmpSPVReg).addReg(sizeVReg);
20962 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20963 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20964 .addReg(SPLimitVReg);
20965 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20967 // bumpMBB simply decreases the stack pointer, since we know the current
20968 // stacklet has enough space.
20969 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20970 .addReg(SPLimitVReg);
20971 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20972 .addReg(SPLimitVReg);
20973 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20975 // Calls into a routine in libgcc to allocate more space from the heap.
20976 const uint32_t *RegMask = MF->getTarget()
20977 .getSubtargetImpl()
20978 ->getRegisterInfo()
20979 ->getCallPreservedMask(CallingConv::C);
20981 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20983 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20984 .addExternalSymbol("__morestack_allocate_stack_space")
20985 .addRegMask(RegMask)
20986 .addReg(X86::RDI, RegState::Implicit)
20987 .addReg(X86::RAX, RegState::ImplicitDefine);
20988 } else if (Is64Bit) {
20989 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20991 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20992 .addExternalSymbol("__morestack_allocate_stack_space")
20993 .addRegMask(RegMask)
20994 .addReg(X86::EDI, RegState::Implicit)
20995 .addReg(X86::EAX, RegState::ImplicitDefine);
20997 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20999 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21000 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21001 .addExternalSymbol("__morestack_allocate_stack_space")
21002 .addRegMask(RegMask)
21003 .addReg(X86::EAX, RegState::ImplicitDefine);
21007 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21010 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21011 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21012 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21014 // Set up the CFG correctly.
21015 BB->addSuccessor(bumpMBB);
21016 BB->addSuccessor(mallocMBB);
21017 mallocMBB->addSuccessor(continueMBB);
21018 bumpMBB->addSuccessor(continueMBB);
21020 // Take care of the PHI nodes.
21021 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21022 MI->getOperand(0).getReg())
21023 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21024 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21026 // Delete the original pseudo instruction.
21027 MI->eraseFromParent();
21030 return continueMBB;
21033 MachineBasicBlock *
21034 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21035 MachineBasicBlock *BB) const {
21036 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
21037 DebugLoc DL = MI->getDebugLoc();
21039 assert(!Subtarget->isTargetMachO());
21041 // The lowering is pretty easy: we're just emitting the call to _alloca. The
21042 // non-trivial part is impdef of ESP.
21044 if (Subtarget->isTargetWin64()) {
21045 if (Subtarget->isTargetCygMing()) {
21046 // ___chkstk(Mingw64):
21047 // Clobbers R10, R11, RAX and EFLAGS.
21049 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
21050 .addExternalSymbol("___chkstk")
21051 .addReg(X86::RAX, RegState::Implicit)
21052 .addReg(X86::RSP, RegState::Implicit)
21053 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
21054 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
21055 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21057 // __chkstk(MSVCRT): does not update stack pointer.
21058 // Clobbers R10, R11 and EFLAGS.
21059 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
21060 .addExternalSymbol("__chkstk")
21061 .addReg(X86::RAX, RegState::Implicit)
21062 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21063 // RAX has the offset to be subtracted from RSP.
21064 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
21069 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
21070 Subtarget->isTargetWindowsItanium())
21074 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
21075 .addExternalSymbol(StackProbeSymbol)
21076 .addReg(X86::EAX, RegState::Implicit)
21077 .addReg(X86::ESP, RegState::Implicit)
21078 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
21079 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
21080 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21083 MI->eraseFromParent(); // The pseudo instruction is gone now.
21087 MachineBasicBlock *
21088 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21089 MachineBasicBlock *BB) const {
21090 // This is pretty easy. We're taking the value that we received from
21091 // our load from the relocation, sticking it in either RDI (x86-64)
21092 // or EAX and doing an indirect call. The return value will then
21093 // be in the normal return register.
21094 MachineFunction *F = BB->getParent();
21095 const X86InstrInfo *TII =
21096 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
21097 DebugLoc DL = MI->getDebugLoc();
21099 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21100 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21102 // Get a register mask for the lowered call.
21103 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21104 // proper register mask.
21105 const uint32_t *RegMask = F->getTarget()
21106 .getSubtargetImpl()
21107 ->getRegisterInfo()
21108 ->getCallPreservedMask(CallingConv::C);
21109 if (Subtarget->is64Bit()) {
21110 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21111 TII->get(X86::MOV64rm), X86::RDI)
21113 .addImm(0).addReg(0)
21114 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21115 MI->getOperand(3).getTargetFlags())
21117 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21118 addDirectMem(MIB, X86::RDI);
21119 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21120 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21121 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21122 TII->get(X86::MOV32rm), X86::EAX)
21124 .addImm(0).addReg(0)
21125 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21126 MI->getOperand(3).getTargetFlags())
21128 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21129 addDirectMem(MIB, X86::EAX);
21130 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21132 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21133 TII->get(X86::MOV32rm), X86::EAX)
21134 .addReg(TII->getGlobalBaseReg(F))
21135 .addImm(0).addReg(0)
21136 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21137 MI->getOperand(3).getTargetFlags())
21139 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21140 addDirectMem(MIB, X86::EAX);
21141 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21144 MI->eraseFromParent(); // The pseudo instruction is gone now.
21148 MachineBasicBlock *
21149 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21150 MachineBasicBlock *MBB) const {
21151 DebugLoc DL = MI->getDebugLoc();
21152 MachineFunction *MF = MBB->getParent();
21153 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21154 MachineRegisterInfo &MRI = MF->getRegInfo();
21156 const BasicBlock *BB = MBB->getBasicBlock();
21157 MachineFunction::iterator I = MBB;
21160 // Memory Reference
21161 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21162 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21165 unsigned MemOpndSlot = 0;
21167 unsigned CurOp = 0;
21169 DstReg = MI->getOperand(CurOp++).getReg();
21170 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21171 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21172 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21173 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21175 MemOpndSlot = CurOp;
21177 MVT PVT = getPointerTy();
21178 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21179 "Invalid Pointer Size!");
21181 // For v = setjmp(buf), we generate
21184 // buf[LabelOffset] = restoreMBB
21185 // SjLjSetup restoreMBB
21191 // v = phi(main, restore)
21194 // if base pointer being used, load it from frame
21197 MachineBasicBlock *thisMBB = MBB;
21198 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21199 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21200 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21201 MF->insert(I, mainMBB);
21202 MF->insert(I, sinkMBB);
21203 MF->push_back(restoreMBB);
21205 MachineInstrBuilder MIB;
21207 // Transfer the remainder of BB and its successor edges to sinkMBB.
21208 sinkMBB->splice(sinkMBB->begin(), MBB,
21209 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21210 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21213 unsigned PtrStoreOpc = 0;
21214 unsigned LabelReg = 0;
21215 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21216 Reloc::Model RM = MF->getTarget().getRelocationModel();
21217 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21218 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21220 // Prepare IP either in reg or imm.
21221 if (!UseImmLabel) {
21222 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21223 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21224 LabelReg = MRI.createVirtualRegister(PtrRC);
21225 if (Subtarget->is64Bit()) {
21226 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21230 .addMBB(restoreMBB)
21233 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21234 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21235 .addReg(XII->getGlobalBaseReg(MF))
21238 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21242 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21244 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21245 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21246 if (i == X86::AddrDisp)
21247 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21249 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21252 MIB.addReg(LabelReg);
21254 MIB.addMBB(restoreMBB);
21255 MIB.setMemRefs(MMOBegin, MMOEnd);
21257 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21258 .addMBB(restoreMBB);
21260 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21261 MF->getSubtarget().getRegisterInfo());
21262 MIB.addRegMask(RegInfo->getNoPreservedMask());
21263 thisMBB->addSuccessor(mainMBB);
21264 thisMBB->addSuccessor(restoreMBB);
21268 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21269 mainMBB->addSuccessor(sinkMBB);
21272 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21273 TII->get(X86::PHI), DstReg)
21274 .addReg(mainDstReg).addMBB(mainMBB)
21275 .addReg(restoreDstReg).addMBB(restoreMBB);
21278 if (RegInfo->hasBasePointer(*MF)) {
21279 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21280 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21281 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21282 X86FI->setRestoreBasePointer(MF);
21283 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21284 unsigned BasePtr = RegInfo->getBaseRegister();
21285 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21286 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21287 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21288 .setMIFlag(MachineInstr::FrameSetup);
21290 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21291 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21292 restoreMBB->addSuccessor(sinkMBB);
21294 MI->eraseFromParent();
21298 MachineBasicBlock *
21299 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21300 MachineBasicBlock *MBB) const {
21301 DebugLoc DL = MI->getDebugLoc();
21302 MachineFunction *MF = MBB->getParent();
21303 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21304 MachineRegisterInfo &MRI = MF->getRegInfo();
21306 // Memory Reference
21307 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21308 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21310 MVT PVT = getPointerTy();
21311 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21312 "Invalid Pointer Size!");
21314 const TargetRegisterClass *RC =
21315 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21316 unsigned Tmp = MRI.createVirtualRegister(RC);
21317 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21318 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21319 MF->getSubtarget().getRegisterInfo());
21320 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21321 unsigned SP = RegInfo->getStackRegister();
21323 MachineInstrBuilder MIB;
21325 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21326 const int64_t SPOffset = 2 * PVT.getStoreSize();
21328 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21329 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21332 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21333 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21334 MIB.addOperand(MI->getOperand(i));
21335 MIB.setMemRefs(MMOBegin, MMOEnd);
21337 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21338 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21339 if (i == X86::AddrDisp)
21340 MIB.addDisp(MI->getOperand(i), LabelOffset);
21342 MIB.addOperand(MI->getOperand(i));
21344 MIB.setMemRefs(MMOBegin, MMOEnd);
21346 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21347 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21348 if (i == X86::AddrDisp)
21349 MIB.addDisp(MI->getOperand(i), SPOffset);
21351 MIB.addOperand(MI->getOperand(i));
21353 MIB.setMemRefs(MMOBegin, MMOEnd);
21355 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21357 MI->eraseFromParent();
21361 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21362 // accumulator loops. Writing back to the accumulator allows the coalescer
21363 // to remove extra copies in the loop.
21364 MachineBasicBlock *
21365 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21366 MachineBasicBlock *MBB) const {
21367 MachineOperand &AddendOp = MI->getOperand(3);
21369 // Bail out early if the addend isn't a register - we can't switch these.
21370 if (!AddendOp.isReg())
21373 MachineFunction &MF = *MBB->getParent();
21374 MachineRegisterInfo &MRI = MF.getRegInfo();
21376 // Check whether the addend is defined by a PHI:
21377 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21378 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21379 if (!AddendDef.isPHI())
21382 // Look for the following pattern:
21384 // %addend = phi [%entry, 0], [%loop, %result]
21386 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21390 // %addend = phi [%entry, 0], [%loop, %result]
21392 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21394 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21395 assert(AddendDef.getOperand(i).isReg());
21396 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21397 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21398 if (&PHISrcInst == MI) {
21399 // Found a matching instruction.
21400 unsigned NewFMAOpc = 0;
21401 switch (MI->getOpcode()) {
21402 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21403 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21404 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21405 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21406 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21407 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21408 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21409 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21410 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21411 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21412 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21413 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21414 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21415 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21416 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21417 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21418 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21419 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21420 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21421 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21423 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21424 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21425 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21426 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21427 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21428 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21429 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21430 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21431 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21432 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21433 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21434 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21435 default: llvm_unreachable("Unrecognized FMA variant.");
21438 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21439 MachineInstrBuilder MIB =
21440 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21441 .addOperand(MI->getOperand(0))
21442 .addOperand(MI->getOperand(3))
21443 .addOperand(MI->getOperand(2))
21444 .addOperand(MI->getOperand(1));
21445 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21446 MI->eraseFromParent();
21453 MachineBasicBlock *
21454 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21455 MachineBasicBlock *BB) const {
21456 switch (MI->getOpcode()) {
21457 default: llvm_unreachable("Unexpected instr type to insert");
21458 case X86::TAILJMPd64:
21459 case X86::TAILJMPr64:
21460 case X86::TAILJMPm64:
21461 llvm_unreachable("TAILJMP64 would not be touched here.");
21462 case X86::TCRETURNdi64:
21463 case X86::TCRETURNri64:
21464 case X86::TCRETURNmi64:
21466 case X86::WIN_ALLOCA:
21467 return EmitLoweredWinAlloca(MI, BB);
21468 case X86::SEG_ALLOCA_32:
21469 case X86::SEG_ALLOCA_64:
21470 return EmitLoweredSegAlloca(MI, BB);
21471 case X86::TLSCall_32:
21472 case X86::TLSCall_64:
21473 return EmitLoweredTLSCall(MI, BB);
21474 case X86::CMOV_GR8:
21475 case X86::CMOV_FR32:
21476 case X86::CMOV_FR64:
21477 case X86::CMOV_V4F32:
21478 case X86::CMOV_V2F64:
21479 case X86::CMOV_V2I64:
21480 case X86::CMOV_V8F32:
21481 case X86::CMOV_V4F64:
21482 case X86::CMOV_V4I64:
21483 case X86::CMOV_V16F32:
21484 case X86::CMOV_V8F64:
21485 case X86::CMOV_V8I64:
21486 case X86::CMOV_GR16:
21487 case X86::CMOV_GR32:
21488 case X86::CMOV_RFP32:
21489 case X86::CMOV_RFP64:
21490 case X86::CMOV_RFP80:
21491 return EmitLoweredSelect(MI, BB);
21493 case X86::FP32_TO_INT16_IN_MEM:
21494 case X86::FP32_TO_INT32_IN_MEM:
21495 case X86::FP32_TO_INT64_IN_MEM:
21496 case X86::FP64_TO_INT16_IN_MEM:
21497 case X86::FP64_TO_INT32_IN_MEM:
21498 case X86::FP64_TO_INT64_IN_MEM:
21499 case X86::FP80_TO_INT16_IN_MEM:
21500 case X86::FP80_TO_INT32_IN_MEM:
21501 case X86::FP80_TO_INT64_IN_MEM: {
21502 MachineFunction *F = BB->getParent();
21503 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21504 DebugLoc DL = MI->getDebugLoc();
21506 // Change the floating point control register to use "round towards zero"
21507 // mode when truncating to an integer value.
21508 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21509 addFrameReference(BuildMI(*BB, MI, DL,
21510 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21512 // Load the old value of the high byte of the control word...
21514 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21515 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21518 // Set the high part to be round to zero...
21519 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21522 // Reload the modified control word now...
21523 addFrameReference(BuildMI(*BB, MI, DL,
21524 TII->get(X86::FLDCW16m)), CWFrameIdx);
21526 // Restore the memory image of control word to original value
21527 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21530 // Get the X86 opcode to use.
21532 switch (MI->getOpcode()) {
21533 default: llvm_unreachable("illegal opcode!");
21534 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21535 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21536 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21537 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21538 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21539 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21540 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21541 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21542 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21546 MachineOperand &Op = MI->getOperand(0);
21548 AM.BaseType = X86AddressMode::RegBase;
21549 AM.Base.Reg = Op.getReg();
21551 AM.BaseType = X86AddressMode::FrameIndexBase;
21552 AM.Base.FrameIndex = Op.getIndex();
21554 Op = MI->getOperand(1);
21556 AM.Scale = Op.getImm();
21557 Op = MI->getOperand(2);
21559 AM.IndexReg = Op.getImm();
21560 Op = MI->getOperand(3);
21561 if (Op.isGlobal()) {
21562 AM.GV = Op.getGlobal();
21564 AM.Disp = Op.getImm();
21566 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21567 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21569 // Reload the original control word now.
21570 addFrameReference(BuildMI(*BB, MI, DL,
21571 TII->get(X86::FLDCW16m)), CWFrameIdx);
21573 MI->eraseFromParent(); // The pseudo instruction is gone now.
21576 // String/text processing lowering.
21577 case X86::PCMPISTRM128REG:
21578 case X86::VPCMPISTRM128REG:
21579 case X86::PCMPISTRM128MEM:
21580 case X86::VPCMPISTRM128MEM:
21581 case X86::PCMPESTRM128REG:
21582 case X86::VPCMPESTRM128REG:
21583 case X86::PCMPESTRM128MEM:
21584 case X86::VPCMPESTRM128MEM:
21585 assert(Subtarget->hasSSE42() &&
21586 "Target must have SSE4.2 or AVX features enabled");
21587 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21589 // String/text processing lowering.
21590 case X86::PCMPISTRIREG:
21591 case X86::VPCMPISTRIREG:
21592 case X86::PCMPISTRIMEM:
21593 case X86::VPCMPISTRIMEM:
21594 case X86::PCMPESTRIREG:
21595 case X86::VPCMPESTRIREG:
21596 case X86::PCMPESTRIMEM:
21597 case X86::VPCMPESTRIMEM:
21598 assert(Subtarget->hasSSE42() &&
21599 "Target must have SSE4.2 or AVX features enabled");
21600 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21602 // Thread synchronization.
21604 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21609 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21611 case X86::VASTART_SAVE_XMM_REGS:
21612 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21614 case X86::VAARG_64:
21615 return EmitVAARG64WithCustomInserter(MI, BB);
21617 case X86::EH_SjLj_SetJmp32:
21618 case X86::EH_SjLj_SetJmp64:
21619 return emitEHSjLjSetJmp(MI, BB);
21621 case X86::EH_SjLj_LongJmp32:
21622 case X86::EH_SjLj_LongJmp64:
21623 return emitEHSjLjLongJmp(MI, BB);
21625 case TargetOpcode::STATEPOINT:
21626 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21627 // this point in the process. We diverge later.
21628 return emitPatchPoint(MI, BB);
21630 case TargetOpcode::STACKMAP:
21631 case TargetOpcode::PATCHPOINT:
21632 return emitPatchPoint(MI, BB);
21634 case X86::VFMADDPDr213r:
21635 case X86::VFMADDPSr213r:
21636 case X86::VFMADDSDr213r:
21637 case X86::VFMADDSSr213r:
21638 case X86::VFMSUBPDr213r:
21639 case X86::VFMSUBPSr213r:
21640 case X86::VFMSUBSDr213r:
21641 case X86::VFMSUBSSr213r:
21642 case X86::VFNMADDPDr213r:
21643 case X86::VFNMADDPSr213r:
21644 case X86::VFNMADDSDr213r:
21645 case X86::VFNMADDSSr213r:
21646 case X86::VFNMSUBPDr213r:
21647 case X86::VFNMSUBPSr213r:
21648 case X86::VFNMSUBSDr213r:
21649 case X86::VFNMSUBSSr213r:
21650 case X86::VFMADDSUBPDr213r:
21651 case X86::VFMADDSUBPSr213r:
21652 case X86::VFMSUBADDPDr213r:
21653 case X86::VFMSUBADDPSr213r:
21654 case X86::VFMADDPDr213rY:
21655 case X86::VFMADDPSr213rY:
21656 case X86::VFMSUBPDr213rY:
21657 case X86::VFMSUBPSr213rY:
21658 case X86::VFNMADDPDr213rY:
21659 case X86::VFNMADDPSr213rY:
21660 case X86::VFNMSUBPDr213rY:
21661 case X86::VFNMSUBPSr213rY:
21662 case X86::VFMADDSUBPDr213rY:
21663 case X86::VFMADDSUBPSr213rY:
21664 case X86::VFMSUBADDPDr213rY:
21665 case X86::VFMSUBADDPSr213rY:
21666 return emitFMA3Instr(MI, BB);
21670 //===----------------------------------------------------------------------===//
21671 // X86 Optimization Hooks
21672 //===----------------------------------------------------------------------===//
21674 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21677 const SelectionDAG &DAG,
21678 unsigned Depth) const {
21679 unsigned BitWidth = KnownZero.getBitWidth();
21680 unsigned Opc = Op.getOpcode();
21681 assert((Opc >= ISD::BUILTIN_OP_END ||
21682 Opc == ISD::INTRINSIC_WO_CHAIN ||
21683 Opc == ISD::INTRINSIC_W_CHAIN ||
21684 Opc == ISD::INTRINSIC_VOID) &&
21685 "Should use MaskedValueIsZero if you don't know whether Op"
21686 " is a target node!");
21688 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21702 // These nodes' second result is a boolean.
21703 if (Op.getResNo() == 0)
21706 case X86ISD::SETCC:
21707 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21709 case ISD::INTRINSIC_WO_CHAIN: {
21710 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21711 unsigned NumLoBits = 0;
21714 case Intrinsic::x86_sse_movmsk_ps:
21715 case Intrinsic::x86_avx_movmsk_ps_256:
21716 case Intrinsic::x86_sse2_movmsk_pd:
21717 case Intrinsic::x86_avx_movmsk_pd_256:
21718 case Intrinsic::x86_mmx_pmovmskb:
21719 case Intrinsic::x86_sse2_pmovmskb_128:
21720 case Intrinsic::x86_avx2_pmovmskb: {
21721 // High bits of movmskp{s|d}, pmovmskb are known zero.
21723 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21724 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21725 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21726 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21727 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21728 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21729 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21730 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21732 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21741 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21743 const SelectionDAG &,
21744 unsigned Depth) const {
21745 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21746 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21747 return Op.getValueType().getScalarType().getSizeInBits();
21753 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21754 /// node is a GlobalAddress + offset.
21755 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21756 const GlobalValue* &GA,
21757 int64_t &Offset) const {
21758 if (N->getOpcode() == X86ISD::Wrapper) {
21759 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21760 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21761 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21765 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21768 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21769 /// same as extracting the high 128-bit part of 256-bit vector and then
21770 /// inserting the result into the low part of a new 256-bit vector
21771 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21772 EVT VT = SVOp->getValueType(0);
21773 unsigned NumElems = VT.getVectorNumElements();
21775 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21776 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21777 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21778 SVOp->getMaskElt(j) >= 0)
21784 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21785 /// same as extracting the low 128-bit part of 256-bit vector and then
21786 /// inserting the result into the high part of a new 256-bit vector
21787 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21788 EVT VT = SVOp->getValueType(0);
21789 unsigned NumElems = VT.getVectorNumElements();
21791 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21792 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21793 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21794 SVOp->getMaskElt(j) >= 0)
21800 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21801 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21802 TargetLowering::DAGCombinerInfo &DCI,
21803 const X86Subtarget* Subtarget) {
21805 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21806 SDValue V1 = SVOp->getOperand(0);
21807 SDValue V2 = SVOp->getOperand(1);
21808 EVT VT = SVOp->getValueType(0);
21809 unsigned NumElems = VT.getVectorNumElements();
21811 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21812 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21816 // V UNDEF BUILD_VECTOR UNDEF
21818 // CONCAT_VECTOR CONCAT_VECTOR
21821 // RESULT: V + zero extended
21823 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21824 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21825 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21828 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21831 // To match the shuffle mask, the first half of the mask should
21832 // be exactly the first vector, and all the rest a splat with the
21833 // first element of the second one.
21834 for (unsigned i = 0; i != NumElems/2; ++i)
21835 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21836 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21839 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21840 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21841 if (Ld->hasNUsesOfValue(1, 0)) {
21842 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21843 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21845 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21847 Ld->getPointerInfo(),
21848 Ld->getAlignment(),
21849 false/*isVolatile*/, true/*ReadMem*/,
21850 false/*WriteMem*/);
21852 // Make sure the newly-created LOAD is in the same position as Ld in
21853 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21854 // and update uses of Ld's output chain to use the TokenFactor.
21855 if (Ld->hasAnyUseOfValue(1)) {
21856 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21857 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21858 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21859 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21860 SDValue(ResNode.getNode(), 1));
21863 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21867 // Emit a zeroed vector and insert the desired subvector on its
21869 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21870 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21871 return DCI.CombineTo(N, InsV);
21874 //===--------------------------------------------------------------------===//
21875 // Combine some shuffles into subvector extracts and inserts:
21878 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21879 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21880 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21881 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21882 return DCI.CombineTo(N, InsV);
21885 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21886 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21887 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21888 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21889 return DCI.CombineTo(N, InsV);
21895 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21898 /// This is the leaf of the recursive combinine below. When we have found some
21899 /// chain of single-use x86 shuffle instructions and accumulated the combined
21900 /// shuffle mask represented by them, this will try to pattern match that mask
21901 /// into either a single instruction if there is a special purpose instruction
21902 /// for this operation, or into a PSHUFB instruction which is a fully general
21903 /// instruction but should only be used to replace chains over a certain depth.
21904 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21905 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21906 TargetLowering::DAGCombinerInfo &DCI,
21907 const X86Subtarget *Subtarget) {
21908 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21910 // Find the operand that enters the chain. Note that multiple uses are OK
21911 // here, we're not going to remove the operand we find.
21912 SDValue Input = Op.getOperand(0);
21913 while (Input.getOpcode() == ISD::BITCAST)
21914 Input = Input.getOperand(0);
21916 MVT VT = Input.getSimpleValueType();
21917 MVT RootVT = Root.getSimpleValueType();
21920 // Just remove no-op shuffle masks.
21921 if (Mask.size() == 1) {
21922 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21927 // Use the float domain if the operand type is a floating point type.
21928 bool FloatDomain = VT.isFloatingPoint();
21930 // For floating point shuffles, we don't have free copies in the shuffle
21931 // instructions or the ability to load as part of the instruction, so
21932 // canonicalize their shuffles to UNPCK or MOV variants.
21934 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21935 // vectors because it can have a load folded into it that UNPCK cannot. This
21936 // doesn't preclude something switching to the shorter encoding post-RA.
21938 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21939 bool Lo = Mask.equals(0, 0);
21942 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21943 // is no slower than UNPCKLPD but has the option to fold the input operand
21944 // into even an unaligned memory load.
21945 if (Lo && Subtarget->hasSSE3()) {
21946 Shuffle = X86ISD::MOVDDUP;
21947 ShuffleVT = MVT::v2f64;
21949 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21950 // than the UNPCK variants.
21951 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21952 ShuffleVT = MVT::v4f32;
21954 if (Depth == 1 && Root->getOpcode() == Shuffle)
21955 return false; // Nothing to do!
21956 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21957 DCI.AddToWorklist(Op.getNode());
21958 if (Shuffle == X86ISD::MOVDDUP)
21959 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21961 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21962 DCI.AddToWorklist(Op.getNode());
21963 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21967 if (Subtarget->hasSSE3() &&
21968 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21969 bool Lo = Mask.equals(0, 0, 2, 2);
21970 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21971 MVT ShuffleVT = MVT::v4f32;
21972 if (Depth == 1 && Root->getOpcode() == Shuffle)
21973 return false; // Nothing to do!
21974 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21975 DCI.AddToWorklist(Op.getNode());
21976 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21977 DCI.AddToWorklist(Op.getNode());
21978 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21982 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21983 bool Lo = Mask.equals(0, 0, 1, 1);
21984 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21985 MVT ShuffleVT = MVT::v4f32;
21986 if (Depth == 1 && Root->getOpcode() == Shuffle)
21987 return false; // Nothing to do!
21988 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21989 DCI.AddToWorklist(Op.getNode());
21990 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21991 DCI.AddToWorklist(Op.getNode());
21992 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21998 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21999 // variants as none of these have single-instruction variants that are
22000 // superior to the UNPCK formulation.
22001 if (!FloatDomain &&
22002 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
22003 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
22004 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
22005 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
22007 bool Lo = Mask[0] == 0;
22008 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22009 if (Depth == 1 && Root->getOpcode() == Shuffle)
22010 return false; // Nothing to do!
22012 switch (Mask.size()) {
22014 ShuffleVT = MVT::v8i16;
22017 ShuffleVT = MVT::v16i8;
22020 llvm_unreachable("Impossible mask size!");
22022 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
22023 DCI.AddToWorklist(Op.getNode());
22024 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22025 DCI.AddToWorklist(Op.getNode());
22026 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
22031 // Don't try to re-form single instruction chains under any circumstances now
22032 // that we've done encoding canonicalization for them.
22036 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22037 // can replace them with a single PSHUFB instruction profitably. Intel's
22038 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22039 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22040 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22041 SmallVector<SDValue, 16> PSHUFBMask;
22042 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
22043 int Ratio = 16 / Mask.size();
22044 for (unsigned i = 0; i < 16; ++i) {
22045 if (Mask[i / Ratio] == SM_SentinelUndef) {
22046 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22049 int M = Mask[i / Ratio] != SM_SentinelZero
22050 ? Ratio * Mask[i / Ratio] + i % Ratio
22052 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
22054 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
22055 DCI.AddToWorklist(Op.getNode());
22056 SDValue PSHUFBMaskOp =
22057 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
22058 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22059 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
22060 DCI.AddToWorklist(Op.getNode());
22061 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
22066 // Failed to find any combines.
22070 /// \brief Fully generic combining of x86 shuffle instructions.
22072 /// This should be the last combine run over the x86 shuffle instructions. Once
22073 /// they have been fully optimized, this will recursively consider all chains
22074 /// of single-use shuffle instructions, build a generic model of the cumulative
22075 /// shuffle operation, and check for simpler instructions which implement this
22076 /// operation. We use this primarily for two purposes:
22078 /// 1) Collapse generic shuffles to specialized single instructions when
22079 /// equivalent. In most cases, this is just an encoding size win, but
22080 /// sometimes we will collapse multiple generic shuffles into a single
22081 /// special-purpose shuffle.
22082 /// 2) Look for sequences of shuffle instructions with 3 or more total
22083 /// instructions, and replace them with the slightly more expensive SSSE3
22084 /// PSHUFB instruction if available. We do this as the last combining step
22085 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22086 /// a suitable short sequence of other instructions. The PHUFB will either
22087 /// use a register or have to read from memory and so is slightly (but only
22088 /// slightly) more expensive than the other shuffle instructions.
22090 /// Because this is inherently a quadratic operation (for each shuffle in
22091 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22092 /// This should never be an issue in practice as the shuffle lowering doesn't
22093 /// produce sequences of more than 8 instructions.
22095 /// FIXME: We will currently miss some cases where the redundant shuffling
22096 /// would simplify under the threshold for PSHUFB formation because of
22097 /// combine-ordering. To fix this, we should do the redundant instruction
22098 /// combining in this recursive walk.
22099 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22100 ArrayRef<int> RootMask,
22101 int Depth, bool HasPSHUFB,
22103 TargetLowering::DAGCombinerInfo &DCI,
22104 const X86Subtarget *Subtarget) {
22105 // Bound the depth of our recursive combine because this is ultimately
22106 // quadratic in nature.
22110 // Directly rip through bitcasts to find the underlying operand.
22111 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22112 Op = Op.getOperand(0);
22114 MVT VT = Op.getSimpleValueType();
22115 if (!VT.isVector())
22116 return false; // Bail if we hit a non-vector.
22117 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22118 // version should be added.
22119 if (VT.getSizeInBits() != 128)
22122 assert(Root.getSimpleValueType().isVector() &&
22123 "Shuffles operate on vector types!");
22124 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22125 "Can only combine shuffles of the same vector register size.");
22127 if (!isTargetShuffle(Op.getOpcode()))
22129 SmallVector<int, 16> OpMask;
22131 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22132 // We only can combine unary shuffles which we can decode the mask for.
22133 if (!HaveMask || !IsUnary)
22136 assert(VT.getVectorNumElements() == OpMask.size() &&
22137 "Different mask size from vector size!");
22138 assert(((RootMask.size() > OpMask.size() &&
22139 RootMask.size() % OpMask.size() == 0) ||
22140 (OpMask.size() > RootMask.size() &&
22141 OpMask.size() % RootMask.size() == 0) ||
22142 OpMask.size() == RootMask.size()) &&
22143 "The smaller number of elements must divide the larger.");
22144 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22145 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22146 assert(((RootRatio == 1 && OpRatio == 1) ||
22147 (RootRatio == 1) != (OpRatio == 1)) &&
22148 "Must not have a ratio for both incoming and op masks!");
22150 SmallVector<int, 16> Mask;
22151 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22153 // Merge this shuffle operation's mask into our accumulated mask. Note that
22154 // this shuffle's mask will be the first applied to the input, followed by the
22155 // root mask to get us all the way to the root value arrangement. The reason
22156 // for this order is that we are recursing up the operation chain.
22157 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22158 int RootIdx = i / RootRatio;
22159 if (RootMask[RootIdx] < 0) {
22160 // This is a zero or undef lane, we're done.
22161 Mask.push_back(RootMask[RootIdx]);
22165 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22166 int OpIdx = RootMaskedIdx / OpRatio;
22167 if (OpMask[OpIdx] < 0) {
22168 // The incoming lanes are zero or undef, it doesn't matter which ones we
22170 Mask.push_back(OpMask[OpIdx]);
22174 // Ok, we have non-zero lanes, map them through.
22175 Mask.push_back(OpMask[OpIdx] * OpRatio +
22176 RootMaskedIdx % OpRatio);
22179 // See if we can recurse into the operand to combine more things.
22180 switch (Op.getOpcode()) {
22181 case X86ISD::PSHUFB:
22183 case X86ISD::PSHUFD:
22184 case X86ISD::PSHUFHW:
22185 case X86ISD::PSHUFLW:
22186 if (Op.getOperand(0).hasOneUse() &&
22187 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22188 HasPSHUFB, DAG, DCI, Subtarget))
22192 case X86ISD::UNPCKL:
22193 case X86ISD::UNPCKH:
22194 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22195 // We can't check for single use, we have to check that this shuffle is the only user.
22196 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22197 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22198 HasPSHUFB, DAG, DCI, Subtarget))
22203 // Minor canonicalization of the accumulated shuffle mask to make it easier
22204 // to match below. All this does is detect masks with squential pairs of
22205 // elements, and shrink them to the half-width mask. It does this in a loop
22206 // so it will reduce the size of the mask to the minimal width mask which
22207 // performs an equivalent shuffle.
22208 SmallVector<int, 16> WidenedMask;
22209 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22210 Mask = std::move(WidenedMask);
22211 WidenedMask.clear();
22214 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22218 /// \brief Get the PSHUF-style mask from PSHUF node.
22220 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22221 /// PSHUF-style masks that can be reused with such instructions.
22222 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22223 SmallVector<int, 4> Mask;
22225 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22229 switch (N.getOpcode()) {
22230 case X86ISD::PSHUFD:
22232 case X86ISD::PSHUFLW:
22235 case X86ISD::PSHUFHW:
22236 Mask.erase(Mask.begin(), Mask.begin() + 4);
22237 for (int &M : Mask)
22241 llvm_unreachable("No valid shuffle instruction found!");
22245 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22247 /// We walk up the chain and look for a combinable shuffle, skipping over
22248 /// shuffles that we could hoist this shuffle's transformation past without
22249 /// altering anything.
22251 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22253 TargetLowering::DAGCombinerInfo &DCI) {
22254 assert(N.getOpcode() == X86ISD::PSHUFD &&
22255 "Called with something other than an x86 128-bit half shuffle!");
22258 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22259 // of the shuffles in the chain so that we can form a fresh chain to replace
22261 SmallVector<SDValue, 8> Chain;
22262 SDValue V = N.getOperand(0);
22263 for (; V.hasOneUse(); V = V.getOperand(0)) {
22264 switch (V.getOpcode()) {
22266 return SDValue(); // Nothing combined!
22269 // Skip bitcasts as we always know the type for the target specific
22273 case X86ISD::PSHUFD:
22274 // Found another dword shuffle.
22277 case X86ISD::PSHUFLW:
22278 // Check that the low words (being shuffled) are the identity in the
22279 // dword shuffle, and the high words are self-contained.
22280 if (Mask[0] != 0 || Mask[1] != 1 ||
22281 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22284 Chain.push_back(V);
22287 case X86ISD::PSHUFHW:
22288 // Check that the high words (being shuffled) are the identity in the
22289 // dword shuffle, and the low words are self-contained.
22290 if (Mask[2] != 2 || Mask[3] != 3 ||
22291 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22294 Chain.push_back(V);
22297 case X86ISD::UNPCKL:
22298 case X86ISD::UNPCKH:
22299 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22300 // shuffle into a preceding word shuffle.
22301 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22304 // Search for a half-shuffle which we can combine with.
22305 unsigned CombineOp =
22306 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22307 if (V.getOperand(0) != V.getOperand(1) ||
22308 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22310 Chain.push_back(V);
22311 V = V.getOperand(0);
22313 switch (V.getOpcode()) {
22315 return SDValue(); // Nothing to combine.
22317 case X86ISD::PSHUFLW:
22318 case X86ISD::PSHUFHW:
22319 if (V.getOpcode() == CombineOp)
22322 Chain.push_back(V);
22326 V = V.getOperand(0);
22330 } while (V.hasOneUse());
22333 // Break out of the loop if we break out of the switch.
22337 if (!V.hasOneUse())
22338 // We fell out of the loop without finding a viable combining instruction.
22341 // Merge this node's mask and our incoming mask.
22342 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22343 for (int &M : Mask)
22345 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22346 getV4X86ShuffleImm8ForMask(Mask, DAG));
22348 // Rebuild the chain around this new shuffle.
22349 while (!Chain.empty()) {
22350 SDValue W = Chain.pop_back_val();
22352 if (V.getValueType() != W.getOperand(0).getValueType())
22353 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22355 switch (W.getOpcode()) {
22357 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22359 case X86ISD::UNPCKL:
22360 case X86ISD::UNPCKH:
22361 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22364 case X86ISD::PSHUFD:
22365 case X86ISD::PSHUFLW:
22366 case X86ISD::PSHUFHW:
22367 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22371 if (V.getValueType() != N.getValueType())
22372 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22374 // Return the new chain to replace N.
22378 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22380 /// We walk up the chain, skipping shuffles of the other half and looking
22381 /// through shuffles which switch halves trying to find a shuffle of the same
22382 /// pair of dwords.
22383 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22385 TargetLowering::DAGCombinerInfo &DCI) {
22387 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22388 "Called with something other than an x86 128-bit half shuffle!");
22390 unsigned CombineOpcode = N.getOpcode();
22392 // Walk up a single-use chain looking for a combinable shuffle.
22393 SDValue V = N.getOperand(0);
22394 for (; V.hasOneUse(); V = V.getOperand(0)) {
22395 switch (V.getOpcode()) {
22397 return false; // Nothing combined!
22400 // Skip bitcasts as we always know the type for the target specific
22404 case X86ISD::PSHUFLW:
22405 case X86ISD::PSHUFHW:
22406 if (V.getOpcode() == CombineOpcode)
22409 // Other-half shuffles are no-ops.
22412 // Break out of the loop if we break out of the switch.
22416 if (!V.hasOneUse())
22417 // We fell out of the loop without finding a viable combining instruction.
22420 // Combine away the bottom node as its shuffle will be accumulated into
22421 // a preceding shuffle.
22422 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22424 // Record the old value.
22427 // Merge this node's mask and our incoming mask (adjusted to account for all
22428 // the pshufd instructions encountered).
22429 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22430 for (int &M : Mask)
22432 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22433 getV4X86ShuffleImm8ForMask(Mask, DAG));
22435 // Check that the shuffles didn't cancel each other out. If not, we need to
22436 // combine to the new one.
22438 // Replace the combinable shuffle with the combined one, updating all users
22439 // so that we re-evaluate the chain here.
22440 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22445 /// \brief Try to combine x86 target specific shuffles.
22446 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22447 TargetLowering::DAGCombinerInfo &DCI,
22448 const X86Subtarget *Subtarget) {
22450 MVT VT = N.getSimpleValueType();
22451 SmallVector<int, 4> Mask;
22453 switch (N.getOpcode()) {
22454 case X86ISD::PSHUFD:
22455 case X86ISD::PSHUFLW:
22456 case X86ISD::PSHUFHW:
22457 Mask = getPSHUFShuffleMask(N);
22458 assert(Mask.size() == 4);
22464 // Nuke no-op shuffles that show up after combining.
22465 if (isNoopShuffleMask(Mask))
22466 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22468 // Look for simplifications involving one or two shuffle instructions.
22469 SDValue V = N.getOperand(0);
22470 switch (N.getOpcode()) {
22473 case X86ISD::PSHUFLW:
22474 case X86ISD::PSHUFHW:
22475 assert(VT == MVT::v8i16);
22478 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22479 return SDValue(); // We combined away this shuffle, so we're done.
22481 // See if this reduces to a PSHUFD which is no more expensive and can
22482 // combine with more operations. Note that it has to at least flip the
22483 // dwords as otherwise it would have been removed as a no-op.
22484 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22485 int DMask[] = {0, 1, 2, 3};
22486 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22487 DMask[DOffset + 0] = DOffset + 1;
22488 DMask[DOffset + 1] = DOffset + 0;
22489 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22490 DCI.AddToWorklist(V.getNode());
22491 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22492 getV4X86ShuffleImm8ForMask(DMask, DAG));
22493 DCI.AddToWorklist(V.getNode());
22494 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22497 // Look for shuffle patterns which can be implemented as a single unpack.
22498 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22499 // only works when we have a PSHUFD followed by two half-shuffles.
22500 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22501 (V.getOpcode() == X86ISD::PSHUFLW ||
22502 V.getOpcode() == X86ISD::PSHUFHW) &&
22503 V.getOpcode() != N.getOpcode() &&
22505 SDValue D = V.getOperand(0);
22506 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22507 D = D.getOperand(0);
22508 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22509 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22510 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22511 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22512 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22514 for (int i = 0; i < 4; ++i) {
22515 WordMask[i + NOffset] = Mask[i] + NOffset;
22516 WordMask[i + VOffset] = VMask[i] + VOffset;
22518 // Map the word mask through the DWord mask.
22520 for (int i = 0; i < 8; ++i)
22521 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22522 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22523 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22524 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22525 std::begin(UnpackLoMask)) ||
22526 std::equal(std::begin(MappedMask), std::end(MappedMask),
22527 std::begin(UnpackHiMask))) {
22528 // We can replace all three shuffles with an unpack.
22529 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22530 DCI.AddToWorklist(V.getNode());
22531 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22533 DL, MVT::v8i16, V, V);
22540 case X86ISD::PSHUFD:
22541 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22550 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22552 /// We combine this directly on the abstract vector shuffle nodes so it is
22553 /// easier to generically match. We also insert dummy vector shuffle nodes for
22554 /// the operands which explicitly discard the lanes which are unused by this
22555 /// operation to try to flow through the rest of the combiner the fact that
22556 /// they're unused.
22557 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22559 EVT VT = N->getValueType(0);
22561 // We only handle target-independent shuffles.
22562 // FIXME: It would be easy and harmless to use the target shuffle mask
22563 // extraction tool to support more.
22564 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22567 auto *SVN = cast<ShuffleVectorSDNode>(N);
22568 ArrayRef<int> Mask = SVN->getMask();
22569 SDValue V1 = N->getOperand(0);
22570 SDValue V2 = N->getOperand(1);
22572 // We require the first shuffle operand to be the SUB node, and the second to
22573 // be the ADD node.
22574 // FIXME: We should support the commuted patterns.
22575 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22578 // If there are other uses of these operations we can't fold them.
22579 if (!V1->hasOneUse() || !V2->hasOneUse())
22582 // Ensure that both operations have the same operands. Note that we can
22583 // commute the FADD operands.
22584 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22585 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22586 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22589 // We're looking for blends between FADD and FSUB nodes. We insist on these
22590 // nodes being lined up in a specific expected pattern.
22591 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22592 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22593 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22596 // Only specific types are legal at this point, assert so we notice if and
22597 // when these change.
22598 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22599 VT == MVT::v4f64) &&
22600 "Unknown vector type encountered!");
22602 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22605 /// PerformShuffleCombine - Performs several different shuffle combines.
22606 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22607 TargetLowering::DAGCombinerInfo &DCI,
22608 const X86Subtarget *Subtarget) {
22610 SDValue N0 = N->getOperand(0);
22611 SDValue N1 = N->getOperand(1);
22612 EVT VT = N->getValueType(0);
22614 // Don't create instructions with illegal types after legalize types has run.
22615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22616 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22619 // If we have legalized the vector types, look for blends of FADD and FSUB
22620 // nodes that we can fuse into an ADDSUB node.
22621 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22622 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22625 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22626 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22627 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22628 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22630 // During Type Legalization, when promoting illegal vector types,
22631 // the backend might introduce new shuffle dag nodes and bitcasts.
22633 // This code performs the following transformation:
22634 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22635 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22637 // We do this only if both the bitcast and the BINOP dag nodes have
22638 // one use. Also, perform this transformation only if the new binary
22639 // operation is legal. This is to avoid introducing dag nodes that
22640 // potentially need to be further expanded (or custom lowered) into a
22641 // less optimal sequence of dag nodes.
22642 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22643 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22644 N0.getOpcode() == ISD::BITCAST) {
22645 SDValue BC0 = N0.getOperand(0);
22646 EVT SVT = BC0.getValueType();
22647 unsigned Opcode = BC0.getOpcode();
22648 unsigned NumElts = VT.getVectorNumElements();
22650 if (BC0.hasOneUse() && SVT.isVector() &&
22651 SVT.getVectorNumElements() * 2 == NumElts &&
22652 TLI.isOperationLegal(Opcode, VT)) {
22653 bool CanFold = false;
22665 unsigned SVTNumElts = SVT.getVectorNumElements();
22666 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22667 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22668 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22669 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22670 CanFold = SVOp->getMaskElt(i) < 0;
22673 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22674 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22675 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22676 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22681 // Only handle 128 wide vector from here on.
22682 if (!VT.is128BitVector())
22685 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22686 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22687 // consecutive, non-overlapping, and in the right order.
22688 SmallVector<SDValue, 16> Elts;
22689 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22690 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22692 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22696 if (isTargetShuffle(N->getOpcode())) {
22698 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22699 if (Shuffle.getNode())
22702 // Try recursively combining arbitrary sequences of x86 shuffle
22703 // instructions into higher-order shuffles. We do this after combining
22704 // specific PSHUF instruction sequences into their minimal form so that we
22705 // can evaluate how many specialized shuffle instructions are involved in
22706 // a particular chain.
22707 SmallVector<int, 1> NonceMask; // Just a placeholder.
22708 NonceMask.push_back(0);
22709 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22710 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22712 return SDValue(); // This routine will use CombineTo to replace N.
22718 /// PerformTruncateCombine - Converts truncate operation to
22719 /// a sequence of vector shuffle operations.
22720 /// It is possible when we truncate 256-bit vector to 128-bit vector
22721 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22722 TargetLowering::DAGCombinerInfo &DCI,
22723 const X86Subtarget *Subtarget) {
22727 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22728 /// specific shuffle of a load can be folded into a single element load.
22729 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22730 /// shuffles have been custom lowered so we need to handle those here.
22731 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22732 TargetLowering::DAGCombinerInfo &DCI) {
22733 if (DCI.isBeforeLegalizeOps())
22736 SDValue InVec = N->getOperand(0);
22737 SDValue EltNo = N->getOperand(1);
22739 if (!isa<ConstantSDNode>(EltNo))
22742 EVT OriginalVT = InVec.getValueType();
22744 if (InVec.getOpcode() == ISD::BITCAST) {
22745 // Don't duplicate a load with other uses.
22746 if (!InVec.hasOneUse())
22748 EVT BCVT = InVec.getOperand(0).getValueType();
22749 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22751 InVec = InVec.getOperand(0);
22754 EVT CurrentVT = InVec.getValueType();
22756 if (!isTargetShuffle(InVec.getOpcode()))
22759 // Don't duplicate a load with other uses.
22760 if (!InVec.hasOneUse())
22763 SmallVector<int, 16> ShuffleMask;
22765 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22766 ShuffleMask, UnaryShuffle))
22769 // Select the input vector, guarding against out of range extract vector.
22770 unsigned NumElems = CurrentVT.getVectorNumElements();
22771 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22772 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22773 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22774 : InVec.getOperand(1);
22776 // If inputs to shuffle are the same for both ops, then allow 2 uses
22777 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22779 if (LdNode.getOpcode() == ISD::BITCAST) {
22780 // Don't duplicate a load with other uses.
22781 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22784 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22785 LdNode = LdNode.getOperand(0);
22788 if (!ISD::isNormalLoad(LdNode.getNode()))
22791 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22793 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22796 EVT EltVT = N->getValueType(0);
22797 // If there's a bitcast before the shuffle, check if the load type and
22798 // alignment is valid.
22799 unsigned Align = LN0->getAlignment();
22800 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22801 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22802 EltVT.getTypeForEVT(*DAG.getContext()));
22804 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22807 // All checks match so transform back to vector_shuffle so that DAG combiner
22808 // can finish the job
22811 // Create shuffle node taking into account the case that its a unary shuffle
22812 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22813 : InVec.getOperand(1);
22814 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22815 InVec.getOperand(0), Shuffle,
22817 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22818 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22822 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22823 /// generation and convert it from being a bunch of shuffles and extracts
22824 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22825 /// storing the value and loading scalars back, while for x64 we should
22826 /// use 64-bit extracts and shifts.
22827 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22828 TargetLowering::DAGCombinerInfo &DCI) {
22829 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22830 if (NewOp.getNode())
22833 SDValue InputVector = N->getOperand(0);
22835 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22836 // from mmx to v2i32 has a single usage.
22837 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22838 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22839 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22840 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22841 N->getValueType(0),
22842 InputVector.getNode()->getOperand(0));
22844 // Only operate on vectors of 4 elements, where the alternative shuffling
22845 // gets to be more expensive.
22846 if (InputVector.getValueType() != MVT::v4i32)
22849 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22850 // single use which is a sign-extend or zero-extend, and all elements are
22852 SmallVector<SDNode *, 4> Uses;
22853 unsigned ExtractedElements = 0;
22854 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22855 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22856 if (UI.getUse().getResNo() != InputVector.getResNo())
22859 SDNode *Extract = *UI;
22860 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22863 if (Extract->getValueType(0) != MVT::i32)
22865 if (!Extract->hasOneUse())
22867 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22868 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22870 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22873 // Record which element was extracted.
22874 ExtractedElements |=
22875 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22877 Uses.push_back(Extract);
22880 // If not all the elements were used, this may not be worthwhile.
22881 if (ExtractedElements != 15)
22884 // Ok, we've now decided to do the transformation.
22885 // If 64-bit shifts are legal, use the extract-shift sequence,
22886 // otherwise bounce the vector off the cache.
22887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22889 SDLoc dl(InputVector);
22891 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22892 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22893 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22894 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22895 DAG.getConstant(0, VecIdxTy));
22896 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22897 DAG.getConstant(1, VecIdxTy));
22899 SDValue ShAmt = DAG.getConstant(32,
22900 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22901 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22902 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22903 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22904 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22905 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22906 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22908 // Store the value to a temporary stack slot.
22909 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22910 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22911 MachinePointerInfo(), false, false, 0);
22913 EVT ElementType = InputVector.getValueType().getVectorElementType();
22914 unsigned EltSize = ElementType.getSizeInBits() / 8;
22916 // Replace each use (extract) with a load of the appropriate element.
22917 for (unsigned i = 0; i < 4; ++i) {
22918 uint64_t Offset = EltSize * i;
22919 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22921 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22922 StackPtr, OffsetVal);
22924 // Load the scalar.
22925 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22926 ScalarAddr, MachinePointerInfo(),
22927 false, false, false, 0);
22932 // Replace the extracts
22933 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22934 UE = Uses.end(); UI != UE; ++UI) {
22935 SDNode *Extract = *UI;
22937 SDValue Idx = Extract->getOperand(1);
22938 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22939 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22942 // The replacement was made in place; don't return anything.
22946 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22947 static std::pair<unsigned, bool>
22948 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22949 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22950 if (!VT.isVector())
22951 return std::make_pair(0, false);
22953 bool NeedSplit = false;
22954 switch (VT.getSimpleVT().SimpleTy) {
22955 default: return std::make_pair(0, false);
22958 if (!Subtarget->hasVLX())
22959 return std::make_pair(0, false);
22963 if (!Subtarget->hasBWI())
22964 return std::make_pair(0, false);
22968 if (!Subtarget->hasAVX512())
22969 return std::make_pair(0, false);
22974 if (!Subtarget->hasAVX2())
22976 if (!Subtarget->hasAVX())
22977 return std::make_pair(0, false);
22982 if (!Subtarget->hasSSE2())
22983 return std::make_pair(0, false);
22986 // SSE2 has only a small subset of the operations.
22987 bool hasUnsigned = Subtarget->hasSSE41() ||
22988 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22989 bool hasSigned = Subtarget->hasSSE41() ||
22990 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22992 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22995 // Check for x CC y ? x : y.
22996 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22997 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23002 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
23005 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
23008 Opc = hasSigned ? X86ISD::SMIN : 0; break;
23011 Opc = hasSigned ? X86ISD::SMAX : 0; break;
23013 // Check for x CC y ? y : x -- a min/max with reversed arms.
23014 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23015 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23020 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
23023 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
23026 Opc = hasSigned ? X86ISD::SMAX : 0; break;
23029 Opc = hasSigned ? X86ISD::SMIN : 0; break;
23033 return std::make_pair(Opc, NeedSplit);
23037 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23038 const X86Subtarget *Subtarget) {
23040 SDValue Cond = N->getOperand(0);
23041 SDValue LHS = N->getOperand(1);
23042 SDValue RHS = N->getOperand(2);
23044 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23045 SDValue CondSrc = Cond->getOperand(0);
23046 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23047 Cond = CondSrc->getOperand(0);
23050 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23053 // A vselect where all conditions and data are constants can be optimized into
23054 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23055 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23056 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23059 unsigned MaskValue = 0;
23060 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23063 MVT VT = N->getSimpleValueType(0);
23064 unsigned NumElems = VT.getVectorNumElements();
23065 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23066 for (unsigned i = 0; i < NumElems; ++i) {
23067 // Be sure we emit undef where we can.
23068 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23069 ShuffleMask[i] = -1;
23071 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23074 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23075 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23077 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23080 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23082 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23083 TargetLowering::DAGCombinerInfo &DCI,
23084 const X86Subtarget *Subtarget) {
23086 SDValue Cond = N->getOperand(0);
23087 // Get the LHS/RHS of the select.
23088 SDValue LHS = N->getOperand(1);
23089 SDValue RHS = N->getOperand(2);
23090 EVT VT = LHS.getValueType();
23091 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23093 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23094 // instructions match the semantics of the common C idiom x<y?x:y but not
23095 // x<=y?x:y, because of how they handle negative zero (which can be
23096 // ignored in unsafe-math mode).
23097 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23098 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23099 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23100 (Subtarget->hasSSE2() ||
23101 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23102 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23104 unsigned Opcode = 0;
23105 // Check for x CC y ? x : y.
23106 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23107 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23111 // Converting this to a min would handle NaNs incorrectly, and swapping
23112 // the operands would cause it to handle comparisons between positive
23113 // and negative zero incorrectly.
23114 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23115 if (!DAG.getTarget().Options.UnsafeFPMath &&
23116 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23118 std::swap(LHS, RHS);
23120 Opcode = X86ISD::FMIN;
23123 // Converting this to a min would handle comparisons between positive
23124 // and negative zero incorrectly.
23125 if (!DAG.getTarget().Options.UnsafeFPMath &&
23126 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23128 Opcode = X86ISD::FMIN;
23131 // Converting this to a min would handle both negative zeros and NaNs
23132 // incorrectly, but we can swap the operands to fix both.
23133 std::swap(LHS, RHS);
23137 Opcode = X86ISD::FMIN;
23141 // Converting this to a max would handle comparisons between positive
23142 // and negative zero incorrectly.
23143 if (!DAG.getTarget().Options.UnsafeFPMath &&
23144 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23146 Opcode = X86ISD::FMAX;
23149 // Converting this to a max would handle NaNs incorrectly, and swapping
23150 // the operands would cause it to handle comparisons between positive
23151 // and negative zero incorrectly.
23152 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23153 if (!DAG.getTarget().Options.UnsafeFPMath &&
23154 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23156 std::swap(LHS, RHS);
23158 Opcode = X86ISD::FMAX;
23161 // Converting this to a max would handle both negative zeros and NaNs
23162 // incorrectly, but we can swap the operands to fix both.
23163 std::swap(LHS, RHS);
23167 Opcode = X86ISD::FMAX;
23170 // Check for x CC y ? y : x -- a min/max with reversed arms.
23171 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23172 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23176 // Converting this to a min would handle comparisons between positive
23177 // and negative zero incorrectly, and swapping the operands would
23178 // cause it to handle NaNs incorrectly.
23179 if (!DAG.getTarget().Options.UnsafeFPMath &&
23180 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23181 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23183 std::swap(LHS, RHS);
23185 Opcode = X86ISD::FMIN;
23188 // Converting this to a min would handle NaNs incorrectly.
23189 if (!DAG.getTarget().Options.UnsafeFPMath &&
23190 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23192 Opcode = X86ISD::FMIN;
23195 // Converting this to a min would handle both negative zeros and NaNs
23196 // incorrectly, but we can swap the operands to fix both.
23197 std::swap(LHS, RHS);
23201 Opcode = X86ISD::FMIN;
23205 // Converting this to a max would handle NaNs incorrectly.
23206 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23208 Opcode = X86ISD::FMAX;
23211 // Converting this to a max would handle comparisons between positive
23212 // and negative zero incorrectly, and swapping the operands would
23213 // cause it to handle NaNs incorrectly.
23214 if (!DAG.getTarget().Options.UnsafeFPMath &&
23215 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23216 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23218 std::swap(LHS, RHS);
23220 Opcode = X86ISD::FMAX;
23223 // Converting this to a max would handle both negative zeros and NaNs
23224 // incorrectly, but we can swap the operands to fix both.
23225 std::swap(LHS, RHS);
23229 Opcode = X86ISD::FMAX;
23235 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23238 EVT CondVT = Cond.getValueType();
23239 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23240 CondVT.getVectorElementType() == MVT::i1) {
23241 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23242 // lowering on KNL. In this case we convert it to
23243 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23244 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23245 // Since SKX these selects have a proper lowering.
23246 EVT OpVT = LHS.getValueType();
23247 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23248 (OpVT.getVectorElementType() == MVT::i8 ||
23249 OpVT.getVectorElementType() == MVT::i16) &&
23250 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23251 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23252 DCI.AddToWorklist(Cond.getNode());
23253 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23256 // If this is a select between two integer constants, try to do some
23258 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23259 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23260 // Don't do this for crazy integer types.
23261 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23262 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23263 // so that TrueC (the true value) is larger than FalseC.
23264 bool NeedsCondInvert = false;
23266 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23267 // Efficiently invertible.
23268 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23269 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23270 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23271 NeedsCondInvert = true;
23272 std::swap(TrueC, FalseC);
23275 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23276 if (FalseC->getAPIntValue() == 0 &&
23277 TrueC->getAPIntValue().isPowerOf2()) {
23278 if (NeedsCondInvert) // Invert the condition if needed.
23279 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23280 DAG.getConstant(1, Cond.getValueType()));
23282 // Zero extend the condition if needed.
23283 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23285 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23286 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23287 DAG.getConstant(ShAmt, MVT::i8));
23290 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23291 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23292 if (NeedsCondInvert) // Invert the condition if needed.
23293 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23294 DAG.getConstant(1, Cond.getValueType()));
23296 // Zero extend the condition if needed.
23297 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23298 FalseC->getValueType(0), Cond);
23299 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23300 SDValue(FalseC, 0));
23303 // Optimize cases that will turn into an LEA instruction. This requires
23304 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23305 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23306 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23307 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23309 bool isFastMultiplier = false;
23311 switch ((unsigned char)Diff) {
23313 case 1: // result = add base, cond
23314 case 2: // result = lea base( , cond*2)
23315 case 3: // result = lea base(cond, cond*2)
23316 case 4: // result = lea base( , cond*4)
23317 case 5: // result = lea base(cond, cond*4)
23318 case 8: // result = lea base( , cond*8)
23319 case 9: // result = lea base(cond, cond*8)
23320 isFastMultiplier = true;
23325 if (isFastMultiplier) {
23326 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23327 if (NeedsCondInvert) // Invert the condition if needed.
23328 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23329 DAG.getConstant(1, Cond.getValueType()));
23331 // Zero extend the condition if needed.
23332 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23334 // Scale the condition by the difference.
23336 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23337 DAG.getConstant(Diff, Cond.getValueType()));
23339 // Add the base if non-zero.
23340 if (FalseC->getAPIntValue() != 0)
23341 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23342 SDValue(FalseC, 0));
23349 // Canonicalize max and min:
23350 // (x > y) ? x : y -> (x >= y) ? x : y
23351 // (x < y) ? x : y -> (x <= y) ? x : y
23352 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23353 // the need for an extra compare
23354 // against zero. e.g.
23355 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23357 // testl %edi, %edi
23359 // cmovgl %edi, %eax
23363 // cmovsl %eax, %edi
23364 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23365 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23366 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23367 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23372 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23373 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23374 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23375 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23380 // Early exit check
23381 if (!TLI.isTypeLegal(VT))
23384 // Match VSELECTs into subs with unsigned saturation.
23385 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23386 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23387 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23388 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23389 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23391 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23392 // left side invert the predicate to simplify logic below.
23394 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23396 CC = ISD::getSetCCInverse(CC, true);
23397 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23401 if (Other.getNode() && Other->getNumOperands() == 2 &&
23402 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23403 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23404 SDValue CondRHS = Cond->getOperand(1);
23406 // Look for a general sub with unsigned saturation first.
23407 // x >= y ? x-y : 0 --> subus x, y
23408 // x > y ? x-y : 0 --> subus x, y
23409 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23410 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23411 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23413 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23414 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23415 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23416 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23417 // If the RHS is a constant we have to reverse the const
23418 // canonicalization.
23419 // x > C-1 ? x+-C : 0 --> subus x, C
23420 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23421 CondRHSConst->getAPIntValue() ==
23422 (-OpRHSConst->getAPIntValue() - 1))
23423 return DAG.getNode(
23424 X86ISD::SUBUS, DL, VT, OpLHS,
23425 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23427 // Another special case: If C was a sign bit, the sub has been
23428 // canonicalized into a xor.
23429 // FIXME: Would it be better to use computeKnownBits to determine
23430 // whether it's safe to decanonicalize the xor?
23431 // x s< 0 ? x^C : 0 --> subus x, C
23432 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23433 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23434 OpRHSConst->getAPIntValue().isSignBit())
23435 // Note that we have to rebuild the RHS constant here to ensure we
23436 // don't rely on particular values of undef lanes.
23437 return DAG.getNode(
23438 X86ISD::SUBUS, DL, VT, OpLHS,
23439 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23444 // Try to match a min/max vector operation.
23445 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23446 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23447 unsigned Opc = ret.first;
23448 bool NeedSplit = ret.second;
23450 if (Opc && NeedSplit) {
23451 unsigned NumElems = VT.getVectorNumElements();
23452 // Extract the LHS vectors
23453 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23454 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23456 // Extract the RHS vectors
23457 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23458 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23460 // Create min/max for each subvector
23461 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23462 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23464 // Merge the result
23465 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23467 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23470 // Simplify vector selection if condition value type matches vselect
23472 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23473 assert(Cond.getValueType().isVector() &&
23474 "vector select expects a vector selector!");
23476 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23477 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23479 // Try invert the condition if true value is not all 1s and false value
23481 if (!TValIsAllOnes && !FValIsAllZeros &&
23482 // Check if the selector will be produced by CMPP*/PCMP*
23483 Cond.getOpcode() == ISD::SETCC &&
23484 // Check if SETCC has already been promoted
23485 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23486 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23487 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23489 if (TValIsAllZeros || FValIsAllOnes) {
23490 SDValue CC = Cond.getOperand(2);
23491 ISD::CondCode NewCC =
23492 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23493 Cond.getOperand(0).getValueType().isInteger());
23494 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23495 std::swap(LHS, RHS);
23496 TValIsAllOnes = FValIsAllOnes;
23497 FValIsAllZeros = TValIsAllZeros;
23501 if (TValIsAllOnes || FValIsAllZeros) {
23504 if (TValIsAllOnes && FValIsAllZeros)
23506 else if (TValIsAllOnes)
23507 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23508 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23509 else if (FValIsAllZeros)
23510 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23511 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23513 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23517 // If we know that this node is legal then we know that it is going to be
23518 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23519 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23520 // to simplify previous instructions.
23521 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23522 !DCI.isBeforeLegalize() &&
23523 // We explicitly check against v8i16 and v16i16 because, although
23524 // they're marked as Custom, they might only be legal when Cond is a
23525 // build_vector of constants. This will be taken care in a later
23527 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23528 VT != MVT::v8i16) &&
23529 // Don't optimize vector of constants. Those are handled by
23530 // the generic code and all the bits must be properly set for
23531 // the generic optimizer.
23532 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23533 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23535 // Don't optimize vector selects that map to mask-registers.
23539 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23540 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23542 APInt KnownZero, KnownOne;
23543 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23544 DCI.isBeforeLegalizeOps());
23545 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23546 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23548 // If we changed the computation somewhere in the DAG, this change
23549 // will affect all users of Cond.
23550 // Make sure it is fine and update all the nodes so that we do not
23551 // use the generic VSELECT anymore. Otherwise, we may perform
23552 // wrong optimizations as we messed up with the actual expectation
23553 // for the vector boolean values.
23554 if (Cond != TLO.Old) {
23555 // Check all uses of that condition operand to check whether it will be
23556 // consumed by non-BLEND instructions, which may depend on all bits are
23558 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23560 if (I->getOpcode() != ISD::VSELECT)
23561 // TODO: Add other opcodes eventually lowered into BLEND.
23564 // Update all the users of the condition, before committing the change,
23565 // so that the VSELECT optimizations that expect the correct vector
23566 // boolean value will not be triggered.
23567 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23569 DAG.ReplaceAllUsesOfValueWith(
23571 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23572 Cond, I->getOperand(1), I->getOperand(2)));
23573 DCI.CommitTargetLoweringOpt(TLO);
23576 // At this point, only Cond is changed. Change the condition
23577 // just for N to keep the opportunity to optimize all other
23578 // users their own way.
23579 DAG.ReplaceAllUsesOfValueWith(
23581 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23582 TLO.New, N->getOperand(1), N->getOperand(2)));
23587 // We should generate an X86ISD::BLENDI from a vselect if its argument
23588 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23589 // constants. This specific pattern gets generated when we split a
23590 // selector for a 512 bit vector in a machine without AVX512 (but with
23591 // 256-bit vectors), during legalization:
23593 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23595 // Iff we find this pattern and the build_vectors are built from
23596 // constants, we translate the vselect into a shuffle_vector that we
23597 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23598 if ((N->getOpcode() == ISD::VSELECT ||
23599 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23600 !DCI.isBeforeLegalize()) {
23601 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23602 if (Shuffle.getNode())
23609 // Check whether a boolean test is testing a boolean value generated by
23610 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23613 // Simplify the following patterns:
23614 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23615 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23616 // to (Op EFLAGS Cond)
23618 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23619 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23620 // to (Op EFLAGS !Cond)
23622 // where Op could be BRCOND or CMOV.
23624 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23625 // Quit if not CMP and SUB with its value result used.
23626 if (Cmp.getOpcode() != X86ISD::CMP &&
23627 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23630 // Quit if not used as a boolean value.
23631 if (CC != X86::COND_E && CC != X86::COND_NE)
23634 // Check CMP operands. One of them should be 0 or 1 and the other should be
23635 // an SetCC or extended from it.
23636 SDValue Op1 = Cmp.getOperand(0);
23637 SDValue Op2 = Cmp.getOperand(1);
23640 const ConstantSDNode* C = nullptr;
23641 bool needOppositeCond = (CC == X86::COND_E);
23642 bool checkAgainstTrue = false; // Is it a comparison against 1?
23644 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23646 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23648 else // Quit if all operands are not constants.
23651 if (C->getZExtValue() == 1) {
23652 needOppositeCond = !needOppositeCond;
23653 checkAgainstTrue = true;
23654 } else if (C->getZExtValue() != 0)
23655 // Quit if the constant is neither 0 or 1.
23658 bool truncatedToBoolWithAnd = false;
23659 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23660 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23661 SetCC.getOpcode() == ISD::TRUNCATE ||
23662 SetCC.getOpcode() == ISD::AND) {
23663 if (SetCC.getOpcode() == ISD::AND) {
23665 ConstantSDNode *CS;
23666 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23667 CS->getZExtValue() == 1)
23669 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23670 CS->getZExtValue() == 1)
23674 SetCC = SetCC.getOperand(OpIdx);
23675 truncatedToBoolWithAnd = true;
23677 SetCC = SetCC.getOperand(0);
23680 switch (SetCC.getOpcode()) {
23681 case X86ISD::SETCC_CARRY:
23682 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23683 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23684 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23685 // truncated to i1 using 'and'.
23686 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23688 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23689 "Invalid use of SETCC_CARRY!");
23691 case X86ISD::SETCC:
23692 // Set the condition code or opposite one if necessary.
23693 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23694 if (needOppositeCond)
23695 CC = X86::GetOppositeBranchCondition(CC);
23696 return SetCC.getOperand(1);
23697 case X86ISD::CMOV: {
23698 // Check whether false/true value has canonical one, i.e. 0 or 1.
23699 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23700 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23701 // Quit if true value is not a constant.
23704 // Quit if false value is not a constant.
23706 SDValue Op = SetCC.getOperand(0);
23707 // Skip 'zext' or 'trunc' node.
23708 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23709 Op.getOpcode() == ISD::TRUNCATE)
23710 Op = Op.getOperand(0);
23711 // A special case for rdrand/rdseed, where 0 is set if false cond is
23713 if ((Op.getOpcode() != X86ISD::RDRAND &&
23714 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23717 // Quit if false value is not the constant 0 or 1.
23718 bool FValIsFalse = true;
23719 if (FVal && FVal->getZExtValue() != 0) {
23720 if (FVal->getZExtValue() != 1)
23722 // If FVal is 1, opposite cond is needed.
23723 needOppositeCond = !needOppositeCond;
23724 FValIsFalse = false;
23726 // Quit if TVal is not the constant opposite of FVal.
23727 if (FValIsFalse && TVal->getZExtValue() != 1)
23729 if (!FValIsFalse && TVal->getZExtValue() != 0)
23731 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23732 if (needOppositeCond)
23733 CC = X86::GetOppositeBranchCondition(CC);
23734 return SetCC.getOperand(3);
23741 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23742 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23743 TargetLowering::DAGCombinerInfo &DCI,
23744 const X86Subtarget *Subtarget) {
23747 // If the flag operand isn't dead, don't touch this CMOV.
23748 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23751 SDValue FalseOp = N->getOperand(0);
23752 SDValue TrueOp = N->getOperand(1);
23753 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23754 SDValue Cond = N->getOperand(3);
23756 if (CC == X86::COND_E || CC == X86::COND_NE) {
23757 switch (Cond.getOpcode()) {
23761 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23762 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23763 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23769 Flags = checkBoolTestSetCCCombine(Cond, CC);
23770 if (Flags.getNode() &&
23771 // Extra check as FCMOV only supports a subset of X86 cond.
23772 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23773 SDValue Ops[] = { FalseOp, TrueOp,
23774 DAG.getConstant(CC, MVT::i8), Flags };
23775 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23778 // If this is a select between two integer constants, try to do some
23779 // optimizations. Note that the operands are ordered the opposite of SELECT
23781 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23782 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23783 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23784 // larger than FalseC (the false value).
23785 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23786 CC = X86::GetOppositeBranchCondition(CC);
23787 std::swap(TrueC, FalseC);
23788 std::swap(TrueOp, FalseOp);
23791 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23792 // This is efficient for any integer data type (including i8/i16) and
23794 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23795 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23796 DAG.getConstant(CC, MVT::i8), Cond);
23798 // Zero extend the condition if needed.
23799 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23801 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23802 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23803 DAG.getConstant(ShAmt, MVT::i8));
23804 if (N->getNumValues() == 2) // Dead flag value?
23805 return DCI.CombineTo(N, Cond, SDValue());
23809 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23810 // for any integer data type, including i8/i16.
23811 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23812 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23813 DAG.getConstant(CC, MVT::i8), Cond);
23815 // Zero extend the condition if needed.
23816 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23817 FalseC->getValueType(0), Cond);
23818 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23819 SDValue(FalseC, 0));
23821 if (N->getNumValues() == 2) // Dead flag value?
23822 return DCI.CombineTo(N, Cond, SDValue());
23826 // Optimize cases that will turn into an LEA instruction. This requires
23827 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23828 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23829 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23830 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23832 bool isFastMultiplier = false;
23834 switch ((unsigned char)Diff) {
23836 case 1: // result = add base, cond
23837 case 2: // result = lea base( , cond*2)
23838 case 3: // result = lea base(cond, cond*2)
23839 case 4: // result = lea base( , cond*4)
23840 case 5: // result = lea base(cond, cond*4)
23841 case 8: // result = lea base( , cond*8)
23842 case 9: // result = lea base(cond, cond*8)
23843 isFastMultiplier = true;
23848 if (isFastMultiplier) {
23849 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23850 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23851 DAG.getConstant(CC, MVT::i8), Cond);
23852 // Zero extend the condition if needed.
23853 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23855 // Scale the condition by the difference.
23857 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23858 DAG.getConstant(Diff, Cond.getValueType()));
23860 // Add the base if non-zero.
23861 if (FalseC->getAPIntValue() != 0)
23862 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23863 SDValue(FalseC, 0));
23864 if (N->getNumValues() == 2) // Dead flag value?
23865 return DCI.CombineTo(N, Cond, SDValue());
23872 // Handle these cases:
23873 // (select (x != c), e, c) -> select (x != c), e, x),
23874 // (select (x == c), c, e) -> select (x == c), x, e)
23875 // where the c is an integer constant, and the "select" is the combination
23876 // of CMOV and CMP.
23878 // The rationale for this change is that the conditional-move from a constant
23879 // needs two instructions, however, conditional-move from a register needs
23880 // only one instruction.
23882 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23883 // some instruction-combining opportunities. This opt needs to be
23884 // postponed as late as possible.
23886 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23887 // the DCI.xxxx conditions are provided to postpone the optimization as
23888 // late as possible.
23890 ConstantSDNode *CmpAgainst = nullptr;
23891 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23892 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23893 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23895 if (CC == X86::COND_NE &&
23896 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23897 CC = X86::GetOppositeBranchCondition(CC);
23898 std::swap(TrueOp, FalseOp);
23901 if (CC == X86::COND_E &&
23902 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23903 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23904 DAG.getConstant(CC, MVT::i8), Cond };
23905 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23913 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23914 const X86Subtarget *Subtarget) {
23915 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23917 default: return SDValue();
23918 // SSE/AVX/AVX2 blend intrinsics.
23919 case Intrinsic::x86_avx2_pblendvb:
23920 case Intrinsic::x86_avx2_pblendw:
23921 case Intrinsic::x86_avx2_pblendd_128:
23922 case Intrinsic::x86_avx2_pblendd_256:
23923 // Don't try to simplify this intrinsic if we don't have AVX2.
23924 if (!Subtarget->hasAVX2())
23927 case Intrinsic::x86_avx_blend_pd_256:
23928 case Intrinsic::x86_avx_blend_ps_256:
23929 case Intrinsic::x86_avx_blendv_pd_256:
23930 case Intrinsic::x86_avx_blendv_ps_256:
23931 // Don't try to simplify this intrinsic if we don't have AVX.
23932 if (!Subtarget->hasAVX())
23935 case Intrinsic::x86_sse41_pblendw:
23936 case Intrinsic::x86_sse41_blendpd:
23937 case Intrinsic::x86_sse41_blendps:
23938 case Intrinsic::x86_sse41_blendvps:
23939 case Intrinsic::x86_sse41_blendvpd:
23940 case Intrinsic::x86_sse41_pblendvb: {
23941 SDValue Op0 = N->getOperand(1);
23942 SDValue Op1 = N->getOperand(2);
23943 SDValue Mask = N->getOperand(3);
23945 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23946 if (!Subtarget->hasSSE41())
23949 // fold (blend A, A, Mask) -> A
23952 // fold (blend A, B, allZeros) -> A
23953 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23955 // fold (blend A, B, allOnes) -> B
23956 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23959 // Simplify the case where the mask is a constant i32 value.
23960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23961 if (C->isNullValue())
23963 if (C->isAllOnesValue())
23970 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23971 case Intrinsic::x86_sse2_psrai_w:
23972 case Intrinsic::x86_sse2_psrai_d:
23973 case Intrinsic::x86_avx2_psrai_w:
23974 case Intrinsic::x86_avx2_psrai_d:
23975 case Intrinsic::x86_sse2_psra_w:
23976 case Intrinsic::x86_sse2_psra_d:
23977 case Intrinsic::x86_avx2_psra_w:
23978 case Intrinsic::x86_avx2_psra_d: {
23979 SDValue Op0 = N->getOperand(1);
23980 SDValue Op1 = N->getOperand(2);
23981 EVT VT = Op0.getValueType();
23982 assert(VT.isVector() && "Expected a vector type!");
23984 if (isa<BuildVectorSDNode>(Op1))
23985 Op1 = Op1.getOperand(0);
23987 if (!isa<ConstantSDNode>(Op1))
23990 EVT SVT = VT.getVectorElementType();
23991 unsigned SVTBits = SVT.getSizeInBits();
23993 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23994 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23995 uint64_t ShAmt = C.getZExtValue();
23997 // Don't try to convert this shift into a ISD::SRA if the shift
23998 // count is bigger than or equal to the element size.
23999 if (ShAmt >= SVTBits)
24002 // Trivial case: if the shift count is zero, then fold this
24003 // into the first operand.
24007 // Replace this packed shift intrinsic with a target independent
24009 SDValue Splat = DAG.getConstant(C, VT);
24010 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
24015 /// PerformMulCombine - Optimize a single multiply with constant into two
24016 /// in order to implement it with two cheaper instructions, e.g.
24017 /// LEA + SHL, LEA + LEA.
24018 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24019 TargetLowering::DAGCombinerInfo &DCI) {
24020 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24023 EVT VT = N->getValueType(0);
24024 if (VT != MVT::i64)
24027 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24030 uint64_t MulAmt = C->getZExtValue();
24031 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24034 uint64_t MulAmt1 = 0;
24035 uint64_t MulAmt2 = 0;
24036 if ((MulAmt % 9) == 0) {
24038 MulAmt2 = MulAmt / 9;
24039 } else if ((MulAmt % 5) == 0) {
24041 MulAmt2 = MulAmt / 5;
24042 } else if ((MulAmt % 3) == 0) {
24044 MulAmt2 = MulAmt / 3;
24047 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24050 if (isPowerOf2_64(MulAmt2) &&
24051 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24052 // If second multiplifer is pow2, issue it first. We want the multiply by
24053 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24055 std::swap(MulAmt1, MulAmt2);
24058 if (isPowerOf2_64(MulAmt1))
24059 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24060 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
24062 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24063 DAG.getConstant(MulAmt1, VT));
24065 if (isPowerOf2_64(MulAmt2))
24066 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24067 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
24069 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24070 DAG.getConstant(MulAmt2, VT));
24072 // Do not add new nodes to DAG combiner worklist.
24073 DCI.CombineTo(N, NewMul, false);
24078 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24079 SDValue N0 = N->getOperand(0);
24080 SDValue N1 = N->getOperand(1);
24081 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24082 EVT VT = N0.getValueType();
24084 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24085 // since the result of setcc_c is all zero's or all ones.
24086 if (VT.isInteger() && !VT.isVector() &&
24087 N1C && N0.getOpcode() == ISD::AND &&
24088 N0.getOperand(1).getOpcode() == ISD::Constant) {
24089 SDValue N00 = N0.getOperand(0);
24090 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
24091 ((N00.getOpcode() == ISD::ANY_EXTEND ||
24092 N00.getOpcode() == ISD::ZERO_EXTEND) &&
24093 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
24094 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24095 APInt ShAmt = N1C->getAPIntValue();
24096 Mask = Mask.shl(ShAmt);
24098 return DAG.getNode(ISD::AND, SDLoc(N), VT,
24099 N00, DAG.getConstant(Mask, VT));
24103 // Hardware support for vector shifts is sparse which makes us scalarize the
24104 // vector operations in many cases. Also, on sandybridge ADD is faster than
24106 // (shl V, 1) -> add V,V
24107 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24108 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24109 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24110 // We shift all of the values by one. In many cases we do not have
24111 // hardware support for this operation. This is better expressed as an ADD
24113 if (N1SplatC->getZExtValue() == 1)
24114 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24120 /// \brief Returns a vector of 0s if the node in input is a vector logical
24121 /// shift by a constant amount which is known to be bigger than or equal
24122 /// to the vector element size in bits.
24123 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24124 const X86Subtarget *Subtarget) {
24125 EVT VT = N->getValueType(0);
24127 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24128 (!Subtarget->hasInt256() ||
24129 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24132 SDValue Amt = N->getOperand(1);
24134 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24135 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24136 APInt ShiftAmt = AmtSplat->getAPIntValue();
24137 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24139 // SSE2/AVX2 logical shifts always return a vector of 0s
24140 // if the shift amount is bigger than or equal to
24141 // the element size. The constant shift amount will be
24142 // encoded as a 8-bit immediate.
24143 if (ShiftAmt.trunc(8).uge(MaxAmount))
24144 return getZeroVector(VT, Subtarget, DAG, DL);
24150 /// PerformShiftCombine - Combine shifts.
24151 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24152 TargetLowering::DAGCombinerInfo &DCI,
24153 const X86Subtarget *Subtarget) {
24154 if (N->getOpcode() == ISD::SHL) {
24155 SDValue V = PerformSHLCombine(N, DAG);
24156 if (V.getNode()) return V;
24159 if (N->getOpcode() != ISD::SRA) {
24160 // Try to fold this logical shift into a zero vector.
24161 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24162 if (V.getNode()) return V;
24168 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24169 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24170 // and friends. Likewise for OR -> CMPNEQSS.
24171 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24172 TargetLowering::DAGCombinerInfo &DCI,
24173 const X86Subtarget *Subtarget) {
24176 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24177 // we're requiring SSE2 for both.
24178 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24179 SDValue N0 = N->getOperand(0);
24180 SDValue N1 = N->getOperand(1);
24181 SDValue CMP0 = N0->getOperand(1);
24182 SDValue CMP1 = N1->getOperand(1);
24185 // The SETCCs should both refer to the same CMP.
24186 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24189 SDValue CMP00 = CMP0->getOperand(0);
24190 SDValue CMP01 = CMP0->getOperand(1);
24191 EVT VT = CMP00.getValueType();
24193 if (VT == MVT::f32 || VT == MVT::f64) {
24194 bool ExpectingFlags = false;
24195 // Check for any users that want flags:
24196 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24197 !ExpectingFlags && UI != UE; ++UI)
24198 switch (UI->getOpcode()) {
24203 ExpectingFlags = true;
24205 case ISD::CopyToReg:
24206 case ISD::SIGN_EXTEND:
24207 case ISD::ZERO_EXTEND:
24208 case ISD::ANY_EXTEND:
24212 if (!ExpectingFlags) {
24213 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24214 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24216 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24217 X86::CondCode tmp = cc0;
24222 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24223 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24224 // FIXME: need symbolic constants for these magic numbers.
24225 // See X86ATTInstPrinter.cpp:printSSECC().
24226 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24227 if (Subtarget->hasAVX512()) {
24228 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24229 CMP01, DAG.getConstant(x86cc, MVT::i8));
24230 if (N->getValueType(0) != MVT::i1)
24231 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24235 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24236 CMP00.getValueType(), CMP00, CMP01,
24237 DAG.getConstant(x86cc, MVT::i8));
24239 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24240 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24242 if (is64BitFP && !Subtarget->is64Bit()) {
24243 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24244 // 64-bit integer, since that's not a legal type. Since
24245 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24246 // bits, but can do this little dance to extract the lowest 32 bits
24247 // and work with those going forward.
24248 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24250 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24252 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24253 Vector32, DAG.getIntPtrConstant(0));
24257 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24258 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24259 DAG.getConstant(1, IntVT));
24260 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24261 return OneBitOfTruth;
24269 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24270 /// so it can be folded inside ANDNP.
24271 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24272 EVT VT = N->getValueType(0);
24274 // Match direct AllOnes for 128 and 256-bit vectors
24275 if (ISD::isBuildVectorAllOnes(N))
24278 // Look through a bit convert.
24279 if (N->getOpcode() == ISD::BITCAST)
24280 N = N->getOperand(0).getNode();
24282 // Sometimes the operand may come from a insert_subvector building a 256-bit
24284 if (VT.is256BitVector() &&
24285 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24286 SDValue V1 = N->getOperand(0);
24287 SDValue V2 = N->getOperand(1);
24289 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24290 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24291 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24292 ISD::isBuildVectorAllOnes(V2.getNode()))
24299 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24300 // register. In most cases we actually compare or select YMM-sized registers
24301 // and mixing the two types creates horrible code. This method optimizes
24302 // some of the transition sequences.
24303 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24304 TargetLowering::DAGCombinerInfo &DCI,
24305 const X86Subtarget *Subtarget) {
24306 EVT VT = N->getValueType(0);
24307 if (!VT.is256BitVector())
24310 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24311 N->getOpcode() == ISD::ZERO_EXTEND ||
24312 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24314 SDValue Narrow = N->getOperand(0);
24315 EVT NarrowVT = Narrow->getValueType(0);
24316 if (!NarrowVT.is128BitVector())
24319 if (Narrow->getOpcode() != ISD::XOR &&
24320 Narrow->getOpcode() != ISD::AND &&
24321 Narrow->getOpcode() != ISD::OR)
24324 SDValue N0 = Narrow->getOperand(0);
24325 SDValue N1 = Narrow->getOperand(1);
24328 // The Left side has to be a trunc.
24329 if (N0.getOpcode() != ISD::TRUNCATE)
24332 // The type of the truncated inputs.
24333 EVT WideVT = N0->getOperand(0)->getValueType(0);
24337 // The right side has to be a 'trunc' or a constant vector.
24338 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24339 ConstantSDNode *RHSConstSplat = nullptr;
24340 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24341 RHSConstSplat = RHSBV->getConstantSplatNode();
24342 if (!RHSTrunc && !RHSConstSplat)
24345 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24347 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24350 // Set N0 and N1 to hold the inputs to the new wide operation.
24351 N0 = N0->getOperand(0);
24352 if (RHSConstSplat) {
24353 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24354 SDValue(RHSConstSplat, 0));
24355 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24356 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24357 } else if (RHSTrunc) {
24358 N1 = N1->getOperand(0);
24361 // Generate the wide operation.
24362 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24363 unsigned Opcode = N->getOpcode();
24365 case ISD::ANY_EXTEND:
24367 case ISD::ZERO_EXTEND: {
24368 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24369 APInt Mask = APInt::getAllOnesValue(InBits);
24370 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24371 return DAG.getNode(ISD::AND, DL, VT,
24372 Op, DAG.getConstant(Mask, VT));
24374 case ISD::SIGN_EXTEND:
24375 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24376 Op, DAG.getValueType(NarrowVT));
24378 llvm_unreachable("Unexpected opcode");
24382 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24383 TargetLowering::DAGCombinerInfo &DCI,
24384 const X86Subtarget *Subtarget) {
24385 EVT VT = N->getValueType(0);
24386 if (DCI.isBeforeLegalizeOps())
24389 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24393 // Create BEXTR instructions
24394 // BEXTR is ((X >> imm) & (2**size-1))
24395 if (VT == MVT::i32 || VT == MVT::i64) {
24396 SDValue N0 = N->getOperand(0);
24397 SDValue N1 = N->getOperand(1);
24400 // Check for BEXTR.
24401 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24402 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24403 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24404 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24405 if (MaskNode && ShiftNode) {
24406 uint64_t Mask = MaskNode->getZExtValue();
24407 uint64_t Shift = ShiftNode->getZExtValue();
24408 if (isMask_64(Mask)) {
24409 uint64_t MaskSize = CountPopulation_64(Mask);
24410 if (Shift + MaskSize <= VT.getSizeInBits())
24411 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24412 DAG.getConstant(Shift | (MaskSize << 8), VT));
24420 // Want to form ANDNP nodes:
24421 // 1) In the hopes of then easily combining them with OR and AND nodes
24422 // to form PBLEND/PSIGN.
24423 // 2) To match ANDN packed intrinsics
24424 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24427 SDValue N0 = N->getOperand(0);
24428 SDValue N1 = N->getOperand(1);
24431 // Check LHS for vnot
24432 if (N0.getOpcode() == ISD::XOR &&
24433 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24434 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24435 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24437 // Check RHS for vnot
24438 if (N1.getOpcode() == ISD::XOR &&
24439 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24440 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24441 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24446 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24447 TargetLowering::DAGCombinerInfo &DCI,
24448 const X86Subtarget *Subtarget) {
24449 if (DCI.isBeforeLegalizeOps())
24452 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24456 SDValue N0 = N->getOperand(0);
24457 SDValue N1 = N->getOperand(1);
24458 EVT VT = N->getValueType(0);
24460 // look for psign/blend
24461 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24462 if (!Subtarget->hasSSSE3() ||
24463 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24466 // Canonicalize pandn to RHS
24467 if (N0.getOpcode() == X86ISD::ANDNP)
24469 // or (and (m, y), (pandn m, x))
24470 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24471 SDValue Mask = N1.getOperand(0);
24472 SDValue X = N1.getOperand(1);
24474 if (N0.getOperand(0) == Mask)
24475 Y = N0.getOperand(1);
24476 if (N0.getOperand(1) == Mask)
24477 Y = N0.getOperand(0);
24479 // Check to see if the mask appeared in both the AND and ANDNP and
24483 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24484 // Look through mask bitcast.
24485 if (Mask.getOpcode() == ISD::BITCAST)
24486 Mask = Mask.getOperand(0);
24487 if (X.getOpcode() == ISD::BITCAST)
24488 X = X.getOperand(0);
24489 if (Y.getOpcode() == ISD::BITCAST)
24490 Y = Y.getOperand(0);
24492 EVT MaskVT = Mask.getValueType();
24494 // Validate that the Mask operand is a vector sra node.
24495 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24496 // there is no psrai.b
24497 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24498 unsigned SraAmt = ~0;
24499 if (Mask.getOpcode() == ISD::SRA) {
24500 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24501 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24502 SraAmt = AmtConst->getZExtValue();
24503 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24504 SDValue SraC = Mask.getOperand(1);
24505 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24507 if ((SraAmt + 1) != EltBits)
24512 // Now we know we at least have a plendvb with the mask val. See if
24513 // we can form a psignb/w/d.
24514 // psign = x.type == y.type == mask.type && y = sub(0, x);
24515 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24516 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24517 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24518 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24519 "Unsupported VT for PSIGN");
24520 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24521 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24523 // PBLENDVB only available on SSE 4.1
24524 if (!Subtarget->hasSSE41())
24527 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24529 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24530 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24531 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24532 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24533 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24537 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24540 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24541 MachineFunction &MF = DAG.getMachineFunction();
24542 bool OptForSize = MF.getFunction()->getAttributes().
24543 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24545 // SHLD/SHRD instructions have lower register pressure, but on some
24546 // platforms they have higher latency than the equivalent
24547 // series of shifts/or that would otherwise be generated.
24548 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24549 // have higher latencies and we are not optimizing for size.
24550 if (!OptForSize && Subtarget->isSHLDSlow())
24553 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24555 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24557 if (!N0.hasOneUse() || !N1.hasOneUse())
24560 SDValue ShAmt0 = N0.getOperand(1);
24561 if (ShAmt0.getValueType() != MVT::i8)
24563 SDValue ShAmt1 = N1.getOperand(1);
24564 if (ShAmt1.getValueType() != MVT::i8)
24566 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24567 ShAmt0 = ShAmt0.getOperand(0);
24568 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24569 ShAmt1 = ShAmt1.getOperand(0);
24572 unsigned Opc = X86ISD::SHLD;
24573 SDValue Op0 = N0.getOperand(0);
24574 SDValue Op1 = N1.getOperand(0);
24575 if (ShAmt0.getOpcode() == ISD::SUB) {
24576 Opc = X86ISD::SHRD;
24577 std::swap(Op0, Op1);
24578 std::swap(ShAmt0, ShAmt1);
24581 unsigned Bits = VT.getSizeInBits();
24582 if (ShAmt1.getOpcode() == ISD::SUB) {
24583 SDValue Sum = ShAmt1.getOperand(0);
24584 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24585 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24586 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24587 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24588 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24589 return DAG.getNode(Opc, DL, VT,
24591 DAG.getNode(ISD::TRUNCATE, DL,
24594 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24595 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24597 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24598 return DAG.getNode(Opc, DL, VT,
24599 N0.getOperand(0), N1.getOperand(0),
24600 DAG.getNode(ISD::TRUNCATE, DL,
24607 // Generate NEG and CMOV for integer abs.
24608 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24609 EVT VT = N->getValueType(0);
24611 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24612 // 8-bit integer abs to NEG and CMOV.
24613 if (VT.isInteger() && VT.getSizeInBits() == 8)
24616 SDValue N0 = N->getOperand(0);
24617 SDValue N1 = N->getOperand(1);
24620 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24621 // and change it to SUB and CMOV.
24622 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24623 N0.getOpcode() == ISD::ADD &&
24624 N0.getOperand(1) == N1 &&
24625 N1.getOpcode() == ISD::SRA &&
24626 N1.getOperand(0) == N0.getOperand(0))
24627 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24628 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24629 // Generate SUB & CMOV.
24630 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24631 DAG.getConstant(0, VT), N0.getOperand(0));
24633 SDValue Ops[] = { N0.getOperand(0), Neg,
24634 DAG.getConstant(X86::COND_GE, MVT::i8),
24635 SDValue(Neg.getNode(), 1) };
24636 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24641 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24642 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24643 TargetLowering::DAGCombinerInfo &DCI,
24644 const X86Subtarget *Subtarget) {
24645 if (DCI.isBeforeLegalizeOps())
24648 if (Subtarget->hasCMov()) {
24649 SDValue RV = performIntegerAbsCombine(N, DAG);
24657 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24658 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24659 TargetLowering::DAGCombinerInfo &DCI,
24660 const X86Subtarget *Subtarget) {
24661 LoadSDNode *Ld = cast<LoadSDNode>(N);
24662 EVT RegVT = Ld->getValueType(0);
24663 EVT MemVT = Ld->getMemoryVT();
24665 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24667 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24668 // into two 16-byte operations.
24669 ISD::LoadExtType Ext = Ld->getExtensionType();
24670 unsigned Alignment = Ld->getAlignment();
24671 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24672 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24673 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24674 unsigned NumElems = RegVT.getVectorNumElements();
24678 SDValue Ptr = Ld->getBasePtr();
24679 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24681 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24683 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24684 Ld->getPointerInfo(), Ld->isVolatile(),
24685 Ld->isNonTemporal(), Ld->isInvariant(),
24687 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24688 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24689 Ld->getPointerInfo(), Ld->isVolatile(),
24690 Ld->isNonTemporal(), Ld->isInvariant(),
24691 std::min(16U, Alignment));
24692 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24694 Load2.getValue(1));
24696 SDValue NewVec = DAG.getUNDEF(RegVT);
24697 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24698 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24699 return DCI.CombineTo(N, NewVec, TF, true);
24705 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24706 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24707 const X86Subtarget *Subtarget) {
24708 StoreSDNode *St = cast<StoreSDNode>(N);
24709 EVT VT = St->getValue().getValueType();
24710 EVT StVT = St->getMemoryVT();
24712 SDValue StoredVal = St->getOperand(1);
24713 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24715 // If we are saving a concatenation of two XMM registers and 32-byte stores
24716 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24717 unsigned Alignment = St->getAlignment();
24718 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24719 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24720 StVT == VT && !IsAligned) {
24721 unsigned NumElems = VT.getVectorNumElements();
24725 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24726 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24728 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24729 SDValue Ptr0 = St->getBasePtr();
24730 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24732 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24733 St->getPointerInfo(), St->isVolatile(),
24734 St->isNonTemporal(), Alignment);
24735 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24736 St->getPointerInfo(), St->isVolatile(),
24737 St->isNonTemporal(),
24738 std::min(16U, Alignment));
24739 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24742 // Optimize trunc store (of multiple scalars) to shuffle and store.
24743 // First, pack all of the elements in one place. Next, store to memory
24744 // in fewer chunks.
24745 if (St->isTruncatingStore() && VT.isVector()) {
24746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24747 unsigned NumElems = VT.getVectorNumElements();
24748 assert(StVT != VT && "Cannot truncate to the same type");
24749 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24750 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24752 // From, To sizes and ElemCount must be pow of two
24753 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24754 // We are going to use the original vector elt for storing.
24755 // Accumulated smaller vector elements must be a multiple of the store size.
24756 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24758 unsigned SizeRatio = FromSz / ToSz;
24760 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24762 // Create a type on which we perform the shuffle
24763 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24764 StVT.getScalarType(), NumElems*SizeRatio);
24766 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24768 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24769 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24770 for (unsigned i = 0; i != NumElems; ++i)
24771 ShuffleVec[i] = i * SizeRatio;
24773 // Can't shuffle using an illegal type.
24774 if (!TLI.isTypeLegal(WideVecVT))
24777 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24778 DAG.getUNDEF(WideVecVT),
24780 // At this point all of the data is stored at the bottom of the
24781 // register. We now need to save it to mem.
24783 // Find the largest store unit
24784 MVT StoreType = MVT::i8;
24785 for (MVT Tp : MVT::integer_valuetypes()) {
24786 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24790 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24791 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24792 (64 <= NumElems * ToSz))
24793 StoreType = MVT::f64;
24795 // Bitcast the original vector into a vector of store-size units
24796 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24797 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24798 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24799 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24800 SmallVector<SDValue, 8> Chains;
24801 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24802 TLI.getPointerTy());
24803 SDValue Ptr = St->getBasePtr();
24805 // Perform one or more big stores into memory.
24806 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24807 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24808 StoreType, ShuffWide,
24809 DAG.getIntPtrConstant(i));
24810 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24811 St->getPointerInfo(), St->isVolatile(),
24812 St->isNonTemporal(), St->getAlignment());
24813 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24814 Chains.push_back(Ch);
24817 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24820 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24821 // the FP state in cases where an emms may be missing.
24822 // A preferable solution to the general problem is to figure out the right
24823 // places to insert EMMS. This qualifies as a quick hack.
24825 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24826 if (VT.getSizeInBits() != 64)
24829 const Function *F = DAG.getMachineFunction().getFunction();
24830 bool NoImplicitFloatOps = F->getAttributes().
24831 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24832 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24833 && Subtarget->hasSSE2();
24834 if ((VT.isVector() ||
24835 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24836 isa<LoadSDNode>(St->getValue()) &&
24837 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24838 St->getChain().hasOneUse() && !St->isVolatile()) {
24839 SDNode* LdVal = St->getValue().getNode();
24840 LoadSDNode *Ld = nullptr;
24841 int TokenFactorIndex = -1;
24842 SmallVector<SDValue, 8> Ops;
24843 SDNode* ChainVal = St->getChain().getNode();
24844 // Must be a store of a load. We currently handle two cases: the load
24845 // is a direct child, and it's under an intervening TokenFactor. It is
24846 // possible to dig deeper under nested TokenFactors.
24847 if (ChainVal == LdVal)
24848 Ld = cast<LoadSDNode>(St->getChain());
24849 else if (St->getValue().hasOneUse() &&
24850 ChainVal->getOpcode() == ISD::TokenFactor) {
24851 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24852 if (ChainVal->getOperand(i).getNode() == LdVal) {
24853 TokenFactorIndex = i;
24854 Ld = cast<LoadSDNode>(St->getValue());
24856 Ops.push_back(ChainVal->getOperand(i));
24860 if (!Ld || !ISD::isNormalLoad(Ld))
24863 // If this is not the MMX case, i.e. we are just turning i64 load/store
24864 // into f64 load/store, avoid the transformation if there are multiple
24865 // uses of the loaded value.
24866 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24871 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24872 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24874 if (Subtarget->is64Bit() || F64IsLegal) {
24875 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24876 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24877 Ld->getPointerInfo(), Ld->isVolatile(),
24878 Ld->isNonTemporal(), Ld->isInvariant(),
24879 Ld->getAlignment());
24880 SDValue NewChain = NewLd.getValue(1);
24881 if (TokenFactorIndex != -1) {
24882 Ops.push_back(NewChain);
24883 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24885 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24886 St->getPointerInfo(),
24887 St->isVolatile(), St->isNonTemporal(),
24888 St->getAlignment());
24891 // Otherwise, lower to two pairs of 32-bit loads / stores.
24892 SDValue LoAddr = Ld->getBasePtr();
24893 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24894 DAG.getConstant(4, MVT::i32));
24896 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24897 Ld->getPointerInfo(),
24898 Ld->isVolatile(), Ld->isNonTemporal(),
24899 Ld->isInvariant(), Ld->getAlignment());
24900 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24901 Ld->getPointerInfo().getWithOffset(4),
24902 Ld->isVolatile(), Ld->isNonTemporal(),
24904 MinAlign(Ld->getAlignment(), 4));
24906 SDValue NewChain = LoLd.getValue(1);
24907 if (TokenFactorIndex != -1) {
24908 Ops.push_back(LoLd);
24909 Ops.push_back(HiLd);
24910 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24913 LoAddr = St->getBasePtr();
24914 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24915 DAG.getConstant(4, MVT::i32));
24917 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24918 St->getPointerInfo(),
24919 St->isVolatile(), St->isNonTemporal(),
24920 St->getAlignment());
24921 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24922 St->getPointerInfo().getWithOffset(4),
24924 St->isNonTemporal(),
24925 MinAlign(St->getAlignment(), 4));
24926 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24931 /// Return 'true' if this vector operation is "horizontal"
24932 /// and return the operands for the horizontal operation in LHS and RHS. A
24933 /// horizontal operation performs the binary operation on successive elements
24934 /// of its first operand, then on successive elements of its second operand,
24935 /// returning the resulting values in a vector. For example, if
24936 /// A = < float a0, float a1, float a2, float a3 >
24938 /// B = < float b0, float b1, float b2, float b3 >
24939 /// then the result of doing a horizontal operation on A and B is
24940 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24941 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24942 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24943 /// set to A, RHS to B, and the routine returns 'true'.
24944 /// Note that the binary operation should have the property that if one of the
24945 /// operands is UNDEF then the result is UNDEF.
24946 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24947 // Look for the following pattern: if
24948 // A = < float a0, float a1, float a2, float a3 >
24949 // B = < float b0, float b1, float b2, float b3 >
24951 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24952 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24953 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24954 // which is A horizontal-op B.
24956 // At least one of the operands should be a vector shuffle.
24957 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24958 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24961 MVT VT = LHS.getSimpleValueType();
24963 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24964 "Unsupported vector type for horizontal add/sub");
24966 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24967 // operate independently on 128-bit lanes.
24968 unsigned NumElts = VT.getVectorNumElements();
24969 unsigned NumLanes = VT.getSizeInBits()/128;
24970 unsigned NumLaneElts = NumElts / NumLanes;
24971 assert((NumLaneElts % 2 == 0) &&
24972 "Vector type should have an even number of elements in each lane");
24973 unsigned HalfLaneElts = NumLaneElts/2;
24975 // View LHS in the form
24976 // LHS = VECTOR_SHUFFLE A, B, LMask
24977 // If LHS is not a shuffle then pretend it is the shuffle
24978 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24979 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24982 SmallVector<int, 16> LMask(NumElts);
24983 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24984 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24985 A = LHS.getOperand(0);
24986 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24987 B = LHS.getOperand(1);
24988 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24989 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24991 if (LHS.getOpcode() != ISD::UNDEF)
24993 for (unsigned i = 0; i != NumElts; ++i)
24997 // Likewise, view RHS in the form
24998 // RHS = VECTOR_SHUFFLE C, D, RMask
25000 SmallVector<int, 16> RMask(NumElts);
25001 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25002 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25003 C = RHS.getOperand(0);
25004 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25005 D = RHS.getOperand(1);
25006 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25007 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25009 if (RHS.getOpcode() != ISD::UNDEF)
25011 for (unsigned i = 0; i != NumElts; ++i)
25015 // Check that the shuffles are both shuffling the same vectors.
25016 if (!(A == C && B == D) && !(A == D && B == C))
25019 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25020 if (!A.getNode() && !B.getNode())
25023 // If A and B occur in reverse order in RHS, then "swap" them (which means
25024 // rewriting the mask).
25026 CommuteVectorShuffleMask(RMask, NumElts);
25028 // At this point LHS and RHS are equivalent to
25029 // LHS = VECTOR_SHUFFLE A, B, LMask
25030 // RHS = VECTOR_SHUFFLE A, B, RMask
25031 // Check that the masks correspond to performing a horizontal operation.
25032 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25033 for (unsigned i = 0; i != NumLaneElts; ++i) {
25034 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25036 // Ignore any UNDEF components.
25037 if (LIdx < 0 || RIdx < 0 ||
25038 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25039 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25042 // Check that successive elements are being operated on. If not, this is
25043 // not a horizontal operation.
25044 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25045 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25046 if (!(LIdx == Index && RIdx == Index + 1) &&
25047 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25052 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25053 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25057 /// Do target-specific dag combines on floating point adds.
25058 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25059 const X86Subtarget *Subtarget) {
25060 EVT VT = N->getValueType(0);
25061 SDValue LHS = N->getOperand(0);
25062 SDValue RHS = N->getOperand(1);
25064 // Try to synthesize horizontal adds from adds of shuffles.
25065 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25066 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25067 isHorizontalBinOp(LHS, RHS, true))
25068 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25072 /// Do target-specific dag combines on floating point subs.
25073 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25074 const X86Subtarget *Subtarget) {
25075 EVT VT = N->getValueType(0);
25076 SDValue LHS = N->getOperand(0);
25077 SDValue RHS = N->getOperand(1);
25079 // Try to synthesize horizontal subs from subs of shuffles.
25080 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25081 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25082 isHorizontalBinOp(LHS, RHS, false))
25083 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25087 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25088 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
25089 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25090 // F[X]OR(0.0, x) -> x
25091 // F[X]OR(x, 0.0) -> x
25092 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25093 if (C->getValueAPF().isPosZero())
25094 return N->getOperand(1);
25095 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25096 if (C->getValueAPF().isPosZero())
25097 return N->getOperand(0);
25101 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25102 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25103 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25105 // Only perform optimizations if UnsafeMath is used.
25106 if (!DAG.getTarget().Options.UnsafeFPMath)
25109 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25110 // into FMINC and FMAXC, which are Commutative operations.
25111 unsigned NewOp = 0;
25112 switch (N->getOpcode()) {
25113 default: llvm_unreachable("unknown opcode");
25114 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25115 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25118 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25119 N->getOperand(0), N->getOperand(1));
25122 /// Do target-specific dag combines on X86ISD::FAND nodes.
25123 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25124 // FAND(0.0, x) -> 0.0
25125 // FAND(x, 0.0) -> 0.0
25126 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25127 if (C->getValueAPF().isPosZero())
25128 return N->getOperand(0);
25129 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25130 if (C->getValueAPF().isPosZero())
25131 return N->getOperand(1);
25135 /// Do target-specific dag combines on X86ISD::FANDN nodes
25136 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25137 // FANDN(x, 0.0) -> 0.0
25138 // FANDN(0.0, x) -> x
25139 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25140 if (C->getValueAPF().isPosZero())
25141 return N->getOperand(1);
25142 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25143 if (C->getValueAPF().isPosZero())
25144 return N->getOperand(1);
25148 static SDValue PerformBTCombine(SDNode *N,
25150 TargetLowering::DAGCombinerInfo &DCI) {
25151 // BT ignores high bits in the bit index operand.
25152 SDValue Op1 = N->getOperand(1);
25153 if (Op1.hasOneUse()) {
25154 unsigned BitWidth = Op1.getValueSizeInBits();
25155 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25156 APInt KnownZero, KnownOne;
25157 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25158 !DCI.isBeforeLegalizeOps());
25159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25160 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25161 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25162 DCI.CommitTargetLoweringOpt(TLO);
25167 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25168 SDValue Op = N->getOperand(0);
25169 if (Op.getOpcode() == ISD::BITCAST)
25170 Op = Op.getOperand(0);
25171 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25172 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25173 VT.getVectorElementType().getSizeInBits() ==
25174 OpVT.getVectorElementType().getSizeInBits()) {
25175 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25180 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25181 const X86Subtarget *Subtarget) {
25182 EVT VT = N->getValueType(0);
25183 if (!VT.isVector())
25186 SDValue N0 = N->getOperand(0);
25187 SDValue N1 = N->getOperand(1);
25188 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25191 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25192 // both SSE and AVX2 since there is no sign-extended shift right
25193 // operation on a vector with 64-bit elements.
25194 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25195 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25196 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25197 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25198 SDValue N00 = N0.getOperand(0);
25200 // EXTLOAD has a better solution on AVX2,
25201 // it may be replaced with X86ISD::VSEXT node.
25202 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25203 if (!ISD::isNormalLoad(N00.getNode()))
25206 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25207 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25209 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25215 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25216 TargetLowering::DAGCombinerInfo &DCI,
25217 const X86Subtarget *Subtarget) {
25218 SDValue N0 = N->getOperand(0);
25219 EVT VT = N->getValueType(0);
25221 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25222 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25223 // This exposes the sext to the sdivrem lowering, so that it directly extends
25224 // from AH (which we otherwise need to do contortions to access).
25225 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25226 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25228 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25229 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25230 N0.getOperand(0), N0.getOperand(1));
25231 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25232 return R.getValue(1);
25235 if (!DCI.isBeforeLegalizeOps())
25238 if (!Subtarget->hasFp256())
25241 if (VT.isVector() && VT.getSizeInBits() == 256) {
25242 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25250 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25251 const X86Subtarget* Subtarget) {
25253 EVT VT = N->getValueType(0);
25255 // Let legalize expand this if it isn't a legal type yet.
25256 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25259 EVT ScalarVT = VT.getScalarType();
25260 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25261 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25264 SDValue A = N->getOperand(0);
25265 SDValue B = N->getOperand(1);
25266 SDValue C = N->getOperand(2);
25268 bool NegA = (A.getOpcode() == ISD::FNEG);
25269 bool NegB = (B.getOpcode() == ISD::FNEG);
25270 bool NegC = (C.getOpcode() == ISD::FNEG);
25272 // Negative multiplication when NegA xor NegB
25273 bool NegMul = (NegA != NegB);
25275 A = A.getOperand(0);
25277 B = B.getOperand(0);
25279 C = C.getOperand(0);
25283 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25285 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25287 return DAG.getNode(Opcode, dl, VT, A, B, C);
25290 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25291 TargetLowering::DAGCombinerInfo &DCI,
25292 const X86Subtarget *Subtarget) {
25293 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25294 // (and (i32 x86isd::setcc_carry), 1)
25295 // This eliminates the zext. This transformation is necessary because
25296 // ISD::SETCC is always legalized to i8.
25298 SDValue N0 = N->getOperand(0);
25299 EVT VT = N->getValueType(0);
25301 if (N0.getOpcode() == ISD::AND &&
25303 N0.getOperand(0).hasOneUse()) {
25304 SDValue N00 = N0.getOperand(0);
25305 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25306 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25307 if (!C || C->getZExtValue() != 1)
25309 return DAG.getNode(ISD::AND, dl, VT,
25310 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25311 N00.getOperand(0), N00.getOperand(1)),
25312 DAG.getConstant(1, VT));
25316 if (N0.getOpcode() == ISD::TRUNCATE &&
25318 N0.getOperand(0).hasOneUse()) {
25319 SDValue N00 = N0.getOperand(0);
25320 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25321 return DAG.getNode(ISD::AND, dl, VT,
25322 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25323 N00.getOperand(0), N00.getOperand(1)),
25324 DAG.getConstant(1, VT));
25327 if (VT.is256BitVector()) {
25328 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25333 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25334 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25335 // This exposes the zext to the udivrem lowering, so that it directly extends
25336 // from AH (which we otherwise need to do contortions to access).
25337 if (N0.getOpcode() == ISD::UDIVREM &&
25338 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25339 (VT == MVT::i32 || VT == MVT::i64)) {
25340 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25341 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25342 N0.getOperand(0), N0.getOperand(1));
25343 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25344 return R.getValue(1);
25350 // Optimize x == -y --> x+y == 0
25351 // x != -y --> x+y != 0
25352 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25353 const X86Subtarget* Subtarget) {
25354 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25355 SDValue LHS = N->getOperand(0);
25356 SDValue RHS = N->getOperand(1);
25357 EVT VT = N->getValueType(0);
25360 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25362 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25363 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25364 LHS.getValueType(), RHS, LHS.getOperand(1));
25365 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25366 addV, DAG.getConstant(0, addV.getValueType()), CC);
25368 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25370 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25371 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25372 RHS.getValueType(), LHS, RHS.getOperand(1));
25373 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25374 addV, DAG.getConstant(0, addV.getValueType()), CC);
25377 if (VT.getScalarType() == MVT::i1) {
25378 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25379 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25380 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25381 if (!IsSEXT0 && !IsVZero0)
25383 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25384 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25385 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25387 if (!IsSEXT1 && !IsVZero1)
25390 if (IsSEXT0 && IsVZero1) {
25391 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25392 if (CC == ISD::SETEQ)
25393 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25394 return LHS.getOperand(0);
25396 if (IsSEXT1 && IsVZero0) {
25397 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25398 if (CC == ISD::SETEQ)
25399 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25400 return RHS.getOperand(0);
25407 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25408 const X86Subtarget *Subtarget) {
25410 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25411 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25412 "X86insertps is only defined for v4x32");
25414 SDValue Ld = N->getOperand(1);
25415 if (MayFoldLoad(Ld)) {
25416 // Extract the countS bits from the immediate so we can get the proper
25417 // address when narrowing the vector load to a specific element.
25418 // When the second source op is a memory address, interps doesn't use
25419 // countS and just gets an f32 from that address.
25420 unsigned DestIndex =
25421 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25422 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25426 // Create this as a scalar to vector to match the instruction pattern.
25427 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25428 // countS bits are ignored when loading from memory on insertps, which
25429 // means we don't need to explicitly set them to 0.
25430 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25431 LoadScalarToVector, N->getOperand(2));
25434 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25435 // as "sbb reg,reg", since it can be extended without zext and produces
25436 // an all-ones bit which is more useful than 0/1 in some cases.
25437 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25440 return DAG.getNode(ISD::AND, DL, VT,
25441 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25442 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25443 DAG.getConstant(1, VT));
25444 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25445 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25446 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25447 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25450 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25451 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25452 TargetLowering::DAGCombinerInfo &DCI,
25453 const X86Subtarget *Subtarget) {
25455 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25456 SDValue EFLAGS = N->getOperand(1);
25458 if (CC == X86::COND_A) {
25459 // Try to convert COND_A into COND_B in an attempt to facilitate
25460 // materializing "setb reg".
25462 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25463 // cannot take an immediate as its first operand.
25465 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25466 EFLAGS.getValueType().isInteger() &&
25467 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25468 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25469 EFLAGS.getNode()->getVTList(),
25470 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25471 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25472 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25476 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25477 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25479 if (CC == X86::COND_B)
25480 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25484 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25485 if (Flags.getNode()) {
25486 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25487 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25493 // Optimize branch condition evaluation.
25495 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25496 TargetLowering::DAGCombinerInfo &DCI,
25497 const X86Subtarget *Subtarget) {
25499 SDValue Chain = N->getOperand(0);
25500 SDValue Dest = N->getOperand(1);
25501 SDValue EFLAGS = N->getOperand(3);
25502 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25506 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25507 if (Flags.getNode()) {
25508 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25509 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25516 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25517 SelectionDAG &DAG) {
25518 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25519 // optimize away operation when it's from a constant.
25521 // The general transformation is:
25522 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25523 // AND(VECTOR_CMP(x,y), constant2)
25524 // constant2 = UNARYOP(constant)
25526 // Early exit if this isn't a vector operation, the operand of the
25527 // unary operation isn't a bitwise AND, or if the sizes of the operations
25528 // aren't the same.
25529 EVT VT = N->getValueType(0);
25530 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25531 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25532 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25535 // Now check that the other operand of the AND is a constant. We could
25536 // make the transformation for non-constant splats as well, but it's unclear
25537 // that would be a benefit as it would not eliminate any operations, just
25538 // perform one more step in scalar code before moving to the vector unit.
25539 if (BuildVectorSDNode *BV =
25540 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25541 // Bail out if the vector isn't a constant.
25542 if (!BV->isConstant())
25545 // Everything checks out. Build up the new and improved node.
25547 EVT IntVT = BV->getValueType(0);
25548 // Create a new constant of the appropriate type for the transformed
25550 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25551 // The AND node needs bitcasts to/from an integer vector type around it.
25552 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25553 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25554 N->getOperand(0)->getOperand(0), MaskConst);
25555 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25562 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25563 const X86TargetLowering *XTLI) {
25564 // First try to optimize away the conversion entirely when it's
25565 // conditionally from a constant. Vectors only.
25566 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25567 if (Res != SDValue())
25570 // Now move on to more general possibilities.
25571 SDValue Op0 = N->getOperand(0);
25572 EVT InVT = Op0->getValueType(0);
25574 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25575 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25577 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25578 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25579 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25582 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25583 // a 32-bit target where SSE doesn't support i64->FP operations.
25584 if (Op0.getOpcode() == ISD::LOAD) {
25585 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25586 EVT VT = Ld->getValueType(0);
25587 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25588 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25589 !XTLI->getSubtarget()->is64Bit() &&
25591 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25592 Ld->getChain(), Op0, DAG);
25593 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25600 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25601 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25602 X86TargetLowering::DAGCombinerInfo &DCI) {
25603 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25604 // the result is either zero or one (depending on the input carry bit).
25605 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25606 if (X86::isZeroNode(N->getOperand(0)) &&
25607 X86::isZeroNode(N->getOperand(1)) &&
25608 // We don't have a good way to replace an EFLAGS use, so only do this when
25610 SDValue(N, 1).use_empty()) {
25612 EVT VT = N->getValueType(0);
25613 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25614 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25615 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25616 DAG.getConstant(X86::COND_B,MVT::i8),
25618 DAG.getConstant(1, VT));
25619 return DCI.CombineTo(N, Res1, CarryOut);
25625 // fold (add Y, (sete X, 0)) -> adc 0, Y
25626 // (add Y, (setne X, 0)) -> sbb -1, Y
25627 // (sub (sete X, 0), Y) -> sbb 0, Y
25628 // (sub (setne X, 0), Y) -> adc -1, Y
25629 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25632 // Look through ZExts.
25633 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25634 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25637 SDValue SetCC = Ext.getOperand(0);
25638 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25641 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25642 if (CC != X86::COND_E && CC != X86::COND_NE)
25645 SDValue Cmp = SetCC.getOperand(1);
25646 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25647 !X86::isZeroNode(Cmp.getOperand(1)) ||
25648 !Cmp.getOperand(0).getValueType().isInteger())
25651 SDValue CmpOp0 = Cmp.getOperand(0);
25652 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25653 DAG.getConstant(1, CmpOp0.getValueType()));
25655 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25656 if (CC == X86::COND_NE)
25657 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25658 DL, OtherVal.getValueType(), OtherVal,
25659 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25660 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25661 DL, OtherVal.getValueType(), OtherVal,
25662 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25665 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25666 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25667 const X86Subtarget *Subtarget) {
25668 EVT VT = N->getValueType(0);
25669 SDValue Op0 = N->getOperand(0);
25670 SDValue Op1 = N->getOperand(1);
25672 // Try to synthesize horizontal adds from adds of shuffles.
25673 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25674 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25675 isHorizontalBinOp(Op0, Op1, true))
25676 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25678 return OptimizeConditionalInDecrement(N, DAG);
25681 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25682 const X86Subtarget *Subtarget) {
25683 SDValue Op0 = N->getOperand(0);
25684 SDValue Op1 = N->getOperand(1);
25686 // X86 can't encode an immediate LHS of a sub. See if we can push the
25687 // negation into a preceding instruction.
25688 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25689 // If the RHS of the sub is a XOR with one use and a constant, invert the
25690 // immediate. Then add one to the LHS of the sub so we can turn
25691 // X-Y -> X+~Y+1, saving one register.
25692 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25693 isa<ConstantSDNode>(Op1.getOperand(1))) {
25694 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25695 EVT VT = Op0.getValueType();
25696 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25698 DAG.getConstant(~XorC, VT));
25699 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25700 DAG.getConstant(C->getAPIntValue()+1, VT));
25704 // Try to synthesize horizontal adds from adds of shuffles.
25705 EVT VT = N->getValueType(0);
25706 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25707 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25708 isHorizontalBinOp(Op0, Op1, true))
25709 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25711 return OptimizeConditionalInDecrement(N, DAG);
25714 /// performVZEXTCombine - Performs build vector combines
25715 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25716 TargetLowering::DAGCombinerInfo &DCI,
25717 const X86Subtarget *Subtarget) {
25719 MVT VT = N->getSimpleValueType(0);
25720 SDValue Op = N->getOperand(0);
25721 MVT OpVT = Op.getSimpleValueType();
25722 MVT OpEltVT = OpVT.getVectorElementType();
25723 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25725 // (vzext (bitcast (vzext (x)) -> (vzext x)
25727 while (V.getOpcode() == ISD::BITCAST)
25728 V = V.getOperand(0);
25730 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25731 MVT InnerVT = V.getSimpleValueType();
25732 MVT InnerEltVT = InnerVT.getVectorElementType();
25734 // If the element sizes match exactly, we can just do one larger vzext. This
25735 // is always an exact type match as vzext operates on integer types.
25736 if (OpEltVT == InnerEltVT) {
25737 assert(OpVT == InnerVT && "Types must match for vzext!");
25738 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25741 // The only other way we can combine them is if only a single element of the
25742 // inner vzext is used in the input to the outer vzext.
25743 if (InnerEltVT.getSizeInBits() < InputBits)
25746 // In this case, the inner vzext is completely dead because we're going to
25747 // only look at bits inside of the low element. Just do the outer vzext on
25748 // a bitcast of the input to the inner.
25749 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25750 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25753 // Check if we can bypass extracting and re-inserting an element of an input
25754 // vector. Essentialy:
25755 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25756 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25757 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25758 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25759 SDValue ExtractedV = V.getOperand(0);
25760 SDValue OrigV = ExtractedV.getOperand(0);
25761 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25762 if (ExtractIdx->getZExtValue() == 0) {
25763 MVT OrigVT = OrigV.getSimpleValueType();
25764 // Extract a subvector if necessary...
25765 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25766 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25767 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25768 OrigVT.getVectorNumElements() / Ratio);
25769 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25770 DAG.getIntPtrConstant(0));
25772 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25773 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25780 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25781 DAGCombinerInfo &DCI) const {
25782 SelectionDAG &DAG = DCI.DAG;
25783 switch (N->getOpcode()) {
25785 case ISD::EXTRACT_VECTOR_ELT:
25786 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25789 case X86ISD::SHRUNKBLEND:
25790 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25791 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25792 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25793 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25794 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25795 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25798 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25799 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25800 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25801 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25802 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25803 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25804 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25805 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25806 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25808 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25810 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25811 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25812 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25813 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25814 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25815 case ISD::ANY_EXTEND:
25816 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25817 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25818 case ISD::SIGN_EXTEND_INREG:
25819 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25820 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25821 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25822 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25823 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25824 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25825 case X86ISD::SHUFP: // Handle all target specific shuffles
25826 case X86ISD::PALIGNR:
25827 case X86ISD::UNPCKH:
25828 case X86ISD::UNPCKL:
25829 case X86ISD::MOVHLPS:
25830 case X86ISD::MOVLHPS:
25831 case X86ISD::PSHUFB:
25832 case X86ISD::PSHUFD:
25833 case X86ISD::PSHUFHW:
25834 case X86ISD::PSHUFLW:
25835 case X86ISD::MOVSS:
25836 case X86ISD::MOVSD:
25837 case X86ISD::VPERMILPI:
25838 case X86ISD::VPERM2X128:
25839 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25840 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25841 case ISD::INTRINSIC_WO_CHAIN:
25842 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25843 case X86ISD::INSERTPS:
25844 return PerformINSERTPSCombine(N, DAG, Subtarget);
25845 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25851 /// isTypeDesirableForOp - Return true if the target has native support for
25852 /// the specified value type and it is 'desirable' to use the type for the
25853 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25854 /// instruction encodings are longer and some i16 instructions are slow.
25855 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25856 if (!isTypeLegal(VT))
25858 if (VT != MVT::i16)
25865 case ISD::SIGN_EXTEND:
25866 case ISD::ZERO_EXTEND:
25867 case ISD::ANY_EXTEND:
25880 /// IsDesirableToPromoteOp - This method query the target whether it is
25881 /// beneficial for dag combiner to promote the specified node. If true, it
25882 /// should return the desired promotion type by reference.
25883 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25884 EVT VT = Op.getValueType();
25885 if (VT != MVT::i16)
25888 bool Promote = false;
25889 bool Commute = false;
25890 switch (Op.getOpcode()) {
25893 LoadSDNode *LD = cast<LoadSDNode>(Op);
25894 // If the non-extending load has a single use and it's not live out, then it
25895 // might be folded.
25896 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25897 Op.hasOneUse()*/) {
25898 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25899 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25900 // The only case where we'd want to promote LOAD (rather then it being
25901 // promoted as an operand is when it's only use is liveout.
25902 if (UI->getOpcode() != ISD::CopyToReg)
25909 case ISD::SIGN_EXTEND:
25910 case ISD::ZERO_EXTEND:
25911 case ISD::ANY_EXTEND:
25916 SDValue N0 = Op.getOperand(0);
25917 // Look out for (store (shl (load), x)).
25918 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25931 SDValue N0 = Op.getOperand(0);
25932 SDValue N1 = Op.getOperand(1);
25933 if (!Commute && MayFoldLoad(N1))
25935 // Avoid disabling potential load folding opportunities.
25936 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25938 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25948 //===----------------------------------------------------------------------===//
25949 // X86 Inline Assembly Support
25950 //===----------------------------------------------------------------------===//
25953 // Helper to match a string separated by whitespace.
25954 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25955 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25957 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25958 StringRef piece(*args[i]);
25959 if (!s.startswith(piece)) // Check if the piece matches.
25962 s = s.substr(piece.size());
25963 StringRef::size_type pos = s.find_first_not_of(" \t");
25964 if (pos == 0) // We matched a prefix.
25972 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25975 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25977 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25978 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25979 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25980 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25982 if (AsmPieces.size() == 3)
25984 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25991 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25992 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25994 std::string AsmStr = IA->getAsmString();
25996 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25997 if (!Ty || Ty->getBitWidth() % 16 != 0)
26000 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26001 SmallVector<StringRef, 4> AsmPieces;
26002 SplitString(AsmStr, AsmPieces, ";\n");
26004 switch (AsmPieces.size()) {
26005 default: return false;
26007 // FIXME: this should verify that we are targeting a 486 or better. If not,
26008 // we will turn this bswap into something that will be lowered to logical
26009 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26010 // lower so don't worry about this.
26012 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
26013 matchAsm(AsmPieces[0], "bswapl", "$0") ||
26014 matchAsm(AsmPieces[0], "bswapq", "$0") ||
26015 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
26016 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
26017 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
26018 // No need to check constraints, nothing other than the equivalent of
26019 // "=r,0" would be valid here.
26020 return IntrinsicLowering::LowerToByteSwap(CI);
26023 // rorw $$8, ${0:w} --> llvm.bswap.i16
26024 if (CI->getType()->isIntegerTy(16) &&
26025 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26026 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
26027 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
26029 const std::string &ConstraintsStr = IA->getConstraintString();
26030 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26031 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26032 if (clobbersFlagRegisters(AsmPieces))
26033 return IntrinsicLowering::LowerToByteSwap(CI);
26037 if (CI->getType()->isIntegerTy(32) &&
26038 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26039 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
26040 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
26041 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
26043 const std::string &ConstraintsStr = IA->getConstraintString();
26044 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26045 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26046 if (clobbersFlagRegisters(AsmPieces))
26047 return IntrinsicLowering::LowerToByteSwap(CI);
26050 if (CI->getType()->isIntegerTy(64)) {
26051 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26052 if (Constraints.size() >= 2 &&
26053 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26054 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26055 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26056 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
26057 matchAsm(AsmPieces[1], "bswap", "%edx") &&
26058 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
26059 return IntrinsicLowering::LowerToByteSwap(CI);
26067 /// getConstraintType - Given a constraint letter, return the type of
26068 /// constraint it is for this target.
26069 X86TargetLowering::ConstraintType
26070 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
26071 if (Constraint.size() == 1) {
26072 switch (Constraint[0]) {
26083 return C_RegisterClass;
26107 return TargetLowering::getConstraintType(Constraint);
26110 /// Examine constraint type and operand type and determine a weight value.
26111 /// This object must already have been set up with the operand type
26112 /// and the current alternative constraint selected.
26113 TargetLowering::ConstraintWeight
26114 X86TargetLowering::getSingleConstraintMatchWeight(
26115 AsmOperandInfo &info, const char *constraint) const {
26116 ConstraintWeight weight = CW_Invalid;
26117 Value *CallOperandVal = info.CallOperandVal;
26118 // If we don't have a value, we can't do a match,
26119 // but allow it at the lowest weight.
26120 if (!CallOperandVal)
26122 Type *type = CallOperandVal->getType();
26123 // Look at the constraint type.
26124 switch (*constraint) {
26126 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26137 if (CallOperandVal->getType()->isIntegerTy())
26138 weight = CW_SpecificReg;
26143 if (type->isFloatingPointTy())
26144 weight = CW_SpecificReg;
26147 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26148 weight = CW_SpecificReg;
26152 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26153 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26154 weight = CW_Register;
26157 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26158 if (C->getZExtValue() <= 31)
26159 weight = CW_Constant;
26163 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26164 if (C->getZExtValue() <= 63)
26165 weight = CW_Constant;
26169 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26170 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26171 weight = CW_Constant;
26175 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26176 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26177 weight = CW_Constant;
26181 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26182 if (C->getZExtValue() <= 3)
26183 weight = CW_Constant;
26187 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26188 if (C->getZExtValue() <= 0xff)
26189 weight = CW_Constant;
26194 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26195 weight = CW_Constant;
26199 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26200 if ((C->getSExtValue() >= -0x80000000LL) &&
26201 (C->getSExtValue() <= 0x7fffffffLL))
26202 weight = CW_Constant;
26206 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26207 if (C->getZExtValue() <= 0xffffffff)
26208 weight = CW_Constant;
26215 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26216 /// with another that has more specific requirements based on the type of the
26217 /// corresponding operand.
26218 const char *X86TargetLowering::
26219 LowerXConstraint(EVT ConstraintVT) const {
26220 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26221 // 'f' like normal targets.
26222 if (ConstraintVT.isFloatingPoint()) {
26223 if (Subtarget->hasSSE2())
26225 if (Subtarget->hasSSE1())
26229 return TargetLowering::LowerXConstraint(ConstraintVT);
26232 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26233 /// vector. If it is invalid, don't add anything to Ops.
26234 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26235 std::string &Constraint,
26236 std::vector<SDValue>&Ops,
26237 SelectionDAG &DAG) const {
26240 // Only support length 1 constraints for now.
26241 if (Constraint.length() > 1) return;
26243 char ConstraintLetter = Constraint[0];
26244 switch (ConstraintLetter) {
26247 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26248 if (C->getZExtValue() <= 31) {
26249 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26255 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26256 if (C->getZExtValue() <= 63) {
26257 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26264 if (isInt<8>(C->getSExtValue())) {
26265 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26271 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26272 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26273 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26274 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
26280 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26281 if (C->getZExtValue() <= 3) {
26282 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26289 if (C->getZExtValue() <= 255) {
26290 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26296 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26297 if (C->getZExtValue() <= 127) {
26298 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26304 // 32-bit signed value
26305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26306 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26307 C->getSExtValue())) {
26308 // Widen to 64 bits here to get it sign extended.
26309 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26312 // FIXME gcc accepts some relocatable values here too, but only in certain
26313 // memory models; it's complicated.
26318 // 32-bit unsigned value
26319 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26320 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26321 C->getZExtValue())) {
26322 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26326 // FIXME gcc accepts some relocatable values here too, but only in certain
26327 // memory models; it's complicated.
26331 // Literal immediates are always ok.
26332 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26333 // Widen to 64 bits here to get it sign extended.
26334 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26338 // In any sort of PIC mode addresses need to be computed at runtime by
26339 // adding in a register or some sort of table lookup. These can't
26340 // be used as immediates.
26341 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26344 // If we are in non-pic codegen mode, we allow the address of a global (with
26345 // an optional displacement) to be used with 'i'.
26346 GlobalAddressSDNode *GA = nullptr;
26347 int64_t Offset = 0;
26349 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26351 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26352 Offset += GA->getOffset();
26354 } else if (Op.getOpcode() == ISD::ADD) {
26355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26356 Offset += C->getZExtValue();
26357 Op = Op.getOperand(0);
26360 } else if (Op.getOpcode() == ISD::SUB) {
26361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26362 Offset += -C->getZExtValue();
26363 Op = Op.getOperand(0);
26368 // Otherwise, this isn't something we can handle, reject it.
26372 const GlobalValue *GV = GA->getGlobal();
26373 // If we require an extra load to get this address, as in PIC mode, we
26374 // can't accept it.
26375 if (isGlobalStubReference(
26376 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26379 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26380 GA->getValueType(0), Offset);
26385 if (Result.getNode()) {
26386 Ops.push_back(Result);
26389 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26392 std::pair<unsigned, const TargetRegisterClass*>
26393 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26395 // First, see if this is a constraint that directly corresponds to an LLVM
26397 if (Constraint.size() == 1) {
26398 // GCC Constraint Letters
26399 switch (Constraint[0]) {
26401 // TODO: Slight differences here in allocation order and leaving
26402 // RIP in the class. Do they matter any more here than they do
26403 // in the normal allocation?
26404 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26405 if (Subtarget->is64Bit()) {
26406 if (VT == MVT::i32 || VT == MVT::f32)
26407 return std::make_pair(0U, &X86::GR32RegClass);
26408 if (VT == MVT::i16)
26409 return std::make_pair(0U, &X86::GR16RegClass);
26410 if (VT == MVT::i8 || VT == MVT::i1)
26411 return std::make_pair(0U, &X86::GR8RegClass);
26412 if (VT == MVT::i64 || VT == MVT::f64)
26413 return std::make_pair(0U, &X86::GR64RegClass);
26416 // 32-bit fallthrough
26417 case 'Q': // Q_REGS
26418 if (VT == MVT::i32 || VT == MVT::f32)
26419 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26420 if (VT == MVT::i16)
26421 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26422 if (VT == MVT::i8 || VT == MVT::i1)
26423 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26424 if (VT == MVT::i64)
26425 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26427 case 'r': // GENERAL_REGS
26428 case 'l': // INDEX_REGS
26429 if (VT == MVT::i8 || VT == MVT::i1)
26430 return std::make_pair(0U, &X86::GR8RegClass);
26431 if (VT == MVT::i16)
26432 return std::make_pair(0U, &X86::GR16RegClass);
26433 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26434 return std::make_pair(0U, &X86::GR32RegClass);
26435 return std::make_pair(0U, &X86::GR64RegClass);
26436 case 'R': // LEGACY_REGS
26437 if (VT == MVT::i8 || VT == MVT::i1)
26438 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26439 if (VT == MVT::i16)
26440 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26441 if (VT == MVT::i32 || !Subtarget->is64Bit())
26442 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26443 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26444 case 'f': // FP Stack registers.
26445 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26446 // value to the correct fpstack register class.
26447 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26448 return std::make_pair(0U, &X86::RFP32RegClass);
26449 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26450 return std::make_pair(0U, &X86::RFP64RegClass);
26451 return std::make_pair(0U, &X86::RFP80RegClass);
26452 case 'y': // MMX_REGS if MMX allowed.
26453 if (!Subtarget->hasMMX()) break;
26454 return std::make_pair(0U, &X86::VR64RegClass);
26455 case 'Y': // SSE_REGS if SSE2 allowed
26456 if (!Subtarget->hasSSE2()) break;
26458 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26459 if (!Subtarget->hasSSE1()) break;
26461 switch (VT.SimpleTy) {
26463 // Scalar SSE types.
26466 return std::make_pair(0U, &X86::FR32RegClass);
26469 return std::make_pair(0U, &X86::FR64RegClass);
26477 return std::make_pair(0U, &X86::VR128RegClass);
26485 return std::make_pair(0U, &X86::VR256RegClass);
26490 return std::make_pair(0U, &X86::VR512RegClass);
26496 // Use the default implementation in TargetLowering to convert the register
26497 // constraint into a member of a register class.
26498 std::pair<unsigned, const TargetRegisterClass*> Res;
26499 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26501 // Not found as a standard register?
26503 // Map st(0) -> st(7) -> ST0
26504 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26505 tolower(Constraint[1]) == 's' &&
26506 tolower(Constraint[2]) == 't' &&
26507 Constraint[3] == '(' &&
26508 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26509 Constraint[5] == ')' &&
26510 Constraint[6] == '}') {
26512 Res.first = X86::FP0+Constraint[4]-'0';
26513 Res.second = &X86::RFP80RegClass;
26517 // GCC allows "st(0)" to be called just plain "st".
26518 if (StringRef("{st}").equals_lower(Constraint)) {
26519 Res.first = X86::FP0;
26520 Res.second = &X86::RFP80RegClass;
26525 if (StringRef("{flags}").equals_lower(Constraint)) {
26526 Res.first = X86::EFLAGS;
26527 Res.second = &X86::CCRRegClass;
26531 // 'A' means EAX + EDX.
26532 if (Constraint == "A") {
26533 Res.first = X86::EAX;
26534 Res.second = &X86::GR32_ADRegClass;
26540 // Otherwise, check to see if this is a register class of the wrong value
26541 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26542 // turn into {ax},{dx}.
26543 if (Res.second->hasType(VT))
26544 return Res; // Correct type already, nothing to do.
26546 // All of the single-register GCC register classes map their values onto
26547 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26548 // really want an 8-bit or 32-bit register, map to the appropriate register
26549 // class and return the appropriate register.
26550 if (Res.second == &X86::GR16RegClass) {
26551 if (VT == MVT::i8 || VT == MVT::i1) {
26552 unsigned DestReg = 0;
26553 switch (Res.first) {
26555 case X86::AX: DestReg = X86::AL; break;
26556 case X86::DX: DestReg = X86::DL; break;
26557 case X86::CX: DestReg = X86::CL; break;
26558 case X86::BX: DestReg = X86::BL; break;
26561 Res.first = DestReg;
26562 Res.second = &X86::GR8RegClass;
26564 } else if (VT == MVT::i32 || VT == MVT::f32) {
26565 unsigned DestReg = 0;
26566 switch (Res.first) {
26568 case X86::AX: DestReg = X86::EAX; break;
26569 case X86::DX: DestReg = X86::EDX; break;
26570 case X86::CX: DestReg = X86::ECX; break;
26571 case X86::BX: DestReg = X86::EBX; break;
26572 case X86::SI: DestReg = X86::ESI; break;
26573 case X86::DI: DestReg = X86::EDI; break;
26574 case X86::BP: DestReg = X86::EBP; break;
26575 case X86::SP: DestReg = X86::ESP; break;
26578 Res.first = DestReg;
26579 Res.second = &X86::GR32RegClass;
26581 } else if (VT == MVT::i64 || VT == MVT::f64) {
26582 unsigned DestReg = 0;
26583 switch (Res.first) {
26585 case X86::AX: DestReg = X86::RAX; break;
26586 case X86::DX: DestReg = X86::RDX; break;
26587 case X86::CX: DestReg = X86::RCX; break;
26588 case X86::BX: DestReg = X86::RBX; break;
26589 case X86::SI: DestReg = X86::RSI; break;
26590 case X86::DI: DestReg = X86::RDI; break;
26591 case X86::BP: DestReg = X86::RBP; break;
26592 case X86::SP: DestReg = X86::RSP; break;
26595 Res.first = DestReg;
26596 Res.second = &X86::GR64RegClass;
26599 } else if (Res.second == &X86::FR32RegClass ||
26600 Res.second == &X86::FR64RegClass ||
26601 Res.second == &X86::VR128RegClass ||
26602 Res.second == &X86::VR256RegClass ||
26603 Res.second == &X86::FR32XRegClass ||
26604 Res.second == &X86::FR64XRegClass ||
26605 Res.second == &X86::VR128XRegClass ||
26606 Res.second == &X86::VR256XRegClass ||
26607 Res.second == &X86::VR512RegClass) {
26608 // Handle references to XMM physical registers that got mapped into the
26609 // wrong class. This can happen with constraints like {xmm0} where the
26610 // target independent register mapper will just pick the first match it can
26611 // find, ignoring the required type.
26613 if (VT == MVT::f32 || VT == MVT::i32)
26614 Res.second = &X86::FR32RegClass;
26615 else if (VT == MVT::f64 || VT == MVT::i64)
26616 Res.second = &X86::FR64RegClass;
26617 else if (X86::VR128RegClass.hasType(VT))
26618 Res.second = &X86::VR128RegClass;
26619 else if (X86::VR256RegClass.hasType(VT))
26620 Res.second = &X86::VR256RegClass;
26621 else if (X86::VR512RegClass.hasType(VT))
26622 Res.second = &X86::VR512RegClass;
26628 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26630 // Scaling factors are not free at all.
26631 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26632 // will take 2 allocations in the out of order engine instead of 1
26633 // for plain addressing mode, i.e. inst (reg1).
26635 // vaddps (%rsi,%drx), %ymm0, %ymm1
26636 // Requires two allocations (one for the load, one for the computation)
26638 // vaddps (%rsi), %ymm0, %ymm1
26639 // Requires just 1 allocation, i.e., freeing allocations for other operations
26640 // and having less micro operations to execute.
26642 // For some X86 architectures, this is even worse because for instance for
26643 // stores, the complex addressing mode forces the instruction to use the
26644 // "load" ports instead of the dedicated "store" port.
26645 // E.g., on Haswell:
26646 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26647 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26648 if (isLegalAddressingMode(AM, Ty))
26649 // Scale represents reg2 * scale, thus account for 1
26650 // as soon as we use a second register.
26651 return AM.Scale != 0;
26655 bool X86TargetLowering::isTargetFTOL() const {
26656 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();