1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec,
69 EVT VT = Vec.getValueType();
70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
71 EVT ElVT = VT.getVectorElementType();
72 int Factor = VT.getSizeInBits()/128;
73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
74 VT.getVectorNumElements()/Factor);
76 // Extract from UNDEF is UNDEF.
77 if (Vec.getOpcode() == ISD::UNDEF)
78 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
80 if (isa<ConstantSDNode>(Idx)) {
81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
84 // we can match to VEXTRACTF128.
85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
87 // This is the index of the first element of the 128-bit chunk
89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
102 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
103 /// sets things up to match to an AVX VINSERTF128 instruction or a
104 /// simple superregister reference. Idx is an index in the 128 bits
105 /// we want. It need not be aligned to a 128-bit bounday. That makes
106 /// lowering INSERT_VECTOR_ELT operations easier.
107 static SDValue Insert128BitVector(SDValue Result,
112 if (isa<ConstantSDNode>(Idx)) {
113 EVT VT = Vec.getValueType();
114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
116 EVT ElVT = VT.getVectorElementType();
117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
118 EVT ResultVT = Result.getValueType();
120 // Insert the relevant 128 bits.
121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
123 // This is the index of the first element of the 128-bit chunk
125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X8664_MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetELF())
148 return new TargetLoweringObjectFileELF();
149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
150 return new TargetLoweringObjectFileCOFF();
151 llvm_unreachable("unknown subtarget type");
154 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
155 : TargetLowering(TM, createTLOF(TM)) {
156 Subtarget = &TM.getSubtarget<X86Subtarget>();
157 X86ScalarSSEf64 = Subtarget->hasSSE2();
158 X86ScalarSSEf32 = Subtarget->hasSSE1();
159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
161 RegInfo = TM.getRegisterInfo();
162 TD = getTargetData();
164 // Set up the TargetLowering object.
165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
167 // X86 is weird, it always uses i8 for shift amounts and setcc results.
168 setBooleanContents(ZeroOrOneBooleanContent);
169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
172 // For 64-bit since we have so many registers use the ILP scheduler, for
173 // 32-bit code use the register pressure specific scheduling.
174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
175 if (Subtarget->is64Bit())
176 setSchedulingPreference(Sched::ILP);
177 else if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::Hybrid);
180 setSchedulingPreference(Sched::RegPressure);
181 setStackPointerRegisterToSaveRestore(X86StackPtr);
183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
184 // Setup Windows compiler runtime calls.
185 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
187 setLibcallName(RTLIB::SREM_I64, "_allrem");
188 setLibcallName(RTLIB::UREM_I64, "_aullrem");
189 setLibcallName(RTLIB::MUL_I64, "_allmul");
190 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
191 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
192 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
198 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
201 if (Subtarget->isTargetDarwin()) {
202 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
203 setUseUnderscoreSetJmp(false);
204 setUseUnderscoreLongJmp(false);
205 } else if (Subtarget->isTargetMingw()) {
206 // MS runtime is weird: it exports _setjmp, but longjmp!
207 setUseUnderscoreSetJmp(true);
208 setUseUnderscoreLongJmp(false);
210 setUseUnderscoreSetJmp(true);
211 setUseUnderscoreLongJmp(true);
214 // Set up the register classes.
215 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
216 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
217 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
218 if (Subtarget->is64Bit())
219 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
221 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
223 // We don't accept any truncstore of integer registers.
224 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
226 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
227 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
228 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
229 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
231 // SETOEQ and SETUNE require checking two conditions.
232 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
234 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
239 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
241 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
243 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
245 if (Subtarget->is64Bit()) {
246 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
248 } else if (!TM.Options.UseSoftFloat) {
249 // We have an algorithm for SSE2->double, and we turn this into a
250 // 64-bit FILD followed by conditional FADD for other targets.
251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
252 // We have an algorithm for SSE2, and we turn this into a 64-bit
253 // FILD for other targets.
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
257 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
259 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
260 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
262 if (!TM.Options.UseSoftFloat) {
263 // SSE has no i16 to fp conversion, only i32
264 if (X86ScalarSSEf32) {
265 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
266 // f32 and f64 cases are Legal, f80 case is not
267 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
277 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
278 // are Legal, f80 is custom lowered.
279 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
280 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
282 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
284 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
285 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
287 if (X86ScalarSSEf32) {
288 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
289 // f32 and f64 cases are Legal, f80 case is not
290 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 // Handle FP_TO_UINT by promoting the destination to a larger signed
298 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
300 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
302 if (Subtarget->is64Bit()) {
303 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
305 } else if (!TM.Options.UseSoftFloat) {
306 // Since AVX is a superset of SSE3, only check for SSE here.
307 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
308 // Expand FP_TO_UINT into a select.
309 // FIXME: We would like to use a Custom expander here eventually to do
310 // the optimal thing for SSE vs. the default expansion in the legalizer.
311 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
313 // With SSE3 we can use fisttpll to convert to a signed i64; without
314 // SSE, we're stuck with a fistpll.
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
318 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
319 if (!X86ScalarSSEf64) {
320 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
321 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
322 if (Subtarget->is64Bit()) {
323 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
324 // Without SSE, i64->f64 goes through memory.
325 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
329 // Scalar integer divide and remainder are lowered to use operations that
330 // produce two results, to match the available instructions. This exposes
331 // the two-result form to trivial CSE, which is able to combine x/y and x%y
332 // into a single instruction.
334 // Scalar integer multiply-high is also lowered to use two-result
335 // operations, to match the available instructions. However, plain multiply
336 // (low) operations are left as Legal, as there are single-result
337 // instructions for this in x86. Using the two-result multiply instructions
338 // when both high and low results are needed must be arranged by dagcombine.
339 for (unsigned i = 0, e = 4; i != e; ++i) {
341 setOperationAction(ISD::MULHS, VT, Expand);
342 setOperationAction(ISD::MULHU, VT, Expand);
343 setOperationAction(ISD::SDIV, VT, Expand);
344 setOperationAction(ISD::UDIV, VT, Expand);
345 setOperationAction(ISD::SREM, VT, Expand);
346 setOperationAction(ISD::UREM, VT, Expand);
348 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
349 setOperationAction(ISD::ADDC, VT, Custom);
350 setOperationAction(ISD::ADDE, VT, Custom);
351 setOperationAction(ISD::SUBC, VT, Custom);
352 setOperationAction(ISD::SUBE, VT, Custom);
355 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
356 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
357 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
358 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
359 if (Subtarget->is64Bit())
360 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
361 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
362 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
363 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
364 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
365 setOperationAction(ISD::FREM , MVT::f32 , Expand);
366 setOperationAction(ISD::FREM , MVT::f64 , Expand);
367 setOperationAction(ISD::FREM , MVT::f80 , Expand);
368 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
370 // Promote the i8 variants and force them on up to i32 which has a shorter
372 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
373 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
374 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
375 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
376 if (Subtarget->hasBMI()) {
377 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
378 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
379 if (Subtarget->is64Bit())
380 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
382 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
383 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
388 if (Subtarget->hasLZCNT()) {
389 // When promoting the i8 variants, force them to i32 for a shorter
391 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
392 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
393 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
394 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
395 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
396 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
397 if (Subtarget->is64Bit())
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
400 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
401 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
402 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
406 if (Subtarget->is64Bit()) {
407 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
412 if (Subtarget->hasPOPCNT()) {
413 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
415 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
416 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
417 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
418 if (Subtarget->is64Bit())
419 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
422 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
423 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
425 // These should be promoted to a larger select which is supported.
426 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
427 // X86 wants to expand cmov itself.
428 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
429 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
430 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
431 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
432 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
433 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
434 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
435 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
436 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
437 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
438 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
439 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
440 if (Subtarget->is64Bit()) {
441 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
442 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
444 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
447 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
448 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
449 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
450 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
451 if (Subtarget->is64Bit())
452 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
453 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
454 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
455 if (Subtarget->is64Bit()) {
456 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
459 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
460 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
462 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
463 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
468 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
469 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
472 if (Subtarget->hasSSE1())
473 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
475 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
476 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
478 // On X86 and X86-64, atomic operations are lowered to locked instructions.
479 // Locked instructions, in turn, have implicit fence semantics (all memory
480 // operations are flushed before issuing the locked instruction, and they
481 // are not buffered), so we can fold away the common pattern of
482 // fence-atomic-fence.
483 setShouldFoldAtomicFences(true);
485 // Expand certain atomics
486 for (unsigned i = 0, e = 4; i != e; ++i) {
488 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
489 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
490 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
493 if (!Subtarget->is64Bit()) {
494 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
495 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
496 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
497 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
498 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
499 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
504 if (Subtarget->hasCmpxchg16b()) {
505 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
508 // FIXME - use subtarget debug flags
509 if (!Subtarget->isTargetDarwin() &&
510 !Subtarget->isTargetELF() &&
511 !Subtarget->isTargetCygMing()) {
512 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
515 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
516 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
517 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
518 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
519 if (Subtarget->is64Bit()) {
520 setExceptionPointerRegister(X86::RAX);
521 setExceptionSelectorRegister(X86::RDX);
523 setExceptionPointerRegister(X86::EAX);
524 setExceptionSelectorRegister(X86::EDX);
526 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
527 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
529 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
530 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
532 setOperationAction(ISD::TRAP, MVT::Other, Legal);
534 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
535 setOperationAction(ISD::VASTART , MVT::Other, Custom);
536 setOperationAction(ISD::VAEND , MVT::Other, Expand);
537 if (Subtarget->is64Bit()) {
538 setOperationAction(ISD::VAARG , MVT::Other, Custom);
539 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
541 setOperationAction(ISD::VAARG , MVT::Other, Expand);
542 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
545 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
546 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
548 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
549 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
550 MVT::i64 : MVT::i32, Custom);
551 else if (TM.Options.EnableSegmentedStacks)
552 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
553 MVT::i64 : MVT::i32, Custom);
555 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
556 MVT::i64 : MVT::i32, Expand);
558 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
559 // f32 and f64 use SSE.
560 // Set up the FP register classes.
561 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
562 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
564 // Use ANDPD to simulate FABS.
565 setOperationAction(ISD::FABS , MVT::f64, Custom);
566 setOperationAction(ISD::FABS , MVT::f32, Custom);
568 // Use XORP to simulate FNEG.
569 setOperationAction(ISD::FNEG , MVT::f64, Custom);
570 setOperationAction(ISD::FNEG , MVT::f32, Custom);
572 // Use ANDPD and ORPD to simulate FCOPYSIGN.
573 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
574 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
576 // Lower this to FGETSIGNx86 plus an AND.
577 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
578 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
580 // We don't support sin/cos/fmod
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSIN , MVT::f32, Expand);
584 setOperationAction(ISD::FCOS , MVT::f32, Expand);
586 // Expand FP immediates into loads from the stack, except for the special
588 addLegalFPImmediate(APFloat(+0.0)); // xorpd
589 addLegalFPImmediate(APFloat(+0.0f)); // xorps
590 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
591 // Use SSE for f32, x87 for f64.
592 // Set up the FP register classes.
593 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
594 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
596 // Use ANDPS to simulate FABS.
597 setOperationAction(ISD::FABS , MVT::f32, Custom);
599 // Use XORP to simulate FNEG.
600 setOperationAction(ISD::FNEG , MVT::f32, Custom);
602 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
604 // Use ANDPS and ORPS to simulate FCOPYSIGN.
605 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
606 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
608 // We don't support sin/cos/fmod
609 setOperationAction(ISD::FSIN , MVT::f32, Expand);
610 setOperationAction(ISD::FCOS , MVT::f32, Expand);
612 // Special cases we handle for FP constants.
613 addLegalFPImmediate(APFloat(+0.0f)); // xorps
614 addLegalFPImmediate(APFloat(+0.0)); // FLD0
615 addLegalFPImmediate(APFloat(+1.0)); // FLD1
616 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
617 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
619 if (!TM.Options.UnsafeFPMath) {
620 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
621 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
623 } else if (!TM.Options.UseSoftFloat) {
624 // f32 and f64 in x87.
625 // Set up the FP register classes.
626 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
627 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
629 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
630 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
631 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
632 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
634 if (!TM.Options.UnsafeFPMath) {
635 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
636 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
638 addLegalFPImmediate(APFloat(+0.0)); // FLD0
639 addLegalFPImmediate(APFloat(+1.0)); // FLD1
640 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
641 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
642 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
643 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
644 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
645 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
648 // We don't support FMA.
649 setOperationAction(ISD::FMA, MVT::f64, Expand);
650 setOperationAction(ISD::FMA, MVT::f32, Expand);
652 // Long double always uses X87.
653 if (!TM.Options.UseSoftFloat) {
654 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
655 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
656 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
658 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
659 addLegalFPImmediate(TmpFlt); // FLD0
661 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
664 APFloat TmpFlt2(+1.0);
665 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
667 addLegalFPImmediate(TmpFlt2); // FLD1
668 TmpFlt2.changeSign();
669 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
672 if (!TM.Options.UnsafeFPMath) {
673 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
674 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
677 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
678 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
679 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
680 setOperationAction(ISD::FRINT, MVT::f80, Expand);
681 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
682 setOperationAction(ISD::FMA, MVT::f80, Expand);
685 // Always use a library call for pow.
686 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
687 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
688 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
690 setOperationAction(ISD::FLOG, MVT::f80, Expand);
691 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
692 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
693 setOperationAction(ISD::FEXP, MVT::f80, Expand);
694 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
696 // First set operation action for all vector types to either promote
697 // (for widening) or expand (for scalarization). Then we will selectively
698 // turn on ones that can be effectively codegen'd.
699 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
700 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
701 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
716 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
718 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
719 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
753 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
758 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
759 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
760 setTruncStoreAction((MVT::SimpleValueType)VT,
761 (MVT::SimpleValueType)InnerVT, Expand);
762 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
763 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
764 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
767 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
768 // with -msoft-float, disable use of MMX as well.
769 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
770 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
771 // No operations on x86mmx supported, everything uses intrinsics.
774 // MMX-sized vectors (other than x86mmx) are expected to be expanded
775 // into smaller operations.
776 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
777 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
778 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
779 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
780 setOperationAction(ISD::AND, MVT::v8i8, Expand);
781 setOperationAction(ISD::AND, MVT::v4i16, Expand);
782 setOperationAction(ISD::AND, MVT::v2i32, Expand);
783 setOperationAction(ISD::AND, MVT::v1i64, Expand);
784 setOperationAction(ISD::OR, MVT::v8i8, Expand);
785 setOperationAction(ISD::OR, MVT::v4i16, Expand);
786 setOperationAction(ISD::OR, MVT::v2i32, Expand);
787 setOperationAction(ISD::OR, MVT::v1i64, Expand);
788 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
789 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
790 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
791 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
792 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
793 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
794 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
795 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
796 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
797 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
798 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
799 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
800 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
801 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
802 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
803 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
804 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
806 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
807 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
809 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
810 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
811 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
812 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
813 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
814 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
815 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
816 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
817 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
818 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
819 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
820 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
823 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
824 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
826 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
827 // registers cannot be used even for integer operations.
828 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
829 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
830 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
831 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
833 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
834 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
835 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
836 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
837 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
838 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
839 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
840 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
841 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
843 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
844 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
845 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
846 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
847 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
848 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
850 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
851 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
852 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
853 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
855 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
856 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
857 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
858 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
859 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
861 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
862 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
863 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
864 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
865 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
867 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
868 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
869 EVT VT = (MVT::SimpleValueType)i;
870 // Do not attempt to custom lower non-power-of-2 vectors
871 if (!isPowerOf2_32(VT.getVectorNumElements()))
873 // Do not attempt to custom lower non-128-bit vectors
874 if (!VT.is128BitVector())
876 setOperationAction(ISD::BUILD_VECTOR,
877 VT.getSimpleVT().SimpleTy, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE,
879 VT.getSimpleVT().SimpleTy, Custom);
880 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
881 VT.getSimpleVT().SimpleTy, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
888 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
891 if (Subtarget->is64Bit()) {
892 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
893 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
896 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
897 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
898 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
901 // Do not attempt to promote non-128-bit vectors
902 if (!VT.is128BitVector())
905 setOperationAction(ISD::AND, SVT, Promote);
906 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
907 setOperationAction(ISD::OR, SVT, Promote);
908 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
909 setOperationAction(ISD::XOR, SVT, Promote);
910 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
911 setOperationAction(ISD::LOAD, SVT, Promote);
912 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
913 setOperationAction(ISD::SELECT, SVT, Promote);
914 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
917 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
919 // Custom lower v2i64 and v2f64 selects.
920 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
921 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
922 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
923 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
925 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
926 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
929 if (Subtarget->hasSSE41()) {
930 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
931 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
932 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
933 setOperationAction(ISD::FRINT, MVT::f32, Legal);
934 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
935 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
938 setOperationAction(ISD::FRINT, MVT::f64, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
941 // FIXME: Do we need to handle scalar-to-vector here?
942 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
944 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
945 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
946 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
947 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
948 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
950 // i8 and i16 vectors are custom , because the source register and source
951 // source memory operand types are not the same width. f32 vectors are
952 // custom since the immediate controlling the insert encodes additional
954 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
955 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
956 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
957 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
959 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
964 // FIXME: these should be Legal but thats only for the case where
965 // the index is constant. For now custom expand to deal with that.
966 if (Subtarget->is64Bit()) {
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
972 if (Subtarget->hasSSE2()) {
973 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
974 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
976 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
977 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
979 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
980 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
982 if (Subtarget->hasAVX2()) {
983 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
984 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
986 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
987 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
989 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
991 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
992 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
994 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
995 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
997 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1001 if (Subtarget->hasSSE42())
1002 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1004 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1005 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1006 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1007 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1008 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1009 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1010 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1012 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1013 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1014 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1016 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1017 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1018 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1019 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1020 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1021 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1023 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1024 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1025 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1026 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1027 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1028 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1030 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1031 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1032 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1034 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1035 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1036 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1037 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1038 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1041 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1042 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1044 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1045 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1048 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1050 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1051 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1053 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1055 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1056 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1057 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1059 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1060 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1061 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1062 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1064 if (Subtarget->hasAVX2()) {
1065 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1066 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1067 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1068 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1070 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1071 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1072 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1073 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1075 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1076 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1077 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1078 // Don't lower v32i8 because there is no 128-bit byte mul
1080 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1082 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1083 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1086 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1088 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1090 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1091 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1092 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1093 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1095 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1096 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1097 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1098 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1100 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1101 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1102 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1103 // Don't lower v32i8 because there is no 128-bit byte mul
1105 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1114 // Custom lower several nodes for 256-bit types.
1115 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1116 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1117 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1120 // Extract subvector is special because the value type
1121 // (result) is 128-bit but the source is 256-bit wide.
1122 if (VT.is128BitVector())
1123 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1125 // Do not attempt to custom lower other non-256-bit vectors
1126 if (!VT.is256BitVector())
1129 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1130 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1131 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1133 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1134 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1137 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1138 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1139 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1142 // Do not attempt to promote non-256-bit vectors
1143 if (!VT.is256BitVector())
1146 setOperationAction(ISD::AND, SVT, Promote);
1147 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1148 setOperationAction(ISD::OR, SVT, Promote);
1149 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1150 setOperationAction(ISD::XOR, SVT, Promote);
1151 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1152 setOperationAction(ISD::LOAD, SVT, Promote);
1153 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1154 setOperationAction(ISD::SELECT, SVT, Promote);
1155 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1159 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1160 // of this type with custom code.
1161 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1162 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1163 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1167 // We want to custom lower some of our intrinsics.
1168 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1171 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1172 // handle type legalization for these operations here.
1174 // FIXME: We really should do custom legalization for addition and
1175 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1176 // than generic legalization for 64-bit multiplication-with-overflow, though.
1177 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1178 // Add/Sub/Mul with overflow operations are custom lowered.
1180 setOperationAction(ISD::SADDO, VT, Custom);
1181 setOperationAction(ISD::UADDO, VT, Custom);
1182 setOperationAction(ISD::SSUBO, VT, Custom);
1183 setOperationAction(ISD::USUBO, VT, Custom);
1184 setOperationAction(ISD::SMULO, VT, Custom);
1185 setOperationAction(ISD::UMULO, VT, Custom);
1188 // There are no 8-bit 3-address imul/mul instructions
1189 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1190 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1192 if (!Subtarget->is64Bit()) {
1193 // These libcalls are not available in 32-bit.
1194 setLibcallName(RTLIB::SHL_I128, 0);
1195 setLibcallName(RTLIB::SRL_I128, 0);
1196 setLibcallName(RTLIB::SRA_I128, 0);
1199 // We have target-specific dag combine patterns for the following nodes:
1200 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1201 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1202 setTargetDAGCombine(ISD::VSELECT);
1203 setTargetDAGCombine(ISD::SELECT);
1204 setTargetDAGCombine(ISD::SHL);
1205 setTargetDAGCombine(ISD::SRA);
1206 setTargetDAGCombine(ISD::SRL);
1207 setTargetDAGCombine(ISD::OR);
1208 setTargetDAGCombine(ISD::AND);
1209 setTargetDAGCombine(ISD::ADD);
1210 setTargetDAGCombine(ISD::FADD);
1211 setTargetDAGCombine(ISD::FSUB);
1212 setTargetDAGCombine(ISD::SUB);
1213 setTargetDAGCombine(ISD::LOAD);
1214 setTargetDAGCombine(ISD::STORE);
1215 setTargetDAGCombine(ISD::ZERO_EXTEND);
1216 setTargetDAGCombine(ISD::SIGN_EXTEND);
1217 setTargetDAGCombine(ISD::TRUNCATE);
1218 setTargetDAGCombine(ISD::SINT_TO_FP);
1219 if (Subtarget->is64Bit())
1220 setTargetDAGCombine(ISD::MUL);
1221 if (Subtarget->hasBMI())
1222 setTargetDAGCombine(ISD::XOR);
1224 computeRegisterProperties();
1226 // On Darwin, -Os means optimize for size without hurting performance,
1227 // do not reduce the limit.
1228 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1229 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1230 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1231 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1232 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1233 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1234 setPrefLoopAlignment(4); // 2^4 bytes.
1235 benefitFromCodePlacementOpt = true;
1237 setPrefFunctionAlignment(4); // 2^4 bytes.
1241 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1242 if (!VT.isVector()) return MVT::i8;
1243 return VT.changeVectorElementTypeToInteger();
1247 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1248 /// the desired ByVal argument alignment.
1249 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1252 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1253 if (VTy->getBitWidth() == 128)
1255 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1256 unsigned EltAlign = 0;
1257 getMaxByValAlign(ATy->getElementType(), EltAlign);
1258 if (EltAlign > MaxAlign)
1259 MaxAlign = EltAlign;
1260 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1261 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1262 unsigned EltAlign = 0;
1263 getMaxByValAlign(STy->getElementType(i), EltAlign);
1264 if (EltAlign > MaxAlign)
1265 MaxAlign = EltAlign;
1273 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1274 /// function arguments in the caller parameter area. For X86, aggregates
1275 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1276 /// are at 4-byte boundaries.
1277 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1278 if (Subtarget->is64Bit()) {
1279 // Max of 8 and alignment of type.
1280 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1287 if (Subtarget->hasSSE1())
1288 getMaxByValAlign(Ty, Align);
1292 /// getOptimalMemOpType - Returns the target specific optimal type for load
1293 /// and store operations as a result of memset, memcpy, and memmove
1294 /// lowering. If DstAlign is zero that means it's safe to destination
1295 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1296 /// means there isn't a need to check it against alignment requirement,
1297 /// probably because the source does not need to be loaded. If
1298 /// 'IsZeroVal' is true, that means it's safe to return a
1299 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1300 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1301 /// constant so it does not need to be loaded.
1302 /// It returns EVT::Other if the type should be determined using generic
1303 /// target-independent logic.
1305 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1306 unsigned DstAlign, unsigned SrcAlign,
1309 MachineFunction &MF) const {
1310 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1311 // linux. This is because the stack realignment code can't handle certain
1312 // cases like PR2962. This should be removed when PR2962 is fixed.
1313 const Function *F = MF.getFunction();
1315 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1317 (Subtarget->isUnalignedMemAccessFast() ||
1318 ((DstAlign == 0 || DstAlign >= 16) &&
1319 (SrcAlign == 0 || SrcAlign >= 16))) &&
1320 Subtarget->getStackAlignment() >= 16) {
1321 if (Subtarget->getStackAlignment() >= 32) {
1322 if (Subtarget->hasAVX2())
1324 if (Subtarget->hasAVX())
1327 if (Subtarget->hasSSE2())
1329 if (Subtarget->hasSSE1())
1331 } else if (!MemcpyStrSrc && Size >= 8 &&
1332 !Subtarget->is64Bit() &&
1333 Subtarget->getStackAlignment() >= 8 &&
1334 Subtarget->hasSSE2()) {
1335 // Do not use f64 to lower memcpy if source is string constant. It's
1336 // better to use i32 to avoid the loads.
1340 if (Subtarget->is64Bit() && Size >= 8)
1345 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1346 /// current function. The returned value is a member of the
1347 /// MachineJumpTableInfo::JTEntryKind enum.
1348 unsigned X86TargetLowering::getJumpTableEncoding() const {
1349 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1351 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1352 Subtarget->isPICStyleGOT())
1353 return MachineJumpTableInfo::EK_Custom32;
1355 // Otherwise, use the normal jump table encoding heuristics.
1356 return TargetLowering::getJumpTableEncoding();
1360 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1361 const MachineBasicBlock *MBB,
1362 unsigned uid,MCContext &Ctx) const{
1363 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1364 Subtarget->isPICStyleGOT());
1365 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1367 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1368 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1371 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1373 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1374 SelectionDAG &DAG) const {
1375 if (!Subtarget->is64Bit())
1376 // This doesn't have DebugLoc associated with it, but is not really the
1377 // same as a Register.
1378 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1382 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1383 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1385 const MCExpr *X86TargetLowering::
1386 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1387 MCContext &Ctx) const {
1388 // X86-64 uses RIP relative addressing based on the jump table label.
1389 if (Subtarget->isPICStyleRIPRel())
1390 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1392 // Otherwise, the reference is relative to the PIC base.
1393 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1396 // FIXME: Why this routine is here? Move to RegInfo!
1397 std::pair<const TargetRegisterClass*, uint8_t>
1398 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1399 const TargetRegisterClass *RRC = 0;
1401 switch (VT.getSimpleVT().SimpleTy) {
1403 return TargetLowering::findRepresentativeClass(VT);
1404 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1405 RRC = (Subtarget->is64Bit()
1406 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1409 RRC = X86::VR64RegisterClass;
1411 case MVT::f32: case MVT::f64:
1412 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1413 case MVT::v4f32: case MVT::v2f64:
1414 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1416 RRC = X86::VR128RegisterClass;
1419 return std::make_pair(RRC, Cost);
1422 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1423 unsigned &Offset) const {
1424 if (!Subtarget->isTargetLinux())
1427 if (Subtarget->is64Bit()) {
1428 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1430 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1443 //===----------------------------------------------------------------------===//
1444 // Return Value Calling Convention Implementation
1445 //===----------------------------------------------------------------------===//
1447 #include "X86GenCallingConv.inc"
1450 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1451 MachineFunction &MF, bool isVarArg,
1452 const SmallVectorImpl<ISD::OutputArg> &Outs,
1453 LLVMContext &Context) const {
1454 SmallVector<CCValAssign, 16> RVLocs;
1455 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1457 return CCInfo.CheckReturn(Outs, RetCC_X86);
1461 X86TargetLowering::LowerReturn(SDValue Chain,
1462 CallingConv::ID CallConv, bool isVarArg,
1463 const SmallVectorImpl<ISD::OutputArg> &Outs,
1464 const SmallVectorImpl<SDValue> &OutVals,
1465 DebugLoc dl, SelectionDAG &DAG) const {
1466 MachineFunction &MF = DAG.getMachineFunction();
1467 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1469 SmallVector<CCValAssign, 16> RVLocs;
1470 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1471 RVLocs, *DAG.getContext());
1472 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1474 // Add the regs to the liveout set for the function.
1475 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1476 for (unsigned i = 0; i != RVLocs.size(); ++i)
1477 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1478 MRI.addLiveOut(RVLocs[i].getLocReg());
1482 SmallVector<SDValue, 6> RetOps;
1483 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1484 // Operand #1 = Bytes To Pop
1485 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1488 // Copy the result values into the output registers.
1489 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1490 CCValAssign &VA = RVLocs[i];
1491 assert(VA.isRegLoc() && "Can only return in registers!");
1492 SDValue ValToCopy = OutVals[i];
1493 EVT ValVT = ValToCopy.getValueType();
1495 // If this is x86-64, and we disabled SSE, we can't return FP values,
1496 // or SSE or MMX vectors.
1497 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1498 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1499 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1500 report_fatal_error("SSE register return with SSE disabled");
1502 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1503 // llvm-gcc has never done it right and no one has noticed, so this
1504 // should be OK for now.
1505 if (ValVT == MVT::f64 &&
1506 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1507 report_fatal_error("SSE2 register return with SSE2 disabled");
1509 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1510 // the RET instruction and handled by the FP Stackifier.
1511 if (VA.getLocReg() == X86::ST0 ||
1512 VA.getLocReg() == X86::ST1) {
1513 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1514 // change the value to the FP stack register class.
1515 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1516 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1517 RetOps.push_back(ValToCopy);
1518 // Don't emit a copytoreg.
1522 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1523 // which is returned in RAX / RDX.
1524 if (Subtarget->is64Bit()) {
1525 if (ValVT == MVT::x86mmx) {
1526 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1527 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1528 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1530 // If we don't have SSE2 available, convert to v4f32 so the generated
1531 // register is legal.
1532 if (!Subtarget->hasSSE2())
1533 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1538 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1539 Flag = Chain.getValue(1);
1542 // The x86-64 ABI for returning structs by value requires that we copy
1543 // the sret argument into %rax for the return. We saved the argument into
1544 // a virtual register in the entry block, so now we copy the value out
1546 if (Subtarget->is64Bit() &&
1547 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1548 MachineFunction &MF = DAG.getMachineFunction();
1549 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1550 unsigned Reg = FuncInfo->getSRetReturnReg();
1552 "SRetReturnReg should have been set in LowerFormalArguments().");
1553 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1555 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1556 Flag = Chain.getValue(1);
1558 // RAX now acts like a return value.
1559 MRI.addLiveOut(X86::RAX);
1562 RetOps[0] = Chain; // Update chain.
1564 // Add the flag if we have it.
1566 RetOps.push_back(Flag);
1568 return DAG.getNode(X86ISD::RET_FLAG, dl,
1569 MVT::Other, &RetOps[0], RetOps.size());
1572 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1573 if (N->getNumValues() != 1)
1575 if (!N->hasNUsesOfValue(1, 0))
1578 SDNode *Copy = *N->use_begin();
1579 if (Copy->getOpcode() != ISD::CopyToReg &&
1580 Copy->getOpcode() != ISD::FP_EXTEND)
1583 bool HasRet = false;
1584 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1586 if (UI->getOpcode() != X86ISD::RET_FLAG)
1595 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1596 ISD::NodeType ExtendKind) const {
1598 // TODO: Is this also valid on 32-bit?
1599 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1600 ReturnMVT = MVT::i8;
1602 ReturnMVT = MVT::i32;
1604 EVT MinVT = getRegisterType(Context, ReturnMVT);
1605 return VT.bitsLT(MinVT) ? MinVT : VT;
1608 /// LowerCallResult - Lower the result values of a call into the
1609 /// appropriate copies out of appropriate physical registers.
1612 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1613 CallingConv::ID CallConv, bool isVarArg,
1614 const SmallVectorImpl<ISD::InputArg> &Ins,
1615 DebugLoc dl, SelectionDAG &DAG,
1616 SmallVectorImpl<SDValue> &InVals) const {
1618 // Assign locations to each value returned by this call.
1619 SmallVector<CCValAssign, 16> RVLocs;
1620 bool Is64Bit = Subtarget->is64Bit();
1621 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1622 getTargetMachine(), RVLocs, *DAG.getContext());
1623 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1625 // Copy all of the result registers out of their specified physreg.
1626 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1627 CCValAssign &VA = RVLocs[i];
1628 EVT CopyVT = VA.getValVT();
1630 // If this is x86-64, and we disabled SSE, we can't return FP values
1631 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1632 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1633 report_fatal_error("SSE register return with SSE disabled");
1638 // If this is a call to a function that returns an fp value on the floating
1639 // point stack, we must guarantee the the value is popped from the stack, so
1640 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1641 // if the return value is not used. We use the FpPOP_RETVAL instruction
1643 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1644 // If we prefer to use the value in xmm registers, copy it out as f80 and
1645 // use a truncate to move it from fp stack reg to xmm reg.
1646 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1647 SDValue Ops[] = { Chain, InFlag };
1648 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1649 MVT::Other, MVT::Glue, Ops, 2), 1);
1650 Val = Chain.getValue(0);
1652 // Round the f80 to the right size, which also moves it to the appropriate
1654 if (CopyVT != VA.getValVT())
1655 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1656 // This truncation won't change the value.
1657 DAG.getIntPtrConstant(1));
1659 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1660 CopyVT, InFlag).getValue(1);
1661 Val = Chain.getValue(0);
1663 InFlag = Chain.getValue(2);
1664 InVals.push_back(Val);
1671 //===----------------------------------------------------------------------===//
1672 // C & StdCall & Fast Calling Convention implementation
1673 //===----------------------------------------------------------------------===//
1674 // StdCall calling convention seems to be standard for many Windows' API
1675 // routines and around. It differs from C calling convention just a little:
1676 // callee should clean up the stack, not caller. Symbols should be also
1677 // decorated in some fancy way :) It doesn't support any vector arguments.
1678 // For info on fast calling convention see Fast Calling Convention (tail call)
1679 // implementation LowerX86_32FastCCCallTo.
1681 /// CallIsStructReturn - Determines whether a call uses struct return
1683 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1687 return Outs[0].Flags.isSRet();
1690 /// ArgsAreStructReturn - Determines whether a function uses struct
1691 /// return semantics.
1693 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1697 return Ins[0].Flags.isSRet();
1700 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1701 /// by "Src" to address "Dst" with size and alignment information specified by
1702 /// the specific parameter attribute. The copy will be passed as a byval
1703 /// function parameter.
1705 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1706 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1708 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1710 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1711 /*isVolatile*/false, /*AlwaysInline=*/true,
1712 MachinePointerInfo(), MachinePointerInfo());
1715 /// IsTailCallConvention - Return true if the calling convention is one that
1716 /// supports tail call optimization.
1717 static bool IsTailCallConvention(CallingConv::ID CC) {
1718 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1721 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1722 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1726 CallingConv::ID CalleeCC = CS.getCallingConv();
1727 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1733 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1734 /// a tailcall target by changing its ABI.
1735 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1736 bool GuaranteedTailCallOpt) {
1737 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1741 X86TargetLowering::LowerMemArgument(SDValue Chain,
1742 CallingConv::ID CallConv,
1743 const SmallVectorImpl<ISD::InputArg> &Ins,
1744 DebugLoc dl, SelectionDAG &DAG,
1745 const CCValAssign &VA,
1746 MachineFrameInfo *MFI,
1748 // Create the nodes corresponding to a load from this parameter slot.
1749 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1750 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1751 getTargetMachine().Options.GuaranteedTailCallOpt);
1752 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1755 // If value is passed by pointer we have address passed instead of the value
1757 if (VA.getLocInfo() == CCValAssign::Indirect)
1758 ValVT = VA.getLocVT();
1760 ValVT = VA.getValVT();
1762 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1763 // changed with more analysis.
1764 // In case of tail call optimization mark all arguments mutable. Since they
1765 // could be overwritten by lowering of arguments in case of a tail call.
1766 if (Flags.isByVal()) {
1767 unsigned Bytes = Flags.getByValSize();
1768 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1769 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1770 return DAG.getFrameIndex(FI, getPointerTy());
1772 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1773 VA.getLocMemOffset(), isImmutable);
1774 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1775 return DAG.getLoad(ValVT, dl, Chain, FIN,
1776 MachinePointerInfo::getFixedStack(FI),
1777 false, false, false, 0);
1782 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1783 CallingConv::ID CallConv,
1785 const SmallVectorImpl<ISD::InputArg> &Ins,
1788 SmallVectorImpl<SDValue> &InVals)
1790 MachineFunction &MF = DAG.getMachineFunction();
1791 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1793 const Function* Fn = MF.getFunction();
1794 if (Fn->hasExternalLinkage() &&
1795 Subtarget->isTargetCygMing() &&
1796 Fn->getName() == "main")
1797 FuncInfo->setForceFramePointer(true);
1799 MachineFrameInfo *MFI = MF.getFrameInfo();
1800 bool Is64Bit = Subtarget->is64Bit();
1801 bool IsWindows = Subtarget->isTargetWindows();
1802 bool IsWin64 = Subtarget->isTargetWin64();
1804 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1805 "Var args not supported with calling convention fastcc or ghc");
1807 // Assign locations to all of the incoming arguments.
1808 SmallVector<CCValAssign, 16> ArgLocs;
1809 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1810 ArgLocs, *DAG.getContext());
1812 // Allocate shadow area for Win64
1814 CCInfo.AllocateStack(32, 8);
1817 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1819 unsigned LastVal = ~0U;
1821 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1822 CCValAssign &VA = ArgLocs[i];
1823 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1825 assert(VA.getValNo() != LastVal &&
1826 "Don't support value assigned to multiple locs yet");
1828 LastVal = VA.getValNo();
1830 if (VA.isRegLoc()) {
1831 EVT RegVT = VA.getLocVT();
1832 TargetRegisterClass *RC = NULL;
1833 if (RegVT == MVT::i32)
1834 RC = X86::GR32RegisterClass;
1835 else if (Is64Bit && RegVT == MVT::i64)
1836 RC = X86::GR64RegisterClass;
1837 else if (RegVT == MVT::f32)
1838 RC = X86::FR32RegisterClass;
1839 else if (RegVT == MVT::f64)
1840 RC = X86::FR64RegisterClass;
1841 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1842 RC = X86::VR256RegisterClass;
1843 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1844 RC = X86::VR128RegisterClass;
1845 else if (RegVT == MVT::x86mmx)
1846 RC = X86::VR64RegisterClass;
1848 llvm_unreachable("Unknown argument type!");
1850 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1851 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1853 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1854 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1856 if (VA.getLocInfo() == CCValAssign::SExt)
1857 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1858 DAG.getValueType(VA.getValVT()));
1859 else if (VA.getLocInfo() == CCValAssign::ZExt)
1860 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1861 DAG.getValueType(VA.getValVT()));
1862 else if (VA.getLocInfo() == CCValAssign::BCvt)
1863 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1865 if (VA.isExtInLoc()) {
1866 // Handle MMX values passed in XMM regs.
1867 if (RegVT.isVector()) {
1868 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1871 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1874 assert(VA.isMemLoc());
1875 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1878 // If value is passed via pointer - do a load.
1879 if (VA.getLocInfo() == CCValAssign::Indirect)
1880 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1881 MachinePointerInfo(), false, false, false, 0);
1883 InVals.push_back(ArgValue);
1886 // The x86-64 ABI for returning structs by value requires that we copy
1887 // the sret argument into %rax for the return. Save the argument into
1888 // a virtual register so that we can access it from the return points.
1889 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1890 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1891 unsigned Reg = FuncInfo->getSRetReturnReg();
1893 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1894 FuncInfo->setSRetReturnReg(Reg);
1896 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1897 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1900 unsigned StackSize = CCInfo.getNextStackOffset();
1901 // Align stack specially for tail calls.
1902 if (FuncIsMadeTailCallSafe(CallConv,
1903 MF.getTarget().Options.GuaranteedTailCallOpt))
1904 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1906 // If the function takes variable number of arguments, make a frame index for
1907 // the start of the first vararg value... for expansion of llvm.va_start.
1909 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1910 CallConv != CallingConv::X86_ThisCall)) {
1911 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1914 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1916 // FIXME: We should really autogenerate these arrays
1917 static const unsigned GPR64ArgRegsWin64[] = {
1918 X86::RCX, X86::RDX, X86::R8, X86::R9
1920 static const unsigned GPR64ArgRegs64Bit[] = {
1921 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1923 static const unsigned XMMArgRegs64Bit[] = {
1924 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1925 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1927 const unsigned *GPR64ArgRegs;
1928 unsigned NumXMMRegs = 0;
1931 // The XMM registers which might contain var arg parameters are shadowed
1932 // in their paired GPR. So we only need to save the GPR to their home
1934 TotalNumIntRegs = 4;
1935 GPR64ArgRegs = GPR64ArgRegsWin64;
1937 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1938 GPR64ArgRegs = GPR64ArgRegs64Bit;
1940 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1943 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1946 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1947 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1948 "SSE register cannot be used when SSE is disabled!");
1949 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1950 NoImplicitFloatOps) &&
1951 "SSE register cannot be used when SSE is disabled!");
1952 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1953 !Subtarget->hasSSE1())
1954 // Kernel mode asks for SSE to be disabled, so don't push them
1956 TotalNumXMMRegs = 0;
1959 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1960 // Get to the caller-allocated home save location. Add 8 to account
1961 // for the return address.
1962 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1963 FuncInfo->setRegSaveFrameIndex(
1964 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1965 // Fixup to set vararg frame on shadow area (4 x i64).
1967 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1969 // For X86-64, if there are vararg parameters that are passed via
1970 // registers, then we must store them to their spots on the stack so
1971 // they may be loaded by deferencing the result of va_next.
1972 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1973 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1974 FuncInfo->setRegSaveFrameIndex(
1975 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1979 // Store the integer parameter registers.
1980 SmallVector<SDValue, 8> MemOps;
1981 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1983 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1984 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1985 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1986 DAG.getIntPtrConstant(Offset));
1987 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1988 X86::GR64RegisterClass);
1989 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1991 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1992 MachinePointerInfo::getFixedStack(
1993 FuncInfo->getRegSaveFrameIndex(), Offset),
1995 MemOps.push_back(Store);
1999 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2000 // Now store the XMM (fp + vector) parameter registers.
2001 SmallVector<SDValue, 11> SaveXMMOps;
2002 SaveXMMOps.push_back(Chain);
2004 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2005 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2006 SaveXMMOps.push_back(ALVal);
2008 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2009 FuncInfo->getRegSaveFrameIndex()));
2010 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2011 FuncInfo->getVarArgsFPOffset()));
2013 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2014 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2015 X86::VR128RegisterClass);
2016 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2017 SaveXMMOps.push_back(Val);
2019 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2021 &SaveXMMOps[0], SaveXMMOps.size()));
2024 if (!MemOps.empty())
2025 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2026 &MemOps[0], MemOps.size());
2030 // Some CCs need callee pop.
2031 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2032 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2033 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2035 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2036 // If this is an sret function, the return should pop the hidden pointer.
2037 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2038 ArgsAreStructReturn(Ins))
2039 FuncInfo->setBytesToPopOnReturn(4);
2043 // RegSaveFrameIndex is X86-64 only.
2044 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2045 if (CallConv == CallingConv::X86_FastCall ||
2046 CallConv == CallingConv::X86_ThisCall)
2047 // fastcc functions can't have varargs.
2048 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2051 FuncInfo->setArgumentStackSize(StackSize);
2057 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2058 SDValue StackPtr, SDValue Arg,
2059 DebugLoc dl, SelectionDAG &DAG,
2060 const CCValAssign &VA,
2061 ISD::ArgFlagsTy Flags) const {
2062 unsigned LocMemOffset = VA.getLocMemOffset();
2063 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2064 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2065 if (Flags.isByVal())
2066 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2068 return DAG.getStore(Chain, dl, Arg, PtrOff,
2069 MachinePointerInfo::getStack(LocMemOffset),
2073 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2074 /// optimization is performed and it is required.
2076 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2077 SDValue &OutRetAddr, SDValue Chain,
2078 bool IsTailCall, bool Is64Bit,
2079 int FPDiff, DebugLoc dl) const {
2080 // Adjust the Return address stack slot.
2081 EVT VT = getPointerTy();
2082 OutRetAddr = getReturnAddressFrameIndex(DAG);
2084 // Load the "old" Return address.
2085 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2086 false, false, false, 0);
2087 return SDValue(OutRetAddr.getNode(), 1);
2090 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2091 /// optimization is performed and it is required (FPDiff!=0).
2093 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2094 SDValue Chain, SDValue RetAddrFrIdx,
2095 bool Is64Bit, int FPDiff, DebugLoc dl) {
2096 // Store the return address to the appropriate stack slot.
2097 if (!FPDiff) return Chain;
2098 // Calculate the new stack slot for the return address.
2099 int SlotSize = Is64Bit ? 8 : 4;
2100 int NewReturnAddrFI =
2101 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2102 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2103 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2104 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2105 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2111 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2112 CallingConv::ID CallConv, bool isVarArg,
2114 const SmallVectorImpl<ISD::OutputArg> &Outs,
2115 const SmallVectorImpl<SDValue> &OutVals,
2116 const SmallVectorImpl<ISD::InputArg> &Ins,
2117 DebugLoc dl, SelectionDAG &DAG,
2118 SmallVectorImpl<SDValue> &InVals) const {
2119 MachineFunction &MF = DAG.getMachineFunction();
2120 bool Is64Bit = Subtarget->is64Bit();
2121 bool IsWin64 = Subtarget->isTargetWin64();
2122 bool IsWindows = Subtarget->isTargetWindows();
2123 bool IsStructRet = CallIsStructReturn(Outs);
2124 bool IsSibcall = false;
2126 if (MF.getTarget().Options.DisableTailCalls)
2130 // Check if it's really possible to do a tail call.
2131 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2132 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2133 Outs, OutVals, Ins, DAG);
2135 // Sibcalls are automatically detected tailcalls which do not require
2137 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2144 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2145 "Var args not supported with calling convention fastcc or ghc");
2147 // Analyze operands of the call, assigning locations to each operand.
2148 SmallVector<CCValAssign, 16> ArgLocs;
2149 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2150 ArgLocs, *DAG.getContext());
2152 // Allocate shadow area for Win64
2154 CCInfo.AllocateStack(32, 8);
2157 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2159 // Get a count of how many bytes are to be pushed on the stack.
2160 unsigned NumBytes = CCInfo.getNextStackOffset();
2162 // This is a sibcall. The memory operands are available in caller's
2163 // own caller's stack.
2165 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2166 IsTailCallConvention(CallConv))
2167 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2170 if (isTailCall && !IsSibcall) {
2171 // Lower arguments at fp - stackoffset + fpdiff.
2172 unsigned NumBytesCallerPushed =
2173 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2174 FPDiff = NumBytesCallerPushed - NumBytes;
2176 // Set the delta of movement of the returnaddr stackslot.
2177 // But only set if delta is greater than previous delta.
2178 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2179 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2183 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2185 SDValue RetAddrFrIdx;
2186 // Load return address for tail calls.
2187 if (isTailCall && FPDiff)
2188 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2189 Is64Bit, FPDiff, dl);
2191 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2192 SmallVector<SDValue, 8> MemOpChains;
2195 // Walk the register/memloc assignments, inserting copies/loads. In the case
2196 // of tail call optimization arguments are handle later.
2197 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2198 CCValAssign &VA = ArgLocs[i];
2199 EVT RegVT = VA.getLocVT();
2200 SDValue Arg = OutVals[i];
2201 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2202 bool isByVal = Flags.isByVal();
2204 // Promote the value if needed.
2205 switch (VA.getLocInfo()) {
2206 default: llvm_unreachable("Unknown loc info!");
2207 case CCValAssign::Full: break;
2208 case CCValAssign::SExt:
2209 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2211 case CCValAssign::ZExt:
2212 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2214 case CCValAssign::AExt:
2215 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2216 // Special case: passing MMX values in XMM registers.
2217 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2218 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2219 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2221 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2223 case CCValAssign::BCvt:
2224 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2226 case CCValAssign::Indirect: {
2227 // Store the argument.
2228 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2229 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2230 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2231 MachinePointerInfo::getFixedStack(FI),
2238 if (VA.isRegLoc()) {
2239 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2240 if (isVarArg && IsWin64) {
2241 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2242 // shadow reg if callee is a varargs function.
2243 unsigned ShadowReg = 0;
2244 switch (VA.getLocReg()) {
2245 case X86::XMM0: ShadowReg = X86::RCX; break;
2246 case X86::XMM1: ShadowReg = X86::RDX; break;
2247 case X86::XMM2: ShadowReg = X86::R8; break;
2248 case X86::XMM3: ShadowReg = X86::R9; break;
2251 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2253 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2254 assert(VA.isMemLoc());
2255 if (StackPtr.getNode() == 0)
2256 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2257 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2258 dl, DAG, VA, Flags));
2262 if (!MemOpChains.empty())
2263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2264 &MemOpChains[0], MemOpChains.size());
2266 // Build a sequence of copy-to-reg nodes chained together with token chain
2267 // and flag operands which copy the outgoing args into registers.
2269 // Tail call byval lowering might overwrite argument registers so in case of
2270 // tail call optimization the copies to registers are lowered later.
2272 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2273 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2274 RegsToPass[i].second, InFlag);
2275 InFlag = Chain.getValue(1);
2278 if (Subtarget->isPICStyleGOT()) {
2279 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2282 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2283 DAG.getNode(X86ISD::GlobalBaseReg,
2284 DebugLoc(), getPointerTy()),
2286 InFlag = Chain.getValue(1);
2288 // If we are tail calling and generating PIC/GOT style code load the
2289 // address of the callee into ECX. The value in ecx is used as target of
2290 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2291 // for tail calls on PIC/GOT architectures. Normally we would just put the
2292 // address of GOT into ebx and then call target@PLT. But for tail calls
2293 // ebx would be restored (since ebx is callee saved) before jumping to the
2296 // Note: The actual moving to ECX is done further down.
2297 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2298 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2299 !G->getGlobal()->hasProtectedVisibility())
2300 Callee = LowerGlobalAddress(Callee, DAG);
2301 else if (isa<ExternalSymbolSDNode>(Callee))
2302 Callee = LowerExternalSymbol(Callee, DAG);
2306 if (Is64Bit && isVarArg && !IsWin64) {
2307 // From AMD64 ABI document:
2308 // For calls that may call functions that use varargs or stdargs
2309 // (prototype-less calls or calls to functions containing ellipsis (...) in
2310 // the declaration) %al is used as hidden argument to specify the number
2311 // of SSE registers used. The contents of %al do not need to match exactly
2312 // the number of registers, but must be an ubound on the number of SSE
2313 // registers used and is in the range 0 - 8 inclusive.
2315 // Count the number of XMM registers allocated.
2316 static const unsigned XMMArgRegs[] = {
2317 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2318 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2320 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2321 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2322 && "SSE registers cannot be used when SSE is disabled");
2324 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2325 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2326 InFlag = Chain.getValue(1);
2330 // For tail calls lower the arguments to the 'real' stack slot.
2332 // Force all the incoming stack arguments to be loaded from the stack
2333 // before any new outgoing arguments are stored to the stack, because the
2334 // outgoing stack slots may alias the incoming argument stack slots, and
2335 // the alias isn't otherwise explicit. This is slightly more conservative
2336 // than necessary, because it means that each store effectively depends
2337 // on every argument instead of just those arguments it would clobber.
2338 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2340 SmallVector<SDValue, 8> MemOpChains2;
2343 // Do not flag preceding copytoreg stuff together with the following stuff.
2345 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2346 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2347 CCValAssign &VA = ArgLocs[i];
2350 assert(VA.isMemLoc());
2351 SDValue Arg = OutVals[i];
2352 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2353 // Create frame index.
2354 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2355 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2356 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2357 FIN = DAG.getFrameIndex(FI, getPointerTy());
2359 if (Flags.isByVal()) {
2360 // Copy relative to framepointer.
2361 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2362 if (StackPtr.getNode() == 0)
2363 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2365 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2367 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2371 // Store relative to framepointer.
2372 MemOpChains2.push_back(
2373 DAG.getStore(ArgChain, dl, Arg, FIN,
2374 MachinePointerInfo::getFixedStack(FI),
2380 if (!MemOpChains2.empty())
2381 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2382 &MemOpChains2[0], MemOpChains2.size());
2384 // Copy arguments to their registers.
2385 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2386 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2387 RegsToPass[i].second, InFlag);
2388 InFlag = Chain.getValue(1);
2392 // Store the return address to the appropriate stack slot.
2393 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2397 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2398 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2399 // In the 64-bit large code model, we have to make all calls
2400 // through a register, since the call instruction's 32-bit
2401 // pc-relative offset may not be large enough to hold the whole
2403 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2404 // If the callee is a GlobalAddress node (quite common, every direct call
2405 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2408 // We should use extra load for direct calls to dllimported functions in
2410 const GlobalValue *GV = G->getGlobal();
2411 if (!GV->hasDLLImportLinkage()) {
2412 unsigned char OpFlags = 0;
2413 bool ExtraLoad = false;
2414 unsigned WrapperKind = ISD::DELETED_NODE;
2416 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2417 // external symbols most go through the PLT in PIC mode. If the symbol
2418 // has hidden or protected visibility, or if it is static or local, then
2419 // we don't need to use the PLT - we can directly call it.
2420 if (Subtarget->isTargetELF() &&
2421 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2422 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2423 OpFlags = X86II::MO_PLT;
2424 } else if (Subtarget->isPICStyleStubAny() &&
2425 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2426 (!Subtarget->getTargetTriple().isMacOSX() ||
2427 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2428 // PC-relative references to external symbols should go through $stub,
2429 // unless we're building with the leopard linker or later, which
2430 // automatically synthesizes these stubs.
2431 OpFlags = X86II::MO_DARWIN_STUB;
2432 } else if (Subtarget->isPICStyleRIPRel() &&
2433 isa<Function>(GV) &&
2434 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2435 // If the function is marked as non-lazy, generate an indirect call
2436 // which loads from the GOT directly. This avoids runtime overhead
2437 // at the cost of eager binding (and one extra byte of encoding).
2438 OpFlags = X86II::MO_GOTPCREL;
2439 WrapperKind = X86ISD::WrapperRIP;
2443 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2444 G->getOffset(), OpFlags);
2446 // Add a wrapper if needed.
2447 if (WrapperKind != ISD::DELETED_NODE)
2448 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2449 // Add extra indirection if needed.
2451 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2452 MachinePointerInfo::getGOT(),
2453 false, false, false, 0);
2455 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2456 unsigned char OpFlags = 0;
2458 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2459 // external symbols should go through the PLT.
2460 if (Subtarget->isTargetELF() &&
2461 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2462 OpFlags = X86II::MO_PLT;
2463 } else if (Subtarget->isPICStyleStubAny() &&
2464 (!Subtarget->getTargetTriple().isMacOSX() ||
2465 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2466 // PC-relative references to external symbols should go through $stub,
2467 // unless we're building with the leopard linker or later, which
2468 // automatically synthesizes these stubs.
2469 OpFlags = X86II::MO_DARWIN_STUB;
2472 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2476 // Returns a chain & a flag for retval copy to use.
2477 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2478 SmallVector<SDValue, 8> Ops;
2480 if (!IsSibcall && isTailCall) {
2481 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2482 DAG.getIntPtrConstant(0, true), InFlag);
2483 InFlag = Chain.getValue(1);
2486 Ops.push_back(Chain);
2487 Ops.push_back(Callee);
2490 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2492 // Add argument registers to the end of the list so that they are known live
2494 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2495 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2496 RegsToPass[i].second.getValueType()));
2498 // Add an implicit use GOT pointer in EBX.
2499 if (!isTailCall && Subtarget->isPICStyleGOT())
2500 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2502 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2503 if (Is64Bit && isVarArg && !IsWin64)
2504 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2506 // Add a register mask operand representing the call-preserved registers.
2507 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2508 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2509 assert(Mask && "Missing call preserved mask for calling convention");
2510 Ops.push_back(DAG.getRegisterMask(Mask));
2512 if (InFlag.getNode())
2513 Ops.push_back(InFlag);
2517 //// If this is the first return lowered for this function, add the regs
2518 //// to the liveout set for the function.
2519 // This isn't right, although it's probably harmless on x86; liveouts
2520 // should be computed from returns not tail calls. Consider a void
2521 // function making a tail call to a function returning int.
2522 return DAG.getNode(X86ISD::TC_RETURN, dl,
2523 NodeTys, &Ops[0], Ops.size());
2526 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2527 InFlag = Chain.getValue(1);
2529 // Create the CALLSEQ_END node.
2530 unsigned NumBytesForCalleeToPush;
2531 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2532 getTargetMachine().Options.GuaranteedTailCallOpt))
2533 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2534 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2536 // If this is a call to a struct-return function, the callee
2537 // pops the hidden struct pointer, so we have to push it back.
2538 // This is common for Darwin/X86, Linux & Mingw32 targets.
2539 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2540 NumBytesForCalleeToPush = 4;
2542 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2544 // Returns a flag for retval copy to use.
2546 Chain = DAG.getCALLSEQ_END(Chain,
2547 DAG.getIntPtrConstant(NumBytes, true),
2548 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2551 InFlag = Chain.getValue(1);
2554 // Handle result values, copying them out of physregs into vregs that we
2556 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2557 Ins, dl, DAG, InVals);
2561 //===----------------------------------------------------------------------===//
2562 // Fast Calling Convention (tail call) implementation
2563 //===----------------------------------------------------------------------===//
2565 // Like std call, callee cleans arguments, convention except that ECX is
2566 // reserved for storing the tail called function address. Only 2 registers are
2567 // free for argument passing (inreg). Tail call optimization is performed
2569 // * tailcallopt is enabled
2570 // * caller/callee are fastcc
2571 // On X86_64 architecture with GOT-style position independent code only local
2572 // (within module) calls are supported at the moment.
2573 // To keep the stack aligned according to platform abi the function
2574 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2575 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2576 // If a tail called function callee has more arguments than the caller the
2577 // caller needs to make sure that there is room to move the RETADDR to. This is
2578 // achieved by reserving an area the size of the argument delta right after the
2579 // original REtADDR, but before the saved framepointer or the spilled registers
2580 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2592 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2593 /// for a 16 byte align requirement.
2595 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2596 SelectionDAG& DAG) const {
2597 MachineFunction &MF = DAG.getMachineFunction();
2598 const TargetMachine &TM = MF.getTarget();
2599 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2600 unsigned StackAlignment = TFI.getStackAlignment();
2601 uint64_t AlignMask = StackAlignment - 1;
2602 int64_t Offset = StackSize;
2603 uint64_t SlotSize = TD->getPointerSize();
2604 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2605 // Number smaller than 12 so just add the difference.
2606 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2608 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2609 Offset = ((~AlignMask) & Offset) + StackAlignment +
2610 (StackAlignment-SlotSize);
2615 /// MatchingStackOffset - Return true if the given stack call argument is
2616 /// already available in the same position (relatively) of the caller's
2617 /// incoming argument stack.
2619 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2620 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2621 const X86InstrInfo *TII) {
2622 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2624 if (Arg.getOpcode() == ISD::CopyFromReg) {
2625 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2626 if (!TargetRegisterInfo::isVirtualRegister(VR))
2628 MachineInstr *Def = MRI->getVRegDef(VR);
2631 if (!Flags.isByVal()) {
2632 if (!TII->isLoadFromStackSlot(Def, FI))
2635 unsigned Opcode = Def->getOpcode();
2636 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2637 Def->getOperand(1).isFI()) {
2638 FI = Def->getOperand(1).getIndex();
2639 Bytes = Flags.getByValSize();
2643 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2644 if (Flags.isByVal())
2645 // ByVal argument is passed in as a pointer but it's now being
2646 // dereferenced. e.g.
2647 // define @foo(%struct.X* %A) {
2648 // tail call @bar(%struct.X* byval %A)
2651 SDValue Ptr = Ld->getBasePtr();
2652 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2655 FI = FINode->getIndex();
2656 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2657 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2658 FI = FINode->getIndex();
2659 Bytes = Flags.getByValSize();
2663 assert(FI != INT_MAX);
2664 if (!MFI->isFixedObjectIndex(FI))
2666 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2669 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2670 /// for tail call optimization. Targets which want to do tail call
2671 /// optimization should implement this function.
2673 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2674 CallingConv::ID CalleeCC,
2676 bool isCalleeStructRet,
2677 bool isCallerStructRet,
2678 const SmallVectorImpl<ISD::OutputArg> &Outs,
2679 const SmallVectorImpl<SDValue> &OutVals,
2680 const SmallVectorImpl<ISD::InputArg> &Ins,
2681 SelectionDAG& DAG) const {
2682 if (!IsTailCallConvention(CalleeCC) &&
2683 CalleeCC != CallingConv::C)
2686 // If -tailcallopt is specified, make fastcc functions tail-callable.
2687 const MachineFunction &MF = DAG.getMachineFunction();
2688 const Function *CallerF = DAG.getMachineFunction().getFunction();
2689 CallingConv::ID CallerCC = CallerF->getCallingConv();
2690 bool CCMatch = CallerCC == CalleeCC;
2692 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2693 if (IsTailCallConvention(CalleeCC) && CCMatch)
2698 // Look for obvious safe cases to perform tail call optimization that do not
2699 // require ABI changes. This is what gcc calls sibcall.
2701 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2702 // emit a special epilogue.
2703 if (RegInfo->needsStackRealignment(MF))
2706 // Also avoid sibcall optimization if either caller or callee uses struct
2707 // return semantics.
2708 if (isCalleeStructRet || isCallerStructRet)
2711 // An stdcall caller is expected to clean up its arguments; the callee
2712 // isn't going to do that.
2713 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2716 // Do not sibcall optimize vararg calls unless all arguments are passed via
2718 if (isVarArg && !Outs.empty()) {
2720 // Optimizing for varargs on Win64 is unlikely to be safe without
2721 // additional testing.
2722 if (Subtarget->isTargetWin64())
2725 SmallVector<CCValAssign, 16> ArgLocs;
2726 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2727 getTargetMachine(), ArgLocs, *DAG.getContext());
2729 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2730 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2731 if (!ArgLocs[i].isRegLoc())
2735 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2736 // stack. Therefore, if it's not used by the call it is not safe to optimize
2737 // this into a sibcall.
2738 bool Unused = false;
2739 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2746 SmallVector<CCValAssign, 16> RVLocs;
2747 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2748 getTargetMachine(), RVLocs, *DAG.getContext());
2749 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2750 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2751 CCValAssign &VA = RVLocs[i];
2752 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2757 // If the calling conventions do not match, then we'd better make sure the
2758 // results are returned in the same way as what the caller expects.
2760 SmallVector<CCValAssign, 16> RVLocs1;
2761 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2762 getTargetMachine(), RVLocs1, *DAG.getContext());
2763 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2765 SmallVector<CCValAssign, 16> RVLocs2;
2766 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2767 getTargetMachine(), RVLocs2, *DAG.getContext());
2768 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2770 if (RVLocs1.size() != RVLocs2.size())
2772 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2773 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2775 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2777 if (RVLocs1[i].isRegLoc()) {
2778 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2781 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2787 // If the callee takes no arguments then go on to check the results of the
2789 if (!Outs.empty()) {
2790 // Check if stack adjustment is needed. For now, do not do this if any
2791 // argument is passed on the stack.
2792 SmallVector<CCValAssign, 16> ArgLocs;
2793 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2794 getTargetMachine(), ArgLocs, *DAG.getContext());
2796 // Allocate shadow area for Win64
2797 if (Subtarget->isTargetWin64()) {
2798 CCInfo.AllocateStack(32, 8);
2801 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2802 if (CCInfo.getNextStackOffset()) {
2803 MachineFunction &MF = DAG.getMachineFunction();
2804 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2807 // Check if the arguments are already laid out in the right way as
2808 // the caller's fixed stack objects.
2809 MachineFrameInfo *MFI = MF.getFrameInfo();
2810 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2811 const X86InstrInfo *TII =
2812 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2813 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2814 CCValAssign &VA = ArgLocs[i];
2815 SDValue Arg = OutVals[i];
2816 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2817 if (VA.getLocInfo() == CCValAssign::Indirect)
2819 if (!VA.isRegLoc()) {
2820 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2827 // If the tailcall address may be in a register, then make sure it's
2828 // possible to register allocate for it. In 32-bit, the call address can
2829 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2830 // callee-saved registers are restored. These happen to be the same
2831 // registers used to pass 'inreg' arguments so watch out for those.
2832 if (!Subtarget->is64Bit() &&
2833 !isa<GlobalAddressSDNode>(Callee) &&
2834 !isa<ExternalSymbolSDNode>(Callee)) {
2835 unsigned NumInRegs = 0;
2836 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2837 CCValAssign &VA = ArgLocs[i];
2840 unsigned Reg = VA.getLocReg();
2843 case X86::EAX: case X86::EDX: case X86::ECX:
2844 if (++NumInRegs == 3)
2856 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2857 return X86::createFastISel(funcInfo);
2861 //===----------------------------------------------------------------------===//
2862 // Other Lowering Hooks
2863 //===----------------------------------------------------------------------===//
2865 static bool MayFoldLoad(SDValue Op) {
2866 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2869 static bool MayFoldIntoStore(SDValue Op) {
2870 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2873 static bool isTargetShuffle(unsigned Opcode) {
2875 default: return false;
2876 case X86ISD::PSHUFD:
2877 case X86ISD::PSHUFHW:
2878 case X86ISD::PSHUFLW:
2880 case X86ISD::PALIGN:
2881 case X86ISD::MOVLHPS:
2882 case X86ISD::MOVLHPD:
2883 case X86ISD::MOVHLPS:
2884 case X86ISD::MOVLPS:
2885 case X86ISD::MOVLPD:
2886 case X86ISD::MOVSHDUP:
2887 case X86ISD::MOVSLDUP:
2888 case X86ISD::MOVDDUP:
2891 case X86ISD::UNPCKL:
2892 case X86ISD::UNPCKH:
2893 case X86ISD::VPERMILP:
2894 case X86ISD::VPERM2X128:
2899 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2900 SDValue V1, SelectionDAG &DAG) {
2902 default: llvm_unreachable("Unknown x86 shuffle node");
2903 case X86ISD::MOVSHDUP:
2904 case X86ISD::MOVSLDUP:
2905 case X86ISD::MOVDDUP:
2906 return DAG.getNode(Opc, dl, VT, V1);
2910 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2911 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2913 default: llvm_unreachable("Unknown x86 shuffle node");
2914 case X86ISD::PSHUFD:
2915 case X86ISD::PSHUFHW:
2916 case X86ISD::PSHUFLW:
2917 case X86ISD::VPERMILP:
2918 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2922 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2923 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2925 default: llvm_unreachable("Unknown x86 shuffle node");
2926 case X86ISD::PALIGN:
2928 case X86ISD::VPERM2X128:
2929 return DAG.getNode(Opc, dl, VT, V1, V2,
2930 DAG.getConstant(TargetMask, MVT::i8));
2934 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2935 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2937 default: llvm_unreachable("Unknown x86 shuffle node");
2938 case X86ISD::MOVLHPS:
2939 case X86ISD::MOVLHPD:
2940 case X86ISD::MOVHLPS:
2941 case X86ISD::MOVLPS:
2942 case X86ISD::MOVLPD:
2945 case X86ISD::UNPCKL:
2946 case X86ISD::UNPCKH:
2947 return DAG.getNode(Opc, dl, VT, V1, V2);
2951 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2952 MachineFunction &MF = DAG.getMachineFunction();
2953 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2954 int ReturnAddrIndex = FuncInfo->getRAIndex();
2956 if (ReturnAddrIndex == 0) {
2957 // Set up a frame object for the return address.
2958 uint64_t SlotSize = TD->getPointerSize();
2959 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2961 FuncInfo->setRAIndex(ReturnAddrIndex);
2964 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2968 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2969 bool hasSymbolicDisplacement) {
2970 // Offset should fit into 32 bit immediate field.
2971 if (!isInt<32>(Offset))
2974 // If we don't have a symbolic displacement - we don't have any extra
2976 if (!hasSymbolicDisplacement)
2979 // FIXME: Some tweaks might be needed for medium code model.
2980 if (M != CodeModel::Small && M != CodeModel::Kernel)
2983 // For small code model we assume that latest object is 16MB before end of 31
2984 // bits boundary. We may also accept pretty large negative constants knowing
2985 // that all objects are in the positive half of address space.
2986 if (M == CodeModel::Small && Offset < 16*1024*1024)
2989 // For kernel code model we know that all object resist in the negative half
2990 // of 32bits address space. We may not accept negative offsets, since they may
2991 // be just off and we may accept pretty large positive ones.
2992 if (M == CodeModel::Kernel && Offset > 0)
2998 /// isCalleePop - Determines whether the callee is required to pop its
2999 /// own arguments. Callee pop is necessary to support tail calls.
3000 bool X86::isCalleePop(CallingConv::ID CallingConv,
3001 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3005 switch (CallingConv) {
3008 case CallingConv::X86_StdCall:
3010 case CallingConv::X86_FastCall:
3012 case CallingConv::X86_ThisCall:
3014 case CallingConv::Fast:
3016 case CallingConv::GHC:
3021 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3022 /// specific condition code, returning the condition code and the LHS/RHS of the
3023 /// comparison to make.
3024 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3025 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3027 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3028 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3029 // X > -1 -> X == 0, jump !sign.
3030 RHS = DAG.getConstant(0, RHS.getValueType());
3031 return X86::COND_NS;
3032 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3033 // X < 0 -> X == 0, jump on sign.
3035 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3037 RHS = DAG.getConstant(0, RHS.getValueType());
3038 return X86::COND_LE;
3042 switch (SetCCOpcode) {
3043 default: llvm_unreachable("Invalid integer condition!");
3044 case ISD::SETEQ: return X86::COND_E;
3045 case ISD::SETGT: return X86::COND_G;
3046 case ISD::SETGE: return X86::COND_GE;
3047 case ISD::SETLT: return X86::COND_L;
3048 case ISD::SETLE: return X86::COND_LE;
3049 case ISD::SETNE: return X86::COND_NE;
3050 case ISD::SETULT: return X86::COND_B;
3051 case ISD::SETUGT: return X86::COND_A;
3052 case ISD::SETULE: return X86::COND_BE;
3053 case ISD::SETUGE: return X86::COND_AE;
3057 // First determine if it is required or is profitable to flip the operands.
3059 // If LHS is a foldable load, but RHS is not, flip the condition.
3060 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3061 !ISD::isNON_EXTLoad(RHS.getNode())) {
3062 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3063 std::swap(LHS, RHS);
3066 switch (SetCCOpcode) {
3072 std::swap(LHS, RHS);
3076 // On a floating point condition, the flags are set as follows:
3078 // 0 | 0 | 0 | X > Y
3079 // 0 | 0 | 1 | X < Y
3080 // 1 | 0 | 0 | X == Y
3081 // 1 | 1 | 1 | unordered
3082 switch (SetCCOpcode) {
3083 default: llvm_unreachable("Condcode should be pre-legalized away");
3085 case ISD::SETEQ: return X86::COND_E;
3086 case ISD::SETOLT: // flipped
3088 case ISD::SETGT: return X86::COND_A;
3089 case ISD::SETOLE: // flipped
3091 case ISD::SETGE: return X86::COND_AE;
3092 case ISD::SETUGT: // flipped
3094 case ISD::SETLT: return X86::COND_B;
3095 case ISD::SETUGE: // flipped
3097 case ISD::SETLE: return X86::COND_BE;
3099 case ISD::SETNE: return X86::COND_NE;
3100 case ISD::SETUO: return X86::COND_P;
3101 case ISD::SETO: return X86::COND_NP;
3103 case ISD::SETUNE: return X86::COND_INVALID;
3107 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3108 /// code. Current x86 isa includes the following FP cmov instructions:
3109 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3110 static bool hasFPCMov(unsigned X86CC) {
3126 /// isFPImmLegal - Returns true if the target can instruction select the
3127 /// specified FP immediate natively. If false, the legalizer will
3128 /// materialize the FP immediate as a load from a constant pool.
3129 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3130 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3131 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3137 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3138 /// the specified range (L, H].
3139 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3140 return (Val < 0) || (Val >= Low && Val < Hi);
3143 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3144 /// specified value.
3145 static bool isUndefOrEqual(int Val, int CmpVal) {
3146 if (Val < 0 || Val == CmpVal)
3151 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3152 /// from position Pos and ending in Pos+Size, falls within the specified
3153 /// sequential range (L, L+Pos]. or is undef.
3154 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3155 int Pos, int Size, int Low) {
3156 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3157 if (!isUndefOrEqual(Mask[i], Low))
3162 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3163 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3164 /// the second operand.
3165 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3166 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3167 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3168 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3169 return (Mask[0] < 2 && Mask[1] < 2);
3173 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3174 /// is suitable for input to PSHUFHW.
3175 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3176 if (VT != MVT::v8i16)
3179 // Lower quadword copied in order or undef.
3180 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3183 // Upper quadword shuffled.
3184 for (unsigned i = 4; i != 8; ++i)
3185 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3191 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3192 /// is suitable for input to PSHUFLW.
3193 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3194 if (VT != MVT::v8i16)
3197 // Upper quadword copied in order.
3198 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3201 // Lower quadword shuffled.
3202 for (unsigned i = 0; i != 4; ++i)
3209 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3210 /// is suitable for input to PALIGNR.
3211 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3212 const X86Subtarget *Subtarget) {
3213 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3214 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3217 unsigned NumElts = VT.getVectorNumElements();
3218 unsigned NumLanes = VT.getSizeInBits()/128;
3219 unsigned NumLaneElts = NumElts/NumLanes;
3221 // Do not handle 64-bit element shuffles with palignr.
3222 if (NumLaneElts == 2)
3225 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3227 for (i = 0; i != NumLaneElts; ++i) {
3232 // Lane is all undef, go to next lane
3233 if (i == NumLaneElts)
3236 int Start = Mask[i+l];
3238 // Make sure its in this lane in one of the sources
3239 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3240 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3243 // If not lane 0, then we must match lane 0
3244 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3247 // Correct second source to be contiguous with first source
3248 if (Start >= (int)NumElts)
3249 Start -= NumElts - NumLaneElts;
3251 // Make sure we're shifting in the right direction.
3252 if (Start <= (int)(i+l))
3257 // Check the rest of the elements to see if they are consecutive.
3258 for (++i; i != NumLaneElts; ++i) {
3259 int Idx = Mask[i+l];
3261 // Make sure its in this lane
3262 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3263 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3266 // If not lane 0, then we must match lane 0
3267 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3270 if (Idx >= (int)NumElts)
3271 Idx -= NumElts - NumLaneElts;
3273 if (!isUndefOrEqual(Idx, Start+i))
3282 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3283 /// the two vector operands have swapped position.
3284 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3285 unsigned NumElems) {
3286 for (unsigned i = 0; i != NumElems; ++i) {
3290 else if (idx < (int)NumElems)
3291 Mask[i] = idx + NumElems;
3293 Mask[i] = idx - NumElems;
3297 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3298 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3299 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3300 /// reverse of what x86 shuffles want.
3301 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3302 bool Commuted = false) {
3303 if (!HasAVX && VT.getSizeInBits() == 256)
3306 unsigned NumElems = VT.getVectorNumElements();
3307 unsigned NumLanes = VT.getSizeInBits()/128;
3308 unsigned NumLaneElems = NumElems/NumLanes;
3310 if (NumLaneElems != 2 && NumLaneElems != 4)
3313 // VSHUFPSY divides the resulting vector into 4 chunks.
3314 // The sources are also splitted into 4 chunks, and each destination
3315 // chunk must come from a different source chunk.
3317 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3318 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3320 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3321 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3323 // VSHUFPDY divides the resulting vector into 4 chunks.
3324 // The sources are also splitted into 4 chunks, and each destination
3325 // chunk must come from a different source chunk.
3327 // SRC1 => X3 X2 X1 X0
3328 // SRC2 => Y3 Y2 Y1 Y0
3330 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3332 unsigned HalfLaneElems = NumLaneElems/2;
3333 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3334 for (unsigned i = 0; i != NumLaneElems; ++i) {
3335 int Idx = Mask[i+l];
3336 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3337 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3339 // For VSHUFPSY, the mask of the second half must be the same as the
3340 // first but with the appropriate offsets. This works in the same way as
3341 // VPERMILPS works with masks.
3342 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3344 if (!isUndefOrEqual(Idx, Mask[i]+l))
3352 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3353 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3354 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3355 unsigned NumElems = VT.getVectorNumElements();
3357 if (VT.getSizeInBits() != 128)
3363 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3364 return isUndefOrEqual(Mask[0], 6) &&
3365 isUndefOrEqual(Mask[1], 7) &&
3366 isUndefOrEqual(Mask[2], 2) &&
3367 isUndefOrEqual(Mask[3], 3);
3370 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3371 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3373 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3374 unsigned NumElems = VT.getVectorNumElements();
3376 if (VT.getSizeInBits() != 128)
3382 return isUndefOrEqual(Mask[0], 2) &&
3383 isUndefOrEqual(Mask[1], 3) &&
3384 isUndefOrEqual(Mask[2], 2) &&
3385 isUndefOrEqual(Mask[3], 3);
3388 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3389 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3390 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3391 if (VT.getSizeInBits() != 128)
3394 unsigned NumElems = VT.getVectorNumElements();
3396 if (NumElems != 2 && NumElems != 4)
3399 for (unsigned i = 0; i != NumElems/2; ++i)
3400 if (!isUndefOrEqual(Mask[i], i + NumElems))
3403 for (unsigned i = NumElems/2; i != NumElems; ++i)
3404 if (!isUndefOrEqual(Mask[i], i))
3410 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3411 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3412 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3413 unsigned NumElems = VT.getVectorNumElements();
3415 if ((NumElems != 2 && NumElems != 4)
3416 || VT.getSizeInBits() > 128)
3419 for (unsigned i = 0; i != NumElems/2; ++i)
3420 if (!isUndefOrEqual(Mask[i], i))
3423 for (unsigned i = 0; i != NumElems/2; ++i)
3424 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3430 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3431 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3432 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3433 bool HasAVX2, bool V2IsSplat = false) {
3434 unsigned NumElts = VT.getVectorNumElements();
3436 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3437 "Unsupported vector type for unpckh");
3439 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3440 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3443 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3444 // independently on 128-bit lanes.
3445 unsigned NumLanes = VT.getSizeInBits()/128;
3446 unsigned NumLaneElts = NumElts/NumLanes;
3448 for (unsigned l = 0; l != NumLanes; ++l) {
3449 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3450 i != (l+1)*NumLaneElts;
3453 int BitI1 = Mask[i+1];
3454 if (!isUndefOrEqual(BitI, j))
3457 if (!isUndefOrEqual(BitI1, NumElts))
3460 if (!isUndefOrEqual(BitI1, j + NumElts))
3469 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3470 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3471 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3472 bool HasAVX2, bool V2IsSplat = false) {
3473 unsigned NumElts = VT.getVectorNumElements();
3475 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3476 "Unsupported vector type for unpckh");
3478 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3479 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3482 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3483 // independently on 128-bit lanes.
3484 unsigned NumLanes = VT.getSizeInBits()/128;
3485 unsigned NumLaneElts = NumElts/NumLanes;
3487 for (unsigned l = 0; l != NumLanes; ++l) {
3488 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3489 i != (l+1)*NumLaneElts; i += 2, ++j) {
3491 int BitI1 = Mask[i+1];
3492 if (!isUndefOrEqual(BitI, j))
3495 if (isUndefOrEqual(BitI1, NumElts))
3498 if (!isUndefOrEqual(BitI1, j+NumElts))
3506 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3507 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3509 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3511 unsigned NumElts = VT.getVectorNumElements();
3513 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3514 "Unsupported vector type for unpckh");
3516 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3517 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3520 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3521 // FIXME: Need a better way to get rid of this, there's no latency difference
3522 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3523 // the former later. We should also remove the "_undef" special mask.
3524 if (NumElts == 4 && VT.getSizeInBits() == 256)
3527 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3528 // independently on 128-bit lanes.
3529 unsigned NumLanes = VT.getSizeInBits()/128;
3530 unsigned NumLaneElts = NumElts/NumLanes;
3532 for (unsigned l = 0; l != NumLanes; ++l) {
3533 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3534 i != (l+1)*NumLaneElts;
3537 int BitI1 = Mask[i+1];
3539 if (!isUndefOrEqual(BitI, j))
3541 if (!isUndefOrEqual(BitI1, j))
3549 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3550 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3552 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3553 unsigned NumElts = VT.getVectorNumElements();
3555 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3556 "Unsupported vector type for unpckh");
3558 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3559 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3562 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3563 // independently on 128-bit lanes.
3564 unsigned NumLanes = VT.getSizeInBits()/128;
3565 unsigned NumLaneElts = NumElts/NumLanes;
3567 for (unsigned l = 0; l != NumLanes; ++l) {
3568 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3569 i != (l+1)*NumLaneElts; i += 2, ++j) {
3571 int BitI1 = Mask[i+1];
3572 if (!isUndefOrEqual(BitI, j))
3574 if (!isUndefOrEqual(BitI1, j))
3581 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3582 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3583 /// MOVSD, and MOVD, i.e. setting the lowest element.
3584 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3585 if (VT.getVectorElementType().getSizeInBits() < 32)
3587 if (VT.getSizeInBits() == 256)
3590 unsigned NumElts = VT.getVectorNumElements();
3592 if (!isUndefOrEqual(Mask[0], NumElts))
3595 for (unsigned i = 1; i != NumElts; ++i)
3596 if (!isUndefOrEqual(Mask[i], i))
3602 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3603 /// as permutations between 128-bit chunks or halves. As an example: this
3605 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3606 /// The first half comes from the second half of V1 and the second half from the
3607 /// the second half of V2.
3608 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3609 if (!HasAVX || VT.getSizeInBits() != 256)
3612 // The shuffle result is divided into half A and half B. In total the two
3613 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3614 // B must come from C, D, E or F.
3615 unsigned HalfSize = VT.getVectorNumElements()/2;
3616 bool MatchA = false, MatchB = false;
3618 // Check if A comes from one of C, D, E, F.
3619 for (unsigned Half = 0; Half != 4; ++Half) {
3620 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3626 // Check if B comes from one of C, D, E, F.
3627 for (unsigned Half = 0; Half != 4; ++Half) {
3628 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3634 return MatchA && MatchB;
3637 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3638 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3639 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3640 EVT VT = SVOp->getValueType(0);
3642 unsigned HalfSize = VT.getVectorNumElements()/2;
3644 unsigned FstHalf = 0, SndHalf = 0;
3645 for (unsigned i = 0; i < HalfSize; ++i) {
3646 if (SVOp->getMaskElt(i) > 0) {
3647 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3651 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3652 if (SVOp->getMaskElt(i) > 0) {
3653 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3658 return (FstHalf | (SndHalf << 4));
3661 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3662 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3663 /// Note that VPERMIL mask matching is different depending whether theunderlying
3664 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3665 /// to the same elements of the low, but to the higher half of the source.
3666 /// In VPERMILPD the two lanes could be shuffled independently of each other
3667 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3668 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3672 unsigned NumElts = VT.getVectorNumElements();
3673 // Only match 256-bit with 32/64-bit types
3674 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3677 unsigned NumLanes = VT.getSizeInBits()/128;
3678 unsigned LaneSize = NumElts/NumLanes;
3679 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3680 for (unsigned i = 0; i != LaneSize; ++i) {
3681 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3683 if (NumElts != 8 || l == 0)
3685 // VPERMILPS handling
3688 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3696 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3697 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3698 /// element of vector 2 and the other elements to come from vector 1 in order.
3699 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3700 bool V2IsSplat = false, bool V2IsUndef = false) {
3701 unsigned NumOps = VT.getVectorNumElements();
3702 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3705 if (!isUndefOrEqual(Mask[0], 0))
3708 for (unsigned i = 1; i != NumOps; ++i)
3709 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3710 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3711 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3717 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3718 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3719 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3720 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3721 const X86Subtarget *Subtarget) {
3722 if (!Subtarget->hasSSE3())
3725 unsigned NumElems = VT.getVectorNumElements();
3727 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3728 (VT.getSizeInBits() == 256 && NumElems != 8))
3731 // "i+1" is the value the indexed mask element must have
3732 for (unsigned i = 0; i != NumElems; i += 2)
3733 if (!isUndefOrEqual(Mask[i], i+1) ||
3734 !isUndefOrEqual(Mask[i+1], i+1))
3740 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3741 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3742 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3743 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3744 const X86Subtarget *Subtarget) {
3745 if (!Subtarget->hasSSE3())
3748 unsigned NumElems = VT.getVectorNumElements();
3750 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3751 (VT.getSizeInBits() == 256 && NumElems != 8))
3754 // "i" is the value the indexed mask element must have
3755 for (unsigned i = 0; i != NumElems; i += 2)
3756 if (!isUndefOrEqual(Mask[i], i) ||
3757 !isUndefOrEqual(Mask[i+1], i))
3763 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3764 /// specifies a shuffle of elements that is suitable for input to 256-bit
3765 /// version of MOVDDUP.
3766 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3767 unsigned NumElts = VT.getVectorNumElements();
3769 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3772 for (unsigned i = 0; i != NumElts/2; ++i)
3773 if (!isUndefOrEqual(Mask[i], 0))
3775 for (unsigned i = NumElts/2; i != NumElts; ++i)
3776 if (!isUndefOrEqual(Mask[i], NumElts/2))
3781 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3782 /// specifies a shuffle of elements that is suitable for input to 128-bit
3783 /// version of MOVDDUP.
3784 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3785 if (VT.getSizeInBits() != 128)
3788 unsigned e = VT.getVectorNumElements() / 2;
3789 for (unsigned i = 0; i != e; ++i)
3790 if (!isUndefOrEqual(Mask[i], i))
3792 for (unsigned i = 0; i != e; ++i)
3793 if (!isUndefOrEqual(Mask[e+i], i))
3798 /// isVEXTRACTF128Index - Return true if the specified
3799 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3800 /// suitable for input to VEXTRACTF128.
3801 bool X86::isVEXTRACTF128Index(SDNode *N) {
3802 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3805 // The index should be aligned on a 128-bit boundary.
3807 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3809 unsigned VL = N->getValueType(0).getVectorNumElements();
3810 unsigned VBits = N->getValueType(0).getSizeInBits();
3811 unsigned ElSize = VBits / VL;
3812 bool Result = (Index * ElSize) % 128 == 0;
3817 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3818 /// operand specifies a subvector insert that is suitable for input to
3820 bool X86::isVINSERTF128Index(SDNode *N) {
3821 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3824 // The index should be aligned on a 128-bit boundary.
3826 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3828 unsigned VL = N->getValueType(0).getVectorNumElements();
3829 unsigned VBits = N->getValueType(0).getSizeInBits();
3830 unsigned ElSize = VBits / VL;
3831 bool Result = (Index * ElSize) % 128 == 0;
3836 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3837 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3838 /// Handles 128-bit and 256-bit.
3839 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3840 EVT VT = N->getValueType(0);
3842 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3843 "Unsupported vector type for PSHUF/SHUFP");
3845 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3846 // independently on 128-bit lanes.
3847 unsigned NumElts = VT.getVectorNumElements();
3848 unsigned NumLanes = VT.getSizeInBits()/128;
3849 unsigned NumLaneElts = NumElts/NumLanes;
3851 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3852 "Only supports 2 or 4 elements per lane");
3854 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3856 for (unsigned i = 0; i != NumElts; ++i) {
3857 int Elt = N->getMaskElt(i);
3858 if (Elt < 0) continue;
3860 unsigned ShAmt = i << Shift;
3861 if (ShAmt >= 8) ShAmt -= 8;
3862 Mask |= Elt << ShAmt;
3868 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3869 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3870 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3872 // 8 nodes, but we only care about the last 4.
3873 for (unsigned i = 7; i >= 4; --i) {
3874 int Val = N->getMaskElt(i);
3883 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3884 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3885 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3887 // 8 nodes, but we only care about the first 4.
3888 for (int i = 3; i >= 0; --i) {
3889 int Val = N->getMaskElt(i);
3898 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3899 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3900 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3901 EVT VT = SVOp->getValueType(0);
3902 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3904 unsigned NumElts = VT.getVectorNumElements();
3905 unsigned NumLanes = VT.getSizeInBits()/128;
3906 unsigned NumLaneElts = NumElts/NumLanes;
3910 for (i = 0; i != NumElts; ++i) {
3911 Val = SVOp->getMaskElt(i);
3915 if (Val >= (int)NumElts)
3916 Val -= NumElts - NumLaneElts;
3918 assert(Val - i > 0 && "PALIGNR imm should be positive");
3919 return (Val - i) * EltSize;
3922 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3923 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3925 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3926 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3927 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3930 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3932 EVT VecVT = N->getOperand(0).getValueType();
3933 EVT ElVT = VecVT.getVectorElementType();
3935 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3936 return Index / NumElemsPerChunk;
3939 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3940 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3942 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3943 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3944 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3947 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3949 EVT VecVT = N->getValueType(0);
3950 EVT ElVT = VecVT.getVectorElementType();
3952 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3953 return Index / NumElemsPerChunk;
3956 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3958 bool X86::isZeroNode(SDValue Elt) {
3959 return ((isa<ConstantSDNode>(Elt) &&
3960 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3961 (isa<ConstantFPSDNode>(Elt) &&
3962 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3965 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3966 /// their permute mask.
3967 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3968 SelectionDAG &DAG) {
3969 EVT VT = SVOp->getValueType(0);
3970 unsigned NumElems = VT.getVectorNumElements();
3971 SmallVector<int, 8> MaskVec;
3973 for (unsigned i = 0; i != NumElems; ++i) {
3974 int idx = SVOp->getMaskElt(i);
3976 MaskVec.push_back(idx);
3977 else if (idx < (int)NumElems)
3978 MaskVec.push_back(idx + NumElems);
3980 MaskVec.push_back(idx - NumElems);
3982 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3983 SVOp->getOperand(0), &MaskVec[0]);
3986 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3987 /// match movhlps. The lower half elements should come from upper half of
3988 /// V1 (and in order), and the upper half elements should come from the upper
3989 /// half of V2 (and in order).
3990 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
3991 if (VT.getSizeInBits() != 128)
3993 if (VT.getVectorNumElements() != 4)
3995 for (unsigned i = 0, e = 2; i != e; ++i)
3996 if (!isUndefOrEqual(Mask[i], i+2))
3998 for (unsigned i = 2; i != 4; ++i)
3999 if (!isUndefOrEqual(Mask[i], i+4))
4004 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4005 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4007 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4008 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4010 N = N->getOperand(0).getNode();
4011 if (!ISD::isNON_EXTLoad(N))
4014 *LD = cast<LoadSDNode>(N);
4018 // Test whether the given value is a vector value which will be legalized
4020 static bool WillBeConstantPoolLoad(SDNode *N) {
4021 if (N->getOpcode() != ISD::BUILD_VECTOR)
4024 // Check for any non-constant elements.
4025 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4026 switch (N->getOperand(i).getNode()->getOpcode()) {
4028 case ISD::ConstantFP:
4035 // Vectors of all-zeros and all-ones are materialized with special
4036 // instructions rather than being loaded.
4037 return !ISD::isBuildVectorAllZeros(N) &&
4038 !ISD::isBuildVectorAllOnes(N);
4041 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4042 /// match movlp{s|d}. The lower half elements should come from lower half of
4043 /// V1 (and in order), and the upper half elements should come from the upper
4044 /// half of V2 (and in order). And since V1 will become the source of the
4045 /// MOVLP, it must be either a vector load or a scalar load to vector.
4046 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4047 ArrayRef<int> Mask, EVT VT) {
4048 if (VT.getSizeInBits() != 128)
4051 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4053 // Is V2 is a vector load, don't do this transformation. We will try to use
4054 // load folding shufps op.
4055 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4058 unsigned NumElems = VT.getVectorNumElements();
4060 if (NumElems != 2 && NumElems != 4)
4062 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4063 if (!isUndefOrEqual(Mask[i], i))
4065 for (unsigned i = NumElems/2; i != NumElems; ++i)
4066 if (!isUndefOrEqual(Mask[i], i+NumElems))
4071 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4073 static bool isSplatVector(SDNode *N) {
4074 if (N->getOpcode() != ISD::BUILD_VECTOR)
4077 SDValue SplatValue = N->getOperand(0);
4078 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4079 if (N->getOperand(i) != SplatValue)
4084 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4085 /// to an zero vector.
4086 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4087 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4088 SDValue V1 = N->getOperand(0);
4089 SDValue V2 = N->getOperand(1);
4090 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4091 for (unsigned i = 0; i != NumElems; ++i) {
4092 int Idx = N->getMaskElt(i);
4093 if (Idx >= (int)NumElems) {
4094 unsigned Opc = V2.getOpcode();
4095 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4097 if (Opc != ISD::BUILD_VECTOR ||
4098 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4100 } else if (Idx >= 0) {
4101 unsigned Opc = V1.getOpcode();
4102 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4104 if (Opc != ISD::BUILD_VECTOR ||
4105 !X86::isZeroNode(V1.getOperand(Idx)))
4112 /// getZeroVector - Returns a vector of specified type with all zero elements.
4114 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4115 SelectionDAG &DAG, DebugLoc dl) {
4116 assert(VT.isVector() && "Expected a vector type");
4118 // Always build SSE zero vectors as <4 x i32> bitcasted
4119 // to their dest type. This ensures they get CSE'd.
4121 if (VT.getSizeInBits() == 128) { // SSE
4122 if (Subtarget->hasSSE2()) { // SSE2
4123 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4124 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4126 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4127 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4129 } else if (VT.getSizeInBits() == 256) { // AVX
4130 if (Subtarget->hasAVX2()) { // AVX2
4131 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4132 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4133 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4135 // 256-bit logic and arithmetic instructions in AVX are all
4136 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4137 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4138 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4139 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4142 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4145 /// getOnesVector - Returns a vector of specified type with all bits set.
4146 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4147 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4148 /// Then bitcast to their original type, ensuring they get CSE'd.
4149 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4151 assert(VT.isVector() && "Expected a vector type");
4152 assert((VT.is128BitVector() || VT.is256BitVector())
4153 && "Expected a 128-bit or 256-bit vector type");
4155 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4157 if (VT.getSizeInBits() == 256) {
4158 if (HasAVX2) { // AVX2
4159 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4160 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4162 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4163 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4164 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4165 Vec = Insert128BitVector(InsV, Vec,
4166 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4169 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4172 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4175 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4176 /// that point to V2 points to its first element.
4177 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4178 for (unsigned i = 0; i != NumElems; ++i) {
4179 if (Mask[i] > (int)NumElems) {
4185 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4186 /// operation of specified width.
4187 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4189 unsigned NumElems = VT.getVectorNumElements();
4190 SmallVector<int, 8> Mask;
4191 Mask.push_back(NumElems);
4192 for (unsigned i = 1; i != NumElems; ++i)
4194 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4197 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4198 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4200 unsigned NumElems = VT.getVectorNumElements();
4201 SmallVector<int, 8> Mask;
4202 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4204 Mask.push_back(i + NumElems);
4206 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4209 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4210 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4212 unsigned NumElems = VT.getVectorNumElements();
4213 unsigned Half = NumElems/2;
4214 SmallVector<int, 8> Mask;
4215 for (unsigned i = 0; i != Half; ++i) {
4216 Mask.push_back(i + Half);
4217 Mask.push_back(i + NumElems + Half);
4219 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4222 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4223 // a generic shuffle instruction because the target has no such instructions.
4224 // Generate shuffles which repeat i16 and i8 several times until they can be
4225 // represented by v4f32 and then be manipulated by target suported shuffles.
4226 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4227 EVT VT = V.getValueType();
4228 int NumElems = VT.getVectorNumElements();
4229 DebugLoc dl = V.getDebugLoc();
4231 while (NumElems > 4) {
4232 if (EltNo < NumElems/2) {
4233 V = getUnpackl(DAG, dl, VT, V, V);
4235 V = getUnpackh(DAG, dl, VT, V, V);
4236 EltNo -= NumElems/2;
4243 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4244 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4245 EVT VT = V.getValueType();
4246 DebugLoc dl = V.getDebugLoc();
4247 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4248 && "Vector size not supported");
4250 if (VT.getSizeInBits() == 128) {
4251 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4252 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4253 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4256 // To use VPERMILPS to splat scalars, the second half of indicies must
4257 // refer to the higher part, which is a duplication of the lower one,
4258 // because VPERMILPS can only handle in-lane permutations.
4259 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4260 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4262 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4263 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4267 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4270 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4271 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4272 EVT SrcVT = SV->getValueType(0);
4273 SDValue V1 = SV->getOperand(0);
4274 DebugLoc dl = SV->getDebugLoc();
4276 int EltNo = SV->getSplatIndex();
4277 int NumElems = SrcVT.getVectorNumElements();
4278 unsigned Size = SrcVT.getSizeInBits();
4280 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4281 "Unknown how to promote splat for type");
4283 // Extract the 128-bit part containing the splat element and update
4284 // the splat element index when it refers to the higher register.
4286 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4287 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4289 EltNo -= NumElems/2;
4292 // All i16 and i8 vector types can't be used directly by a generic shuffle
4293 // instruction because the target has no such instruction. Generate shuffles
4294 // which repeat i16 and i8 several times until they fit in i32, and then can
4295 // be manipulated by target suported shuffles.
4296 EVT EltVT = SrcVT.getVectorElementType();
4297 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4298 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4300 // Recreate the 256-bit vector and place the same 128-bit vector
4301 // into the low and high part. This is necessary because we want
4302 // to use VPERM* to shuffle the vectors
4304 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4305 DAG.getConstant(0, MVT::i32), DAG, dl);
4306 V1 = Insert128BitVector(InsV, V1,
4307 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4310 return getLegalSplat(DAG, V1, EltNo);
4313 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4314 /// vector of zero or undef vector. This produces a shuffle where the low
4315 /// element of V2 is swizzled into the zero/undef vector, landing at element
4316 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4317 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4319 const X86Subtarget *Subtarget,
4320 SelectionDAG &DAG) {
4321 EVT VT = V2.getValueType();
4323 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4324 unsigned NumElems = VT.getVectorNumElements();
4325 SmallVector<int, 16> MaskVec;
4326 for (unsigned i = 0; i != NumElems; ++i)
4327 // If this is the insertion idx, put the low elt of V2 here.
4328 MaskVec.push_back(i == Idx ? NumElems : i);
4329 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4332 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4333 /// element of the result of the vector shuffle.
4334 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4337 return SDValue(); // Limit search depth.
4339 SDValue V = SDValue(N, 0);
4340 EVT VT = V.getValueType();
4341 unsigned Opcode = V.getOpcode();
4343 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4344 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4345 Index = SV->getMaskElt(Index);
4348 return DAG.getUNDEF(VT.getVectorElementType());
4350 unsigned NumElems = VT.getVectorNumElements();
4351 SDValue NewV = (Index < (int)NumElems) ? SV->getOperand(0)
4352 : SV->getOperand(1);
4353 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4356 // Recurse into target specific vector shuffles to find scalars.
4357 if (isTargetShuffle(Opcode)) {
4358 unsigned NumElems = VT.getVectorNumElements();
4359 SmallVector<unsigned, 16> ShuffleMask;
4364 ImmN = N->getOperand(N->getNumOperands()-1);
4365 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4368 case X86ISD::UNPCKH:
4369 DecodeUNPCKHMask(VT, ShuffleMask);
4371 case X86ISD::UNPCKL:
4372 DecodeUNPCKLMask(VT, ShuffleMask);
4374 case X86ISD::MOVHLPS:
4375 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4377 case X86ISD::MOVLHPS:
4378 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4380 case X86ISD::PSHUFD:
4381 case X86ISD::VPERMILP:
4382 ImmN = N->getOperand(N->getNumOperands()-1);
4383 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4386 case X86ISD::PSHUFHW:
4387 ImmN = N->getOperand(N->getNumOperands()-1);
4388 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4391 case X86ISD::PSHUFLW:
4392 ImmN = N->getOperand(N->getNumOperands()-1);
4393 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4397 case X86ISD::MOVSD: {
4398 // The index 0 always comes from the first element of the second source,
4399 // this is why MOVSS and MOVSD are used in the first place. The other
4400 // elements come from the other positions of the first source vector.
4401 unsigned OpNum = (Index == 0) ? 1 : 0;
4402 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4405 case X86ISD::VPERM2X128:
4406 ImmN = N->getOperand(N->getNumOperands()-1);
4407 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4410 case X86ISD::MOVDDUP:
4411 case X86ISD::MOVLHPD:
4412 case X86ISD::MOVLPD:
4413 case X86ISD::MOVLPS:
4414 case X86ISD::MOVSHDUP:
4415 case X86ISD::MOVSLDUP:
4416 case X86ISD::PALIGN:
4417 return SDValue(); // Not yet implemented.
4418 default: llvm_unreachable("unknown target shuffle node");
4421 Index = ShuffleMask[Index];
4423 return DAG.getUNDEF(VT.getVectorElementType());
4425 SDValue NewV = (Index < (int)NumElems) ? N->getOperand(0)
4427 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4431 // Actual nodes that may contain scalar elements
4432 if (Opcode == ISD::BITCAST) {
4433 V = V.getOperand(0);
4434 EVT SrcVT = V.getValueType();
4435 unsigned NumElems = VT.getVectorNumElements();
4437 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4441 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4442 return (Index == 0) ? V.getOperand(0)
4443 : DAG.getUNDEF(VT.getVectorElementType());
4445 if (V.getOpcode() == ISD::BUILD_VECTOR)
4446 return V.getOperand(Index);
4451 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4452 /// shuffle operation which come from a consecutively from a zero. The
4453 /// search can start in two different directions, from left or right.
4455 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4456 bool ZerosFromLeft, SelectionDAG &DAG) {
4459 while (i < NumElems) {
4460 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4461 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4462 if (!(Elt.getNode() &&
4463 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4471 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4472 /// MaskE correspond consecutively to elements from one of the vector operands,
4473 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4475 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4476 int OpIdx, int NumElems, unsigned &OpNum) {
4477 bool SeenV1 = false;
4478 bool SeenV2 = false;
4480 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4481 int Idx = SVOp->getMaskElt(i);
4482 // Ignore undef indicies
4491 // Only accept consecutive elements from the same vector
4492 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4496 OpNum = SeenV1 ? 0 : 1;
4500 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4501 /// logical left shift of a vector.
4502 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4503 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4504 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4505 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4506 false /* check zeros from right */, DAG);
4512 // Considering the elements in the mask that are not consecutive zeros,
4513 // check if they consecutively come from only one of the source vectors.
4515 // V1 = {X, A, B, C} 0
4517 // vector_shuffle V1, V2 <1, 2, 3, X>
4519 if (!isShuffleMaskConsecutive(SVOp,
4520 0, // Mask Start Index
4521 NumElems-NumZeros-1, // Mask End Index
4522 NumZeros, // Where to start looking in the src vector
4523 NumElems, // Number of elements in vector
4524 OpSrc)) // Which source operand ?
4529 ShVal = SVOp->getOperand(OpSrc);
4533 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4534 /// logical left shift of a vector.
4535 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4536 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4537 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4538 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4539 true /* check zeros from left */, DAG);
4545 // Considering the elements in the mask that are not consecutive zeros,
4546 // check if they consecutively come from only one of the source vectors.
4548 // 0 { A, B, X, X } = V2
4550 // vector_shuffle V1, V2 <X, X, 4, 5>
4552 if (!isShuffleMaskConsecutive(SVOp,
4553 NumZeros, // Mask Start Index
4554 NumElems-1, // Mask End Index
4555 0, // Where to start looking in the src vector
4556 NumElems, // Number of elements in vector
4557 OpSrc)) // Which source operand ?
4562 ShVal = SVOp->getOperand(OpSrc);
4566 /// isVectorShift - Returns true if the shuffle can be implemented as a
4567 /// logical left or right shift of a vector.
4568 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4569 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4570 // Although the logic below support any bitwidth size, there are no
4571 // shift instructions which handle more than 128-bit vectors.
4572 if (SVOp->getValueType(0).getSizeInBits() > 128)
4575 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4576 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4582 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4584 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4585 unsigned NumNonZero, unsigned NumZero,
4587 const X86Subtarget* Subtarget,
4588 const TargetLowering &TLI) {
4592 DebugLoc dl = Op.getDebugLoc();
4595 for (unsigned i = 0; i < 16; ++i) {
4596 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4597 if (ThisIsNonZero && First) {
4599 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4601 V = DAG.getUNDEF(MVT::v8i16);
4606 SDValue ThisElt(0, 0), LastElt(0, 0);
4607 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4608 if (LastIsNonZero) {
4609 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4610 MVT::i16, Op.getOperand(i-1));
4612 if (ThisIsNonZero) {
4613 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4614 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4615 ThisElt, DAG.getConstant(8, MVT::i8));
4617 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4621 if (ThisElt.getNode())
4622 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4623 DAG.getIntPtrConstant(i/2));
4627 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4630 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4632 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4633 unsigned NumNonZero, unsigned NumZero,
4635 const X86Subtarget* Subtarget,
4636 const TargetLowering &TLI) {
4640 DebugLoc dl = Op.getDebugLoc();
4643 for (unsigned i = 0; i < 8; ++i) {
4644 bool isNonZero = (NonZeros & (1 << i)) != 0;
4648 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4650 V = DAG.getUNDEF(MVT::v8i16);
4653 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4654 MVT::v8i16, V, Op.getOperand(i),
4655 DAG.getIntPtrConstant(i));
4662 /// getVShift - Return a vector logical shift node.
4664 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4665 unsigned NumBits, SelectionDAG &DAG,
4666 const TargetLowering &TLI, DebugLoc dl) {
4667 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4668 EVT ShVT = MVT::v2i64;
4669 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4670 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4671 return DAG.getNode(ISD::BITCAST, dl, VT,
4672 DAG.getNode(Opc, dl, ShVT, SrcOp,
4673 DAG.getConstant(NumBits,
4674 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4678 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4679 SelectionDAG &DAG) const {
4681 // Check if the scalar load can be widened into a vector load. And if
4682 // the address is "base + cst" see if the cst can be "absorbed" into
4683 // the shuffle mask.
4684 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4685 SDValue Ptr = LD->getBasePtr();
4686 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4688 EVT PVT = LD->getValueType(0);
4689 if (PVT != MVT::i32 && PVT != MVT::f32)
4694 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4695 FI = FINode->getIndex();
4697 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4698 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4699 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4700 Offset = Ptr.getConstantOperandVal(1);
4701 Ptr = Ptr.getOperand(0);
4706 // FIXME: 256-bit vector instructions don't require a strict alignment,
4707 // improve this code to support it better.
4708 unsigned RequiredAlign = VT.getSizeInBits()/8;
4709 SDValue Chain = LD->getChain();
4710 // Make sure the stack object alignment is at least 16 or 32.
4711 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4712 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4713 if (MFI->isFixedObjectIndex(FI)) {
4714 // Can't change the alignment. FIXME: It's possible to compute
4715 // the exact stack offset and reference FI + adjust offset instead.
4716 // If someone *really* cares about this. That's the way to implement it.
4719 MFI->setObjectAlignment(FI, RequiredAlign);
4723 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4724 // Ptr + (Offset & ~15).
4727 if ((Offset % RequiredAlign) & 3)
4729 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4731 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4732 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4734 int EltNo = (Offset - StartOffset) >> 2;
4735 int NumElems = VT.getVectorNumElements();
4737 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4738 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4739 LD->getPointerInfo().getWithOffset(StartOffset),
4740 false, false, false, 0);
4742 SmallVector<int, 8> Mask;
4743 for (int i = 0; i < NumElems; ++i)
4744 Mask.push_back(EltNo);
4746 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4752 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4753 /// vector of type 'VT', see if the elements can be replaced by a single large
4754 /// load which has the same value as a build_vector whose operands are 'elts'.
4756 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4758 /// FIXME: we'd also like to handle the case where the last elements are zero
4759 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4760 /// There's even a handy isZeroNode for that purpose.
4761 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4762 DebugLoc &DL, SelectionDAG &DAG) {
4763 EVT EltVT = VT.getVectorElementType();
4764 unsigned NumElems = Elts.size();
4766 LoadSDNode *LDBase = NULL;
4767 unsigned LastLoadedElt = -1U;
4769 // For each element in the initializer, see if we've found a load or an undef.
4770 // If we don't find an initial load element, or later load elements are
4771 // non-consecutive, bail out.
4772 for (unsigned i = 0; i < NumElems; ++i) {
4773 SDValue Elt = Elts[i];
4775 if (!Elt.getNode() ||
4776 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4779 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4781 LDBase = cast<LoadSDNode>(Elt.getNode());
4785 if (Elt.getOpcode() == ISD::UNDEF)
4788 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4789 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4794 // If we have found an entire vector of loads and undefs, then return a large
4795 // load of the entire vector width starting at the base pointer. If we found
4796 // consecutive loads for the low half, generate a vzext_load node.
4797 if (LastLoadedElt == NumElems - 1) {
4798 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4799 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4800 LDBase->getPointerInfo(),
4801 LDBase->isVolatile(), LDBase->isNonTemporal(),
4802 LDBase->isInvariant(), 0);
4803 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4804 LDBase->getPointerInfo(),
4805 LDBase->isVolatile(), LDBase->isNonTemporal(),
4806 LDBase->isInvariant(), LDBase->getAlignment());
4807 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4808 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4809 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4810 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4812 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4813 LDBase->getPointerInfo(),
4814 LDBase->getAlignment(),
4815 false/*isVolatile*/, true/*ReadMem*/,
4817 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4822 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4823 /// a vbroadcast node. We support two patterns:
4824 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4825 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4827 /// The scalar load node is returned when a pattern is found,
4828 /// or SDValue() otherwise.
4829 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4830 if (!Subtarget->hasAVX())
4833 EVT VT = Op.getValueType();
4836 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4837 V = V.getOperand(0);
4839 //A suspected load to be broadcasted.
4842 switch (V.getOpcode()) {
4844 // Unknown pattern found.
4847 case ISD::BUILD_VECTOR: {
4848 // The BUILD_VECTOR node must be a splat.
4849 if (!isSplatVector(V.getNode()))
4852 Ld = V.getOperand(0);
4854 // The suspected load node has several users. Make sure that all
4855 // of its users are from the BUILD_VECTOR node.
4856 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4861 case ISD::VECTOR_SHUFFLE: {
4862 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4864 // Shuffles must have a splat mask where the first element is
4866 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4869 SDValue Sc = Op.getOperand(0);
4870 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4873 Ld = Sc.getOperand(0);
4875 // The scalar_to_vector node and the suspected
4876 // load node must have exactly one user.
4877 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4883 // The scalar source must be a normal load.
4884 if (!ISD::isNormalLoad(Ld.getNode()))
4887 // Reject loads that have uses of the chain result
4888 if (Ld->hasAnyUseOfValue(1))
4891 bool Is256 = VT.getSizeInBits() == 256;
4892 bool Is128 = VT.getSizeInBits() == 128;
4893 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4895 // VBroadcast to YMM
4896 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4899 // VBroadcast to XMM
4900 if (Is128 && (ScalarSize == 32))
4903 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4904 // double since there is vbroadcastsd xmm
4905 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
4906 // VBroadcast to YMM
4907 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
4910 // VBroadcast to XMM
4911 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
4915 // Unsupported broadcast.
4920 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4921 DebugLoc dl = Op.getDebugLoc();
4923 EVT VT = Op.getValueType();
4924 EVT ExtVT = VT.getVectorElementType();
4925 unsigned NumElems = Op.getNumOperands();
4927 // Vectors containing all zeros can be matched by pxor and xorps later
4928 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4929 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4930 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4931 if (VT == MVT::v4i32 || VT == MVT::v8i32)
4934 return getZeroVector(VT, Subtarget, DAG, dl);
4937 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4938 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
4939 // vpcmpeqd on 256-bit vectors.
4940 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4941 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
4944 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
4947 SDValue LD = isVectorBroadcast(Op, Subtarget);
4949 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
4951 unsigned EVTBits = ExtVT.getSizeInBits();
4953 unsigned NumZero = 0;
4954 unsigned NumNonZero = 0;
4955 unsigned NonZeros = 0;
4956 bool IsAllConstants = true;
4957 SmallSet<SDValue, 8> Values;
4958 for (unsigned i = 0; i < NumElems; ++i) {
4959 SDValue Elt = Op.getOperand(i);
4960 if (Elt.getOpcode() == ISD::UNDEF)
4963 if (Elt.getOpcode() != ISD::Constant &&
4964 Elt.getOpcode() != ISD::ConstantFP)
4965 IsAllConstants = false;
4966 if (X86::isZeroNode(Elt))
4969 NonZeros |= (1 << i);
4974 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4975 if (NumNonZero == 0)
4976 return DAG.getUNDEF(VT);
4978 // Special case for single non-zero, non-undef, element.
4979 if (NumNonZero == 1) {
4980 unsigned Idx = CountTrailingZeros_32(NonZeros);
4981 SDValue Item = Op.getOperand(Idx);
4983 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4984 // the value are obviously zero, truncate the value to i32 and do the
4985 // insertion that way. Only do this if the value is non-constant or if the
4986 // value is a constant being inserted into element 0. It is cheaper to do
4987 // a constant pool load than it is to do a movd + shuffle.
4988 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4989 (!IsAllConstants || Idx == 0)) {
4990 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4992 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4993 EVT VecVT = MVT::v4i32;
4994 unsigned VecElts = 4;
4996 // Truncate the value (which may itself be a constant) to i32, and
4997 // convert it to a vector with movd (S2V+shuffle to zero extend).
4998 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4999 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5000 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5002 // Now we have our 32-bit value zero extended in the low element of
5003 // a vector. If Idx != 0, swizzle it into place.
5005 SmallVector<int, 4> Mask;
5006 Mask.push_back(Idx);
5007 for (unsigned i = 1; i != VecElts; ++i)
5009 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5010 DAG.getUNDEF(Item.getValueType()),
5013 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5017 // If we have a constant or non-constant insertion into the low element of
5018 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5019 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5020 // depending on what the source datatype is.
5023 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5025 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5026 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5027 if (VT.getSizeInBits() == 256) {
5028 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5029 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5030 Item, DAG.getIntPtrConstant(0));
5032 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5033 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5034 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5035 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5038 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5039 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5040 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5041 if (VT.getSizeInBits() == 256) {
5042 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5043 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5046 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5047 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5049 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5053 // Is it a vector logical left shift?
5054 if (NumElems == 2 && Idx == 1 &&
5055 X86::isZeroNode(Op.getOperand(0)) &&
5056 !X86::isZeroNode(Op.getOperand(1))) {
5057 unsigned NumBits = VT.getSizeInBits();
5058 return getVShift(true, VT,
5059 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5060 VT, Op.getOperand(1)),
5061 NumBits/2, DAG, *this, dl);
5064 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5067 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5068 // is a non-constant being inserted into an element other than the low one,
5069 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5070 // movd/movss) to move this into the low element, then shuffle it into
5072 if (EVTBits == 32) {
5073 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5075 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5076 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5077 SmallVector<int, 8> MaskVec;
5078 for (unsigned i = 0; i < NumElems; i++)
5079 MaskVec.push_back(i == Idx ? 0 : 1);
5080 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5084 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5085 if (Values.size() == 1) {
5086 if (EVTBits == 32) {
5087 // Instead of a shuffle like this:
5088 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5089 // Check if it's possible to issue this instead.
5090 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5091 unsigned Idx = CountTrailingZeros_32(NonZeros);
5092 SDValue Item = Op.getOperand(Idx);
5093 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5094 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5099 // A vector full of immediates; various special cases are already
5100 // handled, so this is best done with a single constant-pool load.
5104 // For AVX-length vectors, build the individual 128-bit pieces and use
5105 // shuffles to put them in place.
5106 if (VT.getSizeInBits() == 256) {
5107 SmallVector<SDValue, 32> V;
5108 for (unsigned i = 0; i != NumElems; ++i)
5109 V.push_back(Op.getOperand(i));
5111 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5113 // Build both the lower and upper subvector.
5114 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5115 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5118 // Recreate the wider vector with the lower and upper part.
5119 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5120 DAG.getConstant(0, MVT::i32), DAG, dl);
5121 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5125 // Let legalizer expand 2-wide build_vectors.
5126 if (EVTBits == 64) {
5127 if (NumNonZero == 1) {
5128 // One half is zero or undef.
5129 unsigned Idx = CountTrailingZeros_32(NonZeros);
5130 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5131 Op.getOperand(Idx));
5132 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5137 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5138 if (EVTBits == 8 && NumElems == 16) {
5139 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5141 if (V.getNode()) return V;
5144 if (EVTBits == 16 && NumElems == 8) {
5145 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5147 if (V.getNode()) return V;
5150 // If element VT is == 32 bits, turn it into a number of shuffles.
5151 SmallVector<SDValue, 8> V(NumElems);
5152 if (NumElems == 4 && NumZero > 0) {
5153 for (unsigned i = 0; i < 4; ++i) {
5154 bool isZero = !(NonZeros & (1 << i));
5156 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5158 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5161 for (unsigned i = 0; i < 2; ++i) {
5162 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5165 V[i] = V[i*2]; // Must be a zero vector.
5168 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5171 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5174 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5179 bool Reverse1 = (NonZeros & 0x3) == 2;
5180 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5184 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5185 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5187 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5190 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5191 // Check for a build vector of consecutive loads.
5192 for (unsigned i = 0; i < NumElems; ++i)
5193 V[i] = Op.getOperand(i);
5195 // Check for elements which are consecutive loads.
5196 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5200 // For SSE 4.1, use insertps to put the high elements into the low element.
5201 if (getSubtarget()->hasSSE41()) {
5203 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5204 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5206 Result = DAG.getUNDEF(VT);
5208 for (unsigned i = 1; i < NumElems; ++i) {
5209 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5210 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5211 Op.getOperand(i), DAG.getIntPtrConstant(i));
5216 // Otherwise, expand into a number of unpckl*, start by extending each of
5217 // our (non-undef) elements to the full vector width with the element in the
5218 // bottom slot of the vector (which generates no code for SSE).
5219 for (unsigned i = 0; i < NumElems; ++i) {
5220 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5221 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5223 V[i] = DAG.getUNDEF(VT);
5226 // Next, we iteratively mix elements, e.g. for v4f32:
5227 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5228 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5229 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5230 unsigned EltStride = NumElems >> 1;
5231 while (EltStride != 0) {
5232 for (unsigned i = 0; i < EltStride; ++i) {
5233 // If V[i+EltStride] is undef and this is the first round of mixing,
5234 // then it is safe to just drop this shuffle: V[i] is already in the
5235 // right place, the one element (since it's the first round) being
5236 // inserted as undef can be dropped. This isn't safe for successive
5237 // rounds because they will permute elements within both vectors.
5238 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5239 EltStride == NumElems/2)
5242 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5251 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5252 // them in a MMX register. This is better than doing a stack convert.
5253 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5254 DebugLoc dl = Op.getDebugLoc();
5255 EVT ResVT = Op.getValueType();
5257 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5258 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5260 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5261 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5262 InVec = Op.getOperand(1);
5263 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5264 unsigned NumElts = ResVT.getVectorNumElements();
5265 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5266 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5267 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5269 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5270 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5271 Mask[0] = 0; Mask[1] = 2;
5272 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5274 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5277 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5278 // to create 256-bit vectors from two other 128-bit ones.
5279 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5280 DebugLoc dl = Op.getDebugLoc();
5281 EVT ResVT = Op.getValueType();
5283 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5285 SDValue V1 = Op.getOperand(0);
5286 SDValue V2 = Op.getOperand(1);
5287 unsigned NumElems = ResVT.getVectorNumElements();
5289 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5290 DAG.getConstant(0, MVT::i32), DAG, dl);
5291 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5296 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5297 EVT ResVT = Op.getValueType();
5299 assert(Op.getNumOperands() == 2);
5300 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5301 "Unsupported CONCAT_VECTORS for value type");
5303 // We support concatenate two MMX registers and place them in a MMX register.
5304 // This is better than doing a stack convert.
5305 if (ResVT.is128BitVector())
5306 return LowerMMXCONCAT_VECTORS(Op, DAG);
5308 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5309 // from two other 128-bit ones.
5310 return LowerAVXCONCAT_VECTORS(Op, DAG);
5313 // v8i16 shuffles - Prefer shuffles in the following order:
5314 // 1. [all] pshuflw, pshufhw, optional move
5315 // 2. [ssse3] 1 x pshufb
5316 // 3. [ssse3] 2 x pshufb + 1 x por
5317 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5319 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5320 SelectionDAG &DAG) const {
5321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5322 SDValue V1 = SVOp->getOperand(0);
5323 SDValue V2 = SVOp->getOperand(1);
5324 DebugLoc dl = SVOp->getDebugLoc();
5325 SmallVector<int, 8> MaskVals;
5327 // Determine if more than 1 of the words in each of the low and high quadwords
5328 // of the result come from the same quadword of one of the two inputs. Undef
5329 // mask values count as coming from any quadword, for better codegen.
5330 unsigned LoQuad[] = { 0, 0, 0, 0 };
5331 unsigned HiQuad[] = { 0, 0, 0, 0 };
5332 std::bitset<4> InputQuads;
5333 for (unsigned i = 0; i < 8; ++i) {
5334 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5335 int EltIdx = SVOp->getMaskElt(i);
5336 MaskVals.push_back(EltIdx);
5345 InputQuads.set(EltIdx / 4);
5348 int BestLoQuad = -1;
5349 unsigned MaxQuad = 1;
5350 for (unsigned i = 0; i < 4; ++i) {
5351 if (LoQuad[i] > MaxQuad) {
5353 MaxQuad = LoQuad[i];
5357 int BestHiQuad = -1;
5359 for (unsigned i = 0; i < 4; ++i) {
5360 if (HiQuad[i] > MaxQuad) {
5362 MaxQuad = HiQuad[i];
5366 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5367 // of the two input vectors, shuffle them into one input vector so only a
5368 // single pshufb instruction is necessary. If There are more than 2 input
5369 // quads, disable the next transformation since it does not help SSSE3.
5370 bool V1Used = InputQuads[0] || InputQuads[1];
5371 bool V2Used = InputQuads[2] || InputQuads[3];
5372 if (Subtarget->hasSSSE3()) {
5373 if (InputQuads.count() == 2 && V1Used && V2Used) {
5374 BestLoQuad = InputQuads[0] ? 0 : 1;
5375 BestHiQuad = InputQuads[2] ? 2 : 3;
5377 if (InputQuads.count() > 2) {
5383 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5384 // the shuffle mask. If a quad is scored as -1, that means that it contains
5385 // words from all 4 input quadwords.
5387 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5389 BestLoQuad < 0 ? 0 : BestLoQuad,
5390 BestHiQuad < 0 ? 1 : BestHiQuad
5392 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5393 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5394 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5395 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5397 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5398 // source words for the shuffle, to aid later transformations.
5399 bool AllWordsInNewV = true;
5400 bool InOrder[2] = { true, true };
5401 for (unsigned i = 0; i != 8; ++i) {
5402 int idx = MaskVals[i];
5404 InOrder[i/4] = false;
5405 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5407 AllWordsInNewV = false;
5411 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5412 if (AllWordsInNewV) {
5413 for (int i = 0; i != 8; ++i) {
5414 int idx = MaskVals[i];
5417 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5418 if ((idx != i) && idx < 4)
5420 if ((idx != i) && idx > 3)
5429 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5430 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5431 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5432 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5433 unsigned TargetMask = 0;
5434 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5435 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5436 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5437 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5438 getShufflePSHUFLWImmediate(SVOp);
5439 V1 = NewV.getOperand(0);
5440 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5444 // If we have SSSE3, and all words of the result are from 1 input vector,
5445 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5446 // is present, fall back to case 4.
5447 if (Subtarget->hasSSSE3()) {
5448 SmallVector<SDValue,16> pshufbMask;
5450 // If we have elements from both input vectors, set the high bit of the
5451 // shuffle mask element to zero out elements that come from V2 in the V1
5452 // mask, and elements that come from V1 in the V2 mask, so that the two
5453 // results can be OR'd together.
5454 bool TwoInputs = V1Used && V2Used;
5455 for (unsigned i = 0; i != 8; ++i) {
5456 int EltIdx = MaskVals[i] * 2;
5457 if (TwoInputs && (EltIdx >= 16)) {
5458 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5459 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5462 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5463 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5465 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5466 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5467 DAG.getNode(ISD::BUILD_VECTOR, dl,
5468 MVT::v16i8, &pshufbMask[0], 16));
5470 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5472 // Calculate the shuffle mask for the second input, shuffle it, and
5473 // OR it with the first shuffled input.
5475 for (unsigned i = 0; i != 8; ++i) {
5476 int EltIdx = MaskVals[i] * 2;
5478 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5479 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5482 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5483 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5485 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5486 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5487 DAG.getNode(ISD::BUILD_VECTOR, dl,
5488 MVT::v16i8, &pshufbMask[0], 16));
5489 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5490 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5493 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5494 // and update MaskVals with new element order.
5495 std::bitset<8> InOrder;
5496 if (BestLoQuad >= 0) {
5497 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5498 for (int i = 0; i != 4; ++i) {
5499 int idx = MaskVals[i];
5502 } else if ((idx / 4) == BestLoQuad) {
5507 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5510 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5511 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5512 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5514 getShufflePSHUFLWImmediate(SVOp), DAG);
5518 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5519 // and update MaskVals with the new element order.
5520 if (BestHiQuad >= 0) {
5521 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5522 for (unsigned i = 4; i != 8; ++i) {
5523 int idx = MaskVals[i];
5526 } else if ((idx / 4) == BestHiQuad) {
5527 MaskV[i] = (idx & 3) + 4;
5531 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5534 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5535 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5536 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5538 getShufflePSHUFHWImmediate(SVOp), DAG);
5542 // In case BestHi & BestLo were both -1, which means each quadword has a word
5543 // from each of the four input quadwords, calculate the InOrder bitvector now
5544 // before falling through to the insert/extract cleanup.
5545 if (BestLoQuad == -1 && BestHiQuad == -1) {
5547 for (int i = 0; i != 8; ++i)
5548 if (MaskVals[i] < 0 || MaskVals[i] == i)
5552 // The other elements are put in the right place using pextrw and pinsrw.
5553 for (unsigned i = 0; i != 8; ++i) {
5556 int EltIdx = MaskVals[i];
5559 SDValue ExtOp = (EltIdx < 8)
5560 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5561 DAG.getIntPtrConstant(EltIdx))
5562 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5563 DAG.getIntPtrConstant(EltIdx - 8));
5564 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5565 DAG.getIntPtrConstant(i));
5570 // v16i8 shuffles - Prefer shuffles in the following order:
5571 // 1. [ssse3] 1 x pshufb
5572 // 2. [ssse3] 2 x pshufb + 1 x por
5573 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5575 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5577 const X86TargetLowering &TLI) {
5578 SDValue V1 = SVOp->getOperand(0);
5579 SDValue V2 = SVOp->getOperand(1);
5580 DebugLoc dl = SVOp->getDebugLoc();
5581 ArrayRef<int> MaskVals = SVOp->getMask();
5583 // If we have SSSE3, case 1 is generated when all result bytes come from
5584 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5585 // present, fall back to case 3.
5586 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5589 for (unsigned i = 0; i < 16; ++i) {
5590 int EltIdx = MaskVals[i];
5599 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5600 if (TLI.getSubtarget()->hasSSSE3()) {
5601 SmallVector<SDValue,16> pshufbMask;
5603 // If all result elements are from one input vector, then only translate
5604 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5606 // Otherwise, we have elements from both input vectors, and must zero out
5607 // elements that come from V2 in the first mask, and V1 in the second mask
5608 // so that we can OR them together.
5609 bool TwoInputs = !(V1Only || V2Only);
5610 for (unsigned i = 0; i != 16; ++i) {
5611 int EltIdx = MaskVals[i];
5612 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5613 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5616 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5618 // If all the elements are from V2, assign it to V1 and return after
5619 // building the first pshufb.
5622 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5623 DAG.getNode(ISD::BUILD_VECTOR, dl,
5624 MVT::v16i8, &pshufbMask[0], 16));
5628 // Calculate the shuffle mask for the second input, shuffle it, and
5629 // OR it with the first shuffled input.
5631 for (unsigned i = 0; i != 16; ++i) {
5632 int EltIdx = MaskVals[i];
5634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5637 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5639 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5640 DAG.getNode(ISD::BUILD_VECTOR, dl,
5641 MVT::v16i8, &pshufbMask[0], 16));
5642 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5645 // No SSSE3 - Calculate in place words and then fix all out of place words
5646 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5647 // the 16 different words that comprise the two doublequadword input vectors.
5648 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5649 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5650 SDValue NewV = V2Only ? V2 : V1;
5651 for (int i = 0; i != 8; ++i) {
5652 int Elt0 = MaskVals[i*2];
5653 int Elt1 = MaskVals[i*2+1];
5655 // This word of the result is all undef, skip it.
5656 if (Elt0 < 0 && Elt1 < 0)
5659 // This word of the result is already in the correct place, skip it.
5660 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5662 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5665 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5666 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5669 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5670 // using a single extract together, load it and store it.
5671 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5672 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5673 DAG.getIntPtrConstant(Elt1 / 2));
5674 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5675 DAG.getIntPtrConstant(i));
5679 // If Elt1 is defined, extract it from the appropriate source. If the
5680 // source byte is not also odd, shift the extracted word left 8 bits
5681 // otherwise clear the bottom 8 bits if we need to do an or.
5683 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5684 DAG.getIntPtrConstant(Elt1 / 2));
5685 if ((Elt1 & 1) == 0)
5686 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5688 TLI.getShiftAmountTy(InsElt.getValueType())));
5690 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5691 DAG.getConstant(0xFF00, MVT::i16));
5693 // If Elt0 is defined, extract it from the appropriate source. If the
5694 // source byte is not also even, shift the extracted word right 8 bits. If
5695 // Elt1 was also defined, OR the extracted values together before
5696 // inserting them in the result.
5698 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5699 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5700 if ((Elt0 & 1) != 0)
5701 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5703 TLI.getShiftAmountTy(InsElt0.getValueType())));
5705 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5706 DAG.getConstant(0x00FF, MVT::i16));
5707 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5710 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5711 DAG.getIntPtrConstant(i));
5713 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5716 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5717 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5718 /// done when every pair / quad of shuffle mask elements point to elements in
5719 /// the right sequence. e.g.
5720 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5722 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5723 SelectionDAG &DAG, DebugLoc dl) {
5724 EVT VT = SVOp->getValueType(0);
5725 SDValue V1 = SVOp->getOperand(0);
5726 SDValue V2 = SVOp->getOperand(1);
5727 unsigned NumElems = VT.getVectorNumElements();
5728 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5730 switch (VT.getSimpleVT().SimpleTy) {
5731 default: llvm_unreachable("Unexpected!");
5732 case MVT::v4f32: NewVT = MVT::v2f64; break;
5733 case MVT::v4i32: NewVT = MVT::v2i64; break;
5734 case MVT::v8i16: NewVT = MVT::v4i32; break;
5735 case MVT::v16i8: NewVT = MVT::v4i32; break;
5738 int Scale = NumElems / NewWidth;
5739 SmallVector<int, 8> MaskVec;
5740 for (unsigned i = 0; i < NumElems; i += Scale) {
5742 for (int j = 0; j < Scale; ++j) {
5743 int EltIdx = SVOp->getMaskElt(i+j);
5747 StartIdx = EltIdx - (EltIdx % Scale);
5748 if (EltIdx != StartIdx + j)
5752 MaskVec.push_back(-1);
5754 MaskVec.push_back(StartIdx / Scale);
5757 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5758 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5759 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5762 /// getVZextMovL - Return a zero-extending vector move low node.
5764 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5765 SDValue SrcOp, SelectionDAG &DAG,
5766 const X86Subtarget *Subtarget, DebugLoc dl) {
5767 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5768 LoadSDNode *LD = NULL;
5769 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5770 LD = dyn_cast<LoadSDNode>(SrcOp);
5772 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5774 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5775 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5776 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5777 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5778 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5780 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5781 return DAG.getNode(ISD::BITCAST, dl, VT,
5782 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5783 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5791 return DAG.getNode(ISD::BITCAST, dl, VT,
5792 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5793 DAG.getNode(ISD::BITCAST, dl,
5797 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5798 /// which could not be matched by any known target speficic shuffle
5800 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5801 EVT VT = SVOp->getValueType(0);
5803 unsigned NumElems = VT.getVectorNumElements();
5804 unsigned NumLaneElems = NumElems / 2;
5806 int MinRange[2][2] = { { static_cast<int>(NumElems),
5807 static_cast<int>(NumElems) },
5808 { static_cast<int>(NumElems),
5809 static_cast<int>(NumElems) } };
5810 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5812 // Collect used ranges for each source in each lane
5813 for (unsigned l = 0; l < 2; ++l) {
5814 unsigned LaneStart = l*NumLaneElems;
5815 for (unsigned i = 0; i != NumLaneElems; ++i) {
5816 int Idx = SVOp->getMaskElt(i+LaneStart);
5821 if (Idx >= (int)NumElems) {
5826 if (Idx > MaxRange[l][Input])
5827 MaxRange[l][Input] = Idx;
5828 if (Idx < MinRange[l][Input])
5829 MinRange[l][Input] = Idx;
5833 // Make sure each range is 128-bits
5834 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5835 for (unsigned l = 0; l < 2; ++l) {
5836 for (unsigned Input = 0; Input < 2; ++Input) {
5837 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5840 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5841 ExtractIdx[l][Input] = 0;
5842 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5843 MaxRange[l][Input] < (int)NumElems)
5844 ExtractIdx[l][Input] = NumLaneElems;
5850 DebugLoc dl = SVOp->getDebugLoc();
5851 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5852 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5855 for (unsigned l = 0; l < 2; ++l) {
5856 for (unsigned Input = 0; Input < 2; ++Input) {
5857 if (ExtractIdx[l][Input] >= 0)
5858 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5859 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5862 Ops[l][Input] = DAG.getUNDEF(NVT);
5866 // Generate 128-bit shuffles
5867 SmallVector<int, 16> Mask1, Mask2;
5868 for (unsigned i = 0; i != NumLaneElems; ++i) {
5869 int Elt = SVOp->getMaskElt(i);
5870 if (Elt >= (int)NumElems) {
5871 Elt %= NumLaneElems;
5872 Elt += NumLaneElems;
5873 } else if (Elt >= 0) {
5874 Elt %= NumLaneElems;
5876 Mask1.push_back(Elt);
5878 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
5879 int Elt = SVOp->getMaskElt(i);
5880 if (Elt >= (int)NumElems) {
5881 Elt %= NumLaneElems;
5882 Elt += NumLaneElems;
5883 } else if (Elt >= 0) {
5884 Elt %= NumLaneElems;
5886 Mask2.push_back(Elt);
5889 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
5890 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
5892 // Concatenate the result back
5893 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
5894 DAG.getConstant(0, MVT::i32), DAG, dl);
5895 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
5899 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5900 /// 4 elements, and match them with several different shuffle types.
5902 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5903 SDValue V1 = SVOp->getOperand(0);
5904 SDValue V2 = SVOp->getOperand(1);
5905 DebugLoc dl = SVOp->getDebugLoc();
5906 EVT VT = SVOp->getValueType(0);
5908 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5910 std::pair<int, int> Locs[4];
5911 int Mask1[] = { -1, -1, -1, -1 };
5912 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
5916 for (unsigned i = 0; i != 4; ++i) {
5917 int Idx = PermMask[i];
5919 Locs[i] = std::make_pair(-1, -1);
5921 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5923 Locs[i] = std::make_pair(0, NumLo);
5927 Locs[i] = std::make_pair(1, NumHi);
5929 Mask1[2+NumHi] = Idx;
5935 if (NumLo <= 2 && NumHi <= 2) {
5936 // If no more than two elements come from either vector. This can be
5937 // implemented with two shuffles. First shuffle gather the elements.
5938 // The second shuffle, which takes the first shuffle as both of its
5939 // vector operands, put the elements into the right order.
5940 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5942 int Mask2[] = { -1, -1, -1, -1 };
5944 for (unsigned i = 0; i != 4; ++i)
5945 if (Locs[i].first != -1) {
5946 unsigned Idx = (i < 2) ? 0 : 4;
5947 Idx += Locs[i].first * 2 + Locs[i].second;
5951 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5952 } else if (NumLo == 3 || NumHi == 3) {
5953 // Otherwise, we must have three elements from one vector, call it X, and
5954 // one element from the other, call it Y. First, use a shufps to build an
5955 // intermediate vector with the one element from Y and the element from X
5956 // that will be in the same half in the final destination (the indexes don't
5957 // matter). Then, use a shufps to build the final vector, taking the half
5958 // containing the element from Y from the intermediate, and the other half
5961 // Normalize it so the 3 elements come from V1.
5962 CommuteVectorShuffleMask(PermMask, 4);
5966 // Find the element from V2.
5968 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5969 int Val = PermMask[HiIndex];
5976 Mask1[0] = PermMask[HiIndex];
5978 Mask1[2] = PermMask[HiIndex^1];
5980 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5983 Mask1[0] = PermMask[0];
5984 Mask1[1] = PermMask[1];
5985 Mask1[2] = HiIndex & 1 ? 6 : 4;
5986 Mask1[3] = HiIndex & 1 ? 4 : 6;
5987 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5989 Mask1[0] = HiIndex & 1 ? 2 : 0;
5990 Mask1[1] = HiIndex & 1 ? 0 : 2;
5991 Mask1[2] = PermMask[2];
5992 Mask1[3] = PermMask[3];
5997 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6001 // Break it into (shuffle shuffle_hi, shuffle_lo).
6002 int LoMask[] = { -1, -1, -1, -1 };
6003 int HiMask[] = { -1, -1, -1, -1 };
6005 int *MaskPtr = LoMask;
6006 unsigned MaskIdx = 0;
6009 for (unsigned i = 0; i != 4; ++i) {
6016 int Idx = PermMask[i];
6018 Locs[i] = std::make_pair(-1, -1);
6019 } else if (Idx < 4) {
6020 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6021 MaskPtr[LoIdx] = Idx;
6024 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6025 MaskPtr[HiIdx] = Idx;
6030 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6031 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6032 int MaskOps[] = { -1, -1, -1, -1 };
6033 for (unsigned i = 0; i != 4; ++i)
6034 if (Locs[i].first != -1)
6035 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6036 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6039 static bool MayFoldVectorLoad(SDValue V) {
6040 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6041 V = V.getOperand(0);
6042 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6043 V = V.getOperand(0);
6044 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6045 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6046 // BUILD_VECTOR (load), undef
6047 V = V.getOperand(0);
6053 // FIXME: the version above should always be used. Since there's
6054 // a bug where several vector shuffles can't be folded because the
6055 // DAG is not updated during lowering and a node claims to have two
6056 // uses while it only has one, use this version, and let isel match
6057 // another instruction if the load really happens to have more than
6058 // one use. Remove this version after this bug get fixed.
6059 // rdar://8434668, PR8156
6060 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6061 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6062 V = V.getOperand(0);
6063 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6064 V = V.getOperand(0);
6065 if (ISD::isNormalLoad(V.getNode()))
6070 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6071 /// a vector extract, and if both can be later optimized into a single load.
6072 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6073 /// here because otherwise a target specific shuffle node is going to be
6074 /// emitted for this shuffle, and the optimization not done.
6075 /// FIXME: This is probably not the best approach, but fix the problem
6076 /// until the right path is decided.
6078 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6079 const TargetLowering &TLI) {
6080 EVT VT = V.getValueType();
6081 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6083 // Be sure that the vector shuffle is present in a pattern like this:
6084 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6088 SDNode *N = *V.getNode()->use_begin();
6089 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6092 SDValue EltNo = N->getOperand(1);
6093 if (!isa<ConstantSDNode>(EltNo))
6096 // If the bit convert changed the number of elements, it is unsafe
6097 // to examine the mask.
6098 bool HasShuffleIntoBitcast = false;
6099 if (V.getOpcode() == ISD::BITCAST) {
6100 EVT SrcVT = V.getOperand(0).getValueType();
6101 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6103 V = V.getOperand(0);
6104 HasShuffleIntoBitcast = true;
6107 // Select the input vector, guarding against out of range extract vector.
6108 unsigned NumElems = VT.getVectorNumElements();
6109 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6110 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6111 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6113 // If we are accessing the upper part of a YMM register
6114 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6115 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6116 // because the legalization of N did not happen yet.
6117 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6120 // Skip one more bit_convert if necessary
6121 if (V.getOpcode() == ISD::BITCAST) {
6124 V = V.getOperand(0);
6127 if (!ISD::isNormalLoad(V.getNode()))
6130 // Is the original load suitable?
6131 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6133 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6136 if (!HasShuffleIntoBitcast)
6139 // If there's a bitcast before the shuffle, check if the load type and
6140 // alignment is valid.
6141 unsigned Align = LN0->getAlignment();
6143 TLI.getTargetData()->getABITypeAlignment(
6144 VT.getTypeForEVT(*DAG.getContext()));
6146 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6153 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6154 EVT VT = Op.getValueType();
6156 // Canonizalize to v2f64.
6157 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6158 return DAG.getNode(ISD::BITCAST, dl, VT,
6159 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6164 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6166 SDValue V1 = Op.getOperand(0);
6167 SDValue V2 = Op.getOperand(1);
6168 EVT VT = Op.getValueType();
6170 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6172 if (HasSSE2 && VT == MVT::v2f64)
6173 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6175 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6176 return DAG.getNode(ISD::BITCAST, dl, VT,
6177 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6178 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6179 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6183 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6184 SDValue V1 = Op.getOperand(0);
6185 SDValue V2 = Op.getOperand(1);
6186 EVT VT = Op.getValueType();
6188 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6189 "unsupported shuffle type");
6191 if (V2.getOpcode() == ISD::UNDEF)
6195 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6199 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6200 SDValue V1 = Op.getOperand(0);
6201 SDValue V2 = Op.getOperand(1);
6202 EVT VT = Op.getValueType();
6203 unsigned NumElems = VT.getVectorNumElements();
6205 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6206 // operand of these instructions is only memory, so check if there's a
6207 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6209 bool CanFoldLoad = false;
6211 // Trivial case, when V2 comes from a load.
6212 if (MayFoldVectorLoad(V2))
6215 // When V1 is a load, it can be folded later into a store in isel, example:
6216 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6218 // (MOVLPSmr addr:$src1, VR128:$src2)
6219 // So, recognize this potential and also use MOVLPS or MOVLPD
6220 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6223 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6225 if (HasSSE2 && NumElems == 2)
6226 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6229 // If we don't care about the second element, procede to use movss.
6230 if (SVOp->getMaskElt(1) != -1)
6231 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6234 // movl and movlp will both match v2i64, but v2i64 is never matched by
6235 // movl earlier because we make it strict to avoid messing with the movlp load
6236 // folding logic (see the code above getMOVLP call). Match it here then,
6237 // this is horrible, but will stay like this until we move all shuffle
6238 // matching to x86 specific nodes. Note that for the 1st condition all
6239 // types are matched with movsd.
6241 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6242 // as to remove this logic from here, as much as possible
6243 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6244 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6245 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6248 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6250 // Invert the operand order and use SHUFPS to match it.
6251 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6252 getShuffleSHUFImmediate(SVOp), DAG);
6256 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6257 const TargetLowering &TLI,
6258 const X86Subtarget *Subtarget) {
6259 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6260 EVT VT = Op.getValueType();
6261 DebugLoc dl = Op.getDebugLoc();
6262 SDValue V1 = Op.getOperand(0);
6263 SDValue V2 = Op.getOperand(1);
6265 if (isZeroShuffle(SVOp))
6266 return getZeroVector(VT, Subtarget, DAG, dl);
6268 // Handle splat operations
6269 if (SVOp->isSplat()) {
6270 unsigned NumElem = VT.getVectorNumElements();
6271 int Size = VT.getSizeInBits();
6272 // Special case, this is the only place now where it's allowed to return
6273 // a vector_shuffle operation without using a target specific node, because
6274 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6275 // this be moved to DAGCombine instead?
6276 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6279 // Use vbroadcast whenever the splat comes from a foldable load
6280 SDValue LD = isVectorBroadcast(Op, Subtarget);
6282 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6284 // Handle splats by matching through known shuffle masks
6285 if ((Size == 128 && NumElem <= 4) ||
6286 (Size == 256 && NumElem < 8))
6289 // All remaning splats are promoted to target supported vector shuffles.
6290 return PromoteSplat(SVOp, DAG);
6293 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6295 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6296 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6297 if (NewOp.getNode())
6298 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6299 } else if ((VT == MVT::v4i32 ||
6300 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6301 // FIXME: Figure out a cleaner way to do this.
6302 // Try to make use of movq to zero out the top part.
6303 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6304 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6305 if (NewOp.getNode()) {
6306 EVT NewVT = NewOp.getValueType();
6307 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6308 NewVT, true, false))
6309 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6310 DAG, Subtarget, dl);
6312 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6313 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6314 if (NewOp.getNode()) {
6315 EVT NewVT = NewOp.getValueType();
6316 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6317 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6318 DAG, Subtarget, dl);
6326 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6327 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6328 SDValue V1 = Op.getOperand(0);
6329 SDValue V2 = Op.getOperand(1);
6330 EVT VT = Op.getValueType();
6331 DebugLoc dl = Op.getDebugLoc();
6332 unsigned NumElems = VT.getVectorNumElements();
6333 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6334 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6335 bool V1IsSplat = false;
6336 bool V2IsSplat = false;
6337 bool HasSSE2 = Subtarget->hasSSE2();
6338 bool HasAVX = Subtarget->hasAVX();
6339 bool HasAVX2 = Subtarget->hasAVX2();
6340 MachineFunction &MF = DAG.getMachineFunction();
6341 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6343 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6345 if (V1IsUndef && V2IsUndef)
6346 return DAG.getUNDEF(VT);
6348 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6350 // Vector shuffle lowering takes 3 steps:
6352 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6353 // narrowing and commutation of operands should be handled.
6354 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6356 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6357 // so the shuffle can be broken into other shuffles and the legalizer can
6358 // try the lowering again.
6360 // The general idea is that no vector_shuffle operation should be left to
6361 // be matched during isel, all of them must be converted to a target specific
6364 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6365 // narrowing and commutation of operands should be handled. The actual code
6366 // doesn't include all of those, work in progress...
6367 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6368 if (NewOp.getNode())
6371 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6373 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6374 // unpckh_undef). Only use pshufd if speed is more important than size.
6375 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6376 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6377 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6378 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6380 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6381 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6382 return getMOVDDup(Op, dl, V1, DAG);
6384 if (isMOVHLPS_v_undef_Mask(M, VT))
6385 return getMOVHighToLow(Op, dl, DAG);
6387 // Use to match splats
6388 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6389 (VT == MVT::v2f64 || VT == MVT::v2i64))
6390 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6392 if (isPSHUFDMask(M, VT)) {
6393 // The actual implementation will match the mask in the if above and then
6394 // during isel it can match several different instructions, not only pshufd
6395 // as its name says, sad but true, emulate the behavior for now...
6396 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6397 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6399 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6401 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6402 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6404 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6405 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6407 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6411 // Check if this can be converted into a logical shift.
6412 bool isLeft = false;
6415 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6416 if (isShift && ShVal.hasOneUse()) {
6417 // If the shifted value has multiple uses, it may be cheaper to use
6418 // v_set0 + movlhps or movhlps, etc.
6419 EVT EltVT = VT.getVectorElementType();
6420 ShAmt *= EltVT.getSizeInBits();
6421 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6424 if (isMOVLMask(M, VT)) {
6425 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6426 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6427 if (!isMOVLPMask(M, VT)) {
6428 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6429 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6431 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6432 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6436 // FIXME: fold these into legal mask.
6437 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6438 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6440 if (isMOVHLPSMask(M, VT))
6441 return getMOVHighToLow(Op, dl, DAG);
6443 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6444 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6446 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6447 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6449 if (isMOVLPMask(M, VT))
6450 return getMOVLP(Op, dl, DAG, HasSSE2);
6452 if (ShouldXformToMOVHLPS(M, VT) ||
6453 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6454 return CommuteVectorShuffle(SVOp, DAG);
6457 // No better options. Use a vshldq / vsrldq.
6458 EVT EltVT = VT.getVectorElementType();
6459 ShAmt *= EltVT.getSizeInBits();
6460 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6463 bool Commuted = false;
6464 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6465 // 1,1,1,1 -> v8i16 though.
6466 V1IsSplat = isSplatVector(V1.getNode());
6467 V2IsSplat = isSplatVector(V2.getNode());
6469 // Canonicalize the splat or undef, if present, to be on the RHS.
6470 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6471 CommuteVectorShuffleMask(M, NumElems);
6473 std::swap(V1IsSplat, V2IsSplat);
6477 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6478 // Shuffling low element of v1 into undef, just return v1.
6481 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6482 // the instruction selector will not match, so get a canonical MOVL with
6483 // swapped operands to undo the commute.
6484 return getMOVL(DAG, dl, VT, V2, V1);
6487 if (isUNPCKLMask(M, VT, HasAVX2))
6488 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6490 if (isUNPCKHMask(M, VT, HasAVX2))
6491 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6494 // Normalize mask so all entries that point to V2 points to its first
6495 // element then try to match unpck{h|l} again. If match, return a
6496 // new vector_shuffle with the corrected mask.p
6497 SmallVector<int, 8> NewMask(M.begin(), M.end());
6498 NormalizeMask(NewMask, NumElems);
6499 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6500 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6501 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6502 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6507 // Commute is back and try unpck* again.
6508 // FIXME: this seems wrong.
6509 CommuteVectorShuffleMask(M, NumElems);
6511 std::swap(V1IsSplat, V2IsSplat);
6514 if (isUNPCKLMask(M, VT, HasAVX2))
6515 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6517 if (isUNPCKHMask(M, VT, HasAVX2))
6518 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6521 // Normalize the node to match x86 shuffle ops if needed
6522 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6523 return CommuteVectorShuffle(SVOp, DAG);
6525 // The checks below are all present in isShuffleMaskLegal, but they are
6526 // inlined here right now to enable us to directly emit target specific
6527 // nodes, and remove one by one until they don't return Op anymore.
6529 if (isPALIGNRMask(M, VT, Subtarget))
6530 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6531 getShufflePALIGNRImmediate(SVOp),
6534 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6535 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6536 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6537 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6540 if (isPSHUFHWMask(M, VT))
6541 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6542 getShufflePSHUFHWImmediate(SVOp),
6545 if (isPSHUFLWMask(M, VT))
6546 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6547 getShufflePSHUFLWImmediate(SVOp),
6550 if (isSHUFPMask(M, VT, HasAVX))
6551 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6552 getShuffleSHUFImmediate(SVOp), DAG);
6554 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6555 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6556 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6557 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6559 //===--------------------------------------------------------------------===//
6560 // Generate target specific nodes for 128 or 256-bit shuffles only
6561 // supported in the AVX instruction set.
6564 // Handle VMOVDDUPY permutations
6565 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6566 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6568 // Handle VPERMILPS/D* permutations
6569 if (isVPERMILPMask(M, VT, HasAVX)) {
6570 if (HasAVX2 && VT == MVT::v8i32)
6571 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6572 getShuffleSHUFImmediate(SVOp), DAG);
6573 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6574 getShuffleSHUFImmediate(SVOp), DAG);
6577 // Handle VPERM2F128/VPERM2I128 permutations
6578 if (isVPERM2X128Mask(M, VT, HasAVX))
6579 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6580 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6582 //===--------------------------------------------------------------------===//
6583 // Since no target specific shuffle was selected for this generic one,
6584 // lower it into other known shuffles. FIXME: this isn't true yet, but
6585 // this is the plan.
6588 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6589 if (VT == MVT::v8i16) {
6590 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6591 if (NewOp.getNode())
6595 if (VT == MVT::v16i8) {
6596 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6597 if (NewOp.getNode())
6601 // Handle all 128-bit wide vectors with 4 elements, and match them with
6602 // several different shuffle types.
6603 if (NumElems == 4 && VT.getSizeInBits() == 128)
6604 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6606 // Handle general 256-bit shuffles
6607 if (VT.is256BitVector())
6608 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6614 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6615 SelectionDAG &DAG) const {
6616 EVT VT = Op.getValueType();
6617 DebugLoc dl = Op.getDebugLoc();
6619 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6622 if (VT.getSizeInBits() == 8) {
6623 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6624 Op.getOperand(0), Op.getOperand(1));
6625 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6626 DAG.getValueType(VT));
6627 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6628 } else if (VT.getSizeInBits() == 16) {
6629 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6630 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6632 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6633 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6634 DAG.getNode(ISD::BITCAST, dl,
6638 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6639 Op.getOperand(0), Op.getOperand(1));
6640 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6641 DAG.getValueType(VT));
6642 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6643 } else if (VT == MVT::f32) {
6644 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6645 // the result back to FR32 register. It's only worth matching if the
6646 // result has a single use which is a store or a bitcast to i32. And in
6647 // the case of a store, it's not worth it if the index is a constant 0,
6648 // because a MOVSSmr can be used instead, which is smaller and faster.
6649 if (!Op.hasOneUse())
6651 SDNode *User = *Op.getNode()->use_begin();
6652 if ((User->getOpcode() != ISD::STORE ||
6653 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6654 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6655 (User->getOpcode() != ISD::BITCAST ||
6656 User->getValueType(0) != MVT::i32))
6658 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6659 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6662 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6663 } else if (VT == MVT::i32 || VT == MVT::i64) {
6664 // ExtractPS/pextrq works with constant index.
6665 if (isa<ConstantSDNode>(Op.getOperand(1)))
6673 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6674 SelectionDAG &DAG) const {
6675 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6678 SDValue Vec = Op.getOperand(0);
6679 EVT VecVT = Vec.getValueType();
6681 // If this is a 256-bit vector result, first extract the 128-bit vector and
6682 // then extract the element from the 128-bit vector.
6683 if (VecVT.getSizeInBits() == 256) {
6684 DebugLoc dl = Op.getNode()->getDebugLoc();
6685 unsigned NumElems = VecVT.getVectorNumElements();
6686 SDValue Idx = Op.getOperand(1);
6687 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6689 // Get the 128-bit vector.
6690 bool Upper = IdxVal >= NumElems/2;
6691 Vec = Extract128BitVector(Vec,
6692 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6694 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6695 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6698 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6700 if (Subtarget->hasSSE41()) {
6701 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6706 EVT VT = Op.getValueType();
6707 DebugLoc dl = Op.getDebugLoc();
6708 // TODO: handle v16i8.
6709 if (VT.getSizeInBits() == 16) {
6710 SDValue Vec = Op.getOperand(0);
6711 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6713 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6714 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6715 DAG.getNode(ISD::BITCAST, dl,
6718 // Transform it so it match pextrw which produces a 32-bit result.
6719 EVT EltVT = MVT::i32;
6720 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6721 Op.getOperand(0), Op.getOperand(1));
6722 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6723 DAG.getValueType(VT));
6724 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6725 } else if (VT.getSizeInBits() == 32) {
6726 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6730 // SHUFPS the element to the lowest double word, then movss.
6731 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6732 EVT VVT = Op.getOperand(0).getValueType();
6733 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6734 DAG.getUNDEF(VVT), Mask);
6735 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6736 DAG.getIntPtrConstant(0));
6737 } else if (VT.getSizeInBits() == 64) {
6738 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6739 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6740 // to match extract_elt for f64.
6741 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6745 // UNPCKHPD the element to the lowest double word, then movsd.
6746 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6747 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6748 int Mask[2] = { 1, -1 };
6749 EVT VVT = Op.getOperand(0).getValueType();
6750 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6751 DAG.getUNDEF(VVT), Mask);
6752 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6753 DAG.getIntPtrConstant(0));
6760 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6761 SelectionDAG &DAG) const {
6762 EVT VT = Op.getValueType();
6763 EVT EltVT = VT.getVectorElementType();
6764 DebugLoc dl = Op.getDebugLoc();
6766 SDValue N0 = Op.getOperand(0);
6767 SDValue N1 = Op.getOperand(1);
6768 SDValue N2 = Op.getOperand(2);
6770 if (VT.getSizeInBits() == 256)
6773 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6774 isa<ConstantSDNode>(N2)) {
6776 if (VT == MVT::v8i16)
6777 Opc = X86ISD::PINSRW;
6778 else if (VT == MVT::v16i8)
6779 Opc = X86ISD::PINSRB;
6781 Opc = X86ISD::PINSRB;
6783 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6785 if (N1.getValueType() != MVT::i32)
6786 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6787 if (N2.getValueType() != MVT::i32)
6788 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6789 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6790 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6791 // Bits [7:6] of the constant are the source select. This will always be
6792 // zero here. The DAG Combiner may combine an extract_elt index into these
6793 // bits. For example (insert (extract, 3), 2) could be matched by putting
6794 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6795 // Bits [5:4] of the constant are the destination select. This is the
6796 // value of the incoming immediate.
6797 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6798 // combine either bitwise AND or insert of float 0.0 to set these bits.
6799 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6800 // Create this as a scalar to vector..
6801 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6802 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6803 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6804 isa<ConstantSDNode>(N2)) {
6805 // PINSR* works with constant index.
6812 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6813 EVT VT = Op.getValueType();
6814 EVT EltVT = VT.getVectorElementType();
6816 DebugLoc dl = Op.getDebugLoc();
6817 SDValue N0 = Op.getOperand(0);
6818 SDValue N1 = Op.getOperand(1);
6819 SDValue N2 = Op.getOperand(2);
6821 // If this is a 256-bit vector result, first extract the 128-bit vector,
6822 // insert the element into the extracted half and then place it back.
6823 if (VT.getSizeInBits() == 256) {
6824 if (!isa<ConstantSDNode>(N2))
6827 // Get the desired 128-bit vector half.
6828 unsigned NumElems = VT.getVectorNumElements();
6829 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6830 bool Upper = IdxVal >= NumElems/2;
6831 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6832 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6834 // Insert the element into the desired half.
6835 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6836 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6838 // Insert the changed part back to the 256-bit vector
6839 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6842 if (Subtarget->hasSSE41())
6843 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6845 if (EltVT == MVT::i8)
6848 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6849 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6850 // as its second argument.
6851 if (N1.getValueType() != MVT::i32)
6852 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6853 if (N2.getValueType() != MVT::i32)
6854 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6855 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6861 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6862 LLVMContext *Context = DAG.getContext();
6863 DebugLoc dl = Op.getDebugLoc();
6864 EVT OpVT = Op.getValueType();
6866 // If this is a 256-bit vector result, first insert into a 128-bit
6867 // vector and then insert into the 256-bit vector.
6868 if (OpVT.getSizeInBits() > 128) {
6869 // Insert into a 128-bit vector.
6870 EVT VT128 = EVT::getVectorVT(*Context,
6871 OpVT.getVectorElementType(),
6872 OpVT.getVectorNumElements() / 2);
6874 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6876 // Insert the 128-bit vector.
6877 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6878 DAG.getConstant(0, MVT::i32),
6882 if (Op.getValueType() == MVT::v1i64 &&
6883 Op.getOperand(0).getValueType() == MVT::i64)
6884 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6886 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6887 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6888 "Expected an SSE type!");
6889 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6890 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6893 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6894 // a simple subregister reference or explicit instructions to grab
6895 // upper bits of a vector.
6897 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6898 if (Subtarget->hasAVX()) {
6899 DebugLoc dl = Op.getNode()->getDebugLoc();
6900 SDValue Vec = Op.getNode()->getOperand(0);
6901 SDValue Idx = Op.getNode()->getOperand(1);
6903 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6904 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6905 return Extract128BitVector(Vec, Idx, DAG, dl);
6911 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6912 // simple superregister reference or explicit instructions to insert
6913 // the upper bits of a vector.
6915 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6916 if (Subtarget->hasAVX()) {
6917 DebugLoc dl = Op.getNode()->getDebugLoc();
6918 SDValue Vec = Op.getNode()->getOperand(0);
6919 SDValue SubVec = Op.getNode()->getOperand(1);
6920 SDValue Idx = Op.getNode()->getOperand(2);
6922 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6923 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6924 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6930 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6931 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6932 // one of the above mentioned nodes. It has to be wrapped because otherwise
6933 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6934 // be used to form addressing mode. These wrapped nodes will be selected
6937 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6938 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6940 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6942 unsigned char OpFlag = 0;
6943 unsigned WrapperKind = X86ISD::Wrapper;
6944 CodeModel::Model M = getTargetMachine().getCodeModel();
6946 if (Subtarget->isPICStyleRIPRel() &&
6947 (M == CodeModel::Small || M == CodeModel::Kernel))
6948 WrapperKind = X86ISD::WrapperRIP;
6949 else if (Subtarget->isPICStyleGOT())
6950 OpFlag = X86II::MO_GOTOFF;
6951 else if (Subtarget->isPICStyleStubPIC())
6952 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6954 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6956 CP->getOffset(), OpFlag);
6957 DebugLoc DL = CP->getDebugLoc();
6958 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6959 // With PIC, the address is actually $g + Offset.
6961 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6962 DAG.getNode(X86ISD::GlobalBaseReg,
6963 DebugLoc(), getPointerTy()),
6970 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6971 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6973 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6975 unsigned char OpFlag = 0;
6976 unsigned WrapperKind = X86ISD::Wrapper;
6977 CodeModel::Model M = getTargetMachine().getCodeModel();
6979 if (Subtarget->isPICStyleRIPRel() &&
6980 (M == CodeModel::Small || M == CodeModel::Kernel))
6981 WrapperKind = X86ISD::WrapperRIP;
6982 else if (Subtarget->isPICStyleGOT())
6983 OpFlag = X86II::MO_GOTOFF;
6984 else if (Subtarget->isPICStyleStubPIC())
6985 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6987 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6989 DebugLoc DL = JT->getDebugLoc();
6990 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6992 // With PIC, the address is actually $g + Offset.
6994 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6995 DAG.getNode(X86ISD::GlobalBaseReg,
6996 DebugLoc(), getPointerTy()),
7003 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7004 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7006 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7008 unsigned char OpFlag = 0;
7009 unsigned WrapperKind = X86ISD::Wrapper;
7010 CodeModel::Model M = getTargetMachine().getCodeModel();
7012 if (Subtarget->isPICStyleRIPRel() &&
7013 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7014 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7015 OpFlag = X86II::MO_GOTPCREL;
7016 WrapperKind = X86ISD::WrapperRIP;
7017 } else if (Subtarget->isPICStyleGOT()) {
7018 OpFlag = X86II::MO_GOT;
7019 } else if (Subtarget->isPICStyleStubPIC()) {
7020 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7021 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7022 OpFlag = X86II::MO_DARWIN_NONLAZY;
7025 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7027 DebugLoc DL = Op.getDebugLoc();
7028 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7031 // With PIC, the address is actually $g + Offset.
7032 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7033 !Subtarget->is64Bit()) {
7034 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7035 DAG.getNode(X86ISD::GlobalBaseReg,
7036 DebugLoc(), getPointerTy()),
7040 // For symbols that require a load from a stub to get the address, emit the
7042 if (isGlobalStubReference(OpFlag))
7043 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7044 MachinePointerInfo::getGOT(), false, false, false, 0);
7050 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7051 // Create the TargetBlockAddressAddress node.
7052 unsigned char OpFlags =
7053 Subtarget->ClassifyBlockAddressReference();
7054 CodeModel::Model M = getTargetMachine().getCodeModel();
7055 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7056 DebugLoc dl = Op.getDebugLoc();
7057 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7058 /*isTarget=*/true, OpFlags);
7060 if (Subtarget->isPICStyleRIPRel() &&
7061 (M == CodeModel::Small || M == CodeModel::Kernel))
7062 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7064 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7066 // With PIC, the address is actually $g + Offset.
7067 if (isGlobalRelativeToPICBase(OpFlags)) {
7068 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7069 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7077 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7079 SelectionDAG &DAG) const {
7080 // Create the TargetGlobalAddress node, folding in the constant
7081 // offset if it is legal.
7082 unsigned char OpFlags =
7083 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7084 CodeModel::Model M = getTargetMachine().getCodeModel();
7086 if (OpFlags == X86II::MO_NO_FLAG &&
7087 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7088 // A direct static reference to a global.
7089 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7092 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7095 if (Subtarget->isPICStyleRIPRel() &&
7096 (M == CodeModel::Small || M == CodeModel::Kernel))
7097 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7099 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7101 // With PIC, the address is actually $g + Offset.
7102 if (isGlobalRelativeToPICBase(OpFlags)) {
7103 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7104 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7108 // For globals that require a load from a stub to get the address, emit the
7110 if (isGlobalStubReference(OpFlags))
7111 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7112 MachinePointerInfo::getGOT(), false, false, false, 0);
7114 // If there was a non-zero offset that we didn't fold, create an explicit
7117 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7118 DAG.getConstant(Offset, getPointerTy()));
7124 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7125 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7126 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7127 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7131 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7132 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7133 unsigned char OperandFlags) {
7134 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7135 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7136 DebugLoc dl = GA->getDebugLoc();
7137 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7138 GA->getValueType(0),
7142 SDValue Ops[] = { Chain, TGA, *InFlag };
7143 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7145 SDValue Ops[] = { Chain, TGA };
7146 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7149 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7150 MFI->setAdjustsStack(true);
7152 SDValue Flag = Chain.getValue(1);
7153 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7156 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7158 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7161 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7162 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7163 DAG.getNode(X86ISD::GlobalBaseReg,
7164 DebugLoc(), PtrVT), InFlag);
7165 InFlag = Chain.getValue(1);
7167 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7170 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7172 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7174 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7175 X86::RAX, X86II::MO_TLSGD);
7178 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7179 // "local exec" model.
7180 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7181 const EVT PtrVT, TLSModel::Model model,
7183 DebugLoc dl = GA->getDebugLoc();
7185 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7186 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7187 is64Bit ? 257 : 256));
7189 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7190 DAG.getIntPtrConstant(0),
7191 MachinePointerInfo(Ptr),
7192 false, false, false, 0);
7194 unsigned char OperandFlags = 0;
7195 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7197 unsigned WrapperKind = X86ISD::Wrapper;
7198 if (model == TLSModel::LocalExec) {
7199 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7200 } else if (is64Bit) {
7201 assert(model == TLSModel::InitialExec);
7202 OperandFlags = X86II::MO_GOTTPOFF;
7203 WrapperKind = X86ISD::WrapperRIP;
7205 assert(model == TLSModel::InitialExec);
7206 OperandFlags = X86II::MO_INDNTPOFF;
7209 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7211 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7212 GA->getValueType(0),
7213 GA->getOffset(), OperandFlags);
7214 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7216 if (model == TLSModel::InitialExec)
7217 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7218 MachinePointerInfo::getGOT(), false, false, false, 0);
7220 // The address of the thread local variable is the add of the thread
7221 // pointer with the offset of the variable.
7222 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7226 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7228 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7229 const GlobalValue *GV = GA->getGlobal();
7231 if (Subtarget->isTargetELF()) {
7232 // TODO: implement the "local dynamic" model
7233 // TODO: implement the "initial exec"model for pic executables
7235 // If GV is an alias then use the aliasee for determining
7236 // thread-localness.
7237 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7238 GV = GA->resolveAliasedGlobal(false);
7240 TLSModel::Model model
7241 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7244 case TLSModel::GeneralDynamic:
7245 case TLSModel::LocalDynamic: // not implemented
7246 if (Subtarget->is64Bit())
7247 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7248 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7250 case TLSModel::InitialExec:
7251 case TLSModel::LocalExec:
7252 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7253 Subtarget->is64Bit());
7255 } else if (Subtarget->isTargetDarwin()) {
7256 // Darwin only has one model of TLS. Lower to that.
7257 unsigned char OpFlag = 0;
7258 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7259 X86ISD::WrapperRIP : X86ISD::Wrapper;
7261 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7263 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7264 !Subtarget->is64Bit();
7266 OpFlag = X86II::MO_TLVP_PIC_BASE;
7268 OpFlag = X86II::MO_TLVP;
7269 DebugLoc DL = Op.getDebugLoc();
7270 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7271 GA->getValueType(0),
7272 GA->getOffset(), OpFlag);
7273 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7275 // With PIC32, the address is actually $g + Offset.
7277 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7278 DAG.getNode(X86ISD::GlobalBaseReg,
7279 DebugLoc(), getPointerTy()),
7282 // Lowering the machine isd will make sure everything is in the right
7284 SDValue Chain = DAG.getEntryNode();
7285 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7286 SDValue Args[] = { Chain, Offset };
7287 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7289 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7290 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7291 MFI->setAdjustsStack(true);
7293 // And our return value (tls address) is in the standard call return value
7295 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7296 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7298 } else if (Subtarget->isTargetWindows()) {
7299 // Just use the implicit TLS architecture
7300 // Need to generate someting similar to:
7301 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7303 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7304 // mov rcx, qword [rdx+rcx*8]
7305 // mov eax, .tls$:tlsvar
7306 // [rax+rcx] contains the address
7307 // Windows 64bit: gs:0x58
7308 // Windows 32bit: fs:__tls_array
7310 // If GV is an alias then use the aliasee for determining
7311 // thread-localness.
7312 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7313 GV = GA->resolveAliasedGlobal(false);
7314 DebugLoc dl = GA->getDebugLoc();
7315 SDValue Chain = DAG.getEntryNode();
7317 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7318 // %gs:0x58 (64-bit).
7319 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7320 ? Type::getInt8PtrTy(*DAG.getContext(),
7322 : Type::getInt32PtrTy(*DAG.getContext(),
7325 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7326 Subtarget->is64Bit()
7327 ? DAG.getIntPtrConstant(0x58)
7328 : DAG.getExternalSymbol("_tls_array",
7330 MachinePointerInfo(Ptr),
7331 false, false, false, 0);
7333 // Load the _tls_index variable
7334 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7335 if (Subtarget->is64Bit())
7336 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7337 IDX, MachinePointerInfo(), MVT::i32,
7340 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7341 false, false, false, 0);
7343 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7345 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7347 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7348 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7349 false, false, false, 0);
7351 // Get the offset of start of .tls section
7352 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7353 GA->getValueType(0),
7354 GA->getOffset(), X86II::MO_SECREL);
7355 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7357 // The address of the thread local variable is the add of the thread
7358 // pointer with the offset of the variable.
7359 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7362 llvm_unreachable("TLS not implemented for this target.");
7366 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7367 /// and take a 2 x i32 value to shift plus a shift amount.
7368 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7369 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7370 EVT VT = Op.getValueType();
7371 unsigned VTBits = VT.getSizeInBits();
7372 DebugLoc dl = Op.getDebugLoc();
7373 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7374 SDValue ShOpLo = Op.getOperand(0);
7375 SDValue ShOpHi = Op.getOperand(1);
7376 SDValue ShAmt = Op.getOperand(2);
7377 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7378 DAG.getConstant(VTBits - 1, MVT::i8))
7379 : DAG.getConstant(0, VT);
7382 if (Op.getOpcode() == ISD::SHL_PARTS) {
7383 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7384 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7386 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7387 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7390 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7391 DAG.getConstant(VTBits, MVT::i8));
7392 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7393 AndNode, DAG.getConstant(0, MVT::i8));
7396 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7397 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7398 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7400 if (Op.getOpcode() == ISD::SHL_PARTS) {
7401 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7402 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7404 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7405 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7408 SDValue Ops[2] = { Lo, Hi };
7409 return DAG.getMergeValues(Ops, 2, dl);
7412 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7413 SelectionDAG &DAG) const {
7414 EVT SrcVT = Op.getOperand(0).getValueType();
7416 if (SrcVT.isVector())
7419 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7420 "Unknown SINT_TO_FP to lower!");
7422 // These are really Legal; return the operand so the caller accepts it as
7424 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7426 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7427 Subtarget->is64Bit()) {
7431 DebugLoc dl = Op.getDebugLoc();
7432 unsigned Size = SrcVT.getSizeInBits()/8;
7433 MachineFunction &MF = DAG.getMachineFunction();
7434 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7435 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7436 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7438 MachinePointerInfo::getFixedStack(SSFI),
7440 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7443 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7445 SelectionDAG &DAG) const {
7447 DebugLoc DL = Op.getDebugLoc();
7449 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7451 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7453 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7455 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7457 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7458 MachineMemOperand *MMO;
7460 int SSFI = FI->getIndex();
7462 DAG.getMachineFunction()
7463 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7464 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7466 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7467 StackSlot = StackSlot.getOperand(1);
7469 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7470 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7472 Tys, Ops, array_lengthof(Ops),
7476 Chain = Result.getValue(1);
7477 SDValue InFlag = Result.getValue(2);
7479 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7480 // shouldn't be necessary except that RFP cannot be live across
7481 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7482 MachineFunction &MF = DAG.getMachineFunction();
7483 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7484 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7485 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7486 Tys = DAG.getVTList(MVT::Other);
7488 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7490 MachineMemOperand *MMO =
7491 DAG.getMachineFunction()
7492 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7493 MachineMemOperand::MOStore, SSFISize, SSFISize);
7495 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7496 Ops, array_lengthof(Ops),
7497 Op.getValueType(), MMO);
7498 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7499 MachinePointerInfo::getFixedStack(SSFI),
7500 false, false, false, 0);
7506 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7507 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7508 SelectionDAG &DAG) const {
7509 // This algorithm is not obvious. Here it is what we're trying to output:
7512 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7513 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7517 pshufd $0x4e, %xmm0, %xmm1
7522 DebugLoc dl = Op.getDebugLoc();
7523 LLVMContext *Context = DAG.getContext();
7525 // Build some magic constants.
7526 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7527 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7528 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7530 SmallVector<Constant*,2> CV1;
7532 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7534 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7535 Constant *C1 = ConstantVector::get(CV1);
7536 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7538 // Load the 64-bit value into an XMM register.
7539 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7541 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7542 MachinePointerInfo::getConstantPool(),
7543 false, false, false, 16);
7544 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7545 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7548 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7549 MachinePointerInfo::getConstantPool(),
7550 false, false, false, 16);
7551 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7552 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7555 if (Subtarget->hasSSE3()) {
7556 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7557 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7559 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7560 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7562 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7563 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7567 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7568 DAG.getIntPtrConstant(0));
7571 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7572 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7573 SelectionDAG &DAG) const {
7574 DebugLoc dl = Op.getDebugLoc();
7575 // FP constant to bias correct the final result.
7576 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7579 // Load the 32-bit value into an XMM register.
7580 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7583 // Zero out the upper parts of the register.
7584 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7586 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7587 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7588 DAG.getIntPtrConstant(0));
7590 // Or the load with the bias.
7591 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7592 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7593 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7595 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7596 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7597 MVT::v2f64, Bias)));
7598 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7599 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7600 DAG.getIntPtrConstant(0));
7602 // Subtract the bias.
7603 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7605 // Handle final rounding.
7606 EVT DestVT = Op.getValueType();
7608 if (DestVT.bitsLT(MVT::f64)) {
7609 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7610 DAG.getIntPtrConstant(0));
7611 } else if (DestVT.bitsGT(MVT::f64)) {
7612 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7615 // Handle final rounding.
7619 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7620 SelectionDAG &DAG) const {
7621 SDValue N0 = Op.getOperand(0);
7622 DebugLoc dl = Op.getDebugLoc();
7624 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7625 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7626 // the optimization here.
7627 if (DAG.SignBitIsZero(N0))
7628 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7630 EVT SrcVT = N0.getValueType();
7631 EVT DstVT = Op.getValueType();
7632 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7633 return LowerUINT_TO_FP_i64(Op, DAG);
7634 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7635 return LowerUINT_TO_FP_i32(Op, DAG);
7636 else if (Subtarget->is64Bit() &&
7637 SrcVT == MVT::i64 && DstVT == MVT::f32)
7640 // Make a 64-bit buffer, and use it to build an FILD.
7641 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7642 if (SrcVT == MVT::i32) {
7643 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7644 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7645 getPointerTy(), StackSlot, WordOff);
7646 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7647 StackSlot, MachinePointerInfo(),
7649 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7650 OffsetSlot, MachinePointerInfo(),
7652 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7656 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7657 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7658 StackSlot, MachinePointerInfo(),
7660 // For i64 source, we need to add the appropriate power of 2 if the input
7661 // was negative. This is the same as the optimization in
7662 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7663 // we must be careful to do the computation in x87 extended precision, not
7664 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7665 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7666 MachineMemOperand *MMO =
7667 DAG.getMachineFunction()
7668 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7669 MachineMemOperand::MOLoad, 8, 8);
7671 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7672 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7673 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7676 APInt FF(32, 0x5F800000ULL);
7678 // Check whether the sign bit is set.
7679 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7680 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7683 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7684 SDValue FudgePtr = DAG.getConstantPool(
7685 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7688 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7689 SDValue Zero = DAG.getIntPtrConstant(0);
7690 SDValue Four = DAG.getIntPtrConstant(4);
7691 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7693 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7695 // Load the value out, extending it from f32 to f80.
7696 // FIXME: Avoid the extend by constructing the right constant pool?
7697 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7698 FudgePtr, MachinePointerInfo::getConstantPool(),
7699 MVT::f32, false, false, 4);
7700 // Extend everything to 80 bits to force it to be done on x87.
7701 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7702 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7705 std::pair<SDValue,SDValue> X86TargetLowering::
7706 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7707 DebugLoc DL = Op.getDebugLoc();
7709 EVT DstTy = Op.getValueType();
7712 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7716 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7717 DstTy.getSimpleVT() >= MVT::i16 &&
7718 "Unknown FP_TO_SINT to lower!");
7720 // These are really Legal.
7721 if (DstTy == MVT::i32 &&
7722 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7723 return std::make_pair(SDValue(), SDValue());
7724 if (Subtarget->is64Bit() &&
7725 DstTy == MVT::i64 &&
7726 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7727 return std::make_pair(SDValue(), SDValue());
7729 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7731 MachineFunction &MF = DAG.getMachineFunction();
7732 unsigned MemSize = DstTy.getSizeInBits()/8;
7733 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7734 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7739 switch (DstTy.getSimpleVT().SimpleTy) {
7740 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7741 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7742 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7743 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7746 SDValue Chain = DAG.getEntryNode();
7747 SDValue Value = Op.getOperand(0);
7748 EVT TheVT = Op.getOperand(0).getValueType();
7749 if (isScalarFPTypeInSSEReg(TheVT)) {
7750 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7751 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7752 MachinePointerInfo::getFixedStack(SSFI),
7754 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7756 Chain, StackSlot, DAG.getValueType(TheVT)
7759 MachineMemOperand *MMO =
7760 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7761 MachineMemOperand::MOLoad, MemSize, MemSize);
7762 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7764 Chain = Value.getValue(1);
7765 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7766 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7769 MachineMemOperand *MMO =
7770 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7771 MachineMemOperand::MOStore, MemSize, MemSize);
7773 // Build the FP_TO_INT*_IN_MEM
7774 SDValue Ops[] = { Chain, Value, StackSlot };
7775 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7776 Ops, 3, DstTy, MMO);
7778 return std::make_pair(FIST, StackSlot);
7781 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7782 SelectionDAG &DAG) const {
7783 if (Op.getValueType().isVector())
7786 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7787 SDValue FIST = Vals.first, StackSlot = Vals.second;
7788 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7789 if (FIST.getNode() == 0) return Op;
7792 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7793 FIST, StackSlot, MachinePointerInfo(),
7794 false, false, false, 0);
7797 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7798 SelectionDAG &DAG) const {
7799 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7800 SDValue FIST = Vals.first, StackSlot = Vals.second;
7801 assert(FIST.getNode() && "Unexpected failure");
7804 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7805 FIST, StackSlot, MachinePointerInfo(),
7806 false, false, false, 0);
7809 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7810 SelectionDAG &DAG) const {
7811 LLVMContext *Context = DAG.getContext();
7812 DebugLoc dl = Op.getDebugLoc();
7813 EVT VT = Op.getValueType();
7816 EltVT = VT.getVectorElementType();
7818 if (EltVT == MVT::f64) {
7819 C = ConstantVector::getSplat(2,
7820 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7822 C = ConstantVector::getSplat(4,
7823 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7825 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7826 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7827 MachinePointerInfo::getConstantPool(),
7828 false, false, false, 16);
7829 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7832 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7833 LLVMContext *Context = DAG.getContext();
7834 DebugLoc dl = Op.getDebugLoc();
7835 EVT VT = Op.getValueType();
7837 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7838 if (VT.isVector()) {
7839 EltVT = VT.getVectorElementType();
7840 NumElts = VT.getVectorNumElements();
7843 if (EltVT == MVT::f64)
7844 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7846 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7847 C = ConstantVector::getSplat(NumElts, C);
7848 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7849 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7850 MachinePointerInfo::getConstantPool(),
7851 false, false, false, 16);
7852 if (VT.isVector()) {
7853 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7854 return DAG.getNode(ISD::BITCAST, dl, VT,
7855 DAG.getNode(ISD::XOR, dl, XORVT,
7856 DAG.getNode(ISD::BITCAST, dl, XORVT,
7858 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7860 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7864 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7865 LLVMContext *Context = DAG.getContext();
7866 SDValue Op0 = Op.getOperand(0);
7867 SDValue Op1 = Op.getOperand(1);
7868 DebugLoc dl = Op.getDebugLoc();
7869 EVT VT = Op.getValueType();
7870 EVT SrcVT = Op1.getValueType();
7872 // If second operand is smaller, extend it first.
7873 if (SrcVT.bitsLT(VT)) {
7874 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7877 // And if it is bigger, shrink it first.
7878 if (SrcVT.bitsGT(VT)) {
7879 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7883 // At this point the operands and the result should have the same
7884 // type, and that won't be f80 since that is not custom lowered.
7886 // First get the sign bit of second operand.
7887 SmallVector<Constant*,4> CV;
7888 if (SrcVT == MVT::f64) {
7889 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7890 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7892 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7893 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7894 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7895 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7897 Constant *C = ConstantVector::get(CV);
7898 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7899 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7900 MachinePointerInfo::getConstantPool(),
7901 false, false, false, 16);
7902 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7904 // Shift sign bit right or left if the two operands have different types.
7905 if (SrcVT.bitsGT(VT)) {
7906 // Op0 is MVT::f32, Op1 is MVT::f64.
7907 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7908 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7909 DAG.getConstant(32, MVT::i32));
7910 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7911 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7912 DAG.getIntPtrConstant(0));
7915 // Clear first operand sign bit.
7917 if (VT == MVT::f64) {
7918 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7919 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7921 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7922 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7923 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7924 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7926 C = ConstantVector::get(CV);
7927 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7928 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7929 MachinePointerInfo::getConstantPool(),
7930 false, false, false, 16);
7931 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7933 // Or the value with the sign bit.
7934 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7937 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7938 SDValue N0 = Op.getOperand(0);
7939 DebugLoc dl = Op.getDebugLoc();
7940 EVT VT = Op.getValueType();
7942 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7943 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7944 DAG.getConstant(1, VT));
7945 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7948 /// Emit nodes that will be selected as "test Op0,Op0", or something
7950 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7951 SelectionDAG &DAG) const {
7952 DebugLoc dl = Op.getDebugLoc();
7954 // CF and OF aren't always set the way we want. Determine which
7955 // of these we need.
7956 bool NeedCF = false;
7957 bool NeedOF = false;
7960 case X86::COND_A: case X86::COND_AE:
7961 case X86::COND_B: case X86::COND_BE:
7964 case X86::COND_G: case X86::COND_GE:
7965 case X86::COND_L: case X86::COND_LE:
7966 case X86::COND_O: case X86::COND_NO:
7971 // See if we can use the EFLAGS value from the operand instead of
7972 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7973 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7974 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7975 // Emit a CMP with 0, which is the TEST pattern.
7976 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7977 DAG.getConstant(0, Op.getValueType()));
7979 unsigned Opcode = 0;
7980 unsigned NumOperands = 0;
7981 switch (Op.getNode()->getOpcode()) {
7983 // Due to an isel shortcoming, be conservative if this add is likely to be
7984 // selected as part of a load-modify-store instruction. When the root node
7985 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7986 // uses of other nodes in the match, such as the ADD in this case. This
7987 // leads to the ADD being left around and reselected, with the result being
7988 // two adds in the output. Alas, even if none our users are stores, that
7989 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7990 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7991 // climbing the DAG back to the root, and it doesn't seem to be worth the
7993 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7994 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7995 if (UI->getOpcode() != ISD::CopyToReg &&
7996 UI->getOpcode() != ISD::SETCC &&
7997 UI->getOpcode() != ISD::STORE)
8000 if (ConstantSDNode *C =
8001 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8002 // An add of one will be selected as an INC.
8003 if (C->getAPIntValue() == 1) {
8004 Opcode = X86ISD::INC;
8009 // An add of negative one (subtract of one) will be selected as a DEC.
8010 if (C->getAPIntValue().isAllOnesValue()) {
8011 Opcode = X86ISD::DEC;
8017 // Otherwise use a regular EFLAGS-setting add.
8018 Opcode = X86ISD::ADD;
8022 // If the primary and result isn't used, don't bother using X86ISD::AND,
8023 // because a TEST instruction will be better.
8024 bool NonFlagUse = false;
8025 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8026 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8028 unsigned UOpNo = UI.getOperandNo();
8029 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8030 // Look pass truncate.
8031 UOpNo = User->use_begin().getOperandNo();
8032 User = *User->use_begin();
8035 if (User->getOpcode() != ISD::BRCOND &&
8036 User->getOpcode() != ISD::SETCC &&
8037 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8050 // Due to the ISEL shortcoming noted above, be conservative if this op is
8051 // likely to be selected as part of a load-modify-store instruction.
8052 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8053 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8054 if (UI->getOpcode() == ISD::STORE)
8057 // Otherwise use a regular EFLAGS-setting instruction.
8058 switch (Op.getNode()->getOpcode()) {
8059 default: llvm_unreachable("unexpected operator!");
8060 case ISD::SUB: Opcode = X86ISD::SUB; break;
8061 case ISD::OR: Opcode = X86ISD::OR; break;
8062 case ISD::XOR: Opcode = X86ISD::XOR; break;
8063 case ISD::AND: Opcode = X86ISD::AND; break;
8075 return SDValue(Op.getNode(), 1);
8082 // Emit a CMP with 0, which is the TEST pattern.
8083 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8084 DAG.getConstant(0, Op.getValueType()));
8086 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8087 SmallVector<SDValue, 4> Ops;
8088 for (unsigned i = 0; i != NumOperands; ++i)
8089 Ops.push_back(Op.getOperand(i));
8091 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8092 DAG.ReplaceAllUsesWith(Op, New);
8093 return SDValue(New.getNode(), 1);
8096 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8098 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8099 SelectionDAG &DAG) const {
8100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8101 if (C->getAPIntValue() == 0)
8102 return EmitTest(Op0, X86CC, DAG);
8104 DebugLoc dl = Op0.getDebugLoc();
8105 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8108 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8109 /// if it's possible.
8110 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8111 DebugLoc dl, SelectionDAG &DAG) const {
8112 SDValue Op0 = And.getOperand(0);
8113 SDValue Op1 = And.getOperand(1);
8114 if (Op0.getOpcode() == ISD::TRUNCATE)
8115 Op0 = Op0.getOperand(0);
8116 if (Op1.getOpcode() == ISD::TRUNCATE)
8117 Op1 = Op1.getOperand(0);
8120 if (Op1.getOpcode() == ISD::SHL)
8121 std::swap(Op0, Op1);
8122 if (Op0.getOpcode() == ISD::SHL) {
8123 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8124 if (And00C->getZExtValue() == 1) {
8125 // If we looked past a truncate, check that it's only truncating away
8127 unsigned BitWidth = Op0.getValueSizeInBits();
8128 unsigned AndBitWidth = And.getValueSizeInBits();
8129 if (BitWidth > AndBitWidth) {
8130 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8131 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8132 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8136 RHS = Op0.getOperand(1);
8138 } else if (Op1.getOpcode() == ISD::Constant) {
8139 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8140 uint64_t AndRHSVal = AndRHS->getZExtValue();
8141 SDValue AndLHS = Op0;
8143 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8144 LHS = AndLHS.getOperand(0);
8145 RHS = AndLHS.getOperand(1);
8148 // Use BT if the immediate can't be encoded in a TEST instruction.
8149 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8151 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8155 if (LHS.getNode()) {
8156 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8157 // instruction. Since the shift amount is in-range-or-undefined, we know
8158 // that doing a bittest on the i32 value is ok. We extend to i32 because
8159 // the encoding for the i16 version is larger than the i32 version.
8160 // Also promote i16 to i32 for performance / code size reason.
8161 if (LHS.getValueType() == MVT::i8 ||
8162 LHS.getValueType() == MVT::i16)
8163 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8165 // If the operand types disagree, extend the shift amount to match. Since
8166 // BT ignores high bits (like shifts) we can use anyextend.
8167 if (LHS.getValueType() != RHS.getValueType())
8168 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8170 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8171 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8172 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8173 DAG.getConstant(Cond, MVT::i8), BT);
8179 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8181 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8183 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8184 SDValue Op0 = Op.getOperand(0);
8185 SDValue Op1 = Op.getOperand(1);
8186 DebugLoc dl = Op.getDebugLoc();
8187 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8189 // Optimize to BT if possible.
8190 // Lower (X & (1 << N)) == 0 to BT(X, N).
8191 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8192 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8193 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8194 Op1.getOpcode() == ISD::Constant &&
8195 cast<ConstantSDNode>(Op1)->isNullValue() &&
8196 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8197 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8198 if (NewSetCC.getNode())
8202 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8204 if (Op1.getOpcode() == ISD::Constant &&
8205 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8206 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8207 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8209 // If the input is a setcc, then reuse the input setcc or use a new one with
8210 // the inverted condition.
8211 if (Op0.getOpcode() == X86ISD::SETCC) {
8212 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8213 bool Invert = (CC == ISD::SETNE) ^
8214 cast<ConstantSDNode>(Op1)->isNullValue();
8215 if (!Invert) return Op0;
8217 CCode = X86::GetOppositeBranchCondition(CCode);
8218 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8219 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8223 bool isFP = Op1.getValueType().isFloatingPoint();
8224 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8225 if (X86CC == X86::COND_INVALID)
8228 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8229 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8230 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8233 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8234 // ones, and then concatenate the result back.
8235 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8236 EVT VT = Op.getValueType();
8238 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8239 "Unsupported value type for operation");
8241 int NumElems = VT.getVectorNumElements();
8242 DebugLoc dl = Op.getDebugLoc();
8243 SDValue CC = Op.getOperand(2);
8244 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8245 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8247 // Extract the LHS vectors
8248 SDValue LHS = Op.getOperand(0);
8249 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8250 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8252 // Extract the RHS vectors
8253 SDValue RHS = Op.getOperand(1);
8254 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8255 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8257 // Issue the operation on the smaller types and concatenate the result back
8258 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8259 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8260 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8261 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8262 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8266 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8268 SDValue Op0 = Op.getOperand(0);
8269 SDValue Op1 = Op.getOperand(1);
8270 SDValue CC = Op.getOperand(2);
8271 EVT VT = Op.getValueType();
8272 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8273 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8274 DebugLoc dl = Op.getDebugLoc();
8278 EVT EltVT = Op0.getValueType().getVectorElementType();
8279 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8283 // SSE Condition code mapping:
8292 switch (SetCCOpcode) {
8295 case ISD::SETEQ: SSECC = 0; break;
8297 case ISD::SETGT: Swap = true; // Fallthrough
8299 case ISD::SETOLT: SSECC = 1; break;
8301 case ISD::SETGE: Swap = true; // Fallthrough
8303 case ISD::SETOLE: SSECC = 2; break;
8304 case ISD::SETUO: SSECC = 3; break;
8306 case ISD::SETNE: SSECC = 4; break;
8307 case ISD::SETULE: Swap = true;
8308 case ISD::SETUGE: SSECC = 5; break;
8309 case ISD::SETULT: Swap = true;
8310 case ISD::SETUGT: SSECC = 6; break;
8311 case ISD::SETO: SSECC = 7; break;
8314 std::swap(Op0, Op1);
8316 // In the two special cases we can't handle, emit two comparisons.
8318 if (SetCCOpcode == ISD::SETUEQ) {
8320 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8321 DAG.getConstant(3, MVT::i8));
8322 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8323 DAG.getConstant(0, MVT::i8));
8324 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8325 } else if (SetCCOpcode == ISD::SETONE) {
8327 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8328 DAG.getConstant(7, MVT::i8));
8329 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8330 DAG.getConstant(4, MVT::i8));
8331 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8333 llvm_unreachable("Illegal FP comparison");
8335 // Handle all other FP comparisons here.
8336 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8337 DAG.getConstant(SSECC, MVT::i8));
8340 // Break 256-bit integer vector compare into smaller ones.
8341 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8342 return Lower256IntVSETCC(Op, DAG);
8344 // We are handling one of the integer comparisons here. Since SSE only has
8345 // GT and EQ comparisons for integer, swapping operands and multiple
8346 // operations may be required for some comparisons.
8348 bool Swap = false, Invert = false, FlipSigns = false;
8350 switch (SetCCOpcode) {
8352 case ISD::SETNE: Invert = true;
8353 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8354 case ISD::SETLT: Swap = true;
8355 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8356 case ISD::SETGE: Swap = true;
8357 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8358 case ISD::SETULT: Swap = true;
8359 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8360 case ISD::SETUGE: Swap = true;
8361 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8364 std::swap(Op0, Op1);
8366 // Check that the operation in question is available (most are plain SSE2,
8367 // but PCMPGTQ and PCMPEQQ have different requirements).
8368 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8370 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8373 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8374 // bits of the inputs before performing those operations.
8376 EVT EltVT = VT.getVectorElementType();
8377 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8379 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8380 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8382 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8383 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8386 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8388 // If the logical-not of the result is required, perform that now.
8390 Result = DAG.getNOT(dl, Result, VT);
8395 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8396 static bool isX86LogicalCmp(SDValue Op) {
8397 unsigned Opc = Op.getNode()->getOpcode();
8398 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8400 if (Op.getResNo() == 1 &&
8401 (Opc == X86ISD::ADD ||
8402 Opc == X86ISD::SUB ||
8403 Opc == X86ISD::ADC ||
8404 Opc == X86ISD::SBB ||
8405 Opc == X86ISD::SMUL ||
8406 Opc == X86ISD::UMUL ||
8407 Opc == X86ISD::INC ||
8408 Opc == X86ISD::DEC ||
8409 Opc == X86ISD::OR ||
8410 Opc == X86ISD::XOR ||
8411 Opc == X86ISD::AND))
8414 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8420 static bool isZero(SDValue V) {
8421 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8422 return C && C->isNullValue();
8425 static bool isAllOnes(SDValue V) {
8426 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8427 return C && C->isAllOnesValue();
8430 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8431 bool addTest = true;
8432 SDValue Cond = Op.getOperand(0);
8433 SDValue Op1 = Op.getOperand(1);
8434 SDValue Op2 = Op.getOperand(2);
8435 DebugLoc DL = Op.getDebugLoc();
8438 if (Cond.getOpcode() == ISD::SETCC) {
8439 SDValue NewCond = LowerSETCC(Cond, DAG);
8440 if (NewCond.getNode())
8444 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8445 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8446 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8447 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8448 if (Cond.getOpcode() == X86ISD::SETCC &&
8449 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8450 isZero(Cond.getOperand(1).getOperand(1))) {
8451 SDValue Cmp = Cond.getOperand(1);
8453 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8455 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8456 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8457 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8459 SDValue CmpOp0 = Cmp.getOperand(0);
8460 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8461 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8463 SDValue Res = // Res = 0 or -1.
8464 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8465 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8467 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8468 Res = DAG.getNOT(DL, Res, Res.getValueType());
8470 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8471 if (N2C == 0 || !N2C->isNullValue())
8472 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8477 // Look past (and (setcc_carry (cmp ...)), 1).
8478 if (Cond.getOpcode() == ISD::AND &&
8479 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8480 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8481 if (C && C->getAPIntValue() == 1)
8482 Cond = Cond.getOperand(0);
8485 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8486 // setting operand in place of the X86ISD::SETCC.
8487 unsigned CondOpcode = Cond.getOpcode();
8488 if (CondOpcode == X86ISD::SETCC ||
8489 CondOpcode == X86ISD::SETCC_CARRY) {
8490 CC = Cond.getOperand(0);
8492 SDValue Cmp = Cond.getOperand(1);
8493 unsigned Opc = Cmp.getOpcode();
8494 EVT VT = Op.getValueType();
8496 bool IllegalFPCMov = false;
8497 if (VT.isFloatingPoint() && !VT.isVector() &&
8498 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8499 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8501 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8502 Opc == X86ISD::BT) { // FIXME
8506 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8507 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8508 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8509 Cond.getOperand(0).getValueType() != MVT::i8)) {
8510 SDValue LHS = Cond.getOperand(0);
8511 SDValue RHS = Cond.getOperand(1);
8515 switch (CondOpcode) {
8516 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8517 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8518 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8519 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8520 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8521 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8522 default: llvm_unreachable("unexpected overflowing operator");
8524 if (CondOpcode == ISD::UMULO)
8525 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8528 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8530 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8532 if (CondOpcode == ISD::UMULO)
8533 Cond = X86Op.getValue(2);
8535 Cond = X86Op.getValue(1);
8537 CC = DAG.getConstant(X86Cond, MVT::i8);
8542 // Look pass the truncate.
8543 if (Cond.getOpcode() == ISD::TRUNCATE)
8544 Cond = Cond.getOperand(0);
8546 // We know the result of AND is compared against zero. Try to match
8548 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8549 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8550 if (NewSetCC.getNode()) {
8551 CC = NewSetCC.getOperand(0);
8552 Cond = NewSetCC.getOperand(1);
8559 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8560 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8563 // a < b ? -1 : 0 -> RES = ~setcc_carry
8564 // a < b ? 0 : -1 -> RES = setcc_carry
8565 // a >= b ? -1 : 0 -> RES = setcc_carry
8566 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8567 if (Cond.getOpcode() == X86ISD::CMP) {
8568 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8570 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8571 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8572 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8573 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8574 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8575 return DAG.getNOT(DL, Res, Res.getValueType());
8580 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8581 // condition is true.
8582 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8583 SDValue Ops[] = { Op2, Op1, CC, Cond };
8584 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8587 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8588 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8589 // from the AND / OR.
8590 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8591 Opc = Op.getOpcode();
8592 if (Opc != ISD::OR && Opc != ISD::AND)
8594 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8595 Op.getOperand(0).hasOneUse() &&
8596 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8597 Op.getOperand(1).hasOneUse());
8600 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8601 // 1 and that the SETCC node has a single use.
8602 static bool isXor1OfSetCC(SDValue Op) {
8603 if (Op.getOpcode() != ISD::XOR)
8605 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8606 if (N1C && N1C->getAPIntValue() == 1) {
8607 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8608 Op.getOperand(0).hasOneUse();
8613 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8614 bool addTest = true;
8615 SDValue Chain = Op.getOperand(0);
8616 SDValue Cond = Op.getOperand(1);
8617 SDValue Dest = Op.getOperand(2);
8618 DebugLoc dl = Op.getDebugLoc();
8620 bool Inverted = false;
8622 if (Cond.getOpcode() == ISD::SETCC) {
8623 // Check for setcc([su]{add,sub,mul}o == 0).
8624 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8625 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8626 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8627 Cond.getOperand(0).getResNo() == 1 &&
8628 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8629 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8630 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8631 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8632 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8633 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8635 Cond = Cond.getOperand(0);
8637 SDValue NewCond = LowerSETCC(Cond, DAG);
8638 if (NewCond.getNode())
8643 // FIXME: LowerXALUO doesn't handle these!!
8644 else if (Cond.getOpcode() == X86ISD::ADD ||
8645 Cond.getOpcode() == X86ISD::SUB ||
8646 Cond.getOpcode() == X86ISD::SMUL ||
8647 Cond.getOpcode() == X86ISD::UMUL)
8648 Cond = LowerXALUO(Cond, DAG);
8651 // Look pass (and (setcc_carry (cmp ...)), 1).
8652 if (Cond.getOpcode() == ISD::AND &&
8653 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8654 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8655 if (C && C->getAPIntValue() == 1)
8656 Cond = Cond.getOperand(0);
8659 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8660 // setting operand in place of the X86ISD::SETCC.
8661 unsigned CondOpcode = Cond.getOpcode();
8662 if (CondOpcode == X86ISD::SETCC ||
8663 CondOpcode == X86ISD::SETCC_CARRY) {
8664 CC = Cond.getOperand(0);
8666 SDValue Cmp = Cond.getOperand(1);
8667 unsigned Opc = Cmp.getOpcode();
8668 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8669 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8673 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8677 // These can only come from an arithmetic instruction with overflow,
8678 // e.g. SADDO, UADDO.
8679 Cond = Cond.getNode()->getOperand(1);
8685 CondOpcode = Cond.getOpcode();
8686 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8687 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8688 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8689 Cond.getOperand(0).getValueType() != MVT::i8)) {
8690 SDValue LHS = Cond.getOperand(0);
8691 SDValue RHS = Cond.getOperand(1);
8695 switch (CondOpcode) {
8696 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8697 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8698 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8699 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8700 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8701 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8702 default: llvm_unreachable("unexpected overflowing operator");
8705 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8706 if (CondOpcode == ISD::UMULO)
8707 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8710 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8712 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8714 if (CondOpcode == ISD::UMULO)
8715 Cond = X86Op.getValue(2);
8717 Cond = X86Op.getValue(1);
8719 CC = DAG.getConstant(X86Cond, MVT::i8);
8723 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8724 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8725 if (CondOpc == ISD::OR) {
8726 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8727 // two branches instead of an explicit OR instruction with a
8729 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8730 isX86LogicalCmp(Cmp)) {
8731 CC = Cond.getOperand(0).getOperand(0);
8732 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8733 Chain, Dest, CC, Cmp);
8734 CC = Cond.getOperand(1).getOperand(0);
8738 } else { // ISD::AND
8739 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8740 // two branches instead of an explicit AND instruction with a
8741 // separate test. However, we only do this if this block doesn't
8742 // have a fall-through edge, because this requires an explicit
8743 // jmp when the condition is false.
8744 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8745 isX86LogicalCmp(Cmp) &&
8746 Op.getNode()->hasOneUse()) {
8747 X86::CondCode CCode =
8748 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8749 CCode = X86::GetOppositeBranchCondition(CCode);
8750 CC = DAG.getConstant(CCode, MVT::i8);
8751 SDNode *User = *Op.getNode()->use_begin();
8752 // Look for an unconditional branch following this conditional branch.
8753 // We need this because we need to reverse the successors in order
8754 // to implement FCMP_OEQ.
8755 if (User->getOpcode() == ISD::BR) {
8756 SDValue FalseBB = User->getOperand(1);
8758 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8759 assert(NewBR == User);
8763 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8764 Chain, Dest, CC, Cmp);
8765 X86::CondCode CCode =
8766 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8767 CCode = X86::GetOppositeBranchCondition(CCode);
8768 CC = DAG.getConstant(CCode, MVT::i8);
8774 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8775 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8776 // It should be transformed during dag combiner except when the condition
8777 // is set by a arithmetics with overflow node.
8778 X86::CondCode CCode =
8779 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8780 CCode = X86::GetOppositeBranchCondition(CCode);
8781 CC = DAG.getConstant(CCode, MVT::i8);
8782 Cond = Cond.getOperand(0).getOperand(1);
8784 } else if (Cond.getOpcode() == ISD::SETCC &&
8785 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8786 // For FCMP_OEQ, we can emit
8787 // two branches instead of an explicit AND instruction with a
8788 // separate test. However, we only do this if this block doesn't
8789 // have a fall-through edge, because this requires an explicit
8790 // jmp when the condition is false.
8791 if (Op.getNode()->hasOneUse()) {
8792 SDNode *User = *Op.getNode()->use_begin();
8793 // Look for an unconditional branch following this conditional branch.
8794 // We need this because we need to reverse the successors in order
8795 // to implement FCMP_OEQ.
8796 if (User->getOpcode() == ISD::BR) {
8797 SDValue FalseBB = User->getOperand(1);
8799 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8800 assert(NewBR == User);
8804 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8805 Cond.getOperand(0), Cond.getOperand(1));
8806 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8807 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8808 Chain, Dest, CC, Cmp);
8809 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8814 } else if (Cond.getOpcode() == ISD::SETCC &&
8815 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8816 // For FCMP_UNE, we can emit
8817 // two branches instead of an explicit AND instruction with a
8818 // separate test. However, we only do this if this block doesn't
8819 // have a fall-through edge, because this requires an explicit
8820 // jmp when the condition is false.
8821 if (Op.getNode()->hasOneUse()) {
8822 SDNode *User = *Op.getNode()->use_begin();
8823 // Look for an unconditional branch following this conditional branch.
8824 // We need this because we need to reverse the successors in order
8825 // to implement FCMP_UNE.
8826 if (User->getOpcode() == ISD::BR) {
8827 SDValue FalseBB = User->getOperand(1);
8829 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8830 assert(NewBR == User);
8833 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8834 Cond.getOperand(0), Cond.getOperand(1));
8835 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8836 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8837 Chain, Dest, CC, Cmp);
8838 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8848 // Look pass the truncate.
8849 if (Cond.getOpcode() == ISD::TRUNCATE)
8850 Cond = Cond.getOperand(0);
8852 // We know the result of AND is compared against zero. Try to match
8854 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8855 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8856 if (NewSetCC.getNode()) {
8857 CC = NewSetCC.getOperand(0);
8858 Cond = NewSetCC.getOperand(1);
8865 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8866 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8868 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8869 Chain, Dest, CC, Cond);
8873 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8874 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8875 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8876 // that the guard pages used by the OS virtual memory manager are allocated in
8877 // correct sequence.
8879 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8880 SelectionDAG &DAG) const {
8881 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8882 getTargetMachine().Options.EnableSegmentedStacks) &&
8883 "This should be used only on Windows targets or when segmented stacks "
8885 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8886 DebugLoc dl = Op.getDebugLoc();
8889 SDValue Chain = Op.getOperand(0);
8890 SDValue Size = Op.getOperand(1);
8891 // FIXME: Ensure alignment here
8893 bool Is64Bit = Subtarget->is64Bit();
8894 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8896 if (getTargetMachine().Options.EnableSegmentedStacks) {
8897 MachineFunction &MF = DAG.getMachineFunction();
8898 MachineRegisterInfo &MRI = MF.getRegInfo();
8901 // The 64 bit implementation of segmented stacks needs to clobber both r10
8902 // r11. This makes it impossible to use it along with nested parameters.
8903 const Function *F = MF.getFunction();
8905 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8907 if (I->hasNestAttr())
8908 report_fatal_error("Cannot use segmented stacks with functions that "
8909 "have nested arguments.");
8912 const TargetRegisterClass *AddrRegClass =
8913 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8914 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8915 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8916 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8917 DAG.getRegister(Vreg, SPTy));
8918 SDValue Ops1[2] = { Value, Chain };
8919 return DAG.getMergeValues(Ops1, 2, dl);
8922 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8924 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8925 Flag = Chain.getValue(1);
8926 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8928 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8929 Flag = Chain.getValue(1);
8931 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8933 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8934 return DAG.getMergeValues(Ops1, 2, dl);
8938 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8939 MachineFunction &MF = DAG.getMachineFunction();
8940 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8942 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8943 DebugLoc DL = Op.getDebugLoc();
8945 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8946 // vastart just stores the address of the VarArgsFrameIndex slot into the
8947 // memory location argument.
8948 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8950 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8951 MachinePointerInfo(SV), false, false, 0);
8955 // gp_offset (0 - 6 * 8)
8956 // fp_offset (48 - 48 + 8 * 16)
8957 // overflow_arg_area (point to parameters coming in memory).
8959 SmallVector<SDValue, 8> MemOps;
8960 SDValue FIN = Op.getOperand(1);
8962 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8963 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8965 FIN, MachinePointerInfo(SV), false, false, 0);
8966 MemOps.push_back(Store);
8969 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8970 FIN, DAG.getIntPtrConstant(4));
8971 Store = DAG.getStore(Op.getOperand(0), DL,
8972 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8974 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8975 MemOps.push_back(Store);
8977 // Store ptr to overflow_arg_area
8978 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8979 FIN, DAG.getIntPtrConstant(4));
8980 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8982 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8983 MachinePointerInfo(SV, 8),
8985 MemOps.push_back(Store);
8987 // Store ptr to reg_save_area.
8988 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8989 FIN, DAG.getIntPtrConstant(8));
8990 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8992 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8993 MachinePointerInfo(SV, 16), false, false, 0);
8994 MemOps.push_back(Store);
8995 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8996 &MemOps[0], MemOps.size());
8999 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9000 assert(Subtarget->is64Bit() &&
9001 "LowerVAARG only handles 64-bit va_arg!");
9002 assert((Subtarget->isTargetLinux() ||
9003 Subtarget->isTargetDarwin()) &&
9004 "Unhandled target in LowerVAARG");
9005 assert(Op.getNode()->getNumOperands() == 4);
9006 SDValue Chain = Op.getOperand(0);
9007 SDValue SrcPtr = Op.getOperand(1);
9008 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9009 unsigned Align = Op.getConstantOperandVal(3);
9010 DebugLoc dl = Op.getDebugLoc();
9012 EVT ArgVT = Op.getNode()->getValueType(0);
9013 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9014 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9017 // Decide which area this value should be read from.
9018 // TODO: Implement the AMD64 ABI in its entirety. This simple
9019 // selection mechanism works only for the basic types.
9020 if (ArgVT == MVT::f80) {
9021 llvm_unreachable("va_arg for f80 not yet implemented");
9022 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9023 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9024 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9025 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9027 llvm_unreachable("Unhandled argument type in LowerVAARG");
9031 // Sanity Check: Make sure using fp_offset makes sense.
9032 assert(!getTargetMachine().Options.UseSoftFloat &&
9033 !(DAG.getMachineFunction()
9034 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9035 Subtarget->hasSSE1());
9038 // Insert VAARG_64 node into the DAG
9039 // VAARG_64 returns two values: Variable Argument Address, Chain
9040 SmallVector<SDValue, 11> InstOps;
9041 InstOps.push_back(Chain);
9042 InstOps.push_back(SrcPtr);
9043 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9044 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9045 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9046 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9047 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9048 VTs, &InstOps[0], InstOps.size(),
9050 MachinePointerInfo(SV),
9055 Chain = VAARG.getValue(1);
9057 // Load the next argument and return it
9058 return DAG.getLoad(ArgVT, dl,
9061 MachinePointerInfo(),
9062 false, false, false, 0);
9065 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9066 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9067 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9068 SDValue Chain = Op.getOperand(0);
9069 SDValue DstPtr = Op.getOperand(1);
9070 SDValue SrcPtr = Op.getOperand(2);
9071 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9072 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9073 DebugLoc DL = Op.getDebugLoc();
9075 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9076 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9078 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9081 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9082 // may or may not be a constant. Takes immediate version of shift as input.
9083 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9084 SDValue SrcOp, SDValue ShAmt,
9085 SelectionDAG &DAG) {
9086 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9088 if (isa<ConstantSDNode>(ShAmt)) {
9090 default: llvm_unreachable("Unknown target vector shift node");
9094 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9098 // Change opcode to non-immediate version
9100 default: llvm_unreachable("Unknown target vector shift node");
9101 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9102 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9103 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9106 // Need to build a vector containing shift amount
9107 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9110 ShOps[1] = DAG.getConstant(0, MVT::i32);
9111 ShOps[2] = DAG.getUNDEF(MVT::i32);
9112 ShOps[3] = DAG.getUNDEF(MVT::i32);
9113 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9114 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9115 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9119 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9120 DebugLoc dl = Op.getDebugLoc();
9121 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9123 default: return SDValue(); // Don't custom lower most intrinsics.
9124 // Comparison intrinsics.
9125 case Intrinsic::x86_sse_comieq_ss:
9126 case Intrinsic::x86_sse_comilt_ss:
9127 case Intrinsic::x86_sse_comile_ss:
9128 case Intrinsic::x86_sse_comigt_ss:
9129 case Intrinsic::x86_sse_comige_ss:
9130 case Intrinsic::x86_sse_comineq_ss:
9131 case Intrinsic::x86_sse_ucomieq_ss:
9132 case Intrinsic::x86_sse_ucomilt_ss:
9133 case Intrinsic::x86_sse_ucomile_ss:
9134 case Intrinsic::x86_sse_ucomigt_ss:
9135 case Intrinsic::x86_sse_ucomige_ss:
9136 case Intrinsic::x86_sse_ucomineq_ss:
9137 case Intrinsic::x86_sse2_comieq_sd:
9138 case Intrinsic::x86_sse2_comilt_sd:
9139 case Intrinsic::x86_sse2_comile_sd:
9140 case Intrinsic::x86_sse2_comigt_sd:
9141 case Intrinsic::x86_sse2_comige_sd:
9142 case Intrinsic::x86_sse2_comineq_sd:
9143 case Intrinsic::x86_sse2_ucomieq_sd:
9144 case Intrinsic::x86_sse2_ucomilt_sd:
9145 case Intrinsic::x86_sse2_ucomile_sd:
9146 case Intrinsic::x86_sse2_ucomigt_sd:
9147 case Intrinsic::x86_sse2_ucomige_sd:
9148 case Intrinsic::x86_sse2_ucomineq_sd: {
9150 ISD::CondCode CC = ISD::SETCC_INVALID;
9152 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9153 case Intrinsic::x86_sse_comieq_ss:
9154 case Intrinsic::x86_sse2_comieq_sd:
9158 case Intrinsic::x86_sse_comilt_ss:
9159 case Intrinsic::x86_sse2_comilt_sd:
9163 case Intrinsic::x86_sse_comile_ss:
9164 case Intrinsic::x86_sse2_comile_sd:
9168 case Intrinsic::x86_sse_comigt_ss:
9169 case Intrinsic::x86_sse2_comigt_sd:
9173 case Intrinsic::x86_sse_comige_ss:
9174 case Intrinsic::x86_sse2_comige_sd:
9178 case Intrinsic::x86_sse_comineq_ss:
9179 case Intrinsic::x86_sse2_comineq_sd:
9183 case Intrinsic::x86_sse_ucomieq_ss:
9184 case Intrinsic::x86_sse2_ucomieq_sd:
9185 Opc = X86ISD::UCOMI;
9188 case Intrinsic::x86_sse_ucomilt_ss:
9189 case Intrinsic::x86_sse2_ucomilt_sd:
9190 Opc = X86ISD::UCOMI;
9193 case Intrinsic::x86_sse_ucomile_ss:
9194 case Intrinsic::x86_sse2_ucomile_sd:
9195 Opc = X86ISD::UCOMI;
9198 case Intrinsic::x86_sse_ucomigt_ss:
9199 case Intrinsic::x86_sse2_ucomigt_sd:
9200 Opc = X86ISD::UCOMI;
9203 case Intrinsic::x86_sse_ucomige_ss:
9204 case Intrinsic::x86_sse2_ucomige_sd:
9205 Opc = X86ISD::UCOMI;
9208 case Intrinsic::x86_sse_ucomineq_ss:
9209 case Intrinsic::x86_sse2_ucomineq_sd:
9210 Opc = X86ISD::UCOMI;
9215 SDValue LHS = Op.getOperand(1);
9216 SDValue RHS = Op.getOperand(2);
9217 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9218 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9219 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9220 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9221 DAG.getConstant(X86CC, MVT::i8), Cond);
9222 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9224 // XOP comparison intrinsics
9225 case Intrinsic::x86_xop_vpcomltb:
9226 case Intrinsic::x86_xop_vpcomltw:
9227 case Intrinsic::x86_xop_vpcomltd:
9228 case Intrinsic::x86_xop_vpcomltq:
9229 case Intrinsic::x86_xop_vpcomltub:
9230 case Intrinsic::x86_xop_vpcomltuw:
9231 case Intrinsic::x86_xop_vpcomltud:
9232 case Intrinsic::x86_xop_vpcomltuq:
9233 case Intrinsic::x86_xop_vpcomleb:
9234 case Intrinsic::x86_xop_vpcomlew:
9235 case Intrinsic::x86_xop_vpcomled:
9236 case Intrinsic::x86_xop_vpcomleq:
9237 case Intrinsic::x86_xop_vpcomleub:
9238 case Intrinsic::x86_xop_vpcomleuw:
9239 case Intrinsic::x86_xop_vpcomleud:
9240 case Intrinsic::x86_xop_vpcomleuq:
9241 case Intrinsic::x86_xop_vpcomgtb:
9242 case Intrinsic::x86_xop_vpcomgtw:
9243 case Intrinsic::x86_xop_vpcomgtd:
9244 case Intrinsic::x86_xop_vpcomgtq:
9245 case Intrinsic::x86_xop_vpcomgtub:
9246 case Intrinsic::x86_xop_vpcomgtuw:
9247 case Intrinsic::x86_xop_vpcomgtud:
9248 case Intrinsic::x86_xop_vpcomgtuq:
9249 case Intrinsic::x86_xop_vpcomgeb:
9250 case Intrinsic::x86_xop_vpcomgew:
9251 case Intrinsic::x86_xop_vpcomged:
9252 case Intrinsic::x86_xop_vpcomgeq:
9253 case Intrinsic::x86_xop_vpcomgeub:
9254 case Intrinsic::x86_xop_vpcomgeuw:
9255 case Intrinsic::x86_xop_vpcomgeud:
9256 case Intrinsic::x86_xop_vpcomgeuq:
9257 case Intrinsic::x86_xop_vpcomeqb:
9258 case Intrinsic::x86_xop_vpcomeqw:
9259 case Intrinsic::x86_xop_vpcomeqd:
9260 case Intrinsic::x86_xop_vpcomeqq:
9261 case Intrinsic::x86_xop_vpcomequb:
9262 case Intrinsic::x86_xop_vpcomequw:
9263 case Intrinsic::x86_xop_vpcomequd:
9264 case Intrinsic::x86_xop_vpcomequq:
9265 case Intrinsic::x86_xop_vpcomneb:
9266 case Intrinsic::x86_xop_vpcomnew:
9267 case Intrinsic::x86_xop_vpcomned:
9268 case Intrinsic::x86_xop_vpcomneq:
9269 case Intrinsic::x86_xop_vpcomneub:
9270 case Intrinsic::x86_xop_vpcomneuw:
9271 case Intrinsic::x86_xop_vpcomneud:
9272 case Intrinsic::x86_xop_vpcomneuq:
9273 case Intrinsic::x86_xop_vpcomfalseb:
9274 case Intrinsic::x86_xop_vpcomfalsew:
9275 case Intrinsic::x86_xop_vpcomfalsed:
9276 case Intrinsic::x86_xop_vpcomfalseq:
9277 case Intrinsic::x86_xop_vpcomfalseub:
9278 case Intrinsic::x86_xop_vpcomfalseuw:
9279 case Intrinsic::x86_xop_vpcomfalseud:
9280 case Intrinsic::x86_xop_vpcomfalseuq:
9281 case Intrinsic::x86_xop_vpcomtrueb:
9282 case Intrinsic::x86_xop_vpcomtruew:
9283 case Intrinsic::x86_xop_vpcomtrued:
9284 case Intrinsic::x86_xop_vpcomtrueq:
9285 case Intrinsic::x86_xop_vpcomtrueub:
9286 case Intrinsic::x86_xop_vpcomtrueuw:
9287 case Intrinsic::x86_xop_vpcomtrueud:
9288 case Intrinsic::x86_xop_vpcomtrueuq: {
9293 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9294 case Intrinsic::x86_xop_vpcomltb:
9295 case Intrinsic::x86_xop_vpcomltw:
9296 case Intrinsic::x86_xop_vpcomltd:
9297 case Intrinsic::x86_xop_vpcomltq:
9299 Opc = X86ISD::VPCOM;
9301 case Intrinsic::x86_xop_vpcomltub:
9302 case Intrinsic::x86_xop_vpcomltuw:
9303 case Intrinsic::x86_xop_vpcomltud:
9304 case Intrinsic::x86_xop_vpcomltuq:
9306 Opc = X86ISD::VPCOMU;
9308 case Intrinsic::x86_xop_vpcomleb:
9309 case Intrinsic::x86_xop_vpcomlew:
9310 case Intrinsic::x86_xop_vpcomled:
9311 case Intrinsic::x86_xop_vpcomleq:
9313 Opc = X86ISD::VPCOM;
9315 case Intrinsic::x86_xop_vpcomleub:
9316 case Intrinsic::x86_xop_vpcomleuw:
9317 case Intrinsic::x86_xop_vpcomleud:
9318 case Intrinsic::x86_xop_vpcomleuq:
9320 Opc = X86ISD::VPCOMU;
9322 case Intrinsic::x86_xop_vpcomgtb:
9323 case Intrinsic::x86_xop_vpcomgtw:
9324 case Intrinsic::x86_xop_vpcomgtd:
9325 case Intrinsic::x86_xop_vpcomgtq:
9327 Opc = X86ISD::VPCOM;
9329 case Intrinsic::x86_xop_vpcomgtub:
9330 case Intrinsic::x86_xop_vpcomgtuw:
9331 case Intrinsic::x86_xop_vpcomgtud:
9332 case Intrinsic::x86_xop_vpcomgtuq:
9334 Opc = X86ISD::VPCOMU;
9336 case Intrinsic::x86_xop_vpcomgeb:
9337 case Intrinsic::x86_xop_vpcomgew:
9338 case Intrinsic::x86_xop_vpcomged:
9339 case Intrinsic::x86_xop_vpcomgeq:
9341 Opc = X86ISD::VPCOM;
9343 case Intrinsic::x86_xop_vpcomgeub:
9344 case Intrinsic::x86_xop_vpcomgeuw:
9345 case Intrinsic::x86_xop_vpcomgeud:
9346 case Intrinsic::x86_xop_vpcomgeuq:
9348 Opc = X86ISD::VPCOMU;
9350 case Intrinsic::x86_xop_vpcomeqb:
9351 case Intrinsic::x86_xop_vpcomeqw:
9352 case Intrinsic::x86_xop_vpcomeqd:
9353 case Intrinsic::x86_xop_vpcomeqq:
9355 Opc = X86ISD::VPCOM;
9357 case Intrinsic::x86_xop_vpcomequb:
9358 case Intrinsic::x86_xop_vpcomequw:
9359 case Intrinsic::x86_xop_vpcomequd:
9360 case Intrinsic::x86_xop_vpcomequq:
9362 Opc = X86ISD::VPCOMU;
9364 case Intrinsic::x86_xop_vpcomneb:
9365 case Intrinsic::x86_xop_vpcomnew:
9366 case Intrinsic::x86_xop_vpcomned:
9367 case Intrinsic::x86_xop_vpcomneq:
9369 Opc = X86ISD::VPCOM;
9371 case Intrinsic::x86_xop_vpcomneub:
9372 case Intrinsic::x86_xop_vpcomneuw:
9373 case Intrinsic::x86_xop_vpcomneud:
9374 case Intrinsic::x86_xop_vpcomneuq:
9376 Opc = X86ISD::VPCOMU;
9378 case Intrinsic::x86_xop_vpcomfalseb:
9379 case Intrinsic::x86_xop_vpcomfalsew:
9380 case Intrinsic::x86_xop_vpcomfalsed:
9381 case Intrinsic::x86_xop_vpcomfalseq:
9383 Opc = X86ISD::VPCOM;
9385 case Intrinsic::x86_xop_vpcomfalseub:
9386 case Intrinsic::x86_xop_vpcomfalseuw:
9387 case Intrinsic::x86_xop_vpcomfalseud:
9388 case Intrinsic::x86_xop_vpcomfalseuq:
9390 Opc = X86ISD::VPCOMU;
9392 case Intrinsic::x86_xop_vpcomtrueb:
9393 case Intrinsic::x86_xop_vpcomtruew:
9394 case Intrinsic::x86_xop_vpcomtrued:
9395 case Intrinsic::x86_xop_vpcomtrueq:
9397 Opc = X86ISD::VPCOM;
9399 case Intrinsic::x86_xop_vpcomtrueub:
9400 case Intrinsic::x86_xop_vpcomtrueuw:
9401 case Intrinsic::x86_xop_vpcomtrueud:
9402 case Intrinsic::x86_xop_vpcomtrueuq:
9404 Opc = X86ISD::VPCOMU;
9408 SDValue LHS = Op.getOperand(1);
9409 SDValue RHS = Op.getOperand(2);
9410 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9411 DAG.getConstant(CC, MVT::i8));
9414 // Arithmetic intrinsics.
9415 case Intrinsic::x86_sse2_pmulu_dq:
9416 case Intrinsic::x86_avx2_pmulu_dq:
9417 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9418 Op.getOperand(1), Op.getOperand(2));
9419 case Intrinsic::x86_sse3_hadd_ps:
9420 case Intrinsic::x86_sse3_hadd_pd:
9421 case Intrinsic::x86_avx_hadd_ps_256:
9422 case Intrinsic::x86_avx_hadd_pd_256:
9423 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9424 Op.getOperand(1), Op.getOperand(2));
9425 case Intrinsic::x86_sse3_hsub_ps:
9426 case Intrinsic::x86_sse3_hsub_pd:
9427 case Intrinsic::x86_avx_hsub_ps_256:
9428 case Intrinsic::x86_avx_hsub_pd_256:
9429 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9430 Op.getOperand(1), Op.getOperand(2));
9431 case Intrinsic::x86_ssse3_phadd_w_128:
9432 case Intrinsic::x86_ssse3_phadd_d_128:
9433 case Intrinsic::x86_avx2_phadd_w:
9434 case Intrinsic::x86_avx2_phadd_d:
9435 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9436 Op.getOperand(1), Op.getOperand(2));
9437 case Intrinsic::x86_ssse3_phsub_w_128:
9438 case Intrinsic::x86_ssse3_phsub_d_128:
9439 case Intrinsic::x86_avx2_phsub_w:
9440 case Intrinsic::x86_avx2_phsub_d:
9441 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9442 Op.getOperand(1), Op.getOperand(2));
9443 case Intrinsic::x86_avx2_psllv_d:
9444 case Intrinsic::x86_avx2_psllv_q:
9445 case Intrinsic::x86_avx2_psllv_d_256:
9446 case Intrinsic::x86_avx2_psllv_q_256:
9447 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9448 Op.getOperand(1), Op.getOperand(2));
9449 case Intrinsic::x86_avx2_psrlv_d:
9450 case Intrinsic::x86_avx2_psrlv_q:
9451 case Intrinsic::x86_avx2_psrlv_d_256:
9452 case Intrinsic::x86_avx2_psrlv_q_256:
9453 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9454 Op.getOperand(1), Op.getOperand(2));
9455 case Intrinsic::x86_avx2_psrav_d:
9456 case Intrinsic::x86_avx2_psrav_d_256:
9457 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9458 Op.getOperand(1), Op.getOperand(2));
9459 case Intrinsic::x86_ssse3_pshuf_b_128:
9460 case Intrinsic::x86_avx2_pshuf_b:
9461 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9462 Op.getOperand(1), Op.getOperand(2));
9463 case Intrinsic::x86_ssse3_psign_b_128:
9464 case Intrinsic::x86_ssse3_psign_w_128:
9465 case Intrinsic::x86_ssse3_psign_d_128:
9466 case Intrinsic::x86_avx2_psign_b:
9467 case Intrinsic::x86_avx2_psign_w:
9468 case Intrinsic::x86_avx2_psign_d:
9469 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9470 Op.getOperand(1), Op.getOperand(2));
9471 case Intrinsic::x86_sse41_insertps:
9472 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9473 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9474 case Intrinsic::x86_avx_vperm2f128_ps_256:
9475 case Intrinsic::x86_avx_vperm2f128_pd_256:
9476 case Intrinsic::x86_avx_vperm2f128_si_256:
9477 case Intrinsic::x86_avx2_vperm2i128:
9478 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9479 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9480 case Intrinsic::x86_avx_vpermil_ps:
9481 case Intrinsic::x86_avx_vpermil_pd:
9482 case Intrinsic::x86_avx_vpermil_ps_256:
9483 case Intrinsic::x86_avx_vpermil_pd_256:
9484 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(),
9485 Op.getOperand(1), Op.getOperand(2));
9487 // ptest and testp intrinsics. The intrinsic these come from are designed to
9488 // return an integer value, not just an instruction so lower it to the ptest
9489 // or testp pattern and a setcc for the result.
9490 case Intrinsic::x86_sse41_ptestz:
9491 case Intrinsic::x86_sse41_ptestc:
9492 case Intrinsic::x86_sse41_ptestnzc:
9493 case Intrinsic::x86_avx_ptestz_256:
9494 case Intrinsic::x86_avx_ptestc_256:
9495 case Intrinsic::x86_avx_ptestnzc_256:
9496 case Intrinsic::x86_avx_vtestz_ps:
9497 case Intrinsic::x86_avx_vtestc_ps:
9498 case Intrinsic::x86_avx_vtestnzc_ps:
9499 case Intrinsic::x86_avx_vtestz_pd:
9500 case Intrinsic::x86_avx_vtestc_pd:
9501 case Intrinsic::x86_avx_vtestnzc_pd:
9502 case Intrinsic::x86_avx_vtestz_ps_256:
9503 case Intrinsic::x86_avx_vtestc_ps_256:
9504 case Intrinsic::x86_avx_vtestnzc_ps_256:
9505 case Intrinsic::x86_avx_vtestz_pd_256:
9506 case Intrinsic::x86_avx_vtestc_pd_256:
9507 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9508 bool IsTestPacked = false;
9511 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9512 case Intrinsic::x86_avx_vtestz_ps:
9513 case Intrinsic::x86_avx_vtestz_pd:
9514 case Intrinsic::x86_avx_vtestz_ps_256:
9515 case Intrinsic::x86_avx_vtestz_pd_256:
9516 IsTestPacked = true; // Fallthrough
9517 case Intrinsic::x86_sse41_ptestz:
9518 case Intrinsic::x86_avx_ptestz_256:
9520 X86CC = X86::COND_E;
9522 case Intrinsic::x86_avx_vtestc_ps:
9523 case Intrinsic::x86_avx_vtestc_pd:
9524 case Intrinsic::x86_avx_vtestc_ps_256:
9525 case Intrinsic::x86_avx_vtestc_pd_256:
9526 IsTestPacked = true; // Fallthrough
9527 case Intrinsic::x86_sse41_ptestc:
9528 case Intrinsic::x86_avx_ptestc_256:
9530 X86CC = X86::COND_B;
9532 case Intrinsic::x86_avx_vtestnzc_ps:
9533 case Intrinsic::x86_avx_vtestnzc_pd:
9534 case Intrinsic::x86_avx_vtestnzc_ps_256:
9535 case Intrinsic::x86_avx_vtestnzc_pd_256:
9536 IsTestPacked = true; // Fallthrough
9537 case Intrinsic::x86_sse41_ptestnzc:
9538 case Intrinsic::x86_avx_ptestnzc_256:
9540 X86CC = X86::COND_A;
9544 SDValue LHS = Op.getOperand(1);
9545 SDValue RHS = Op.getOperand(2);
9546 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9547 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9548 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9549 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9550 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9553 // SSE/AVX shift intrinsics
9554 case Intrinsic::x86_sse2_psll_w:
9555 case Intrinsic::x86_sse2_psll_d:
9556 case Intrinsic::x86_sse2_psll_q:
9557 case Intrinsic::x86_avx2_psll_w:
9558 case Intrinsic::x86_avx2_psll_d:
9559 case Intrinsic::x86_avx2_psll_q:
9560 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9561 Op.getOperand(1), Op.getOperand(2));
9562 case Intrinsic::x86_sse2_psrl_w:
9563 case Intrinsic::x86_sse2_psrl_d:
9564 case Intrinsic::x86_sse2_psrl_q:
9565 case Intrinsic::x86_avx2_psrl_w:
9566 case Intrinsic::x86_avx2_psrl_d:
9567 case Intrinsic::x86_avx2_psrl_q:
9568 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9569 Op.getOperand(1), Op.getOperand(2));
9570 case Intrinsic::x86_sse2_psra_w:
9571 case Intrinsic::x86_sse2_psra_d:
9572 case Intrinsic::x86_avx2_psra_w:
9573 case Intrinsic::x86_avx2_psra_d:
9574 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9575 Op.getOperand(1), Op.getOperand(2));
9576 case Intrinsic::x86_sse2_pslli_w:
9577 case Intrinsic::x86_sse2_pslli_d:
9578 case Intrinsic::x86_sse2_pslli_q:
9579 case Intrinsic::x86_avx2_pslli_w:
9580 case Intrinsic::x86_avx2_pslli_d:
9581 case Intrinsic::x86_avx2_pslli_q:
9582 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9583 Op.getOperand(1), Op.getOperand(2), DAG);
9584 case Intrinsic::x86_sse2_psrli_w:
9585 case Intrinsic::x86_sse2_psrli_d:
9586 case Intrinsic::x86_sse2_psrli_q:
9587 case Intrinsic::x86_avx2_psrli_w:
9588 case Intrinsic::x86_avx2_psrli_d:
9589 case Intrinsic::x86_avx2_psrli_q:
9590 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9591 Op.getOperand(1), Op.getOperand(2), DAG);
9592 case Intrinsic::x86_sse2_psrai_w:
9593 case Intrinsic::x86_sse2_psrai_d:
9594 case Intrinsic::x86_avx2_psrai_w:
9595 case Intrinsic::x86_avx2_psrai_d:
9596 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9597 Op.getOperand(1), Op.getOperand(2), DAG);
9598 // Fix vector shift instructions where the last operand is a non-immediate
9600 case Intrinsic::x86_mmx_pslli_w:
9601 case Intrinsic::x86_mmx_pslli_d:
9602 case Intrinsic::x86_mmx_pslli_q:
9603 case Intrinsic::x86_mmx_psrli_w:
9604 case Intrinsic::x86_mmx_psrli_d:
9605 case Intrinsic::x86_mmx_psrli_q:
9606 case Intrinsic::x86_mmx_psrai_w:
9607 case Intrinsic::x86_mmx_psrai_d: {
9608 SDValue ShAmt = Op.getOperand(2);
9609 if (isa<ConstantSDNode>(ShAmt))
9612 unsigned NewIntNo = 0;
9614 case Intrinsic::x86_mmx_pslli_w:
9615 NewIntNo = Intrinsic::x86_mmx_psll_w;
9617 case Intrinsic::x86_mmx_pslli_d:
9618 NewIntNo = Intrinsic::x86_mmx_psll_d;
9620 case Intrinsic::x86_mmx_pslli_q:
9621 NewIntNo = Intrinsic::x86_mmx_psll_q;
9623 case Intrinsic::x86_mmx_psrli_w:
9624 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9626 case Intrinsic::x86_mmx_psrli_d:
9627 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9629 case Intrinsic::x86_mmx_psrli_q:
9630 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9632 case Intrinsic::x86_mmx_psrai_w:
9633 NewIntNo = Intrinsic::x86_mmx_psra_w;
9635 case Intrinsic::x86_mmx_psrai_d:
9636 NewIntNo = Intrinsic::x86_mmx_psra_d;
9638 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9641 // The vector shift intrinsics with scalars uses 32b shift amounts but
9642 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9644 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9645 DAG.getConstant(0, MVT::i32));
9646 // FIXME this must be lowered to get rid of the invalid type.
9648 EVT VT = Op.getValueType();
9649 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9650 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9651 DAG.getConstant(NewIntNo, MVT::i32),
9652 Op.getOperand(1), ShAmt);
9657 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9658 SelectionDAG &DAG) const {
9659 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9660 MFI->setReturnAddressIsTaken(true);
9662 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9663 DebugLoc dl = Op.getDebugLoc();
9666 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9668 DAG.getConstant(TD->getPointerSize(),
9669 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9670 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9671 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9673 MachinePointerInfo(), false, false, false, 0);
9676 // Just load the return address.
9677 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9678 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9679 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9682 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9683 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9684 MFI->setFrameAddressIsTaken(true);
9686 EVT VT = Op.getValueType();
9687 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9688 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9689 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9690 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9692 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9693 MachinePointerInfo(),
9694 false, false, false, 0);
9698 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9699 SelectionDAG &DAG) const {
9700 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9703 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9704 MachineFunction &MF = DAG.getMachineFunction();
9705 SDValue Chain = Op.getOperand(0);
9706 SDValue Offset = Op.getOperand(1);
9707 SDValue Handler = Op.getOperand(2);
9708 DebugLoc dl = Op.getDebugLoc();
9710 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9711 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9713 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9715 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9716 DAG.getIntPtrConstant(TD->getPointerSize()));
9717 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9718 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9720 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9721 MF.getRegInfo().addLiveOut(StoreAddrReg);
9723 return DAG.getNode(X86ISD::EH_RETURN, dl,
9725 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9728 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9729 SelectionDAG &DAG) const {
9730 return Op.getOperand(0);
9733 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9734 SelectionDAG &DAG) const {
9735 SDValue Root = Op.getOperand(0);
9736 SDValue Trmp = Op.getOperand(1); // trampoline
9737 SDValue FPtr = Op.getOperand(2); // nested function
9738 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9739 DebugLoc dl = Op.getDebugLoc();
9741 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9743 if (Subtarget->is64Bit()) {
9744 SDValue OutChains[6];
9746 // Large code-model.
9747 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9748 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9750 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9751 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9753 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9755 // Load the pointer to the nested function into R11.
9756 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9757 SDValue Addr = Trmp;
9758 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9759 Addr, MachinePointerInfo(TrmpAddr),
9762 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9763 DAG.getConstant(2, MVT::i64));
9764 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9765 MachinePointerInfo(TrmpAddr, 2),
9768 // Load the 'nest' parameter value into R10.
9769 // R10 is specified in X86CallingConv.td
9770 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9771 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9772 DAG.getConstant(10, MVT::i64));
9773 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9774 Addr, MachinePointerInfo(TrmpAddr, 10),
9777 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9778 DAG.getConstant(12, MVT::i64));
9779 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9780 MachinePointerInfo(TrmpAddr, 12),
9783 // Jump to the nested function.
9784 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9785 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9786 DAG.getConstant(20, MVT::i64));
9787 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9788 Addr, MachinePointerInfo(TrmpAddr, 20),
9791 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9792 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9793 DAG.getConstant(22, MVT::i64));
9794 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9795 MachinePointerInfo(TrmpAddr, 22),
9798 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9800 const Function *Func =
9801 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9802 CallingConv::ID CC = Func->getCallingConv();
9807 llvm_unreachable("Unsupported calling convention");
9808 case CallingConv::C:
9809 case CallingConv::X86_StdCall: {
9810 // Pass 'nest' parameter in ECX.
9811 // Must be kept in sync with X86CallingConv.td
9814 // Check that ECX wasn't needed by an 'inreg' parameter.
9815 FunctionType *FTy = Func->getFunctionType();
9816 const AttrListPtr &Attrs = Func->getAttributes();
9818 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9819 unsigned InRegCount = 0;
9822 for (FunctionType::param_iterator I = FTy->param_begin(),
9823 E = FTy->param_end(); I != E; ++I, ++Idx)
9824 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9825 // FIXME: should only count parameters that are lowered to integers.
9826 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9828 if (InRegCount > 2) {
9829 report_fatal_error("Nest register in use - reduce number of inreg"
9835 case CallingConv::X86_FastCall:
9836 case CallingConv::X86_ThisCall:
9837 case CallingConv::Fast:
9838 // Pass 'nest' parameter in EAX.
9839 // Must be kept in sync with X86CallingConv.td
9844 SDValue OutChains[4];
9847 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9848 DAG.getConstant(10, MVT::i32));
9849 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9851 // This is storing the opcode for MOV32ri.
9852 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9853 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9854 OutChains[0] = DAG.getStore(Root, dl,
9855 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9856 Trmp, MachinePointerInfo(TrmpAddr),
9859 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9860 DAG.getConstant(1, MVT::i32));
9861 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9862 MachinePointerInfo(TrmpAddr, 1),
9865 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9866 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9867 DAG.getConstant(5, MVT::i32));
9868 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9869 MachinePointerInfo(TrmpAddr, 5),
9872 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9873 DAG.getConstant(6, MVT::i32));
9874 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9875 MachinePointerInfo(TrmpAddr, 6),
9878 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9882 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9883 SelectionDAG &DAG) const {
9885 The rounding mode is in bits 11:10 of FPSR, and has the following
9892 FLT_ROUNDS, on the other hand, expects the following:
9899 To perform the conversion, we do:
9900 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9903 MachineFunction &MF = DAG.getMachineFunction();
9904 const TargetMachine &TM = MF.getTarget();
9905 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9906 unsigned StackAlignment = TFI.getStackAlignment();
9907 EVT VT = Op.getValueType();
9908 DebugLoc DL = Op.getDebugLoc();
9910 // Save FP Control Word to stack slot
9911 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9912 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9915 MachineMemOperand *MMO =
9916 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9917 MachineMemOperand::MOStore, 2, 2);
9919 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9920 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9921 DAG.getVTList(MVT::Other),
9922 Ops, 2, MVT::i16, MMO);
9924 // Load FP Control Word from stack slot
9925 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9926 MachinePointerInfo(), false, false, false, 0);
9928 // Transform as necessary
9930 DAG.getNode(ISD::SRL, DL, MVT::i16,
9931 DAG.getNode(ISD::AND, DL, MVT::i16,
9932 CWD, DAG.getConstant(0x800, MVT::i16)),
9933 DAG.getConstant(11, MVT::i8));
9935 DAG.getNode(ISD::SRL, DL, MVT::i16,
9936 DAG.getNode(ISD::AND, DL, MVT::i16,
9937 CWD, DAG.getConstant(0x400, MVT::i16)),
9938 DAG.getConstant(9, MVT::i8));
9941 DAG.getNode(ISD::AND, DL, MVT::i16,
9942 DAG.getNode(ISD::ADD, DL, MVT::i16,
9943 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9944 DAG.getConstant(1, MVT::i16)),
9945 DAG.getConstant(3, MVT::i16));
9948 return DAG.getNode((VT.getSizeInBits() < 16 ?
9949 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9952 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9953 EVT VT = Op.getValueType();
9955 unsigned NumBits = VT.getSizeInBits();
9956 DebugLoc dl = Op.getDebugLoc();
9958 Op = Op.getOperand(0);
9959 if (VT == MVT::i8) {
9960 // Zero extend to i32 since there is not an i8 bsr.
9962 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9965 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9966 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9967 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9969 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9972 DAG.getConstant(NumBits+NumBits-1, OpVT),
9973 DAG.getConstant(X86::COND_E, MVT::i8),
9976 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9978 // Finally xor with NumBits-1.
9979 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9982 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9986 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
9987 SelectionDAG &DAG) const {
9988 EVT VT = Op.getValueType();
9990 unsigned NumBits = VT.getSizeInBits();
9991 DebugLoc dl = Op.getDebugLoc();
9993 Op = Op.getOperand(0);
9994 if (VT == MVT::i8) {
9995 // Zero extend to i32 since there is not an i8 bsr.
9997 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10000 // Issue a bsr (scan bits in reverse).
10001 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10002 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10004 // And xor with NumBits-1.
10005 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10008 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10012 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10013 EVT VT = Op.getValueType();
10014 unsigned NumBits = VT.getSizeInBits();
10015 DebugLoc dl = Op.getDebugLoc();
10016 Op = Op.getOperand(0);
10018 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10019 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10020 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10022 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10025 DAG.getConstant(NumBits, VT),
10026 DAG.getConstant(X86::COND_E, MVT::i8),
10029 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10032 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10033 // ones, and then concatenate the result back.
10034 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10035 EVT VT = Op.getValueType();
10037 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10038 "Unsupported value type for operation");
10040 int NumElems = VT.getVectorNumElements();
10041 DebugLoc dl = Op.getDebugLoc();
10042 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10043 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10045 // Extract the LHS vectors
10046 SDValue LHS = Op.getOperand(0);
10047 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10048 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10050 // Extract the RHS vectors
10051 SDValue RHS = Op.getOperand(1);
10052 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10053 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10055 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10056 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10058 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10059 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10060 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10063 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10064 assert(Op.getValueType().getSizeInBits() == 256 &&
10065 Op.getValueType().isInteger() &&
10066 "Only handle AVX 256-bit vector integer operation");
10067 return Lower256IntArith(Op, DAG);
10070 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10071 assert(Op.getValueType().getSizeInBits() == 256 &&
10072 Op.getValueType().isInteger() &&
10073 "Only handle AVX 256-bit vector integer operation");
10074 return Lower256IntArith(Op, DAG);
10077 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10078 EVT VT = Op.getValueType();
10080 // Decompose 256-bit ops into smaller 128-bit ops.
10081 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10082 return Lower256IntArith(Op, DAG);
10084 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10085 "Only know how to lower V2I64/V4I64 multiply");
10087 DebugLoc dl = Op.getDebugLoc();
10089 // Ahi = psrlqi(a, 32);
10090 // Bhi = psrlqi(b, 32);
10092 // AloBlo = pmuludq(a, b);
10093 // AloBhi = pmuludq(a, Bhi);
10094 // AhiBlo = pmuludq(Ahi, b);
10096 // AloBhi = psllqi(AloBhi, 32);
10097 // AhiBlo = psllqi(AhiBlo, 32);
10098 // return AloBlo + AloBhi + AhiBlo;
10100 SDValue A = Op.getOperand(0);
10101 SDValue B = Op.getOperand(1);
10103 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10105 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10106 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10108 // Bit cast to 32-bit vectors for MULUDQ
10109 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10110 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10111 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10112 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10113 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10115 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10116 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10117 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10119 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10120 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10122 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10123 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10126 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10128 EVT VT = Op.getValueType();
10129 DebugLoc dl = Op.getDebugLoc();
10130 SDValue R = Op.getOperand(0);
10131 SDValue Amt = Op.getOperand(1);
10132 LLVMContext *Context = DAG.getContext();
10134 if (!Subtarget->hasSSE2())
10137 // Optimize shl/srl/sra with constant shift amount.
10138 if (isSplatVector(Amt.getNode())) {
10139 SDValue SclrAmt = Amt->getOperand(0);
10140 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10141 uint64_t ShiftAmt = C->getZExtValue();
10143 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10144 (Subtarget->hasAVX2() &&
10145 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10146 if (Op.getOpcode() == ISD::SHL)
10147 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10148 DAG.getConstant(ShiftAmt, MVT::i32));
10149 if (Op.getOpcode() == ISD::SRL)
10150 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10151 DAG.getConstant(ShiftAmt, MVT::i32));
10152 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10153 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10154 DAG.getConstant(ShiftAmt, MVT::i32));
10157 if (VT == MVT::v16i8) {
10158 if (Op.getOpcode() == ISD::SHL) {
10159 // Make a large shift.
10160 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10161 DAG.getConstant(ShiftAmt, MVT::i32));
10162 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10163 // Zero out the rightmost bits.
10164 SmallVector<SDValue, 16> V(16,
10165 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10167 return DAG.getNode(ISD::AND, dl, VT, SHL,
10168 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10170 if (Op.getOpcode() == ISD::SRL) {
10171 // Make a large shift.
10172 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10173 DAG.getConstant(ShiftAmt, MVT::i32));
10174 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10175 // Zero out the leftmost bits.
10176 SmallVector<SDValue, 16> V(16,
10177 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10179 return DAG.getNode(ISD::AND, dl, VT, SRL,
10180 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10182 if (Op.getOpcode() == ISD::SRA) {
10183 if (ShiftAmt == 7) {
10184 // R s>> 7 === R s< 0
10185 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10186 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10189 // R s>> a === ((R u>> a) ^ m) - m
10190 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10191 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10193 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10194 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10195 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10200 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10201 if (Op.getOpcode() == ISD::SHL) {
10202 // Make a large shift.
10203 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10204 DAG.getConstant(ShiftAmt, MVT::i32));
10205 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10206 // Zero out the rightmost bits.
10207 SmallVector<SDValue, 32> V(32,
10208 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10210 return DAG.getNode(ISD::AND, dl, VT, SHL,
10211 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10213 if (Op.getOpcode() == ISD::SRL) {
10214 // Make a large shift.
10215 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10216 DAG.getConstant(ShiftAmt, MVT::i32));
10217 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10218 // Zero out the leftmost bits.
10219 SmallVector<SDValue, 32> V(32,
10220 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10222 return DAG.getNode(ISD::AND, dl, VT, SRL,
10223 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10225 if (Op.getOpcode() == ISD::SRA) {
10226 if (ShiftAmt == 7) {
10227 // R s>> 7 === R s< 0
10228 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10229 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10232 // R s>> a === ((R u>> a) ^ m) - m
10233 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10234 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10236 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10237 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10238 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10245 // Lower SHL with variable shift amount.
10246 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10247 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10248 DAG.getConstant(23, MVT::i32));
10250 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10251 Constant *C = ConstantDataVector::get(*Context, CV);
10252 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10253 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10254 MachinePointerInfo::getConstantPool(),
10255 false, false, false, 16);
10257 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10258 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10259 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10260 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10262 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10263 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10266 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10267 DAG.getConstant(5, MVT::i32));
10268 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10270 // Turn 'a' into a mask suitable for VSELECT
10271 SDValue VSelM = DAG.getConstant(0x80, VT);
10272 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10273 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10275 SDValue CM1 = DAG.getConstant(0x0f, VT);
10276 SDValue CM2 = DAG.getConstant(0x3f, VT);
10278 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10279 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10280 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10281 DAG.getConstant(4, MVT::i32), DAG);
10282 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10283 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10286 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10287 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10288 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10290 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10291 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10292 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10293 DAG.getConstant(2, MVT::i32), DAG);
10294 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10295 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10298 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10299 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10300 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10302 // return VSELECT(r, r+r, a);
10303 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10304 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10308 // Decompose 256-bit shifts into smaller 128-bit shifts.
10309 if (VT.getSizeInBits() == 256) {
10310 unsigned NumElems = VT.getVectorNumElements();
10311 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10312 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10314 // Extract the two vectors
10315 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10316 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10319 // Recreate the shift amount vectors
10320 SDValue Amt1, Amt2;
10321 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10322 // Constant shift amount
10323 SmallVector<SDValue, 4> Amt1Csts;
10324 SmallVector<SDValue, 4> Amt2Csts;
10325 for (unsigned i = 0; i != NumElems/2; ++i)
10326 Amt1Csts.push_back(Amt->getOperand(i));
10327 for (unsigned i = NumElems/2; i != NumElems; ++i)
10328 Amt2Csts.push_back(Amt->getOperand(i));
10330 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10331 &Amt1Csts[0], NumElems/2);
10332 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10333 &Amt2Csts[0], NumElems/2);
10335 // Variable shift amount
10336 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10337 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10341 // Issue new vector shifts for the smaller types
10342 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10343 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10345 // Concatenate the result back
10346 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10352 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10353 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10354 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10355 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10356 // has only one use.
10357 SDNode *N = Op.getNode();
10358 SDValue LHS = N->getOperand(0);
10359 SDValue RHS = N->getOperand(1);
10360 unsigned BaseOp = 0;
10362 DebugLoc DL = Op.getDebugLoc();
10363 switch (Op.getOpcode()) {
10364 default: llvm_unreachable("Unknown ovf instruction!");
10366 // A subtract of one will be selected as a INC. Note that INC doesn't
10367 // set CF, so we can't do this for UADDO.
10368 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10370 BaseOp = X86ISD::INC;
10371 Cond = X86::COND_O;
10374 BaseOp = X86ISD::ADD;
10375 Cond = X86::COND_O;
10378 BaseOp = X86ISD::ADD;
10379 Cond = X86::COND_B;
10382 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10383 // set CF, so we can't do this for USUBO.
10384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10386 BaseOp = X86ISD::DEC;
10387 Cond = X86::COND_O;
10390 BaseOp = X86ISD::SUB;
10391 Cond = X86::COND_O;
10394 BaseOp = X86ISD::SUB;
10395 Cond = X86::COND_B;
10398 BaseOp = X86ISD::SMUL;
10399 Cond = X86::COND_O;
10401 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10402 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10404 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10407 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10408 DAG.getConstant(X86::COND_O, MVT::i32),
10409 SDValue(Sum.getNode(), 2));
10411 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10415 // Also sets EFLAGS.
10416 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10417 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10420 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10421 DAG.getConstant(Cond, MVT::i32),
10422 SDValue(Sum.getNode(), 1));
10424 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10427 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10428 SelectionDAG &DAG) const {
10429 DebugLoc dl = Op.getDebugLoc();
10430 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10431 EVT VT = Op.getValueType();
10433 if (!Subtarget->hasSSE2() || !VT.isVector())
10436 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10437 ExtraVT.getScalarType().getSizeInBits();
10438 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10440 switch (VT.getSimpleVT().SimpleTy) {
10441 default: return SDValue();
10444 if (!Subtarget->hasAVX())
10446 if (!Subtarget->hasAVX2()) {
10447 // needs to be split
10448 int NumElems = VT.getVectorNumElements();
10449 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10450 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10452 // Extract the LHS vectors
10453 SDValue LHS = Op.getOperand(0);
10454 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10455 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10457 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10458 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10460 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10461 int ExtraNumElems = ExtraVT.getVectorNumElements();
10462 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10464 SDValue Extra = DAG.getValueType(ExtraVT);
10466 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10467 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10469 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10474 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10475 Op.getOperand(0), ShAmt, DAG);
10476 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10482 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10483 DebugLoc dl = Op.getDebugLoc();
10485 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10486 // There isn't any reason to disable it if the target processor supports it.
10487 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10488 SDValue Chain = Op.getOperand(0);
10489 SDValue Zero = DAG.getConstant(0, MVT::i32);
10491 DAG.getRegister(X86::ESP, MVT::i32), // Base
10492 DAG.getTargetConstant(1, MVT::i8), // Scale
10493 DAG.getRegister(0, MVT::i32), // Index
10494 DAG.getTargetConstant(0, MVT::i32), // Disp
10495 DAG.getRegister(0, MVT::i32), // Segment.
10500 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10501 array_lengthof(Ops));
10502 return SDValue(Res, 0);
10505 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10507 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10509 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10510 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10511 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10512 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10514 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10515 if (!Op1 && !Op2 && !Op3 && Op4)
10516 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10518 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10519 if (Op1 && !Op2 && !Op3 && !Op4)
10520 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10522 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10524 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10527 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10528 SelectionDAG &DAG) const {
10529 DebugLoc dl = Op.getDebugLoc();
10530 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10531 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10532 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10533 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10535 // The only fence that needs an instruction is a sequentially-consistent
10536 // cross-thread fence.
10537 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10538 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10539 // no-sse2). There isn't any reason to disable it if the target processor
10541 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10542 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10544 SDValue Chain = Op.getOperand(0);
10545 SDValue Zero = DAG.getConstant(0, MVT::i32);
10547 DAG.getRegister(X86::ESP, MVT::i32), // Base
10548 DAG.getTargetConstant(1, MVT::i8), // Scale
10549 DAG.getRegister(0, MVT::i32), // Index
10550 DAG.getTargetConstant(0, MVT::i32), // Disp
10551 DAG.getRegister(0, MVT::i32), // Segment.
10556 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10557 array_lengthof(Ops));
10558 return SDValue(Res, 0);
10561 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10562 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10566 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10567 EVT T = Op.getValueType();
10568 DebugLoc DL = Op.getDebugLoc();
10571 switch(T.getSimpleVT().SimpleTy) {
10572 default: llvm_unreachable("Invalid value type!");
10573 case MVT::i8: Reg = X86::AL; size = 1; break;
10574 case MVT::i16: Reg = X86::AX; size = 2; break;
10575 case MVT::i32: Reg = X86::EAX; size = 4; break;
10577 assert(Subtarget->is64Bit() && "Node not type legal!");
10578 Reg = X86::RAX; size = 8;
10581 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10582 Op.getOperand(2), SDValue());
10583 SDValue Ops[] = { cpIn.getValue(0),
10586 DAG.getTargetConstant(size, MVT::i8),
10587 cpIn.getValue(1) };
10588 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10589 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10590 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10593 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10597 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10598 SelectionDAG &DAG) const {
10599 assert(Subtarget->is64Bit() && "Result not type legalized?");
10600 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10601 SDValue TheChain = Op.getOperand(0);
10602 DebugLoc dl = Op.getDebugLoc();
10603 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10604 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10605 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10607 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10608 DAG.getConstant(32, MVT::i8));
10610 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10613 return DAG.getMergeValues(Ops, 2, dl);
10616 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10617 SelectionDAG &DAG) const {
10618 EVT SrcVT = Op.getOperand(0).getValueType();
10619 EVT DstVT = Op.getValueType();
10620 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10621 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10622 assert((DstVT == MVT::i64 ||
10623 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10624 "Unexpected custom BITCAST");
10625 // i64 <=> MMX conversions are Legal.
10626 if (SrcVT==MVT::i64 && DstVT.isVector())
10628 if (DstVT==MVT::i64 && SrcVT.isVector())
10630 // MMX <=> MMX conversions are Legal.
10631 if (SrcVT.isVector() && DstVT.isVector())
10633 // All other conversions need to be expanded.
10637 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10638 SDNode *Node = Op.getNode();
10639 DebugLoc dl = Node->getDebugLoc();
10640 EVT T = Node->getValueType(0);
10641 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10642 DAG.getConstant(0, T), Node->getOperand(2));
10643 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10644 cast<AtomicSDNode>(Node)->getMemoryVT(),
10645 Node->getOperand(0),
10646 Node->getOperand(1), negOp,
10647 cast<AtomicSDNode>(Node)->getSrcValue(),
10648 cast<AtomicSDNode>(Node)->getAlignment(),
10649 cast<AtomicSDNode>(Node)->getOrdering(),
10650 cast<AtomicSDNode>(Node)->getSynchScope());
10653 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10654 SDNode *Node = Op.getNode();
10655 DebugLoc dl = Node->getDebugLoc();
10656 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10658 // Convert seq_cst store -> xchg
10659 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10660 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10661 // (The only way to get a 16-byte store is cmpxchg16b)
10662 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10663 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10664 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10665 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10666 cast<AtomicSDNode>(Node)->getMemoryVT(),
10667 Node->getOperand(0),
10668 Node->getOperand(1), Node->getOperand(2),
10669 cast<AtomicSDNode>(Node)->getMemOperand(),
10670 cast<AtomicSDNode>(Node)->getOrdering(),
10671 cast<AtomicSDNode>(Node)->getSynchScope());
10672 return Swap.getValue(1);
10674 // Other atomic stores have a simple pattern.
10678 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10679 EVT VT = Op.getNode()->getValueType(0);
10681 // Let legalize expand this if it isn't a legal type yet.
10682 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10685 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10688 bool ExtraOp = false;
10689 switch (Op.getOpcode()) {
10690 default: llvm_unreachable("Invalid code");
10691 case ISD::ADDC: Opc = X86ISD::ADD; break;
10692 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10693 case ISD::SUBC: Opc = X86ISD::SUB; break;
10694 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10698 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10700 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10701 Op.getOperand(1), Op.getOperand(2));
10704 /// LowerOperation - Provide custom lowering hooks for some operations.
10706 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10707 switch (Op.getOpcode()) {
10708 default: llvm_unreachable("Should not custom lower this!");
10709 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10710 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10711 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10712 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10713 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10714 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10715 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10716 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10717 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10718 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10719 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10720 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10721 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10722 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10723 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10724 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10725 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10726 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10727 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10728 case ISD::SHL_PARTS:
10729 case ISD::SRA_PARTS:
10730 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10731 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10732 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10733 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10734 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10735 case ISD::FABS: return LowerFABS(Op, DAG);
10736 case ISD::FNEG: return LowerFNEG(Op, DAG);
10737 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10738 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10739 case ISD::SETCC: return LowerSETCC(Op, DAG);
10740 case ISD::SELECT: return LowerSELECT(Op, DAG);
10741 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10742 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10743 case ISD::VASTART: return LowerVASTART(Op, DAG);
10744 case ISD::VAARG: return LowerVAARG(Op, DAG);
10745 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10746 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10747 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10748 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10749 case ISD::FRAME_TO_ARGS_OFFSET:
10750 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10751 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10752 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10753 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10754 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10755 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10756 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10757 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10758 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10759 case ISD::MUL: return LowerMUL(Op, DAG);
10762 case ISD::SHL: return LowerShift(Op, DAG);
10768 case ISD::UMULO: return LowerXALUO(Op, DAG);
10769 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10770 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10774 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10775 case ISD::ADD: return LowerADD(Op, DAG);
10776 case ISD::SUB: return LowerSUB(Op, DAG);
10780 static void ReplaceATOMIC_LOAD(SDNode *Node,
10781 SmallVectorImpl<SDValue> &Results,
10782 SelectionDAG &DAG) {
10783 DebugLoc dl = Node->getDebugLoc();
10784 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10786 // Convert wide load -> cmpxchg8b/cmpxchg16b
10787 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10788 // (The only way to get a 16-byte load is cmpxchg16b)
10789 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10790 SDValue Zero = DAG.getConstant(0, VT);
10791 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10792 Node->getOperand(0),
10793 Node->getOperand(1), Zero, Zero,
10794 cast<AtomicSDNode>(Node)->getMemOperand(),
10795 cast<AtomicSDNode>(Node)->getOrdering(),
10796 cast<AtomicSDNode>(Node)->getSynchScope());
10797 Results.push_back(Swap.getValue(0));
10798 Results.push_back(Swap.getValue(1));
10801 void X86TargetLowering::
10802 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10803 SelectionDAG &DAG, unsigned NewOp) const {
10804 DebugLoc dl = Node->getDebugLoc();
10805 assert (Node->getValueType(0) == MVT::i64 &&
10806 "Only know how to expand i64 atomics");
10808 SDValue Chain = Node->getOperand(0);
10809 SDValue In1 = Node->getOperand(1);
10810 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10811 Node->getOperand(2), DAG.getIntPtrConstant(0));
10812 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10813 Node->getOperand(2), DAG.getIntPtrConstant(1));
10814 SDValue Ops[] = { Chain, In1, In2L, In2H };
10815 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10817 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10818 cast<MemSDNode>(Node)->getMemOperand());
10819 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10820 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10821 Results.push_back(Result.getValue(2));
10824 /// ReplaceNodeResults - Replace a node with an illegal result type
10825 /// with a new node built out of custom code.
10826 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10827 SmallVectorImpl<SDValue>&Results,
10828 SelectionDAG &DAG) const {
10829 DebugLoc dl = N->getDebugLoc();
10830 switch (N->getOpcode()) {
10832 llvm_unreachable("Do not know how to custom type legalize this operation!");
10833 case ISD::SIGN_EXTEND_INREG:
10838 // We don't want to expand or promote these.
10840 case ISD::FP_TO_SINT: {
10841 std::pair<SDValue,SDValue> Vals =
10842 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10843 SDValue FIST = Vals.first, StackSlot = Vals.second;
10844 if (FIST.getNode() != 0) {
10845 EVT VT = N->getValueType(0);
10846 // Return a load from the stack slot.
10847 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10848 MachinePointerInfo(),
10849 false, false, false, 0));
10853 case ISD::READCYCLECOUNTER: {
10854 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10855 SDValue TheChain = N->getOperand(0);
10856 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10857 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10859 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10861 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10862 SDValue Ops[] = { eax, edx };
10863 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10864 Results.push_back(edx.getValue(1));
10867 case ISD::ATOMIC_CMP_SWAP: {
10868 EVT T = N->getValueType(0);
10869 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10870 bool Regs64bit = T == MVT::i128;
10871 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10872 SDValue cpInL, cpInH;
10873 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10874 DAG.getConstant(0, HalfT));
10875 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10876 DAG.getConstant(1, HalfT));
10877 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10878 Regs64bit ? X86::RAX : X86::EAX,
10880 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10881 Regs64bit ? X86::RDX : X86::EDX,
10882 cpInH, cpInL.getValue(1));
10883 SDValue swapInL, swapInH;
10884 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10885 DAG.getConstant(0, HalfT));
10886 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10887 DAG.getConstant(1, HalfT));
10888 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10889 Regs64bit ? X86::RBX : X86::EBX,
10890 swapInL, cpInH.getValue(1));
10891 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10892 Regs64bit ? X86::RCX : X86::ECX,
10893 swapInH, swapInL.getValue(1));
10894 SDValue Ops[] = { swapInH.getValue(0),
10896 swapInH.getValue(1) };
10897 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10898 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10899 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10900 X86ISD::LCMPXCHG8_DAG;
10901 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10903 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10904 Regs64bit ? X86::RAX : X86::EAX,
10905 HalfT, Result.getValue(1));
10906 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10907 Regs64bit ? X86::RDX : X86::EDX,
10908 HalfT, cpOutL.getValue(2));
10909 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10910 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10911 Results.push_back(cpOutH.getValue(1));
10914 case ISD::ATOMIC_LOAD_ADD:
10915 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10917 case ISD::ATOMIC_LOAD_AND:
10918 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10920 case ISD::ATOMIC_LOAD_NAND:
10921 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10923 case ISD::ATOMIC_LOAD_OR:
10924 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10926 case ISD::ATOMIC_LOAD_SUB:
10927 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10929 case ISD::ATOMIC_LOAD_XOR:
10930 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10932 case ISD::ATOMIC_SWAP:
10933 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10935 case ISD::ATOMIC_LOAD:
10936 ReplaceATOMIC_LOAD(N, Results, DAG);
10940 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10942 default: return NULL;
10943 case X86ISD::BSF: return "X86ISD::BSF";
10944 case X86ISD::BSR: return "X86ISD::BSR";
10945 case X86ISD::SHLD: return "X86ISD::SHLD";
10946 case X86ISD::SHRD: return "X86ISD::SHRD";
10947 case X86ISD::FAND: return "X86ISD::FAND";
10948 case X86ISD::FOR: return "X86ISD::FOR";
10949 case X86ISD::FXOR: return "X86ISD::FXOR";
10950 case X86ISD::FSRL: return "X86ISD::FSRL";
10951 case X86ISD::FILD: return "X86ISD::FILD";
10952 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10953 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10954 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10955 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10956 case X86ISD::FLD: return "X86ISD::FLD";
10957 case X86ISD::FST: return "X86ISD::FST";
10958 case X86ISD::CALL: return "X86ISD::CALL";
10959 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10960 case X86ISD::BT: return "X86ISD::BT";
10961 case X86ISD::CMP: return "X86ISD::CMP";
10962 case X86ISD::COMI: return "X86ISD::COMI";
10963 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10964 case X86ISD::SETCC: return "X86ISD::SETCC";
10965 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10966 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10967 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10968 case X86ISD::CMOV: return "X86ISD::CMOV";
10969 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10970 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10971 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10972 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10973 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10974 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10975 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10976 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10977 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10978 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10979 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10980 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10981 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10982 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10983 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10984 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10985 case X86ISD::HADD: return "X86ISD::HADD";
10986 case X86ISD::HSUB: return "X86ISD::HSUB";
10987 case X86ISD::FHADD: return "X86ISD::FHADD";
10988 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10989 case X86ISD::FMAX: return "X86ISD::FMAX";
10990 case X86ISD::FMIN: return "X86ISD::FMIN";
10991 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10992 case X86ISD::FRCP: return "X86ISD::FRCP";
10993 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10994 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10995 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10996 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10997 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10998 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10999 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11000 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11001 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11002 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11003 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11004 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11005 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11006 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11007 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11008 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11009 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11010 case X86ISD::VSHL: return "X86ISD::VSHL";
11011 case X86ISD::VSRL: return "X86ISD::VSRL";
11012 case X86ISD::VSRA: return "X86ISD::VSRA";
11013 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11014 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11015 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11016 case X86ISD::CMPP: return "X86ISD::CMPP";
11017 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11018 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11019 case X86ISD::ADD: return "X86ISD::ADD";
11020 case X86ISD::SUB: return "X86ISD::SUB";
11021 case X86ISD::ADC: return "X86ISD::ADC";
11022 case X86ISD::SBB: return "X86ISD::SBB";
11023 case X86ISD::SMUL: return "X86ISD::SMUL";
11024 case X86ISD::UMUL: return "X86ISD::UMUL";
11025 case X86ISD::INC: return "X86ISD::INC";
11026 case X86ISD::DEC: return "X86ISD::DEC";
11027 case X86ISD::OR: return "X86ISD::OR";
11028 case X86ISD::XOR: return "X86ISD::XOR";
11029 case X86ISD::AND: return "X86ISD::AND";
11030 case X86ISD::ANDN: return "X86ISD::ANDN";
11031 case X86ISD::BLSI: return "X86ISD::BLSI";
11032 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11033 case X86ISD::BLSR: return "X86ISD::BLSR";
11034 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11035 case X86ISD::PTEST: return "X86ISD::PTEST";
11036 case X86ISD::TESTP: return "X86ISD::TESTP";
11037 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11038 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11039 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11040 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11041 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11042 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11043 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11044 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11045 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11046 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11047 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11048 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11049 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11050 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11051 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11052 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11053 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11054 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11055 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11056 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11057 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11058 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11059 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11060 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11061 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11062 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11066 // isLegalAddressingMode - Return true if the addressing mode represented
11067 // by AM is legal for this target, for a load/store of the specified type.
11068 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11070 // X86 supports extremely general addressing modes.
11071 CodeModel::Model M = getTargetMachine().getCodeModel();
11072 Reloc::Model R = getTargetMachine().getRelocationModel();
11074 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11075 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11080 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11082 // If a reference to this global requires an extra load, we can't fold it.
11083 if (isGlobalStubReference(GVFlags))
11086 // If BaseGV requires a register for the PIC base, we cannot also have a
11087 // BaseReg specified.
11088 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11091 // If lower 4G is not available, then we must use rip-relative addressing.
11092 if ((M != CodeModel::Small || R != Reloc::Static) &&
11093 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11097 switch (AM.Scale) {
11103 // These scales always work.
11108 // These scales are formed with basereg+scalereg. Only accept if there is
11113 default: // Other stuff never works.
11121 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11122 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11124 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11125 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11126 if (NumBits1 <= NumBits2)
11131 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11132 if (!VT1.isInteger() || !VT2.isInteger())
11134 unsigned NumBits1 = VT1.getSizeInBits();
11135 unsigned NumBits2 = VT2.getSizeInBits();
11136 if (NumBits1 <= NumBits2)
11141 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11142 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11143 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11146 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11147 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11148 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11151 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11152 // i16 instructions are longer (0x66 prefix) and potentially slower.
11153 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11156 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11157 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11158 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11159 /// are assumed to be legal.
11161 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11163 // Very little shuffling can be done for 64-bit vectors right now.
11164 if (VT.getSizeInBits() == 64)
11167 // FIXME: pshufb, blends, shifts.
11168 return (VT.getVectorNumElements() == 2 ||
11169 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11170 isMOVLMask(M, VT) ||
11171 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11172 isPSHUFDMask(M, VT) ||
11173 isPSHUFHWMask(M, VT) ||
11174 isPSHUFLWMask(M, VT) ||
11175 isPALIGNRMask(M, VT, Subtarget) ||
11176 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11177 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11178 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11179 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11183 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11185 unsigned NumElts = VT.getVectorNumElements();
11186 // FIXME: This collection of masks seems suspect.
11189 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11190 return (isMOVLMask(Mask, VT) ||
11191 isCommutedMOVLMask(Mask, VT, true) ||
11192 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11193 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11198 //===----------------------------------------------------------------------===//
11199 // X86 Scheduler Hooks
11200 //===----------------------------------------------------------------------===//
11202 // private utility function
11203 MachineBasicBlock *
11204 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11205 MachineBasicBlock *MBB,
11212 TargetRegisterClass *RC,
11213 bool invSrc) const {
11214 // For the atomic bitwise operator, we generate
11217 // ld t1 = [bitinstr.addr]
11218 // op t2 = t1, [bitinstr.val]
11220 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11222 // fallthrough -->nextMBB
11223 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11224 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11225 MachineFunction::iterator MBBIter = MBB;
11228 /// First build the CFG
11229 MachineFunction *F = MBB->getParent();
11230 MachineBasicBlock *thisMBB = MBB;
11231 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11232 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11233 F->insert(MBBIter, newMBB);
11234 F->insert(MBBIter, nextMBB);
11236 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11237 nextMBB->splice(nextMBB->begin(), thisMBB,
11238 llvm::next(MachineBasicBlock::iterator(bInstr)),
11240 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11242 // Update thisMBB to fall through to newMBB
11243 thisMBB->addSuccessor(newMBB);
11245 // newMBB jumps to itself and fall through to nextMBB
11246 newMBB->addSuccessor(nextMBB);
11247 newMBB->addSuccessor(newMBB);
11249 // Insert instructions into newMBB based on incoming instruction
11250 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11251 "unexpected number of operands");
11252 DebugLoc dl = bInstr->getDebugLoc();
11253 MachineOperand& destOper = bInstr->getOperand(0);
11254 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11255 int numArgs = bInstr->getNumOperands() - 1;
11256 for (int i=0; i < numArgs; ++i)
11257 argOpers[i] = &bInstr->getOperand(i+1);
11259 // x86 address has 4 operands: base, index, scale, and displacement
11260 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11261 int valArgIndx = lastAddrIndx + 1;
11263 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11264 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11265 for (int i=0; i <= lastAddrIndx; ++i)
11266 (*MIB).addOperand(*argOpers[i]);
11268 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11270 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11275 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11276 assert((argOpers[valArgIndx]->isReg() ||
11277 argOpers[valArgIndx]->isImm()) &&
11278 "invalid operand");
11279 if (argOpers[valArgIndx]->isReg())
11280 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11282 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11284 (*MIB).addOperand(*argOpers[valArgIndx]);
11286 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11289 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11290 for (int i=0; i <= lastAddrIndx; ++i)
11291 (*MIB).addOperand(*argOpers[i]);
11293 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11294 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11295 bInstr->memoperands_end());
11297 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11298 MIB.addReg(EAXreg);
11301 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11303 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11307 // private utility function: 64 bit atomics on 32 bit host.
11308 MachineBasicBlock *
11309 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11310 MachineBasicBlock *MBB,
11315 bool invSrc) const {
11316 // For the atomic bitwise operator, we generate
11317 // thisMBB (instructions are in pairs, except cmpxchg8b)
11318 // ld t1,t2 = [bitinstr.addr]
11320 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11321 // op t5, t6 <- out1, out2, [bitinstr.val]
11322 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11323 // mov ECX, EBX <- t5, t6
11324 // mov EAX, EDX <- t1, t2
11325 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11326 // mov t3, t4 <- EAX, EDX
11328 // result in out1, out2
11329 // fallthrough -->nextMBB
11331 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11332 const unsigned LoadOpc = X86::MOV32rm;
11333 const unsigned NotOpc = X86::NOT32r;
11334 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11335 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11336 MachineFunction::iterator MBBIter = MBB;
11339 /// First build the CFG
11340 MachineFunction *F = MBB->getParent();
11341 MachineBasicBlock *thisMBB = MBB;
11342 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11343 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11344 F->insert(MBBIter, newMBB);
11345 F->insert(MBBIter, nextMBB);
11347 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11348 nextMBB->splice(nextMBB->begin(), thisMBB,
11349 llvm::next(MachineBasicBlock::iterator(bInstr)),
11351 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11353 // Update thisMBB to fall through to newMBB
11354 thisMBB->addSuccessor(newMBB);
11356 // newMBB jumps to itself and fall through to nextMBB
11357 newMBB->addSuccessor(nextMBB);
11358 newMBB->addSuccessor(newMBB);
11360 DebugLoc dl = bInstr->getDebugLoc();
11361 // Insert instructions into newMBB based on incoming instruction
11362 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11363 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11364 "unexpected number of operands");
11365 MachineOperand& dest1Oper = bInstr->getOperand(0);
11366 MachineOperand& dest2Oper = bInstr->getOperand(1);
11367 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11368 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11369 argOpers[i] = &bInstr->getOperand(i+2);
11371 // We use some of the operands multiple times, so conservatively just
11372 // clear any kill flags that might be present.
11373 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11374 argOpers[i]->setIsKill(false);
11377 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11378 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11380 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11381 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11382 for (int i=0; i <= lastAddrIndx; ++i)
11383 (*MIB).addOperand(*argOpers[i]);
11384 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11385 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11386 // add 4 to displacement.
11387 for (int i=0; i <= lastAddrIndx-2; ++i)
11388 (*MIB).addOperand(*argOpers[i]);
11389 MachineOperand newOp3 = *(argOpers[3]);
11390 if (newOp3.isImm())
11391 newOp3.setImm(newOp3.getImm()+4);
11393 newOp3.setOffset(newOp3.getOffset()+4);
11394 (*MIB).addOperand(newOp3);
11395 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11397 // t3/4 are defined later, at the bottom of the loop
11398 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11399 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11400 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11401 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11402 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11403 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11405 // The subsequent operations should be using the destination registers of
11406 //the PHI instructions.
11408 t1 = F->getRegInfo().createVirtualRegister(RC);
11409 t2 = F->getRegInfo().createVirtualRegister(RC);
11410 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11411 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11413 t1 = dest1Oper.getReg();
11414 t2 = dest2Oper.getReg();
11417 int valArgIndx = lastAddrIndx + 1;
11418 assert((argOpers[valArgIndx]->isReg() ||
11419 argOpers[valArgIndx]->isImm()) &&
11420 "invalid operand");
11421 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11422 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11423 if (argOpers[valArgIndx]->isReg())
11424 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11426 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11427 if (regOpcL != X86::MOV32rr)
11429 (*MIB).addOperand(*argOpers[valArgIndx]);
11430 assert(argOpers[valArgIndx + 1]->isReg() ==
11431 argOpers[valArgIndx]->isReg());
11432 assert(argOpers[valArgIndx + 1]->isImm() ==
11433 argOpers[valArgIndx]->isImm());
11434 if (argOpers[valArgIndx + 1]->isReg())
11435 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11437 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11438 if (regOpcH != X86::MOV32rr)
11440 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11442 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11444 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11447 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11449 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11452 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11453 for (int i=0; i <= lastAddrIndx; ++i)
11454 (*MIB).addOperand(*argOpers[i]);
11456 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11457 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11458 bInstr->memoperands_end());
11460 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11461 MIB.addReg(X86::EAX);
11462 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11463 MIB.addReg(X86::EDX);
11466 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11468 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11472 // private utility function
11473 MachineBasicBlock *
11474 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11475 MachineBasicBlock *MBB,
11476 unsigned cmovOpc) const {
11477 // For the atomic min/max operator, we generate
11480 // ld t1 = [min/max.addr]
11481 // mov t2 = [min/max.val]
11483 // cmov[cond] t2 = t1
11485 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11487 // fallthrough -->nextMBB
11489 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11490 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11491 MachineFunction::iterator MBBIter = MBB;
11494 /// First build the CFG
11495 MachineFunction *F = MBB->getParent();
11496 MachineBasicBlock *thisMBB = MBB;
11497 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11498 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11499 F->insert(MBBIter, newMBB);
11500 F->insert(MBBIter, nextMBB);
11502 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11503 nextMBB->splice(nextMBB->begin(), thisMBB,
11504 llvm::next(MachineBasicBlock::iterator(mInstr)),
11506 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11508 // Update thisMBB to fall through to newMBB
11509 thisMBB->addSuccessor(newMBB);
11511 // newMBB jumps to newMBB and fall through to nextMBB
11512 newMBB->addSuccessor(nextMBB);
11513 newMBB->addSuccessor(newMBB);
11515 DebugLoc dl = mInstr->getDebugLoc();
11516 // Insert instructions into newMBB based on incoming instruction
11517 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11518 "unexpected number of operands");
11519 MachineOperand& destOper = mInstr->getOperand(0);
11520 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11521 int numArgs = mInstr->getNumOperands() - 1;
11522 for (int i=0; i < numArgs; ++i)
11523 argOpers[i] = &mInstr->getOperand(i+1);
11525 // x86 address has 4 operands: base, index, scale, and displacement
11526 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11527 int valArgIndx = lastAddrIndx + 1;
11529 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11530 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11531 for (int i=0; i <= lastAddrIndx; ++i)
11532 (*MIB).addOperand(*argOpers[i]);
11534 // We only support register and immediate values
11535 assert((argOpers[valArgIndx]->isReg() ||
11536 argOpers[valArgIndx]->isImm()) &&
11537 "invalid operand");
11539 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11540 if (argOpers[valArgIndx]->isReg())
11541 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11543 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11544 (*MIB).addOperand(*argOpers[valArgIndx]);
11546 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11549 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11554 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11555 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11559 // Cmp and exchange if none has modified the memory location
11560 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11561 for (int i=0; i <= lastAddrIndx; ++i)
11562 (*MIB).addOperand(*argOpers[i]);
11564 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11565 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11566 mInstr->memoperands_end());
11568 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11569 MIB.addReg(X86::EAX);
11572 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11574 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11578 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11579 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11580 // in the .td file.
11581 MachineBasicBlock *
11582 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11583 unsigned numArgs, bool memArg) const {
11584 assert(Subtarget->hasSSE42() &&
11585 "Target must have SSE4.2 or AVX features enabled");
11587 DebugLoc dl = MI->getDebugLoc();
11588 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11590 if (!Subtarget->hasAVX()) {
11592 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11594 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11597 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11599 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11602 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11603 for (unsigned i = 0; i < numArgs; ++i) {
11604 MachineOperand &Op = MI->getOperand(i+1);
11605 if (!(Op.isReg() && Op.isImplicit()))
11606 MIB.addOperand(Op);
11608 BuildMI(*BB, MI, dl,
11609 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11610 MI->getOperand(0).getReg())
11611 .addReg(X86::XMM0);
11613 MI->eraseFromParent();
11617 MachineBasicBlock *
11618 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11619 DebugLoc dl = MI->getDebugLoc();
11620 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11622 // Address into RAX/EAX, other two args into ECX, EDX.
11623 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11624 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11625 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11626 for (int i = 0; i < X86::AddrNumOperands; ++i)
11627 MIB.addOperand(MI->getOperand(i));
11629 unsigned ValOps = X86::AddrNumOperands;
11630 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11631 .addReg(MI->getOperand(ValOps).getReg());
11632 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11633 .addReg(MI->getOperand(ValOps+1).getReg());
11635 // The instruction doesn't actually take any operands though.
11636 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11638 MI->eraseFromParent(); // The pseudo is gone now.
11642 MachineBasicBlock *
11643 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11644 DebugLoc dl = MI->getDebugLoc();
11645 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11647 // First arg in ECX, the second in EAX.
11648 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11649 .addReg(MI->getOperand(0).getReg());
11650 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11651 .addReg(MI->getOperand(1).getReg());
11653 // The instruction doesn't actually take any operands though.
11654 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11656 MI->eraseFromParent(); // The pseudo is gone now.
11660 MachineBasicBlock *
11661 X86TargetLowering::EmitVAARG64WithCustomInserter(
11663 MachineBasicBlock *MBB) const {
11664 // Emit va_arg instruction on X86-64.
11666 // Operands to this pseudo-instruction:
11667 // 0 ) Output : destination address (reg)
11668 // 1-5) Input : va_list address (addr, i64mem)
11669 // 6 ) ArgSize : Size (in bytes) of vararg type
11670 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11671 // 8 ) Align : Alignment of type
11672 // 9 ) EFLAGS (implicit-def)
11674 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11675 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11677 unsigned DestReg = MI->getOperand(0).getReg();
11678 MachineOperand &Base = MI->getOperand(1);
11679 MachineOperand &Scale = MI->getOperand(2);
11680 MachineOperand &Index = MI->getOperand(3);
11681 MachineOperand &Disp = MI->getOperand(4);
11682 MachineOperand &Segment = MI->getOperand(5);
11683 unsigned ArgSize = MI->getOperand(6).getImm();
11684 unsigned ArgMode = MI->getOperand(7).getImm();
11685 unsigned Align = MI->getOperand(8).getImm();
11687 // Memory Reference
11688 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11689 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11690 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11692 // Machine Information
11693 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11694 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11695 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11696 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11697 DebugLoc DL = MI->getDebugLoc();
11699 // struct va_list {
11702 // i64 overflow_area (address)
11703 // i64 reg_save_area (address)
11705 // sizeof(va_list) = 24
11706 // alignment(va_list) = 8
11708 unsigned TotalNumIntRegs = 6;
11709 unsigned TotalNumXMMRegs = 8;
11710 bool UseGPOffset = (ArgMode == 1);
11711 bool UseFPOffset = (ArgMode == 2);
11712 unsigned MaxOffset = TotalNumIntRegs * 8 +
11713 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11715 /* Align ArgSize to a multiple of 8 */
11716 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11717 bool NeedsAlign = (Align > 8);
11719 MachineBasicBlock *thisMBB = MBB;
11720 MachineBasicBlock *overflowMBB;
11721 MachineBasicBlock *offsetMBB;
11722 MachineBasicBlock *endMBB;
11724 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11725 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11726 unsigned OffsetReg = 0;
11728 if (!UseGPOffset && !UseFPOffset) {
11729 // If we only pull from the overflow region, we don't create a branch.
11730 // We don't need to alter control flow.
11731 OffsetDestReg = 0; // unused
11732 OverflowDestReg = DestReg;
11735 overflowMBB = thisMBB;
11738 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11739 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11740 // If not, pull from overflow_area. (branch to overflowMBB)
11745 // offsetMBB overflowMBB
11750 // Registers for the PHI in endMBB
11751 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11752 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11754 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11755 MachineFunction *MF = MBB->getParent();
11756 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11757 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11758 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11760 MachineFunction::iterator MBBIter = MBB;
11763 // Insert the new basic blocks
11764 MF->insert(MBBIter, offsetMBB);
11765 MF->insert(MBBIter, overflowMBB);
11766 MF->insert(MBBIter, endMBB);
11768 // Transfer the remainder of MBB and its successor edges to endMBB.
11769 endMBB->splice(endMBB->begin(), thisMBB,
11770 llvm::next(MachineBasicBlock::iterator(MI)),
11772 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11774 // Make offsetMBB and overflowMBB successors of thisMBB
11775 thisMBB->addSuccessor(offsetMBB);
11776 thisMBB->addSuccessor(overflowMBB);
11778 // endMBB is a successor of both offsetMBB and overflowMBB
11779 offsetMBB->addSuccessor(endMBB);
11780 overflowMBB->addSuccessor(endMBB);
11782 // Load the offset value into a register
11783 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11784 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11788 .addDisp(Disp, UseFPOffset ? 4 : 0)
11789 .addOperand(Segment)
11790 .setMemRefs(MMOBegin, MMOEnd);
11792 // Check if there is enough room left to pull this argument.
11793 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11795 .addImm(MaxOffset + 8 - ArgSizeA8);
11797 // Branch to "overflowMBB" if offset >= max
11798 // Fall through to "offsetMBB" otherwise
11799 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11800 .addMBB(overflowMBB);
11803 // In offsetMBB, emit code to use the reg_save_area.
11805 assert(OffsetReg != 0);
11807 // Read the reg_save_area address.
11808 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11809 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11814 .addOperand(Segment)
11815 .setMemRefs(MMOBegin, MMOEnd);
11817 // Zero-extend the offset
11818 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11819 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11822 .addImm(X86::sub_32bit);
11824 // Add the offset to the reg_save_area to get the final address.
11825 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11826 .addReg(OffsetReg64)
11827 .addReg(RegSaveReg);
11829 // Compute the offset for the next argument
11830 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11831 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11833 .addImm(UseFPOffset ? 16 : 8);
11835 // Store it back into the va_list.
11836 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11840 .addDisp(Disp, UseFPOffset ? 4 : 0)
11841 .addOperand(Segment)
11842 .addReg(NextOffsetReg)
11843 .setMemRefs(MMOBegin, MMOEnd);
11846 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11851 // Emit code to use overflow area
11854 // Load the overflow_area address into a register.
11855 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11856 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11861 .addOperand(Segment)
11862 .setMemRefs(MMOBegin, MMOEnd);
11864 // If we need to align it, do so. Otherwise, just copy the address
11865 // to OverflowDestReg.
11867 // Align the overflow address
11868 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11869 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11871 // aligned_addr = (addr + (align-1)) & ~(align-1)
11872 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11873 .addReg(OverflowAddrReg)
11876 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11878 .addImm(~(uint64_t)(Align-1));
11880 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11881 .addReg(OverflowAddrReg);
11884 // Compute the next overflow address after this argument.
11885 // (the overflow address should be kept 8-byte aligned)
11886 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11887 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11888 .addReg(OverflowDestReg)
11889 .addImm(ArgSizeA8);
11891 // Store the new overflow address.
11892 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11897 .addOperand(Segment)
11898 .addReg(NextAddrReg)
11899 .setMemRefs(MMOBegin, MMOEnd);
11901 // If we branched, emit the PHI to the front of endMBB.
11903 BuildMI(*endMBB, endMBB->begin(), DL,
11904 TII->get(X86::PHI), DestReg)
11905 .addReg(OffsetDestReg).addMBB(offsetMBB)
11906 .addReg(OverflowDestReg).addMBB(overflowMBB);
11909 // Erase the pseudo instruction
11910 MI->eraseFromParent();
11915 MachineBasicBlock *
11916 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11918 MachineBasicBlock *MBB) const {
11919 // Emit code to save XMM registers to the stack. The ABI says that the
11920 // number of registers to save is given in %al, so it's theoretically
11921 // possible to do an indirect jump trick to avoid saving all of them,
11922 // however this code takes a simpler approach and just executes all
11923 // of the stores if %al is non-zero. It's less code, and it's probably
11924 // easier on the hardware branch predictor, and stores aren't all that
11925 // expensive anyway.
11927 // Create the new basic blocks. One block contains all the XMM stores,
11928 // and one block is the final destination regardless of whether any
11929 // stores were performed.
11930 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11931 MachineFunction *F = MBB->getParent();
11932 MachineFunction::iterator MBBIter = MBB;
11934 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11935 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11936 F->insert(MBBIter, XMMSaveMBB);
11937 F->insert(MBBIter, EndMBB);
11939 // Transfer the remainder of MBB and its successor edges to EndMBB.
11940 EndMBB->splice(EndMBB->begin(), MBB,
11941 llvm::next(MachineBasicBlock::iterator(MI)),
11943 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11945 // The original block will now fall through to the XMM save block.
11946 MBB->addSuccessor(XMMSaveMBB);
11947 // The XMMSaveMBB will fall through to the end block.
11948 XMMSaveMBB->addSuccessor(EndMBB);
11950 // Now add the instructions.
11951 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11952 DebugLoc DL = MI->getDebugLoc();
11954 unsigned CountReg = MI->getOperand(0).getReg();
11955 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11956 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11958 if (!Subtarget->isTargetWin64()) {
11959 // If %al is 0, branch around the XMM save block.
11960 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11961 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11962 MBB->addSuccessor(EndMBB);
11965 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11966 // In the XMM save block, save all the XMM argument registers.
11967 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11968 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11969 MachineMemOperand *MMO =
11970 F->getMachineMemOperand(
11971 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11972 MachineMemOperand::MOStore,
11973 /*Size=*/16, /*Align=*/16);
11974 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11975 .addFrameIndex(RegSaveFrameIndex)
11976 .addImm(/*Scale=*/1)
11977 .addReg(/*IndexReg=*/0)
11978 .addImm(/*Disp=*/Offset)
11979 .addReg(/*Segment=*/0)
11980 .addReg(MI->getOperand(i).getReg())
11981 .addMemOperand(MMO);
11984 MI->eraseFromParent(); // The pseudo instruction is gone now.
11989 // The EFLAGS operand of SelectItr might be missing a kill marker
11990 // because there were multiple uses of EFLAGS, and ISel didn't know
11991 // which to mark. Figure out whether SelectItr should have had a
11992 // kill marker, and set it if it should. Returns the correct kill
11994 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
11995 MachineBasicBlock* BB,
11996 const TargetRegisterInfo* TRI) {
11997 // Scan forward through BB for a use/def of EFLAGS.
11998 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
11999 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12000 const MachineInstr& mi = *miI;
12001 if (mi.readsRegister(X86::EFLAGS))
12003 if (mi.definesRegister(X86::EFLAGS))
12004 break; // Should have kill-flag - update below.
12007 // If we hit the end of the block, check whether EFLAGS is live into a
12009 if (miI == BB->end()) {
12010 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12011 sEnd = BB->succ_end();
12012 sItr != sEnd; ++sItr) {
12013 MachineBasicBlock* succ = *sItr;
12014 if (succ->isLiveIn(X86::EFLAGS))
12019 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12020 // out. SelectMI should have a kill flag on EFLAGS.
12021 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12025 MachineBasicBlock *
12026 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12027 MachineBasicBlock *BB) const {
12028 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12029 DebugLoc DL = MI->getDebugLoc();
12031 // To "insert" a SELECT_CC instruction, we actually have to insert the
12032 // diamond control-flow pattern. The incoming instruction knows the
12033 // destination vreg to set, the condition code register to branch on, the
12034 // true/false values to select between, and a branch opcode to use.
12035 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12036 MachineFunction::iterator It = BB;
12042 // cmpTY ccX, r1, r2
12044 // fallthrough --> copy0MBB
12045 MachineBasicBlock *thisMBB = BB;
12046 MachineFunction *F = BB->getParent();
12047 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12048 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12049 F->insert(It, copy0MBB);
12050 F->insert(It, sinkMBB);
12052 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12053 // live into the sink and copy blocks.
12054 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12055 if (!MI->killsRegister(X86::EFLAGS) &&
12056 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12057 copy0MBB->addLiveIn(X86::EFLAGS);
12058 sinkMBB->addLiveIn(X86::EFLAGS);
12061 // Transfer the remainder of BB and its successor edges to sinkMBB.
12062 sinkMBB->splice(sinkMBB->begin(), BB,
12063 llvm::next(MachineBasicBlock::iterator(MI)),
12065 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12067 // Add the true and fallthrough blocks as its successors.
12068 BB->addSuccessor(copy0MBB);
12069 BB->addSuccessor(sinkMBB);
12071 // Create the conditional branch instruction.
12073 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12074 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12077 // %FalseValue = ...
12078 // # fallthrough to sinkMBB
12079 copy0MBB->addSuccessor(sinkMBB);
12082 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12084 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12085 TII->get(X86::PHI), MI->getOperand(0).getReg())
12086 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12087 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12089 MI->eraseFromParent(); // The pseudo instruction is gone now.
12093 MachineBasicBlock *
12094 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12095 bool Is64Bit) const {
12096 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12097 DebugLoc DL = MI->getDebugLoc();
12098 MachineFunction *MF = BB->getParent();
12099 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12101 assert(getTargetMachine().Options.EnableSegmentedStacks);
12103 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12104 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12107 // ... [Till the alloca]
12108 // If stacklet is not large enough, jump to mallocMBB
12111 // Allocate by subtracting from RSP
12112 // Jump to continueMBB
12115 // Allocate by call to runtime
12119 // [rest of original BB]
12122 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12123 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12124 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12126 MachineRegisterInfo &MRI = MF->getRegInfo();
12127 const TargetRegisterClass *AddrRegClass =
12128 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12130 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12131 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12132 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12133 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12134 sizeVReg = MI->getOperand(1).getReg(),
12135 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12137 MachineFunction::iterator MBBIter = BB;
12140 MF->insert(MBBIter, bumpMBB);
12141 MF->insert(MBBIter, mallocMBB);
12142 MF->insert(MBBIter, continueMBB);
12144 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12145 (MachineBasicBlock::iterator(MI)), BB->end());
12146 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12148 // Add code to the main basic block to check if the stack limit has been hit,
12149 // and if so, jump to mallocMBB otherwise to bumpMBB.
12150 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12151 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12152 .addReg(tmpSPVReg).addReg(sizeVReg);
12153 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12154 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12155 .addReg(SPLimitVReg);
12156 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12158 // bumpMBB simply decreases the stack pointer, since we know the current
12159 // stacklet has enough space.
12160 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12161 .addReg(SPLimitVReg);
12162 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12163 .addReg(SPLimitVReg);
12164 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12166 // Calls into a routine in libgcc to allocate more space from the heap.
12167 const uint32_t *RegMask =
12168 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12170 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12172 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12173 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12174 .addRegMask(RegMask)
12175 .addReg(X86::RAX, RegState::ImplicitDefine);
12177 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12179 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12180 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12181 .addExternalSymbol("__morestack_allocate_stack_space")
12182 .addRegMask(RegMask)
12183 .addReg(X86::EAX, RegState::ImplicitDefine);
12187 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12190 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12191 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12192 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12194 // Set up the CFG correctly.
12195 BB->addSuccessor(bumpMBB);
12196 BB->addSuccessor(mallocMBB);
12197 mallocMBB->addSuccessor(continueMBB);
12198 bumpMBB->addSuccessor(continueMBB);
12200 // Take care of the PHI nodes.
12201 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12202 MI->getOperand(0).getReg())
12203 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12204 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12206 // Delete the original pseudo instruction.
12207 MI->eraseFromParent();
12210 return continueMBB;
12213 MachineBasicBlock *
12214 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12215 MachineBasicBlock *BB) const {
12216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12217 DebugLoc DL = MI->getDebugLoc();
12219 assert(!Subtarget->isTargetEnvMacho());
12221 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12222 // non-trivial part is impdef of ESP.
12224 if (Subtarget->isTargetWin64()) {
12225 if (Subtarget->isTargetCygMing()) {
12226 // ___chkstk(Mingw64):
12227 // Clobbers R10, R11, RAX and EFLAGS.
12229 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12230 .addExternalSymbol("___chkstk")
12231 .addReg(X86::RAX, RegState::Implicit)
12232 .addReg(X86::RSP, RegState::Implicit)
12233 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12234 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12235 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12237 // __chkstk(MSVCRT): does not update stack pointer.
12238 // Clobbers R10, R11 and EFLAGS.
12239 // FIXME: RAX(allocated size) might be reused and not killed.
12240 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12241 .addExternalSymbol("__chkstk")
12242 .addReg(X86::RAX, RegState::Implicit)
12243 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12244 // RAX has the offset to subtracted from RSP.
12245 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12250 const char *StackProbeSymbol =
12251 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12253 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12254 .addExternalSymbol(StackProbeSymbol)
12255 .addReg(X86::EAX, RegState::Implicit)
12256 .addReg(X86::ESP, RegState::Implicit)
12257 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12258 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12259 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12262 MI->eraseFromParent(); // The pseudo instruction is gone now.
12266 MachineBasicBlock *
12267 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12268 MachineBasicBlock *BB) const {
12269 // This is pretty easy. We're taking the value that we received from
12270 // our load from the relocation, sticking it in either RDI (x86-64)
12271 // or EAX and doing an indirect call. The return value will then
12272 // be in the normal return register.
12273 const X86InstrInfo *TII
12274 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12275 DebugLoc DL = MI->getDebugLoc();
12276 MachineFunction *F = BB->getParent();
12278 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12279 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12281 // Get a register mask for the lowered call.
12282 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12283 // proper register mask.
12284 const uint32_t *RegMask =
12285 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12286 if (Subtarget->is64Bit()) {
12287 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12288 TII->get(X86::MOV64rm), X86::RDI)
12290 .addImm(0).addReg(0)
12291 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12292 MI->getOperand(3).getTargetFlags())
12294 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12295 addDirectMem(MIB, X86::RDI);
12296 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12297 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12298 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12299 TII->get(X86::MOV32rm), X86::EAX)
12301 .addImm(0).addReg(0)
12302 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12303 MI->getOperand(3).getTargetFlags())
12305 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12306 addDirectMem(MIB, X86::EAX);
12307 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12309 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12310 TII->get(X86::MOV32rm), X86::EAX)
12311 .addReg(TII->getGlobalBaseReg(F))
12312 .addImm(0).addReg(0)
12313 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12314 MI->getOperand(3).getTargetFlags())
12316 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12317 addDirectMem(MIB, X86::EAX);
12318 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12321 MI->eraseFromParent(); // The pseudo instruction is gone now.
12325 MachineBasicBlock *
12326 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12327 MachineBasicBlock *BB) const {
12328 switch (MI->getOpcode()) {
12329 default: llvm_unreachable("Unexpected instr type to insert");
12330 case X86::TAILJMPd64:
12331 case X86::TAILJMPr64:
12332 case X86::TAILJMPm64:
12333 llvm_unreachable("TAILJMP64 would not be touched here.");
12334 case X86::TCRETURNdi64:
12335 case X86::TCRETURNri64:
12336 case X86::TCRETURNmi64:
12338 case X86::WIN_ALLOCA:
12339 return EmitLoweredWinAlloca(MI, BB);
12340 case X86::SEG_ALLOCA_32:
12341 return EmitLoweredSegAlloca(MI, BB, false);
12342 case X86::SEG_ALLOCA_64:
12343 return EmitLoweredSegAlloca(MI, BB, true);
12344 case X86::TLSCall_32:
12345 case X86::TLSCall_64:
12346 return EmitLoweredTLSCall(MI, BB);
12347 case X86::CMOV_GR8:
12348 case X86::CMOV_FR32:
12349 case X86::CMOV_FR64:
12350 case X86::CMOV_V4F32:
12351 case X86::CMOV_V2F64:
12352 case X86::CMOV_V2I64:
12353 case X86::CMOV_V8F32:
12354 case X86::CMOV_V4F64:
12355 case X86::CMOV_V4I64:
12356 case X86::CMOV_GR16:
12357 case X86::CMOV_GR32:
12358 case X86::CMOV_RFP32:
12359 case X86::CMOV_RFP64:
12360 case X86::CMOV_RFP80:
12361 return EmitLoweredSelect(MI, BB);
12363 case X86::FP32_TO_INT16_IN_MEM:
12364 case X86::FP32_TO_INT32_IN_MEM:
12365 case X86::FP32_TO_INT64_IN_MEM:
12366 case X86::FP64_TO_INT16_IN_MEM:
12367 case X86::FP64_TO_INT32_IN_MEM:
12368 case X86::FP64_TO_INT64_IN_MEM:
12369 case X86::FP80_TO_INT16_IN_MEM:
12370 case X86::FP80_TO_INT32_IN_MEM:
12371 case X86::FP80_TO_INT64_IN_MEM: {
12372 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12373 DebugLoc DL = MI->getDebugLoc();
12375 // Change the floating point control register to use "round towards zero"
12376 // mode when truncating to an integer value.
12377 MachineFunction *F = BB->getParent();
12378 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12379 addFrameReference(BuildMI(*BB, MI, DL,
12380 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12382 // Load the old value of the high byte of the control word...
12384 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12385 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12388 // Set the high part to be round to zero...
12389 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12392 // Reload the modified control word now...
12393 addFrameReference(BuildMI(*BB, MI, DL,
12394 TII->get(X86::FLDCW16m)), CWFrameIdx);
12396 // Restore the memory image of control word to original value
12397 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12400 // Get the X86 opcode to use.
12402 switch (MI->getOpcode()) {
12403 default: llvm_unreachable("illegal opcode!");
12404 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12405 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12406 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12407 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12408 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12409 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12410 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12411 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12412 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12416 MachineOperand &Op = MI->getOperand(0);
12418 AM.BaseType = X86AddressMode::RegBase;
12419 AM.Base.Reg = Op.getReg();
12421 AM.BaseType = X86AddressMode::FrameIndexBase;
12422 AM.Base.FrameIndex = Op.getIndex();
12424 Op = MI->getOperand(1);
12426 AM.Scale = Op.getImm();
12427 Op = MI->getOperand(2);
12429 AM.IndexReg = Op.getImm();
12430 Op = MI->getOperand(3);
12431 if (Op.isGlobal()) {
12432 AM.GV = Op.getGlobal();
12434 AM.Disp = Op.getImm();
12436 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12437 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12439 // Reload the original control word now.
12440 addFrameReference(BuildMI(*BB, MI, DL,
12441 TII->get(X86::FLDCW16m)), CWFrameIdx);
12443 MI->eraseFromParent(); // The pseudo instruction is gone now.
12446 // String/text processing lowering.
12447 case X86::PCMPISTRM128REG:
12448 case X86::VPCMPISTRM128REG:
12449 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12450 case X86::PCMPISTRM128MEM:
12451 case X86::VPCMPISTRM128MEM:
12452 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12453 case X86::PCMPESTRM128REG:
12454 case X86::VPCMPESTRM128REG:
12455 return EmitPCMP(MI, BB, 5, false /* in mem */);
12456 case X86::PCMPESTRM128MEM:
12457 case X86::VPCMPESTRM128MEM:
12458 return EmitPCMP(MI, BB, 5, true /* in mem */);
12460 // Thread synchronization.
12462 return EmitMonitor(MI, BB);
12464 return EmitMwait(MI, BB);
12466 // Atomic Lowering.
12467 case X86::ATOMAND32:
12468 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12469 X86::AND32ri, X86::MOV32rm,
12471 X86::NOT32r, X86::EAX,
12472 X86::GR32RegisterClass);
12473 case X86::ATOMOR32:
12474 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12475 X86::OR32ri, X86::MOV32rm,
12477 X86::NOT32r, X86::EAX,
12478 X86::GR32RegisterClass);
12479 case X86::ATOMXOR32:
12480 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12481 X86::XOR32ri, X86::MOV32rm,
12483 X86::NOT32r, X86::EAX,
12484 X86::GR32RegisterClass);
12485 case X86::ATOMNAND32:
12486 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12487 X86::AND32ri, X86::MOV32rm,
12489 X86::NOT32r, X86::EAX,
12490 X86::GR32RegisterClass, true);
12491 case X86::ATOMMIN32:
12492 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12493 case X86::ATOMMAX32:
12494 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12495 case X86::ATOMUMIN32:
12496 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12497 case X86::ATOMUMAX32:
12498 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12500 case X86::ATOMAND16:
12501 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12502 X86::AND16ri, X86::MOV16rm,
12504 X86::NOT16r, X86::AX,
12505 X86::GR16RegisterClass);
12506 case X86::ATOMOR16:
12507 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12508 X86::OR16ri, X86::MOV16rm,
12510 X86::NOT16r, X86::AX,
12511 X86::GR16RegisterClass);
12512 case X86::ATOMXOR16:
12513 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12514 X86::XOR16ri, X86::MOV16rm,
12516 X86::NOT16r, X86::AX,
12517 X86::GR16RegisterClass);
12518 case X86::ATOMNAND16:
12519 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12520 X86::AND16ri, X86::MOV16rm,
12522 X86::NOT16r, X86::AX,
12523 X86::GR16RegisterClass, true);
12524 case X86::ATOMMIN16:
12525 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12526 case X86::ATOMMAX16:
12527 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12528 case X86::ATOMUMIN16:
12529 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12530 case X86::ATOMUMAX16:
12531 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12533 case X86::ATOMAND8:
12534 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12535 X86::AND8ri, X86::MOV8rm,
12537 X86::NOT8r, X86::AL,
12538 X86::GR8RegisterClass);
12540 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12541 X86::OR8ri, X86::MOV8rm,
12543 X86::NOT8r, X86::AL,
12544 X86::GR8RegisterClass);
12545 case X86::ATOMXOR8:
12546 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12547 X86::XOR8ri, X86::MOV8rm,
12549 X86::NOT8r, X86::AL,
12550 X86::GR8RegisterClass);
12551 case X86::ATOMNAND8:
12552 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12553 X86::AND8ri, X86::MOV8rm,
12555 X86::NOT8r, X86::AL,
12556 X86::GR8RegisterClass, true);
12557 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12558 // This group is for 64-bit host.
12559 case X86::ATOMAND64:
12560 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12561 X86::AND64ri32, X86::MOV64rm,
12563 X86::NOT64r, X86::RAX,
12564 X86::GR64RegisterClass);
12565 case X86::ATOMOR64:
12566 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12567 X86::OR64ri32, X86::MOV64rm,
12569 X86::NOT64r, X86::RAX,
12570 X86::GR64RegisterClass);
12571 case X86::ATOMXOR64:
12572 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12573 X86::XOR64ri32, X86::MOV64rm,
12575 X86::NOT64r, X86::RAX,
12576 X86::GR64RegisterClass);
12577 case X86::ATOMNAND64:
12578 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12579 X86::AND64ri32, X86::MOV64rm,
12581 X86::NOT64r, X86::RAX,
12582 X86::GR64RegisterClass, true);
12583 case X86::ATOMMIN64:
12584 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12585 case X86::ATOMMAX64:
12586 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12587 case X86::ATOMUMIN64:
12588 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12589 case X86::ATOMUMAX64:
12590 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12592 // This group does 64-bit operations on a 32-bit host.
12593 case X86::ATOMAND6432:
12594 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12595 X86::AND32rr, X86::AND32rr,
12596 X86::AND32ri, X86::AND32ri,
12598 case X86::ATOMOR6432:
12599 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12600 X86::OR32rr, X86::OR32rr,
12601 X86::OR32ri, X86::OR32ri,
12603 case X86::ATOMXOR6432:
12604 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12605 X86::XOR32rr, X86::XOR32rr,
12606 X86::XOR32ri, X86::XOR32ri,
12608 case X86::ATOMNAND6432:
12609 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12610 X86::AND32rr, X86::AND32rr,
12611 X86::AND32ri, X86::AND32ri,
12613 case X86::ATOMADD6432:
12614 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12615 X86::ADD32rr, X86::ADC32rr,
12616 X86::ADD32ri, X86::ADC32ri,
12618 case X86::ATOMSUB6432:
12619 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12620 X86::SUB32rr, X86::SBB32rr,
12621 X86::SUB32ri, X86::SBB32ri,
12623 case X86::ATOMSWAP6432:
12624 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12625 X86::MOV32rr, X86::MOV32rr,
12626 X86::MOV32ri, X86::MOV32ri,
12628 case X86::VASTART_SAVE_XMM_REGS:
12629 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12631 case X86::VAARG_64:
12632 return EmitVAARG64WithCustomInserter(MI, BB);
12636 //===----------------------------------------------------------------------===//
12637 // X86 Optimization Hooks
12638 //===----------------------------------------------------------------------===//
12640 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12644 const SelectionDAG &DAG,
12645 unsigned Depth) const {
12646 unsigned Opc = Op.getOpcode();
12647 assert((Opc >= ISD::BUILTIN_OP_END ||
12648 Opc == ISD::INTRINSIC_WO_CHAIN ||
12649 Opc == ISD::INTRINSIC_W_CHAIN ||
12650 Opc == ISD::INTRINSIC_VOID) &&
12651 "Should use MaskedValueIsZero if you don't know whether Op"
12652 " is a target node!");
12654 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12668 // These nodes' second result is a boolean.
12669 if (Op.getResNo() == 0)
12672 case X86ISD::SETCC:
12673 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12674 Mask.getBitWidth() - 1);
12676 case ISD::INTRINSIC_WO_CHAIN: {
12677 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12678 unsigned NumLoBits = 0;
12681 case Intrinsic::x86_sse_movmsk_ps:
12682 case Intrinsic::x86_avx_movmsk_ps_256:
12683 case Intrinsic::x86_sse2_movmsk_pd:
12684 case Intrinsic::x86_avx_movmsk_pd_256:
12685 case Intrinsic::x86_mmx_pmovmskb:
12686 case Intrinsic::x86_sse2_pmovmskb_128:
12687 case Intrinsic::x86_avx2_pmovmskb: {
12688 // High bits of movmskp{s|d}, pmovmskb are known zero.
12690 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12691 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12692 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12693 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12694 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12695 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12696 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12697 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12699 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12700 Mask.getBitWidth() - NumLoBits);
12709 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12710 unsigned Depth) const {
12711 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12712 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12713 return Op.getValueType().getScalarType().getSizeInBits();
12719 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12720 /// node is a GlobalAddress + offset.
12721 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12722 const GlobalValue* &GA,
12723 int64_t &Offset) const {
12724 if (N->getOpcode() == X86ISD::Wrapper) {
12725 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12726 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12727 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12731 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12734 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12735 /// same as extracting the high 128-bit part of 256-bit vector and then
12736 /// inserting the result into the low part of a new 256-bit vector
12737 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12738 EVT VT = SVOp->getValueType(0);
12739 int NumElems = VT.getVectorNumElements();
12741 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12742 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12743 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12744 SVOp->getMaskElt(j) >= 0)
12750 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12751 /// same as extracting the low 128-bit part of 256-bit vector and then
12752 /// inserting the result into the high part of a new 256-bit vector
12753 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12754 EVT VT = SVOp->getValueType(0);
12755 int NumElems = VT.getVectorNumElements();
12757 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12758 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12759 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12760 SVOp->getMaskElt(j) >= 0)
12766 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12767 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12768 TargetLowering::DAGCombinerInfo &DCI,
12769 const X86Subtarget* Subtarget) {
12770 DebugLoc dl = N->getDebugLoc();
12771 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12772 SDValue V1 = SVOp->getOperand(0);
12773 SDValue V2 = SVOp->getOperand(1);
12774 EVT VT = SVOp->getValueType(0);
12775 int NumElems = VT.getVectorNumElements();
12777 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12778 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12782 // V UNDEF BUILD_VECTOR UNDEF
12784 // CONCAT_VECTOR CONCAT_VECTOR
12787 // RESULT: V + zero extended
12789 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12790 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12791 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12794 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12797 // To match the shuffle mask, the first half of the mask should
12798 // be exactly the first vector, and all the rest a splat with the
12799 // first element of the second one.
12800 for (int i = 0; i < NumElems/2; ++i)
12801 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12802 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12805 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12806 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12807 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12808 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12810 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12812 Ld->getPointerInfo(),
12813 Ld->getAlignment(),
12814 false/*isVolatile*/, true/*ReadMem*/,
12815 false/*WriteMem*/);
12816 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12819 // Emit a zeroed vector and insert the desired subvector on its
12821 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12822 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12823 DAG.getConstant(0, MVT::i32), DAG, dl);
12824 return DCI.CombineTo(N, InsV);
12827 //===--------------------------------------------------------------------===//
12828 // Combine some shuffles into subvector extracts and inserts:
12831 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12832 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12833 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12835 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12836 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12837 return DCI.CombineTo(N, InsV);
12840 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12841 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12842 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12843 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12844 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12845 return DCI.CombineTo(N, InsV);
12851 /// PerformShuffleCombine - Performs several different shuffle combines.
12852 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12853 TargetLowering::DAGCombinerInfo &DCI,
12854 const X86Subtarget *Subtarget) {
12855 DebugLoc dl = N->getDebugLoc();
12856 EVT VT = N->getValueType(0);
12858 // Don't create instructions with illegal types after legalize types has run.
12859 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12860 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12863 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12864 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12865 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12866 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12868 // Only handle 128 wide vector from here on.
12869 if (VT.getSizeInBits() != 128)
12872 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12873 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12874 // consecutive, non-overlapping, and in the right order.
12875 SmallVector<SDValue, 16> Elts;
12876 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12877 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12879 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12883 /// PerformTruncateCombine - Converts truncate operation to
12884 /// a sequence of vector shuffle operations.
12885 /// It is possible when we truncate 256-bit vector to 128-bit vector
12887 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12888 DAGCombinerInfo &DCI) const {
12889 if (!DCI.isBeforeLegalizeOps())
12892 if (!Subtarget->hasAVX()) return SDValue();
12894 EVT VT = N->getValueType(0);
12895 SDValue Op = N->getOperand(0);
12896 EVT OpVT = Op.getValueType();
12897 DebugLoc dl = N->getDebugLoc();
12899 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12901 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12902 DAG.getIntPtrConstant(0));
12904 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12905 DAG.getIntPtrConstant(2));
12907 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12908 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12911 int ShufMask1[] = {0, 2, 0, 0};
12913 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
12915 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
12919 int ShufMask2[] = {0, 1, 4, 5};
12921 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
12923 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
12925 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12926 DAG.getIntPtrConstant(0));
12928 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12929 DAG.getIntPtrConstant(4));
12931 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
12932 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
12935 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12936 -1, -1, -1, -1, -1, -1, -1, -1};
12938 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
12939 DAG.getUNDEF(MVT::v16i8),
12941 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
12942 DAG.getUNDEF(MVT::v16i8),
12945 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12946 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12949 int ShufMask2[] = {0, 1, 4, 5};
12951 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
12952 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
12958 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12959 /// generation and convert it from being a bunch of shuffles and extracts
12960 /// to a simple store and scalar loads to extract the elements.
12961 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12962 const TargetLowering &TLI) {
12963 SDValue InputVector = N->getOperand(0);
12965 // Only operate on vectors of 4 elements, where the alternative shuffling
12966 // gets to be more expensive.
12967 if (InputVector.getValueType() != MVT::v4i32)
12970 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12971 // single use which is a sign-extend or zero-extend, and all elements are
12973 SmallVector<SDNode *, 4> Uses;
12974 unsigned ExtractedElements = 0;
12975 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12976 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12977 if (UI.getUse().getResNo() != InputVector.getResNo())
12980 SDNode *Extract = *UI;
12981 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12984 if (Extract->getValueType(0) != MVT::i32)
12986 if (!Extract->hasOneUse())
12988 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12989 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12991 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12994 // Record which element was extracted.
12995 ExtractedElements |=
12996 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12998 Uses.push_back(Extract);
13001 // If not all the elements were used, this may not be worthwhile.
13002 if (ExtractedElements != 15)
13005 // Ok, we've now decided to do the transformation.
13006 DebugLoc dl = InputVector.getDebugLoc();
13008 // Store the value to a temporary stack slot.
13009 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13010 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13011 MachinePointerInfo(), false, false, 0);
13013 // Replace each use (extract) with a load of the appropriate element.
13014 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13015 UE = Uses.end(); UI != UE; ++UI) {
13016 SDNode *Extract = *UI;
13018 // cOMpute the element's address.
13019 SDValue Idx = Extract->getOperand(1);
13021 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13022 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13023 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13025 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13026 StackPtr, OffsetVal);
13028 // Load the scalar.
13029 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13030 ScalarAddr, MachinePointerInfo(),
13031 false, false, false, 0);
13033 // Replace the exact with the load.
13034 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13037 // The replacement was made in place; don't return anything.
13041 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13043 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13044 TargetLowering::DAGCombinerInfo &DCI,
13045 const X86Subtarget *Subtarget) {
13046 DebugLoc DL = N->getDebugLoc();
13047 SDValue Cond = N->getOperand(0);
13048 // Get the LHS/RHS of the select.
13049 SDValue LHS = N->getOperand(1);
13050 SDValue RHS = N->getOperand(2);
13051 EVT VT = LHS.getValueType();
13053 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13054 // instructions match the semantics of the common C idiom x<y?x:y but not
13055 // x<=y?x:y, because of how they handle negative zero (which can be
13056 // ignored in unsafe-math mode).
13057 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13058 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13059 (Subtarget->hasSSE2() ||
13060 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13061 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13063 unsigned Opcode = 0;
13064 // Check for x CC y ? x : y.
13065 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13066 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13070 // Converting this to a min would handle NaNs incorrectly, and swapping
13071 // the operands would cause it to handle comparisons between positive
13072 // and negative zero incorrectly.
13073 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13074 if (!DAG.getTarget().Options.UnsafeFPMath &&
13075 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13077 std::swap(LHS, RHS);
13079 Opcode = X86ISD::FMIN;
13082 // Converting this to a min would handle comparisons between positive
13083 // and negative zero incorrectly.
13084 if (!DAG.getTarget().Options.UnsafeFPMath &&
13085 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13087 Opcode = X86ISD::FMIN;
13090 // Converting this to a min would handle both negative zeros and NaNs
13091 // incorrectly, but we can swap the operands to fix both.
13092 std::swap(LHS, RHS);
13096 Opcode = X86ISD::FMIN;
13100 // Converting this to a max would handle comparisons between positive
13101 // and negative zero incorrectly.
13102 if (!DAG.getTarget().Options.UnsafeFPMath &&
13103 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13105 Opcode = X86ISD::FMAX;
13108 // Converting this to a max would handle NaNs incorrectly, and swapping
13109 // the operands would cause it to handle comparisons between positive
13110 // and negative zero incorrectly.
13111 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13112 if (!DAG.getTarget().Options.UnsafeFPMath &&
13113 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13115 std::swap(LHS, RHS);
13117 Opcode = X86ISD::FMAX;
13120 // Converting this to a max would handle both negative zeros and NaNs
13121 // incorrectly, but we can swap the operands to fix both.
13122 std::swap(LHS, RHS);
13126 Opcode = X86ISD::FMAX;
13129 // Check for x CC y ? y : x -- a min/max with reversed arms.
13130 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13131 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13135 // Converting this to a min would handle comparisons between positive
13136 // and negative zero incorrectly, and swapping the operands would
13137 // cause it to handle NaNs incorrectly.
13138 if (!DAG.getTarget().Options.UnsafeFPMath &&
13139 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13140 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13142 std::swap(LHS, RHS);
13144 Opcode = X86ISD::FMIN;
13147 // Converting this to a min would handle NaNs incorrectly.
13148 if (!DAG.getTarget().Options.UnsafeFPMath &&
13149 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13151 Opcode = X86ISD::FMIN;
13154 // Converting this to a min would handle both negative zeros and NaNs
13155 // incorrectly, but we can swap the operands to fix both.
13156 std::swap(LHS, RHS);
13160 Opcode = X86ISD::FMIN;
13164 // Converting this to a max would handle NaNs incorrectly.
13165 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13167 Opcode = X86ISD::FMAX;
13170 // Converting this to a max would handle comparisons between positive
13171 // and negative zero incorrectly, and swapping the operands would
13172 // cause it to handle NaNs incorrectly.
13173 if (!DAG.getTarget().Options.UnsafeFPMath &&
13174 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13175 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13177 std::swap(LHS, RHS);
13179 Opcode = X86ISD::FMAX;
13182 // Converting this to a max would handle both negative zeros and NaNs
13183 // incorrectly, but we can swap the operands to fix both.
13184 std::swap(LHS, RHS);
13188 Opcode = X86ISD::FMAX;
13194 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13197 // If this is a select between two integer constants, try to do some
13199 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13200 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13201 // Don't do this for crazy integer types.
13202 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13203 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13204 // so that TrueC (the true value) is larger than FalseC.
13205 bool NeedsCondInvert = false;
13207 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13208 // Efficiently invertible.
13209 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13210 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13211 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13212 NeedsCondInvert = true;
13213 std::swap(TrueC, FalseC);
13216 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13217 if (FalseC->getAPIntValue() == 0 &&
13218 TrueC->getAPIntValue().isPowerOf2()) {
13219 if (NeedsCondInvert) // Invert the condition if needed.
13220 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13221 DAG.getConstant(1, Cond.getValueType()));
13223 // Zero extend the condition if needed.
13224 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13226 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13227 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13228 DAG.getConstant(ShAmt, MVT::i8));
13231 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13232 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13233 if (NeedsCondInvert) // Invert the condition if needed.
13234 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13235 DAG.getConstant(1, Cond.getValueType()));
13237 // Zero extend the condition if needed.
13238 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13239 FalseC->getValueType(0), Cond);
13240 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13241 SDValue(FalseC, 0));
13244 // Optimize cases that will turn into an LEA instruction. This requires
13245 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13246 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13247 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13248 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13250 bool isFastMultiplier = false;
13252 switch ((unsigned char)Diff) {
13254 case 1: // result = add base, cond
13255 case 2: // result = lea base( , cond*2)
13256 case 3: // result = lea base(cond, cond*2)
13257 case 4: // result = lea base( , cond*4)
13258 case 5: // result = lea base(cond, cond*4)
13259 case 8: // result = lea base( , cond*8)
13260 case 9: // result = lea base(cond, cond*8)
13261 isFastMultiplier = true;
13266 if (isFastMultiplier) {
13267 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13268 if (NeedsCondInvert) // Invert the condition if needed.
13269 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13270 DAG.getConstant(1, Cond.getValueType()));
13272 // Zero extend the condition if needed.
13273 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13275 // Scale the condition by the difference.
13277 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13278 DAG.getConstant(Diff, Cond.getValueType()));
13280 // Add the base if non-zero.
13281 if (FalseC->getAPIntValue() != 0)
13282 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13283 SDValue(FalseC, 0));
13290 // Canonicalize max and min:
13291 // (x > y) ? x : y -> (x >= y) ? x : y
13292 // (x < y) ? x : y -> (x <= y) ? x : y
13293 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13294 // the need for an extra compare
13295 // against zero. e.g.
13296 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13298 // testl %edi, %edi
13300 // cmovgl %edi, %eax
13304 // cmovsl %eax, %edi
13305 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13306 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13307 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13308 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13313 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13314 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13315 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13316 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13321 // If we know that this node is legal then we know that it is going to be
13322 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13323 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13324 // to simplify previous instructions.
13325 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13326 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13327 !DCI.isBeforeLegalize() &&
13328 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13329 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13330 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13331 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13333 APInt KnownZero, KnownOne;
13334 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13335 DCI.isBeforeLegalizeOps());
13336 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13337 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13338 DCI.CommitTargetLoweringOpt(TLO);
13344 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13345 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13346 TargetLowering::DAGCombinerInfo &DCI) {
13347 DebugLoc DL = N->getDebugLoc();
13349 // If the flag operand isn't dead, don't touch this CMOV.
13350 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13353 SDValue FalseOp = N->getOperand(0);
13354 SDValue TrueOp = N->getOperand(1);
13355 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13356 SDValue Cond = N->getOperand(3);
13357 if (CC == X86::COND_E || CC == X86::COND_NE) {
13358 switch (Cond.getOpcode()) {
13362 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13363 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13364 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13368 // If this is a select between two integer constants, try to do some
13369 // optimizations. Note that the operands are ordered the opposite of SELECT
13371 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13372 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13373 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13374 // larger than FalseC (the false value).
13375 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13376 CC = X86::GetOppositeBranchCondition(CC);
13377 std::swap(TrueC, FalseC);
13380 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13381 // This is efficient for any integer data type (including i8/i16) and
13383 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13384 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13385 DAG.getConstant(CC, MVT::i8), Cond);
13387 // Zero extend the condition if needed.
13388 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13390 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13391 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13392 DAG.getConstant(ShAmt, MVT::i8));
13393 if (N->getNumValues() == 2) // Dead flag value?
13394 return DCI.CombineTo(N, Cond, SDValue());
13398 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13399 // for any integer data type, including i8/i16.
13400 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13401 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13402 DAG.getConstant(CC, MVT::i8), Cond);
13404 // Zero extend the condition if needed.
13405 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13406 FalseC->getValueType(0), Cond);
13407 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13408 SDValue(FalseC, 0));
13410 if (N->getNumValues() == 2) // Dead flag value?
13411 return DCI.CombineTo(N, Cond, SDValue());
13415 // Optimize cases that will turn into an LEA instruction. This requires
13416 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13417 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13418 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13419 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13421 bool isFastMultiplier = false;
13423 switch ((unsigned char)Diff) {
13425 case 1: // result = add base, cond
13426 case 2: // result = lea base( , cond*2)
13427 case 3: // result = lea base(cond, cond*2)
13428 case 4: // result = lea base( , cond*4)
13429 case 5: // result = lea base(cond, cond*4)
13430 case 8: // result = lea base( , cond*8)
13431 case 9: // result = lea base(cond, cond*8)
13432 isFastMultiplier = true;
13437 if (isFastMultiplier) {
13438 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13439 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13440 DAG.getConstant(CC, MVT::i8), Cond);
13441 // Zero extend the condition if needed.
13442 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13444 // Scale the condition by the difference.
13446 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13447 DAG.getConstant(Diff, Cond.getValueType()));
13449 // Add the base if non-zero.
13450 if (FalseC->getAPIntValue() != 0)
13451 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13452 SDValue(FalseC, 0));
13453 if (N->getNumValues() == 2) // Dead flag value?
13454 return DCI.CombineTo(N, Cond, SDValue());
13464 /// PerformMulCombine - Optimize a single multiply with constant into two
13465 /// in order to implement it with two cheaper instructions, e.g.
13466 /// LEA + SHL, LEA + LEA.
13467 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13468 TargetLowering::DAGCombinerInfo &DCI) {
13469 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13472 EVT VT = N->getValueType(0);
13473 if (VT != MVT::i64)
13476 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13479 uint64_t MulAmt = C->getZExtValue();
13480 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13483 uint64_t MulAmt1 = 0;
13484 uint64_t MulAmt2 = 0;
13485 if ((MulAmt % 9) == 0) {
13487 MulAmt2 = MulAmt / 9;
13488 } else if ((MulAmt % 5) == 0) {
13490 MulAmt2 = MulAmt / 5;
13491 } else if ((MulAmt % 3) == 0) {
13493 MulAmt2 = MulAmt / 3;
13496 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13497 DebugLoc DL = N->getDebugLoc();
13499 if (isPowerOf2_64(MulAmt2) &&
13500 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13501 // If second multiplifer is pow2, issue it first. We want the multiply by
13502 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13504 std::swap(MulAmt1, MulAmt2);
13507 if (isPowerOf2_64(MulAmt1))
13508 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13509 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13511 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13512 DAG.getConstant(MulAmt1, VT));
13514 if (isPowerOf2_64(MulAmt2))
13515 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13516 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13518 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13519 DAG.getConstant(MulAmt2, VT));
13521 // Do not add new nodes to DAG combiner worklist.
13522 DCI.CombineTo(N, NewMul, false);
13527 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13528 SDValue N0 = N->getOperand(0);
13529 SDValue N1 = N->getOperand(1);
13530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13531 EVT VT = N0.getValueType();
13533 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13534 // since the result of setcc_c is all zero's or all ones.
13535 if (VT.isInteger() && !VT.isVector() &&
13536 N1C && N0.getOpcode() == ISD::AND &&
13537 N0.getOperand(1).getOpcode() == ISD::Constant) {
13538 SDValue N00 = N0.getOperand(0);
13539 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13540 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13541 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13542 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13543 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13544 APInt ShAmt = N1C->getAPIntValue();
13545 Mask = Mask.shl(ShAmt);
13547 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13548 N00, DAG.getConstant(Mask, VT));
13553 // Hardware support for vector shifts is sparse which makes us scalarize the
13554 // vector operations in many cases. Also, on sandybridge ADD is faster than
13556 // (shl V, 1) -> add V,V
13557 if (isSplatVector(N1.getNode())) {
13558 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13560 // We shift all of the values by one. In many cases we do not have
13561 // hardware support for this operation. This is better expressed as an ADD
13563 if (N1C && (1 == N1C->getZExtValue())) {
13564 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13571 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13573 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13574 TargetLowering::DAGCombinerInfo &DCI,
13575 const X86Subtarget *Subtarget) {
13576 EVT VT = N->getValueType(0);
13577 if (N->getOpcode() == ISD::SHL) {
13578 SDValue V = PerformSHLCombine(N, DAG);
13579 if (V.getNode()) return V;
13582 // On X86 with SSE2 support, we can transform this to a vector shift if
13583 // all elements are shifted by the same amount. We can't do this in legalize
13584 // because the a constant vector is typically transformed to a constant pool
13585 // so we have no knowledge of the shift amount.
13586 if (!Subtarget->hasSSE2())
13589 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13590 (!Subtarget->hasAVX2() ||
13591 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13594 SDValue ShAmtOp = N->getOperand(1);
13595 EVT EltVT = VT.getVectorElementType();
13596 DebugLoc DL = N->getDebugLoc();
13597 SDValue BaseShAmt = SDValue();
13598 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13599 unsigned NumElts = VT.getVectorNumElements();
13601 for (; i != NumElts; ++i) {
13602 SDValue Arg = ShAmtOp.getOperand(i);
13603 if (Arg.getOpcode() == ISD::UNDEF) continue;
13607 // Handle the case where the build_vector is all undef
13608 // FIXME: Should DAG allow this?
13612 for (; i != NumElts; ++i) {
13613 SDValue Arg = ShAmtOp.getOperand(i);
13614 if (Arg.getOpcode() == ISD::UNDEF) continue;
13615 if (Arg != BaseShAmt) {
13619 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13620 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13621 SDValue InVec = ShAmtOp.getOperand(0);
13622 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13623 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13625 for (; i != NumElts; ++i) {
13626 SDValue Arg = InVec.getOperand(i);
13627 if (Arg.getOpcode() == ISD::UNDEF) continue;
13631 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13632 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13633 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13634 if (C->getZExtValue() == SplatIdx)
13635 BaseShAmt = InVec.getOperand(1);
13638 if (BaseShAmt.getNode() == 0) {
13639 // Don't create instructions with illegal types after legalize
13641 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13642 !DCI.isBeforeLegalize())
13645 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13646 DAG.getIntPtrConstant(0));
13651 // The shift amount is an i32.
13652 if (EltVT.bitsGT(MVT::i32))
13653 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13654 else if (EltVT.bitsLT(MVT::i32))
13655 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13657 // The shift amount is identical so we can do a vector shift.
13658 SDValue ValOp = N->getOperand(0);
13659 switch (N->getOpcode()) {
13661 llvm_unreachable("Unknown shift opcode!");
13663 switch (VT.getSimpleVT().SimpleTy) {
13664 default: return SDValue();
13671 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13674 switch (VT.getSimpleVT().SimpleTy) {
13675 default: return SDValue();
13680 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13683 switch (VT.getSimpleVT().SimpleTy) {
13684 default: return SDValue();
13691 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13697 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13698 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13699 // and friends. Likewise for OR -> CMPNEQSS.
13700 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13701 TargetLowering::DAGCombinerInfo &DCI,
13702 const X86Subtarget *Subtarget) {
13705 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13706 // we're requiring SSE2 for both.
13707 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13708 SDValue N0 = N->getOperand(0);
13709 SDValue N1 = N->getOperand(1);
13710 SDValue CMP0 = N0->getOperand(1);
13711 SDValue CMP1 = N1->getOperand(1);
13712 DebugLoc DL = N->getDebugLoc();
13714 // The SETCCs should both refer to the same CMP.
13715 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13718 SDValue CMP00 = CMP0->getOperand(0);
13719 SDValue CMP01 = CMP0->getOperand(1);
13720 EVT VT = CMP00.getValueType();
13722 if (VT == MVT::f32 || VT == MVT::f64) {
13723 bool ExpectingFlags = false;
13724 // Check for any users that want flags:
13725 for (SDNode::use_iterator UI = N->use_begin(),
13727 !ExpectingFlags && UI != UE; ++UI)
13728 switch (UI->getOpcode()) {
13733 ExpectingFlags = true;
13735 case ISD::CopyToReg:
13736 case ISD::SIGN_EXTEND:
13737 case ISD::ZERO_EXTEND:
13738 case ISD::ANY_EXTEND:
13742 if (!ExpectingFlags) {
13743 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13744 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13746 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13747 X86::CondCode tmp = cc0;
13752 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13753 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13754 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13755 X86ISD::NodeType NTOperator = is64BitFP ?
13756 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13757 // FIXME: need symbolic constants for these magic numbers.
13758 // See X86ATTInstPrinter.cpp:printSSECC().
13759 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13760 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13761 DAG.getConstant(x86cc, MVT::i8));
13762 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13764 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13765 DAG.getConstant(1, MVT::i32));
13766 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13767 return OneBitOfTruth;
13775 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13776 /// so it can be folded inside ANDNP.
13777 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13778 EVT VT = N->getValueType(0);
13780 // Match direct AllOnes for 128 and 256-bit vectors
13781 if (ISD::isBuildVectorAllOnes(N))
13784 // Look through a bit convert.
13785 if (N->getOpcode() == ISD::BITCAST)
13786 N = N->getOperand(0).getNode();
13788 // Sometimes the operand may come from a insert_subvector building a 256-bit
13790 if (VT.getSizeInBits() == 256 &&
13791 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13792 SDValue V1 = N->getOperand(0);
13793 SDValue V2 = N->getOperand(1);
13795 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13796 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13797 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13798 ISD::isBuildVectorAllOnes(V2.getNode()))
13805 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13806 TargetLowering::DAGCombinerInfo &DCI,
13807 const X86Subtarget *Subtarget) {
13808 if (DCI.isBeforeLegalizeOps())
13811 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13815 EVT VT = N->getValueType(0);
13817 // Create ANDN, BLSI, and BLSR instructions
13818 // BLSI is X & (-X)
13819 // BLSR is X & (X-1)
13820 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13821 SDValue N0 = N->getOperand(0);
13822 SDValue N1 = N->getOperand(1);
13823 DebugLoc DL = N->getDebugLoc();
13825 // Check LHS for not
13826 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13827 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13828 // Check RHS for not
13829 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13830 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13832 // Check LHS for neg
13833 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13834 isZero(N0.getOperand(0)))
13835 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13837 // Check RHS for neg
13838 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13839 isZero(N1.getOperand(0)))
13840 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13842 // Check LHS for X-1
13843 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13844 isAllOnes(N0.getOperand(1)))
13845 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13847 // Check RHS for X-1
13848 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13849 isAllOnes(N1.getOperand(1)))
13850 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13855 // Want to form ANDNP nodes:
13856 // 1) In the hopes of then easily combining them with OR and AND nodes
13857 // to form PBLEND/PSIGN.
13858 // 2) To match ANDN packed intrinsics
13859 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13862 SDValue N0 = N->getOperand(0);
13863 SDValue N1 = N->getOperand(1);
13864 DebugLoc DL = N->getDebugLoc();
13866 // Check LHS for vnot
13867 if (N0.getOpcode() == ISD::XOR &&
13868 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13869 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13870 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13872 // Check RHS for vnot
13873 if (N1.getOpcode() == ISD::XOR &&
13874 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13875 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13876 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13881 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13882 TargetLowering::DAGCombinerInfo &DCI,
13883 const X86Subtarget *Subtarget) {
13884 if (DCI.isBeforeLegalizeOps())
13887 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13891 EVT VT = N->getValueType(0);
13893 SDValue N0 = N->getOperand(0);
13894 SDValue N1 = N->getOperand(1);
13896 // look for psign/blend
13897 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13898 if (!Subtarget->hasSSSE3() ||
13899 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13902 // Canonicalize pandn to RHS
13903 if (N0.getOpcode() == X86ISD::ANDNP)
13905 // or (and (m, y), (pandn m, x))
13906 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13907 SDValue Mask = N1.getOperand(0);
13908 SDValue X = N1.getOperand(1);
13910 if (N0.getOperand(0) == Mask)
13911 Y = N0.getOperand(1);
13912 if (N0.getOperand(1) == Mask)
13913 Y = N0.getOperand(0);
13915 // Check to see if the mask appeared in both the AND and ANDNP and
13919 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13920 if (Mask.getOpcode() != ISD::BITCAST ||
13921 X.getOpcode() != ISD::BITCAST ||
13922 Y.getOpcode() != ISD::BITCAST)
13925 // Look through mask bitcast.
13926 Mask = Mask.getOperand(0);
13927 EVT MaskVT = Mask.getValueType();
13929 // Validate that the Mask operand is a vector sra node.
13930 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13931 // there is no psrai.b
13932 if (Mask.getOpcode() != X86ISD::VSRAI)
13935 // Check that the SRA is all signbits.
13936 SDValue SraC = Mask.getOperand(1);
13937 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13938 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13939 if ((SraAmt + 1) != EltBits)
13942 DebugLoc DL = N->getDebugLoc();
13944 // Now we know we at least have a plendvb with the mask val. See if
13945 // we can form a psignb/w/d.
13946 // psign = x.type == y.type == mask.type && y = sub(0, x);
13947 X = X.getOperand(0);
13948 Y = Y.getOperand(0);
13949 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13950 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13951 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
13952 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
13953 "Unsupported VT for PSIGN");
13954 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
13955 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13957 // PBLENDVB only available on SSE 4.1
13958 if (!Subtarget->hasSSE41())
13961 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13963 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13964 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13965 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13966 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13967 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13971 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13974 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13975 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13977 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13979 if (!N0.hasOneUse() || !N1.hasOneUse())
13982 SDValue ShAmt0 = N0.getOperand(1);
13983 if (ShAmt0.getValueType() != MVT::i8)
13985 SDValue ShAmt1 = N1.getOperand(1);
13986 if (ShAmt1.getValueType() != MVT::i8)
13988 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13989 ShAmt0 = ShAmt0.getOperand(0);
13990 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13991 ShAmt1 = ShAmt1.getOperand(0);
13993 DebugLoc DL = N->getDebugLoc();
13994 unsigned Opc = X86ISD::SHLD;
13995 SDValue Op0 = N0.getOperand(0);
13996 SDValue Op1 = N1.getOperand(0);
13997 if (ShAmt0.getOpcode() == ISD::SUB) {
13998 Opc = X86ISD::SHRD;
13999 std::swap(Op0, Op1);
14000 std::swap(ShAmt0, ShAmt1);
14003 unsigned Bits = VT.getSizeInBits();
14004 if (ShAmt1.getOpcode() == ISD::SUB) {
14005 SDValue Sum = ShAmt1.getOperand(0);
14006 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14007 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14008 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14009 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14010 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14011 return DAG.getNode(Opc, DL, VT,
14013 DAG.getNode(ISD::TRUNCATE, DL,
14016 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14017 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14019 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14020 return DAG.getNode(Opc, DL, VT,
14021 N0.getOperand(0), N1.getOperand(0),
14022 DAG.getNode(ISD::TRUNCATE, DL,
14029 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14030 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14031 TargetLowering::DAGCombinerInfo &DCI,
14032 const X86Subtarget *Subtarget) {
14033 if (DCI.isBeforeLegalizeOps())
14036 EVT VT = N->getValueType(0);
14038 if (VT != MVT::i32 && VT != MVT::i64)
14041 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14043 // Create BLSMSK instructions by finding X ^ (X-1)
14044 SDValue N0 = N->getOperand(0);
14045 SDValue N1 = N->getOperand(1);
14046 DebugLoc DL = N->getDebugLoc();
14048 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14049 isAllOnes(N0.getOperand(1)))
14050 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14052 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14053 isAllOnes(N1.getOperand(1)))
14054 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14059 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14060 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14061 const X86Subtarget *Subtarget) {
14062 LoadSDNode *Ld = cast<LoadSDNode>(N);
14063 EVT RegVT = Ld->getValueType(0);
14064 EVT MemVT = Ld->getMemoryVT();
14065 DebugLoc dl = Ld->getDebugLoc();
14066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14068 ISD::LoadExtType Ext = Ld->getExtensionType();
14070 // If this is a vector EXT Load then attempt to optimize it using a
14071 // shuffle. We need SSE4 for the shuffles.
14072 // TODO: It is possible to support ZExt by zeroing the undef values
14073 // during the shuffle phase or after the shuffle.
14074 if (RegVT.isVector() && RegVT.isInteger() &&
14075 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14076 assert(MemVT != RegVT && "Cannot extend to the same type");
14077 assert(MemVT.isVector() && "Must load a vector from memory");
14079 unsigned NumElems = RegVT.getVectorNumElements();
14080 unsigned RegSz = RegVT.getSizeInBits();
14081 unsigned MemSz = MemVT.getSizeInBits();
14082 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14083 // All sizes must be a power of two
14084 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14086 // Attempt to load the original value using a single load op.
14087 // Find a scalar type which is equal to the loaded word size.
14088 MVT SclrLoadTy = MVT::i8;
14089 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14090 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14091 MVT Tp = (MVT::SimpleValueType)tp;
14092 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14098 // Proceed if a load word is found.
14099 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14101 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14102 RegSz/SclrLoadTy.getSizeInBits());
14104 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14105 RegSz/MemVT.getScalarType().getSizeInBits());
14106 // Can't shuffle using an illegal type.
14107 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14109 // Perform a single load.
14110 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14112 Ld->getPointerInfo(), Ld->isVolatile(),
14113 Ld->isNonTemporal(), Ld->isInvariant(),
14114 Ld->getAlignment());
14116 // Insert the word loaded into a vector.
14117 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14118 LoadUnitVecVT, ScalarLoad);
14120 // Bitcast the loaded value to a vector of the original element type, in
14121 // the size of the target vector type.
14122 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14124 unsigned SizeRatio = RegSz/MemSz;
14126 // Redistribute the loaded elements into the different locations.
14127 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14128 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14130 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14131 DAG.getUNDEF(SlicedVec.getValueType()),
14132 ShuffleVec.data());
14134 // Bitcast to the requested type.
14135 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14136 // Replace the original load with the new sequence
14137 // and return the new chain.
14138 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14139 return SDValue(ScalarLoad.getNode(), 1);
14145 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14146 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14147 const X86Subtarget *Subtarget) {
14148 StoreSDNode *St = cast<StoreSDNode>(N);
14149 EVT VT = St->getValue().getValueType();
14150 EVT StVT = St->getMemoryVT();
14151 DebugLoc dl = St->getDebugLoc();
14152 SDValue StoredVal = St->getOperand(1);
14153 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14155 // If we are saving a concatenation of two XMM registers, perform two stores.
14156 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14157 // 128-bit ones. If in the future the cost becomes only one memory access the
14158 // first version would be better.
14159 if (VT.getSizeInBits() == 256 &&
14160 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14161 StoredVal.getNumOperands() == 2) {
14163 SDValue Value0 = StoredVal.getOperand(0);
14164 SDValue Value1 = StoredVal.getOperand(1);
14166 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14167 SDValue Ptr0 = St->getBasePtr();
14168 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14170 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14171 St->getPointerInfo(), St->isVolatile(),
14172 St->isNonTemporal(), St->getAlignment());
14173 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14174 St->getPointerInfo(), St->isVolatile(),
14175 St->isNonTemporal(), St->getAlignment());
14176 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14179 // Optimize trunc store (of multiple scalars) to shuffle and store.
14180 // First, pack all of the elements in one place. Next, store to memory
14181 // in fewer chunks.
14182 if (St->isTruncatingStore() && VT.isVector()) {
14183 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14184 unsigned NumElems = VT.getVectorNumElements();
14185 assert(StVT != VT && "Cannot truncate to the same type");
14186 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14187 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14189 // From, To sizes and ElemCount must be pow of two
14190 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14191 // We are going to use the original vector elt for storing.
14192 // Accumulated smaller vector elements must be a multiple of the store size.
14193 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14195 unsigned SizeRatio = FromSz / ToSz;
14197 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14199 // Create a type on which we perform the shuffle
14200 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14201 StVT.getScalarType(), NumElems*SizeRatio);
14203 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14205 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14206 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14207 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14209 // Can't shuffle using an illegal type
14210 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14212 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14213 DAG.getUNDEF(WideVec.getValueType()),
14214 ShuffleVec.data());
14215 // At this point all of the data is stored at the bottom of the
14216 // register. We now need to save it to mem.
14218 // Find the largest store unit
14219 MVT StoreType = MVT::i8;
14220 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14221 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14222 MVT Tp = (MVT::SimpleValueType)tp;
14223 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14227 // Bitcast the original vector into a vector of store-size units
14228 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14229 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14230 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14231 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14232 SmallVector<SDValue, 8> Chains;
14233 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14234 TLI.getPointerTy());
14235 SDValue Ptr = St->getBasePtr();
14237 // Perform one or more big stores into memory.
14238 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14239 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14240 StoreType, ShuffWide,
14241 DAG.getIntPtrConstant(i));
14242 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14243 St->getPointerInfo(), St->isVolatile(),
14244 St->isNonTemporal(), St->getAlignment());
14245 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14246 Chains.push_back(Ch);
14249 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14254 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14255 // the FP state in cases where an emms may be missing.
14256 // A preferable solution to the general problem is to figure out the right
14257 // places to insert EMMS. This qualifies as a quick hack.
14259 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14260 if (VT.getSizeInBits() != 64)
14263 const Function *F = DAG.getMachineFunction().getFunction();
14264 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14265 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14266 && Subtarget->hasSSE2();
14267 if ((VT.isVector() ||
14268 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14269 isa<LoadSDNode>(St->getValue()) &&
14270 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14271 St->getChain().hasOneUse() && !St->isVolatile()) {
14272 SDNode* LdVal = St->getValue().getNode();
14273 LoadSDNode *Ld = 0;
14274 int TokenFactorIndex = -1;
14275 SmallVector<SDValue, 8> Ops;
14276 SDNode* ChainVal = St->getChain().getNode();
14277 // Must be a store of a load. We currently handle two cases: the load
14278 // is a direct child, and it's under an intervening TokenFactor. It is
14279 // possible to dig deeper under nested TokenFactors.
14280 if (ChainVal == LdVal)
14281 Ld = cast<LoadSDNode>(St->getChain());
14282 else if (St->getValue().hasOneUse() &&
14283 ChainVal->getOpcode() == ISD::TokenFactor) {
14284 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14285 if (ChainVal->getOperand(i).getNode() == LdVal) {
14286 TokenFactorIndex = i;
14287 Ld = cast<LoadSDNode>(St->getValue());
14289 Ops.push_back(ChainVal->getOperand(i));
14293 if (!Ld || !ISD::isNormalLoad(Ld))
14296 // If this is not the MMX case, i.e. we are just turning i64 load/store
14297 // into f64 load/store, avoid the transformation if there are multiple
14298 // uses of the loaded value.
14299 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14302 DebugLoc LdDL = Ld->getDebugLoc();
14303 DebugLoc StDL = N->getDebugLoc();
14304 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14305 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14307 if (Subtarget->is64Bit() || F64IsLegal) {
14308 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14309 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14310 Ld->getPointerInfo(), Ld->isVolatile(),
14311 Ld->isNonTemporal(), Ld->isInvariant(),
14312 Ld->getAlignment());
14313 SDValue NewChain = NewLd.getValue(1);
14314 if (TokenFactorIndex != -1) {
14315 Ops.push_back(NewChain);
14316 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14319 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14320 St->getPointerInfo(),
14321 St->isVolatile(), St->isNonTemporal(),
14322 St->getAlignment());
14325 // Otherwise, lower to two pairs of 32-bit loads / stores.
14326 SDValue LoAddr = Ld->getBasePtr();
14327 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14328 DAG.getConstant(4, MVT::i32));
14330 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14331 Ld->getPointerInfo(),
14332 Ld->isVolatile(), Ld->isNonTemporal(),
14333 Ld->isInvariant(), Ld->getAlignment());
14334 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14335 Ld->getPointerInfo().getWithOffset(4),
14336 Ld->isVolatile(), Ld->isNonTemporal(),
14338 MinAlign(Ld->getAlignment(), 4));
14340 SDValue NewChain = LoLd.getValue(1);
14341 if (TokenFactorIndex != -1) {
14342 Ops.push_back(LoLd);
14343 Ops.push_back(HiLd);
14344 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14348 LoAddr = St->getBasePtr();
14349 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14350 DAG.getConstant(4, MVT::i32));
14352 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14353 St->getPointerInfo(),
14354 St->isVolatile(), St->isNonTemporal(),
14355 St->getAlignment());
14356 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14357 St->getPointerInfo().getWithOffset(4),
14359 St->isNonTemporal(),
14360 MinAlign(St->getAlignment(), 4));
14361 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14366 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14367 /// and return the operands for the horizontal operation in LHS and RHS. A
14368 /// horizontal operation performs the binary operation on successive elements
14369 /// of its first operand, then on successive elements of its second operand,
14370 /// returning the resulting values in a vector. For example, if
14371 /// A = < float a0, float a1, float a2, float a3 >
14373 /// B = < float b0, float b1, float b2, float b3 >
14374 /// then the result of doing a horizontal operation on A and B is
14375 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14376 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14377 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14378 /// set to A, RHS to B, and the routine returns 'true'.
14379 /// Note that the binary operation should have the property that if one of the
14380 /// operands is UNDEF then the result is UNDEF.
14381 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14382 // Look for the following pattern: if
14383 // A = < float a0, float a1, float a2, float a3 >
14384 // B = < float b0, float b1, float b2, float b3 >
14386 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14387 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14388 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14389 // which is A horizontal-op B.
14391 // At least one of the operands should be a vector shuffle.
14392 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14393 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14396 EVT VT = LHS.getValueType();
14398 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14399 "Unsupported vector type for horizontal add/sub");
14401 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14402 // operate independently on 128-bit lanes.
14403 unsigned NumElts = VT.getVectorNumElements();
14404 unsigned NumLanes = VT.getSizeInBits()/128;
14405 unsigned NumLaneElts = NumElts / NumLanes;
14406 assert((NumLaneElts % 2 == 0) &&
14407 "Vector type should have an even number of elements in each lane");
14408 unsigned HalfLaneElts = NumLaneElts/2;
14410 // View LHS in the form
14411 // LHS = VECTOR_SHUFFLE A, B, LMask
14412 // If LHS is not a shuffle then pretend it is the shuffle
14413 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14414 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14417 SmallVector<int, 16> LMask(NumElts);
14418 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14419 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14420 A = LHS.getOperand(0);
14421 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14422 B = LHS.getOperand(1);
14423 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14424 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14426 if (LHS.getOpcode() != ISD::UNDEF)
14428 for (unsigned i = 0; i != NumElts; ++i)
14432 // Likewise, view RHS in the form
14433 // RHS = VECTOR_SHUFFLE C, D, RMask
14435 SmallVector<int, 16> RMask(NumElts);
14436 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14437 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14438 C = RHS.getOperand(0);
14439 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14440 D = RHS.getOperand(1);
14441 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14442 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14444 if (RHS.getOpcode() != ISD::UNDEF)
14446 for (unsigned i = 0; i != NumElts; ++i)
14450 // Check that the shuffles are both shuffling the same vectors.
14451 if (!(A == C && B == D) && !(A == D && B == C))
14454 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14455 if (!A.getNode() && !B.getNode())
14458 // If A and B occur in reverse order in RHS, then "swap" them (which means
14459 // rewriting the mask).
14461 CommuteVectorShuffleMask(RMask, NumElts);
14463 // At this point LHS and RHS are equivalent to
14464 // LHS = VECTOR_SHUFFLE A, B, LMask
14465 // RHS = VECTOR_SHUFFLE A, B, RMask
14466 // Check that the masks correspond to performing a horizontal operation.
14467 for (unsigned i = 0; i != NumElts; ++i) {
14468 int LIdx = LMask[i], RIdx = RMask[i];
14470 // Ignore any UNDEF components.
14471 if (LIdx < 0 || RIdx < 0 ||
14472 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14473 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14476 // Check that successive elements are being operated on. If not, this is
14477 // not a horizontal operation.
14478 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14479 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14480 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14481 if (!(LIdx == Index && RIdx == Index + 1) &&
14482 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14486 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14487 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14491 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14492 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14493 const X86Subtarget *Subtarget) {
14494 EVT VT = N->getValueType(0);
14495 SDValue LHS = N->getOperand(0);
14496 SDValue RHS = N->getOperand(1);
14498 // Try to synthesize horizontal adds from adds of shuffles.
14499 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14500 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14501 isHorizontalBinOp(LHS, RHS, true))
14502 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14506 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14507 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14508 const X86Subtarget *Subtarget) {
14509 EVT VT = N->getValueType(0);
14510 SDValue LHS = N->getOperand(0);
14511 SDValue RHS = N->getOperand(1);
14513 // Try to synthesize horizontal subs from subs of shuffles.
14514 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14515 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14516 isHorizontalBinOp(LHS, RHS, false))
14517 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14521 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14522 /// X86ISD::FXOR nodes.
14523 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14524 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14525 // F[X]OR(0.0, x) -> x
14526 // F[X]OR(x, 0.0) -> x
14527 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14528 if (C->getValueAPF().isPosZero())
14529 return N->getOperand(1);
14530 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14531 if (C->getValueAPF().isPosZero())
14532 return N->getOperand(0);
14536 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14537 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14538 // FAND(0.0, x) -> 0.0
14539 // FAND(x, 0.0) -> 0.0
14540 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14541 if (C->getValueAPF().isPosZero())
14542 return N->getOperand(0);
14543 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14544 if (C->getValueAPF().isPosZero())
14545 return N->getOperand(1);
14549 static SDValue PerformBTCombine(SDNode *N,
14551 TargetLowering::DAGCombinerInfo &DCI) {
14552 // BT ignores high bits in the bit index operand.
14553 SDValue Op1 = N->getOperand(1);
14554 if (Op1.hasOneUse()) {
14555 unsigned BitWidth = Op1.getValueSizeInBits();
14556 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14557 APInt KnownZero, KnownOne;
14558 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14559 !DCI.isBeforeLegalizeOps());
14560 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14561 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14562 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14563 DCI.CommitTargetLoweringOpt(TLO);
14568 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14569 SDValue Op = N->getOperand(0);
14570 if (Op.getOpcode() == ISD::BITCAST)
14571 Op = Op.getOperand(0);
14572 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14573 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14574 VT.getVectorElementType().getSizeInBits() ==
14575 OpVT.getVectorElementType().getSizeInBits()) {
14576 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14581 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14582 TargetLowering::DAGCombinerInfo &DCI,
14583 const X86Subtarget *Subtarget) {
14584 if (!DCI.isBeforeLegalizeOps())
14587 if (!Subtarget->hasAVX())
14590 // Optimize vectors in AVX mode
14591 // Sign extend v8i16 to v8i32 and
14594 // Divide input vector into two parts
14595 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14596 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14597 // concat the vectors to original VT
14599 EVT VT = N->getValueType(0);
14600 SDValue Op = N->getOperand(0);
14601 EVT OpVT = Op.getValueType();
14602 DebugLoc dl = N->getDebugLoc();
14604 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14605 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14607 unsigned NumElems = OpVT.getVectorNumElements();
14608 SmallVector<int,8> ShufMask1(NumElems, -1);
14609 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14611 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14614 SmallVector<int,8> ShufMask2(NumElems, -1);
14615 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14617 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14620 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14621 VT.getVectorNumElements()/2);
14623 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14624 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14626 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14631 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14632 const X86Subtarget *Subtarget) {
14633 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14634 // (and (i32 x86isd::setcc_carry), 1)
14635 // This eliminates the zext. This transformation is necessary because
14636 // ISD::SETCC is always legalized to i8.
14637 DebugLoc dl = N->getDebugLoc();
14638 SDValue N0 = N->getOperand(0);
14639 EVT VT = N->getValueType(0);
14640 EVT OpVT = N0.getValueType();
14642 if (N0.getOpcode() == ISD::AND &&
14644 N0.getOperand(0).hasOneUse()) {
14645 SDValue N00 = N0.getOperand(0);
14646 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14648 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14649 if (!C || C->getZExtValue() != 1)
14651 return DAG.getNode(ISD::AND, dl, VT,
14652 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14653 N00.getOperand(0), N00.getOperand(1)),
14654 DAG.getConstant(1, VT));
14656 // Optimize vectors in AVX mode:
14659 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14660 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14661 // Concat upper and lower parts.
14664 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14665 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14666 // Concat upper and lower parts.
14668 if (Subtarget->hasAVX()) {
14670 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14671 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14673 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14674 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14675 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14677 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14678 VT.getVectorNumElements()/2);
14680 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14681 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14683 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14691 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14692 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14693 unsigned X86CC = N->getConstantOperandVal(0);
14694 SDValue EFLAG = N->getOperand(1);
14695 DebugLoc DL = N->getDebugLoc();
14697 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14698 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14700 if (X86CC == X86::COND_B)
14701 return DAG.getNode(ISD::AND, DL, MVT::i8,
14702 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14703 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14704 DAG.getConstant(1, MVT::i8));
14709 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14710 const X86TargetLowering *XTLI) {
14711 SDValue Op0 = N->getOperand(0);
14712 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14713 // a 32-bit target where SSE doesn't support i64->FP operations.
14714 if (Op0.getOpcode() == ISD::LOAD) {
14715 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14716 EVT VT = Ld->getValueType(0);
14717 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14718 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14719 !XTLI->getSubtarget()->is64Bit() &&
14720 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14721 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14722 Ld->getChain(), Op0, DAG);
14723 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14730 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14731 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14732 X86TargetLowering::DAGCombinerInfo &DCI) {
14733 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14734 // the result is either zero or one (depending on the input carry bit).
14735 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14736 if (X86::isZeroNode(N->getOperand(0)) &&
14737 X86::isZeroNode(N->getOperand(1)) &&
14738 // We don't have a good way to replace an EFLAGS use, so only do this when
14740 SDValue(N, 1).use_empty()) {
14741 DebugLoc DL = N->getDebugLoc();
14742 EVT VT = N->getValueType(0);
14743 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14744 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14745 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14746 DAG.getConstant(X86::COND_B,MVT::i8),
14748 DAG.getConstant(1, VT));
14749 return DCI.CombineTo(N, Res1, CarryOut);
14755 // fold (add Y, (sete X, 0)) -> adc 0, Y
14756 // (add Y, (setne X, 0)) -> sbb -1, Y
14757 // (sub (sete X, 0), Y) -> sbb 0, Y
14758 // (sub (setne X, 0), Y) -> adc -1, Y
14759 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14760 DebugLoc DL = N->getDebugLoc();
14762 // Look through ZExts.
14763 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14764 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14767 SDValue SetCC = Ext.getOperand(0);
14768 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14771 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14772 if (CC != X86::COND_E && CC != X86::COND_NE)
14775 SDValue Cmp = SetCC.getOperand(1);
14776 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14777 !X86::isZeroNode(Cmp.getOperand(1)) ||
14778 !Cmp.getOperand(0).getValueType().isInteger())
14781 SDValue CmpOp0 = Cmp.getOperand(0);
14782 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14783 DAG.getConstant(1, CmpOp0.getValueType()));
14785 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14786 if (CC == X86::COND_NE)
14787 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14788 DL, OtherVal.getValueType(), OtherVal,
14789 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14790 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14791 DL, OtherVal.getValueType(), OtherVal,
14792 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14795 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14796 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14797 const X86Subtarget *Subtarget) {
14798 EVT VT = N->getValueType(0);
14799 SDValue Op0 = N->getOperand(0);
14800 SDValue Op1 = N->getOperand(1);
14802 // Try to synthesize horizontal adds from adds of shuffles.
14803 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14804 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14805 isHorizontalBinOp(Op0, Op1, true))
14806 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14808 return OptimizeConditionalInDecrement(N, DAG);
14811 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14812 const X86Subtarget *Subtarget) {
14813 SDValue Op0 = N->getOperand(0);
14814 SDValue Op1 = N->getOperand(1);
14816 // X86 can't encode an immediate LHS of a sub. See if we can push the
14817 // negation into a preceding instruction.
14818 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14819 // If the RHS of the sub is a XOR with one use and a constant, invert the
14820 // immediate. Then add one to the LHS of the sub so we can turn
14821 // X-Y -> X+~Y+1, saving one register.
14822 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14823 isa<ConstantSDNode>(Op1.getOperand(1))) {
14824 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14825 EVT VT = Op0.getValueType();
14826 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14828 DAG.getConstant(~XorC, VT));
14829 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14830 DAG.getConstant(C->getAPIntValue()+1, VT));
14834 // Try to synthesize horizontal adds from adds of shuffles.
14835 EVT VT = N->getValueType(0);
14836 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14837 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14838 isHorizontalBinOp(Op0, Op1, true))
14839 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14841 return OptimizeConditionalInDecrement(N, DAG);
14844 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14845 DAGCombinerInfo &DCI) const {
14846 SelectionDAG &DAG = DCI.DAG;
14847 switch (N->getOpcode()) {
14849 case ISD::EXTRACT_VECTOR_ELT:
14850 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14852 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14853 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14854 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14855 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14856 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14857 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14860 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
14861 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14862 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14863 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14864 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14865 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14866 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14867 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14868 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14870 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14871 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14872 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14873 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14874 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14875 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
14876 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
14877 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14878 case X86ISD::SHUFP: // Handle all target specific shuffles
14879 case X86ISD::PALIGN:
14880 case X86ISD::UNPCKH:
14881 case X86ISD::UNPCKL:
14882 case X86ISD::MOVHLPS:
14883 case X86ISD::MOVLHPS:
14884 case X86ISD::PSHUFD:
14885 case X86ISD::PSHUFHW:
14886 case X86ISD::PSHUFLW:
14887 case X86ISD::MOVSS:
14888 case X86ISD::MOVSD:
14889 case X86ISD::VPERMILP:
14890 case X86ISD::VPERM2X128:
14891 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14897 /// isTypeDesirableForOp - Return true if the target has native support for
14898 /// the specified value type and it is 'desirable' to use the type for the
14899 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14900 /// instruction encodings are longer and some i16 instructions are slow.
14901 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14902 if (!isTypeLegal(VT))
14904 if (VT != MVT::i16)
14911 case ISD::SIGN_EXTEND:
14912 case ISD::ZERO_EXTEND:
14913 case ISD::ANY_EXTEND:
14926 /// IsDesirableToPromoteOp - This method query the target whether it is
14927 /// beneficial for dag combiner to promote the specified node. If true, it
14928 /// should return the desired promotion type by reference.
14929 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14930 EVT VT = Op.getValueType();
14931 if (VT != MVT::i16)
14934 bool Promote = false;
14935 bool Commute = false;
14936 switch (Op.getOpcode()) {
14939 LoadSDNode *LD = cast<LoadSDNode>(Op);
14940 // If the non-extending load has a single use and it's not live out, then it
14941 // might be folded.
14942 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14943 Op.hasOneUse()*/) {
14944 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14945 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14946 // The only case where we'd want to promote LOAD (rather then it being
14947 // promoted as an operand is when it's only use is liveout.
14948 if (UI->getOpcode() != ISD::CopyToReg)
14955 case ISD::SIGN_EXTEND:
14956 case ISD::ZERO_EXTEND:
14957 case ISD::ANY_EXTEND:
14962 SDValue N0 = Op.getOperand(0);
14963 // Look out for (store (shl (load), x)).
14964 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14977 SDValue N0 = Op.getOperand(0);
14978 SDValue N1 = Op.getOperand(1);
14979 if (!Commute && MayFoldLoad(N1))
14981 // Avoid disabling potential load folding opportunities.
14982 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14984 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14994 //===----------------------------------------------------------------------===//
14995 // X86 Inline Assembly Support
14996 //===----------------------------------------------------------------------===//
14999 // Helper to match a string separated by whitespace.
15000 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15001 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15003 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15004 StringRef piece(*args[i]);
15005 if (!s.startswith(piece)) // Check if the piece matches.
15008 s = s.substr(piece.size());
15009 StringRef::size_type pos = s.find_first_not_of(" \t");
15010 if (pos == 0) // We matched a prefix.
15018 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15021 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15022 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15024 std::string AsmStr = IA->getAsmString();
15026 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15027 if (!Ty || Ty->getBitWidth() % 16 != 0)
15030 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15031 SmallVector<StringRef, 4> AsmPieces;
15032 SplitString(AsmStr, AsmPieces, ";\n");
15034 switch (AsmPieces.size()) {
15035 default: return false;
15037 // FIXME: this should verify that we are targeting a 486 or better. If not,
15038 // we will turn this bswap into something that will be lowered to logical
15039 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15040 // lower so don't worry about this.
15042 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15043 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15044 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15045 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15046 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15047 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15048 // No need to check constraints, nothing other than the equivalent of
15049 // "=r,0" would be valid here.
15050 return IntrinsicLowering::LowerToByteSwap(CI);
15053 // rorw $$8, ${0:w} --> llvm.bswap.i16
15054 if (CI->getType()->isIntegerTy(16) &&
15055 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15056 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15057 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15059 const std::string &ConstraintsStr = IA->getConstraintString();
15060 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15061 std::sort(AsmPieces.begin(), AsmPieces.end());
15062 if (AsmPieces.size() == 4 &&
15063 AsmPieces[0] == "~{cc}" &&
15064 AsmPieces[1] == "~{dirflag}" &&
15065 AsmPieces[2] == "~{flags}" &&
15066 AsmPieces[3] == "~{fpsr}")
15067 return IntrinsicLowering::LowerToByteSwap(CI);
15071 if (CI->getType()->isIntegerTy(32) &&
15072 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15073 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15074 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15075 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15077 const std::string &ConstraintsStr = IA->getConstraintString();
15078 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15079 std::sort(AsmPieces.begin(), AsmPieces.end());
15080 if (AsmPieces.size() == 4 &&
15081 AsmPieces[0] == "~{cc}" &&
15082 AsmPieces[1] == "~{dirflag}" &&
15083 AsmPieces[2] == "~{flags}" &&
15084 AsmPieces[3] == "~{fpsr}")
15085 return IntrinsicLowering::LowerToByteSwap(CI);
15088 if (CI->getType()->isIntegerTy(64)) {
15089 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15090 if (Constraints.size() >= 2 &&
15091 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15092 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15093 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15094 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15095 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15096 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15097 return IntrinsicLowering::LowerToByteSwap(CI);
15107 /// getConstraintType - Given a constraint letter, return the type of
15108 /// constraint it is for this target.
15109 X86TargetLowering::ConstraintType
15110 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15111 if (Constraint.size() == 1) {
15112 switch (Constraint[0]) {
15123 return C_RegisterClass;
15147 return TargetLowering::getConstraintType(Constraint);
15150 /// Examine constraint type and operand type and determine a weight value.
15151 /// This object must already have been set up with the operand type
15152 /// and the current alternative constraint selected.
15153 TargetLowering::ConstraintWeight
15154 X86TargetLowering::getSingleConstraintMatchWeight(
15155 AsmOperandInfo &info, const char *constraint) const {
15156 ConstraintWeight weight = CW_Invalid;
15157 Value *CallOperandVal = info.CallOperandVal;
15158 // If we don't have a value, we can't do a match,
15159 // but allow it at the lowest weight.
15160 if (CallOperandVal == NULL)
15162 Type *type = CallOperandVal->getType();
15163 // Look at the constraint type.
15164 switch (*constraint) {
15166 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15177 if (CallOperandVal->getType()->isIntegerTy())
15178 weight = CW_SpecificReg;
15183 if (type->isFloatingPointTy())
15184 weight = CW_SpecificReg;
15187 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15188 weight = CW_SpecificReg;
15192 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15193 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15194 weight = CW_Register;
15197 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15198 if (C->getZExtValue() <= 31)
15199 weight = CW_Constant;
15203 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15204 if (C->getZExtValue() <= 63)
15205 weight = CW_Constant;
15209 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15210 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15211 weight = CW_Constant;
15215 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15216 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15217 weight = CW_Constant;
15221 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15222 if (C->getZExtValue() <= 3)
15223 weight = CW_Constant;
15227 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15228 if (C->getZExtValue() <= 0xff)
15229 weight = CW_Constant;
15234 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15235 weight = CW_Constant;
15239 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15240 if ((C->getSExtValue() >= -0x80000000LL) &&
15241 (C->getSExtValue() <= 0x7fffffffLL))
15242 weight = CW_Constant;
15246 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15247 if (C->getZExtValue() <= 0xffffffff)
15248 weight = CW_Constant;
15255 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15256 /// with another that has more specific requirements based on the type of the
15257 /// corresponding operand.
15258 const char *X86TargetLowering::
15259 LowerXConstraint(EVT ConstraintVT) const {
15260 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15261 // 'f' like normal targets.
15262 if (ConstraintVT.isFloatingPoint()) {
15263 if (Subtarget->hasSSE2())
15265 if (Subtarget->hasSSE1())
15269 return TargetLowering::LowerXConstraint(ConstraintVT);
15272 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15273 /// vector. If it is invalid, don't add anything to Ops.
15274 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15275 std::string &Constraint,
15276 std::vector<SDValue>&Ops,
15277 SelectionDAG &DAG) const {
15278 SDValue Result(0, 0);
15280 // Only support length 1 constraints for now.
15281 if (Constraint.length() > 1) return;
15283 char ConstraintLetter = Constraint[0];
15284 switch (ConstraintLetter) {
15287 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15288 if (C->getZExtValue() <= 31) {
15289 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15296 if (C->getZExtValue() <= 63) {
15297 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15303 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15304 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15305 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15311 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15312 if (C->getZExtValue() <= 255) {
15313 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15319 // 32-bit signed value
15320 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15321 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15322 C->getSExtValue())) {
15323 // Widen to 64 bits here to get it sign extended.
15324 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15327 // FIXME gcc accepts some relocatable values here too, but only in certain
15328 // memory models; it's complicated.
15333 // 32-bit unsigned value
15334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15335 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15336 C->getZExtValue())) {
15337 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15341 // FIXME gcc accepts some relocatable values here too, but only in certain
15342 // memory models; it's complicated.
15346 // Literal immediates are always ok.
15347 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15348 // Widen to 64 bits here to get it sign extended.
15349 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15353 // In any sort of PIC mode addresses need to be computed at runtime by
15354 // adding in a register or some sort of table lookup. These can't
15355 // be used as immediates.
15356 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15359 // If we are in non-pic codegen mode, we allow the address of a global (with
15360 // an optional displacement) to be used with 'i'.
15361 GlobalAddressSDNode *GA = 0;
15362 int64_t Offset = 0;
15364 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15366 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15367 Offset += GA->getOffset();
15369 } else if (Op.getOpcode() == ISD::ADD) {
15370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15371 Offset += C->getZExtValue();
15372 Op = Op.getOperand(0);
15375 } else if (Op.getOpcode() == ISD::SUB) {
15376 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15377 Offset += -C->getZExtValue();
15378 Op = Op.getOperand(0);
15383 // Otherwise, this isn't something we can handle, reject it.
15387 const GlobalValue *GV = GA->getGlobal();
15388 // If we require an extra load to get this address, as in PIC mode, we
15389 // can't accept it.
15390 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15391 getTargetMachine())))
15394 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15395 GA->getValueType(0), Offset);
15400 if (Result.getNode()) {
15401 Ops.push_back(Result);
15404 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15407 std::pair<unsigned, const TargetRegisterClass*>
15408 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15410 // First, see if this is a constraint that directly corresponds to an LLVM
15412 if (Constraint.size() == 1) {
15413 // GCC Constraint Letters
15414 switch (Constraint[0]) {
15416 // TODO: Slight differences here in allocation order and leaving
15417 // RIP in the class. Do they matter any more here than they do
15418 // in the normal allocation?
15419 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15420 if (Subtarget->is64Bit()) {
15421 if (VT == MVT::i32 || VT == MVT::f32)
15422 return std::make_pair(0U, X86::GR32RegisterClass);
15423 else if (VT == MVT::i16)
15424 return std::make_pair(0U, X86::GR16RegisterClass);
15425 else if (VT == MVT::i8 || VT == MVT::i1)
15426 return std::make_pair(0U, X86::GR8RegisterClass);
15427 else if (VT == MVT::i64 || VT == MVT::f64)
15428 return std::make_pair(0U, X86::GR64RegisterClass);
15431 // 32-bit fallthrough
15432 case 'Q': // Q_REGS
15433 if (VT == MVT::i32 || VT == MVT::f32)
15434 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15435 else if (VT == MVT::i16)
15436 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15437 else if (VT == MVT::i8 || VT == MVT::i1)
15438 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15439 else if (VT == MVT::i64)
15440 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15442 case 'r': // GENERAL_REGS
15443 case 'l': // INDEX_REGS
15444 if (VT == MVT::i8 || VT == MVT::i1)
15445 return std::make_pair(0U, X86::GR8RegisterClass);
15446 if (VT == MVT::i16)
15447 return std::make_pair(0U, X86::GR16RegisterClass);
15448 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15449 return std::make_pair(0U, X86::GR32RegisterClass);
15450 return std::make_pair(0U, X86::GR64RegisterClass);
15451 case 'R': // LEGACY_REGS
15452 if (VT == MVT::i8 || VT == MVT::i1)
15453 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15454 if (VT == MVT::i16)
15455 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15456 if (VT == MVT::i32 || !Subtarget->is64Bit())
15457 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15458 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15459 case 'f': // FP Stack registers.
15460 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15461 // value to the correct fpstack register class.
15462 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15463 return std::make_pair(0U, X86::RFP32RegisterClass);
15464 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15465 return std::make_pair(0U, X86::RFP64RegisterClass);
15466 return std::make_pair(0U, X86::RFP80RegisterClass);
15467 case 'y': // MMX_REGS if MMX allowed.
15468 if (!Subtarget->hasMMX()) break;
15469 return std::make_pair(0U, X86::VR64RegisterClass);
15470 case 'Y': // SSE_REGS if SSE2 allowed
15471 if (!Subtarget->hasSSE2()) break;
15473 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15474 if (!Subtarget->hasSSE1()) break;
15476 switch (VT.getSimpleVT().SimpleTy) {
15478 // Scalar SSE types.
15481 return std::make_pair(0U, X86::FR32RegisterClass);
15484 return std::make_pair(0U, X86::FR64RegisterClass);
15492 return std::make_pair(0U, X86::VR128RegisterClass);
15500 return std::make_pair(0U, X86::VR256RegisterClass);
15507 // Use the default implementation in TargetLowering to convert the register
15508 // constraint into a member of a register class.
15509 std::pair<unsigned, const TargetRegisterClass*> Res;
15510 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15512 // Not found as a standard register?
15513 if (Res.second == 0) {
15514 // Map st(0) -> st(7) -> ST0
15515 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15516 tolower(Constraint[1]) == 's' &&
15517 tolower(Constraint[2]) == 't' &&
15518 Constraint[3] == '(' &&
15519 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15520 Constraint[5] == ')' &&
15521 Constraint[6] == '}') {
15523 Res.first = X86::ST0+Constraint[4]-'0';
15524 Res.second = X86::RFP80RegisterClass;
15528 // GCC allows "st(0)" to be called just plain "st".
15529 if (StringRef("{st}").equals_lower(Constraint)) {
15530 Res.first = X86::ST0;
15531 Res.second = X86::RFP80RegisterClass;
15536 if (StringRef("{flags}").equals_lower(Constraint)) {
15537 Res.first = X86::EFLAGS;
15538 Res.second = X86::CCRRegisterClass;
15542 // 'A' means EAX + EDX.
15543 if (Constraint == "A") {
15544 Res.first = X86::EAX;
15545 Res.second = X86::GR32_ADRegisterClass;
15551 // Otherwise, check to see if this is a register class of the wrong value
15552 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15553 // turn into {ax},{dx}.
15554 if (Res.second->hasType(VT))
15555 return Res; // Correct type already, nothing to do.
15557 // All of the single-register GCC register classes map their values onto
15558 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15559 // really want an 8-bit or 32-bit register, map to the appropriate register
15560 // class and return the appropriate register.
15561 if (Res.second == X86::GR16RegisterClass) {
15562 if (VT == MVT::i8) {
15563 unsigned DestReg = 0;
15564 switch (Res.first) {
15566 case X86::AX: DestReg = X86::AL; break;
15567 case X86::DX: DestReg = X86::DL; break;
15568 case X86::CX: DestReg = X86::CL; break;
15569 case X86::BX: DestReg = X86::BL; break;
15572 Res.first = DestReg;
15573 Res.second = X86::GR8RegisterClass;
15575 } else if (VT == MVT::i32) {
15576 unsigned DestReg = 0;
15577 switch (Res.first) {
15579 case X86::AX: DestReg = X86::EAX; break;
15580 case X86::DX: DestReg = X86::EDX; break;
15581 case X86::CX: DestReg = X86::ECX; break;
15582 case X86::BX: DestReg = X86::EBX; break;
15583 case X86::SI: DestReg = X86::ESI; break;
15584 case X86::DI: DestReg = X86::EDI; break;
15585 case X86::BP: DestReg = X86::EBP; break;
15586 case X86::SP: DestReg = X86::ESP; break;
15589 Res.first = DestReg;
15590 Res.second = X86::GR32RegisterClass;
15592 } else if (VT == MVT::i64) {
15593 unsigned DestReg = 0;
15594 switch (Res.first) {
15596 case X86::AX: DestReg = X86::RAX; break;
15597 case X86::DX: DestReg = X86::RDX; break;
15598 case X86::CX: DestReg = X86::RCX; break;
15599 case X86::BX: DestReg = X86::RBX; break;
15600 case X86::SI: DestReg = X86::RSI; break;
15601 case X86::DI: DestReg = X86::RDI; break;
15602 case X86::BP: DestReg = X86::RBP; break;
15603 case X86::SP: DestReg = X86::RSP; break;
15606 Res.first = DestReg;
15607 Res.second = X86::GR64RegisterClass;
15610 } else if (Res.second == X86::FR32RegisterClass ||
15611 Res.second == X86::FR64RegisterClass ||
15612 Res.second == X86::VR128RegisterClass) {
15613 // Handle references to XMM physical registers that got mapped into the
15614 // wrong class. This can happen with constraints like {xmm0} where the
15615 // target independent register mapper will just pick the first match it can
15616 // find, ignoring the required type.
15617 if (VT == MVT::f32)
15618 Res.second = X86::FR32RegisterClass;
15619 else if (VT == MVT::f64)
15620 Res.second = X86::FR64RegisterClass;
15621 else if (X86::VR128RegisterClass->hasType(VT))
15622 Res.second = X86::VR128RegisterClass;