1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Only provide customized ctpop vector bit twiddling for vector types we
991 // know to perform better than using the popcnt instructions on each vector
992 // element. If popcnt isn't supported, always provide the custom version.
993 if (!Subtarget->hasPOPCNT()) {
994 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
995 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
998 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
999 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1000 MVT VT = (MVT::SimpleValueType)i;
1001 // Do not attempt to custom lower non-power-of-2 vectors
1002 if (!isPowerOf2_32(VT.getVectorNumElements()))
1004 // Do not attempt to custom lower non-128-bit vectors
1005 if (!VT.is128BitVector())
1007 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1008 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1012 // We support custom legalizing of sext and anyext loads for specific
1013 // memory vector types which we can load as a scalar (or sequence of
1014 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1015 // loads these must work with a single scalar load.
1016 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1026 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1027 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1028 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1029 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1033 if (Subtarget->is64Bit()) {
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1038 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1039 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1040 MVT VT = (MVT::SimpleValueType)i;
1042 // Do not attempt to promote non-128-bit vectors
1043 if (!VT.is128BitVector())
1046 setOperationAction(ISD::AND, VT, Promote);
1047 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1048 setOperationAction(ISD::OR, VT, Promote);
1049 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1050 setOperationAction(ISD::XOR, VT, Promote);
1051 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1052 setOperationAction(ISD::LOAD, VT, Promote);
1053 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1054 setOperationAction(ISD::SELECT, VT, Promote);
1055 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1058 // Custom lower v2i64 and v2f64 selects.
1059 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1060 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1061 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1065 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1069 // As there is no 64-bit GPR available, we need build a special custom
1070 // sequence to convert from v2i32 to v2f32.
1071 if (!Subtarget->is64Bit())
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1074 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1075 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1077 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1079 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1080 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1081 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1084 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1085 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1090 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1107 // FIXME: Do we need to handle scalar-to-vector here?
1108 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1110 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1112 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1113 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1114 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1115 // There is no BLENDI for byte vectors. We don't need to custom lower
1116 // some vselects for now.
1117 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1119 // SSE41 brings specific instructions for doing vector sign extend even in
1120 // cases where we don't have SRA.
1121 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1122 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1123 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1125 // i8 and i16 vectors are custom because the source register and source
1126 // source memory operand types are not the same width. f32 vectors are
1127 // custom since the immediate controlling the insert encodes additional
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1139 // FIXME: these should be Legal, but that's only for the case where
1140 // the index is constant. For now custom expand to deal with that.
1141 if (Subtarget->is64Bit()) {
1142 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1147 if (Subtarget->hasSSE2()) {
1148 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1154 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1157 // In the customized shift lowering, the legal cases in AVX2 will be
1159 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1163 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1165 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1168 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1169 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1172 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1173 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1174 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1176 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1178 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1180 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1191 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1193 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1204 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1206 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1207 // even though v8i16 is a legal type.
1208 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1209 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1210 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1212 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1213 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1214 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1216 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1217 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1219 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1221 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1233 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1235 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1240 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1241 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1242 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1254 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1255 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1257 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1258 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1260 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1261 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1262 setOperationAction(ISD::FMA, MVT::f32, Legal);
1263 setOperationAction(ISD::FMA, MVT::f64, Legal);
1266 if (Subtarget->hasInt256()) {
1267 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1268 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1269 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1270 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1272 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1273 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1274 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1275 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1277 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1278 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1279 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1280 // Don't lower v32i8 because there is no 128-bit byte mul
1282 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1283 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1284 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1285 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1287 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1288 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1290 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1291 // when we have a 256bit-wide blend with immediate.
1292 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1294 // Only provide customized ctpop vector bit twiddling for vector types we
1295 // know to perform better than using the popcnt instructions on each
1296 // vector element. If popcnt isn't supported, always provide the custom
1298 if (!Subtarget->hasPOPCNT())
1299 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1301 // Custom CTPOP always performs better on natively supported v8i32
1302 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1304 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1305 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1306 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1307 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1309 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1312 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1314 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1317 // Don't lower v32i8 because there is no 128-bit byte mul
1320 // In the customized shift lowering, the legal cases in AVX2 will be
1322 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1323 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1325 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1326 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1328 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1330 // Custom lower several nodes for 256-bit types.
1331 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1332 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1333 MVT VT = (MVT::SimpleValueType)i;
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector()) {
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1351 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1353 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1354 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1357 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1358 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1359 MVT VT = (MVT::SimpleValueType)i;
1361 // Do not attempt to promote non-256-bit vectors
1362 if (!VT.is256BitVector())
1365 setOperationAction(ISD::AND, VT, Promote);
1366 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1367 setOperationAction(ISD::OR, VT, Promote);
1368 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1369 setOperationAction(ISD::XOR, VT, Promote);
1370 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1371 setOperationAction(ISD::LOAD, VT, Promote);
1372 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1373 setOperationAction(ISD::SELECT, VT, Promote);
1374 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1378 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1379 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1380 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1381 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1382 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1384 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1385 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1386 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1388 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1389 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1390 setOperationAction(ISD::XOR, MVT::i1, Legal);
1391 setOperationAction(ISD::OR, MVT::i1, Legal);
1392 setOperationAction(ISD::AND, MVT::i1, Legal);
1393 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1394 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1395 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1398 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1400 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1407 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1413 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1420 if (Subtarget->is64Bit()) {
1421 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1433 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1434 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1435 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1436 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1439 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1441 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1444 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1445 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1446 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1447 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1506 // Custom lower several nodes.
1507 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1508 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1509 MVT VT = (MVT::SimpleValueType)i;
1511 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1512 // Extract subvector is special because the value type
1513 // (result) is 256/128-bit but the source is 512-bit wide.
1514 if (VT.is128BitVector() || VT.is256BitVector()) {
1515 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1517 if (VT.getVectorElementType() == MVT::i1)
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1520 // Do not attempt to custom lower other non-512-bit vectors
1521 if (!VT.is512BitVector())
1524 if ( EltSize >= 32) {
1525 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1526 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1527 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1528 setOperationAction(ISD::VSELECT, VT, Legal);
1529 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1530 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1531 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1532 setOperationAction(ISD::MLOAD, VT, Legal);
1533 setOperationAction(ISD::MSTORE, VT, Legal);
1536 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1537 MVT VT = (MVT::SimpleValueType)i;
1539 // Do not attempt to promote non-256-bit vectors.
1540 if (!VT.is512BitVector())
1543 setOperationAction(ISD::SELECT, VT, Promote);
1544 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1548 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1549 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1550 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1552 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1553 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1555 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1556 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1557 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1558 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1559 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1560 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1561 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1562 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1563 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1565 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1566 const MVT VT = (MVT::SimpleValueType)i;
1568 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1570 // Do not attempt to promote non-256-bit vectors.
1571 if (!VT.is512BitVector())
1575 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1576 setOperationAction(ISD::VSELECT, VT, Legal);
1581 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1582 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1583 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1585 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1586 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1587 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1589 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1590 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1591 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1592 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1593 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1594 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1597 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1598 // of this type with custom code.
1599 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1600 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1601 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1605 // We want to custom lower some of our intrinsics.
1606 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1607 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1608 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1609 if (!Subtarget->is64Bit())
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1612 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1613 // handle type legalization for these operations here.
1615 // FIXME: We really should do custom legalization for addition and
1616 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1617 // than generic legalization for 64-bit multiplication-with-overflow, though.
1618 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1619 // Add/Sub/Mul with overflow operations are custom lowered.
1621 setOperationAction(ISD::SADDO, VT, Custom);
1622 setOperationAction(ISD::UADDO, VT, Custom);
1623 setOperationAction(ISD::SSUBO, VT, Custom);
1624 setOperationAction(ISD::USUBO, VT, Custom);
1625 setOperationAction(ISD::SMULO, VT, Custom);
1626 setOperationAction(ISD::UMULO, VT, Custom);
1630 if (!Subtarget->is64Bit()) {
1631 // These libcalls are not available in 32-bit.
1632 setLibcallName(RTLIB::SHL_I128, nullptr);
1633 setLibcallName(RTLIB::SRL_I128, nullptr);
1634 setLibcallName(RTLIB::SRA_I128, nullptr);
1637 // Combine sin / cos into one node or libcall if possible.
1638 if (Subtarget->hasSinCos()) {
1639 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1640 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1641 if (Subtarget->isTargetDarwin()) {
1642 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1643 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1644 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1645 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1649 if (Subtarget->isTargetWin64()) {
1650 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1651 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1652 setOperationAction(ISD::SREM, MVT::i128, Custom);
1653 setOperationAction(ISD::UREM, MVT::i128, Custom);
1654 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1655 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1658 // We have target-specific dag combine patterns for the following nodes:
1659 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1660 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1661 setTargetDAGCombine(ISD::VSELECT);
1662 setTargetDAGCombine(ISD::SELECT);
1663 setTargetDAGCombine(ISD::SHL);
1664 setTargetDAGCombine(ISD::SRA);
1665 setTargetDAGCombine(ISD::SRL);
1666 setTargetDAGCombine(ISD::OR);
1667 setTargetDAGCombine(ISD::AND);
1668 setTargetDAGCombine(ISD::ADD);
1669 setTargetDAGCombine(ISD::FADD);
1670 setTargetDAGCombine(ISD::FSUB);
1671 setTargetDAGCombine(ISD::FMA);
1672 setTargetDAGCombine(ISD::SUB);
1673 setTargetDAGCombine(ISD::LOAD);
1674 setTargetDAGCombine(ISD::STORE);
1675 setTargetDAGCombine(ISD::ZERO_EXTEND);
1676 setTargetDAGCombine(ISD::ANY_EXTEND);
1677 setTargetDAGCombine(ISD::SIGN_EXTEND);
1678 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1679 setTargetDAGCombine(ISD::TRUNCATE);
1680 setTargetDAGCombine(ISD::SINT_TO_FP);
1681 setTargetDAGCombine(ISD::SETCC);
1682 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1683 setTargetDAGCombine(ISD::BUILD_VECTOR);
1684 if (Subtarget->is64Bit())
1685 setTargetDAGCombine(ISD::MUL);
1686 setTargetDAGCombine(ISD::XOR);
1688 computeRegisterProperties();
1690 // On Darwin, -Os means optimize for size without hurting performance,
1691 // do not reduce the limit.
1692 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1693 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1694 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1695 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1696 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1697 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1698 setPrefLoopAlignment(4); // 2^4 bytes.
1700 // Predictable cmov don't hurt on atom because it's in-order.
1701 PredictableSelectIsExpensive = !Subtarget->isAtom();
1702 EnableExtLdPromotion = true;
1703 setPrefFunctionAlignment(4); // 2^4 bytes.
1705 verifyIntrinsicTables();
1708 // This has so far only been implemented for 64-bit MachO.
1709 bool X86TargetLowering::useLoadStackGuardNode() const {
1710 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1713 TargetLoweringBase::LegalizeTypeAction
1714 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1715 if (ExperimentalVectorWideningLegalization &&
1716 VT.getVectorNumElements() != 1 &&
1717 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1718 return TypeWidenVector;
1720 return TargetLoweringBase::getPreferredVectorAction(VT);
1723 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1725 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1727 const unsigned NumElts = VT.getVectorNumElements();
1728 const EVT EltVT = VT.getVectorElementType();
1729 if (VT.is512BitVector()) {
1730 if (Subtarget->hasAVX512())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 8: return MVT::v8i1;
1735 case 16: return MVT::v16i1;
1737 if (Subtarget->hasBWI())
1738 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1740 case 32: return MVT::v32i1;
1741 case 64: return MVT::v64i1;
1745 if (VT.is256BitVector() || VT.is128BitVector()) {
1746 if (Subtarget->hasVLX())
1747 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1748 EltVT == MVT::f32 || EltVT == MVT::f64)
1750 case 2: return MVT::v2i1;
1751 case 4: return MVT::v4i1;
1752 case 8: return MVT::v8i1;
1754 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1755 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1757 case 8: return MVT::v8i1;
1758 case 16: return MVT::v16i1;
1759 case 32: return MVT::v32i1;
1763 return VT.changeVectorElementTypeToInteger();
1766 /// Helper for getByValTypeAlignment to determine
1767 /// the desired ByVal argument alignment.
1768 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1771 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1772 if (VTy->getBitWidth() == 128)
1774 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1775 unsigned EltAlign = 0;
1776 getMaxByValAlign(ATy->getElementType(), EltAlign);
1777 if (EltAlign > MaxAlign)
1778 MaxAlign = EltAlign;
1779 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1780 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1781 unsigned EltAlign = 0;
1782 getMaxByValAlign(STy->getElementType(i), EltAlign);
1783 if (EltAlign > MaxAlign)
1784 MaxAlign = EltAlign;
1791 /// Return the desired alignment for ByVal aggregate
1792 /// function arguments in the caller parameter area. For X86, aggregates
1793 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1794 /// are at 4-byte boundaries.
1795 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1796 if (Subtarget->is64Bit()) {
1797 // Max of 8 and alignment of type.
1798 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1805 if (Subtarget->hasSSE1())
1806 getMaxByValAlign(Ty, Align);
1810 /// Returns the target specific optimal type for load
1811 /// and store operations as a result of memset, memcpy, and memmove
1812 /// lowering. If DstAlign is zero that means it's safe to destination
1813 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1814 /// means there isn't a need to check it against alignment requirement,
1815 /// probably because the source does not need to be loaded. If 'IsMemset' is
1816 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1817 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1818 /// source is constant so it does not need to be loaded.
1819 /// It returns EVT::Other if the type should be determined using generic
1820 /// target-independent logic.
1822 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1823 unsigned DstAlign, unsigned SrcAlign,
1824 bool IsMemset, bool ZeroMemset,
1826 MachineFunction &MF) const {
1827 const Function *F = MF.getFunction();
1828 if ((!IsMemset || ZeroMemset) &&
1829 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1830 Attribute::NoImplicitFloat)) {
1832 (Subtarget->isUnalignedMemAccessFast() ||
1833 ((DstAlign == 0 || DstAlign >= 16) &&
1834 (SrcAlign == 0 || SrcAlign >= 16)))) {
1836 if (Subtarget->hasInt256())
1838 if (Subtarget->hasFp256())
1841 if (Subtarget->hasSSE2())
1843 if (Subtarget->hasSSE1())
1845 } else if (!MemcpyStrSrc && Size >= 8 &&
1846 !Subtarget->is64Bit() &&
1847 Subtarget->hasSSE2()) {
1848 // Do not use f64 to lower memcpy if source is string constant. It's
1849 // better to use i32 to avoid the loads.
1853 if (Subtarget->is64Bit() && Size >= 8)
1858 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1860 return X86ScalarSSEf32;
1861 else if (VT == MVT::f64)
1862 return X86ScalarSSEf64;
1867 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1872 *Fast = Subtarget->isUnalignedMemAccessFast();
1876 /// Return the entry encoding for a jump table in the
1877 /// current function. The returned value is a member of the
1878 /// MachineJumpTableInfo::JTEntryKind enum.
1879 unsigned X86TargetLowering::getJumpTableEncoding() const {
1880 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1882 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1883 Subtarget->isPICStyleGOT())
1884 return MachineJumpTableInfo::EK_Custom32;
1886 // Otherwise, use the normal jump table encoding heuristics.
1887 return TargetLowering::getJumpTableEncoding();
1891 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1892 const MachineBasicBlock *MBB,
1893 unsigned uid,MCContext &Ctx) const{
1894 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1895 Subtarget->isPICStyleGOT());
1896 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1898 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1899 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1902 /// Returns relocation base for the given PIC jumptable.
1903 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1904 SelectionDAG &DAG) const {
1905 if (!Subtarget->is64Bit())
1906 // This doesn't have SDLoc associated with it, but is not really the
1907 // same as a Register.
1908 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1912 /// This returns the relocation base for the given PIC jumptable,
1913 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1914 const MCExpr *X86TargetLowering::
1915 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1916 MCContext &Ctx) const {
1917 // X86-64 uses RIP relative addressing based on the jump table label.
1918 if (Subtarget->isPICStyleRIPRel())
1919 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1921 // Otherwise, the reference is relative to the PIC base.
1922 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1925 // FIXME: Why this routine is here? Move to RegInfo!
1926 std::pair<const TargetRegisterClass*, uint8_t>
1927 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1928 const TargetRegisterClass *RRC = nullptr;
1930 switch (VT.SimpleTy) {
1932 return TargetLowering::findRepresentativeClass(VT);
1933 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1934 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1937 RRC = &X86::VR64RegClass;
1939 case MVT::f32: case MVT::f64:
1940 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1941 case MVT::v4f32: case MVT::v2f64:
1942 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1944 RRC = &X86::VR128RegClass;
1947 return std::make_pair(RRC, Cost);
1950 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1951 unsigned &Offset) const {
1952 if (!Subtarget->isTargetLinux())
1955 if (Subtarget->is64Bit()) {
1956 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1958 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1970 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1971 unsigned DestAS) const {
1972 assert(SrcAS != DestAS && "Expected different address spaces!");
1974 return SrcAS < 256 && DestAS < 256;
1977 //===----------------------------------------------------------------------===//
1978 // Return Value Calling Convention Implementation
1979 //===----------------------------------------------------------------------===//
1981 #include "X86GenCallingConv.inc"
1984 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1985 MachineFunction &MF, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 LLVMContext &Context) const {
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1990 return CCInfo.CheckReturn(Outs, RetCC_X86);
1993 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1994 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1999 X86TargetLowering::LowerReturn(SDValue Chain,
2000 CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::OutputArg> &Outs,
2002 const SmallVectorImpl<SDValue> &OutVals,
2003 SDLoc dl, SelectionDAG &DAG) const {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2007 SmallVector<CCValAssign, 16> RVLocs;
2008 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2009 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2012 SmallVector<SDValue, 6> RetOps;
2013 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2014 // Operand #1 = Bytes To Pop
2015 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2018 // Copy the result values into the output registers.
2019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2020 CCValAssign &VA = RVLocs[i];
2021 assert(VA.isRegLoc() && "Can only return in registers!");
2022 SDValue ValToCopy = OutVals[i];
2023 EVT ValVT = ValToCopy.getValueType();
2025 // Promote values to the appropriate types.
2026 if (VA.getLocInfo() == CCValAssign::SExt)
2027 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::ZExt)
2029 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::AExt)
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // The x86-64 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // Win32 requires us to put the sret argument to %eax as well.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2091 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2092 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2095 unsigned Reg = FuncInfo->getSRetReturnReg();
2097 "SRetReturnReg should have been set in LowerFormalArguments().");
2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2107 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getValVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2203 isScalarFPTypeInSSEReg(VA.getValVT()))
2206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2207 CopyVT, InFlag).getValue(1);
2208 SDValue Val = Chain.getValue(0);
2210 if (CopyVT != VA.getValVT())
2211 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2212 // This truncation won't change the value.
2213 DAG.getIntPtrConstant(1));
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 MachinePointerInfo(), MachinePointerInfo());
2280 /// Return true if the calling convention is one that
2281 /// supports tail call optimization.
2282 static bool IsTailCallConvention(CallingConv::ID CC) {
2283 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2284 CC == CallingConv::HiPE);
2287 /// \brief Return true if the calling convention is a C calling convention.
2288 static bool IsCCallConvention(CallingConv::ID CC) {
2289 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2290 CC == CallingConv::X86_64_SysV);
2293 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2294 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2298 CallingConv::ID CalleeCC = CS.getCallingConv();
2299 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2305 /// Return true if the function is being made into
2306 /// a tailcall target by changing its ABI.
2307 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2308 bool GuaranteedTailCallOpt) {
2309 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2313 X86TargetLowering::LowerMemArgument(SDValue Chain,
2314 CallingConv::ID CallConv,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 const CCValAssign &VA,
2318 MachineFrameInfo *MFI,
2320 // Create the nodes corresponding to a load from this parameter slot.
2321 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2322 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2323 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2324 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2327 // If value is passed by pointer we have address passed instead of the value
2329 if (VA.getLocInfo() == CCValAssign::Indirect)
2330 ValVT = VA.getLocVT();
2332 ValVT = VA.getValVT();
2334 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2335 // changed with more analysis.
2336 // In case of tail call optimization mark all arguments mutable. Since they
2337 // could be overwritten by lowering of arguments in case of a tail call.
2338 if (Flags.isByVal()) {
2339 unsigned Bytes = Flags.getByValSize();
2340 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2341 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2342 return DAG.getFrameIndex(FI, getPointerTy());
2344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2345 VA.getLocMemOffset(), isImmutable);
2346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2347 return DAG.getLoad(ValVT, dl, Chain, FIN,
2348 MachinePointerInfo::getFixedStack(FI),
2349 false, false, false, 0);
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2355 const X86Subtarget *Subtarget) {
2356 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 static const MCPhysReg GPR64ArgRegsWin64[] = {
2360 X86::RCX, X86::RDX, X86::R8, X86::R9
2362 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2365 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2366 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2368 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2371 // FIXME: Get this from tablegen.
2372 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2373 CallingConv::ID CallConv,
2374 const X86Subtarget *Subtarget) {
2375 assert(Subtarget->is64Bit());
2376 if (Subtarget->isCallingConvWin64(CallConv)) {
2377 // The XMM registers which might contain var arg parameters are shadowed
2378 // in their paired GPR. So we only need to save the GPR to their home
2380 // TODO: __vectorcall will change this.
2384 const Function *Fn = MF.getFunction();
2385 bool NoImplicitFloatOps = Fn->getAttributes().
2386 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2387 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2388 "SSE register cannot be used when SSE is disabled!");
2389 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2390 !Subtarget->hasSSE1())
2391 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2395 static const MCPhysReg XMMArgRegs64Bit[] = {
2396 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2397 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2399 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2404 CallingConv::ID CallConv,
2406 const SmallVectorImpl<ISD::InputArg> &Ins,
2409 SmallVectorImpl<SDValue> &InVals)
2411 MachineFunction &MF = DAG.getMachineFunction();
2412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2414 const Function* Fn = MF.getFunction();
2415 if (Fn->hasExternalLinkage() &&
2416 Subtarget->isTargetCygMing() &&
2417 Fn->getName() == "main")
2418 FuncInfo->setForceFramePointer(true);
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 bool Is64Bit = Subtarget->is64Bit();
2422 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2424 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2425 "Var args not supported with calling convention fastcc, ghc or hipe");
2427 // Assign locations to all of the incoming arguments.
2428 SmallVector<CCValAssign, 16> ArgLocs;
2429 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2431 // Allocate shadow area for Win64
2433 CCInfo.AllocateStack(32, 8);
2435 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2437 unsigned LastVal = ~0U;
2439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2440 CCValAssign &VA = ArgLocs[i];
2441 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2443 assert(VA.getValNo() != LastVal &&
2444 "Don't support value assigned to multiple locs yet");
2446 LastVal = VA.getValNo();
2448 if (VA.isRegLoc()) {
2449 EVT RegVT = VA.getLocVT();
2450 const TargetRegisterClass *RC;
2451 if (RegVT == MVT::i32)
2452 RC = &X86::GR32RegClass;
2453 else if (Is64Bit && RegVT == MVT::i64)
2454 RC = &X86::GR64RegClass;
2455 else if (RegVT == MVT::f32)
2456 RC = &X86::FR32RegClass;
2457 else if (RegVT == MVT::f64)
2458 RC = &X86::FR64RegClass;
2459 else if (RegVT.is512BitVector())
2460 RC = &X86::VR512RegClass;
2461 else if (RegVT.is256BitVector())
2462 RC = &X86::VR256RegClass;
2463 else if (RegVT.is128BitVector())
2464 RC = &X86::VR128RegClass;
2465 else if (RegVT == MVT::x86mmx)
2466 RC = &X86::VR64RegClass;
2467 else if (RegVT == MVT::i1)
2468 RC = &X86::VK1RegClass;
2469 else if (RegVT == MVT::v8i1)
2470 RC = &X86::VK8RegClass;
2471 else if (RegVT == MVT::v16i1)
2472 RC = &X86::VK16RegClass;
2473 else if (RegVT == MVT::v32i1)
2474 RC = &X86::VK32RegClass;
2475 else if (RegVT == MVT::v64i1)
2476 RC = &X86::VK64RegClass;
2478 llvm_unreachable("Unknown argument type!");
2480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2483 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2484 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2486 if (VA.getLocInfo() == CCValAssign::SExt)
2487 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2488 DAG.getValueType(VA.getValVT()));
2489 else if (VA.getLocInfo() == CCValAssign::ZExt)
2490 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2491 DAG.getValueType(VA.getValVT()));
2492 else if (VA.getLocInfo() == CCValAssign::BCvt)
2493 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2495 if (VA.isExtInLoc()) {
2496 // Handle MMX values passed in XMM regs.
2497 if (RegVT.isVector())
2498 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2500 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2503 assert(VA.isMemLoc());
2504 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2507 // If value is passed via pointer - do a load.
2508 if (VA.getLocInfo() == CCValAssign::Indirect)
2509 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2510 MachinePointerInfo(), false, false, false, 0);
2512 InVals.push_back(ArgValue);
2515 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 // The x86-64 ABIs require that for returning structs by value we copy
2518 // the sret argument into %rax/%eax (depending on ABI) for the return.
2519 // Win32 requires us to put the sret argument to %eax as well.
2520 // Save the argument into a virtual register so that we can access it
2521 // from the return points.
2522 if (Ins[i].Flags.isSRet()) {
2523 unsigned Reg = FuncInfo->getSRetReturnReg();
2525 MVT PtrTy = getPointerTy();
2526 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2527 FuncInfo->setSRetReturnReg(Reg);
2529 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2536 unsigned StackSize = CCInfo.getNextStackOffset();
2537 // Align stack specially for tail calls.
2538 if (FuncIsMadeTailCallSafe(CallConv,
2539 MF.getTarget().Options.GuaranteedTailCallOpt))
2540 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2542 // If the function takes variable number of arguments, make a frame index for
2543 // the start of the first vararg value... for expansion of llvm.va_start. We
2544 // can skip this if there are no va_start calls.
2545 if (MFI->hasVAStart() &&
2546 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2547 CallConv != CallingConv::X86_ThisCall))) {
2548 FuncInfo->setVarArgsFrameIndex(
2549 MFI->CreateFixedObject(1, StackSize, true));
2552 // Figure out if XMM registers are in use.
2553 assert(!(MF.getTarget().Options.UseSoftFloat &&
2554 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2555 Attribute::NoImplicitFloat)) &&
2556 "SSE register cannot be used when SSE is disabled!");
2558 // 64-bit calling conventions support varargs and register parameters, so we
2559 // have to do extra work to spill them in the prologue.
2560 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2561 // Find the first unallocated argument registers.
2562 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2563 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2564 unsigned NumIntRegs =
2565 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2566 unsigned NumXMMRegs =
2567 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2568 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2569 "SSE register cannot be used when SSE is disabled!");
2571 // Gather all the live in physical registers.
2572 SmallVector<SDValue, 6> LiveGPRs;
2573 SmallVector<SDValue, 8> LiveXMMRegs;
2575 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2576 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2578 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2580 if (!ArgXMMs.empty()) {
2581 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2582 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2583 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2584 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2585 LiveXMMRegs.push_back(
2586 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2591 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2592 // Get to the caller-allocated home save location. Add 8 to account
2593 // for the return address.
2594 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2595 FuncInfo->setRegSaveFrameIndex(
2596 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2597 // Fixup to set vararg frame on shadow area (4 x i64).
2599 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2601 // For X86-64, if there are vararg parameters that are passed via
2602 // registers, then we must store them to their spots on the stack so
2603 // they may be loaded by deferencing the result of va_next.
2604 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2605 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2606 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2607 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2610 // Store the integer parameter registers.
2611 SmallVector<SDValue, 8> MemOps;
2612 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2614 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2615 for (SDValue Val : LiveGPRs) {
2616 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2617 DAG.getIntPtrConstant(Offset));
2619 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2620 MachinePointerInfo::getFixedStack(
2621 FuncInfo->getRegSaveFrameIndex(), Offset),
2623 MemOps.push_back(Store);
2627 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2628 // Now store the XMM (fp + vector) parameter registers.
2629 SmallVector<SDValue, 12> SaveXMMOps;
2630 SaveXMMOps.push_back(Chain);
2631 SaveXMMOps.push_back(ALVal);
2632 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2633 FuncInfo->getRegSaveFrameIndex()));
2634 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2635 FuncInfo->getVarArgsFPOffset()));
2636 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2638 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2639 MVT::Other, SaveXMMOps));
2642 if (!MemOps.empty())
2643 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2646 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2647 // Find the largest legal vector type.
2648 MVT VecVT = MVT::Other;
2649 // FIXME: Only some x86_32 calling conventions support AVX512.
2650 if (Subtarget->hasAVX512() &&
2651 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2652 CallConv == CallingConv::Intel_OCL_BI)))
2653 VecVT = MVT::v16f32;
2654 else if (Subtarget->hasAVX())
2656 else if (Subtarget->hasSSE2())
2659 // We forward some GPRs and some vector types.
2660 SmallVector<MVT, 2> RegParmTypes;
2661 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2662 RegParmTypes.push_back(IntVT);
2663 if (VecVT != MVT::Other)
2664 RegParmTypes.push_back(VecVT);
2666 // Compute the set of forwarded registers. The rest are scratch.
2667 SmallVectorImpl<ForwardedRegister> &Forwards =
2668 FuncInfo->getForwardedMustTailRegParms();
2669 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2671 // Conservatively forward AL on x86_64, since it might be used for varargs.
2672 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2673 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2674 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2677 // Copy all forwards from physical to virtual registers.
2678 for (ForwardedRegister &F : Forwards) {
2679 // FIXME: Can we use a less constrained schedule?
2680 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2681 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2682 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2686 // Some CCs need callee pop.
2687 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2688 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2689 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2691 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2692 // If this is an sret function, the return should pop the hidden pointer.
2693 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2694 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2695 argsAreStructReturn(Ins) == StackStructReturn)
2696 FuncInfo->setBytesToPopOnReturn(4);
2700 // RegSaveFrameIndex is X86-64 only.
2701 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2702 if (CallConv == CallingConv::X86_FastCall ||
2703 CallConv == CallingConv::X86_ThisCall)
2704 // fastcc functions can't have varargs.
2705 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2708 FuncInfo->setArgumentStackSize(StackSize);
2714 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2715 SDValue StackPtr, SDValue Arg,
2716 SDLoc dl, SelectionDAG &DAG,
2717 const CCValAssign &VA,
2718 ISD::ArgFlagsTy Flags) const {
2719 unsigned LocMemOffset = VA.getLocMemOffset();
2720 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2721 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2722 if (Flags.isByVal())
2723 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2725 return DAG.getStore(Chain, dl, Arg, PtrOff,
2726 MachinePointerInfo::getStack(LocMemOffset),
2730 /// Emit a load of return address if tail call
2731 /// optimization is performed and it is required.
2733 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2734 SDValue &OutRetAddr, SDValue Chain,
2735 bool IsTailCall, bool Is64Bit,
2736 int FPDiff, SDLoc dl) const {
2737 // Adjust the Return address stack slot.
2738 EVT VT = getPointerTy();
2739 OutRetAddr = getReturnAddressFrameIndex(DAG);
2741 // Load the "old" Return address.
2742 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2743 false, false, false, 0);
2744 return SDValue(OutRetAddr.getNode(), 1);
2747 /// Emit a store of the return address if tail call
2748 /// optimization is performed and it is required (FPDiff!=0).
2749 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2750 SDValue Chain, SDValue RetAddrFrIdx,
2751 EVT PtrVT, unsigned SlotSize,
2752 int FPDiff, SDLoc dl) {
2753 // Store the return address to the appropriate stack slot.
2754 if (!FPDiff) return Chain;
2755 // Calculate the new stack slot for the return address.
2756 int NewReturnAddrFI =
2757 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2759 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2760 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2761 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2767 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2768 SmallVectorImpl<SDValue> &InVals) const {
2769 SelectionDAG &DAG = CLI.DAG;
2771 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2772 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2773 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2774 SDValue Chain = CLI.Chain;
2775 SDValue Callee = CLI.Callee;
2776 CallingConv::ID CallConv = CLI.CallConv;
2777 bool &isTailCall = CLI.IsTailCall;
2778 bool isVarArg = CLI.IsVarArg;
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 bool Is64Bit = Subtarget->is64Bit();
2782 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2783 StructReturnType SR = callIsStructReturn(Outs);
2784 bool IsSibcall = false;
2785 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2787 if (MF.getTarget().Options.DisableTailCalls)
2790 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2792 // Force this to be a tail call. The verifier rules are enough to ensure
2793 // that we can lower this successfully without moving the return address
2796 } else if (isTailCall) {
2797 // Check if it's really possible to do a tail call.
2798 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2799 isVarArg, SR != NotStructReturn,
2800 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2801 Outs, OutVals, Ins, DAG);
2803 // Sibcalls are automatically detected tailcalls which do not require
2805 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2812 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2813 "Var args not supported with calling convention fastcc, ghc or hipe");
2815 // Analyze operands of the call, assigning locations to each operand.
2816 SmallVector<CCValAssign, 16> ArgLocs;
2817 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2821 CCInfo.AllocateStack(32, 8);
2823 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 // Get a count of how many bytes are to be pushed on the stack.
2826 unsigned NumBytes = CCInfo.getNextStackOffset();
2828 // This is a sibcall. The memory operands are available in caller's
2829 // own caller's stack.
2831 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2832 IsTailCallConvention(CallConv))
2833 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2836 if (isTailCall && !IsSibcall && !IsMustTail) {
2837 // Lower arguments at fp - stackoffset + fpdiff.
2838 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2840 FPDiff = NumBytesCallerPushed - NumBytes;
2842 // Set the delta of movement of the returnaddr stackslot.
2843 // But only set if delta is greater than previous delta.
2844 if (FPDiff < X86Info->getTCReturnAddrDelta())
2845 X86Info->setTCReturnAddrDelta(FPDiff);
2848 unsigned NumBytesToPush = NumBytes;
2849 unsigned NumBytesToPop = NumBytes;
2851 // If we have an inalloca argument, all stack space has already been allocated
2852 // for us and be right at the top of the stack. We don't support multiple
2853 // arguments passed in memory when using inalloca.
2854 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2856 if (!ArgLocs.back().isMemLoc())
2857 report_fatal_error("cannot use inalloca attribute on a register "
2859 if (ArgLocs.back().getLocMemOffset() != 0)
2860 report_fatal_error("any parameter with the inalloca attribute must be "
2861 "the only memory argument");
2865 Chain = DAG.getCALLSEQ_START(
2866 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2868 SDValue RetAddrFrIdx;
2869 // Load return address for tail calls.
2870 if (isTailCall && FPDiff)
2871 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2872 Is64Bit, FPDiff, dl);
2874 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2875 SmallVector<SDValue, 8> MemOpChains;
2878 // Walk the register/memloc assignments, inserting copies/loads. In the case
2879 // of tail call optimization arguments are handle later.
2880 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2881 DAG.getSubtarget().getRegisterInfo());
2882 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2883 // Skip inalloca arguments, they have already been written.
2884 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2885 if (Flags.isInAlloca())
2888 CCValAssign &VA = ArgLocs[i];
2889 EVT RegVT = VA.getLocVT();
2890 SDValue Arg = OutVals[i];
2891 bool isByVal = Flags.isByVal();
2893 // Promote the value if needed.
2894 switch (VA.getLocInfo()) {
2895 default: llvm_unreachable("Unknown loc info!");
2896 case CCValAssign::Full: break;
2897 case CCValAssign::SExt:
2898 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2900 case CCValAssign::ZExt:
2901 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2903 case CCValAssign::AExt:
2904 if (RegVT.is128BitVector()) {
2905 // Special case: passing MMX values in XMM registers.
2906 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2907 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2908 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2910 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2912 case CCValAssign::BCvt:
2913 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2915 case CCValAssign::Indirect: {
2916 // Store the argument.
2917 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2918 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2919 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2920 MachinePointerInfo::getFixedStack(FI),
2927 if (VA.isRegLoc()) {
2928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2929 if (isVarArg && IsWin64) {
2930 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2931 // shadow reg if callee is a varargs function.
2932 unsigned ShadowReg = 0;
2933 switch (VA.getLocReg()) {
2934 case X86::XMM0: ShadowReg = X86::RCX; break;
2935 case X86::XMM1: ShadowReg = X86::RDX; break;
2936 case X86::XMM2: ShadowReg = X86::R8; break;
2937 case X86::XMM3: ShadowReg = X86::R9; break;
2940 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2943 assert(VA.isMemLoc());
2944 if (!StackPtr.getNode())
2945 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2947 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2948 dl, DAG, VA, Flags));
2952 if (!MemOpChains.empty())
2953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2955 if (Subtarget->isPICStyleGOT()) {
2956 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2962 // If we are tail calling and generating PIC/GOT style code load the
2963 // address of the callee into ECX. The value in ecx is used as target of
2964 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2965 // for tail calls on PIC/GOT architectures. Normally we would just put the
2966 // address of GOT into ebx and then call target@PLT. But for tail calls
2967 // ebx would be restored (since ebx is callee saved) before jumping to the
2970 // Note: The actual moving to ECX is done further down.
2971 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2972 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2973 !G->getGlobal()->hasProtectedVisibility())
2974 Callee = LowerGlobalAddress(Callee, DAG);
2975 else if (isa<ExternalSymbolSDNode>(Callee))
2976 Callee = LowerExternalSymbol(Callee, DAG);
2980 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2981 // From AMD64 ABI document:
2982 // For calls that may call functions that use varargs or stdargs
2983 // (prototype-less calls or calls to functions containing ellipsis (...) in
2984 // the declaration) %al is used as hidden argument to specify the number
2985 // of SSE registers used. The contents of %al do not need to match exactly
2986 // the number of registers, but must be an ubound on the number of SSE
2987 // registers used and is in the range 0 - 8 inclusive.
2989 // Count the number of XMM registers allocated.
2990 static const MCPhysReg XMMArgRegs[] = {
2991 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2992 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2994 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2995 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2996 && "SSE registers cannot be used when SSE is disabled");
2998 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2999 DAG.getConstant(NumXMMRegs, MVT::i8)));
3002 if (isVarArg && IsMustTail) {
3003 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3004 for (const auto &F : Forwards) {
3005 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3006 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3010 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3011 // don't need this because the eligibility check rejects calls that require
3012 // shuffling arguments passed in memory.
3013 if (!IsSibcall && isTailCall) {
3014 // Force all the incoming stack arguments to be loaded from the stack
3015 // before any new outgoing arguments are stored to the stack, because the
3016 // outgoing stack slots may alias the incoming argument stack slots, and
3017 // the alias isn't otherwise explicit. This is slightly more conservative
3018 // than necessary, because it means that each store effectively depends
3019 // on every argument instead of just those arguments it would clobber.
3020 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3022 SmallVector<SDValue, 8> MemOpChains2;
3025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3026 CCValAssign &VA = ArgLocs[i];
3029 assert(VA.isMemLoc());
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // Skip inalloca arguments. They don't require any work.
3033 if (Flags.isInAlloca())
3035 // Create frame index.
3036 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3037 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3038 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3039 FIN = DAG.getFrameIndex(FI, getPointerTy());
3041 if (Flags.isByVal()) {
3042 // Copy relative to framepointer.
3043 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3044 if (!StackPtr.getNode())
3045 StackPtr = DAG.getCopyFromReg(Chain, dl,
3046 RegInfo->getStackRegister(),
3048 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3050 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3054 // Store relative to framepointer.
3055 MemOpChains2.push_back(
3056 DAG.getStore(ArgChain, dl, Arg, FIN,
3057 MachinePointerInfo::getFixedStack(FI),
3062 if (!MemOpChains2.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3065 // Store the return address to the appropriate stack slot.
3066 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3067 getPointerTy(), RegInfo->getSlotSize(),
3071 // Build a sequence of copy-to-reg nodes chained together with token chain
3072 // and flag operands which copy the outgoing args into registers.
3074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3076 RegsToPass[i].second, InFlag);
3077 InFlag = Chain.getValue(1);
3080 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3081 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3082 // In the 64-bit large code model, we have to make all calls
3083 // through a register, since the call instruction's 32-bit
3084 // pc-relative offset may not be large enough to hold the whole
3086 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3087 // If the callee is a GlobalAddress node (quite common, every direct call
3088 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3091 // We should use extra load for direct calls to dllimported functions in
3093 const GlobalValue *GV = G->getGlobal();
3094 if (!GV->hasDLLImportStorageClass()) {
3095 unsigned char OpFlags = 0;
3096 bool ExtraLoad = false;
3097 unsigned WrapperKind = ISD::DELETED_NODE;
3099 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3100 // external symbols most go through the PLT in PIC mode. If the symbol
3101 // has hidden or protected visibility, or if it is static or local, then
3102 // we don't need to use the PLT - we can directly call it.
3103 if (Subtarget->isTargetELF() &&
3104 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3105 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3106 OpFlags = X86II::MO_PLT;
3107 } else if (Subtarget->isPICStyleStubAny() &&
3108 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3109 (!Subtarget->getTargetTriple().isMacOSX() ||
3110 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3111 // PC-relative references to external symbols should go through $stub,
3112 // unless we're building with the leopard linker or later, which
3113 // automatically synthesizes these stubs.
3114 OpFlags = X86II::MO_DARWIN_STUB;
3115 } else if (Subtarget->isPICStyleRIPRel() &&
3116 isa<Function>(GV) &&
3117 cast<Function>(GV)->getAttributes().
3118 hasAttribute(AttributeSet::FunctionIndex,
3119 Attribute::NonLazyBind)) {
3120 // If the function is marked as non-lazy, generate an indirect call
3121 // which loads from the GOT directly. This avoids runtime overhead
3122 // at the cost of eager binding (and one extra byte of encoding).
3123 OpFlags = X86II::MO_GOTPCREL;
3124 WrapperKind = X86ISD::WrapperRIP;
3128 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3129 G->getOffset(), OpFlags);
3131 // Add a wrapper if needed.
3132 if (WrapperKind != ISD::DELETED_NODE)
3133 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3134 // Add extra indirection if needed.
3136 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3137 MachinePointerInfo::getGOT(),
3138 false, false, false, 0);
3140 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3141 unsigned char OpFlags = 0;
3143 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3144 // external symbols should go through the PLT.
3145 if (Subtarget->isTargetELF() &&
3146 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3147 OpFlags = X86II::MO_PLT;
3148 } else if (Subtarget->isPICStyleStubAny() &&
3149 (!Subtarget->getTargetTriple().isMacOSX() ||
3150 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3151 // PC-relative references to external symbols should go through $stub,
3152 // unless we're building with the leopard linker or later, which
3153 // automatically synthesizes these stubs.
3154 OpFlags = X86II::MO_DARWIN_STUB;
3157 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3159 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3160 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3161 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3164 // Returns a chain & a flag for retval copy to use.
3165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3166 SmallVector<SDValue, 8> Ops;
3168 if (!IsSibcall && isTailCall) {
3169 Chain = DAG.getCALLSEQ_END(Chain,
3170 DAG.getIntPtrConstant(NumBytesToPop, true),
3171 DAG.getIntPtrConstant(0, true), InFlag, dl);
3172 InFlag = Chain.getValue(1);
3175 Ops.push_back(Chain);
3176 Ops.push_back(Callee);
3179 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3181 // Add argument registers to the end of the list so that they are known live
3183 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3184 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3185 RegsToPass[i].second.getValueType()));
3187 // Add a register mask operand representing the call-preserved registers.
3188 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3189 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3190 assert(Mask && "Missing call preserved mask for calling convention");
3191 Ops.push_back(DAG.getRegisterMask(Mask));
3193 if (InFlag.getNode())
3194 Ops.push_back(InFlag);
3198 //// If this is the first return lowered for this function, add the regs
3199 //// to the liveout set for the function.
3200 // This isn't right, although it's probably harmless on x86; liveouts
3201 // should be computed from returns not tail calls. Consider a void
3202 // function making a tail call to a function returning int.
3203 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3206 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3207 InFlag = Chain.getValue(1);
3209 // Create the CALLSEQ_END node.
3210 unsigned NumBytesForCalleeToPop;
3211 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3212 DAG.getTarget().Options.GuaranteedTailCallOpt))
3213 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3214 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3215 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3216 SR == StackStructReturn)
3217 // If this is a call to a struct-return function, the callee
3218 // pops the hidden struct pointer, so we have to push it back.
3219 // This is common for Darwin/X86, Linux & Mingw32 targets.
3220 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3221 NumBytesForCalleeToPop = 4;
3223 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3225 // Returns a flag for retval copy to use.
3227 Chain = DAG.getCALLSEQ_END(Chain,
3228 DAG.getIntPtrConstant(NumBytesToPop, true),
3229 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3232 InFlag = Chain.getValue(1);
3235 // Handle result values, copying them out of physregs into vregs that we
3237 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3238 Ins, dl, DAG, InVals);
3241 //===----------------------------------------------------------------------===//
3242 // Fast Calling Convention (tail call) implementation
3243 //===----------------------------------------------------------------------===//
3245 // Like std call, callee cleans arguments, convention except that ECX is
3246 // reserved for storing the tail called function address. Only 2 registers are
3247 // free for argument passing (inreg). Tail call optimization is performed
3249 // * tailcallopt is enabled
3250 // * caller/callee are fastcc
3251 // On X86_64 architecture with GOT-style position independent code only local
3252 // (within module) calls are supported at the moment.
3253 // To keep the stack aligned according to platform abi the function
3254 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3255 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3256 // If a tail called function callee has more arguments than the caller the
3257 // caller needs to make sure that there is room to move the RETADDR to. This is
3258 // achieved by reserving an area the size of the argument delta right after the
3259 // original RETADDR, but before the saved framepointer or the spilled registers
3260 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3272 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3273 /// for a 16 byte align requirement.
3275 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3276 SelectionDAG& DAG) const {
3277 MachineFunction &MF = DAG.getMachineFunction();
3278 const TargetMachine &TM = MF.getTarget();
3279 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3280 TM.getSubtargetImpl()->getRegisterInfo());
3281 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3282 unsigned StackAlignment = TFI.getStackAlignment();
3283 uint64_t AlignMask = StackAlignment - 1;
3284 int64_t Offset = StackSize;
3285 unsigned SlotSize = RegInfo->getSlotSize();
3286 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3287 // Number smaller than 12 so just add the difference.
3288 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3290 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3291 Offset = ((~AlignMask) & Offset) + StackAlignment +
3292 (StackAlignment-SlotSize);
3297 /// MatchingStackOffset - Return true if the given stack call argument is
3298 /// already available in the same position (relatively) of the caller's
3299 /// incoming argument stack.
3301 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3302 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3303 const X86InstrInfo *TII) {
3304 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3306 if (Arg.getOpcode() == ISD::CopyFromReg) {
3307 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3308 if (!TargetRegisterInfo::isVirtualRegister(VR))
3310 MachineInstr *Def = MRI->getVRegDef(VR);
3313 if (!Flags.isByVal()) {
3314 if (!TII->isLoadFromStackSlot(Def, FI))
3317 unsigned Opcode = Def->getOpcode();
3318 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3319 Def->getOperand(1).isFI()) {
3320 FI = Def->getOperand(1).getIndex();
3321 Bytes = Flags.getByValSize();
3325 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3326 if (Flags.isByVal())
3327 // ByVal argument is passed in as a pointer but it's now being
3328 // dereferenced. e.g.
3329 // define @foo(%struct.X* %A) {
3330 // tail call @bar(%struct.X* byval %A)
3333 SDValue Ptr = Ld->getBasePtr();
3334 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3337 FI = FINode->getIndex();
3338 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3339 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3340 FI = FINode->getIndex();
3341 Bytes = Flags.getByValSize();
3345 assert(FI != INT_MAX);
3346 if (!MFI->isFixedObjectIndex(FI))
3348 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3351 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3352 /// for tail call optimization. Targets which want to do tail call
3353 /// optimization should implement this function.
3355 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3356 CallingConv::ID CalleeCC,
3358 bool isCalleeStructRet,
3359 bool isCallerStructRet,
3361 const SmallVectorImpl<ISD::OutputArg> &Outs,
3362 const SmallVectorImpl<SDValue> &OutVals,
3363 const SmallVectorImpl<ISD::InputArg> &Ins,
3364 SelectionDAG &DAG) const {
3365 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3368 // If -tailcallopt is specified, make fastcc functions tail-callable.
3369 const MachineFunction &MF = DAG.getMachineFunction();
3370 const Function *CallerF = MF.getFunction();
3372 // If the function return type is x86_fp80 and the callee return type is not,
3373 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3374 // perform a tailcall optimization here.
3375 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3378 CallingConv::ID CallerCC = CallerF->getCallingConv();
3379 bool CCMatch = CallerCC == CalleeCC;
3380 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3381 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3383 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3384 if (IsTailCallConvention(CalleeCC) && CCMatch)
3389 // Look for obvious safe cases to perform tail call optimization that do not
3390 // require ABI changes. This is what gcc calls sibcall.
3392 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3393 // emit a special epilogue.
3394 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3395 DAG.getSubtarget().getRegisterInfo());
3396 if (RegInfo->needsStackRealignment(MF))
3399 // Also avoid sibcall optimization if either caller or callee uses struct
3400 // return semantics.
3401 if (isCalleeStructRet || isCallerStructRet)
3404 // An stdcall/thiscall caller is expected to clean up its arguments; the
3405 // callee isn't going to do that.
3406 // FIXME: this is more restrictive than needed. We could produce a tailcall
3407 // when the stack adjustment matches. For example, with a thiscall that takes
3408 // only one argument.
3409 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3410 CallerCC == CallingConv::X86_ThisCall))
3413 // Do not sibcall optimize vararg calls unless all arguments are passed via
3415 if (isVarArg && !Outs.empty()) {
3417 // Optimizing for varargs on Win64 is unlikely to be safe without
3418 // additional testing.
3419 if (IsCalleeWin64 || IsCallerWin64)
3422 SmallVector<CCValAssign, 16> ArgLocs;
3423 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3426 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3427 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3428 if (!ArgLocs[i].isRegLoc())
3432 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3433 // stack. Therefore, if it's not used by the call it is not safe to optimize
3434 // this into a sibcall.
3435 bool Unused = false;
3436 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3443 SmallVector<CCValAssign, 16> RVLocs;
3444 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3446 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3447 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3448 CCValAssign &VA = RVLocs[i];
3449 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3454 // If the calling conventions do not match, then we'd better make sure the
3455 // results are returned in the same way as what the caller expects.
3457 SmallVector<CCValAssign, 16> RVLocs1;
3458 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3460 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3462 SmallVector<CCValAssign, 16> RVLocs2;
3463 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3465 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3467 if (RVLocs1.size() != RVLocs2.size())
3469 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3470 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3472 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3474 if (RVLocs1[i].isRegLoc()) {
3475 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3478 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3484 // If the callee takes no arguments then go on to check the results of the
3486 if (!Outs.empty()) {
3487 // Check if stack adjustment is needed. For now, do not do this if any
3488 // argument is passed on the stack.
3489 SmallVector<CCValAssign, 16> ArgLocs;
3490 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3493 // Allocate shadow area for Win64
3495 CCInfo.AllocateStack(32, 8);
3497 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3498 if (CCInfo.getNextStackOffset()) {
3499 MachineFunction &MF = DAG.getMachineFunction();
3500 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3503 // Check if the arguments are already laid out in the right way as
3504 // the caller's fixed stack objects.
3505 MachineFrameInfo *MFI = MF.getFrameInfo();
3506 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3507 const X86InstrInfo *TII =
3508 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3509 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3510 CCValAssign &VA = ArgLocs[i];
3511 SDValue Arg = OutVals[i];
3512 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3513 if (VA.getLocInfo() == CCValAssign::Indirect)
3515 if (!VA.isRegLoc()) {
3516 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3523 // If the tailcall address may be in a register, then make sure it's
3524 // possible to register allocate for it. In 32-bit, the call address can
3525 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3526 // callee-saved registers are restored. These happen to be the same
3527 // registers used to pass 'inreg' arguments so watch out for those.
3528 if (!Subtarget->is64Bit() &&
3529 ((!isa<GlobalAddressSDNode>(Callee) &&
3530 !isa<ExternalSymbolSDNode>(Callee)) ||
3531 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3532 unsigned NumInRegs = 0;
3533 // In PIC we need an extra register to formulate the address computation
3535 unsigned MaxInRegs =
3536 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3538 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3539 CCValAssign &VA = ArgLocs[i];
3542 unsigned Reg = VA.getLocReg();
3545 case X86::EAX: case X86::EDX: case X86::ECX:
3546 if (++NumInRegs == MaxInRegs)
3558 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3559 const TargetLibraryInfo *libInfo) const {
3560 return X86::createFastISel(funcInfo, libInfo);
3563 //===----------------------------------------------------------------------===//
3564 // Other Lowering Hooks
3565 //===----------------------------------------------------------------------===//
3567 static bool MayFoldLoad(SDValue Op) {
3568 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3571 static bool MayFoldIntoStore(SDValue Op) {
3572 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3575 static bool isTargetShuffle(unsigned Opcode) {
3577 default: return false;
3578 case X86ISD::BLENDI:
3579 case X86ISD::PSHUFB:
3580 case X86ISD::PSHUFD:
3581 case X86ISD::PSHUFHW:
3582 case X86ISD::PSHUFLW:
3584 case X86ISD::PALIGNR:
3585 case X86ISD::MOVLHPS:
3586 case X86ISD::MOVLHPD:
3587 case X86ISD::MOVHLPS:
3588 case X86ISD::MOVLPS:
3589 case X86ISD::MOVLPD:
3590 case X86ISD::MOVSHDUP:
3591 case X86ISD::MOVSLDUP:
3592 case X86ISD::MOVDDUP:
3595 case X86ISD::UNPCKL:
3596 case X86ISD::UNPCKH:
3597 case X86ISD::VPERMILPI:
3598 case X86ISD::VPERM2X128:
3599 case X86ISD::VPERMI:
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVSHDUP:
3609 case X86ISD::MOVSLDUP:
3610 case X86ISD::MOVDDUP:
3611 return DAG.getNode(Opc, dl, VT, V1);
3615 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3616 SDValue V1, unsigned TargetMask,
3617 SelectionDAG &DAG) {
3619 default: llvm_unreachable("Unknown x86 shuffle node");
3620 case X86ISD::PSHUFD:
3621 case X86ISD::PSHUFHW:
3622 case X86ISD::PSHUFLW:
3623 case X86ISD::VPERMILPI:
3624 case X86ISD::VPERMI:
3625 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3629 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3630 SDValue V1, SDValue V2, unsigned TargetMask,
3631 SelectionDAG &DAG) {
3633 default: llvm_unreachable("Unknown x86 shuffle node");
3634 case X86ISD::PALIGNR:
3635 case X86ISD::VALIGN:
3637 case X86ISD::VPERM2X128:
3638 return DAG.getNode(Opc, dl, VT, V1, V2,
3639 DAG.getConstant(TargetMask, MVT::i8));
3643 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3644 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3646 default: llvm_unreachable("Unknown x86 shuffle node");
3647 case X86ISD::MOVLHPS:
3648 case X86ISD::MOVLHPD:
3649 case X86ISD::MOVHLPS:
3650 case X86ISD::MOVLPS:
3651 case X86ISD::MOVLPD:
3654 case X86ISD::UNPCKL:
3655 case X86ISD::UNPCKH:
3656 return DAG.getNode(Opc, dl, VT, V1, V2);
3660 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3661 MachineFunction &MF = DAG.getMachineFunction();
3662 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3663 DAG.getSubtarget().getRegisterInfo());
3664 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3665 int ReturnAddrIndex = FuncInfo->getRAIndex();
3667 if (ReturnAddrIndex == 0) {
3668 // Set up a frame object for the return address.
3669 unsigned SlotSize = RegInfo->getSlotSize();
3670 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3673 FuncInfo->setRAIndex(ReturnAddrIndex);
3676 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3679 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3680 bool hasSymbolicDisplacement) {
3681 // Offset should fit into 32 bit immediate field.
3682 if (!isInt<32>(Offset))
3685 // If we don't have a symbolic displacement - we don't have any extra
3687 if (!hasSymbolicDisplacement)
3690 // FIXME: Some tweaks might be needed for medium code model.
3691 if (M != CodeModel::Small && M != CodeModel::Kernel)
3694 // For small code model we assume that latest object is 16MB before end of 31
3695 // bits boundary. We may also accept pretty large negative constants knowing
3696 // that all objects are in the positive half of address space.
3697 if (M == CodeModel::Small && Offset < 16*1024*1024)
3700 // For kernel code model we know that all object resist in the negative half
3701 // of 32bits address space. We may not accept negative offsets, since they may
3702 // be just off and we may accept pretty large positive ones.
3703 if (M == CodeModel::Kernel && Offset >= 0)
3709 /// isCalleePop - Determines whether the callee is required to pop its
3710 /// own arguments. Callee pop is necessary to support tail calls.
3711 bool X86::isCalleePop(CallingConv::ID CallingConv,
3712 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3713 switch (CallingConv) {
3716 case CallingConv::X86_StdCall:
3717 case CallingConv::X86_FastCall:
3718 case CallingConv::X86_ThisCall:
3720 case CallingConv::Fast:
3721 case CallingConv::GHC:
3722 case CallingConv::HiPE:
3729 /// \brief Return true if the condition is an unsigned comparison operation.
3730 static bool isX86CCUnsigned(unsigned X86CC) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case X86::COND_E: return true;
3734 case X86::COND_G: return false;
3735 case X86::COND_GE: return false;
3736 case X86::COND_L: return false;
3737 case X86::COND_LE: return false;
3738 case X86::COND_NE: return true;
3739 case X86::COND_B: return true;
3740 case X86::COND_A: return true;
3741 case X86::COND_BE: return true;
3742 case X86::COND_AE: return true;
3744 llvm_unreachable("covered switch fell through?!");
3747 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3748 /// specific condition code, returning the condition code and the LHS/RHS of the
3749 /// comparison to make.
3750 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3751 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3753 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3754 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3755 // X > -1 -> X == 0, jump !sign.
3756 RHS = DAG.getConstant(0, RHS.getValueType());
3757 return X86::COND_NS;
3759 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3760 // X < 0 -> X == 0, jump on sign.
3763 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3765 RHS = DAG.getConstant(0, RHS.getValueType());
3766 return X86::COND_LE;
3770 switch (SetCCOpcode) {
3771 default: llvm_unreachable("Invalid integer condition!");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETGT: return X86::COND_G;
3774 case ISD::SETGE: return X86::COND_GE;
3775 case ISD::SETLT: return X86::COND_L;
3776 case ISD::SETLE: return X86::COND_LE;
3777 case ISD::SETNE: return X86::COND_NE;
3778 case ISD::SETULT: return X86::COND_B;
3779 case ISD::SETUGT: return X86::COND_A;
3780 case ISD::SETULE: return X86::COND_BE;
3781 case ISD::SETUGE: return X86::COND_AE;
3785 // First determine if it is required or is profitable to flip the operands.
3787 // If LHS is a foldable load, but RHS is not, flip the condition.
3788 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3789 !ISD::isNON_EXTLoad(RHS.getNode())) {
3790 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3791 std::swap(LHS, RHS);
3794 switch (SetCCOpcode) {
3800 std::swap(LHS, RHS);
3804 // On a floating point condition, the flags are set as follows:
3806 // 0 | 0 | 0 | X > Y
3807 // 0 | 0 | 1 | X < Y
3808 // 1 | 0 | 0 | X == Y
3809 // 1 | 1 | 1 | unordered
3810 switch (SetCCOpcode) {
3811 default: llvm_unreachable("Condcode should be pre-legalized away");
3813 case ISD::SETEQ: return X86::COND_E;
3814 case ISD::SETOLT: // flipped
3816 case ISD::SETGT: return X86::COND_A;
3817 case ISD::SETOLE: // flipped
3819 case ISD::SETGE: return X86::COND_AE;
3820 case ISD::SETUGT: // flipped
3822 case ISD::SETLT: return X86::COND_B;
3823 case ISD::SETUGE: // flipped
3825 case ISD::SETLE: return X86::COND_BE;
3827 case ISD::SETNE: return X86::COND_NE;
3828 case ISD::SETUO: return X86::COND_P;
3829 case ISD::SETO: return X86::COND_NP;
3831 case ISD::SETUNE: return X86::COND_INVALID;
3835 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3836 /// code. Current x86 isa includes the following FP cmov instructions:
3837 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3838 static bool hasFPCMov(unsigned X86CC) {
3854 /// isFPImmLegal - Returns true if the target can instruction select the
3855 /// specified FP immediate natively. If false, the legalizer will
3856 /// materialize the FP immediate as a load from a constant pool.
3857 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3858 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3859 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3865 /// \brief Returns true if it is beneficial to convert a load of a constant
3866 /// to just the constant itself.
3867 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3869 assert(Ty->isIntegerTy());
3871 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3872 if (BitSize == 0 || BitSize > 64)
3877 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3878 unsigned Index) const {
3879 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3882 return (Index == 0 || Index == ResVT.getVectorNumElements());
3885 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3886 // Speculate cttz only if we can directly use TZCNT.
3887 return Subtarget->hasBMI();
3890 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3891 // Speculate ctlz only if we can directly use LZCNT.
3892 return Subtarget->hasLZCNT();
3895 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3896 /// the specified range (L, H].
3897 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3898 return (Val < 0) || (Val >= Low && Val < Hi);
3901 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3902 /// specified value.
3903 static bool isUndefOrEqual(int Val, int CmpVal) {
3904 return (Val < 0 || Val == CmpVal);
3907 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3908 /// from position Pos and ending in Pos+Size, falls within the specified
3909 /// sequential range (L, L+Pos]. or is undef.
3910 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3911 unsigned Pos, unsigned Size, int Low) {
3912 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3913 if (!isUndefOrEqual(Mask[i], Low))
3918 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3919 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3920 /// operand - by default will match for first operand.
3921 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3922 bool TestSecondOperand = false) {
3923 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3924 VT != MVT::v2f64 && VT != MVT::v2i64)
3927 unsigned NumElems = VT.getVectorNumElements();
3928 unsigned Lo = TestSecondOperand ? NumElems : 0;
3929 unsigned Hi = Lo + NumElems;
3931 for (unsigned i = 0; i < NumElems; ++i)
3932 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3938 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3939 /// is suitable for input to PSHUFHW.
3940 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3941 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3944 // Lower quadword copied in order or undef.
3945 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3948 // Upper quadword shuffled.
3949 for (unsigned i = 4; i != 8; ++i)
3950 if (!isUndefOrInRange(Mask[i], 4, 8))
3953 if (VT == MVT::v16i16) {
3954 // Lower quadword copied in order or undef.
3955 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3958 // Upper quadword shuffled.
3959 for (unsigned i = 12; i != 16; ++i)
3960 if (!isUndefOrInRange(Mask[i], 12, 16))
3967 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3968 /// is suitable for input to PSHUFLW.
3969 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3970 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3973 // Upper quadword copied in order.
3974 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3977 // Lower quadword shuffled.
3978 for (unsigned i = 0; i != 4; ++i)
3979 if (!isUndefOrInRange(Mask[i], 0, 4))
3982 if (VT == MVT::v16i16) {
3983 // Upper quadword copied in order.
3984 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3987 // Lower quadword shuffled.
3988 for (unsigned i = 8; i != 12; ++i)
3989 if (!isUndefOrInRange(Mask[i], 8, 12))
3996 /// \brief Return true if the mask specifies a shuffle of elements that is
3997 /// suitable for input to intralane (palignr) or interlane (valign) vector
3999 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4000 unsigned NumElts = VT.getVectorNumElements();
4001 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4002 unsigned NumLaneElts = NumElts/NumLanes;
4004 // Do not handle 64-bit element shuffles with palignr.
4005 if (NumLaneElts == 2)
4008 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4010 for (i = 0; i != NumLaneElts; ++i) {
4015 // Lane is all undef, go to next lane
4016 if (i == NumLaneElts)
4019 int Start = Mask[i+l];
4021 // Make sure its in this lane in one of the sources
4022 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4023 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4026 // If not lane 0, then we must match lane 0
4027 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4030 // Correct second source to be contiguous with first source
4031 if (Start >= (int)NumElts)
4032 Start -= NumElts - NumLaneElts;
4034 // Make sure we're shifting in the right direction.
4035 if (Start <= (int)(i+l))
4040 // Check the rest of the elements to see if they are consecutive.
4041 for (++i; i != NumLaneElts; ++i) {
4042 int Idx = Mask[i+l];
4044 // Make sure its in this lane
4045 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4046 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4049 // If not lane 0, then we must match lane 0
4050 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4053 if (Idx >= (int)NumElts)
4054 Idx -= NumElts - NumLaneElts;
4056 if (!isUndefOrEqual(Idx, Start+i))
4065 /// \brief Return true if the node specifies a shuffle of elements that is
4066 /// suitable for input to PALIGNR.
4067 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4068 const X86Subtarget *Subtarget) {
4069 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4070 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4071 VT.is512BitVector())
4072 // FIXME: Add AVX512BW.
4075 return isAlignrMask(Mask, VT, false);
4078 /// \brief Return true if the node specifies a shuffle of elements that is
4079 /// suitable for input to VALIGN.
4080 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4081 const X86Subtarget *Subtarget) {
4082 // FIXME: Add AVX512VL.
4083 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4085 return isAlignrMask(Mask, VT, true);
4088 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4089 /// the two vector operands have swapped position.
4090 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4091 unsigned NumElems) {
4092 for (unsigned i = 0; i != NumElems; ++i) {
4096 else if (idx < (int)NumElems)
4097 Mask[i] = idx + NumElems;
4099 Mask[i] = idx - NumElems;
4103 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4104 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4105 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4106 /// reverse of what x86 shuffles want.
4107 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4109 unsigned NumElems = VT.getVectorNumElements();
4110 unsigned NumLanes = VT.getSizeInBits()/128;
4111 unsigned NumLaneElems = NumElems/NumLanes;
4113 if (NumLaneElems != 2 && NumLaneElems != 4)
4116 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4117 bool symetricMaskRequired =
4118 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4120 // VSHUFPSY divides the resulting vector into 4 chunks.
4121 // The sources are also splitted into 4 chunks, and each destination
4122 // chunk must come from a different source chunk.
4124 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4125 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4127 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4128 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4130 // VSHUFPDY divides the resulting vector into 4 chunks.
4131 // The sources are also splitted into 4 chunks, and each destination
4132 // chunk must come from a different source chunk.
4134 // SRC1 => X3 X2 X1 X0
4135 // SRC2 => Y3 Y2 Y1 Y0
4137 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4139 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4140 unsigned HalfLaneElems = NumLaneElems/2;
4141 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4142 for (unsigned i = 0; i != NumLaneElems; ++i) {
4143 int Idx = Mask[i+l];
4144 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4145 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4147 // For VSHUFPSY, the mask of the second half must be the same as the
4148 // first but with the appropriate offsets. This works in the same way as
4149 // VPERMILPS works with masks.
4150 if (!symetricMaskRequired || Idx < 0)
4152 if (MaskVal[i] < 0) {
4153 MaskVal[i] = Idx - l;
4156 if ((signed)(Idx - l) != MaskVal[i])
4164 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4165 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4166 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4167 if (!VT.is128BitVector())
4170 unsigned NumElems = VT.getVectorNumElements();
4175 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4176 return isUndefOrEqual(Mask[0], 6) &&
4177 isUndefOrEqual(Mask[1], 7) &&
4178 isUndefOrEqual(Mask[2], 2) &&
4179 isUndefOrEqual(Mask[3], 3);
4182 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4183 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4185 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4186 if (!VT.is128BitVector())
4189 unsigned NumElems = VT.getVectorNumElements();
4194 return isUndefOrEqual(Mask[0], 2) &&
4195 isUndefOrEqual(Mask[1], 3) &&
4196 isUndefOrEqual(Mask[2], 2) &&
4197 isUndefOrEqual(Mask[3], 3);
4200 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4201 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4202 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4203 if (!VT.is128BitVector())
4206 unsigned NumElems = VT.getVectorNumElements();
4208 if (NumElems != 2 && NumElems != 4)
4211 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4212 if (!isUndefOrEqual(Mask[i], i + NumElems))
4215 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4216 if (!isUndefOrEqual(Mask[i], i))
4222 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4223 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4224 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4225 if (!VT.is128BitVector())
4228 unsigned NumElems = VT.getVectorNumElements();
4230 if (NumElems != 2 && NumElems != 4)
4233 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4234 if (!isUndefOrEqual(Mask[i], i))
4237 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4238 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4244 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4245 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4246 /// i. e: If all but one element come from the same vector.
4247 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4248 // TODO: Deal with AVX's VINSERTPS
4249 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4252 unsigned CorrectPosV1 = 0;
4253 unsigned CorrectPosV2 = 0;
4254 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4255 if (Mask[i] == -1) {
4263 else if (Mask[i] == i + 4)
4267 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4268 // We have 3 elements (undefs count as elements from any vector) from one
4269 // vector, and one from another.
4276 // Some special combinations that can be optimized.
4279 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4280 SelectionDAG &DAG) {
4281 MVT VT = SVOp->getSimpleValueType(0);
4284 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4287 ArrayRef<int> Mask = SVOp->getMask();
4289 // These are the special masks that may be optimized.
4290 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4291 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4292 bool MatchEvenMask = true;
4293 bool MatchOddMask = true;
4294 for (int i=0; i<8; ++i) {
4295 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4296 MatchEvenMask = false;
4297 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4298 MatchOddMask = false;
4301 if (!MatchEvenMask && !MatchOddMask)
4304 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4306 SDValue Op0 = SVOp->getOperand(0);
4307 SDValue Op1 = SVOp->getOperand(1);
4309 if (MatchEvenMask) {
4310 // Shift the second operand right to 32 bits.
4311 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4312 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4314 // Shift the first operand left to 32 bits.
4315 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4316 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4318 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4319 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4322 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4324 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4325 bool HasInt256, bool V2IsSplat = false) {
4327 assert(VT.getSizeInBits() >= 128 &&
4328 "Unsupported vector type for unpckl");
4330 unsigned NumElts = VT.getVectorNumElements();
4331 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4332 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4335 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4336 "Unsupported vector type for unpckh");
4338 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4339 unsigned NumLanes = VT.getSizeInBits()/128;
4340 unsigned NumLaneElts = NumElts/NumLanes;
4342 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4343 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4344 int BitI = Mask[l+i];
4345 int BitI1 = Mask[l+i+1];
4346 if (!isUndefOrEqual(BitI, j))
4349 if (!isUndefOrEqual(BitI1, NumElts))
4352 if (!isUndefOrEqual(BitI1, j + NumElts))
4361 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4362 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4363 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4364 bool HasInt256, bool V2IsSplat = false) {
4365 assert(VT.getSizeInBits() >= 128 &&
4366 "Unsupported vector type for unpckh");
4368 unsigned NumElts = VT.getVectorNumElements();
4369 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4370 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4373 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4374 "Unsupported vector type for unpckh");
4376 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4377 unsigned NumLanes = VT.getSizeInBits()/128;
4378 unsigned NumLaneElts = NumElts/NumLanes;
4380 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4381 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4382 int BitI = Mask[l+i];
4383 int BitI1 = Mask[l+i+1];
4384 if (!isUndefOrEqual(BitI, j))
4387 if (isUndefOrEqual(BitI1, NumElts))
4390 if (!isUndefOrEqual(BitI1, j+NumElts))
4398 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4399 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4401 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4402 unsigned NumElts = VT.getVectorNumElements();
4403 bool Is256BitVec = VT.is256BitVector();
4405 if (VT.is512BitVector())
4407 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4408 "Unsupported vector type for unpckh");
4410 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4411 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4414 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4415 // FIXME: Need a better way to get rid of this, there's no latency difference
4416 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4417 // the former later. We should also remove the "_undef" special mask.
4418 if (NumElts == 4 && Is256BitVec)
4421 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4422 // independently on 128-bit lanes.
4423 unsigned NumLanes = VT.getSizeInBits()/128;
4424 unsigned NumLaneElts = NumElts/NumLanes;
4426 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4427 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4428 int BitI = Mask[l+i];
4429 int BitI1 = Mask[l+i+1];
4431 if (!isUndefOrEqual(BitI, j))
4433 if (!isUndefOrEqual(BitI1, j))
4441 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4442 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4444 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (VT.is512BitVector())
4450 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4451 "Unsupported vector type for unpckh");
4453 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4454 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4457 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4458 // independently on 128-bit lanes.
4459 unsigned NumLanes = VT.getSizeInBits()/128;
4460 unsigned NumLaneElts = NumElts/NumLanes;
4462 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4463 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4464 int BitI = Mask[l+i];
4465 int BitI1 = Mask[l+i+1];
4466 if (!isUndefOrEqual(BitI, j))
4468 if (!isUndefOrEqual(BitI1, j))
4475 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4476 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4477 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4478 if (!VT.is512BitVector())
4481 unsigned NumElts = VT.getVectorNumElements();
4482 unsigned HalfSize = NumElts/2;
4483 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4484 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4489 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4490 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4498 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4499 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4500 /// MOVSD, and MOVD, i.e. setting the lowest element.
4501 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4502 if (VT.getVectorElementType().getSizeInBits() < 32)
4504 if (!VT.is128BitVector())
4507 unsigned NumElts = VT.getVectorNumElements();
4509 if (!isUndefOrEqual(Mask[0], NumElts))
4512 for (unsigned i = 1; i != NumElts; ++i)
4513 if (!isUndefOrEqual(Mask[i], i))
4519 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4520 /// as permutations between 128-bit chunks or halves. As an example: this
4522 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4523 /// The first half comes from the second half of V1 and the second half from the
4524 /// the second half of V2.
4525 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4526 if (!HasFp256 || !VT.is256BitVector())
4529 // The shuffle result is divided into half A and half B. In total the two
4530 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4531 // B must come from C, D, E or F.
4532 unsigned HalfSize = VT.getVectorNumElements()/2;
4533 bool MatchA = false, MatchB = false;
4535 // Check if A comes from one of C, D, E, F.
4536 for (unsigned Half = 0; Half != 4; ++Half) {
4537 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4543 // Check if B comes from one of C, D, E, F.
4544 for (unsigned Half = 0; Half != 4; ++Half) {
4545 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4551 return MatchA && MatchB;
4554 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4555 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4556 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4557 MVT VT = SVOp->getSimpleValueType(0);
4559 unsigned HalfSize = VT.getVectorNumElements()/2;
4561 unsigned FstHalf = 0, SndHalf = 0;
4562 for (unsigned i = 0; i < HalfSize; ++i) {
4563 if (SVOp->getMaskElt(i) > 0) {
4564 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4568 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4569 if (SVOp->getMaskElt(i) > 0) {
4570 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4575 return (FstHalf | (SndHalf << 4));
4578 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4579 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4580 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4584 unsigned NumElts = VT.getVectorNumElements();
4586 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4587 for (unsigned i = 0; i != NumElts; ++i) {
4590 Imm8 |= Mask[i] << (i*2);
4595 unsigned LaneSize = 4;
4596 SmallVector<int, 4> MaskVal(LaneSize, -1);
4598 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4599 for (unsigned i = 0; i != LaneSize; ++i) {
4600 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4604 if (MaskVal[i] < 0) {
4605 MaskVal[i] = Mask[i+l] - l;
4606 Imm8 |= MaskVal[i] << (i*2);
4609 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4616 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4617 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4618 /// Note that VPERMIL mask matching is different depending whether theunderlying
4619 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4620 /// to the same elements of the low, but to the higher half of the source.
4621 /// In VPERMILPD the two lanes could be shuffled independently of each other
4622 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4623 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4624 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4625 if (VT.getSizeInBits() < 256 || EltSize < 32)
4627 bool symetricMaskRequired = (EltSize == 32);
4628 unsigned NumElts = VT.getVectorNumElements();
4630 unsigned NumLanes = VT.getSizeInBits()/128;
4631 unsigned LaneSize = NumElts/NumLanes;
4632 // 2 or 4 elements in one lane
4634 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4635 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4636 for (unsigned i = 0; i != LaneSize; ++i) {
4637 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4639 if (symetricMaskRequired) {
4640 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4641 ExpectedMaskVal[i] = Mask[i+l] - l;
4644 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4652 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4653 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4654 /// element of vector 2 and the other elements to come from vector 1 in order.
4655 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4656 bool V2IsSplat = false, bool V2IsUndef = false) {
4657 if (!VT.is128BitVector())
4660 unsigned NumOps = VT.getVectorNumElements();
4661 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4664 if (!isUndefOrEqual(Mask[0], 0))
4667 for (unsigned i = 1; i != NumOps; ++i)
4668 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4669 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4670 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4676 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4677 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4678 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4679 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4680 const X86Subtarget *Subtarget) {
4681 if (!Subtarget->hasSSE3())
4684 unsigned NumElems = VT.getVectorNumElements();
4686 if ((VT.is128BitVector() && NumElems != 4) ||
4687 (VT.is256BitVector() && NumElems != 8) ||
4688 (VT.is512BitVector() && NumElems != 16))
4691 // "i+1" is the value the indexed mask element must have
4692 for (unsigned i = 0; i != NumElems; i += 2)
4693 if (!isUndefOrEqual(Mask[i], i+1) ||
4694 !isUndefOrEqual(Mask[i+1], i+1))
4700 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4701 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4702 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4703 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4704 const X86Subtarget *Subtarget) {
4705 if (!Subtarget->hasSSE3())
4708 unsigned NumElems = VT.getVectorNumElements();
4710 if ((VT.is128BitVector() && NumElems != 4) ||
4711 (VT.is256BitVector() && NumElems != 8) ||
4712 (VT.is512BitVector() && NumElems != 16))
4715 // "i" is the value the indexed mask element must have
4716 for (unsigned i = 0; i != NumElems; i += 2)
4717 if (!isUndefOrEqual(Mask[i], i) ||
4718 !isUndefOrEqual(Mask[i+1], i))
4724 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4725 /// specifies a shuffle of elements that is suitable for input to 256-bit
4726 /// version of MOVDDUP.
4727 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4728 if (!HasFp256 || !VT.is256BitVector())
4731 unsigned NumElts = VT.getVectorNumElements();
4735 for (unsigned i = 0; i != NumElts/2; ++i)
4736 if (!isUndefOrEqual(Mask[i], 0))
4738 for (unsigned i = NumElts/2; i != NumElts; ++i)
4739 if (!isUndefOrEqual(Mask[i], NumElts/2))
4744 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4745 /// specifies a shuffle of elements that is suitable for input to 128-bit
4746 /// version of MOVDDUP.
4747 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4748 if (!VT.is128BitVector())
4751 unsigned e = VT.getVectorNumElements() / 2;
4752 for (unsigned i = 0; i != e; ++i)
4753 if (!isUndefOrEqual(Mask[i], i))
4755 for (unsigned i = 0; i != e; ++i)
4756 if (!isUndefOrEqual(Mask[e+i], i))
4761 /// isVEXTRACTIndex - Return true if the specified
4762 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4763 /// suitable for instruction that extract 128 or 256 bit vectors
4764 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4765 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4766 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4769 // The index should be aligned on a vecWidth-bit boundary.
4771 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4773 MVT VT = N->getSimpleValueType(0);
4774 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4775 bool Result = (Index * ElSize) % vecWidth == 0;
4780 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4781 /// operand specifies a subvector insert that is suitable for input to
4782 /// insertion of 128 or 256-bit subvectors
4783 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4784 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4785 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4787 // The index should be aligned on a vecWidth-bit boundary.
4789 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4791 MVT VT = N->getSimpleValueType(0);
4792 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4793 bool Result = (Index * ElSize) % vecWidth == 0;
4798 bool X86::isVINSERT128Index(SDNode *N) {
4799 return isVINSERTIndex(N, 128);
4802 bool X86::isVINSERT256Index(SDNode *N) {
4803 return isVINSERTIndex(N, 256);
4806 bool X86::isVEXTRACT128Index(SDNode *N) {
4807 return isVEXTRACTIndex(N, 128);
4810 bool X86::isVEXTRACT256Index(SDNode *N) {
4811 return isVEXTRACTIndex(N, 256);
4814 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4815 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4816 /// Handles 128-bit and 256-bit.
4817 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4818 MVT VT = N->getSimpleValueType(0);
4820 assert((VT.getSizeInBits() >= 128) &&
4821 "Unsupported vector type for PSHUF/SHUFP");
4823 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4824 // independently on 128-bit lanes.
4825 unsigned NumElts = VT.getVectorNumElements();
4826 unsigned NumLanes = VT.getSizeInBits()/128;
4827 unsigned NumLaneElts = NumElts/NumLanes;
4829 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4830 "Only supports 2, 4 or 8 elements per lane");
4832 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4834 for (unsigned i = 0; i != NumElts; ++i) {
4835 int Elt = N->getMaskElt(i);
4836 if (Elt < 0) continue;
4837 Elt &= NumLaneElts - 1;
4838 unsigned ShAmt = (i << Shift) % 8;
4839 Mask |= Elt << ShAmt;
4845 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4846 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4847 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4848 MVT VT = N->getSimpleValueType(0);
4850 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4851 "Unsupported vector type for PSHUFHW");
4853 unsigned NumElts = VT.getVectorNumElements();
4856 for (unsigned l = 0; l != NumElts; l += 8) {
4857 // 8 nodes per lane, but we only care about the last 4.
4858 for (unsigned i = 0; i < 4; ++i) {
4859 int Elt = N->getMaskElt(l+i+4);
4860 if (Elt < 0) continue;
4861 Elt &= 0x3; // only 2-bits.
4862 Mask |= Elt << (i * 2);
4869 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4870 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4871 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4872 MVT VT = N->getSimpleValueType(0);
4874 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4875 "Unsupported vector type for PSHUFHW");
4877 unsigned NumElts = VT.getVectorNumElements();
4880 for (unsigned l = 0; l != NumElts; l += 8) {
4881 // 8 nodes per lane, but we only care about the first 4.
4882 for (unsigned i = 0; i < 4; ++i) {
4883 int Elt = N->getMaskElt(l+i);
4884 if (Elt < 0) continue;
4885 Elt &= 0x3; // only 2-bits
4886 Mask |= Elt << (i * 2);
4893 /// \brief Return the appropriate immediate to shuffle the specified
4894 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4895 /// VALIGN (if Interlane is true) instructions.
4896 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4898 MVT VT = SVOp->getSimpleValueType(0);
4899 unsigned EltSize = InterLane ? 1 :
4900 VT.getVectorElementType().getSizeInBits() >> 3;
4902 unsigned NumElts = VT.getVectorNumElements();
4903 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4904 unsigned NumLaneElts = NumElts/NumLanes;
4908 for (i = 0; i != NumElts; ++i) {
4909 Val = SVOp->getMaskElt(i);
4913 if (Val >= (int)NumElts)
4914 Val -= NumElts - NumLaneElts;
4916 assert(Val - i > 0 && "PALIGNR imm should be positive");
4917 return (Val - i) * EltSize;
4920 /// \brief Return the appropriate immediate to shuffle the specified
4921 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4922 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4923 return getShuffleAlignrImmediate(SVOp, false);
4926 /// \brief Return the appropriate immediate to shuffle the specified
4927 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4928 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4929 return getShuffleAlignrImmediate(SVOp, true);
4933 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4934 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4935 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4936 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4939 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4941 MVT VecVT = N->getOperand(0).getSimpleValueType();
4942 MVT ElVT = VecVT.getVectorElementType();
4944 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4945 return Index / NumElemsPerChunk;
4948 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4949 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4950 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4951 llvm_unreachable("Illegal insert subvector for VINSERT");
4954 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4956 MVT VecVT = N->getSimpleValueType(0);
4957 MVT ElVT = VecVT.getVectorElementType();
4959 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4960 return Index / NumElemsPerChunk;
4963 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4964 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4965 /// and VINSERTI128 instructions.
4966 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4967 return getExtractVEXTRACTImmediate(N, 128);
4970 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4971 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4972 /// and VINSERTI64x4 instructions.
4973 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4974 return getExtractVEXTRACTImmediate(N, 256);
4977 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4978 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4979 /// and VINSERTI128 instructions.
4980 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4981 return getInsertVINSERTImmediate(N, 128);
4984 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4985 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4986 /// and VINSERTI64x4 instructions.
4987 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4988 return getInsertVINSERTImmediate(N, 256);
4991 /// isZero - Returns true if Elt is a constant integer zero
4992 static bool isZero(SDValue V) {
4993 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4994 return C && C->isNullValue();
4997 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4999 bool X86::isZeroNode(SDValue Elt) {
5002 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5003 return CFP->getValueAPF().isPosZero();
5007 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5008 /// match movhlps. The lower half elements should come from upper half of
5009 /// V1 (and in order), and the upper half elements should come from the upper
5010 /// half of V2 (and in order).
5011 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5012 if (!VT.is128BitVector())
5014 if (VT.getVectorNumElements() != 4)
5016 for (unsigned i = 0, e = 2; i != e; ++i)
5017 if (!isUndefOrEqual(Mask[i], i+2))
5019 for (unsigned i = 2; i != 4; ++i)
5020 if (!isUndefOrEqual(Mask[i], i+4))
5025 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5026 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5028 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5029 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5031 N = N->getOperand(0).getNode();
5032 if (!ISD::isNON_EXTLoad(N))
5035 *LD = cast<LoadSDNode>(N);
5039 // Test whether the given value is a vector value which will be legalized
5041 static bool WillBeConstantPoolLoad(SDNode *N) {
5042 if (N->getOpcode() != ISD::BUILD_VECTOR)
5045 // Check for any non-constant elements.
5046 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5047 switch (N->getOperand(i).getNode()->getOpcode()) {
5049 case ISD::ConstantFP:
5056 // Vectors of all-zeros and all-ones are materialized with special
5057 // instructions rather than being loaded.
5058 return !ISD::isBuildVectorAllZeros(N) &&
5059 !ISD::isBuildVectorAllOnes(N);
5062 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5063 /// match movlp{s|d}. The lower half elements should come from lower half of
5064 /// V1 (and in order), and the upper half elements should come from the upper
5065 /// half of V2 (and in order). And since V1 will become the source of the
5066 /// MOVLP, it must be either a vector load or a scalar load to vector.
5067 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5068 ArrayRef<int> Mask, MVT VT) {
5069 if (!VT.is128BitVector())
5072 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5074 // Is V2 is a vector load, don't do this transformation. We will try to use
5075 // load folding shufps op.
5076 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5079 unsigned NumElems = VT.getVectorNumElements();
5081 if (NumElems != 2 && NumElems != 4)
5083 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5084 if (!isUndefOrEqual(Mask[i], i))
5086 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5087 if (!isUndefOrEqual(Mask[i], i+NumElems))
5092 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5093 /// to an zero vector.
5094 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5095 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5096 SDValue V1 = N->getOperand(0);
5097 SDValue V2 = N->getOperand(1);
5098 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5099 for (unsigned i = 0; i != NumElems; ++i) {
5100 int Idx = N->getMaskElt(i);
5101 if (Idx >= (int)NumElems) {
5102 unsigned Opc = V2.getOpcode();
5103 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5105 if (Opc != ISD::BUILD_VECTOR ||
5106 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5108 } else if (Idx >= 0) {
5109 unsigned Opc = V1.getOpcode();
5110 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5112 if (Opc != ISD::BUILD_VECTOR ||
5113 !X86::isZeroNode(V1.getOperand(Idx)))
5120 /// getZeroVector - Returns a vector of specified type with all zero elements.
5122 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5123 SelectionDAG &DAG, SDLoc dl) {
5124 assert(VT.isVector() && "Expected a vector type");
5126 // Always build SSE zero vectors as <4 x i32> bitcasted
5127 // to their dest type. This ensures they get CSE'd.
5129 if (VT.is128BitVector()) { // SSE
5130 if (Subtarget->hasSSE2()) { // SSE2
5131 SDValue Cst = DAG.getConstant(0, MVT::i32);
5132 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5134 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5137 } else if (VT.is256BitVector()) { // AVX
5138 if (Subtarget->hasInt256()) { // AVX2
5139 SDValue Cst = DAG.getConstant(0, MVT::i32);
5140 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5141 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5143 // 256-bit logic and arithmetic instructions in AVX are all
5144 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5145 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5146 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5149 } else if (VT.is512BitVector()) { // AVX-512
5150 SDValue Cst = DAG.getConstant(0, MVT::i32);
5151 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5152 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5153 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5154 } else if (VT.getScalarType() == MVT::i1) {
5155 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5156 SDValue Cst = DAG.getConstant(0, MVT::i1);
5157 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5158 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5160 llvm_unreachable("Unexpected vector type");
5162 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5165 /// getOnesVector - Returns a vector of specified type with all bits set.
5166 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5167 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5168 /// Then bitcast to their original type, ensuring they get CSE'd.
5169 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5171 assert(VT.isVector() && "Expected a vector type");
5173 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5175 if (VT.is256BitVector()) {
5176 if (HasInt256) { // AVX2
5177 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5178 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5180 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5181 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5183 } else if (VT.is128BitVector()) {
5184 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5186 llvm_unreachable("Unexpected vector type");
5188 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5191 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5192 /// that point to V2 points to its first element.
5193 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5194 for (unsigned i = 0; i != NumElems; ++i) {
5195 if (Mask[i] > (int)NumElems) {
5201 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5202 /// operation of specified width.
5203 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5205 unsigned NumElems = VT.getVectorNumElements();
5206 SmallVector<int, 8> Mask;
5207 Mask.push_back(NumElems);
5208 for (unsigned i = 1; i != NumElems; ++i)
5210 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5213 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5214 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5216 unsigned NumElems = VT.getVectorNumElements();
5217 SmallVector<int, 8> Mask;
5218 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5220 Mask.push_back(i + NumElems);
5222 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5225 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5226 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5228 unsigned NumElems = VT.getVectorNumElements();
5229 SmallVector<int, 8> Mask;
5230 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5231 Mask.push_back(i + Half);
5232 Mask.push_back(i + NumElems + Half);
5234 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5237 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5238 // a generic shuffle instruction because the target has no such instructions.
5239 // Generate shuffles which repeat i16 and i8 several times until they can be
5240 // represented by v4f32 and then be manipulated by target suported shuffles.
5241 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5242 MVT VT = V.getSimpleValueType();
5243 int NumElems = VT.getVectorNumElements();
5246 while (NumElems > 4) {
5247 if (EltNo < NumElems/2) {
5248 V = getUnpackl(DAG, dl, VT, V, V);
5250 V = getUnpackh(DAG, dl, VT, V, V);
5251 EltNo -= NumElems/2;
5258 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5259 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5260 MVT VT = V.getSimpleValueType();
5263 if (VT.is128BitVector()) {
5264 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5265 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5266 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5268 } else if (VT.is256BitVector()) {
5269 // To use VPERMILPS to splat scalars, the second half of indicies must
5270 // refer to the higher part, which is a duplication of the lower one,
5271 // because VPERMILPS can only handle in-lane permutations.
5272 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5273 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5275 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5276 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5279 llvm_unreachable("Vector size not supported");
5281 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5284 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5285 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5286 MVT SrcVT = SV->getSimpleValueType(0);
5287 SDValue V1 = SV->getOperand(0);
5290 int EltNo = SV->getSplatIndex();
5291 int NumElems = SrcVT.getVectorNumElements();
5292 bool Is256BitVec = SrcVT.is256BitVector();
5294 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5295 "Unknown how to promote splat for type");
5297 // Extract the 128-bit part containing the splat element and update
5298 // the splat element index when it refers to the higher register.
5300 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5301 if (EltNo >= NumElems/2)
5302 EltNo -= NumElems/2;
5305 // All i16 and i8 vector types can't be used directly by a generic shuffle
5306 // instruction because the target has no such instruction. Generate shuffles
5307 // which repeat i16 and i8 several times until they fit in i32, and then can
5308 // be manipulated by target suported shuffles.
5309 MVT EltVT = SrcVT.getVectorElementType();
5310 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5311 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5313 // Recreate the 256-bit vector and place the same 128-bit vector
5314 // into the low and high part. This is necessary because we want
5315 // to use VPERM* to shuffle the vectors
5317 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5320 return getLegalSplat(DAG, V1, EltNo);
5323 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5324 /// vector of zero or undef vector. This produces a shuffle where the low
5325 /// element of V2 is swizzled into the zero/undef vector, landing at element
5326 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5327 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5329 const X86Subtarget *Subtarget,
5330 SelectionDAG &DAG) {
5331 MVT VT = V2.getSimpleValueType();
5333 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5334 unsigned NumElems = VT.getVectorNumElements();
5335 SmallVector<int, 16> MaskVec;
5336 for (unsigned i = 0; i != NumElems; ++i)
5337 // If this is the insertion idx, put the low elt of V2 here.
5338 MaskVec.push_back(i == Idx ? NumElems : i);
5339 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5342 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5343 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5344 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5345 /// shuffles which use a single input multiple times, and in those cases it will
5346 /// adjust the mask to only have indices within that single input.
5347 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5348 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5349 unsigned NumElems = VT.getVectorNumElements();
5353 bool IsFakeUnary = false;
5354 switch(N->getOpcode()) {
5355 case X86ISD::BLENDI:
5356 ImmN = N->getOperand(N->getNumOperands()-1);
5357 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5360 ImmN = N->getOperand(N->getNumOperands()-1);
5361 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5362 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5364 case X86ISD::UNPCKH:
5365 DecodeUNPCKHMask(VT, Mask);
5366 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5368 case X86ISD::UNPCKL:
5369 DecodeUNPCKLMask(VT, Mask);
5370 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5372 case X86ISD::MOVHLPS:
5373 DecodeMOVHLPSMask(NumElems, Mask);
5374 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5376 case X86ISD::MOVLHPS:
5377 DecodeMOVLHPSMask(NumElems, Mask);
5378 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5380 case X86ISD::PALIGNR:
5381 ImmN = N->getOperand(N->getNumOperands()-1);
5382 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5384 case X86ISD::PSHUFD:
5385 case X86ISD::VPERMILPI:
5386 ImmN = N->getOperand(N->getNumOperands()-1);
5387 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5390 case X86ISD::PSHUFHW:
5391 ImmN = N->getOperand(N->getNumOperands()-1);
5392 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5395 case X86ISD::PSHUFLW:
5396 ImmN = N->getOperand(N->getNumOperands()-1);
5397 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5400 case X86ISD::PSHUFB: {
5402 SDValue MaskNode = N->getOperand(1);
5403 while (MaskNode->getOpcode() == ISD::BITCAST)
5404 MaskNode = MaskNode->getOperand(0);
5406 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5407 // If we have a build-vector, then things are easy.
5408 EVT VT = MaskNode.getValueType();
5409 assert(VT.isVector() &&
5410 "Can't produce a non-vector with a build_vector!");
5411 if (!VT.isInteger())
5414 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5416 SmallVector<uint64_t, 32> RawMask;
5417 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5418 SDValue Op = MaskNode->getOperand(i);
5419 if (Op->getOpcode() == ISD::UNDEF) {
5420 RawMask.push_back((uint64_t)SM_SentinelUndef);
5423 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5426 APInt MaskElement = CN->getAPIntValue();
5428 // We now have to decode the element which could be any integer size and
5429 // extract each byte of it.
5430 for (int j = 0; j < NumBytesPerElement; ++j) {
5431 // Note that this is x86 and so always little endian: the low byte is
5432 // the first byte of the mask.
5433 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5434 MaskElement = MaskElement.lshr(8);
5437 DecodePSHUFBMask(RawMask, Mask);
5441 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5445 SDValue Ptr = MaskLoad->getBasePtr();
5446 if (Ptr->getOpcode() == X86ISD::Wrapper)
5447 Ptr = Ptr->getOperand(0);
5449 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5450 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5453 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5454 // FIXME: Support AVX-512 here.
5455 Type *Ty = C->getType();
5456 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5457 Ty->getVectorNumElements() != 32))
5460 DecodePSHUFBMask(C, Mask);
5466 case X86ISD::VPERMI:
5467 ImmN = N->getOperand(N->getNumOperands()-1);
5468 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5472 case X86ISD::MOVSD: {
5473 // The index 0 always comes from the first element of the second source,
5474 // this is why MOVSS and MOVSD are used in the first place. The other
5475 // elements come from the other positions of the first source vector
5476 Mask.push_back(NumElems);
5477 for (unsigned i = 1; i != NumElems; ++i) {
5482 case X86ISD::VPERM2X128:
5483 ImmN = N->getOperand(N->getNumOperands()-1);
5484 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5485 if (Mask.empty()) return false;
5487 case X86ISD::MOVSLDUP:
5488 DecodeMOVSLDUPMask(VT, Mask);
5490 case X86ISD::MOVSHDUP:
5491 DecodeMOVSHDUPMask(VT, Mask);
5493 case X86ISD::MOVDDUP:
5494 case X86ISD::MOVLHPD:
5495 case X86ISD::MOVLPD:
5496 case X86ISD::MOVLPS:
5497 // Not yet implemented
5499 default: llvm_unreachable("unknown target shuffle node");
5502 // If we have a fake unary shuffle, the shuffle mask is spread across two
5503 // inputs that are actually the same node. Re-map the mask to always point
5504 // into the first input.
5507 if (M >= (int)Mask.size())
5513 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5514 /// element of the result of the vector shuffle.
5515 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5518 return SDValue(); // Limit search depth.
5520 SDValue V = SDValue(N, 0);
5521 EVT VT = V.getValueType();
5522 unsigned Opcode = V.getOpcode();
5524 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5525 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5526 int Elt = SV->getMaskElt(Index);
5529 return DAG.getUNDEF(VT.getVectorElementType());
5531 unsigned NumElems = VT.getVectorNumElements();
5532 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5533 : SV->getOperand(1);
5534 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5537 // Recurse into target specific vector shuffles to find scalars.
5538 if (isTargetShuffle(Opcode)) {
5539 MVT ShufVT = V.getSimpleValueType();
5540 unsigned NumElems = ShufVT.getVectorNumElements();
5541 SmallVector<int, 16> ShuffleMask;
5544 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5547 int Elt = ShuffleMask[Index];
5549 return DAG.getUNDEF(ShufVT.getVectorElementType());
5551 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5553 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5557 // Actual nodes that may contain scalar elements
5558 if (Opcode == ISD::BITCAST) {
5559 V = V.getOperand(0);
5560 EVT SrcVT = V.getValueType();
5561 unsigned NumElems = VT.getVectorNumElements();
5563 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5567 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5568 return (Index == 0) ? V.getOperand(0)
5569 : DAG.getUNDEF(VT.getVectorElementType());
5571 if (V.getOpcode() == ISD::BUILD_VECTOR)
5572 return V.getOperand(Index);
5577 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5578 /// shuffle operation which come from a consecutively from a zero. The
5579 /// search can start in two different directions, from left or right.
5580 /// We count undefs as zeros until PreferredNum is reached.
5581 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5582 unsigned NumElems, bool ZerosFromLeft,
5584 unsigned PreferredNum = -1U) {
5585 unsigned NumZeros = 0;
5586 for (unsigned i = 0; i != NumElems; ++i) {
5587 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5588 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5592 if (X86::isZeroNode(Elt))
5594 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5595 NumZeros = std::min(NumZeros + 1, PreferredNum);
5603 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5604 /// correspond consecutively to elements from one of the vector operands,
5605 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5607 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5608 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5609 unsigned NumElems, unsigned &OpNum) {
5610 bool SeenV1 = false;
5611 bool SeenV2 = false;
5613 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5614 int Idx = SVOp->getMaskElt(i);
5615 // Ignore undef indicies
5619 if (Idx < (int)NumElems)
5624 // Only accept consecutive elements from the same vector
5625 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5629 OpNum = SeenV1 ? 0 : 1;
5633 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5634 /// logical left shift of a vector.
5635 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5636 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5638 SVOp->getSimpleValueType(0).getVectorNumElements();
5639 unsigned NumZeros = getNumOfConsecutiveZeros(
5640 SVOp, NumElems, false /* check zeros from right */, DAG,
5641 SVOp->getMaskElt(0));
5647 // Considering the elements in the mask that are not consecutive zeros,
5648 // check if they consecutively come from only one of the source vectors.
5650 // V1 = {X, A, B, C} 0
5652 // vector_shuffle V1, V2 <1, 2, 3, X>
5654 if (!isShuffleMaskConsecutive(SVOp,
5655 0, // Mask Start Index
5656 NumElems-NumZeros, // Mask End Index(exclusive)
5657 NumZeros, // Where to start looking in the src vector
5658 NumElems, // Number of elements in vector
5659 OpSrc)) // Which source operand ?
5664 ShVal = SVOp->getOperand(OpSrc);
5668 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5669 /// logical left shift of a vector.
5670 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5671 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5673 SVOp->getSimpleValueType(0).getVectorNumElements();
5674 unsigned NumZeros = getNumOfConsecutiveZeros(
5675 SVOp, NumElems, true /* check zeros from left */, DAG,
5676 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5682 // Considering the elements in the mask that are not consecutive zeros,
5683 // check if they consecutively come from only one of the source vectors.
5685 // 0 { A, B, X, X } = V2
5687 // vector_shuffle V1, V2 <X, X, 4, 5>
5689 if (!isShuffleMaskConsecutive(SVOp,
5690 NumZeros, // Mask Start Index
5691 NumElems, // Mask End Index(exclusive)
5692 0, // Where to start looking in the src vector
5693 NumElems, // Number of elements in vector
5694 OpSrc)) // Which source operand ?
5699 ShVal = SVOp->getOperand(OpSrc);
5703 /// isVectorShift - Returns true if the shuffle can be implemented as a
5704 /// logical left or right shift of a vector.
5705 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5706 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5707 // Although the logic below support any bitwidth size, there are no
5708 // shift instructions which handle more than 128-bit vectors.
5709 if (!SVOp->getSimpleValueType(0).is128BitVector())
5712 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5713 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5719 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5721 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5722 unsigned NumNonZero, unsigned NumZero,
5724 const X86Subtarget* Subtarget,
5725 const TargetLowering &TLI) {
5732 for (unsigned i = 0; i < 16; ++i) {
5733 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5734 if (ThisIsNonZero && First) {
5736 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5738 V = DAG.getUNDEF(MVT::v8i16);
5743 SDValue ThisElt, LastElt;
5744 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5745 if (LastIsNonZero) {
5746 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5747 MVT::i16, Op.getOperand(i-1));
5749 if (ThisIsNonZero) {
5750 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5751 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5752 ThisElt, DAG.getConstant(8, MVT::i8));
5754 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5758 if (ThisElt.getNode())
5759 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5760 DAG.getIntPtrConstant(i/2));
5764 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5767 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5769 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5770 unsigned NumNonZero, unsigned NumZero,
5772 const X86Subtarget* Subtarget,
5773 const TargetLowering &TLI) {
5780 for (unsigned i = 0; i < 8; ++i) {
5781 bool isNonZero = (NonZeros & (1 << i)) != 0;
5785 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5787 V = DAG.getUNDEF(MVT::v8i16);
5790 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5791 MVT::v8i16, V, Op.getOperand(i),
5792 DAG.getIntPtrConstant(i));
5799 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5800 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5801 const X86Subtarget *Subtarget,
5802 const TargetLowering &TLI) {
5803 // Find all zeroable elements.
5805 for (int i=0; i < 4; ++i) {
5806 SDValue Elt = Op->getOperand(i);
5807 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5809 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5810 [](bool M) { return !M; }) > 1 &&
5811 "We expect at least two non-zero elements!");
5813 // We only know how to deal with build_vector nodes where elements are either
5814 // zeroable or extract_vector_elt with constant index.
5815 SDValue FirstNonZero;
5816 unsigned FirstNonZeroIdx;
5817 for (unsigned i=0; i < 4; ++i) {
5820 SDValue Elt = Op->getOperand(i);
5821 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5822 !isa<ConstantSDNode>(Elt.getOperand(1)))
5824 // Make sure that this node is extracting from a 128-bit vector.
5825 MVT VT = Elt.getOperand(0).getSimpleValueType();
5826 if (!VT.is128BitVector())
5828 if (!FirstNonZero.getNode()) {
5830 FirstNonZeroIdx = i;
5834 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5835 SDValue V1 = FirstNonZero.getOperand(0);
5836 MVT VT = V1.getSimpleValueType();
5838 // See if this build_vector can be lowered as a blend with zero.
5840 unsigned EltMaskIdx, EltIdx;
5842 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5843 if (Zeroable[EltIdx]) {
5844 // The zero vector will be on the right hand side.
5845 Mask[EltIdx] = EltIdx+4;
5849 Elt = Op->getOperand(EltIdx);
5850 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5851 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5852 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5854 Mask[EltIdx] = EltIdx;
5858 // Let the shuffle legalizer deal with blend operations.
5859 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5860 if (V1.getSimpleValueType() != VT)
5861 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5862 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5865 // See if we can lower this build_vector to a INSERTPS.
5866 if (!Subtarget->hasSSE41())
5869 SDValue V2 = Elt.getOperand(0);
5870 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5873 bool CanFold = true;
5874 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5878 SDValue Current = Op->getOperand(i);
5879 SDValue SrcVector = Current->getOperand(0);
5882 CanFold = SrcVector == V1 &&
5883 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5889 assert(V1.getNode() && "Expected at least two non-zero elements!");
5890 if (V1.getSimpleValueType() != MVT::v4f32)
5891 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5892 if (V2.getSimpleValueType() != MVT::v4f32)
5893 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5895 // Ok, we can emit an INSERTPS instruction.
5897 for (int i = 0; i < 4; ++i)
5901 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5902 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5903 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5904 DAG.getIntPtrConstant(InsertPSMask));
5905 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5908 /// getVShift - Return a vector logical shift node.
5910 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5911 unsigned NumBits, SelectionDAG &DAG,
5912 const TargetLowering &TLI, SDLoc dl) {
5913 assert(VT.is128BitVector() && "Unknown type for VShift");
5914 EVT ShVT = MVT::v2i64;
5915 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5916 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5917 return DAG.getNode(ISD::BITCAST, dl, VT,
5918 DAG.getNode(Opc, dl, ShVT, SrcOp,
5919 DAG.getConstant(NumBits,
5920 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5924 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5926 // Check if the scalar load can be widened into a vector load. And if
5927 // the address is "base + cst" see if the cst can be "absorbed" into
5928 // the shuffle mask.
5929 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5930 SDValue Ptr = LD->getBasePtr();
5931 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5933 EVT PVT = LD->getValueType(0);
5934 if (PVT != MVT::i32 && PVT != MVT::f32)
5939 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5940 FI = FINode->getIndex();
5942 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5943 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5944 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5945 Offset = Ptr.getConstantOperandVal(1);
5946 Ptr = Ptr.getOperand(0);
5951 // FIXME: 256-bit vector instructions don't require a strict alignment,
5952 // improve this code to support it better.
5953 unsigned RequiredAlign = VT.getSizeInBits()/8;
5954 SDValue Chain = LD->getChain();
5955 // Make sure the stack object alignment is at least 16 or 32.
5956 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5957 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5958 if (MFI->isFixedObjectIndex(FI)) {
5959 // Can't change the alignment. FIXME: It's possible to compute
5960 // the exact stack offset and reference FI + adjust offset instead.
5961 // If someone *really* cares about this. That's the way to implement it.
5964 MFI->setObjectAlignment(FI, RequiredAlign);
5968 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5969 // Ptr + (Offset & ~15).
5972 if ((Offset % RequiredAlign) & 3)
5974 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5976 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5977 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5979 int EltNo = (Offset - StartOffset) >> 2;
5980 unsigned NumElems = VT.getVectorNumElements();
5982 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5983 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5984 LD->getPointerInfo().getWithOffset(StartOffset),
5985 false, false, false, 0);
5987 SmallVector<int, 8> Mask;
5988 for (unsigned i = 0; i != NumElems; ++i)
5989 Mask.push_back(EltNo);
5991 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5997 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5998 /// vector of type 'VT', see if the elements can be replaced by a single large
5999 /// load which has the same value as a build_vector whose operands are 'elts'.
6001 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6003 /// FIXME: we'd also like to handle the case where the last elements are zero
6004 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6005 /// There's even a handy isZeroNode for that purpose.
6006 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6007 SDLoc &DL, SelectionDAG &DAG,
6008 bool isAfterLegalize) {
6009 EVT EltVT = VT.getVectorElementType();
6010 unsigned NumElems = Elts.size();
6012 LoadSDNode *LDBase = nullptr;
6013 unsigned LastLoadedElt = -1U;
6015 // For each element in the initializer, see if we've found a load or an undef.
6016 // If we don't find an initial load element, or later load elements are
6017 // non-consecutive, bail out.
6018 for (unsigned i = 0; i < NumElems; ++i) {
6019 SDValue Elt = Elts[i];
6021 if (!Elt.getNode() ||
6022 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6025 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6027 LDBase = cast<LoadSDNode>(Elt.getNode());
6031 if (Elt.getOpcode() == ISD::UNDEF)
6034 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6035 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6040 // If we have found an entire vector of loads and undefs, then return a large
6041 // load of the entire vector width starting at the base pointer. If we found
6042 // consecutive loads for the low half, generate a vzext_load node.
6043 if (LastLoadedElt == NumElems - 1) {
6045 if (isAfterLegalize &&
6046 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6049 SDValue NewLd = SDValue();
6051 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6052 LDBase->getPointerInfo(), LDBase->isVolatile(),
6053 LDBase->isNonTemporal(), LDBase->isInvariant(),
6054 LDBase->getAlignment());
6056 if (LDBase->hasAnyUseOfValue(1)) {
6057 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6059 SDValue(NewLd.getNode(), 1));
6060 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6061 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6062 SDValue(NewLd.getNode(), 1));
6068 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6069 //of a v4i32 / v4f32. It's probably worth generalizing.
6070 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6071 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6072 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6073 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6075 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6076 LDBase->getPointerInfo(),
6077 LDBase->getAlignment(),
6078 false/*isVolatile*/, true/*ReadMem*/,
6081 // Make sure the newly-created LOAD is in the same position as LDBase in
6082 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6083 // update uses of LDBase's output chain to use the TokenFactor.
6084 if (LDBase->hasAnyUseOfValue(1)) {
6085 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6086 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6087 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6088 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6089 SDValue(ResNode.getNode(), 1));
6092 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6097 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6098 /// to generate a splat value for the following cases:
6099 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6100 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6101 /// a scalar load, or a constant.
6102 /// The VBROADCAST node is returned when a pattern is found,
6103 /// or SDValue() otherwise.
6104 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6105 SelectionDAG &DAG) {
6106 // VBROADCAST requires AVX.
6107 // TODO: Splats could be generated for non-AVX CPUs using SSE
6108 // instructions, but there's less potential gain for only 128-bit vectors.
6109 if (!Subtarget->hasAVX())
6112 MVT VT = Op.getSimpleValueType();
6115 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6116 "Unsupported vector type for broadcast.");
6121 switch (Op.getOpcode()) {
6123 // Unknown pattern found.
6126 case ISD::BUILD_VECTOR: {
6127 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6128 BitVector UndefElements;
6129 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6131 // We need a splat of a single value to use broadcast, and it doesn't
6132 // make any sense if the value is only in one element of the vector.
6133 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6137 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6138 Ld.getOpcode() == ISD::ConstantFP);
6140 // Make sure that all of the users of a non-constant load are from the
6141 // BUILD_VECTOR node.
6142 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6147 case ISD::VECTOR_SHUFFLE: {
6148 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6150 // Shuffles must have a splat mask where the first element is
6152 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6155 SDValue Sc = Op.getOperand(0);
6156 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6157 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6159 if (!Subtarget->hasInt256())
6162 // Use the register form of the broadcast instruction available on AVX2.
6163 if (VT.getSizeInBits() >= 256)
6164 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6165 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6168 Ld = Sc.getOperand(0);
6169 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6170 Ld.getOpcode() == ISD::ConstantFP);
6172 // The scalar_to_vector node and the suspected
6173 // load node must have exactly one user.
6174 // Constants may have multiple users.
6176 // AVX-512 has register version of the broadcast
6177 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6178 Ld.getValueType().getSizeInBits() >= 32;
6179 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6186 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6187 bool IsGE256 = (VT.getSizeInBits() >= 256);
6189 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6190 // instruction to save 8 or more bytes of constant pool data.
6191 // TODO: If multiple splats are generated to load the same constant,
6192 // it may be detrimental to overall size. There needs to be a way to detect
6193 // that condition to know if this is truly a size win.
6194 const Function *F = DAG.getMachineFunction().getFunction();
6195 bool OptForSize = F->getAttributes().
6196 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6198 // Handle broadcasting a single constant scalar from the constant pool
6200 // On Sandybridge (no AVX2), it is still better to load a constant vector
6201 // from the constant pool and not to broadcast it from a scalar.
6202 // But override that restriction when optimizing for size.
6203 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6204 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6205 EVT CVT = Ld.getValueType();
6206 assert(!CVT.isVector() && "Must not broadcast a vector type");
6208 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6209 // For size optimization, also splat v2f64 and v2i64, and for size opt
6210 // with AVX2, also splat i8 and i16.
6211 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6212 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6213 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6214 const Constant *C = nullptr;
6215 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6216 C = CI->getConstantIntValue();
6217 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6218 C = CF->getConstantFPValue();
6220 assert(C && "Invalid constant type");
6222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6223 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6224 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6225 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6226 MachinePointerInfo::getConstantPool(),
6227 false, false, false, Alignment);
6229 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6233 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6235 // Handle AVX2 in-register broadcasts.
6236 if (!IsLoad && Subtarget->hasInt256() &&
6237 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6238 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6240 // The scalar source must be a normal load.
6244 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6245 (Subtarget->hasVLX() && ScalarSize == 64))
6246 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6248 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6249 // double since there is no vbroadcastsd xmm
6250 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6251 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6252 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6255 // Unsupported broadcast.
6259 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6260 /// underlying vector and index.
6262 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6264 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6266 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6267 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6270 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6272 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6274 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6275 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6278 // In this case the vector is the extract_subvector expression and the index
6279 // is 2, as specified by the shuffle.
6280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6281 SDValue ShuffleVec = SVOp->getOperand(0);
6282 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6283 assert(ShuffleVecVT.getVectorElementType() ==
6284 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6286 int ShuffleIdx = SVOp->getMaskElt(Idx);
6287 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6288 ExtractedFromVec = ShuffleVec;
6294 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6295 MVT VT = Op.getSimpleValueType();
6297 // Skip if insert_vec_elt is not supported.
6298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6299 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6303 unsigned NumElems = Op.getNumOperands();
6307 SmallVector<unsigned, 4> InsertIndices;
6308 SmallVector<int, 8> Mask(NumElems, -1);
6310 for (unsigned i = 0; i != NumElems; ++i) {
6311 unsigned Opc = Op.getOperand(i).getOpcode();
6313 if (Opc == ISD::UNDEF)
6316 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6317 // Quit if more than 1 elements need inserting.
6318 if (InsertIndices.size() > 1)
6321 InsertIndices.push_back(i);
6325 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6326 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6327 // Quit if non-constant index.
6328 if (!isa<ConstantSDNode>(ExtIdx))
6330 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6332 // Quit if extracted from vector of different type.
6333 if (ExtractedFromVec.getValueType() != VT)
6336 if (!VecIn1.getNode())
6337 VecIn1 = ExtractedFromVec;
6338 else if (VecIn1 != ExtractedFromVec) {
6339 if (!VecIn2.getNode())
6340 VecIn2 = ExtractedFromVec;
6341 else if (VecIn2 != ExtractedFromVec)
6342 // Quit if more than 2 vectors to shuffle
6346 if (ExtractedFromVec == VecIn1)
6348 else if (ExtractedFromVec == VecIn2)
6349 Mask[i] = Idx + NumElems;
6352 if (!VecIn1.getNode())
6355 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6356 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6357 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6358 unsigned Idx = InsertIndices[i];
6359 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6360 DAG.getIntPtrConstant(Idx));
6366 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6368 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6370 MVT VT = Op.getSimpleValueType();
6371 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6372 "Unexpected type in LowerBUILD_VECTORvXi1!");
6375 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6376 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6377 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6378 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6381 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6382 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6383 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6384 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6387 bool AllContants = true;
6388 uint64_t Immediate = 0;
6389 int NonConstIdx = -1;
6390 bool IsSplat = true;
6391 unsigned NumNonConsts = 0;
6392 unsigned NumConsts = 0;
6393 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6394 SDValue In = Op.getOperand(idx);
6395 if (In.getOpcode() == ISD::UNDEF)
6397 if (!isa<ConstantSDNode>(In)) {
6398 AllContants = false;
6403 if (cast<ConstantSDNode>(In)->getZExtValue())
6404 Immediate |= (1ULL << idx);
6406 if (In != Op.getOperand(0))
6411 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6412 DAG.getConstant(Immediate, MVT::i16));
6413 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6414 DAG.getIntPtrConstant(0));
6417 if (NumNonConsts == 1 && NonConstIdx != 0) {
6420 SDValue VecAsImm = DAG.getConstant(Immediate,
6421 MVT::getIntegerVT(VT.getSizeInBits()));
6422 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6425 DstVec = DAG.getUNDEF(VT);
6426 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6427 Op.getOperand(NonConstIdx),
6428 DAG.getIntPtrConstant(NonConstIdx));
6430 if (!IsSplat && (NonConstIdx != 0))
6431 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6432 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6435 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6436 DAG.getConstant(-1, SelectVT),
6437 DAG.getConstant(0, SelectVT));
6439 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6440 DAG.getConstant((Immediate | 1), SelectVT),
6441 DAG.getConstant(Immediate, SelectVT));
6442 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6445 /// \brief Return true if \p N implements a horizontal binop and return the
6446 /// operands for the horizontal binop into V0 and V1.
6448 /// This is a helper function of PerformBUILD_VECTORCombine.
6449 /// This function checks that the build_vector \p N in input implements a
6450 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6451 /// operation to match.
6452 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6453 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6454 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6457 /// This function only analyzes elements of \p N whose indices are
6458 /// in range [BaseIdx, LastIdx).
6459 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6461 unsigned BaseIdx, unsigned LastIdx,
6462 SDValue &V0, SDValue &V1) {
6463 EVT VT = N->getValueType(0);
6465 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6466 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6467 "Invalid Vector in input!");
6469 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6470 bool CanFold = true;
6471 unsigned ExpectedVExtractIdx = BaseIdx;
6472 unsigned NumElts = LastIdx - BaseIdx;
6473 V0 = DAG.getUNDEF(VT);
6474 V1 = DAG.getUNDEF(VT);
6476 // Check if N implements a horizontal binop.
6477 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6478 SDValue Op = N->getOperand(i + BaseIdx);
6481 if (Op->getOpcode() == ISD::UNDEF) {
6482 // Update the expected vector extract index.
6483 if (i * 2 == NumElts)
6484 ExpectedVExtractIdx = BaseIdx;
6485 ExpectedVExtractIdx += 2;
6489 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6494 SDValue Op0 = Op.getOperand(0);
6495 SDValue Op1 = Op.getOperand(1);
6497 // Try to match the following pattern:
6498 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6499 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6500 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6501 Op0.getOperand(0) == Op1.getOperand(0) &&
6502 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6503 isa<ConstantSDNode>(Op1.getOperand(1)));
6507 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6508 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6510 if (i * 2 < NumElts) {
6511 if (V0.getOpcode() == ISD::UNDEF)
6512 V0 = Op0.getOperand(0);
6514 if (V1.getOpcode() == ISD::UNDEF)
6515 V1 = Op0.getOperand(0);
6516 if (i * 2 == NumElts)
6517 ExpectedVExtractIdx = BaseIdx;
6520 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6521 if (I0 == ExpectedVExtractIdx)
6522 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6523 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6524 // Try to match the following dag sequence:
6525 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6526 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6530 ExpectedVExtractIdx += 2;
6536 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6537 /// a concat_vector.
6539 /// This is a helper function of PerformBUILD_VECTORCombine.
6540 /// This function expects two 256-bit vectors called V0 and V1.
6541 /// At first, each vector is split into two separate 128-bit vectors.
6542 /// Then, the resulting 128-bit vectors are used to implement two
6543 /// horizontal binary operations.
6545 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6547 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6548 /// the two new horizontal binop.
6549 /// When Mode is set, the first horizontal binop dag node would take as input
6550 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6551 /// horizontal binop dag node would take as input the lower 128-bit of V1
6552 /// and the upper 128-bit of V1.
6554 /// HADD V0_LO, V0_HI
6555 /// HADD V1_LO, V1_HI
6557 /// Otherwise, the first horizontal binop dag node takes as input the lower
6558 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6559 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6561 /// HADD V0_LO, V1_LO
6562 /// HADD V0_HI, V1_HI
6564 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6565 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6566 /// the upper 128-bits of the result.
6567 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6568 SDLoc DL, SelectionDAG &DAG,
6569 unsigned X86Opcode, bool Mode,
6570 bool isUndefLO, bool isUndefHI) {
6571 EVT VT = V0.getValueType();
6572 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6573 "Invalid nodes in input!");
6575 unsigned NumElts = VT.getVectorNumElements();
6576 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6577 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6578 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6579 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6580 EVT NewVT = V0_LO.getValueType();
6582 SDValue LO = DAG.getUNDEF(NewVT);
6583 SDValue HI = DAG.getUNDEF(NewVT);
6586 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6587 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6588 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6589 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6590 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6592 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6593 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6594 V1_LO->getOpcode() != ISD::UNDEF))
6595 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6597 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6598 V1_HI->getOpcode() != ISD::UNDEF))
6599 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6602 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6605 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6606 /// sequence of 'vadd + vsub + blendi'.
6607 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6608 const X86Subtarget *Subtarget) {
6610 EVT VT = BV->getValueType(0);
6611 unsigned NumElts = VT.getVectorNumElements();
6612 SDValue InVec0 = DAG.getUNDEF(VT);
6613 SDValue InVec1 = DAG.getUNDEF(VT);
6615 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6616 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6618 // Odd-numbered elements in the input build vector are obtained from
6619 // adding two integer/float elements.
6620 // Even-numbered elements in the input build vector are obtained from
6621 // subtracting two integer/float elements.
6622 unsigned ExpectedOpcode = ISD::FSUB;
6623 unsigned NextExpectedOpcode = ISD::FADD;
6624 bool AddFound = false;
6625 bool SubFound = false;
6627 for (unsigned i = 0, e = NumElts; i != e; i++) {
6628 SDValue Op = BV->getOperand(i);
6630 // Skip 'undef' values.
6631 unsigned Opcode = Op.getOpcode();
6632 if (Opcode == ISD::UNDEF) {
6633 std::swap(ExpectedOpcode, NextExpectedOpcode);
6637 // Early exit if we found an unexpected opcode.
6638 if (Opcode != ExpectedOpcode)
6641 SDValue Op0 = Op.getOperand(0);
6642 SDValue Op1 = Op.getOperand(1);
6644 // Try to match the following pattern:
6645 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6646 // Early exit if we cannot match that sequence.
6647 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6648 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6649 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6650 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6651 Op0.getOperand(1) != Op1.getOperand(1))
6654 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6658 // We found a valid add/sub node. Update the information accordingly.
6664 // Update InVec0 and InVec1.
6665 if (InVec0.getOpcode() == ISD::UNDEF)
6666 InVec0 = Op0.getOperand(0);
6667 if (InVec1.getOpcode() == ISD::UNDEF)
6668 InVec1 = Op1.getOperand(0);
6670 // Make sure that operands in input to each add/sub node always
6671 // come from a same pair of vectors.
6672 if (InVec0 != Op0.getOperand(0)) {
6673 if (ExpectedOpcode == ISD::FSUB)
6676 // FADD is commutable. Try to commute the operands
6677 // and then test again.
6678 std::swap(Op0, Op1);
6679 if (InVec0 != Op0.getOperand(0))
6683 if (InVec1 != Op1.getOperand(0))
6686 // Update the pair of expected opcodes.
6687 std::swap(ExpectedOpcode, NextExpectedOpcode);
6690 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6691 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6692 InVec1.getOpcode() != ISD::UNDEF)
6693 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6698 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6699 const X86Subtarget *Subtarget) {
6701 EVT VT = N->getValueType(0);
6702 unsigned NumElts = VT.getVectorNumElements();
6703 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6704 SDValue InVec0, InVec1;
6706 // Try to match an ADDSUB.
6707 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6708 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6709 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6710 if (Value.getNode())
6714 // Try to match horizontal ADD/SUB.
6715 unsigned NumUndefsLO = 0;
6716 unsigned NumUndefsHI = 0;
6717 unsigned Half = NumElts/2;
6719 // Count the number of UNDEF operands in the build_vector in input.
6720 for (unsigned i = 0, e = Half; i != e; ++i)
6721 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6724 for (unsigned i = Half, e = NumElts; i != e; ++i)
6725 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6728 // Early exit if this is either a build_vector of all UNDEFs or all the
6729 // operands but one are UNDEF.
6730 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6733 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6734 // Try to match an SSE3 float HADD/HSUB.
6735 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6736 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6738 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6739 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6740 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6741 // Try to match an SSSE3 integer HADD/HSUB.
6742 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6743 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6745 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6746 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6749 if (!Subtarget->hasAVX())
6752 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6753 // Try to match an AVX horizontal add/sub of packed single/double
6754 // precision floating point values from 256-bit vectors.
6755 SDValue InVec2, InVec3;
6756 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6757 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6758 ((InVec0.getOpcode() == ISD::UNDEF ||
6759 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6760 ((InVec1.getOpcode() == ISD::UNDEF ||
6761 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6762 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6764 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6765 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6766 ((InVec0.getOpcode() == ISD::UNDEF ||
6767 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6768 ((InVec1.getOpcode() == ISD::UNDEF ||
6769 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6770 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6771 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6772 // Try to match an AVX2 horizontal add/sub of signed integers.
6773 SDValue InVec2, InVec3;
6775 bool CanFold = true;
6777 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6778 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6779 ((InVec0.getOpcode() == ISD::UNDEF ||
6780 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6781 ((InVec1.getOpcode() == ISD::UNDEF ||
6782 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6783 X86Opcode = X86ISD::HADD;
6784 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6785 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6786 ((InVec0.getOpcode() == ISD::UNDEF ||
6787 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6788 ((InVec1.getOpcode() == ISD::UNDEF ||
6789 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6790 X86Opcode = X86ISD::HSUB;
6795 // Fold this build_vector into a single horizontal add/sub.
6796 // Do this only if the target has AVX2.
6797 if (Subtarget->hasAVX2())
6798 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6800 // Do not try to expand this build_vector into a pair of horizontal
6801 // add/sub if we can emit a pair of scalar add/sub.
6802 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6805 // Convert this build_vector into a pair of horizontal binop followed by
6807 bool isUndefLO = NumUndefsLO == Half;
6808 bool isUndefHI = NumUndefsHI == Half;
6809 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6810 isUndefLO, isUndefHI);
6814 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6815 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6817 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6818 X86Opcode = X86ISD::HADD;
6819 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6820 X86Opcode = X86ISD::HSUB;
6821 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6822 X86Opcode = X86ISD::FHADD;
6823 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6824 X86Opcode = X86ISD::FHSUB;
6828 // Don't try to expand this build_vector into a pair of horizontal add/sub
6829 // if we can simply emit a pair of scalar add/sub.
6830 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6833 // Convert this build_vector into two horizontal add/sub followed by
6835 bool isUndefLO = NumUndefsLO == Half;
6836 bool isUndefHI = NumUndefsHI == Half;
6837 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6838 isUndefLO, isUndefHI);
6845 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6848 MVT VT = Op.getSimpleValueType();
6849 MVT ExtVT = VT.getVectorElementType();
6850 unsigned NumElems = Op.getNumOperands();
6852 // Generate vectors for predicate vectors.
6853 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6854 return LowerBUILD_VECTORvXi1(Op, DAG);
6856 // Vectors containing all zeros can be matched by pxor and xorps later
6857 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6858 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6859 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6860 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6863 return getZeroVector(VT, Subtarget, DAG, dl);
6866 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6867 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6868 // vpcmpeqd on 256-bit vectors.
6869 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6870 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6873 if (!VT.is512BitVector())
6874 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6877 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6878 if (Broadcast.getNode())
6881 unsigned EVTBits = ExtVT.getSizeInBits();
6883 unsigned NumZero = 0;
6884 unsigned NumNonZero = 0;
6885 unsigned NonZeros = 0;
6886 bool IsAllConstants = true;
6887 SmallSet<SDValue, 8> Values;
6888 for (unsigned i = 0; i < NumElems; ++i) {
6889 SDValue Elt = Op.getOperand(i);
6890 if (Elt.getOpcode() == ISD::UNDEF)
6893 if (Elt.getOpcode() != ISD::Constant &&
6894 Elt.getOpcode() != ISD::ConstantFP)
6895 IsAllConstants = false;
6896 if (X86::isZeroNode(Elt))
6899 NonZeros |= (1 << i);
6904 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6905 if (NumNonZero == 0)
6906 return DAG.getUNDEF(VT);
6908 // Special case for single non-zero, non-undef, element.
6909 if (NumNonZero == 1) {
6910 unsigned Idx = countTrailingZeros(NonZeros);
6911 SDValue Item = Op.getOperand(Idx);
6913 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6914 // the value are obviously zero, truncate the value to i32 and do the
6915 // insertion that way. Only do this if the value is non-constant or if the
6916 // value is a constant being inserted into element 0. It is cheaper to do
6917 // a constant pool load than it is to do a movd + shuffle.
6918 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6919 (!IsAllConstants || Idx == 0)) {
6920 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6922 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6923 EVT VecVT = MVT::v4i32;
6924 unsigned VecElts = 4;
6926 // Truncate the value (which may itself be a constant) to i32, and
6927 // convert it to a vector with movd (S2V+shuffle to zero extend).
6928 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6929 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6931 // If using the new shuffle lowering, just directly insert this.
6932 if (ExperimentalVectorShuffleLowering)
6934 ISD::BITCAST, dl, VT,
6935 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6937 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6939 // Now we have our 32-bit value zero extended in the low element of
6940 // a vector. If Idx != 0, swizzle it into place.
6942 SmallVector<int, 4> Mask;
6943 Mask.push_back(Idx);
6944 for (unsigned i = 1; i != VecElts; ++i)
6946 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6949 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6953 // If we have a constant or non-constant insertion into the low element of
6954 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6955 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6956 // depending on what the source datatype is.
6959 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6961 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6962 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6963 if (VT.is256BitVector() || VT.is512BitVector()) {
6964 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6965 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6966 Item, DAG.getIntPtrConstant(0));
6968 assert(VT.is128BitVector() && "Expected an SSE value type!");
6969 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6970 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6971 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6974 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6975 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6976 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6977 if (VT.is256BitVector()) {
6978 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6979 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6981 assert(VT.is128BitVector() && "Expected an SSE value type!");
6982 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6984 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6988 // Is it a vector logical left shift?
6989 if (NumElems == 2 && Idx == 1 &&
6990 X86::isZeroNode(Op.getOperand(0)) &&
6991 !X86::isZeroNode(Op.getOperand(1))) {
6992 unsigned NumBits = VT.getSizeInBits();
6993 return getVShift(true, VT,
6994 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6995 VT, Op.getOperand(1)),
6996 NumBits/2, DAG, *this, dl);
6999 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7002 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7003 // is a non-constant being inserted into an element other than the low one,
7004 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7005 // movd/movss) to move this into the low element, then shuffle it into
7007 if (EVTBits == 32) {
7008 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7010 // If using the new shuffle lowering, just directly insert this.
7011 if (ExperimentalVectorShuffleLowering)
7012 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7014 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7015 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7016 SmallVector<int, 8> MaskVec;
7017 for (unsigned i = 0; i != NumElems; ++i)
7018 MaskVec.push_back(i == Idx ? 0 : 1);
7019 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7023 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7024 if (Values.size() == 1) {
7025 if (EVTBits == 32) {
7026 // Instead of a shuffle like this:
7027 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7028 // Check if it's possible to issue this instead.
7029 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7030 unsigned Idx = countTrailingZeros(NonZeros);
7031 SDValue Item = Op.getOperand(Idx);
7032 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7033 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7038 // A vector full of immediates; various special cases are already
7039 // handled, so this is best done with a single constant-pool load.
7043 // For AVX-length vectors, see if we can use a vector load to get all of the
7044 // elements, otherwise build the individual 128-bit pieces and use
7045 // shuffles to put them in place.
7046 if (VT.is256BitVector() || VT.is512BitVector()) {
7047 SmallVector<SDValue, 64> V;
7048 for (unsigned i = 0; i != NumElems; ++i)
7049 V.push_back(Op.getOperand(i));
7051 // Check for a build vector of consecutive loads.
7052 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7055 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7057 // Build both the lower and upper subvector.
7058 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7059 makeArrayRef(&V[0], NumElems/2));
7060 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7061 makeArrayRef(&V[NumElems / 2], NumElems/2));
7063 // Recreate the wider vector with the lower and upper part.
7064 if (VT.is256BitVector())
7065 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7066 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7069 // Let legalizer expand 2-wide build_vectors.
7070 if (EVTBits == 64) {
7071 if (NumNonZero == 1) {
7072 // One half is zero or undef.
7073 unsigned Idx = countTrailingZeros(NonZeros);
7074 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7075 Op.getOperand(Idx));
7076 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7081 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7082 if (EVTBits == 8 && NumElems == 16) {
7083 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7085 if (V.getNode()) return V;
7088 if (EVTBits == 16 && NumElems == 8) {
7089 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7091 if (V.getNode()) return V;
7094 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7095 if (EVTBits == 32 && NumElems == 4) {
7096 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7101 // If element VT is == 32 bits, turn it into a number of shuffles.
7102 SmallVector<SDValue, 8> V(NumElems);
7103 if (NumElems == 4 && NumZero > 0) {
7104 for (unsigned i = 0; i < 4; ++i) {
7105 bool isZero = !(NonZeros & (1 << i));
7107 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7109 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7112 for (unsigned i = 0; i < 2; ++i) {
7113 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7116 V[i] = V[i*2]; // Must be a zero vector.
7119 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7122 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7125 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7130 bool Reverse1 = (NonZeros & 0x3) == 2;
7131 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7135 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7136 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7138 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7141 if (Values.size() > 1 && VT.is128BitVector()) {
7142 // Check for a build vector of consecutive loads.
7143 for (unsigned i = 0; i < NumElems; ++i)
7144 V[i] = Op.getOperand(i);
7146 // Check for elements which are consecutive loads.
7147 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7151 // Check for a build vector from mostly shuffle plus few inserting.
7152 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7156 // For SSE 4.1, use insertps to put the high elements into the low element.
7157 if (getSubtarget()->hasSSE41()) {
7159 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7160 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7162 Result = DAG.getUNDEF(VT);
7164 for (unsigned i = 1; i < NumElems; ++i) {
7165 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7166 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7167 Op.getOperand(i), DAG.getIntPtrConstant(i));
7172 // Otherwise, expand into a number of unpckl*, start by extending each of
7173 // our (non-undef) elements to the full vector width with the element in the
7174 // bottom slot of the vector (which generates no code for SSE).
7175 for (unsigned i = 0; i < NumElems; ++i) {
7176 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7177 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7179 V[i] = DAG.getUNDEF(VT);
7182 // Next, we iteratively mix elements, e.g. for v4f32:
7183 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7184 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7185 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7186 unsigned EltStride = NumElems >> 1;
7187 while (EltStride != 0) {
7188 for (unsigned i = 0; i < EltStride; ++i) {
7189 // If V[i+EltStride] is undef and this is the first round of mixing,
7190 // then it is safe to just drop this shuffle: V[i] is already in the
7191 // right place, the one element (since it's the first round) being
7192 // inserted as undef can be dropped. This isn't safe for successive
7193 // rounds because they will permute elements within both vectors.
7194 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7195 EltStride == NumElems/2)
7198 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7207 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7208 // to create 256-bit vectors from two other 128-bit ones.
7209 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7211 MVT ResVT = Op.getSimpleValueType();
7213 assert((ResVT.is256BitVector() ||
7214 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7216 SDValue V1 = Op.getOperand(0);
7217 SDValue V2 = Op.getOperand(1);
7218 unsigned NumElems = ResVT.getVectorNumElements();
7219 if(ResVT.is256BitVector())
7220 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7222 if (Op.getNumOperands() == 4) {
7223 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7224 ResVT.getVectorNumElements()/2);
7225 SDValue V3 = Op.getOperand(2);
7226 SDValue V4 = Op.getOperand(3);
7227 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7228 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7230 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7233 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7234 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7235 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7236 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7237 Op.getNumOperands() == 4)));
7239 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7240 // from two other 128-bit ones.
7242 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7243 return LowerAVXCONCAT_VECTORS(Op, DAG);
7247 //===----------------------------------------------------------------------===//
7248 // Vector shuffle lowering
7250 // This is an experimental code path for lowering vector shuffles on x86. It is
7251 // designed to handle arbitrary vector shuffles and blends, gracefully
7252 // degrading performance as necessary. It works hard to recognize idiomatic
7253 // shuffles and lower them to optimal instruction patterns without leaving
7254 // a framework that allows reasonably efficient handling of all vector shuffle
7256 //===----------------------------------------------------------------------===//
7258 /// \brief Tiny helper function to identify a no-op mask.
7260 /// This is a somewhat boring predicate function. It checks whether the mask
7261 /// array input, which is assumed to be a single-input shuffle mask of the kind
7262 /// used by the X86 shuffle instructions (not a fully general
7263 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7264 /// in-place shuffle are 'no-op's.
7265 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7266 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7267 if (Mask[i] != -1 && Mask[i] != i)
7272 /// \brief Helper function to classify a mask as a single-input mask.
7274 /// This isn't a generic single-input test because in the vector shuffle
7275 /// lowering we canonicalize single inputs to be the first input operand. This
7276 /// means we can more quickly test for a single input by only checking whether
7277 /// an input from the second operand exists. We also assume that the size of
7278 /// mask corresponds to the size of the input vectors which isn't true in the
7279 /// fully general case.
7280 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7282 if (M >= (int)Mask.size())
7287 /// \brief Test whether there are elements crossing 128-bit lanes in this
7290 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7291 /// and we routinely test for these.
7292 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7293 int LaneSize = 128 / VT.getScalarSizeInBits();
7294 int Size = Mask.size();
7295 for (int i = 0; i < Size; ++i)
7296 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7301 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7303 /// This checks a shuffle mask to see if it is performing the same
7304 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7305 /// that it is also not lane-crossing. It may however involve a blend from the
7306 /// same lane of a second vector.
7308 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7309 /// non-trivial to compute in the face of undef lanes. The representation is
7310 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7311 /// entries from both V1 and V2 inputs to the wider mask.
7313 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7314 SmallVectorImpl<int> &RepeatedMask) {
7315 int LaneSize = 128 / VT.getScalarSizeInBits();
7316 RepeatedMask.resize(LaneSize, -1);
7317 int Size = Mask.size();
7318 for (int i = 0; i < Size; ++i) {
7321 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7322 // This entry crosses lanes, so there is no way to model this shuffle.
7325 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7326 if (RepeatedMask[i % LaneSize] == -1)
7327 // This is the first non-undef entry in this slot of a 128-bit lane.
7328 RepeatedMask[i % LaneSize] =
7329 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7330 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7331 // Found a mismatch with the repeated mask.
7337 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7338 // 2013 will allow us to use it as a non-type template parameter.
7341 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7343 /// See its documentation for details.
7344 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7345 if (Mask.size() != Args.size())
7347 for (int i = 0, e = Mask.size(); i < e; ++i) {
7348 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7349 if (Mask[i] != -1 && Mask[i] != *Args[i])
7357 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7360 /// This is a fast way to test a shuffle mask against a fixed pattern:
7362 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7364 /// It returns true if the mask is exactly as wide as the argument list, and
7365 /// each element of the mask is either -1 (signifying undef) or the value given
7366 /// in the argument.
7367 static const VariadicFunction1<
7368 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7370 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7372 /// This helper function produces an 8-bit shuffle immediate corresponding to
7373 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7374 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7377 /// NB: We rely heavily on "undef" masks preserving the input lane.
7378 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7379 SelectionDAG &DAG) {
7380 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7381 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7382 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7383 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7384 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7387 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7388 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7389 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7390 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7391 return DAG.getConstant(Imm, MVT::i8);
7394 /// \brief Try to emit a blend instruction for a shuffle.
7396 /// This doesn't do any checks for the availability of instructions for blending
7397 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7398 /// be matched in the backend with the type given. What it does check for is
7399 /// that the shuffle mask is in fact a blend.
7400 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7401 SDValue V2, ArrayRef<int> Mask,
7402 const X86Subtarget *Subtarget,
7403 SelectionDAG &DAG) {
7405 unsigned BlendMask = 0;
7406 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7407 if (Mask[i] >= Size) {
7408 if (Mask[i] != i + Size)
7409 return SDValue(); // Shuffled V2 input!
7410 BlendMask |= 1u << i;
7413 if (Mask[i] >= 0 && Mask[i] != i)
7414 return SDValue(); // Shuffled V1 input!
7416 switch (VT.SimpleTy) {
7421 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7422 DAG.getConstant(BlendMask, MVT::i8));
7426 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7430 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7431 // that instruction.
7432 if (Subtarget->hasAVX2()) {
7433 // Scale the blend by the number of 32-bit dwords per element.
7434 int Scale = VT.getScalarSizeInBits() / 32;
7436 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7437 if (Mask[i] >= Size)
7438 for (int j = 0; j < Scale; ++j)
7439 BlendMask |= 1u << (i * Scale + j);
7441 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7442 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7443 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7444 return DAG.getNode(ISD::BITCAST, DL, VT,
7445 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7446 DAG.getConstant(BlendMask, MVT::i8)));
7450 // For integer shuffles we need to expand the mask and cast the inputs to
7451 // v8i16s prior to blending.
7452 int Scale = 8 / VT.getVectorNumElements();
7454 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7455 if (Mask[i] >= Size)
7456 for (int j = 0; j < Scale; ++j)
7457 BlendMask |= 1u << (i * Scale + j);
7459 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7460 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7461 return DAG.getNode(ISD::BITCAST, DL, VT,
7462 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7463 DAG.getConstant(BlendMask, MVT::i8)));
7467 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7468 SmallVector<int, 8> RepeatedMask;
7469 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7470 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7471 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7473 for (int i = 0; i < 8; ++i)
7474 if (RepeatedMask[i] >= 16)
7475 BlendMask |= 1u << i;
7476 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7477 DAG.getConstant(BlendMask, MVT::i8));
7482 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7483 // Scale the blend by the number of bytes per element.
7484 int Scale = VT.getScalarSizeInBits() / 8;
7485 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7487 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7488 // mix of LLVM's code generator and the x86 backend. We tell the code
7489 // generator that boolean values in the elements of an x86 vector register
7490 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7491 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7492 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7493 // of the element (the remaining are ignored) and 0 in that high bit would
7494 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7495 // the LLVM model for boolean values in vector elements gets the relevant
7496 // bit set, it is set backwards and over constrained relative to x86's
7498 SDValue VSELECTMask[32];
7499 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7500 for (int j = 0; j < Scale; ++j)
7501 VSELECTMask[Scale * i + j] =
7502 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7503 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7505 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7506 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7508 ISD::BITCAST, DL, VT,
7509 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7510 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7515 llvm_unreachable("Not a supported integer vector type!");
7519 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7520 /// unblended shuffles followed by an unshuffled blend.
7522 /// This matches the extremely common pattern for handling combined
7523 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7525 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7529 SelectionDAG &DAG) {
7530 // Shuffle the input elements into the desired positions in V1 and V2 and
7531 // blend them together.
7532 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7533 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7534 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7535 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7536 if (Mask[i] >= 0 && Mask[i] < Size) {
7537 V1Mask[i] = Mask[i];
7539 } else if (Mask[i] >= Size) {
7540 V2Mask[i] = Mask[i] - Size;
7541 BlendMask[i] = i + Size;
7544 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7545 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7546 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7549 /// \brief Try to lower a vector shuffle as a byte rotation.
7551 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7552 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7553 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7554 /// try to generically lower a vector shuffle through such an pattern. It
7555 /// does not check for the profitability of lowering either as PALIGNR or
7556 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7557 /// This matches shuffle vectors that look like:
7559 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7561 /// Essentially it concatenates V1 and V2, shifts right by some number of
7562 /// elements, and takes the low elements as the result. Note that while this is
7563 /// specified as a *right shift* because x86 is little-endian, it is a *left
7564 /// rotate* of the vector lanes.
7566 /// Note that this only handles 128-bit vector widths currently.
7567 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7570 const X86Subtarget *Subtarget,
7571 SelectionDAG &DAG) {
7572 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7574 // We need to detect various ways of spelling a rotation:
7575 // [11, 12, 13, 14, 15, 0, 1, 2]
7576 // [-1, 12, 13, 14, -1, -1, 1, -1]
7577 // [-1, -1, -1, -1, -1, -1, 1, 2]
7578 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7579 // [-1, 4, 5, 6, -1, -1, 9, -1]
7580 // [-1, 4, 5, 6, -1, -1, -1, -1]
7583 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7586 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7588 // Based on the mod-Size value of this mask element determine where
7589 // a rotated vector would have started.
7590 int StartIdx = i - (Mask[i] % Size);
7592 // The identity rotation isn't interesting, stop.
7595 // If we found the tail of a vector the rotation must be the missing
7596 // front. If we found the head of a vector, it must be how much of the head.
7597 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7600 Rotation = CandidateRotation;
7601 else if (Rotation != CandidateRotation)
7602 // The rotations don't match, so we can't match this mask.
7605 // Compute which value this mask is pointing at.
7606 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7608 // Compute which of the two target values this index should be assigned to.
7609 // This reflects whether the high elements are remaining or the low elements
7611 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7613 // Either set up this value if we've not encountered it before, or check
7614 // that it remains consistent.
7617 else if (TargetV != MaskV)
7618 // This may be a rotation, but it pulls from the inputs in some
7619 // unsupported interleaving.
7623 // Check that we successfully analyzed the mask, and normalize the results.
7624 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7625 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7631 assert(VT.getSizeInBits() == 128 &&
7632 "Rotate-based lowering only supports 128-bit lowering!");
7633 assert(Mask.size() <= 16 &&
7634 "Can shuffle at most 16 bytes in a 128-bit vector!");
7636 // The actual rotate instruction rotates bytes, so we need to scale the
7637 // rotation based on how many bytes are in the vector.
7638 int Scale = 16 / Mask.size();
7640 // SSSE3 targets can use the palignr instruction
7641 if (Subtarget->hasSSSE3()) {
7642 // Cast the inputs to v16i8 to match PALIGNR.
7643 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7644 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7646 return DAG.getNode(ISD::BITCAST, DL, VT,
7647 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7648 DAG.getConstant(Rotation * Scale, MVT::i8)));
7651 // Default SSE2 implementation
7652 int LoByteShift = 16 - Rotation * Scale;
7653 int HiByteShift = Rotation * Scale;
7655 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7656 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7657 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7659 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7660 DAG.getConstant(8 * LoByteShift, MVT::i8));
7661 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7662 DAG.getConstant(8 * HiByteShift, MVT::i8));
7663 return DAG.getNode(ISD::BITCAST, DL, VT,
7664 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7667 /// \brief Compute whether each element of a shuffle is zeroable.
7669 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7670 /// Either it is an undef element in the shuffle mask, the element of the input
7671 /// referenced is undef, or the element of the input referenced is known to be
7672 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7673 /// as many lanes with this technique as possible to simplify the remaining
7675 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7676 SDValue V1, SDValue V2) {
7677 SmallBitVector Zeroable(Mask.size(), false);
7679 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7680 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7682 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7684 // Handle the easy cases.
7685 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7690 // If this is an index into a build_vector node, dig out the input value and
7692 SDValue V = M < Size ? V1 : V2;
7693 if (V.getOpcode() != ISD::BUILD_VECTOR)
7696 SDValue Input = V.getOperand(M % Size);
7697 // The UNDEF opcode check really should be dead code here, but not quite
7698 // worth asserting on (it isn't invalid, just unexpected).
7699 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7706 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7708 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7709 /// byte-shift instructions. The mask must consist of a shifted sequential
7710 /// shuffle from one of the input vectors and zeroable elements for the
7711 /// remaining 'shifted in' elements.
7713 /// Note that this only handles 128-bit vector widths currently.
7714 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7715 SDValue V2, ArrayRef<int> Mask,
7716 SelectionDAG &DAG) {
7717 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7719 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7721 int Size = Mask.size();
7722 int Scale = 16 / Size;
7724 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7725 ArrayRef<int> Mask) {
7726 for (int i = StartIndex; i < EndIndex; i++) {
7729 if (i + Base != Mask[i] - MaskOffset)
7735 for (int Shift = 1; Shift < Size; Shift++) {
7736 int ByteShift = Shift * Scale;
7738 // PSRLDQ : (little-endian) right byte shift
7739 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7740 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7741 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7742 bool ZeroableRight = true;
7743 for (int i = Size - Shift; i < Size; i++) {
7744 ZeroableRight &= Zeroable[i];
7747 if (ZeroableRight) {
7748 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7749 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7751 if (ValidShiftRight1 || ValidShiftRight2) {
7752 // Cast the inputs to v2i64 to match PSRLDQ.
7753 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7754 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7755 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7756 DAG.getConstant(ByteShift * 8, MVT::i8));
7757 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7761 // PSLLDQ : (little-endian) left byte shift
7762 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7763 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7764 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7765 bool ZeroableLeft = true;
7766 for (int i = 0; i < Shift; i++) {
7767 ZeroableLeft &= Zeroable[i];
7771 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7772 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7774 if (ValidShiftLeft1 || ValidShiftLeft2) {
7775 // Cast the inputs to v2i64 to match PSLLDQ.
7776 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7777 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7778 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7779 DAG.getConstant(ByteShift * 8, MVT::i8));
7780 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7788 /// \brief Lower a vector shuffle as a zero or any extension.
7790 /// Given a specific number of elements, element bit width, and extension
7791 /// stride, produce either a zero or any extension based on the available
7792 /// features of the subtarget.
7793 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7794 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7795 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7796 assert(Scale > 1 && "Need a scale to extend.");
7797 int EltBits = VT.getSizeInBits() / NumElements;
7798 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7799 "Only 8, 16, and 32 bit elements can be extended.");
7800 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7802 // Found a valid zext mask! Try various lowering strategies based on the
7803 // input type and available ISA extensions.
7804 if (Subtarget->hasSSE41()) {
7805 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7806 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7807 NumElements / Scale);
7808 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7809 return DAG.getNode(ISD::BITCAST, DL, VT,
7810 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7813 // For any extends we can cheat for larger element sizes and use shuffle
7814 // instructions that can fold with a load and/or copy.
7815 if (AnyExt && EltBits == 32) {
7816 int PSHUFDMask[4] = {0, -1, 1, -1};
7818 ISD::BITCAST, DL, VT,
7819 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7820 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7821 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7823 if (AnyExt && EltBits == 16 && Scale > 2) {
7824 int PSHUFDMask[4] = {0, -1, 0, -1};
7825 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7826 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7827 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7828 int PSHUFHWMask[4] = {1, -1, -1, -1};
7830 ISD::BITCAST, DL, VT,
7831 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7832 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7833 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7836 // If this would require more than 2 unpack instructions to expand, use
7837 // pshufb when available. We can only use more than 2 unpack instructions
7838 // when zero extending i8 elements which also makes it easier to use pshufb.
7839 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7840 assert(NumElements == 16 && "Unexpected byte vector width!");
7841 SDValue PSHUFBMask[16];
7842 for (int i = 0; i < 16; ++i)
7844 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7845 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7846 return DAG.getNode(ISD::BITCAST, DL, VT,
7847 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7848 DAG.getNode(ISD::BUILD_VECTOR, DL,
7849 MVT::v16i8, PSHUFBMask)));
7852 // Otherwise emit a sequence of unpacks.
7854 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7855 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7856 : getZeroVector(InputVT, Subtarget, DAG, DL);
7857 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7858 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7862 } while (Scale > 1);
7863 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7866 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7868 /// This routine will try to do everything in its power to cleverly lower
7869 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7870 /// check for the profitability of this lowering, it tries to aggressively
7871 /// match this pattern. It will use all of the micro-architectural details it
7872 /// can to emit an efficient lowering. It handles both blends with all-zero
7873 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7874 /// masking out later).
7876 /// The reason we have dedicated lowering for zext-style shuffles is that they
7877 /// are both incredibly common and often quite performance sensitive.
7878 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7879 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7880 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7881 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7883 int Bits = VT.getSizeInBits();
7884 int NumElements = Mask.size();
7886 // Define a helper function to check a particular ext-scale and lower to it if
7888 auto Lower = [&](int Scale) -> SDValue {
7891 for (int i = 0; i < NumElements; ++i) {
7893 continue; // Valid anywhere but doesn't tell us anything.
7894 if (i % Scale != 0) {
7895 // Each of the extend elements needs to be zeroable.
7899 // We no lorger are in the anyext case.
7904 // Each of the base elements needs to be consecutive indices into the
7905 // same input vector.
7906 SDValue V = Mask[i] < NumElements ? V1 : V2;
7909 else if (InputV != V)
7910 return SDValue(); // Flip-flopping inputs.
7912 if (Mask[i] % NumElements != i / Scale)
7913 return SDValue(); // Non-consecutive strided elemenst.
7916 // If we fail to find an input, we have a zero-shuffle which should always
7917 // have already been handled.
7918 // FIXME: Maybe handle this here in case during blending we end up with one?
7922 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7923 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7926 // The widest scale possible for extending is to a 64-bit integer.
7927 assert(Bits % 64 == 0 &&
7928 "The number of bits in a vector must be divisible by 64 on x86!");
7929 int NumExtElements = Bits / 64;
7931 // Each iteration, try extending the elements half as much, but into twice as
7933 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7934 assert(NumElements % NumExtElements == 0 &&
7935 "The input vector size must be divisble by the extended size.");
7936 if (SDValue V = Lower(NumElements / NumExtElements))
7940 // No viable ext lowering found.
7944 /// \brief Try to get a scalar value for a specific element of a vector.
7946 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7947 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7948 SelectionDAG &DAG) {
7949 MVT VT = V.getSimpleValueType();
7950 MVT EltVT = VT.getVectorElementType();
7951 while (V.getOpcode() == ISD::BITCAST)
7952 V = V.getOperand(0);
7953 // If the bitcasts shift the element size, we can't extract an equivalent
7955 MVT NewVT = V.getSimpleValueType();
7956 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7959 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7960 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7961 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7966 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7968 /// This is particularly important because the set of instructions varies
7969 /// significantly based on whether the operand is a load or not.
7970 static bool isShuffleFoldableLoad(SDValue V) {
7971 while (V.getOpcode() == ISD::BITCAST)
7972 V = V.getOperand(0);
7974 return ISD::isNON_EXTLoad(V.getNode());
7977 /// \brief Try to lower insertion of a single element into a zero vector.
7979 /// This is a common pattern that we have especially efficient patterns to lower
7980 /// across all subtarget feature sets.
7981 static SDValue lowerVectorShuffleAsElementInsertion(
7982 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7983 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7984 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7986 MVT EltVT = VT.getVectorElementType();
7988 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7989 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7991 bool IsV1Zeroable = true;
7992 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7993 if (i != V2Index && !Zeroable[i]) {
7994 IsV1Zeroable = false;
7998 // Check for a single input from a SCALAR_TO_VECTOR node.
7999 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
8000 // all the smarts here sunk into that routine. However, the current
8001 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8002 // vector shuffle lowering is dead.
8003 if (SDValue V2S = getScalarValueForVectorElement(
8004 V2, Mask[V2Index] - Mask.size(), DAG)) {
8005 // We need to zext the scalar if it is smaller than an i32.
8006 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8007 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8008 // Using zext to expand a narrow element won't work for non-zero
8013 // Zero-extend directly to i32.
8015 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8017 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8018 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8019 EltVT == MVT::i16) {
8020 // Either not inserting from the low element of the input or the input
8021 // element size is too small to use VZEXT_MOVL to clear the high bits.
8025 if (!IsV1Zeroable) {
8026 // If V1 can't be treated as a zero vector we have fewer options to lower
8027 // this. We can't support integer vectors or non-zero targets cheaply, and
8028 // the V1 elements can't be permuted in any way.
8029 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8030 if (!VT.isFloatingPoint() || V2Index != 0)
8032 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8033 V1Mask[V2Index] = -1;
8034 if (!isNoopShuffleMask(V1Mask))
8036 // This is essentially a special case blend operation, but if we have
8037 // general purpose blend operations, they are always faster. Bail and let
8038 // the rest of the lowering handle these as blends.
8039 if (Subtarget->hasSSE41())
8042 // Otherwise, use MOVSD or MOVSS.
8043 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8044 "Only two types of floating point element types to handle!");
8045 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8049 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8051 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8054 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8055 // the desired position. Otherwise it is more efficient to do a vector
8056 // shift left. We know that we can do a vector shift left because all
8057 // the inputs are zero.
8058 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8059 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8060 V2Shuffle[V2Index] = 0;
8061 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8063 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8065 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8067 V2Index * EltVT.getSizeInBits(),
8068 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8069 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8075 /// \brief Try to lower broadcast of a single element.
8077 /// For convenience, this code also bundles all of the subtarget feature set
8078 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8079 /// a convenient way to factor it out.
8080 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8082 const X86Subtarget *Subtarget,
8083 SelectionDAG &DAG) {
8084 if (!Subtarget->hasAVX())
8086 if (VT.isInteger() && !Subtarget->hasAVX2())
8089 // Check that the mask is a broadcast.
8090 int BroadcastIdx = -1;
8092 if (M >= 0 && BroadcastIdx == -1)
8094 else if (M >= 0 && M != BroadcastIdx)
8097 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8098 "a sorted mask where the broadcast "
8101 // Go up the chain of (vector) values to try and find a scalar load that
8102 // we can combine with the broadcast.
8104 switch (V.getOpcode()) {
8105 case ISD::CONCAT_VECTORS: {
8106 int OperandSize = Mask.size() / V.getNumOperands();
8107 V = V.getOperand(BroadcastIdx / OperandSize);
8108 BroadcastIdx %= OperandSize;
8112 case ISD::INSERT_SUBVECTOR: {
8113 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8114 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8118 int BeginIdx = (int)ConstantIdx->getZExtValue();
8120 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8121 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8122 BroadcastIdx -= BeginIdx;
8133 // Check if this is a broadcast of a scalar. We special case lowering
8134 // for scalars so that we can more effectively fold with loads.
8135 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8136 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8137 V = V.getOperand(BroadcastIdx);
8139 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8141 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8143 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8144 // We can't broadcast from a vector register w/o AVX2, and we can only
8145 // broadcast from the zero-element of a vector register.
8149 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8152 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8154 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8155 /// support for floating point shuffles but not integer shuffles. These
8156 /// instructions will incur a domain crossing penalty on some chips though so
8157 /// it is better to avoid lowering through this for integer vectors where
8159 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8160 const X86Subtarget *Subtarget,
8161 SelectionDAG &DAG) {
8163 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8164 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8165 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8166 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8167 ArrayRef<int> Mask = SVOp->getMask();
8168 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8170 if (isSingleInputShuffleMask(Mask)) {
8171 // Straight shuffle of a single input vector. Simulate this by using the
8172 // single input as both of the "inputs" to this instruction..
8173 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8175 if (Subtarget->hasAVX()) {
8176 // If we have AVX, we can use VPERMILPS which will allow folding a load
8177 // into the shuffle.
8178 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8179 DAG.getConstant(SHUFPDMask, MVT::i8));
8182 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8183 DAG.getConstant(SHUFPDMask, MVT::i8));
8185 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8186 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8188 // Use dedicated unpack instructions for masks that match their pattern.
8189 if (isShuffleEquivalent(Mask, 0, 2))
8190 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8191 if (isShuffleEquivalent(Mask, 1, 3))
8192 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8194 // If we have a single input, insert that into V1 if we can do so cheaply.
8195 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8196 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8197 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8199 // Try inverting the insertion since for v2 masks it is easy to do and we
8200 // can't reliably sort the mask one way or the other.
8201 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8202 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8203 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8204 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8208 // Try to use one of the special instruction patterns to handle two common
8209 // blend patterns if a zero-blend above didn't work.
8210 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8211 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8212 // We can either use a special instruction to load over the low double or
8213 // to move just the low double.
8215 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8217 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8219 if (Subtarget->hasSSE41())
8220 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8224 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8225 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8226 DAG.getConstant(SHUFPDMask, MVT::i8));
8229 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8231 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8232 /// the integer unit to minimize domain crossing penalties. However, for blends
8233 /// it falls back to the floating point shuffle operation with appropriate bit
8235 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8236 const X86Subtarget *Subtarget,
8237 SelectionDAG &DAG) {
8239 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8240 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8241 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8243 ArrayRef<int> Mask = SVOp->getMask();
8244 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8246 if (isSingleInputShuffleMask(Mask)) {
8247 // Check for being able to broadcast a single element.
8248 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8249 Mask, Subtarget, DAG))
8252 // Straight shuffle of a single input vector. For everything from SSE2
8253 // onward this has a single fast instruction with no scary immediates.
8254 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8255 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8256 int WidenedMask[4] = {
8257 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8258 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8260 ISD::BITCAST, DL, MVT::v2i64,
8261 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8262 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8265 // Try to use byte shift instructions.
8266 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8267 DL, MVT::v2i64, V1, V2, Mask, DAG))
8270 // If we have a single input from V2 insert that into V1 if we can do so
8272 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8273 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8274 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8276 // Try inverting the insertion since for v2 masks it is easy to do and we
8277 // can't reliably sort the mask one way or the other.
8278 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8279 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8280 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8281 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8285 // Use dedicated unpack instructions for masks that match their pattern.
8286 if (isShuffleEquivalent(Mask, 0, 2))
8287 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8288 if (isShuffleEquivalent(Mask, 1, 3))
8289 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8291 if (Subtarget->hasSSE41())
8292 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8296 // Try to use byte rotation instructions.
8297 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8298 if (Subtarget->hasSSSE3())
8299 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8300 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8303 // We implement this with SHUFPD which is pretty lame because it will likely
8304 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8305 // However, all the alternatives are still more cycles and newer chips don't
8306 // have this problem. It would be really nice if x86 had better shuffles here.
8307 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8308 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8309 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8310 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8313 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8315 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8316 /// It makes no assumptions about whether this is the *best* lowering, it simply
8318 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8319 ArrayRef<int> Mask, SDValue V1,
8320 SDValue V2, SelectionDAG &DAG) {
8321 SDValue LowV = V1, HighV = V2;
8322 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8325 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8327 if (NumV2Elements == 1) {
8329 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8332 // Compute the index adjacent to V2Index and in the same half by toggling
8334 int V2AdjIndex = V2Index ^ 1;
8336 if (Mask[V2AdjIndex] == -1) {
8337 // Handles all the cases where we have a single V2 element and an undef.
8338 // This will only ever happen in the high lanes because we commute the
8339 // vector otherwise.
8341 std::swap(LowV, HighV);
8342 NewMask[V2Index] -= 4;
8344 // Handle the case where the V2 element ends up adjacent to a V1 element.
8345 // To make this work, blend them together as the first step.
8346 int V1Index = V2AdjIndex;
8347 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8348 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8349 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8351 // Now proceed to reconstruct the final blend as we have the necessary
8352 // high or low half formed.
8359 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8360 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8362 } else if (NumV2Elements == 2) {
8363 if (Mask[0] < 4 && Mask[1] < 4) {
8364 // Handle the easy case where we have V1 in the low lanes and V2 in the
8368 } else if (Mask[2] < 4 && Mask[3] < 4) {
8369 // We also handle the reversed case because this utility may get called
8370 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8371 // arrange things in the right direction.
8377 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8378 // trying to place elements directly, just blend them and set up the final
8379 // shuffle to place them.
8381 // The first two blend mask elements are for V1, the second two are for
8383 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8384 Mask[2] < 4 ? Mask[2] : Mask[3],
8385 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8386 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8387 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8388 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8390 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8393 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8394 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8395 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8396 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8399 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8400 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8403 /// \brief Lower 4-lane 32-bit floating point shuffles.
8405 /// Uses instructions exclusively from the floating point unit to minimize
8406 /// domain crossing penalties, as these are sufficient to implement all v4f32
8408 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8409 const X86Subtarget *Subtarget,
8410 SelectionDAG &DAG) {
8412 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8413 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8414 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8415 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8416 ArrayRef<int> Mask = SVOp->getMask();
8417 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8420 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8422 if (NumV2Elements == 0) {
8423 // Check for being able to broadcast a single element.
8424 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8425 Mask, Subtarget, DAG))
8428 if (Subtarget->hasAVX()) {
8429 // If we have AVX, we can use VPERMILPS which will allow folding a load
8430 // into the shuffle.
8431 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8432 getV4X86ShuffleImm8ForMask(Mask, DAG));
8435 // Otherwise, use a straight shuffle of a single input vector. We pass the
8436 // input vector to both operands to simulate this with a SHUFPS.
8437 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8438 getV4X86ShuffleImm8ForMask(Mask, DAG));
8441 // Use dedicated unpack instructions for masks that match their pattern.
8442 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8443 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8444 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8445 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8447 // There are special ways we can lower some single-element blends. However, we
8448 // have custom ways we can lower more complex single-element blends below that
8449 // we defer to if both this and BLENDPS fail to match, so restrict this to
8450 // when the V2 input is targeting element 0 of the mask -- that is the fast
8452 if (NumV2Elements == 1 && Mask[0] >= 4)
8453 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8454 Mask, Subtarget, DAG))
8457 if (Subtarget->hasSSE41())
8458 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8462 // Check for whether we can use INSERTPS to perform the blend. We only use
8463 // INSERTPS when the V1 elements are already in the correct locations
8464 // because otherwise we can just always use two SHUFPS instructions which
8465 // are much smaller to encode than a SHUFPS and an INSERTPS.
8466 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8468 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8471 // When using INSERTPS we can zero any lane of the destination. Collect
8472 // the zero inputs into a mask and drop them from the lanes of V1 which
8473 // actually need to be present as inputs to the INSERTPS.
8474 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8476 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8477 bool InsertNeedsShuffle = false;
8479 for (int i = 0; i < 4; ++i)
8483 } else if (Mask[i] != i) {
8484 InsertNeedsShuffle = true;
8489 // We don't want to use INSERTPS or other insertion techniques if it will
8490 // require shuffling anyways.
8491 if (!InsertNeedsShuffle) {
8492 // If all of V1 is zeroable, replace it with undef.
8493 if ((ZMask | 1 << V2Index) == 0xF)
8494 V1 = DAG.getUNDEF(MVT::v4f32);
8496 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8497 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8499 // Insert the V2 element into the desired position.
8500 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8501 DAG.getConstant(InsertPSMask, MVT::i8));
8505 // Otherwise fall back to a SHUFPS lowering strategy.
8506 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8509 /// \brief Lower 4-lane i32 vector shuffles.
8511 /// We try to handle these with integer-domain shuffles where we can, but for
8512 /// blends we use the floating point domain blend instructions.
8513 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8514 const X86Subtarget *Subtarget,
8515 SelectionDAG &DAG) {
8517 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8518 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8519 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8520 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8521 ArrayRef<int> Mask = SVOp->getMask();
8522 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8524 // Whenever we can lower this as a zext, that instruction is strictly faster
8525 // than any alternative. It also allows us to fold memory operands into the
8526 // shuffle in many cases.
8527 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8528 Mask, Subtarget, DAG))
8532 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8534 if (NumV2Elements == 0) {
8535 // Check for being able to broadcast a single element.
8536 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8537 Mask, Subtarget, DAG))
8540 // Straight shuffle of a single input vector. For everything from SSE2
8541 // onward this has a single fast instruction with no scary immediates.
8542 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8543 // but we aren't actually going to use the UNPCK instruction because doing
8544 // so prevents folding a load into this instruction or making a copy.
8545 const int UnpackLoMask[] = {0, 0, 1, 1};
8546 const int UnpackHiMask[] = {2, 2, 3, 3};
8547 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8548 Mask = UnpackLoMask;
8549 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8550 Mask = UnpackHiMask;
8552 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8553 getV4X86ShuffleImm8ForMask(Mask, DAG));
8556 // Try to use byte shift instructions.
8557 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8558 DL, MVT::v4i32, V1, V2, Mask, DAG))
8561 // There are special ways we can lower some single-element blends.
8562 if (NumV2Elements == 1)
8563 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8564 Mask, Subtarget, DAG))
8567 // Use dedicated unpack instructions for masks that match their pattern.
8568 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8569 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8570 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8571 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8573 if (Subtarget->hasSSE41())
8574 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8578 // Try to use byte rotation instructions.
8579 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8580 if (Subtarget->hasSSSE3())
8581 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8582 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8585 // We implement this with SHUFPS because it can blend from two vectors.
8586 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8587 // up the inputs, bypassing domain shift penalties that we would encur if we
8588 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8590 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8591 DAG.getVectorShuffle(
8593 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8594 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8597 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8598 /// shuffle lowering, and the most complex part.
8600 /// The lowering strategy is to try to form pairs of input lanes which are
8601 /// targeted at the same half of the final vector, and then use a dword shuffle
8602 /// to place them onto the right half, and finally unpack the paired lanes into
8603 /// their final position.
8605 /// The exact breakdown of how to form these dword pairs and align them on the
8606 /// correct sides is really tricky. See the comments within the function for
8607 /// more of the details.
8608 static SDValue lowerV8I16SingleInputVectorShuffle(
8609 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8610 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8611 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8612 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8613 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8615 SmallVector<int, 4> LoInputs;
8616 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8617 [](int M) { return M >= 0; });
8618 std::sort(LoInputs.begin(), LoInputs.end());
8619 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8620 SmallVector<int, 4> HiInputs;
8621 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8622 [](int M) { return M >= 0; });
8623 std::sort(HiInputs.begin(), HiInputs.end());
8624 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8626 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8627 int NumHToL = LoInputs.size() - NumLToL;
8629 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8630 int NumHToH = HiInputs.size() - NumLToH;
8631 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8632 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8633 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8634 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8636 // Check for being able to broadcast a single element.
8637 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8638 Mask, Subtarget, DAG))
8641 // Try to use byte shift instructions.
8642 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8643 DL, MVT::v8i16, V, V, Mask, DAG))
8646 // Use dedicated unpack instructions for masks that match their pattern.
8647 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8648 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8649 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8650 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8652 // Try to use byte rotation instructions.
8653 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8654 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8657 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8658 // such inputs we can swap two of the dwords across the half mark and end up
8659 // with <=2 inputs to each half in each half. Once there, we can fall through
8660 // to the generic code below. For example:
8662 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8663 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8665 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8666 // and an existing 2-into-2 on the other half. In this case we may have to
8667 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8668 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8669 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8670 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8671 // half than the one we target for fixing) will be fixed when we re-enter this
8672 // path. We will also combine away any sequence of PSHUFD instructions that
8673 // result into a single instruction. Here is an example of the tricky case:
8675 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8676 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8678 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8680 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8681 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8683 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8684 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8686 // The result is fine to be handled by the generic logic.
8687 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8688 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8689 int AOffset, int BOffset) {
8690 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8691 "Must call this with A having 3 or 1 inputs from the A half.");
8692 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8693 "Must call this with B having 1 or 3 inputs from the B half.");
8694 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8695 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8697 // Compute the index of dword with only one word among the three inputs in
8698 // a half by taking the sum of the half with three inputs and subtracting
8699 // the sum of the actual three inputs. The difference is the remaining
8702 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8703 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8704 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8705 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8706 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8707 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8708 int TripleNonInputIdx =
8709 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8710 TripleDWord = TripleNonInputIdx / 2;
8712 // We use xor with one to compute the adjacent DWord to whichever one the
8714 OneInputDWord = (OneInput / 2) ^ 1;
8716 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8717 // and BToA inputs. If there is also such a problem with the BToB and AToB
8718 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8719 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8720 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8721 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8722 // Compute how many inputs will be flipped by swapping these DWords. We
8724 // to balance this to ensure we don't form a 3-1 shuffle in the other
8726 int NumFlippedAToBInputs =
8727 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8728 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8729 int NumFlippedBToBInputs =
8730 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8731 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8732 if ((NumFlippedAToBInputs == 1 &&
8733 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8734 (NumFlippedBToBInputs == 1 &&
8735 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8736 // We choose whether to fix the A half or B half based on whether that
8737 // half has zero flipped inputs. At zero, we may not be able to fix it
8738 // with that half. We also bias towards fixing the B half because that
8739 // will more commonly be the high half, and we have to bias one way.
8740 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8741 ArrayRef<int> Inputs) {
8742 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8743 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8744 PinnedIdx ^ 1) != Inputs.end();
8745 // Determine whether the free index is in the flipped dword or the
8746 // unflipped dword based on where the pinned index is. We use this bit
8747 // in an xor to conditionally select the adjacent dword.
8748 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8749 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8750 FixFreeIdx) != Inputs.end();
8751 if (IsFixIdxInput == IsFixFreeIdxInput)
8753 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8754 FixFreeIdx) != Inputs.end();
8755 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8756 "We need to be changing the number of flipped inputs!");
8757 int PSHUFHalfMask[] = {0, 1, 2, 3};
8758 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8759 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8761 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8764 if (M != -1 && M == FixIdx)
8766 else if (M != -1 && M == FixFreeIdx)
8769 if (NumFlippedBToBInputs != 0) {
8771 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8772 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8774 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8776 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8777 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8782 int PSHUFDMask[] = {0, 1, 2, 3};
8783 PSHUFDMask[ADWord] = BDWord;
8784 PSHUFDMask[BDWord] = ADWord;
8785 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8786 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8787 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8788 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8790 // Adjust the mask to match the new locations of A and B.
8792 if (M != -1 && M/2 == ADWord)
8793 M = 2 * BDWord + M % 2;
8794 else if (M != -1 && M/2 == BDWord)
8795 M = 2 * ADWord + M % 2;
8797 // Recurse back into this routine to re-compute state now that this isn't
8798 // a 3 and 1 problem.
8799 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8802 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8803 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8804 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8805 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8807 // At this point there are at most two inputs to the low and high halves from
8808 // each half. That means the inputs can always be grouped into dwords and
8809 // those dwords can then be moved to the correct half with a dword shuffle.
8810 // We use at most one low and one high word shuffle to collect these paired
8811 // inputs into dwords, and finally a dword shuffle to place them.
8812 int PSHUFLMask[4] = {-1, -1, -1, -1};
8813 int PSHUFHMask[4] = {-1, -1, -1, -1};
8814 int PSHUFDMask[4] = {-1, -1, -1, -1};
8816 // First fix the masks for all the inputs that are staying in their
8817 // original halves. This will then dictate the targets of the cross-half
8819 auto fixInPlaceInputs =
8820 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8821 MutableArrayRef<int> SourceHalfMask,
8822 MutableArrayRef<int> HalfMask, int HalfOffset) {
8823 if (InPlaceInputs.empty())
8825 if (InPlaceInputs.size() == 1) {
8826 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8827 InPlaceInputs[0] - HalfOffset;
8828 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8831 if (IncomingInputs.empty()) {
8832 // Just fix all of the in place inputs.
8833 for (int Input : InPlaceInputs) {
8834 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8835 PSHUFDMask[Input / 2] = Input / 2;
8840 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8841 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8842 InPlaceInputs[0] - HalfOffset;
8843 // Put the second input next to the first so that they are packed into
8844 // a dword. We find the adjacent index by toggling the low bit.
8845 int AdjIndex = InPlaceInputs[0] ^ 1;
8846 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8847 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8848 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8850 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8851 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8853 // Now gather the cross-half inputs and place them into a free dword of
8854 // their target half.
8855 // FIXME: This operation could almost certainly be simplified dramatically to
8856 // look more like the 3-1 fixing operation.
8857 auto moveInputsToRightHalf = [&PSHUFDMask](
8858 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8859 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8860 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8862 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8863 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8865 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8867 int LowWord = Word & ~1;
8868 int HighWord = Word | 1;
8869 return isWordClobbered(SourceHalfMask, LowWord) ||
8870 isWordClobbered(SourceHalfMask, HighWord);
8873 if (IncomingInputs.empty())
8876 if (ExistingInputs.empty()) {
8877 // Map any dwords with inputs from them into the right half.
8878 for (int Input : IncomingInputs) {
8879 // If the source half mask maps over the inputs, turn those into
8880 // swaps and use the swapped lane.
8881 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8882 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8883 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8884 Input - SourceOffset;
8885 // We have to swap the uses in our half mask in one sweep.
8886 for (int &M : HalfMask)
8887 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8889 else if (M == Input)
8890 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8892 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8893 Input - SourceOffset &&
8894 "Previous placement doesn't match!");
8896 // Note that this correctly re-maps both when we do a swap and when
8897 // we observe the other side of the swap above. We rely on that to
8898 // avoid swapping the members of the input list directly.
8899 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8902 // Map the input's dword into the correct half.
8903 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8904 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8906 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8908 "Previous placement doesn't match!");
8911 // And just directly shift any other-half mask elements to be same-half
8912 // as we will have mirrored the dword containing the element into the
8913 // same position within that half.
8914 for (int &M : HalfMask)
8915 if (M >= SourceOffset && M < SourceOffset + 4) {
8916 M = M - SourceOffset + DestOffset;
8917 assert(M >= 0 && "This should never wrap below zero!");
8922 // Ensure we have the input in a viable dword of its current half. This
8923 // is particularly tricky because the original position may be clobbered
8924 // by inputs being moved and *staying* in that half.
8925 if (IncomingInputs.size() == 1) {
8926 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8927 int InputFixed = std::find(std::begin(SourceHalfMask),
8928 std::end(SourceHalfMask), -1) -
8929 std::begin(SourceHalfMask) + SourceOffset;
8930 SourceHalfMask[InputFixed - SourceOffset] =
8931 IncomingInputs[0] - SourceOffset;
8932 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8934 IncomingInputs[0] = InputFixed;
8936 } else if (IncomingInputs.size() == 2) {
8937 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8938 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8939 // We have two non-adjacent or clobbered inputs we need to extract from
8940 // the source half. To do this, we need to map them into some adjacent
8941 // dword slot in the source mask.
8942 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8943 IncomingInputs[1] - SourceOffset};
8945 // If there is a free slot in the source half mask adjacent to one of
8946 // the inputs, place the other input in it. We use (Index XOR 1) to
8947 // compute an adjacent index.
8948 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8949 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8950 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8951 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8952 InputsFixed[1] = InputsFixed[0] ^ 1;
8953 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8954 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8955 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8956 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8957 InputsFixed[0] = InputsFixed[1] ^ 1;
8958 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8959 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8960 // The two inputs are in the same DWord but it is clobbered and the
8961 // adjacent DWord isn't used at all. Move both inputs to the free
8963 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8964 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8965 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8966 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8968 // The only way we hit this point is if there is no clobbering
8969 // (because there are no off-half inputs to this half) and there is no
8970 // free slot adjacent to one of the inputs. In this case, we have to
8971 // swap an input with a non-input.
8972 for (int i = 0; i < 4; ++i)
8973 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8974 "We can't handle any clobbers here!");
8975 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8976 "Cannot have adjacent inputs here!");
8978 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8979 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8981 // We also have to update the final source mask in this case because
8982 // it may need to undo the above swap.
8983 for (int &M : FinalSourceHalfMask)
8984 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8985 M = InputsFixed[1] + SourceOffset;
8986 else if (M == InputsFixed[1] + SourceOffset)
8987 M = (InputsFixed[0] ^ 1) + SourceOffset;
8989 InputsFixed[1] = InputsFixed[0] ^ 1;
8992 // Point everything at the fixed inputs.
8993 for (int &M : HalfMask)
8994 if (M == IncomingInputs[0])
8995 M = InputsFixed[0] + SourceOffset;
8996 else if (M == IncomingInputs[1])
8997 M = InputsFixed[1] + SourceOffset;
8999 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9000 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9003 llvm_unreachable("Unhandled input size!");
9006 // Now hoist the DWord down to the right half.
9007 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9008 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9009 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9010 for (int &M : HalfMask)
9011 for (int Input : IncomingInputs)
9013 M = FreeDWord * 2 + Input % 2;
9015 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9016 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9017 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9018 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9020 // Now enact all the shuffles we've computed to move the inputs into their
9022 if (!isNoopShuffleMask(PSHUFLMask))
9023 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9024 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9025 if (!isNoopShuffleMask(PSHUFHMask))
9026 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9027 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9028 if (!isNoopShuffleMask(PSHUFDMask))
9029 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9030 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9031 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9032 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9034 // At this point, each half should contain all its inputs, and we can then
9035 // just shuffle them into their final position.
9036 assert(std::count_if(LoMask.begin(), LoMask.end(),
9037 [](int M) { return M >= 4; }) == 0 &&
9038 "Failed to lift all the high half inputs to the low mask!");
9039 assert(std::count_if(HiMask.begin(), HiMask.end(),
9040 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9041 "Failed to lift all the low half inputs to the high mask!");
9043 // Do a half shuffle for the low mask.
9044 if (!isNoopShuffleMask(LoMask))
9045 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9046 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9048 // Do a half shuffle with the high mask after shifting its values down.
9049 for (int &M : HiMask)
9052 if (!isNoopShuffleMask(HiMask))
9053 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9054 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9059 /// \brief Detect whether the mask pattern should be lowered through
9062 /// This essentially tests whether viewing the mask as an interleaving of two
9063 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9064 /// lowering it through interleaving is a significantly better strategy.
9065 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9066 int NumEvenInputs[2] = {0, 0};
9067 int NumOddInputs[2] = {0, 0};
9068 int NumLoInputs[2] = {0, 0};
9069 int NumHiInputs[2] = {0, 0};
9070 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9074 int InputIdx = Mask[i] >= Size;
9077 ++NumLoInputs[InputIdx];
9079 ++NumHiInputs[InputIdx];
9082 ++NumEvenInputs[InputIdx];
9084 ++NumOddInputs[InputIdx];
9087 // The minimum number of cross-input results for both the interleaved and
9088 // split cases. If interleaving results in fewer cross-input results, return
9090 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9091 NumEvenInputs[0] + NumOddInputs[1]);
9092 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9093 NumLoInputs[0] + NumHiInputs[1]);
9094 return InterleavedCrosses < SplitCrosses;
9097 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9099 /// This strategy only works when the inputs from each vector fit into a single
9100 /// half of that vector, and generally there are not so many inputs as to leave
9101 /// the in-place shuffles required highly constrained (and thus expensive). It
9102 /// shifts all the inputs into a single side of both input vectors and then
9103 /// uses an unpack to interleave these inputs in a single vector. At that
9104 /// point, we will fall back on the generic single input shuffle lowering.
9105 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9107 MutableArrayRef<int> Mask,
9108 const X86Subtarget *Subtarget,
9109 SelectionDAG &DAG) {
9110 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9111 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9112 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9113 for (int i = 0; i < 8; ++i)
9114 if (Mask[i] >= 0 && Mask[i] < 4)
9115 LoV1Inputs.push_back(i);
9116 else if (Mask[i] >= 4 && Mask[i] < 8)
9117 HiV1Inputs.push_back(i);
9118 else if (Mask[i] >= 8 && Mask[i] < 12)
9119 LoV2Inputs.push_back(i);
9120 else if (Mask[i] >= 12)
9121 HiV2Inputs.push_back(i);
9123 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9124 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9127 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9128 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9129 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9131 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9132 HiV1Inputs.size() + HiV2Inputs.size();
9134 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9135 ArrayRef<int> HiInputs, bool MoveToLo,
9137 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9138 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9139 if (BadInputs.empty())
9142 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9143 int MoveOffset = MoveToLo ? 0 : 4;
9145 if (GoodInputs.empty()) {
9146 for (int BadInput : BadInputs) {
9147 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9148 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9151 if (GoodInputs.size() == 2) {
9152 // If the low inputs are spread across two dwords, pack them into
9154 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9155 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9156 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9157 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9159 // Otherwise pin the good inputs.
9160 for (int GoodInput : GoodInputs)
9161 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9164 if (BadInputs.size() == 2) {
9165 // If we have two bad inputs then there may be either one or two good
9166 // inputs fixed in place. Find a fixed input, and then find the *other*
9167 // two adjacent indices by using modular arithmetic.
9169 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9170 [](int M) { return M >= 0; }) -
9171 std::begin(MoveMask);
9173 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9174 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9175 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9176 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9177 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9178 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9179 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9181 assert(BadInputs.size() == 1 && "All sizes handled");
9182 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9183 std::end(MoveMask), -1) -
9184 std::begin(MoveMask);
9185 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9186 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9190 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9193 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9195 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9198 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9199 // cross-half traffic in the final shuffle.
9201 // Munge the mask to be a single-input mask after the unpack merges the
9205 M = 2 * (M % 4) + (M / 8);
9207 return DAG.getVectorShuffle(
9208 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9209 DL, MVT::v8i16, V1, V2),
9210 DAG.getUNDEF(MVT::v8i16), Mask);
9213 /// \brief Generic lowering of 8-lane i16 shuffles.
9215 /// This handles both single-input shuffles and combined shuffle/blends with
9216 /// two inputs. The single input shuffles are immediately delegated to
9217 /// a dedicated lowering routine.
9219 /// The blends are lowered in one of three fundamental ways. If there are few
9220 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9221 /// of the input is significantly cheaper when lowered as an interleaving of
9222 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9223 /// halves of the inputs separately (making them have relatively few inputs)
9224 /// and then concatenate them.
9225 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9226 const X86Subtarget *Subtarget,
9227 SelectionDAG &DAG) {
9229 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9230 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9231 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9232 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9233 ArrayRef<int> OrigMask = SVOp->getMask();
9234 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9235 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9236 MutableArrayRef<int> Mask(MaskStorage);
9238 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9240 // Whenever we can lower this as a zext, that instruction is strictly faster
9241 // than any alternative.
9242 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9243 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9246 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9247 auto isV2 = [](int M) { return M >= 8; };
9249 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9250 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9252 if (NumV2Inputs == 0)
9253 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9255 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9256 "to be V1-input shuffles.");
9258 // Try to use byte shift instructions.
9259 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9260 DL, MVT::v8i16, V1, V2, Mask, DAG))
9263 // There are special ways we can lower some single-element blends.
9264 if (NumV2Inputs == 1)
9265 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9266 Mask, Subtarget, DAG))
9269 // Use dedicated unpack instructions for masks that match their pattern.
9270 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9271 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9272 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9273 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9275 if (Subtarget->hasSSE41())
9276 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9280 // Try to use byte rotation instructions.
9281 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9282 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9285 if (NumV1Inputs + NumV2Inputs <= 4)
9286 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9288 // Check whether an interleaving lowering is likely to be more efficient.
9289 // This isn't perfect but it is a strong heuristic that tends to work well on
9290 // the kinds of shuffles that show up in practice.
9292 // FIXME: Handle 1x, 2x, and 4x interleaving.
9293 if (shouldLowerAsInterleaving(Mask)) {
9294 // FIXME: Figure out whether we should pack these into the low or high
9297 int EMask[8], OMask[8];
9298 for (int i = 0; i < 4; ++i) {
9299 EMask[i] = Mask[2*i];
9300 OMask[i] = Mask[2*i + 1];
9305 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9306 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9308 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9311 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9312 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9314 for (int i = 0; i < 4; ++i) {
9315 LoBlendMask[i] = Mask[i];
9316 HiBlendMask[i] = Mask[i + 4];
9319 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9320 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9321 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9322 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9324 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9325 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9328 /// \brief Check whether a compaction lowering can be done by dropping even
9329 /// elements and compute how many times even elements must be dropped.
9331 /// This handles shuffles which take every Nth element where N is a power of
9332 /// two. Example shuffle masks:
9334 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9335 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9336 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9337 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9338 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9339 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9341 /// Any of these lanes can of course be undef.
9343 /// This routine only supports N <= 3.
9344 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9347 /// \returns N above, or the number of times even elements must be dropped if
9348 /// there is such a number. Otherwise returns zero.
9349 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9350 // Figure out whether we're looping over two inputs or just one.
9351 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9353 // The modulus for the shuffle vector entries is based on whether this is
9354 // a single input or not.
9355 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9356 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9357 "We should only be called with masks with a power-of-2 size!");
9359 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9361 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9362 // and 2^3 simultaneously. This is because we may have ambiguity with
9363 // partially undef inputs.
9364 bool ViableForN[3] = {true, true, true};
9366 for (int i = 0, e = Mask.size(); i < e; ++i) {
9367 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9372 bool IsAnyViable = false;
9373 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9374 if (ViableForN[j]) {
9377 // The shuffle mask must be equal to (i * 2^N) % M.
9378 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9381 ViableForN[j] = false;
9383 // Early exit if we exhaust the possible powers of two.
9388 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9392 // Return 0 as there is no viable power of two.
9396 /// \brief Generic lowering of v16i8 shuffles.
9398 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9399 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9400 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9401 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9403 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9404 const X86Subtarget *Subtarget,
9405 SelectionDAG &DAG) {
9407 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9408 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9409 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9410 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9411 ArrayRef<int> OrigMask = SVOp->getMask();
9412 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9414 // Try to use byte shift instructions.
9415 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9416 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9419 // Try to use byte rotation instructions.
9420 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9421 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9424 // Try to use a zext lowering.
9425 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9426 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9429 int MaskStorage[16] = {
9430 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9431 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9432 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9433 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9434 MutableArrayRef<int> Mask(MaskStorage);
9435 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9436 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9439 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9441 // For single-input shuffles, there are some nicer lowering tricks we can use.
9442 if (NumV2Elements == 0) {
9443 // Check for being able to broadcast a single element.
9444 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9445 Mask, Subtarget, DAG))
9448 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9449 // Notably, this handles splat and partial-splat shuffles more efficiently.
9450 // However, it only makes sense if the pre-duplication shuffle simplifies
9451 // things significantly. Currently, this means we need to be able to
9452 // express the pre-duplication shuffle as an i16 shuffle.
9454 // FIXME: We should check for other patterns which can be widened into an
9455 // i16 shuffle as well.
9456 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9457 for (int i = 0; i < 16; i += 2)
9458 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9463 auto tryToWidenViaDuplication = [&]() -> SDValue {
9464 if (!canWidenViaDuplication(Mask))
9466 SmallVector<int, 4> LoInputs;
9467 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9468 [](int M) { return M >= 0 && M < 8; });
9469 std::sort(LoInputs.begin(), LoInputs.end());
9470 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9472 SmallVector<int, 4> HiInputs;
9473 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9474 [](int M) { return M >= 8; });
9475 std::sort(HiInputs.begin(), HiInputs.end());
9476 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9479 bool TargetLo = LoInputs.size() >= HiInputs.size();
9480 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9481 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9483 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9484 SmallDenseMap<int, int, 8> LaneMap;
9485 for (int I : InPlaceInputs) {
9486 PreDupI16Shuffle[I/2] = I/2;
9489 int j = TargetLo ? 0 : 4, je = j + 4;
9490 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9491 // Check if j is already a shuffle of this input. This happens when
9492 // there are two adjacent bytes after we move the low one.
9493 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9494 // If we haven't yet mapped the input, search for a slot into which
9496 while (j < je && PreDupI16Shuffle[j] != -1)
9500 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9503 // Map this input with the i16 shuffle.
9504 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9507 // Update the lane map based on the mapping we ended up with.
9508 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9511 ISD::BITCAST, DL, MVT::v16i8,
9512 DAG.getVectorShuffle(MVT::v8i16, DL,
9513 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9514 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9516 // Unpack the bytes to form the i16s that will be shuffled into place.
9517 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9518 MVT::v16i8, V1, V1);
9520 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9521 for (int i = 0; i < 16; ++i)
9522 if (Mask[i] != -1) {
9523 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9524 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9525 if (PostDupI16Shuffle[i / 2] == -1)
9526 PostDupI16Shuffle[i / 2] = MappedMask;
9528 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9529 "Conflicting entrties in the original shuffle!");
9532 ISD::BITCAST, DL, MVT::v16i8,
9533 DAG.getVectorShuffle(MVT::v8i16, DL,
9534 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9535 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9537 if (SDValue V = tryToWidenViaDuplication())
9541 // Check whether an interleaving lowering is likely to be more efficient.
9542 // This isn't perfect but it is a strong heuristic that tends to work well on
9543 // the kinds of shuffles that show up in practice.
9545 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9546 if (shouldLowerAsInterleaving(Mask)) {
9547 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9548 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9550 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9551 return (M >= 8 && M < 16) || M >= 24;
9553 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9554 -1, -1, -1, -1, -1, -1, -1, -1};
9555 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9556 -1, -1, -1, -1, -1, -1, -1, -1};
9557 bool UnpackLo = NumLoHalf >= NumHiHalf;
9558 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9559 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9560 for (int i = 0; i < 8; ++i) {
9561 TargetEMask[i] = Mask[2 * i];
9562 TargetOMask[i] = Mask[2 * i + 1];
9565 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9566 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9568 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9569 MVT::v16i8, Evens, Odds);
9572 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9573 // with PSHUFB. It is important to do this before we attempt to generate any
9574 // blends but after all of the single-input lowerings. If the single input
9575 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9576 // want to preserve that and we can DAG combine any longer sequences into
9577 // a PSHUFB in the end. But once we start blending from multiple inputs,
9578 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9579 // and there are *very* few patterns that would actually be faster than the
9580 // PSHUFB approach because of its ability to zero lanes.
9582 // FIXME: The only exceptions to the above are blends which are exact
9583 // interleavings with direct instructions supporting them. We currently don't
9584 // handle those well here.
9585 if (Subtarget->hasSSSE3()) {
9588 for (int i = 0; i < 16; ++i)
9589 if (Mask[i] == -1) {
9590 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9592 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9594 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9596 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9597 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9598 if (isSingleInputShuffleMask(Mask))
9599 return V1; // Single inputs are easy.
9601 // Otherwise, blend the two.
9602 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9603 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9604 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9607 // There are special ways we can lower some single-element blends.
9608 if (NumV2Elements == 1)
9609 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9610 Mask, Subtarget, DAG))
9613 // Check whether a compaction lowering can be done. This handles shuffles
9614 // which take every Nth element for some even N. See the helper function for
9617 // We special case these as they can be particularly efficiently handled with
9618 // the PACKUSB instruction on x86 and they show up in common patterns of
9619 // rearranging bytes to truncate wide elements.
9620 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9621 // NumEvenDrops is the power of two stride of the elements. Another way of
9622 // thinking about it is that we need to drop the even elements this many
9623 // times to get the original input.
9624 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9626 // First we need to zero all the dropped bytes.
9627 assert(NumEvenDrops <= 3 &&
9628 "No support for dropping even elements more than 3 times.");
9629 // We use the mask type to pick which bytes are preserved based on how many
9630 // elements are dropped.
9631 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9632 SDValue ByteClearMask =
9633 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9634 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9635 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9637 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9639 // Now pack things back together.
9640 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9641 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9642 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9643 for (int i = 1; i < NumEvenDrops; ++i) {
9644 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9645 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9651 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9652 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9653 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9654 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9656 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9657 MutableArrayRef<int> V1HalfBlendMask,
9658 MutableArrayRef<int> V2HalfBlendMask) {
9659 for (int i = 0; i < 8; ++i)
9660 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9661 V1HalfBlendMask[i] = HalfMask[i];
9663 } else if (HalfMask[i] >= 16) {
9664 V2HalfBlendMask[i] = HalfMask[i] - 16;
9665 HalfMask[i] = i + 8;
9668 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9669 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9671 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9673 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9674 MutableArrayRef<int> HiBlendMask) {
9676 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9677 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9679 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9680 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9681 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9682 [](int M) { return M >= 0 && M % 2 == 1; })) {
9683 // Use a mask to drop the high bytes.
9684 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9685 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9686 DAG.getConstant(0x00FF, MVT::v8i16));
9688 // This will be a single vector shuffle instead of a blend so nuke V2.
9689 V2 = DAG.getUNDEF(MVT::v8i16);
9691 // Squash the masks to point directly into V1.
9692 for (int &M : LoBlendMask)
9695 for (int &M : HiBlendMask)
9699 // Otherwise just unpack the low half of V into V1 and the high half into
9700 // V2 so that we can blend them as i16s.
9701 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9702 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9703 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9704 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9707 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9708 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9709 return std::make_pair(BlendedLo, BlendedHi);
9711 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9712 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9713 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9715 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9716 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9718 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9721 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9723 /// This routine breaks down the specific type of 128-bit shuffle and
9724 /// dispatches to the lowering routines accordingly.
9725 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9726 MVT VT, const X86Subtarget *Subtarget,
9727 SelectionDAG &DAG) {
9728 switch (VT.SimpleTy) {
9730 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9732 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9734 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9736 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9738 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9740 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9743 llvm_unreachable("Unimplemented!");
9747 /// \brief Helper function to test whether a shuffle mask could be
9748 /// simplified by widening the elements being shuffled.
9750 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9751 /// leaves it in an unspecified state.
9753 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9754 /// shuffle masks. The latter have the special property of a '-2' representing
9755 /// a zero-ed lane of a vector.
9756 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9757 SmallVectorImpl<int> &WidenedMask) {
9758 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9759 // If both elements are undef, its trivial.
9760 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9761 WidenedMask.push_back(SM_SentinelUndef);
9765 // Check for an undef mask and a mask value properly aligned to fit with
9766 // a pair of values. If we find such a case, use the non-undef mask's value.
9767 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9768 WidenedMask.push_back(Mask[i + 1] / 2);
9771 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9772 WidenedMask.push_back(Mask[i] / 2);
9776 // When zeroing, we need to spread the zeroing across both lanes to widen.
9777 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9778 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9779 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9780 WidenedMask.push_back(SM_SentinelZero);
9786 // Finally check if the two mask values are adjacent and aligned with
9788 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9789 WidenedMask.push_back(Mask[i] / 2);
9793 // Otherwise we can't safely widen the elements used in this shuffle.
9796 assert(WidenedMask.size() == Mask.size() / 2 &&
9797 "Incorrect size of mask after widening the elements!");
9802 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9804 /// This routine just extracts two subvectors, shuffles them independently, and
9805 /// then concatenates them back together. This should work effectively with all
9806 /// AVX vector shuffle types.
9807 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9808 SDValue V2, ArrayRef<int> Mask,
9809 SelectionDAG &DAG) {
9810 assert(VT.getSizeInBits() >= 256 &&
9811 "Only for 256-bit or wider vector shuffles!");
9812 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9813 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9815 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9816 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9818 int NumElements = VT.getVectorNumElements();
9819 int SplitNumElements = NumElements / 2;
9820 MVT ScalarVT = VT.getScalarType();
9821 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9823 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9824 DAG.getIntPtrConstant(0));
9825 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9826 DAG.getIntPtrConstant(SplitNumElements));
9827 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9828 DAG.getIntPtrConstant(0));
9829 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9830 DAG.getIntPtrConstant(SplitNumElements));
9832 // Now create two 4-way blends of these half-width vectors.
9833 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9834 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9835 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9836 for (int i = 0; i < SplitNumElements; ++i) {
9837 int M = HalfMask[i];
9838 if (M >= NumElements) {
9839 if (M >= NumElements + SplitNumElements)
9843 V2BlendMask.push_back(M - NumElements);
9844 V1BlendMask.push_back(-1);
9845 BlendMask.push_back(SplitNumElements + i);
9846 } else if (M >= 0) {
9847 if (M >= SplitNumElements)
9851 V2BlendMask.push_back(-1);
9852 V1BlendMask.push_back(M);
9853 BlendMask.push_back(i);
9855 V2BlendMask.push_back(-1);
9856 V1BlendMask.push_back(-1);
9857 BlendMask.push_back(-1);
9861 // Because the lowering happens after all combining takes place, we need to
9862 // manually combine these blend masks as much as possible so that we create
9863 // a minimal number of high-level vector shuffle nodes.
9865 // First try just blending the halves of V1 or V2.
9866 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9867 return DAG.getUNDEF(SplitVT);
9868 if (!UseLoV2 && !UseHiV2)
9869 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9870 if (!UseLoV1 && !UseHiV1)
9871 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9873 SDValue V1Blend, V2Blend;
9874 if (UseLoV1 && UseHiV1) {
9876 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9878 // We only use half of V1 so map the usage down into the final blend mask.
9879 V1Blend = UseLoV1 ? LoV1 : HiV1;
9880 for (int i = 0; i < SplitNumElements; ++i)
9881 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9882 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9884 if (UseLoV2 && UseHiV2) {
9886 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9888 // We only use half of V2 so map the usage down into the final blend mask.
9889 V2Blend = UseLoV2 ? LoV2 : HiV2;
9890 for (int i = 0; i < SplitNumElements; ++i)
9891 if (BlendMask[i] >= SplitNumElements)
9892 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9894 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9896 SDValue Lo = HalfBlend(LoMask);
9897 SDValue Hi = HalfBlend(HiMask);
9898 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9901 /// \brief Either split a vector in halves or decompose the shuffles and the
9904 /// This is provided as a good fallback for many lowerings of non-single-input
9905 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9906 /// between splitting the shuffle into 128-bit components and stitching those
9907 /// back together vs. extracting the single-input shuffles and blending those
9909 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9910 SDValue V2, ArrayRef<int> Mask,
9911 SelectionDAG &DAG) {
9912 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9913 "lower single-input shuffles as it "
9914 "could then recurse on itself.");
9915 int Size = Mask.size();
9917 // If this can be modeled as a broadcast of two elements followed by a blend,
9918 // prefer that lowering. This is especially important because broadcasts can
9919 // often fold with memory operands.
9920 auto DoBothBroadcast = [&] {
9921 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9924 if (V2BroadcastIdx == -1)
9925 V2BroadcastIdx = M - Size;
9926 else if (M - Size != V2BroadcastIdx)
9928 } else if (M >= 0) {
9929 if (V1BroadcastIdx == -1)
9931 else if (M != V1BroadcastIdx)
9936 if (DoBothBroadcast())
9937 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9940 // If the inputs all stem from a single 128-bit lane of each input, then we
9941 // split them rather than blending because the split will decompose to
9942 // unusually few instructions.
9943 int LaneCount = VT.getSizeInBits() / 128;
9944 int LaneSize = Size / LaneCount;
9945 SmallBitVector LaneInputs[2];
9946 LaneInputs[0].resize(LaneCount, false);
9947 LaneInputs[1].resize(LaneCount, false);
9948 for (int i = 0; i < Size; ++i)
9950 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9951 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9952 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9954 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9955 // that the decomposed single-input shuffles don't end up here.
9956 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9959 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9960 /// a permutation and blend of those lanes.
9962 /// This essentially blends the out-of-lane inputs to each lane into the lane
9963 /// from a permuted copy of the vector. This lowering strategy results in four
9964 /// instructions in the worst case for a single-input cross lane shuffle which
9965 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9966 /// of. Special cases for each particular shuffle pattern should be handled
9967 /// prior to trying this lowering.
9968 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9969 SDValue V1, SDValue V2,
9971 SelectionDAG &DAG) {
9972 // FIXME: This should probably be generalized for 512-bit vectors as well.
9973 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9974 int LaneSize = Mask.size() / 2;
9976 // If there are only inputs from one 128-bit lane, splitting will in fact be
9977 // less expensive. The flags track wether the given lane contains an element
9978 // that crosses to another lane.
9979 bool LaneCrossing[2] = {false, false};
9980 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9981 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9982 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9983 if (!LaneCrossing[0] || !LaneCrossing[1])
9984 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9986 if (isSingleInputShuffleMask(Mask)) {
9987 SmallVector<int, 32> FlippedBlendMask;
9988 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9989 FlippedBlendMask.push_back(
9990 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9992 : Mask[i] % LaneSize +
9993 (i / LaneSize) * LaneSize + Size));
9995 // Flip the vector, and blend the results which should now be in-lane. The
9996 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9997 // 5 for the high source. The value 3 selects the high half of source 2 and
9998 // the value 2 selects the low half of source 2. We only use source 2 to
9999 // allow folding it into a memory operand.
10000 unsigned PERMMask = 3 | 2 << 4;
10001 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10002 V1, DAG.getConstant(PERMMask, MVT::i8));
10003 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10006 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10007 // will be handled by the above logic and a blend of the results, much like
10008 // other patterns in AVX.
10009 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10012 /// \brief Handle lowering 2-lane 128-bit shuffles.
10013 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10014 SDValue V2, ArrayRef<int> Mask,
10015 const X86Subtarget *Subtarget,
10016 SelectionDAG &DAG) {
10017 // Blends are faster and handle all the non-lane-crossing cases.
10018 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10022 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10023 VT.getVectorNumElements() / 2);
10024 // Check for patterns which can be matched with a single insert of a 128-bit
10026 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10027 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10028 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10029 DAG.getIntPtrConstant(0));
10030 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10031 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10032 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10034 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10035 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10036 DAG.getIntPtrConstant(0));
10037 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10038 DAG.getIntPtrConstant(2));
10039 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10042 // Otherwise form a 128-bit permutation.
10043 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10044 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10045 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10046 DAG.getConstant(PermMask, MVT::i8));
10049 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10050 /// shuffling each lane.
10052 /// This will only succeed when the result of fixing the 128-bit lanes results
10053 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10054 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10055 /// the lane crosses early and then use simpler shuffles within each lane.
10057 /// FIXME: It might be worthwhile at some point to support this without
10058 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10059 /// in x86 only floating point has interesting non-repeating shuffles, and even
10060 /// those are still *marginally* more expensive.
10061 static SDValue lowerVectorShuffleByMerging128BitLanes(
10062 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10063 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10064 assert(!isSingleInputShuffleMask(Mask) &&
10065 "This is only useful with multiple inputs.");
10067 int Size = Mask.size();
10068 int LaneSize = 128 / VT.getScalarSizeInBits();
10069 int NumLanes = Size / LaneSize;
10070 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10072 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10073 // check whether the in-128-bit lane shuffles share a repeating pattern.
10074 SmallVector<int, 4> Lanes;
10075 Lanes.resize(NumLanes, -1);
10076 SmallVector<int, 4> InLaneMask;
10077 InLaneMask.resize(LaneSize, -1);
10078 for (int i = 0; i < Size; ++i) {
10082 int j = i / LaneSize;
10084 if (Lanes[j] < 0) {
10085 // First entry we've seen for this lane.
10086 Lanes[j] = Mask[i] / LaneSize;
10087 } else if (Lanes[j] != Mask[i] / LaneSize) {
10088 // This doesn't match the lane selected previously!
10092 // Check that within each lane we have a consistent shuffle mask.
10093 int k = i % LaneSize;
10094 if (InLaneMask[k] < 0) {
10095 InLaneMask[k] = Mask[i] % LaneSize;
10096 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10097 // This doesn't fit a repeating in-lane mask.
10102 // First shuffle the lanes into place.
10103 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10104 VT.getSizeInBits() / 64);
10105 SmallVector<int, 8> LaneMask;
10106 LaneMask.resize(NumLanes * 2, -1);
10107 for (int i = 0; i < NumLanes; ++i)
10108 if (Lanes[i] >= 0) {
10109 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10110 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10113 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10114 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10115 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10117 // Cast it back to the type we actually want.
10118 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10120 // Now do a simple shuffle that isn't lane crossing.
10121 SmallVector<int, 8> NewMask;
10122 NewMask.resize(Size, -1);
10123 for (int i = 0; i < Size; ++i)
10125 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10126 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10127 "Must not introduce lane crosses at this point!");
10129 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10132 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10135 /// This returns true if the elements from a particular input are already in the
10136 /// slot required by the given mask and require no permutation.
10137 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10138 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10139 int Size = Mask.size();
10140 for (int i = 0; i < Size; ++i)
10141 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10147 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10149 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10150 /// isn't available.
10151 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10152 const X86Subtarget *Subtarget,
10153 SelectionDAG &DAG) {
10155 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10156 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10157 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10158 ArrayRef<int> Mask = SVOp->getMask();
10159 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10161 SmallVector<int, 4> WidenedMask;
10162 if (canWidenShuffleElements(Mask, WidenedMask))
10163 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10166 if (isSingleInputShuffleMask(Mask)) {
10167 // Check for being able to broadcast a single element.
10168 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10169 Mask, Subtarget, DAG))
10172 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10173 // Non-half-crossing single input shuffles can be lowerid with an
10174 // interleaved permutation.
10175 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10176 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10177 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10178 DAG.getConstant(VPERMILPMask, MVT::i8));
10181 // With AVX2 we have direct support for this permutation.
10182 if (Subtarget->hasAVX2())
10183 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10184 getV4X86ShuffleImm8ForMask(Mask, DAG));
10186 // Otherwise, fall back.
10187 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10191 // X86 has dedicated unpack instructions that can handle specific blend
10192 // operations: UNPCKH and UNPCKL.
10193 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10194 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10195 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10196 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10198 // If we have a single input to the zero element, insert that into V1 if we
10199 // can do so cheaply.
10200 int NumV2Elements =
10201 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10202 if (NumV2Elements == 1 && Mask[0] >= 4)
10203 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10204 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10207 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10211 // Check if the blend happens to exactly fit that of SHUFPD.
10212 if ((Mask[0] == -1 || Mask[0] < 2) &&
10213 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10214 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10215 (Mask[3] == -1 || Mask[3] >= 6)) {
10216 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10217 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10218 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10219 DAG.getConstant(SHUFPDMask, MVT::i8));
10221 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10222 (Mask[1] == -1 || Mask[1] < 2) &&
10223 (Mask[2] == -1 || Mask[2] >= 6) &&
10224 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10225 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10226 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10227 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10228 DAG.getConstant(SHUFPDMask, MVT::i8));
10231 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10232 // shuffle. However, if we have AVX2 and either inputs are already in place,
10233 // we will be able to shuffle even across lanes the other input in a single
10234 // instruction so skip this pattern.
10235 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10236 isShuffleMaskInputInPlace(1, Mask))))
10237 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10238 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10241 // If we have AVX2 then we always want to lower with a blend because an v4 we
10242 // can fully permute the elements.
10243 if (Subtarget->hasAVX2())
10244 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10247 // Otherwise fall back on generic lowering.
10248 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10251 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10253 /// This routine is only called when we have AVX2 and thus a reasonable
10254 /// instruction set for v4i64 shuffling..
10255 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10256 const X86Subtarget *Subtarget,
10257 SelectionDAG &DAG) {
10259 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10260 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10262 ArrayRef<int> Mask = SVOp->getMask();
10263 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10264 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10266 SmallVector<int, 4> WidenedMask;
10267 if (canWidenShuffleElements(Mask, WidenedMask))
10268 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10271 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10275 // Check for being able to broadcast a single element.
10276 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10277 Mask, Subtarget, DAG))
10280 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10281 // use lower latency instructions that will operate on both 128-bit lanes.
10282 SmallVector<int, 2> RepeatedMask;
10283 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10284 if (isSingleInputShuffleMask(Mask)) {
10285 int PSHUFDMask[] = {-1, -1, -1, -1};
10286 for (int i = 0; i < 2; ++i)
10287 if (RepeatedMask[i] >= 0) {
10288 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10289 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10291 return DAG.getNode(
10292 ISD::BITCAST, DL, MVT::v4i64,
10293 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10294 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10295 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10298 // Use dedicated unpack instructions for masks that match their pattern.
10299 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10300 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10301 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10302 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10305 // AVX2 provides a direct instruction for permuting a single input across
10307 if (isSingleInputShuffleMask(Mask))
10308 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10309 getV4X86ShuffleImm8ForMask(Mask, DAG));
10311 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10312 // shuffle. However, if we have AVX2 and either inputs are already in place,
10313 // we will be able to shuffle even across lanes the other input in a single
10314 // instruction so skip this pattern.
10315 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10316 isShuffleMaskInputInPlace(1, Mask))))
10317 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10318 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10321 // Otherwise fall back on generic blend lowering.
10322 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10326 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10328 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10329 /// isn't available.
10330 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10331 const X86Subtarget *Subtarget,
10332 SelectionDAG &DAG) {
10334 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10335 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10337 ArrayRef<int> Mask = SVOp->getMask();
10338 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10340 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10344 // Check for being able to broadcast a single element.
10345 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10346 Mask, Subtarget, DAG))
10349 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10350 // options to efficiently lower the shuffle.
10351 SmallVector<int, 4> RepeatedMask;
10352 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10353 assert(RepeatedMask.size() == 4 &&
10354 "Repeated masks must be half the mask width!");
10355 if (isSingleInputShuffleMask(Mask))
10356 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10357 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10359 // Use dedicated unpack instructions for masks that match their pattern.
10360 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10361 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10362 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10363 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10365 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10366 // have already handled any direct blends. We also need to squash the
10367 // repeated mask into a simulated v4f32 mask.
10368 for (int i = 0; i < 4; ++i)
10369 if (RepeatedMask[i] >= 8)
10370 RepeatedMask[i] -= 4;
10371 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10374 // If we have a single input shuffle with different shuffle patterns in the
10375 // two 128-bit lanes use the variable mask to VPERMILPS.
10376 if (isSingleInputShuffleMask(Mask)) {
10377 SDValue VPermMask[8];
10378 for (int i = 0; i < 8; ++i)
10379 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10380 : DAG.getConstant(Mask[i], MVT::i32);
10381 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10382 return DAG.getNode(
10383 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10384 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10386 if (Subtarget->hasAVX2())
10387 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10388 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10389 DAG.getNode(ISD::BUILD_VECTOR, DL,
10390 MVT::v8i32, VPermMask)),
10393 // Otherwise, fall back.
10394 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10398 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10400 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10401 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10404 // If we have AVX2 then we always want to lower with a blend because at v8 we
10405 // can fully permute the elements.
10406 if (Subtarget->hasAVX2())
10407 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10410 // Otherwise fall back on generic lowering.
10411 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10414 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10416 /// This routine is only called when we have AVX2 and thus a reasonable
10417 /// instruction set for v8i32 shuffling..
10418 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10419 const X86Subtarget *Subtarget,
10420 SelectionDAG &DAG) {
10422 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10423 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10424 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10425 ArrayRef<int> Mask = SVOp->getMask();
10426 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10427 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10429 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10433 // Check for being able to broadcast a single element.
10434 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10435 Mask, Subtarget, DAG))
10438 // If the shuffle mask is repeated in each 128-bit lane we can use more
10439 // efficient instructions that mirror the shuffles across the two 128-bit
10441 SmallVector<int, 4> RepeatedMask;
10442 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10443 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10444 if (isSingleInputShuffleMask(Mask))
10445 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10446 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10448 // Use dedicated unpack instructions for masks that match their pattern.
10449 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10450 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10451 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10452 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10455 // If the shuffle patterns aren't repeated but it is a single input, directly
10456 // generate a cross-lane VPERMD instruction.
10457 if (isSingleInputShuffleMask(Mask)) {
10458 SDValue VPermMask[8];
10459 for (int i = 0; i < 8; ++i)
10460 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10461 : DAG.getConstant(Mask[i], MVT::i32);
10462 return DAG.getNode(
10463 X86ISD::VPERMV, DL, MVT::v8i32,
10464 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10467 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10469 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10470 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10473 // Otherwise fall back on generic blend lowering.
10474 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10478 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10480 /// This routine is only called when we have AVX2 and thus a reasonable
10481 /// instruction set for v16i16 shuffling..
10482 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10483 const X86Subtarget *Subtarget,
10484 SelectionDAG &DAG) {
10486 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10487 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10488 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10489 ArrayRef<int> Mask = SVOp->getMask();
10490 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10491 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10493 // Check for being able to broadcast a single element.
10494 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10495 Mask, Subtarget, DAG))
10498 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10502 // Use dedicated unpack instructions for masks that match their pattern.
10503 if (isShuffleEquivalent(Mask,
10504 // First 128-bit lane:
10505 0, 16, 1, 17, 2, 18, 3, 19,
10506 // Second 128-bit lane:
10507 8, 24, 9, 25, 10, 26, 11, 27))
10508 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10509 if (isShuffleEquivalent(Mask,
10510 // First 128-bit lane:
10511 4, 20, 5, 21, 6, 22, 7, 23,
10512 // Second 128-bit lane:
10513 12, 28, 13, 29, 14, 30, 15, 31))
10514 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10516 if (isSingleInputShuffleMask(Mask)) {
10517 // There are no generalized cross-lane shuffle operations available on i16
10519 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10520 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10523 SDValue PSHUFBMask[32];
10524 for (int i = 0; i < 16; ++i) {
10525 if (Mask[i] == -1) {
10526 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10530 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10531 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10532 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10533 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10535 return DAG.getNode(
10536 ISD::BITCAST, DL, MVT::v16i16,
10538 X86ISD::PSHUFB, DL, MVT::v32i8,
10539 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10540 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10543 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10545 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10546 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10549 // Otherwise fall back on generic lowering.
10550 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10553 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10555 /// This routine is only called when we have AVX2 and thus a reasonable
10556 /// instruction set for v32i8 shuffling..
10557 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10558 const X86Subtarget *Subtarget,
10559 SelectionDAG &DAG) {
10561 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10562 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10564 ArrayRef<int> Mask = SVOp->getMask();
10565 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10566 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10568 // Check for being able to broadcast a single element.
10569 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10570 Mask, Subtarget, DAG))
10573 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10577 // Use dedicated unpack instructions for masks that match their pattern.
10578 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10580 if (isShuffleEquivalent(
10582 // First 128-bit lane:
10583 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10584 // Second 128-bit lane:
10585 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10586 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10587 if (isShuffleEquivalent(
10589 // First 128-bit lane:
10590 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10591 // Second 128-bit lane:
10592 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10593 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10595 if (isSingleInputShuffleMask(Mask)) {
10596 // There are no generalized cross-lane shuffle operations available on i8
10598 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10599 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10602 SDValue PSHUFBMask[32];
10603 for (int i = 0; i < 32; ++i)
10606 ? DAG.getUNDEF(MVT::i8)
10607 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10609 return DAG.getNode(
10610 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10611 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10614 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10616 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10617 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10620 // Otherwise fall back on generic lowering.
10621 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10624 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10626 /// This routine either breaks down the specific type of a 256-bit x86 vector
10627 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10628 /// together based on the available instructions.
10629 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10630 MVT VT, const X86Subtarget *Subtarget,
10631 SelectionDAG &DAG) {
10633 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10634 ArrayRef<int> Mask = SVOp->getMask();
10636 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10637 // check for those subtargets here and avoid much of the subtarget querying in
10638 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10639 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10640 // floating point types there eventually, just immediately cast everything to
10641 // a float and operate entirely in that domain.
10642 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10643 int ElementBits = VT.getScalarSizeInBits();
10644 if (ElementBits < 32)
10645 // No floating point type available, decompose into 128-bit vectors.
10646 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10648 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10649 VT.getVectorNumElements());
10650 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10651 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10652 return DAG.getNode(ISD::BITCAST, DL, VT,
10653 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10656 switch (VT.SimpleTy) {
10658 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10660 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10662 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10664 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10666 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10668 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10671 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10675 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10676 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10677 const X86Subtarget *Subtarget,
10678 SelectionDAG &DAG) {
10680 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10681 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10683 ArrayRef<int> Mask = SVOp->getMask();
10684 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10686 // FIXME: Implement direct support for this type!
10687 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10690 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10691 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10692 const X86Subtarget *Subtarget,
10693 SelectionDAG &DAG) {
10695 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10696 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10698 ArrayRef<int> Mask = SVOp->getMask();
10699 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10701 // FIXME: Implement direct support for this type!
10702 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10705 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10706 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10707 const X86Subtarget *Subtarget,
10708 SelectionDAG &DAG) {
10710 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10711 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10713 ArrayRef<int> Mask = SVOp->getMask();
10714 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10716 // FIXME: Implement direct support for this type!
10717 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10720 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10721 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10722 const X86Subtarget *Subtarget,
10723 SelectionDAG &DAG) {
10725 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10726 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10727 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10728 ArrayRef<int> Mask = SVOp->getMask();
10729 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10731 // FIXME: Implement direct support for this type!
10732 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10735 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10736 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10737 const X86Subtarget *Subtarget,
10738 SelectionDAG &DAG) {
10740 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10741 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10742 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10743 ArrayRef<int> Mask = SVOp->getMask();
10744 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10745 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10747 // FIXME: Implement direct support for this type!
10748 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10751 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10752 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10753 const X86Subtarget *Subtarget,
10754 SelectionDAG &DAG) {
10756 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10757 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10758 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10759 ArrayRef<int> Mask = SVOp->getMask();
10760 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10761 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10763 // FIXME: Implement direct support for this type!
10764 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10767 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10769 /// This routine either breaks down the specific type of a 512-bit x86 vector
10770 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10771 /// together based on the available instructions.
10772 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10773 MVT VT, const X86Subtarget *Subtarget,
10774 SelectionDAG &DAG) {
10776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10777 ArrayRef<int> Mask = SVOp->getMask();
10778 assert(Subtarget->hasAVX512() &&
10779 "Cannot lower 512-bit vectors w/ basic ISA!");
10781 // Check for being able to broadcast a single element.
10782 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10783 Mask, Subtarget, DAG))
10786 // Dispatch to each element type for lowering. If we don't have supprot for
10787 // specific element type shuffles at 512 bits, immediately split them and
10788 // lower them. Each lowering routine of a given type is allowed to assume that
10789 // the requisite ISA extensions for that element type are available.
10790 switch (VT.SimpleTy) {
10792 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10794 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10796 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10798 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10800 if (Subtarget->hasBWI())
10801 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10804 if (Subtarget->hasBWI())
10805 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10809 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10812 // Otherwise fall back on splitting.
10813 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10816 /// \brief Top-level lowering for x86 vector shuffles.
10818 /// This handles decomposition, canonicalization, and lowering of all x86
10819 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10820 /// above in helper routines. The canonicalization attempts to widen shuffles
10821 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10822 /// s.t. only one of the two inputs needs to be tested, etc.
10823 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10824 SelectionDAG &DAG) {
10825 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10826 ArrayRef<int> Mask = SVOp->getMask();
10827 SDValue V1 = Op.getOperand(0);
10828 SDValue V2 = Op.getOperand(1);
10829 MVT VT = Op.getSimpleValueType();
10830 int NumElements = VT.getVectorNumElements();
10833 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10835 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10836 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10837 if (V1IsUndef && V2IsUndef)
10838 return DAG.getUNDEF(VT);
10840 // When we create a shuffle node we put the UNDEF node to second operand,
10841 // but in some cases the first operand may be transformed to UNDEF.
10842 // In this case we should just commute the node.
10844 return DAG.getCommutedVectorShuffle(*SVOp);
10846 // Check for non-undef masks pointing at an undef vector and make the masks
10847 // undef as well. This makes it easier to match the shuffle based solely on
10851 if (M >= NumElements) {
10852 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10853 for (int &M : NewMask)
10854 if (M >= NumElements)
10856 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10859 // Try to collapse shuffles into using a vector type with fewer elements but
10860 // wider element types. We cap this to not form integers or floating point
10861 // elements wider than 64 bits, but it might be interesting to form i128
10862 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10863 SmallVector<int, 16> WidenedMask;
10864 if (VT.getScalarSizeInBits() < 64 &&
10865 canWidenShuffleElements(Mask, WidenedMask)) {
10866 MVT NewEltVT = VT.isFloatingPoint()
10867 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10868 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10869 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10870 // Make sure that the new vector type is legal. For example, v2f64 isn't
10872 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10873 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10874 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10875 return DAG.getNode(ISD::BITCAST, dl, VT,
10876 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10880 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10881 for (int M : SVOp->getMask())
10883 ++NumUndefElements;
10884 else if (M < NumElements)
10889 // Commute the shuffle as needed such that more elements come from V1 than
10890 // V2. This allows us to match the shuffle pattern strictly on how many
10891 // elements come from V1 without handling the symmetric cases.
10892 if (NumV2Elements > NumV1Elements)
10893 return DAG.getCommutedVectorShuffle(*SVOp);
10895 // When the number of V1 and V2 elements are the same, try to minimize the
10896 // number of uses of V2 in the low half of the vector. When that is tied,
10897 // ensure that the sum of indices for V1 is equal to or lower than the sum
10898 // indices for V2. When those are equal, try to ensure that the number of odd
10899 // indices for V1 is lower than the number of odd indices for V2.
10900 if (NumV1Elements == NumV2Elements) {
10901 int LowV1Elements = 0, LowV2Elements = 0;
10902 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10903 if (M >= NumElements)
10907 if (LowV2Elements > LowV1Elements) {
10908 return DAG.getCommutedVectorShuffle(*SVOp);
10909 } else if (LowV2Elements == LowV1Elements) {
10910 int SumV1Indices = 0, SumV2Indices = 0;
10911 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10912 if (SVOp->getMask()[i] >= NumElements)
10914 else if (SVOp->getMask()[i] >= 0)
10916 if (SumV2Indices < SumV1Indices) {
10917 return DAG.getCommutedVectorShuffle(*SVOp);
10918 } else if (SumV2Indices == SumV1Indices) {
10919 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10920 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10921 if (SVOp->getMask()[i] >= NumElements)
10922 NumV2OddIndices += i % 2;
10923 else if (SVOp->getMask()[i] >= 0)
10924 NumV1OddIndices += i % 2;
10925 if (NumV2OddIndices < NumV1OddIndices)
10926 return DAG.getCommutedVectorShuffle(*SVOp);
10931 // For each vector width, delegate to a specialized lowering routine.
10932 if (VT.getSizeInBits() == 128)
10933 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10935 if (VT.getSizeInBits() == 256)
10936 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10938 // Force AVX-512 vectors to be scalarized for now.
10939 // FIXME: Implement AVX-512 support!
10940 if (VT.getSizeInBits() == 512)
10941 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10943 llvm_unreachable("Unimplemented!");
10947 //===----------------------------------------------------------------------===//
10948 // Legacy vector shuffle lowering
10950 // This code is the legacy code handling vector shuffles until the above
10951 // replaces its functionality and performance.
10952 //===----------------------------------------------------------------------===//
10954 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10955 bool hasInt256, unsigned *MaskOut = nullptr) {
10956 MVT EltVT = VT.getVectorElementType();
10958 // There is no blend with immediate in AVX-512.
10959 if (VT.is512BitVector())
10962 if (!hasSSE41 || EltVT == MVT::i8)
10964 if (!hasInt256 && VT == MVT::v16i16)
10967 unsigned MaskValue = 0;
10968 unsigned NumElems = VT.getVectorNumElements();
10969 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10970 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10971 unsigned NumElemsInLane = NumElems / NumLanes;
10973 // Blend for v16i16 should be symetric for the both lanes.
10974 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10976 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10977 int EltIdx = MaskVals[i];
10979 if ((EltIdx < 0 || EltIdx == (int)i) &&
10980 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10983 if (((unsigned)EltIdx == (i + NumElems)) &&
10984 (SndLaneEltIdx < 0 ||
10985 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10986 MaskValue |= (1 << i);
10992 *MaskOut = MaskValue;
10996 // Try to lower a shuffle node into a simple blend instruction.
10997 // This function assumes isBlendMask returns true for this
10998 // SuffleVectorSDNode
10999 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
11000 unsigned MaskValue,
11001 const X86Subtarget *Subtarget,
11002 SelectionDAG &DAG) {
11003 MVT VT = SVOp->getSimpleValueType(0);
11004 MVT EltVT = VT.getVectorElementType();
11005 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11006 Subtarget->hasInt256() && "Trying to lower a "
11007 "VECTOR_SHUFFLE to a Blend but "
11008 "with the wrong mask"));
11009 SDValue V1 = SVOp->getOperand(0);
11010 SDValue V2 = SVOp->getOperand(1);
11012 unsigned NumElems = VT.getVectorNumElements();
11014 // Convert i32 vectors to floating point if it is not AVX2.
11015 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11017 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11018 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11020 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11021 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11024 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11025 DAG.getConstant(MaskValue, MVT::i32));
11026 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11029 /// In vector type \p VT, return true if the element at index \p InputIdx
11030 /// falls on a different 128-bit lane than \p OutputIdx.
11031 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11032 unsigned OutputIdx) {
11033 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11034 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11037 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11038 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11039 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11040 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11042 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11043 SelectionDAG &DAG) {
11044 MVT VT = V1.getSimpleValueType();
11045 assert(VT.is128BitVector() || VT.is256BitVector());
11047 MVT EltVT = VT.getVectorElementType();
11048 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11049 unsigned NumElts = VT.getVectorNumElements();
11051 SmallVector<SDValue, 32> PshufbMask;
11052 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11053 int InputIdx = MaskVals[OutputIdx];
11054 unsigned InputByteIdx;
11056 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11057 InputByteIdx = 0x80;
11059 // Cross lane is not allowed.
11060 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11062 InputByteIdx = InputIdx * EltSizeInBytes;
11063 // Index is an byte offset within the 128-bit lane.
11064 InputByteIdx &= 0xf;
11067 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11068 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11069 if (InputByteIdx != 0x80)
11074 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11076 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11077 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11078 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11081 // v8i16 shuffles - Prefer shuffles in the following order:
11082 // 1. [all] pshuflw, pshufhw, optional move
11083 // 2. [ssse3] 1 x pshufb
11084 // 3. [ssse3] 2 x pshufb + 1 x por
11085 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11087 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11088 SelectionDAG &DAG) {
11089 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11090 SDValue V1 = SVOp->getOperand(0);
11091 SDValue V2 = SVOp->getOperand(1);
11093 SmallVector<int, 8> MaskVals;
11095 // Determine if more than 1 of the words in each of the low and high quadwords
11096 // of the result come from the same quadword of one of the two inputs. Undef
11097 // mask values count as coming from any quadword, for better codegen.
11099 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11100 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11101 unsigned LoQuad[] = { 0, 0, 0, 0 };
11102 unsigned HiQuad[] = { 0, 0, 0, 0 };
11103 // Indices of quads used.
11104 std::bitset<4> InputQuads;
11105 for (unsigned i = 0; i < 8; ++i) {
11106 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11107 int EltIdx = SVOp->getMaskElt(i);
11108 MaskVals.push_back(EltIdx);
11116 ++Quad[EltIdx / 4];
11117 InputQuads.set(EltIdx / 4);
11120 int BestLoQuad = -1;
11121 unsigned MaxQuad = 1;
11122 for (unsigned i = 0; i < 4; ++i) {
11123 if (LoQuad[i] > MaxQuad) {
11125 MaxQuad = LoQuad[i];
11129 int BestHiQuad = -1;
11131 for (unsigned i = 0; i < 4; ++i) {
11132 if (HiQuad[i] > MaxQuad) {
11134 MaxQuad = HiQuad[i];
11138 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11139 // of the two input vectors, shuffle them into one input vector so only a
11140 // single pshufb instruction is necessary. If there are more than 2 input
11141 // quads, disable the next transformation since it does not help SSSE3.
11142 bool V1Used = InputQuads[0] || InputQuads[1];
11143 bool V2Used = InputQuads[2] || InputQuads[3];
11144 if (Subtarget->hasSSSE3()) {
11145 if (InputQuads.count() == 2 && V1Used && V2Used) {
11146 BestLoQuad = InputQuads[0] ? 0 : 1;
11147 BestHiQuad = InputQuads[2] ? 2 : 3;
11149 if (InputQuads.count() > 2) {
11155 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11156 // the shuffle mask. If a quad is scored as -1, that means that it contains
11157 // words from all 4 input quadwords.
11159 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11161 BestLoQuad < 0 ? 0 : BestLoQuad,
11162 BestHiQuad < 0 ? 1 : BestHiQuad
11164 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11165 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11166 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11167 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11169 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11170 // source words for the shuffle, to aid later transformations.
11171 bool AllWordsInNewV = true;
11172 bool InOrder[2] = { true, true };
11173 for (unsigned i = 0; i != 8; ++i) {
11174 int idx = MaskVals[i];
11176 InOrder[i/4] = false;
11177 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11179 AllWordsInNewV = false;
11183 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11184 if (AllWordsInNewV) {
11185 for (int i = 0; i != 8; ++i) {
11186 int idx = MaskVals[i];
11189 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11190 if ((idx != i) && idx < 4)
11192 if ((idx != i) && idx > 3)
11201 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11202 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11203 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11204 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11205 unsigned TargetMask = 0;
11206 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11207 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11209 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11210 getShufflePSHUFLWImmediate(SVOp);
11211 V1 = NewV.getOperand(0);
11212 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11216 // Promote splats to a larger type which usually leads to more efficient code.
11217 // FIXME: Is this true if pshufb is available?
11218 if (SVOp->isSplat())
11219 return PromoteSplat(SVOp, DAG);
11221 // If we have SSSE3, and all words of the result are from 1 input vector,
11222 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11223 // is present, fall back to case 4.
11224 if (Subtarget->hasSSSE3()) {
11225 SmallVector<SDValue,16> pshufbMask;
11227 // If we have elements from both input vectors, set the high bit of the
11228 // shuffle mask element to zero out elements that come from V2 in the V1
11229 // mask, and elements that come from V1 in the V2 mask, so that the two
11230 // results can be OR'd together.
11231 bool TwoInputs = V1Used && V2Used;
11232 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11234 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11236 // Calculate the shuffle mask for the second input, shuffle it, and
11237 // OR it with the first shuffled input.
11238 CommuteVectorShuffleMask(MaskVals, 8);
11239 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11240 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11241 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11244 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11245 // and update MaskVals with new element order.
11246 std::bitset<8> InOrder;
11247 if (BestLoQuad >= 0) {
11248 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11249 for (int i = 0; i != 4; ++i) {
11250 int idx = MaskVals[i];
11253 } else if ((idx / 4) == BestLoQuad) {
11254 MaskV[i] = idx & 3;
11258 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11261 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11263 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11264 NewV.getOperand(0),
11265 getShufflePSHUFLWImmediate(SVOp), DAG);
11269 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11270 // and update MaskVals with the new element order.
11271 if (BestHiQuad >= 0) {
11272 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11273 for (unsigned i = 4; i != 8; ++i) {
11274 int idx = MaskVals[i];
11277 } else if ((idx / 4) == BestHiQuad) {
11278 MaskV[i] = (idx & 3) + 4;
11282 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11285 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11286 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11287 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11288 NewV.getOperand(0),
11289 getShufflePSHUFHWImmediate(SVOp), DAG);
11293 // In case BestHi & BestLo were both -1, which means each quadword has a word
11294 // from each of the four input quadwords, calculate the InOrder bitvector now
11295 // before falling through to the insert/extract cleanup.
11296 if (BestLoQuad == -1 && BestHiQuad == -1) {
11298 for (int i = 0; i != 8; ++i)
11299 if (MaskVals[i] < 0 || MaskVals[i] == i)
11303 // The other elements are put in the right place using pextrw and pinsrw.
11304 for (unsigned i = 0; i != 8; ++i) {
11307 int EltIdx = MaskVals[i];
11310 SDValue ExtOp = (EltIdx < 8) ?
11311 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11312 DAG.getIntPtrConstant(EltIdx)) :
11313 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11314 DAG.getIntPtrConstant(EltIdx - 8));
11315 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11316 DAG.getIntPtrConstant(i));
11321 /// \brief v16i16 shuffles
11323 /// FIXME: We only support generation of a single pshufb currently. We can
11324 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11325 /// well (e.g 2 x pshufb + 1 x por).
11327 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11329 SDValue V1 = SVOp->getOperand(0);
11330 SDValue V2 = SVOp->getOperand(1);
11333 if (V2.getOpcode() != ISD::UNDEF)
11336 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11337 return getPSHUFB(MaskVals, V1, dl, DAG);
11340 // v16i8 shuffles - Prefer shuffles in the following order:
11341 // 1. [ssse3] 1 x pshufb
11342 // 2. [ssse3] 2 x pshufb + 1 x por
11343 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11344 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11345 const X86Subtarget* Subtarget,
11346 SelectionDAG &DAG) {
11347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11348 SDValue V1 = SVOp->getOperand(0);
11349 SDValue V2 = SVOp->getOperand(1);
11351 ArrayRef<int> MaskVals = SVOp->getMask();
11353 // Promote splats to a larger type which usually leads to more efficient code.
11354 // FIXME: Is this true if pshufb is available?
11355 if (SVOp->isSplat())
11356 return PromoteSplat(SVOp, DAG);
11358 // If we have SSSE3, case 1 is generated when all result bytes come from
11359 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11360 // present, fall back to case 3.
11362 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11363 if (Subtarget->hasSSSE3()) {
11364 SmallVector<SDValue,16> pshufbMask;
11366 // If all result elements are from one input vector, then only translate
11367 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11369 // Otherwise, we have elements from both input vectors, and must zero out
11370 // elements that come from V2 in the first mask, and V1 in the second mask
11371 // so that we can OR them together.
11372 for (unsigned i = 0; i != 16; ++i) {
11373 int EltIdx = MaskVals[i];
11374 if (EltIdx < 0 || EltIdx >= 16)
11376 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11378 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11379 DAG.getNode(ISD::BUILD_VECTOR, dl,
11380 MVT::v16i8, pshufbMask));
11382 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11383 // the 2nd operand if it's undefined or zero.
11384 if (V2.getOpcode() == ISD::UNDEF ||
11385 ISD::isBuildVectorAllZeros(V2.getNode()))
11388 // Calculate the shuffle mask for the second input, shuffle it, and
11389 // OR it with the first shuffled input.
11390 pshufbMask.clear();
11391 for (unsigned i = 0; i != 16; ++i) {
11392 int EltIdx = MaskVals[i];
11393 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11394 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11396 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11397 DAG.getNode(ISD::BUILD_VECTOR, dl,
11398 MVT::v16i8, pshufbMask));
11399 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11402 // No SSSE3 - Calculate in place words and then fix all out of place words
11403 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11404 // the 16 different words that comprise the two doublequadword input vectors.
11405 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11406 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11408 for (int i = 0; i != 8; ++i) {
11409 int Elt0 = MaskVals[i*2];
11410 int Elt1 = MaskVals[i*2+1];
11412 // This word of the result is all undef, skip it.
11413 if (Elt0 < 0 && Elt1 < 0)
11416 // This word of the result is already in the correct place, skip it.
11417 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11420 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11421 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11424 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11425 // using a single extract together, load it and store it.
11426 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11427 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11428 DAG.getIntPtrConstant(Elt1 / 2));
11429 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11430 DAG.getIntPtrConstant(i));
11434 // If Elt1 is defined, extract it from the appropriate source. If the
11435 // source byte is not also odd, shift the extracted word left 8 bits
11436 // otherwise clear the bottom 8 bits if we need to do an or.
11438 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11439 DAG.getIntPtrConstant(Elt1 / 2));
11440 if ((Elt1 & 1) == 0)
11441 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11443 TLI.getShiftAmountTy(InsElt.getValueType())));
11444 else if (Elt0 >= 0)
11445 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11446 DAG.getConstant(0xFF00, MVT::i16));
11448 // If Elt0 is defined, extract it from the appropriate source. If the
11449 // source byte is not also even, shift the extracted word right 8 bits. If
11450 // Elt1 was also defined, OR the extracted values together before
11451 // inserting them in the result.
11453 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11454 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11455 if ((Elt0 & 1) != 0)
11456 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11458 TLI.getShiftAmountTy(InsElt0.getValueType())));
11459 else if (Elt1 >= 0)
11460 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11461 DAG.getConstant(0x00FF, MVT::i16));
11462 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11465 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11466 DAG.getIntPtrConstant(i));
11468 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11471 // v32i8 shuffles - Translate to VPSHUFB if possible.
11473 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11474 const X86Subtarget *Subtarget,
11475 SelectionDAG &DAG) {
11476 MVT VT = SVOp->getSimpleValueType(0);
11477 SDValue V1 = SVOp->getOperand(0);
11478 SDValue V2 = SVOp->getOperand(1);
11480 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11482 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11483 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11484 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11486 // VPSHUFB may be generated if
11487 // (1) one of input vector is undefined or zeroinitializer.
11488 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11489 // And (2) the mask indexes don't cross the 128-bit lane.
11490 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11491 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11494 if (V1IsAllZero && !V2IsAllZero) {
11495 CommuteVectorShuffleMask(MaskVals, 32);
11498 return getPSHUFB(MaskVals, V1, dl, DAG);
11501 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11502 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11503 /// done when every pair / quad of shuffle mask elements point to elements in
11504 /// the right sequence. e.g.
11505 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11507 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11508 SelectionDAG &DAG) {
11509 MVT VT = SVOp->getSimpleValueType(0);
11511 unsigned NumElems = VT.getVectorNumElements();
11514 switch (VT.SimpleTy) {
11515 default: llvm_unreachable("Unexpected!");
11518 return SDValue(SVOp, 0);
11519 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11520 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11521 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11522 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11523 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11524 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11527 SmallVector<int, 8> MaskVec;
11528 for (unsigned i = 0; i != NumElems; i += Scale) {
11530 for (unsigned j = 0; j != Scale; ++j) {
11531 int EltIdx = SVOp->getMaskElt(i+j);
11535 StartIdx = (EltIdx / Scale);
11536 if (EltIdx != (int)(StartIdx*Scale + j))
11539 MaskVec.push_back(StartIdx);
11542 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11543 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11544 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11547 /// getVZextMovL - Return a zero-extending vector move low node.
11549 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11550 SDValue SrcOp, SelectionDAG &DAG,
11551 const X86Subtarget *Subtarget, SDLoc dl) {
11552 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11553 LoadSDNode *LD = nullptr;
11554 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11555 LD = dyn_cast<LoadSDNode>(SrcOp);
11557 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11559 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11560 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11561 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11562 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11563 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11565 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11566 return DAG.getNode(ISD::BITCAST, dl, VT,
11567 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11568 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11570 SrcOp.getOperand(0)
11576 return DAG.getNode(ISD::BITCAST, dl, VT,
11577 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11578 DAG.getNode(ISD::BITCAST, dl,
11582 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11583 /// which could not be matched by any known target speficic shuffle
11585 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11587 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11588 if (NewOp.getNode())
11591 MVT VT = SVOp->getSimpleValueType(0);
11593 unsigned NumElems = VT.getVectorNumElements();
11594 unsigned NumLaneElems = NumElems / 2;
11597 MVT EltVT = VT.getVectorElementType();
11598 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11601 SmallVector<int, 16> Mask;
11602 for (unsigned l = 0; l < 2; ++l) {
11603 // Build a shuffle mask for the output, discovering on the fly which
11604 // input vectors to use as shuffle operands (recorded in InputUsed).
11605 // If building a suitable shuffle vector proves too hard, then bail
11606 // out with UseBuildVector set.
11607 bool UseBuildVector = false;
11608 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11609 unsigned LaneStart = l * NumLaneElems;
11610 for (unsigned i = 0; i != NumLaneElems; ++i) {
11611 // The mask element. This indexes into the input.
11612 int Idx = SVOp->getMaskElt(i+LaneStart);
11614 // the mask element does not index into any input vector.
11615 Mask.push_back(-1);
11619 // The input vector this mask element indexes into.
11620 int Input = Idx / NumLaneElems;
11622 // Turn the index into an offset from the start of the input vector.
11623 Idx -= Input * NumLaneElems;
11625 // Find or create a shuffle vector operand to hold this input.
11627 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11628 if (InputUsed[OpNo] == Input)
11629 // This input vector is already an operand.
11631 if (InputUsed[OpNo] < 0) {
11632 // Create a new operand for this input vector.
11633 InputUsed[OpNo] = Input;
11638 if (OpNo >= array_lengthof(InputUsed)) {
11639 // More than two input vectors used! Give up on trying to create a
11640 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11641 UseBuildVector = true;
11645 // Add the mask index for the new shuffle vector.
11646 Mask.push_back(Idx + OpNo * NumLaneElems);
11649 if (UseBuildVector) {
11650 SmallVector<SDValue, 16> SVOps;
11651 for (unsigned i = 0; i != NumLaneElems; ++i) {
11652 // The mask element. This indexes into the input.
11653 int Idx = SVOp->getMaskElt(i+LaneStart);
11655 SVOps.push_back(DAG.getUNDEF(EltVT));
11659 // The input vector this mask element indexes into.
11660 int Input = Idx / NumElems;
11662 // Turn the index into an offset from the start of the input vector.
11663 Idx -= Input * NumElems;
11665 // Extract the vector element by hand.
11666 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11667 SVOp->getOperand(Input),
11668 DAG.getIntPtrConstant(Idx)));
11671 // Construct the output using a BUILD_VECTOR.
11672 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11673 } else if (InputUsed[0] < 0) {
11674 // No input vectors were used! The result is undefined.
11675 Output[l] = DAG.getUNDEF(NVT);
11677 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11678 (InputUsed[0] % 2) * NumLaneElems,
11680 // If only one input was used, use an undefined vector for the other.
11681 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11682 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11683 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11684 // At least one input vector was used. Create a new shuffle vector.
11685 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11691 // Concatenate the result back
11692 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11695 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11696 /// 4 elements, and match them with several different shuffle types.
11698 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11699 SDValue V1 = SVOp->getOperand(0);
11700 SDValue V2 = SVOp->getOperand(1);
11702 MVT VT = SVOp->getSimpleValueType(0);
11704 assert(VT.is128BitVector() && "Unsupported vector size");
11706 std::pair<int, int> Locs[4];
11707 int Mask1[] = { -1, -1, -1, -1 };
11708 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11710 unsigned NumHi = 0;
11711 unsigned NumLo = 0;
11712 for (unsigned i = 0; i != 4; ++i) {
11713 int Idx = PermMask[i];
11715 Locs[i] = std::make_pair(-1, -1);
11717 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11719 Locs[i] = std::make_pair(0, NumLo);
11720 Mask1[NumLo] = Idx;
11723 Locs[i] = std::make_pair(1, NumHi);
11725 Mask1[2+NumHi] = Idx;
11731 if (NumLo <= 2 && NumHi <= 2) {
11732 // If no more than two elements come from either vector. This can be
11733 // implemented with two shuffles. First shuffle gather the elements.
11734 // The second shuffle, which takes the first shuffle as both of its
11735 // vector operands, put the elements into the right order.
11736 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11738 int Mask2[] = { -1, -1, -1, -1 };
11740 for (unsigned i = 0; i != 4; ++i)
11741 if (Locs[i].first != -1) {
11742 unsigned Idx = (i < 2) ? 0 : 4;
11743 Idx += Locs[i].first * 2 + Locs[i].second;
11747 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11750 if (NumLo == 3 || NumHi == 3) {
11751 // Otherwise, we must have three elements from one vector, call it X, and
11752 // one element from the other, call it Y. First, use a shufps to build an
11753 // intermediate vector with the one element from Y and the element from X
11754 // that will be in the same half in the final destination (the indexes don't
11755 // matter). Then, use a shufps to build the final vector, taking the half
11756 // containing the element from Y from the intermediate, and the other half
11759 // Normalize it so the 3 elements come from V1.
11760 CommuteVectorShuffleMask(PermMask, 4);
11764 // Find the element from V2.
11766 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11767 int Val = PermMask[HiIndex];
11774 Mask1[0] = PermMask[HiIndex];
11776 Mask1[2] = PermMask[HiIndex^1];
11778 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11780 if (HiIndex >= 2) {
11781 Mask1[0] = PermMask[0];
11782 Mask1[1] = PermMask[1];
11783 Mask1[2] = HiIndex & 1 ? 6 : 4;
11784 Mask1[3] = HiIndex & 1 ? 4 : 6;
11785 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11788 Mask1[0] = HiIndex & 1 ? 2 : 0;
11789 Mask1[1] = HiIndex & 1 ? 0 : 2;
11790 Mask1[2] = PermMask[2];
11791 Mask1[3] = PermMask[3];
11796 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11799 // Break it into (shuffle shuffle_hi, shuffle_lo).
11800 int LoMask[] = { -1, -1, -1, -1 };
11801 int HiMask[] = { -1, -1, -1, -1 };
11803 int *MaskPtr = LoMask;
11804 unsigned MaskIdx = 0;
11805 unsigned LoIdx = 0;
11806 unsigned HiIdx = 2;
11807 for (unsigned i = 0; i != 4; ++i) {
11814 int Idx = PermMask[i];
11816 Locs[i] = std::make_pair(-1, -1);
11817 } else if (Idx < 4) {
11818 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11819 MaskPtr[LoIdx] = Idx;
11822 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11823 MaskPtr[HiIdx] = Idx;
11828 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11829 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11830 int MaskOps[] = { -1, -1, -1, -1 };
11831 for (unsigned i = 0; i != 4; ++i)
11832 if (Locs[i].first != -1)
11833 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11834 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11837 static bool MayFoldVectorLoad(SDValue V) {
11838 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11839 V = V.getOperand(0);
11841 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11842 V = V.getOperand(0);
11843 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11844 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11845 // BUILD_VECTOR (load), undef
11846 V = V.getOperand(0);
11848 return MayFoldLoad(V);
11852 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11853 MVT VT = Op.getSimpleValueType();
11855 // Canonizalize to v2f64.
11856 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11857 return DAG.getNode(ISD::BITCAST, dl, VT,
11858 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11863 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11865 SDValue V1 = Op.getOperand(0);
11866 SDValue V2 = Op.getOperand(1);
11867 MVT VT = Op.getSimpleValueType();
11869 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11871 if (HasSSE2 && VT == MVT::v2f64)
11872 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11874 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11875 return DAG.getNode(ISD::BITCAST, dl, VT,
11876 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11877 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11878 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11882 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11883 SDValue V1 = Op.getOperand(0);
11884 SDValue V2 = Op.getOperand(1);
11885 MVT VT = Op.getSimpleValueType();
11887 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11888 "unsupported shuffle type");
11890 if (V2.getOpcode() == ISD::UNDEF)
11894 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11898 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11899 SDValue V1 = Op.getOperand(0);
11900 SDValue V2 = Op.getOperand(1);
11901 MVT VT = Op.getSimpleValueType();
11902 unsigned NumElems = VT.getVectorNumElements();
11904 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11905 // operand of these instructions is only memory, so check if there's a
11906 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11908 bool CanFoldLoad = false;
11910 // Trivial case, when V2 comes from a load.
11911 if (MayFoldVectorLoad(V2))
11912 CanFoldLoad = true;
11914 // When V1 is a load, it can be folded later into a store in isel, example:
11915 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11917 // (MOVLPSmr addr:$src1, VR128:$src2)
11918 // So, recognize this potential and also use MOVLPS or MOVLPD
11919 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11920 CanFoldLoad = true;
11922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11924 if (HasSSE2 && NumElems == 2)
11925 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11928 // If we don't care about the second element, proceed to use movss.
11929 if (SVOp->getMaskElt(1) != -1)
11930 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11933 // movl and movlp will both match v2i64, but v2i64 is never matched by
11934 // movl earlier because we make it strict to avoid messing with the movlp load
11935 // folding logic (see the code above getMOVLP call). Match it here then,
11936 // this is horrible, but will stay like this until we move all shuffle
11937 // matching to x86 specific nodes. Note that for the 1st condition all
11938 // types are matched with movsd.
11940 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11941 // as to remove this logic from here, as much as possible
11942 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11943 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11944 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11947 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11949 // Invert the operand order and use SHUFPS to match it.
11950 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11951 getShuffleSHUFImmediate(SVOp), DAG);
11954 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11955 SelectionDAG &DAG) {
11957 MVT VT = Load->getSimpleValueType(0);
11958 MVT EVT = VT.getVectorElementType();
11959 SDValue Addr = Load->getOperand(1);
11960 SDValue NewAddr = DAG.getNode(
11961 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11962 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11965 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11966 DAG.getMachineFunction().getMachineMemOperand(
11967 Load->getMemOperand(), 0, EVT.getStoreSize()));
11971 // It is only safe to call this function if isINSERTPSMask is true for
11972 // this shufflevector mask.
11973 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11974 SelectionDAG &DAG) {
11975 // Generate an insertps instruction when inserting an f32 from memory onto a
11976 // v4f32 or when copying a member from one v4f32 to another.
11977 // We also use it for transferring i32 from one register to another,
11978 // since it simply copies the same bits.
11979 // If we're transferring an i32 from memory to a specific element in a
11980 // register, we output a generic DAG that will match the PINSRD
11982 MVT VT = SVOp->getSimpleValueType(0);
11983 MVT EVT = VT.getVectorElementType();
11984 SDValue V1 = SVOp->getOperand(0);
11985 SDValue V2 = SVOp->getOperand(1);
11986 auto Mask = SVOp->getMask();
11987 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11988 "unsupported vector type for insertps/pinsrd");
11990 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11991 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11992 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11996 unsigned DestIndex;
12000 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12003 // If we have 1 element from each vector, we have to check if we're
12004 // changing V1's element's place. If so, we're done. Otherwise, we
12005 // should assume we're changing V2's element's place and behave
12007 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12008 assert(DestIndex <= INT32_MAX && "truncated destination index");
12009 if (FromV1 == FromV2 &&
12010 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12014 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12017 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12018 "More than one element from V1 and from V2, or no elements from one "
12019 "of the vectors. This case should not have returned true from "
12024 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12027 // Get an index into the source vector in the range [0,4) (the mask is
12028 // in the range [0,8) because it can address V1 and V2)
12029 unsigned SrcIndex = Mask[DestIndex] % 4;
12030 if (MayFoldLoad(From)) {
12031 // Trivial case, when From comes from a load and is only used by the
12032 // shuffle. Make it use insertps from the vector that we need from that
12035 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12036 if (!NewLoad.getNode())
12039 if (EVT == MVT::f32) {
12040 // Create this as a scalar to vector to match the instruction pattern.
12041 SDValue LoadScalarToVector =
12042 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12043 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12044 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12046 } else { // EVT == MVT::i32
12047 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12048 // instruction, to match the PINSRD instruction, which loads an i32 to a
12049 // certain vector element.
12050 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12051 DAG.getConstant(DestIndex, MVT::i32));
12055 // Vector-element-to-vector
12056 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12057 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12060 // Reduce a vector shuffle to zext.
12061 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12062 SelectionDAG &DAG) {
12063 // PMOVZX is only available from SSE41.
12064 if (!Subtarget->hasSSE41())
12067 MVT VT = Op.getSimpleValueType();
12069 // Only AVX2 support 256-bit vector integer extending.
12070 if (!Subtarget->hasInt256() && VT.is256BitVector())
12073 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12075 SDValue V1 = Op.getOperand(0);
12076 SDValue V2 = Op.getOperand(1);
12077 unsigned NumElems = VT.getVectorNumElements();
12079 // Extending is an unary operation and the element type of the source vector
12080 // won't be equal to or larger than i64.
12081 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12082 VT.getVectorElementType() == MVT::i64)
12085 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12086 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12087 while ((1U << Shift) < NumElems) {
12088 if (SVOp->getMaskElt(1U << Shift) == 1)
12091 // The maximal ratio is 8, i.e. from i8 to i64.
12096 // Check the shuffle mask.
12097 unsigned Mask = (1U << Shift) - 1;
12098 for (unsigned i = 0; i != NumElems; ++i) {
12099 int EltIdx = SVOp->getMaskElt(i);
12100 if ((i & Mask) != 0 && EltIdx != -1)
12102 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12106 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12107 MVT NeVT = MVT::getIntegerVT(NBits);
12108 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12110 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12113 return DAG.getNode(ISD::BITCAST, DL, VT,
12114 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12117 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12118 SelectionDAG &DAG) {
12119 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12120 MVT VT = Op.getSimpleValueType();
12122 SDValue V1 = Op.getOperand(0);
12123 SDValue V2 = Op.getOperand(1);
12125 if (isZeroShuffle(SVOp))
12126 return getZeroVector(VT, Subtarget, DAG, dl);
12128 // Handle splat operations
12129 if (SVOp->isSplat()) {
12130 // Use vbroadcast whenever the splat comes from a foldable load
12131 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12132 if (Broadcast.getNode())
12136 // Check integer expanding shuffles.
12137 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12138 if (NewOp.getNode())
12141 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12143 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12144 VT == MVT::v32i8) {
12145 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12146 if (NewOp.getNode())
12147 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12148 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12149 // FIXME: Figure out a cleaner way to do this.
12150 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12151 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12152 if (NewOp.getNode()) {
12153 MVT NewVT = NewOp.getSimpleValueType();
12154 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12155 NewVT, true, false))
12156 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12159 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12160 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12161 if (NewOp.getNode()) {
12162 MVT NewVT = NewOp.getSimpleValueType();
12163 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12164 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12173 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12175 SDValue V1 = Op.getOperand(0);
12176 SDValue V2 = Op.getOperand(1);
12177 MVT VT = Op.getSimpleValueType();
12179 unsigned NumElems = VT.getVectorNumElements();
12180 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12181 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12182 bool V1IsSplat = false;
12183 bool V2IsSplat = false;
12184 bool HasSSE2 = Subtarget->hasSSE2();
12185 bool HasFp256 = Subtarget->hasFp256();
12186 bool HasInt256 = Subtarget->hasInt256();
12187 MachineFunction &MF = DAG.getMachineFunction();
12188 bool OptForSize = MF.getFunction()->getAttributes().
12189 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12191 // Check if we should use the experimental vector shuffle lowering. If so,
12192 // delegate completely to that code path.
12193 if (ExperimentalVectorShuffleLowering)
12194 return lowerVectorShuffle(Op, Subtarget, DAG);
12196 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12198 if (V1IsUndef && V2IsUndef)
12199 return DAG.getUNDEF(VT);
12201 // When we create a shuffle node we put the UNDEF node to second operand,
12202 // but in some cases the first operand may be transformed to UNDEF.
12203 // In this case we should just commute the node.
12205 return DAG.getCommutedVectorShuffle(*SVOp);
12207 // Vector shuffle lowering takes 3 steps:
12209 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12210 // narrowing and commutation of operands should be handled.
12211 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12213 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12214 // so the shuffle can be broken into other shuffles and the legalizer can
12215 // try the lowering again.
12217 // The general idea is that no vector_shuffle operation should be left to
12218 // be matched during isel, all of them must be converted to a target specific
12221 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12222 // narrowing and commutation of operands should be handled. The actual code
12223 // doesn't include all of those, work in progress...
12224 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12225 if (NewOp.getNode())
12228 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12230 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12231 // unpckh_undef). Only use pshufd if speed is more important than size.
12232 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12233 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12234 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12235 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12237 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12238 V2IsUndef && MayFoldVectorLoad(V1))
12239 return getMOVDDup(Op, dl, V1, DAG);
12241 if (isMOVHLPS_v_undef_Mask(M, VT))
12242 return getMOVHighToLow(Op, dl, DAG);
12244 // Use to match splats
12245 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12246 (VT == MVT::v2f64 || VT == MVT::v2i64))
12247 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12249 if (isPSHUFDMask(M, VT)) {
12250 // The actual implementation will match the mask in the if above and then
12251 // during isel it can match several different instructions, not only pshufd
12252 // as its name says, sad but true, emulate the behavior for now...
12253 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12254 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12256 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12258 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12259 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12261 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12262 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12265 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12269 if (isPALIGNRMask(M, VT, Subtarget))
12270 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12271 getShufflePALIGNRImmediate(SVOp),
12274 if (isVALIGNMask(M, VT, Subtarget))
12275 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12276 getShuffleVALIGNImmediate(SVOp),
12279 // Check if this can be converted into a logical shift.
12280 bool isLeft = false;
12281 unsigned ShAmt = 0;
12283 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12284 if (isShift && ShVal.hasOneUse()) {
12285 // If the shifted value has multiple uses, it may be cheaper to use
12286 // v_set0 + movlhps or movhlps, etc.
12287 MVT EltVT = VT.getVectorElementType();
12288 ShAmt *= EltVT.getSizeInBits();
12289 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12292 if (isMOVLMask(M, VT)) {
12293 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12294 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12295 if (!isMOVLPMask(M, VT)) {
12296 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12297 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12299 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12300 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12304 // FIXME: fold these into legal mask.
12305 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12306 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12308 if (isMOVHLPSMask(M, VT))
12309 return getMOVHighToLow(Op, dl, DAG);
12311 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12312 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12314 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12315 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12317 if (isMOVLPMask(M, VT))
12318 return getMOVLP(Op, dl, DAG, HasSSE2);
12320 if (ShouldXformToMOVHLPS(M, VT) ||
12321 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12322 return DAG.getCommutedVectorShuffle(*SVOp);
12325 // No better options. Use a vshldq / vsrldq.
12326 MVT EltVT = VT.getVectorElementType();
12327 ShAmt *= EltVT.getSizeInBits();
12328 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12331 bool Commuted = false;
12332 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12333 // 1,1,1,1 -> v8i16 though.
12334 BitVector UndefElements;
12335 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12336 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12338 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12339 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12342 // Canonicalize the splat or undef, if present, to be on the RHS.
12343 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12344 CommuteVectorShuffleMask(M, NumElems);
12346 std::swap(V1IsSplat, V2IsSplat);
12350 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12351 // Shuffling low element of v1 into undef, just return v1.
12354 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12355 // the instruction selector will not match, so get a canonical MOVL with
12356 // swapped operands to undo the commute.
12357 return getMOVL(DAG, dl, VT, V2, V1);
12360 if (isUNPCKLMask(M, VT, HasInt256))
12361 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12363 if (isUNPCKHMask(M, VT, HasInt256))
12364 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12367 // Normalize mask so all entries that point to V2 points to its first
12368 // element then try to match unpck{h|l} again. If match, return a
12369 // new vector_shuffle with the corrected mask.p
12370 SmallVector<int, 8> NewMask(M.begin(), M.end());
12371 NormalizeMask(NewMask, NumElems);
12372 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12373 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12374 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12375 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12379 // Commute is back and try unpck* again.
12380 // FIXME: this seems wrong.
12381 CommuteVectorShuffleMask(M, NumElems);
12383 std::swap(V1IsSplat, V2IsSplat);
12385 if (isUNPCKLMask(M, VT, HasInt256))
12386 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12388 if (isUNPCKHMask(M, VT, HasInt256))
12389 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12392 // Normalize the node to match x86 shuffle ops if needed
12393 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12394 return DAG.getCommutedVectorShuffle(*SVOp);
12396 // The checks below are all present in isShuffleMaskLegal, but they are
12397 // inlined here right now to enable us to directly emit target specific
12398 // nodes, and remove one by one until they don't return Op anymore.
12400 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12401 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12402 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12403 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12406 if (isPSHUFHWMask(M, VT, HasInt256))
12407 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12408 getShufflePSHUFHWImmediate(SVOp),
12411 if (isPSHUFLWMask(M, VT, HasInt256))
12412 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12413 getShufflePSHUFLWImmediate(SVOp),
12416 unsigned MaskValue;
12417 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12419 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12421 if (isSHUFPMask(M, VT))
12422 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12423 getShuffleSHUFImmediate(SVOp), DAG);
12425 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12426 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12427 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12428 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12430 //===--------------------------------------------------------------------===//
12431 // Generate target specific nodes for 128 or 256-bit shuffles only
12432 // supported in the AVX instruction set.
12435 // Handle VMOVDDUPY permutations
12436 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12437 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12439 // Handle VPERMILPS/D* permutations
12440 if (isVPERMILPMask(M, VT)) {
12441 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12442 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12443 getShuffleSHUFImmediate(SVOp), DAG);
12444 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12445 getShuffleSHUFImmediate(SVOp), DAG);
12449 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12450 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12451 Idx*(NumElems/2), DAG, dl);
12453 // Handle VPERM2F128/VPERM2I128 permutations
12454 if (isVPERM2X128Mask(M, VT, HasFp256))
12455 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12456 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12458 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12459 return getINSERTPS(SVOp, dl, DAG);
12462 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12463 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12465 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12466 VT.is512BitVector()) {
12467 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12468 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12469 SmallVector<SDValue, 16> permclMask;
12470 for (unsigned i = 0; i != NumElems; ++i) {
12471 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12474 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12476 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12477 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12478 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12479 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12480 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12483 //===--------------------------------------------------------------------===//
12484 // Since no target specific shuffle was selected for this generic one,
12485 // lower it into other known shuffles. FIXME: this isn't true yet, but
12486 // this is the plan.
12489 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12490 if (VT == MVT::v8i16) {
12491 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12492 if (NewOp.getNode())
12496 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12497 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12498 if (NewOp.getNode())
12502 if (VT == MVT::v16i8) {
12503 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12504 if (NewOp.getNode())
12508 if (VT == MVT::v32i8) {
12509 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12510 if (NewOp.getNode())
12514 // Handle all 128-bit wide vectors with 4 elements, and match them with
12515 // several different shuffle types.
12516 if (NumElems == 4 && VT.is128BitVector())
12517 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12519 // Handle general 256-bit shuffles
12520 if (VT.is256BitVector())
12521 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12526 // This function assumes its argument is a BUILD_VECTOR of constants or
12527 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12529 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12530 unsigned &MaskValue) {
12532 unsigned NumElems = BuildVector->getNumOperands();
12533 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12534 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12535 unsigned NumElemsInLane = NumElems / NumLanes;
12537 // Blend for v16i16 should be symetric for the both lanes.
12538 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12539 SDValue EltCond = BuildVector->getOperand(i);
12540 SDValue SndLaneEltCond =
12541 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12543 int Lane1Cond = -1, Lane2Cond = -1;
12544 if (isa<ConstantSDNode>(EltCond))
12545 Lane1Cond = !isZero(EltCond);
12546 if (isa<ConstantSDNode>(SndLaneEltCond))
12547 Lane2Cond = !isZero(SndLaneEltCond);
12549 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12550 // Lane1Cond != 0, means we want the first argument.
12551 // Lane1Cond == 0, means we want the second argument.
12552 // The encoding of this argument is 0 for the first argument, 1
12553 // for the second. Therefore, invert the condition.
12554 MaskValue |= !Lane1Cond << i;
12555 else if (Lane1Cond < 0)
12556 MaskValue |= !Lane2Cond << i;
12563 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12565 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12566 SelectionDAG &DAG) {
12567 SDValue Cond = Op.getOperand(0);
12568 SDValue LHS = Op.getOperand(1);
12569 SDValue RHS = Op.getOperand(2);
12571 MVT VT = Op.getSimpleValueType();
12572 MVT EltVT = VT.getVectorElementType();
12573 unsigned NumElems = VT.getVectorNumElements();
12575 // There is no blend with immediate in AVX-512.
12576 if (VT.is512BitVector())
12579 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12581 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12584 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12587 // Check the mask for BLEND and build the value.
12588 unsigned MaskValue = 0;
12589 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12592 // Convert i32 vectors to floating point if it is not AVX2.
12593 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12595 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12596 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12598 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12599 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12602 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12603 DAG.getConstant(MaskValue, MVT::i32));
12604 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12607 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12608 // A vselect where all conditions and data are constants can be optimized into
12609 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12610 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12611 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12612 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12615 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12616 if (BlendOp.getNode())
12619 // Some types for vselect were previously set to Expand, not Legal or
12620 // Custom. Return an empty SDValue so we fall-through to Expand, after
12621 // the Custom lowering phase.
12622 MVT VT = Op.getSimpleValueType();
12623 switch (VT.SimpleTy) {
12628 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12633 // We couldn't create a "Blend with immediate" node.
12634 // This node should still be legal, but we'll have to emit a blendv*
12639 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12640 MVT VT = Op.getSimpleValueType();
12643 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12646 if (VT.getSizeInBits() == 8) {
12647 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12648 Op.getOperand(0), Op.getOperand(1));
12649 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12650 DAG.getValueType(VT));
12651 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12654 if (VT.getSizeInBits() == 16) {
12655 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12656 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12658 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12659 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12660 DAG.getNode(ISD::BITCAST, dl,
12663 Op.getOperand(1)));
12664 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12665 Op.getOperand(0), Op.getOperand(1));
12666 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12667 DAG.getValueType(VT));
12668 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12671 if (VT == MVT::f32) {
12672 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12673 // the result back to FR32 register. It's only worth matching if the
12674 // result has a single use which is a store or a bitcast to i32. And in
12675 // the case of a store, it's not worth it if the index is a constant 0,
12676 // because a MOVSSmr can be used instead, which is smaller and faster.
12677 if (!Op.hasOneUse())
12679 SDNode *User = *Op.getNode()->use_begin();
12680 if ((User->getOpcode() != ISD::STORE ||
12681 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12682 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12683 (User->getOpcode() != ISD::BITCAST ||
12684 User->getValueType(0) != MVT::i32))
12686 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12687 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12690 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12693 if (VT == MVT::i32 || VT == MVT::i64) {
12694 // ExtractPS/pextrq works with constant index.
12695 if (isa<ConstantSDNode>(Op.getOperand(1)))
12701 /// Extract one bit from mask vector, like v16i1 or v8i1.
12702 /// AVX-512 feature.
12704 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12705 SDValue Vec = Op.getOperand(0);
12707 MVT VecVT = Vec.getSimpleValueType();
12708 SDValue Idx = Op.getOperand(1);
12709 MVT EltVT = Op.getSimpleValueType();
12711 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12713 // variable index can't be handled in mask registers,
12714 // extend vector to VR512
12715 if (!isa<ConstantSDNode>(Idx)) {
12716 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12717 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12718 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12719 ExtVT.getVectorElementType(), Ext, Idx);
12720 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12723 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12724 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12725 unsigned MaxSift = rc->getSize()*8 - 1;
12726 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12727 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12728 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12729 DAG.getConstant(MaxSift, MVT::i8));
12730 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12731 DAG.getIntPtrConstant(0));
12735 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12736 SelectionDAG &DAG) const {
12738 SDValue Vec = Op.getOperand(0);
12739 MVT VecVT = Vec.getSimpleValueType();
12740 SDValue Idx = Op.getOperand(1);
12742 if (Op.getSimpleValueType() == MVT::i1)
12743 return ExtractBitFromMaskVector(Op, DAG);
12745 if (!isa<ConstantSDNode>(Idx)) {
12746 if (VecVT.is512BitVector() ||
12747 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12748 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12751 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12752 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12753 MaskEltVT.getSizeInBits());
12755 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12756 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12757 getZeroVector(MaskVT, Subtarget, DAG, dl),
12758 Idx, DAG.getConstant(0, getPointerTy()));
12759 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12760 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12761 Perm, DAG.getConstant(0, getPointerTy()));
12766 // If this is a 256-bit vector result, first extract the 128-bit vector and
12767 // then extract the element from the 128-bit vector.
12768 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12770 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12771 // Get the 128-bit vector.
12772 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12773 MVT EltVT = VecVT.getVectorElementType();
12775 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12777 //if (IdxVal >= NumElems/2)
12778 // IdxVal -= NumElems/2;
12779 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12780 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12781 DAG.getConstant(IdxVal, MVT::i32));
12784 assert(VecVT.is128BitVector() && "Unexpected vector length");
12786 if (Subtarget->hasSSE41()) {
12787 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12792 MVT VT = Op.getSimpleValueType();
12793 // TODO: handle v16i8.
12794 if (VT.getSizeInBits() == 16) {
12795 SDValue Vec = Op.getOperand(0);
12796 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12798 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12799 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12800 DAG.getNode(ISD::BITCAST, dl,
12802 Op.getOperand(1)));
12803 // Transform it so it match pextrw which produces a 32-bit result.
12804 MVT EltVT = MVT::i32;
12805 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12806 Op.getOperand(0), Op.getOperand(1));
12807 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12808 DAG.getValueType(VT));
12809 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12812 if (VT.getSizeInBits() == 32) {
12813 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12817 // SHUFPS the element to the lowest double word, then movss.
12818 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12819 MVT VVT = Op.getOperand(0).getSimpleValueType();
12820 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12821 DAG.getUNDEF(VVT), Mask);
12822 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12823 DAG.getIntPtrConstant(0));
12826 if (VT.getSizeInBits() == 64) {
12827 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12828 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12829 // to match extract_elt for f64.
12830 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12834 // UNPCKHPD the element to the lowest double word, then movsd.
12835 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12836 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12837 int Mask[2] = { 1, -1 };
12838 MVT VVT = Op.getOperand(0).getSimpleValueType();
12839 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12840 DAG.getUNDEF(VVT), Mask);
12841 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12842 DAG.getIntPtrConstant(0));
12848 /// Insert one bit to mask vector, like v16i1 or v8i1.
12849 /// AVX-512 feature.
12851 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12853 SDValue Vec = Op.getOperand(0);
12854 SDValue Elt = Op.getOperand(1);
12855 SDValue Idx = Op.getOperand(2);
12856 MVT VecVT = Vec.getSimpleValueType();
12858 if (!isa<ConstantSDNode>(Idx)) {
12859 // Non constant index. Extend source and destination,
12860 // insert element and then truncate the result.
12861 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12862 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12863 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12864 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12865 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12866 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12869 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12870 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12871 if (Vec.getOpcode() == ISD::UNDEF)
12872 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12873 DAG.getConstant(IdxVal, MVT::i8));
12874 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12875 unsigned MaxSift = rc->getSize()*8 - 1;
12876 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12877 DAG.getConstant(MaxSift, MVT::i8));
12878 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12879 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12880 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12883 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12884 SelectionDAG &DAG) const {
12885 MVT VT = Op.getSimpleValueType();
12886 MVT EltVT = VT.getVectorElementType();
12888 if (EltVT == MVT::i1)
12889 return InsertBitToMaskVector(Op, DAG);
12892 SDValue N0 = Op.getOperand(0);
12893 SDValue N1 = Op.getOperand(1);
12894 SDValue N2 = Op.getOperand(2);
12895 if (!isa<ConstantSDNode>(N2))
12897 auto *N2C = cast<ConstantSDNode>(N2);
12898 unsigned IdxVal = N2C->getZExtValue();
12900 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12901 // into that, and then insert the subvector back into the result.
12902 if (VT.is256BitVector() || VT.is512BitVector()) {
12903 // Get the desired 128-bit vector half.
12904 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12906 // Insert the element into the desired half.
12907 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12908 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12910 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12911 DAG.getConstant(IdxIn128, MVT::i32));
12913 // Insert the changed part back to the 256-bit vector
12914 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12916 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12918 if (Subtarget->hasSSE41()) {
12919 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12921 if (VT == MVT::v8i16) {
12922 Opc = X86ISD::PINSRW;
12924 assert(VT == MVT::v16i8);
12925 Opc = X86ISD::PINSRB;
12928 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12930 if (N1.getValueType() != MVT::i32)
12931 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12932 if (N2.getValueType() != MVT::i32)
12933 N2 = DAG.getIntPtrConstant(IdxVal);
12934 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12937 if (EltVT == MVT::f32) {
12938 // Bits [7:6] of the constant are the source select. This will always be
12939 // zero here. The DAG Combiner may combine an extract_elt index into
12941 // bits. For example (insert (extract, 3), 2) could be matched by
12943 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12944 // Bits [5:4] of the constant are the destination select. This is the
12945 // value of the incoming immediate.
12946 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12947 // combine either bitwise AND or insert of float 0.0 to set these bits.
12948 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12949 // Create this as a scalar to vector..
12950 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12951 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12954 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12955 // PINSR* works with constant index.
12960 if (EltVT == MVT::i8)
12963 if (EltVT.getSizeInBits() == 16) {
12964 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12965 // as its second argument.
12966 if (N1.getValueType() != MVT::i32)
12967 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12968 if (N2.getValueType() != MVT::i32)
12969 N2 = DAG.getIntPtrConstant(IdxVal);
12970 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12975 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12977 MVT OpVT = Op.getSimpleValueType();
12979 // If this is a 256-bit vector result, first insert into a 128-bit
12980 // vector and then insert into the 256-bit vector.
12981 if (!OpVT.is128BitVector()) {
12982 // Insert into a 128-bit vector.
12983 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12984 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12985 OpVT.getVectorNumElements() / SizeFactor);
12987 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12989 // Insert the 128-bit vector.
12990 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12993 if (OpVT == MVT::v1i64 &&
12994 Op.getOperand(0).getValueType() == MVT::i64)
12995 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12997 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12998 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12999 return DAG.getNode(ISD::BITCAST, dl, OpVT,
13000 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13003 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13004 // a simple subregister reference or explicit instructions to grab
13005 // upper bits of a vector.
13006 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13007 SelectionDAG &DAG) {
13009 SDValue In = Op.getOperand(0);
13010 SDValue Idx = Op.getOperand(1);
13011 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13012 MVT ResVT = Op.getSimpleValueType();
13013 MVT InVT = In.getSimpleValueType();
13015 if (Subtarget->hasFp256()) {
13016 if (ResVT.is128BitVector() &&
13017 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13018 isa<ConstantSDNode>(Idx)) {
13019 return Extract128BitVector(In, IdxVal, DAG, dl);
13021 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13022 isa<ConstantSDNode>(Idx)) {
13023 return Extract256BitVector(In, IdxVal, DAG, dl);
13029 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13030 // simple superregister reference or explicit instructions to insert
13031 // the upper bits of a vector.
13032 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13033 SelectionDAG &DAG) {
13034 if (Subtarget->hasFp256()) {
13035 SDLoc dl(Op.getNode());
13036 SDValue Vec = Op.getNode()->getOperand(0);
13037 SDValue SubVec = Op.getNode()->getOperand(1);
13038 SDValue Idx = Op.getNode()->getOperand(2);
13040 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13041 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13042 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13043 isa<ConstantSDNode>(Idx)) {
13044 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13045 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13048 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13049 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13050 isa<ConstantSDNode>(Idx)) {
13051 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13052 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13058 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13059 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13060 // one of the above mentioned nodes. It has to be wrapped because otherwise
13061 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13062 // be used to form addressing mode. These wrapped nodes will be selected
13065 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13066 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13068 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13069 // global base reg.
13070 unsigned char OpFlag = 0;
13071 unsigned WrapperKind = X86ISD::Wrapper;
13072 CodeModel::Model M = DAG.getTarget().getCodeModel();
13074 if (Subtarget->isPICStyleRIPRel() &&
13075 (M == CodeModel::Small || M == CodeModel::Kernel))
13076 WrapperKind = X86ISD::WrapperRIP;
13077 else if (Subtarget->isPICStyleGOT())
13078 OpFlag = X86II::MO_GOTOFF;
13079 else if (Subtarget->isPICStyleStubPIC())
13080 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13082 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13083 CP->getAlignment(),
13084 CP->getOffset(), OpFlag);
13086 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13087 // With PIC, the address is actually $g + Offset.
13089 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13090 DAG.getNode(X86ISD::GlobalBaseReg,
13091 SDLoc(), getPointerTy()),
13098 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13099 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13101 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13102 // global base reg.
13103 unsigned char OpFlag = 0;
13104 unsigned WrapperKind = X86ISD::Wrapper;
13105 CodeModel::Model M = DAG.getTarget().getCodeModel();
13107 if (Subtarget->isPICStyleRIPRel() &&
13108 (M == CodeModel::Small || M == CodeModel::Kernel))
13109 WrapperKind = X86ISD::WrapperRIP;
13110 else if (Subtarget->isPICStyleGOT())
13111 OpFlag = X86II::MO_GOTOFF;
13112 else if (Subtarget->isPICStyleStubPIC())
13113 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13115 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13118 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13120 // With PIC, the address is actually $g + Offset.
13122 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13123 DAG.getNode(X86ISD::GlobalBaseReg,
13124 SDLoc(), getPointerTy()),
13131 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13132 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13134 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13135 // global base reg.
13136 unsigned char OpFlag = 0;
13137 unsigned WrapperKind = X86ISD::Wrapper;
13138 CodeModel::Model M = DAG.getTarget().getCodeModel();
13140 if (Subtarget->isPICStyleRIPRel() &&
13141 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13142 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13143 OpFlag = X86II::MO_GOTPCREL;
13144 WrapperKind = X86ISD::WrapperRIP;
13145 } else if (Subtarget->isPICStyleGOT()) {
13146 OpFlag = X86II::MO_GOT;
13147 } else if (Subtarget->isPICStyleStubPIC()) {
13148 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13149 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13150 OpFlag = X86II::MO_DARWIN_NONLAZY;
13153 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13156 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13158 // With PIC, the address is actually $g + Offset.
13159 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13160 !Subtarget->is64Bit()) {
13161 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13162 DAG.getNode(X86ISD::GlobalBaseReg,
13163 SDLoc(), getPointerTy()),
13167 // For symbols that require a load from a stub to get the address, emit the
13169 if (isGlobalStubReference(OpFlag))
13170 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13171 MachinePointerInfo::getGOT(), false, false, false, 0);
13177 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13178 // Create the TargetBlockAddressAddress node.
13179 unsigned char OpFlags =
13180 Subtarget->ClassifyBlockAddressReference();
13181 CodeModel::Model M = DAG.getTarget().getCodeModel();
13182 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13183 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13185 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13188 if (Subtarget->isPICStyleRIPRel() &&
13189 (M == CodeModel::Small || M == CodeModel::Kernel))
13190 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13192 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13194 // With PIC, the address is actually $g + Offset.
13195 if (isGlobalRelativeToPICBase(OpFlags)) {
13196 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13197 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13205 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13206 int64_t Offset, SelectionDAG &DAG) const {
13207 // Create the TargetGlobalAddress node, folding in the constant
13208 // offset if it is legal.
13209 unsigned char OpFlags =
13210 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13211 CodeModel::Model M = DAG.getTarget().getCodeModel();
13213 if (OpFlags == X86II::MO_NO_FLAG &&
13214 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13215 // A direct static reference to a global.
13216 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13219 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13222 if (Subtarget->isPICStyleRIPRel() &&
13223 (M == CodeModel::Small || M == CodeModel::Kernel))
13224 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13226 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13228 // With PIC, the address is actually $g + Offset.
13229 if (isGlobalRelativeToPICBase(OpFlags)) {
13230 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13231 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13235 // For globals that require a load from a stub to get the address, emit the
13237 if (isGlobalStubReference(OpFlags))
13238 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13239 MachinePointerInfo::getGOT(), false, false, false, 0);
13241 // If there was a non-zero offset that we didn't fold, create an explicit
13242 // addition for it.
13244 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13245 DAG.getConstant(Offset, getPointerTy()));
13251 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13252 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13253 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13254 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13258 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13259 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13260 unsigned char OperandFlags, bool LocalDynamic = false) {
13261 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13262 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13264 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13265 GA->getValueType(0),
13269 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13273 SDValue Ops[] = { Chain, TGA, *InFlag };
13274 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13276 SDValue Ops[] = { Chain, TGA };
13277 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13280 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13281 MFI->setAdjustsStack(true);
13282 MFI->setHasCalls(true);
13284 SDValue Flag = Chain.getValue(1);
13285 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13288 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13290 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13293 SDLoc dl(GA); // ? function entry point might be better
13294 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13295 DAG.getNode(X86ISD::GlobalBaseReg,
13296 SDLoc(), PtrVT), InFlag);
13297 InFlag = Chain.getValue(1);
13299 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13302 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13304 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13306 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13307 X86::RAX, X86II::MO_TLSGD);
13310 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13316 // Get the start address of the TLS block for this module.
13317 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13318 .getInfo<X86MachineFunctionInfo>();
13319 MFI->incNumLocalDynamicTLSAccesses();
13323 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13324 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13327 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13328 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13329 InFlag = Chain.getValue(1);
13330 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13331 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13334 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13338 unsigned char OperandFlags = X86II::MO_DTPOFF;
13339 unsigned WrapperKind = X86ISD::Wrapper;
13340 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13341 GA->getValueType(0),
13342 GA->getOffset(), OperandFlags);
13343 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13345 // Add x@dtpoff with the base.
13346 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13349 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13350 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13351 const EVT PtrVT, TLSModel::Model model,
13352 bool is64Bit, bool isPIC) {
13355 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13356 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13357 is64Bit ? 257 : 256));
13359 SDValue ThreadPointer =
13360 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13361 MachinePointerInfo(Ptr), false, false, false, 0);
13363 unsigned char OperandFlags = 0;
13364 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13366 unsigned WrapperKind = X86ISD::Wrapper;
13367 if (model == TLSModel::LocalExec) {
13368 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13369 } else if (model == TLSModel::InitialExec) {
13371 OperandFlags = X86II::MO_GOTTPOFF;
13372 WrapperKind = X86ISD::WrapperRIP;
13374 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13377 llvm_unreachable("Unexpected model");
13380 // emit "addl x@ntpoff,%eax" (local exec)
13381 // or "addl x@indntpoff,%eax" (initial exec)
13382 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13384 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13385 GA->getOffset(), OperandFlags);
13386 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13388 if (model == TLSModel::InitialExec) {
13389 if (isPIC && !is64Bit) {
13390 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13391 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13395 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13396 MachinePointerInfo::getGOT(), false, false, false, 0);
13399 // The address of the thread local variable is the add of the thread
13400 // pointer with the offset of the variable.
13401 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13405 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13407 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13408 const GlobalValue *GV = GA->getGlobal();
13410 if (Subtarget->isTargetELF()) {
13411 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13414 case TLSModel::GeneralDynamic:
13415 if (Subtarget->is64Bit())
13416 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13417 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13418 case TLSModel::LocalDynamic:
13419 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13420 Subtarget->is64Bit());
13421 case TLSModel::InitialExec:
13422 case TLSModel::LocalExec:
13423 return LowerToTLSExecModel(
13424 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13425 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13427 llvm_unreachable("Unknown TLS model.");
13430 if (Subtarget->isTargetDarwin()) {
13431 // Darwin only has one model of TLS. Lower to that.
13432 unsigned char OpFlag = 0;
13433 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13434 X86ISD::WrapperRIP : X86ISD::Wrapper;
13436 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13437 // global base reg.
13438 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13439 !Subtarget->is64Bit();
13441 OpFlag = X86II::MO_TLVP_PIC_BASE;
13443 OpFlag = X86II::MO_TLVP;
13445 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13446 GA->getValueType(0),
13447 GA->getOffset(), OpFlag);
13448 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13450 // With PIC32, the address is actually $g + Offset.
13452 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13453 DAG.getNode(X86ISD::GlobalBaseReg,
13454 SDLoc(), getPointerTy()),
13457 // Lowering the machine isd will make sure everything is in the right
13459 SDValue Chain = DAG.getEntryNode();
13460 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13461 SDValue Args[] = { Chain, Offset };
13462 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13464 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13465 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13466 MFI->setAdjustsStack(true);
13468 // And our return value (tls address) is in the standard call return value
13470 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13471 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13472 Chain.getValue(1));
13475 if (Subtarget->isTargetKnownWindowsMSVC() ||
13476 Subtarget->isTargetWindowsGNU()) {
13477 // Just use the implicit TLS architecture
13478 // Need to generate someting similar to:
13479 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13481 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13482 // mov rcx, qword [rdx+rcx*8]
13483 // mov eax, .tls$:tlsvar
13484 // [rax+rcx] contains the address
13485 // Windows 64bit: gs:0x58
13486 // Windows 32bit: fs:__tls_array
13489 SDValue Chain = DAG.getEntryNode();
13491 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13492 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13493 // use its literal value of 0x2C.
13494 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13495 ? Type::getInt8PtrTy(*DAG.getContext(),
13497 : Type::getInt32PtrTy(*DAG.getContext(),
13501 Subtarget->is64Bit()
13502 ? DAG.getIntPtrConstant(0x58)
13503 : (Subtarget->isTargetWindowsGNU()
13504 ? DAG.getIntPtrConstant(0x2C)
13505 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13507 SDValue ThreadPointer =
13508 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13509 MachinePointerInfo(Ptr), false, false, false, 0);
13511 // Load the _tls_index variable
13512 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13513 if (Subtarget->is64Bit())
13514 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13515 IDX, MachinePointerInfo(), MVT::i32,
13516 false, false, false, 0);
13518 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13519 false, false, false, 0);
13521 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13523 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13525 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13526 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13527 false, false, false, 0);
13529 // Get the offset of start of .tls section
13530 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13531 GA->getValueType(0),
13532 GA->getOffset(), X86II::MO_SECREL);
13533 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13535 // The address of the thread local variable is the add of the thread
13536 // pointer with the offset of the variable.
13537 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13540 llvm_unreachable("TLS not implemented for this target.");
13543 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13544 /// and take a 2 x i32 value to shift plus a shift amount.
13545 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13546 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13547 MVT VT = Op.getSimpleValueType();
13548 unsigned VTBits = VT.getSizeInBits();
13550 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13551 SDValue ShOpLo = Op.getOperand(0);
13552 SDValue ShOpHi = Op.getOperand(1);
13553 SDValue ShAmt = Op.getOperand(2);
13554 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13555 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13557 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13558 DAG.getConstant(VTBits - 1, MVT::i8));
13559 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13560 DAG.getConstant(VTBits - 1, MVT::i8))
13561 : DAG.getConstant(0, VT);
13563 SDValue Tmp2, Tmp3;
13564 if (Op.getOpcode() == ISD::SHL_PARTS) {
13565 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13566 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13568 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13569 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13572 // If the shift amount is larger or equal than the width of a part we can't
13573 // rely on the results of shld/shrd. Insert a test and select the appropriate
13574 // values for large shift amounts.
13575 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13576 DAG.getConstant(VTBits, MVT::i8));
13577 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13578 AndNode, DAG.getConstant(0, MVT::i8));
13581 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13582 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13583 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13585 if (Op.getOpcode() == ISD::SHL_PARTS) {
13586 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13587 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13589 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13590 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13593 SDValue Ops[2] = { Lo, Hi };
13594 return DAG.getMergeValues(Ops, dl);
13597 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13598 SelectionDAG &DAG) const {
13599 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13602 if (SrcVT.isVector()) {
13603 if (SrcVT.getVectorElementType() == MVT::i1) {
13604 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13605 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13606 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13607 Op.getOperand(0)));
13612 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13613 "Unknown SINT_TO_FP to lower!");
13615 // These are really Legal; return the operand so the caller accepts it as
13617 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13619 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13620 Subtarget->is64Bit()) {
13624 unsigned Size = SrcVT.getSizeInBits()/8;
13625 MachineFunction &MF = DAG.getMachineFunction();
13626 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13627 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13628 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13630 MachinePointerInfo::getFixedStack(SSFI),
13632 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13635 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13637 SelectionDAG &DAG) const {
13641 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13643 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13645 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13647 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13649 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13650 MachineMemOperand *MMO;
13652 int SSFI = FI->getIndex();
13654 DAG.getMachineFunction()
13655 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13656 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13658 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13659 StackSlot = StackSlot.getOperand(1);
13661 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13662 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13664 Tys, Ops, SrcVT, MMO);
13667 Chain = Result.getValue(1);
13668 SDValue InFlag = Result.getValue(2);
13670 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13671 // shouldn't be necessary except that RFP cannot be live across
13672 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13673 MachineFunction &MF = DAG.getMachineFunction();
13674 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13675 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13676 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13677 Tys = DAG.getVTList(MVT::Other);
13679 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13681 MachineMemOperand *MMO =
13682 DAG.getMachineFunction()
13683 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13684 MachineMemOperand::MOStore, SSFISize, SSFISize);
13686 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13687 Ops, Op.getValueType(), MMO);
13688 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13689 MachinePointerInfo::getFixedStack(SSFI),
13690 false, false, false, 0);
13696 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13697 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13698 SelectionDAG &DAG) const {
13699 // This algorithm is not obvious. Here it is what we're trying to output:
13702 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13703 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13705 haddpd %xmm0, %xmm0
13707 pshufd $0x4e, %xmm0, %xmm1
13713 LLVMContext *Context = DAG.getContext();
13715 // Build some magic constants.
13716 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13717 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13718 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13720 SmallVector<Constant*,2> CV1;
13722 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13723 APInt(64, 0x4330000000000000ULL))));
13725 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13726 APInt(64, 0x4530000000000000ULL))));
13727 Constant *C1 = ConstantVector::get(CV1);
13728 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13730 // Load the 64-bit value into an XMM register.
13731 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13733 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13734 MachinePointerInfo::getConstantPool(),
13735 false, false, false, 16);
13736 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13737 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13740 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13741 MachinePointerInfo::getConstantPool(),
13742 false, false, false, 16);
13743 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13744 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13747 if (Subtarget->hasSSE3()) {
13748 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13749 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13751 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13752 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13754 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13755 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13759 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13760 DAG.getIntPtrConstant(0));
13763 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13764 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13765 SelectionDAG &DAG) const {
13767 // FP constant to bias correct the final result.
13768 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13771 // Load the 32-bit value into an XMM register.
13772 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13775 // Zero out the upper parts of the register.
13776 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13778 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13779 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13780 DAG.getIntPtrConstant(0));
13782 // Or the load with the bias.
13783 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13784 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13785 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13786 MVT::v2f64, Load)),
13787 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13788 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13789 MVT::v2f64, Bias)));
13790 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13791 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13792 DAG.getIntPtrConstant(0));
13794 // Subtract the bias.
13795 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13797 // Handle final rounding.
13798 EVT DestVT = Op.getValueType();
13800 if (DestVT.bitsLT(MVT::f64))
13801 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13802 DAG.getIntPtrConstant(0));
13803 if (DestVT.bitsGT(MVT::f64))
13804 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13806 // Handle final rounding.
13810 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13811 const X86Subtarget &Subtarget) {
13812 // The algorithm is the following:
13813 // #ifdef __SSE4_1__
13814 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13815 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13816 // (uint4) 0x53000000, 0xaa);
13818 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13819 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13821 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13822 // return (float4) lo + fhi;
13825 SDValue V = Op->getOperand(0);
13826 EVT VecIntVT = V.getValueType();
13827 bool Is128 = VecIntVT == MVT::v4i32;
13828 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13829 // If we convert to something else than the supported type, e.g., to v4f64,
13831 if (VecFloatVT != Op->getValueType(0))
13834 unsigned NumElts = VecIntVT.getVectorNumElements();
13835 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13836 "Unsupported custom type");
13837 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13839 // In the #idef/#else code, we have in common:
13840 // - The vector of constants:
13846 // Create the splat vector for 0x4b000000.
13847 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13848 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13849 CstLow, CstLow, CstLow, CstLow};
13850 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13851 makeArrayRef(&CstLowArray[0], NumElts));
13852 // Create the splat vector for 0x53000000.
13853 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13854 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13855 CstHigh, CstHigh, CstHigh, CstHigh};
13856 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13857 makeArrayRef(&CstHighArray[0], NumElts));
13859 // Create the right shift.
13860 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13861 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13862 CstShift, CstShift, CstShift, CstShift};
13863 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13864 makeArrayRef(&CstShiftArray[0], NumElts));
13865 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13868 if (Subtarget.hasSSE41()) {
13869 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13870 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13871 SDValue VecCstLowBitcast =
13872 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13873 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13874 // Low will be bitcasted right away, so do not bother bitcasting back to its
13876 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13877 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13878 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13879 // (uint4) 0x53000000, 0xaa);
13880 SDValue VecCstHighBitcast =
13881 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13882 SDValue VecShiftBitcast =
13883 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13884 // High will be bitcasted right away, so do not bother bitcasting back to
13885 // its original type.
13886 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13887 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13889 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13890 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13891 CstMask, CstMask, CstMask);
13892 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13893 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13894 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13896 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13897 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13900 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13901 SDValue CstFAdd = DAG.getConstantFP(
13902 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13903 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13904 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13905 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13906 makeArrayRef(&CstFAddArray[0], NumElts));
13908 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13909 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13911 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13912 // return (float4) lo + fhi;
13913 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13914 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13917 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13918 SelectionDAG &DAG) const {
13919 SDValue N0 = Op.getOperand(0);
13920 MVT SVT = N0.getSimpleValueType();
13923 switch (SVT.SimpleTy) {
13925 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13930 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13931 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13932 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13936 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13938 llvm_unreachable(nullptr);
13941 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13942 SelectionDAG &DAG) const {
13943 SDValue N0 = Op.getOperand(0);
13946 if (Op.getValueType().isVector())
13947 return lowerUINT_TO_FP_vec(Op, DAG);
13949 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13950 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13951 // the optimization here.
13952 if (DAG.SignBitIsZero(N0))
13953 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13955 MVT SrcVT = N0.getSimpleValueType();
13956 MVT DstVT = Op.getSimpleValueType();
13957 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13958 return LowerUINT_TO_FP_i64(Op, DAG);
13959 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13960 return LowerUINT_TO_FP_i32(Op, DAG);
13961 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13964 // Make a 64-bit buffer, and use it to build an FILD.
13965 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13966 if (SrcVT == MVT::i32) {
13967 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13968 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13969 getPointerTy(), StackSlot, WordOff);
13970 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13971 StackSlot, MachinePointerInfo(),
13973 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13974 OffsetSlot, MachinePointerInfo(),
13976 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13980 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13981 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13982 StackSlot, MachinePointerInfo(),
13984 // For i64 source, we need to add the appropriate power of 2 if the input
13985 // was negative. This is the same as the optimization in
13986 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13987 // we must be careful to do the computation in x87 extended precision, not
13988 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13989 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13990 MachineMemOperand *MMO =
13991 DAG.getMachineFunction()
13992 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13993 MachineMemOperand::MOLoad, 8, 8);
13995 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13996 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13997 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
14000 APInt FF(32, 0x5F800000ULL);
14002 // Check whether the sign bit is set.
14003 SDValue SignSet = DAG.getSetCC(dl,
14004 getSetCCResultType(*DAG.getContext(), MVT::i64),
14005 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14008 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14009 SDValue FudgePtr = DAG.getConstantPool(
14010 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14013 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14014 SDValue Zero = DAG.getIntPtrConstant(0);
14015 SDValue Four = DAG.getIntPtrConstant(4);
14016 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14018 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14020 // Load the value out, extending it from f32 to f80.
14021 // FIXME: Avoid the extend by constructing the right constant pool?
14022 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14023 FudgePtr, MachinePointerInfo::getConstantPool(),
14024 MVT::f32, false, false, false, 4);
14025 // Extend everything to 80 bits to force it to be done on x87.
14026 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14027 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14030 std::pair<SDValue,SDValue>
14031 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14032 bool IsSigned, bool IsReplace) const {
14035 EVT DstTy = Op.getValueType();
14037 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14038 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14042 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14043 DstTy.getSimpleVT() >= MVT::i16 &&
14044 "Unknown FP_TO_INT to lower!");
14046 // These are really Legal.
14047 if (DstTy == MVT::i32 &&
14048 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14049 return std::make_pair(SDValue(), SDValue());
14050 if (Subtarget->is64Bit() &&
14051 DstTy == MVT::i64 &&
14052 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14053 return std::make_pair(SDValue(), SDValue());
14055 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14056 // stack slot, or into the FTOL runtime function.
14057 MachineFunction &MF = DAG.getMachineFunction();
14058 unsigned MemSize = DstTy.getSizeInBits()/8;
14059 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14060 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14063 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14064 Opc = X86ISD::WIN_FTOL;
14066 switch (DstTy.getSimpleVT().SimpleTy) {
14067 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14068 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14069 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14070 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14073 SDValue Chain = DAG.getEntryNode();
14074 SDValue Value = Op.getOperand(0);
14075 EVT TheVT = Op.getOperand(0).getValueType();
14076 // FIXME This causes a redundant load/store if the SSE-class value is already
14077 // in memory, such as if it is on the callstack.
14078 if (isScalarFPTypeInSSEReg(TheVT)) {
14079 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14080 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14081 MachinePointerInfo::getFixedStack(SSFI),
14083 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14085 Chain, StackSlot, DAG.getValueType(TheVT)
14088 MachineMemOperand *MMO =
14089 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14090 MachineMemOperand::MOLoad, MemSize, MemSize);
14091 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14092 Chain = Value.getValue(1);
14093 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14094 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14097 MachineMemOperand *MMO =
14098 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14099 MachineMemOperand::MOStore, MemSize, MemSize);
14101 if (Opc != X86ISD::WIN_FTOL) {
14102 // Build the FP_TO_INT*_IN_MEM
14103 SDValue Ops[] = { Chain, Value, StackSlot };
14104 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14106 return std::make_pair(FIST, StackSlot);
14108 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14109 DAG.getVTList(MVT::Other, MVT::Glue),
14111 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14112 MVT::i32, ftol.getValue(1));
14113 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14114 MVT::i32, eax.getValue(2));
14115 SDValue Ops[] = { eax, edx };
14116 SDValue pair = IsReplace
14117 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14118 : DAG.getMergeValues(Ops, DL);
14119 return std::make_pair(pair, SDValue());
14123 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14124 const X86Subtarget *Subtarget) {
14125 MVT VT = Op->getSimpleValueType(0);
14126 SDValue In = Op->getOperand(0);
14127 MVT InVT = In.getSimpleValueType();
14130 // Optimize vectors in AVX mode:
14133 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14134 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14135 // Concat upper and lower parts.
14138 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14139 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14140 // Concat upper and lower parts.
14143 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14144 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14145 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14148 if (Subtarget->hasInt256())
14149 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14151 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14152 SDValue Undef = DAG.getUNDEF(InVT);
14153 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14154 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14155 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14157 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14158 VT.getVectorNumElements()/2);
14160 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14161 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14163 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14166 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14167 SelectionDAG &DAG) {
14168 MVT VT = Op->getSimpleValueType(0);
14169 SDValue In = Op->getOperand(0);
14170 MVT InVT = In.getSimpleValueType();
14172 unsigned int NumElts = VT.getVectorNumElements();
14173 if (NumElts != 8 && NumElts != 16)
14176 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14177 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14179 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14180 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14181 // Now we have only mask extension
14182 assert(InVT.getVectorElementType() == MVT::i1);
14183 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14184 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14185 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14186 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14187 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14188 MachinePointerInfo::getConstantPool(),
14189 false, false, false, Alignment);
14191 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14192 if (VT.is512BitVector())
14194 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14197 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14198 SelectionDAG &DAG) {
14199 if (Subtarget->hasFp256()) {
14200 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14208 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14209 SelectionDAG &DAG) {
14211 MVT VT = Op.getSimpleValueType();
14212 SDValue In = Op.getOperand(0);
14213 MVT SVT = In.getSimpleValueType();
14215 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14216 return LowerZERO_EXTEND_AVX512(Op, DAG);
14218 if (Subtarget->hasFp256()) {
14219 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14224 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14225 VT.getVectorNumElements() != SVT.getVectorNumElements());
14229 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14231 MVT VT = Op.getSimpleValueType();
14232 SDValue In = Op.getOperand(0);
14233 MVT InVT = In.getSimpleValueType();
14235 if (VT == MVT::i1) {
14236 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14237 "Invalid scalar TRUNCATE operation");
14238 if (InVT.getSizeInBits() >= 32)
14240 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14241 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14243 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14244 "Invalid TRUNCATE operation");
14246 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14247 if (VT.getVectorElementType().getSizeInBits() >=8)
14248 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14250 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14251 unsigned NumElts = InVT.getVectorNumElements();
14252 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14253 if (InVT.getSizeInBits() < 512) {
14254 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14255 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14259 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14260 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14261 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14262 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14263 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14264 MachinePointerInfo::getConstantPool(),
14265 false, false, false, Alignment);
14266 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14267 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14268 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14271 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14272 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14273 if (Subtarget->hasInt256()) {
14274 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14275 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14276 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14279 DAG.getIntPtrConstant(0));
14282 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14283 DAG.getIntPtrConstant(0));
14284 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14285 DAG.getIntPtrConstant(2));
14286 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14287 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14288 static const int ShufMask[] = {0, 2, 4, 6};
14289 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14292 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14293 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14294 if (Subtarget->hasInt256()) {
14295 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14297 SmallVector<SDValue,32> pshufbMask;
14298 for (unsigned i = 0; i < 2; ++i) {
14299 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14300 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14301 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14302 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14303 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14304 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14305 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14306 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14307 for (unsigned j = 0; j < 8; ++j)
14308 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14310 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14311 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14312 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14314 static const int ShufMask[] = {0, 2, -1, -1};
14315 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14317 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14318 DAG.getIntPtrConstant(0));
14319 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14322 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14323 DAG.getIntPtrConstant(0));
14325 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14326 DAG.getIntPtrConstant(4));
14328 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14329 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14331 // The PSHUFB mask:
14332 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14333 -1, -1, -1, -1, -1, -1, -1, -1};
14335 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14336 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14337 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14339 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14340 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14342 // The MOVLHPS Mask:
14343 static const int ShufMask2[] = {0, 1, 4, 5};
14344 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14345 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14348 // Handle truncation of V256 to V128 using shuffles.
14349 if (!VT.is128BitVector() || !InVT.is256BitVector())
14352 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14354 unsigned NumElems = VT.getVectorNumElements();
14355 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14357 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14358 // Prepare truncation shuffle mask
14359 for (unsigned i = 0; i != NumElems; ++i)
14360 MaskVec[i] = i * 2;
14361 SDValue V = DAG.getVectorShuffle(NVT, DL,
14362 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14363 DAG.getUNDEF(NVT), &MaskVec[0]);
14364 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14365 DAG.getIntPtrConstant(0));
14368 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14369 SelectionDAG &DAG) const {
14370 assert(!Op.getSimpleValueType().isVector());
14372 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14373 /*IsSigned=*/ true, /*IsReplace=*/ false);
14374 SDValue FIST = Vals.first, StackSlot = Vals.second;
14375 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14376 if (!FIST.getNode()) return Op;
14378 if (StackSlot.getNode())
14379 // Load the result.
14380 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14381 FIST, StackSlot, MachinePointerInfo(),
14382 false, false, false, 0);
14384 // The node is the result.
14388 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14389 SelectionDAG &DAG) const {
14390 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14391 /*IsSigned=*/ false, /*IsReplace=*/ false);
14392 SDValue FIST = Vals.first, StackSlot = Vals.second;
14393 assert(FIST.getNode() && "Unexpected failure");
14395 if (StackSlot.getNode())
14396 // Load the result.
14397 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14398 FIST, StackSlot, MachinePointerInfo(),
14399 false, false, false, 0);
14401 // The node is the result.
14405 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14407 MVT VT = Op.getSimpleValueType();
14408 SDValue In = Op.getOperand(0);
14409 MVT SVT = In.getSimpleValueType();
14411 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14413 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14414 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14415 In, DAG.getUNDEF(SVT)));
14418 /// The only differences between FABS and FNEG are the mask and the logic op.
14419 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14420 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14421 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14422 "Wrong opcode for lowering FABS or FNEG.");
14424 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14426 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14427 // into an FNABS. We'll lower the FABS after that if it is still in use.
14429 for (SDNode *User : Op->uses())
14430 if (User->getOpcode() == ISD::FNEG)
14433 SDValue Op0 = Op.getOperand(0);
14434 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14437 MVT VT = Op.getSimpleValueType();
14438 // Assume scalar op for initialization; update for vector if needed.
14439 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14440 // generate a 16-byte vector constant and logic op even for the scalar case.
14441 // Using a 16-byte mask allows folding the load of the mask with
14442 // the logic op, so it can save (~4 bytes) on code size.
14444 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14445 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14446 // decide if we should generate a 16-byte constant mask when we only need 4 or
14447 // 8 bytes for the scalar case.
14448 if (VT.isVector()) {
14449 EltVT = VT.getVectorElementType();
14450 NumElts = VT.getVectorNumElements();
14453 unsigned EltBits = EltVT.getSizeInBits();
14454 LLVMContext *Context = DAG.getContext();
14455 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14457 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14458 Constant *C = ConstantInt::get(*Context, MaskElt);
14459 C = ConstantVector::getSplat(NumElts, C);
14460 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14461 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14462 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14463 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14464 MachinePointerInfo::getConstantPool(),
14465 false, false, false, Alignment);
14467 if (VT.isVector()) {
14468 // For a vector, cast operands to a vector type, perform the logic op,
14469 // and cast the result back to the original value type.
14470 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14471 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14472 SDValue Operand = IsFNABS ?
14473 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14474 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14475 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14476 return DAG.getNode(ISD::BITCAST, dl, VT,
14477 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14480 // If not vector, then scalar.
14481 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14482 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14483 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14486 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14487 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14488 LLVMContext *Context = DAG.getContext();
14489 SDValue Op0 = Op.getOperand(0);
14490 SDValue Op1 = Op.getOperand(1);
14492 MVT VT = Op.getSimpleValueType();
14493 MVT SrcVT = Op1.getSimpleValueType();
14495 // If second operand is smaller, extend it first.
14496 if (SrcVT.bitsLT(VT)) {
14497 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14500 // And if it is bigger, shrink it first.
14501 if (SrcVT.bitsGT(VT)) {
14502 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14506 // At this point the operands and the result should have the same
14507 // type, and that won't be f80 since that is not custom lowered.
14509 const fltSemantics &Sem =
14510 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14511 const unsigned SizeInBits = VT.getSizeInBits();
14513 SmallVector<Constant *, 4> CV(
14514 VT == MVT::f64 ? 2 : 4,
14515 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14517 // First, clear all bits but the sign bit from the second operand (sign).
14518 CV[0] = ConstantFP::get(*Context,
14519 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14520 Constant *C = ConstantVector::get(CV);
14521 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14522 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14523 MachinePointerInfo::getConstantPool(),
14524 false, false, false, 16);
14525 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14527 // Next, clear the sign bit from the first operand (magnitude).
14528 CV[0] = ConstantFP::get(
14529 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14530 C = ConstantVector::get(CV);
14531 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14532 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14533 MachinePointerInfo::getConstantPool(),
14534 false, false, false, 16);
14535 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14537 // OR the magnitude value with the sign bit.
14538 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14541 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14542 SDValue N0 = Op.getOperand(0);
14544 MVT VT = Op.getSimpleValueType();
14546 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14547 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14548 DAG.getConstant(1, VT));
14549 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14552 // Check whether an OR'd tree is PTEST-able.
14553 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14554 SelectionDAG &DAG) {
14555 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14557 if (!Subtarget->hasSSE41())
14560 if (!Op->hasOneUse())
14563 SDNode *N = Op.getNode();
14566 SmallVector<SDValue, 8> Opnds;
14567 DenseMap<SDValue, unsigned> VecInMap;
14568 SmallVector<SDValue, 8> VecIns;
14569 EVT VT = MVT::Other;
14571 // Recognize a special case where a vector is casted into wide integer to
14573 Opnds.push_back(N->getOperand(0));
14574 Opnds.push_back(N->getOperand(1));
14576 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14577 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14578 // BFS traverse all OR'd operands.
14579 if (I->getOpcode() == ISD::OR) {
14580 Opnds.push_back(I->getOperand(0));
14581 Opnds.push_back(I->getOperand(1));
14582 // Re-evaluate the number of nodes to be traversed.
14583 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14587 // Quit if a non-EXTRACT_VECTOR_ELT
14588 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14591 // Quit if without a constant index.
14592 SDValue Idx = I->getOperand(1);
14593 if (!isa<ConstantSDNode>(Idx))
14596 SDValue ExtractedFromVec = I->getOperand(0);
14597 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14598 if (M == VecInMap.end()) {
14599 VT = ExtractedFromVec.getValueType();
14600 // Quit if not 128/256-bit vector.
14601 if (!VT.is128BitVector() && !VT.is256BitVector())
14603 // Quit if not the same type.
14604 if (VecInMap.begin() != VecInMap.end() &&
14605 VT != VecInMap.begin()->first.getValueType())
14607 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14608 VecIns.push_back(ExtractedFromVec);
14610 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14613 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14614 "Not extracted from 128-/256-bit vector.");
14616 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14618 for (DenseMap<SDValue, unsigned>::const_iterator
14619 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14620 // Quit if not all elements are used.
14621 if (I->second != FullMask)
14625 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14627 // Cast all vectors into TestVT for PTEST.
14628 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14629 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14631 // If more than one full vectors are evaluated, OR them first before PTEST.
14632 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14633 // Each iteration will OR 2 nodes and append the result until there is only
14634 // 1 node left, i.e. the final OR'd value of all vectors.
14635 SDValue LHS = VecIns[Slot];
14636 SDValue RHS = VecIns[Slot + 1];
14637 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14640 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14641 VecIns.back(), VecIns.back());
14644 /// \brief return true if \c Op has a use that doesn't just read flags.
14645 static bool hasNonFlagsUse(SDValue Op) {
14646 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14648 SDNode *User = *UI;
14649 unsigned UOpNo = UI.getOperandNo();
14650 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14651 // Look pass truncate.
14652 UOpNo = User->use_begin().getOperandNo();
14653 User = *User->use_begin();
14656 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14657 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14663 /// Emit nodes that will be selected as "test Op0,Op0", or something
14665 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14666 SelectionDAG &DAG) const {
14667 if (Op.getValueType() == MVT::i1)
14668 // KORTEST instruction should be selected
14669 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14670 DAG.getConstant(0, Op.getValueType()));
14672 // CF and OF aren't always set the way we want. Determine which
14673 // of these we need.
14674 bool NeedCF = false;
14675 bool NeedOF = false;
14678 case X86::COND_A: case X86::COND_AE:
14679 case X86::COND_B: case X86::COND_BE:
14682 case X86::COND_G: case X86::COND_GE:
14683 case X86::COND_L: case X86::COND_LE:
14684 case X86::COND_O: case X86::COND_NO: {
14685 // Check if we really need to set the
14686 // Overflow flag. If NoSignedWrap is present
14687 // that is not actually needed.
14688 switch (Op->getOpcode()) {
14693 const BinaryWithFlagsSDNode *BinNode =
14694 cast<BinaryWithFlagsSDNode>(Op.getNode());
14695 if (BinNode->hasNoSignedWrap())
14705 // See if we can use the EFLAGS value from the operand instead of
14706 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14707 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14708 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14709 // Emit a CMP with 0, which is the TEST pattern.
14710 //if (Op.getValueType() == MVT::i1)
14711 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14712 // DAG.getConstant(0, MVT::i1));
14713 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14714 DAG.getConstant(0, Op.getValueType()));
14716 unsigned Opcode = 0;
14717 unsigned NumOperands = 0;
14719 // Truncate operations may prevent the merge of the SETCC instruction
14720 // and the arithmetic instruction before it. Attempt to truncate the operands
14721 // of the arithmetic instruction and use a reduced bit-width instruction.
14722 bool NeedTruncation = false;
14723 SDValue ArithOp = Op;
14724 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14725 SDValue Arith = Op->getOperand(0);
14726 // Both the trunc and the arithmetic op need to have one user each.
14727 if (Arith->hasOneUse())
14728 switch (Arith.getOpcode()) {
14735 NeedTruncation = true;
14741 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14742 // which may be the result of a CAST. We use the variable 'Op', which is the
14743 // non-casted variable when we check for possible users.
14744 switch (ArithOp.getOpcode()) {
14746 // Due to an isel shortcoming, be conservative if this add is likely to be
14747 // selected as part of a load-modify-store instruction. When the root node
14748 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14749 // uses of other nodes in the match, such as the ADD in this case. This
14750 // leads to the ADD being left around and reselected, with the result being
14751 // two adds in the output. Alas, even if none our users are stores, that
14752 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14753 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14754 // climbing the DAG back to the root, and it doesn't seem to be worth the
14756 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14757 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14758 if (UI->getOpcode() != ISD::CopyToReg &&
14759 UI->getOpcode() != ISD::SETCC &&
14760 UI->getOpcode() != ISD::STORE)
14763 if (ConstantSDNode *C =
14764 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14765 // An add of one will be selected as an INC.
14766 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14767 Opcode = X86ISD::INC;
14772 // An add of negative one (subtract of one) will be selected as a DEC.
14773 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14774 Opcode = X86ISD::DEC;
14780 // Otherwise use a regular EFLAGS-setting add.
14781 Opcode = X86ISD::ADD;
14786 // If we have a constant logical shift that's only used in a comparison
14787 // against zero turn it into an equivalent AND. This allows turning it into
14788 // a TEST instruction later.
14789 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14790 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14791 EVT VT = Op.getValueType();
14792 unsigned BitWidth = VT.getSizeInBits();
14793 unsigned ShAmt = Op->getConstantOperandVal(1);
14794 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14796 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14797 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14798 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14799 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14801 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14802 DAG.getConstant(Mask, VT));
14803 DAG.ReplaceAllUsesWith(Op, New);
14809 // If the primary and result isn't used, don't bother using X86ISD::AND,
14810 // because a TEST instruction will be better.
14811 if (!hasNonFlagsUse(Op))
14817 // Due to the ISEL shortcoming noted above, be conservative if this op is
14818 // likely to be selected as part of a load-modify-store instruction.
14819 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14820 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14821 if (UI->getOpcode() == ISD::STORE)
14824 // Otherwise use a regular EFLAGS-setting instruction.
14825 switch (ArithOp.getOpcode()) {
14826 default: llvm_unreachable("unexpected operator!");
14827 case ISD::SUB: Opcode = X86ISD::SUB; break;
14828 case ISD::XOR: Opcode = X86ISD::XOR; break;
14829 case ISD::AND: Opcode = X86ISD::AND; break;
14831 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14832 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14833 if (EFLAGS.getNode())
14836 Opcode = X86ISD::OR;
14850 return SDValue(Op.getNode(), 1);
14856 // If we found that truncation is beneficial, perform the truncation and
14858 if (NeedTruncation) {
14859 EVT VT = Op.getValueType();
14860 SDValue WideVal = Op->getOperand(0);
14861 EVT WideVT = WideVal.getValueType();
14862 unsigned ConvertedOp = 0;
14863 // Use a target machine opcode to prevent further DAGCombine
14864 // optimizations that may separate the arithmetic operations
14865 // from the setcc node.
14866 switch (WideVal.getOpcode()) {
14868 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14869 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14870 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14871 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14872 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14876 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14877 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14878 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14879 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14880 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14886 // Emit a CMP with 0, which is the TEST pattern.
14887 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14888 DAG.getConstant(0, Op.getValueType()));
14890 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14891 SmallVector<SDValue, 4> Ops;
14892 for (unsigned i = 0; i != NumOperands; ++i)
14893 Ops.push_back(Op.getOperand(i));
14895 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14896 DAG.ReplaceAllUsesWith(Op, New);
14897 return SDValue(New.getNode(), 1);
14900 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14902 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14903 SDLoc dl, SelectionDAG &DAG) const {
14904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14905 if (C->getAPIntValue() == 0)
14906 return EmitTest(Op0, X86CC, dl, DAG);
14908 if (Op0.getValueType() == MVT::i1)
14909 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14912 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14913 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14914 // Do the comparison at i32 if it's smaller, besides the Atom case.
14915 // This avoids subregister aliasing issues. Keep the smaller reference
14916 // if we're optimizing for size, however, as that'll allow better folding
14917 // of memory operations.
14918 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14919 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14920 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14921 !Subtarget->isAtom()) {
14922 unsigned ExtendOp =
14923 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14924 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14925 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14927 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14928 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14929 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14931 return SDValue(Sub.getNode(), 1);
14933 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14936 /// Convert a comparison if required by the subtarget.
14937 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14938 SelectionDAG &DAG) const {
14939 // If the subtarget does not support the FUCOMI instruction, floating-point
14940 // comparisons have to be converted.
14941 if (Subtarget->hasCMov() ||
14942 Cmp.getOpcode() != X86ISD::CMP ||
14943 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14944 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14947 // The instruction selector will select an FUCOM instruction instead of
14948 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14949 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14950 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14952 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14953 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14954 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14955 DAG.getConstant(8, MVT::i8));
14956 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14957 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14960 /// The minimum architected relative accuracy is 2^-12. We need one
14961 /// Newton-Raphson step to have a good float result (24 bits of precision).
14962 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14963 DAGCombinerInfo &DCI,
14964 unsigned &RefinementSteps,
14965 bool &UseOneConstNR) const {
14966 // FIXME: We should use instruction latency models to calculate the cost of
14967 // each potential sequence, but this is very hard to do reliably because
14968 // at least Intel's Core* chips have variable timing based on the number of
14969 // significant digits in the divisor and/or sqrt operand.
14970 if (!Subtarget->useSqrtEst())
14973 EVT VT = Op.getValueType();
14975 // SSE1 has rsqrtss and rsqrtps.
14976 // TODO: Add support for AVX512 (v16f32).
14977 // It is likely not profitable to do this for f64 because a double-precision
14978 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14979 // instructions: convert to single, rsqrtss, convert back to double, refine
14980 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14981 // along with FMA, this could be a throughput win.
14982 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14983 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14984 RefinementSteps = 1;
14985 UseOneConstNR = false;
14986 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14991 /// The minimum architected relative accuracy is 2^-12. We need one
14992 /// Newton-Raphson step to have a good float result (24 bits of precision).
14993 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14994 DAGCombinerInfo &DCI,
14995 unsigned &RefinementSteps) const {
14996 // FIXME: We should use instruction latency models to calculate the cost of
14997 // each potential sequence, but this is very hard to do reliably because
14998 // at least Intel's Core* chips have variable timing based on the number of
14999 // significant digits in the divisor.
15000 if (!Subtarget->useReciprocalEst())
15003 EVT VT = Op.getValueType();
15005 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15006 // TODO: Add support for AVX512 (v16f32).
15007 // It is likely not profitable to do this for f64 because a double-precision
15008 // reciprocal estimate with refinement on x86 prior to FMA requires
15009 // 15 instructions: convert to single, rcpss, convert back to double, refine
15010 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15011 // along with FMA, this could be a throughput win.
15012 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15013 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15014 RefinementSteps = ReciprocalEstimateRefinementSteps;
15015 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15020 static bool isAllOnes(SDValue V) {
15021 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15022 return C && C->isAllOnesValue();
15025 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15026 /// if it's possible.
15027 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15028 SDLoc dl, SelectionDAG &DAG) const {
15029 SDValue Op0 = And.getOperand(0);
15030 SDValue Op1 = And.getOperand(1);
15031 if (Op0.getOpcode() == ISD::TRUNCATE)
15032 Op0 = Op0.getOperand(0);
15033 if (Op1.getOpcode() == ISD::TRUNCATE)
15034 Op1 = Op1.getOperand(0);
15037 if (Op1.getOpcode() == ISD::SHL)
15038 std::swap(Op0, Op1);
15039 if (Op0.getOpcode() == ISD::SHL) {
15040 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15041 if (And00C->getZExtValue() == 1) {
15042 // If we looked past a truncate, check that it's only truncating away
15044 unsigned BitWidth = Op0.getValueSizeInBits();
15045 unsigned AndBitWidth = And.getValueSizeInBits();
15046 if (BitWidth > AndBitWidth) {
15048 DAG.computeKnownBits(Op0, Zeros, Ones);
15049 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15053 RHS = Op0.getOperand(1);
15055 } else if (Op1.getOpcode() == ISD::Constant) {
15056 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15057 uint64_t AndRHSVal = AndRHS->getZExtValue();
15058 SDValue AndLHS = Op0;
15060 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15061 LHS = AndLHS.getOperand(0);
15062 RHS = AndLHS.getOperand(1);
15065 // Use BT if the immediate can't be encoded in a TEST instruction.
15066 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15068 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15072 if (LHS.getNode()) {
15073 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15074 // instruction. Since the shift amount is in-range-or-undefined, we know
15075 // that doing a bittest on the i32 value is ok. We extend to i32 because
15076 // the encoding for the i16 version is larger than the i32 version.
15077 // Also promote i16 to i32 for performance / code size reason.
15078 if (LHS.getValueType() == MVT::i8 ||
15079 LHS.getValueType() == MVT::i16)
15080 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15082 // If the operand types disagree, extend the shift amount to match. Since
15083 // BT ignores high bits (like shifts) we can use anyextend.
15084 if (LHS.getValueType() != RHS.getValueType())
15085 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15087 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15088 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15089 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15090 DAG.getConstant(Cond, MVT::i8), BT);
15096 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15098 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15103 // SSE Condition code mapping:
15112 switch (SetCCOpcode) {
15113 default: llvm_unreachable("Unexpected SETCC condition");
15115 case ISD::SETEQ: SSECC = 0; break;
15117 case ISD::SETGT: Swap = true; // Fallthrough
15119 case ISD::SETOLT: SSECC = 1; break;
15121 case ISD::SETGE: Swap = true; // Fallthrough
15123 case ISD::SETOLE: SSECC = 2; break;
15124 case ISD::SETUO: SSECC = 3; break;
15126 case ISD::SETNE: SSECC = 4; break;
15127 case ISD::SETULE: Swap = true; // Fallthrough
15128 case ISD::SETUGE: SSECC = 5; break;
15129 case ISD::SETULT: Swap = true; // Fallthrough
15130 case ISD::SETUGT: SSECC = 6; break;
15131 case ISD::SETO: SSECC = 7; break;
15133 case ISD::SETONE: SSECC = 8; break;
15136 std::swap(Op0, Op1);
15141 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15142 // ones, and then concatenate the result back.
15143 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15144 MVT VT = Op.getSimpleValueType();
15146 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15147 "Unsupported value type for operation");
15149 unsigned NumElems = VT.getVectorNumElements();
15151 SDValue CC = Op.getOperand(2);
15153 // Extract the LHS vectors
15154 SDValue LHS = Op.getOperand(0);
15155 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15156 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15158 // Extract the RHS vectors
15159 SDValue RHS = Op.getOperand(1);
15160 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15161 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15163 // Issue the operation on the smaller types and concatenate the result back
15164 MVT EltVT = VT.getVectorElementType();
15165 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15166 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15167 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15168 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15171 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15172 const X86Subtarget *Subtarget) {
15173 SDValue Op0 = Op.getOperand(0);
15174 SDValue Op1 = Op.getOperand(1);
15175 SDValue CC = Op.getOperand(2);
15176 MVT VT = Op.getSimpleValueType();
15179 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15180 Op.getValueType().getScalarType() == MVT::i1 &&
15181 "Cannot set masked compare for this operation");
15183 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15185 bool Unsigned = false;
15188 switch (SetCCOpcode) {
15189 default: llvm_unreachable("Unexpected SETCC condition");
15190 case ISD::SETNE: SSECC = 4; break;
15191 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15192 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15193 case ISD::SETLT: Swap = true; //fall-through
15194 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15195 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15196 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15197 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15198 case ISD::SETULE: Unsigned = true; //fall-through
15199 case ISD::SETLE: SSECC = 2; break;
15203 std::swap(Op0, Op1);
15205 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15206 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15207 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15208 DAG.getConstant(SSECC, MVT::i8));
15211 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15212 /// operand \p Op1. If non-trivial (for example because it's not constant)
15213 /// return an empty value.
15214 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15216 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15220 MVT VT = Op1.getSimpleValueType();
15221 MVT EVT = VT.getVectorElementType();
15222 unsigned n = VT.getVectorNumElements();
15223 SmallVector<SDValue, 8> ULTOp1;
15225 for (unsigned i = 0; i < n; ++i) {
15226 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15227 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15230 // Avoid underflow.
15231 APInt Val = Elt->getAPIntValue();
15235 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15238 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15241 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15242 SelectionDAG &DAG) {
15243 SDValue Op0 = Op.getOperand(0);
15244 SDValue Op1 = Op.getOperand(1);
15245 SDValue CC = Op.getOperand(2);
15246 MVT VT = Op.getSimpleValueType();
15247 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15248 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15253 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15254 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15257 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15258 unsigned Opc = X86ISD::CMPP;
15259 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15260 assert(VT.getVectorNumElements() <= 16);
15261 Opc = X86ISD::CMPM;
15263 // In the two special cases we can't handle, emit two comparisons.
15266 unsigned CombineOpc;
15267 if (SetCCOpcode == ISD::SETUEQ) {
15268 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15270 assert(SetCCOpcode == ISD::SETONE);
15271 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15274 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15275 DAG.getConstant(CC0, MVT::i8));
15276 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15277 DAG.getConstant(CC1, MVT::i8));
15278 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15280 // Handle all other FP comparisons here.
15281 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15282 DAG.getConstant(SSECC, MVT::i8));
15285 // Break 256-bit integer vector compare into smaller ones.
15286 if (VT.is256BitVector() && !Subtarget->hasInt256())
15287 return Lower256IntVSETCC(Op, DAG);
15289 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15290 EVT OpVT = Op1.getValueType();
15291 if (Subtarget->hasAVX512()) {
15292 if (Op1.getValueType().is512BitVector() ||
15293 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15294 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15295 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15297 // In AVX-512 architecture setcc returns mask with i1 elements,
15298 // But there is no compare instruction for i8 and i16 elements in KNL.
15299 // We are not talking about 512-bit operands in this case, these
15300 // types are illegal.
15302 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15303 OpVT.getVectorElementType().getSizeInBits() >= 8))
15304 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15305 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15308 // We are handling one of the integer comparisons here. Since SSE only has
15309 // GT and EQ comparisons for integer, swapping operands and multiple
15310 // operations may be required for some comparisons.
15312 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15313 bool Subus = false;
15315 switch (SetCCOpcode) {
15316 default: llvm_unreachable("Unexpected SETCC condition");
15317 case ISD::SETNE: Invert = true;
15318 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15319 case ISD::SETLT: Swap = true;
15320 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15321 case ISD::SETGE: Swap = true;
15322 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15323 Invert = true; break;
15324 case ISD::SETULT: Swap = true;
15325 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15326 FlipSigns = true; break;
15327 case ISD::SETUGE: Swap = true;
15328 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15329 FlipSigns = true; Invert = true; break;
15332 // Special case: Use min/max operations for SETULE/SETUGE
15333 MVT VET = VT.getVectorElementType();
15335 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15336 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15339 switch (SetCCOpcode) {
15341 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15342 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15345 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15348 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15349 if (!MinMax && hasSubus) {
15350 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15352 // t = psubus Op0, Op1
15353 // pcmpeq t, <0..0>
15354 switch (SetCCOpcode) {
15356 case ISD::SETULT: {
15357 // If the comparison is against a constant we can turn this into a
15358 // setule. With psubus, setule does not require a swap. This is
15359 // beneficial because the constant in the register is no longer
15360 // destructed as the destination so it can be hoisted out of a loop.
15361 // Only do this pre-AVX since vpcmp* is no longer destructive.
15362 if (Subtarget->hasAVX())
15364 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15365 if (ULEOp1.getNode()) {
15367 Subus = true; Invert = false; Swap = false;
15371 // Psubus is better than flip-sign because it requires no inversion.
15372 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15373 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15377 Opc = X86ISD::SUBUS;
15383 std::swap(Op0, Op1);
15385 // Check that the operation in question is available (most are plain SSE2,
15386 // but PCMPGTQ and PCMPEQQ have different requirements).
15387 if (VT == MVT::v2i64) {
15388 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15389 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15391 // First cast everything to the right type.
15392 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15393 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15395 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15396 // bits of the inputs before performing those operations. The lower
15397 // compare is always unsigned.
15400 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15402 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15403 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15404 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15405 Sign, Zero, Sign, Zero);
15407 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15408 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15410 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15411 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15412 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15414 // Create masks for only the low parts/high parts of the 64 bit integers.
15415 static const int MaskHi[] = { 1, 1, 3, 3 };
15416 static const int MaskLo[] = { 0, 0, 2, 2 };
15417 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15418 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15419 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15421 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15422 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15425 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15427 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15430 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15431 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15432 // pcmpeqd + pshufd + pand.
15433 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15435 // First cast everything to the right type.
15436 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15437 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15440 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15442 // Make sure the lower and upper halves are both all-ones.
15443 static const int Mask[] = { 1, 0, 3, 2 };
15444 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15445 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15448 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15450 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15454 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15455 // bits of the inputs before performing those operations.
15457 EVT EltVT = VT.getVectorElementType();
15458 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15459 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15460 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15463 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15465 // If the logical-not of the result is required, perform that now.
15467 Result = DAG.getNOT(dl, Result, VT);
15470 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15473 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15474 getZeroVector(VT, Subtarget, DAG, dl));
15479 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15481 MVT VT = Op.getSimpleValueType();
15483 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15485 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15486 && "SetCC type must be 8-bit or 1-bit integer");
15487 SDValue Op0 = Op.getOperand(0);
15488 SDValue Op1 = Op.getOperand(1);
15490 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15492 // Optimize to BT if possible.
15493 // Lower (X & (1 << N)) == 0 to BT(X, N).
15494 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15495 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15496 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15497 Op1.getOpcode() == ISD::Constant &&
15498 cast<ConstantSDNode>(Op1)->isNullValue() &&
15499 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15500 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15501 if (NewSetCC.getNode()) {
15503 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15508 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15510 if (Op1.getOpcode() == ISD::Constant &&
15511 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15512 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15513 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15515 // If the input is a setcc, then reuse the input setcc or use a new one with
15516 // the inverted condition.
15517 if (Op0.getOpcode() == X86ISD::SETCC) {
15518 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15519 bool Invert = (CC == ISD::SETNE) ^
15520 cast<ConstantSDNode>(Op1)->isNullValue();
15524 CCode = X86::GetOppositeBranchCondition(CCode);
15525 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15526 DAG.getConstant(CCode, MVT::i8),
15527 Op0.getOperand(1));
15529 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15533 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15534 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15535 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15537 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15538 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15541 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15542 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15543 if (X86CC == X86::COND_INVALID)
15546 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15547 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15548 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15549 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15551 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15555 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15556 static bool isX86LogicalCmp(SDValue Op) {
15557 unsigned Opc = Op.getNode()->getOpcode();
15558 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15559 Opc == X86ISD::SAHF)
15561 if (Op.getResNo() == 1 &&
15562 (Opc == X86ISD::ADD ||
15563 Opc == X86ISD::SUB ||
15564 Opc == X86ISD::ADC ||
15565 Opc == X86ISD::SBB ||
15566 Opc == X86ISD::SMUL ||
15567 Opc == X86ISD::UMUL ||
15568 Opc == X86ISD::INC ||
15569 Opc == X86ISD::DEC ||
15570 Opc == X86ISD::OR ||
15571 Opc == X86ISD::XOR ||
15572 Opc == X86ISD::AND))
15575 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15581 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15582 if (V.getOpcode() != ISD::TRUNCATE)
15585 SDValue VOp0 = V.getOperand(0);
15586 unsigned InBits = VOp0.getValueSizeInBits();
15587 unsigned Bits = V.getValueSizeInBits();
15588 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15591 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15592 bool addTest = true;
15593 SDValue Cond = Op.getOperand(0);
15594 SDValue Op1 = Op.getOperand(1);
15595 SDValue Op2 = Op.getOperand(2);
15597 EVT VT = Op1.getValueType();
15600 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15601 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15602 // sequence later on.
15603 if (Cond.getOpcode() == ISD::SETCC &&
15604 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15605 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15606 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15607 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15608 int SSECC = translateX86FSETCC(
15609 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15612 if (Subtarget->hasAVX512()) {
15613 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15614 DAG.getConstant(SSECC, MVT::i8));
15615 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15617 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15618 DAG.getConstant(SSECC, MVT::i8));
15619 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15620 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15621 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15625 if (Cond.getOpcode() == ISD::SETCC) {
15626 SDValue NewCond = LowerSETCC(Cond, DAG);
15627 if (NewCond.getNode())
15631 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15632 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15633 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15634 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15635 if (Cond.getOpcode() == X86ISD::SETCC &&
15636 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15637 isZero(Cond.getOperand(1).getOperand(1))) {
15638 SDValue Cmp = Cond.getOperand(1);
15640 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15642 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15643 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15644 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15646 SDValue CmpOp0 = Cmp.getOperand(0);
15647 // Apply further optimizations for special cases
15648 // (select (x != 0), -1, 0) -> neg & sbb
15649 // (select (x == 0), 0, -1) -> neg & sbb
15650 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15651 if (YC->isNullValue() &&
15652 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15653 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15654 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15655 DAG.getConstant(0, CmpOp0.getValueType()),
15657 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15658 DAG.getConstant(X86::COND_B, MVT::i8),
15659 SDValue(Neg.getNode(), 1));
15663 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15664 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15665 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15667 SDValue Res = // Res = 0 or -1.
15668 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15669 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15671 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15672 Res = DAG.getNOT(DL, Res, Res.getValueType());
15674 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15675 if (!N2C || !N2C->isNullValue())
15676 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15681 // Look past (and (setcc_carry (cmp ...)), 1).
15682 if (Cond.getOpcode() == ISD::AND &&
15683 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15684 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15685 if (C && C->getAPIntValue() == 1)
15686 Cond = Cond.getOperand(0);
15689 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15690 // setting operand in place of the X86ISD::SETCC.
15691 unsigned CondOpcode = Cond.getOpcode();
15692 if (CondOpcode == X86ISD::SETCC ||
15693 CondOpcode == X86ISD::SETCC_CARRY) {
15694 CC = Cond.getOperand(0);
15696 SDValue Cmp = Cond.getOperand(1);
15697 unsigned Opc = Cmp.getOpcode();
15698 MVT VT = Op.getSimpleValueType();
15700 bool IllegalFPCMov = false;
15701 if (VT.isFloatingPoint() && !VT.isVector() &&
15702 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15703 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15705 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15706 Opc == X86ISD::BT) { // FIXME
15710 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15711 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15712 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15713 Cond.getOperand(0).getValueType() != MVT::i8)) {
15714 SDValue LHS = Cond.getOperand(0);
15715 SDValue RHS = Cond.getOperand(1);
15716 unsigned X86Opcode;
15719 switch (CondOpcode) {
15720 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15721 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15722 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15723 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15724 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15725 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15726 default: llvm_unreachable("unexpected overflowing operator");
15728 if (CondOpcode == ISD::UMULO)
15729 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15732 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15734 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15736 if (CondOpcode == ISD::UMULO)
15737 Cond = X86Op.getValue(2);
15739 Cond = X86Op.getValue(1);
15741 CC = DAG.getConstant(X86Cond, MVT::i8);
15746 // Look pass the truncate if the high bits are known zero.
15747 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15748 Cond = Cond.getOperand(0);
15750 // We know the result of AND is compared against zero. Try to match
15752 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15753 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15754 if (NewSetCC.getNode()) {
15755 CC = NewSetCC.getOperand(0);
15756 Cond = NewSetCC.getOperand(1);
15763 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15764 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15767 // a < b ? -1 : 0 -> RES = ~setcc_carry
15768 // a < b ? 0 : -1 -> RES = setcc_carry
15769 // a >= b ? -1 : 0 -> RES = setcc_carry
15770 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15771 if (Cond.getOpcode() == X86ISD::SUB) {
15772 Cond = ConvertCmpIfNecessary(Cond, DAG);
15773 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15775 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15776 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15777 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15778 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15779 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15780 return DAG.getNOT(DL, Res, Res.getValueType());
15785 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15786 // widen the cmov and push the truncate through. This avoids introducing a new
15787 // branch during isel and doesn't add any extensions.
15788 if (Op.getValueType() == MVT::i8 &&
15789 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15790 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15791 if (T1.getValueType() == T2.getValueType() &&
15792 // Blacklist CopyFromReg to avoid partial register stalls.
15793 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15794 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15795 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15796 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15800 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15801 // condition is true.
15802 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15803 SDValue Ops[] = { Op2, Op1, CC, Cond };
15804 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15807 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15808 SelectionDAG &DAG) {
15809 MVT VT = Op->getSimpleValueType(0);
15810 SDValue In = Op->getOperand(0);
15811 MVT InVT = In.getSimpleValueType();
15812 MVT VTElt = VT.getVectorElementType();
15813 MVT InVTElt = InVT.getVectorElementType();
15817 if ((InVTElt == MVT::i1) &&
15818 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15819 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15821 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15822 VTElt.getSizeInBits() <= 16)) ||
15824 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15825 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15827 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15828 VTElt.getSizeInBits() >= 32))))
15829 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15831 unsigned int NumElts = VT.getVectorNumElements();
15833 if (NumElts != 8 && NumElts != 16)
15836 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15837 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15838 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15839 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15842 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15843 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15845 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15846 Constant *C = ConstantInt::get(*DAG.getContext(),
15847 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15849 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15850 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15851 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15852 MachinePointerInfo::getConstantPool(),
15853 false, false, false, Alignment);
15854 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15855 if (VT.is512BitVector())
15857 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15860 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15861 SelectionDAG &DAG) {
15862 MVT VT = Op->getSimpleValueType(0);
15863 SDValue In = Op->getOperand(0);
15864 MVT InVT = In.getSimpleValueType();
15867 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15868 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15870 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15871 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15872 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15875 if (Subtarget->hasInt256())
15876 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15878 // Optimize vectors in AVX mode
15879 // Sign extend v8i16 to v8i32 and
15882 // Divide input vector into two parts
15883 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15884 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15885 // concat the vectors to original VT
15887 unsigned NumElems = InVT.getVectorNumElements();
15888 SDValue Undef = DAG.getUNDEF(InVT);
15890 SmallVector<int,8> ShufMask1(NumElems, -1);
15891 for (unsigned i = 0; i != NumElems/2; ++i)
15894 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15896 SmallVector<int,8> ShufMask2(NumElems, -1);
15897 for (unsigned i = 0; i != NumElems/2; ++i)
15898 ShufMask2[i] = i + NumElems/2;
15900 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15902 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15903 VT.getVectorNumElements()/2);
15905 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15906 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15908 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15911 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15912 // may emit an illegal shuffle but the expansion is still better than scalar
15913 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15914 // we'll emit a shuffle and a arithmetic shift.
15915 // TODO: It is possible to support ZExt by zeroing the undef values during
15916 // the shuffle phase or after the shuffle.
15917 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15918 SelectionDAG &DAG) {
15919 MVT RegVT = Op.getSimpleValueType();
15920 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15921 assert(RegVT.isInteger() &&
15922 "We only custom lower integer vector sext loads.");
15924 // Nothing useful we can do without SSE2 shuffles.
15925 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15927 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15929 EVT MemVT = Ld->getMemoryVT();
15930 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15931 unsigned RegSz = RegVT.getSizeInBits();
15933 ISD::LoadExtType Ext = Ld->getExtensionType();
15935 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15936 && "Only anyext and sext are currently implemented.");
15937 assert(MemVT != RegVT && "Cannot extend to the same type");
15938 assert(MemVT.isVector() && "Must load a vector from memory");
15940 unsigned NumElems = RegVT.getVectorNumElements();
15941 unsigned MemSz = MemVT.getSizeInBits();
15942 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15944 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15945 // The only way in which we have a legal 256-bit vector result but not the
15946 // integer 256-bit operations needed to directly lower a sextload is if we
15947 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15948 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15949 // correctly legalized. We do this late to allow the canonical form of
15950 // sextload to persist throughout the rest of the DAG combiner -- it wants
15951 // to fold together any extensions it can, and so will fuse a sign_extend
15952 // of an sextload into a sextload targeting a wider value.
15954 if (MemSz == 128) {
15955 // Just switch this to a normal load.
15956 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15957 "it must be a legal 128-bit vector "
15959 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15960 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15961 Ld->isInvariant(), Ld->getAlignment());
15963 assert(MemSz < 128 &&
15964 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15965 // Do an sext load to a 128-bit vector type. We want to use the same
15966 // number of elements, but elements half as wide. This will end up being
15967 // recursively lowered by this routine, but will succeed as we definitely
15968 // have all the necessary features if we're using AVX1.
15970 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15971 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15973 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15974 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15975 Ld->isNonTemporal(), Ld->isInvariant(),
15976 Ld->getAlignment());
15979 // Replace chain users with the new chain.
15980 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15981 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15983 // Finally, do a normal sign-extend to the desired register.
15984 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15987 // All sizes must be a power of two.
15988 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15989 "Non-power-of-two elements are not custom lowered!");
15991 // Attempt to load the original value using scalar loads.
15992 // Find the largest scalar type that divides the total loaded size.
15993 MVT SclrLoadTy = MVT::i8;
15994 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15995 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15996 MVT Tp = (MVT::SimpleValueType)tp;
15997 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16002 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16003 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16005 SclrLoadTy = MVT::f64;
16007 // Calculate the number of scalar loads that we need to perform
16008 // in order to load our vector from memory.
16009 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16011 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16012 "Can only lower sext loads with a single scalar load!");
16014 unsigned loadRegZize = RegSz;
16015 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16018 // Represent our vector as a sequence of elements which are the
16019 // largest scalar that we can load.
16020 EVT LoadUnitVecVT = EVT::getVectorVT(
16021 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16023 // Represent the data using the same element type that is stored in
16024 // memory. In practice, we ''widen'' MemVT.
16026 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16027 loadRegZize / MemVT.getScalarType().getSizeInBits());
16029 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16030 "Invalid vector type");
16032 // We can't shuffle using an illegal type.
16033 assert(TLI.isTypeLegal(WideVecVT) &&
16034 "We only lower types that form legal widened vector types");
16036 SmallVector<SDValue, 8> Chains;
16037 SDValue Ptr = Ld->getBasePtr();
16038 SDValue Increment =
16039 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16040 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16042 for (unsigned i = 0; i < NumLoads; ++i) {
16043 // Perform a single load.
16044 SDValue ScalarLoad =
16045 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16046 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16047 Ld->getAlignment());
16048 Chains.push_back(ScalarLoad.getValue(1));
16049 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16050 // another round of DAGCombining.
16052 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16054 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16055 ScalarLoad, DAG.getIntPtrConstant(i));
16057 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16060 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16062 // Bitcast the loaded value to a vector of the original element type, in
16063 // the size of the target vector type.
16064 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16065 unsigned SizeRatio = RegSz / MemSz;
16067 if (Ext == ISD::SEXTLOAD) {
16068 // If we have SSE4.1, we can directly emit a VSEXT node.
16069 if (Subtarget->hasSSE41()) {
16070 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16071 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16075 // Otherwise we'll shuffle the small elements in the high bits of the
16076 // larger type and perform an arithmetic shift. If the shift is not legal
16077 // it's better to scalarize.
16078 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16079 "We can't implement a sext load without an arithmetic right shift!");
16081 // Redistribute the loaded elements into the different locations.
16082 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16083 for (unsigned i = 0; i != NumElems; ++i)
16084 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16086 SDValue Shuff = DAG.getVectorShuffle(
16087 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16089 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16091 // Build the arithmetic shift.
16092 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16093 MemVT.getVectorElementType().getSizeInBits();
16095 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16097 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16101 // Redistribute the loaded elements into the different locations.
16102 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16103 for (unsigned i = 0; i != NumElems; ++i)
16104 ShuffleVec[i * SizeRatio] = i;
16106 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16107 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16109 // Bitcast to the requested type.
16110 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16111 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16115 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16116 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16117 // from the AND / OR.
16118 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16119 Opc = Op.getOpcode();
16120 if (Opc != ISD::OR && Opc != ISD::AND)
16122 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16123 Op.getOperand(0).hasOneUse() &&
16124 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16125 Op.getOperand(1).hasOneUse());
16128 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16129 // 1 and that the SETCC node has a single use.
16130 static bool isXor1OfSetCC(SDValue Op) {
16131 if (Op.getOpcode() != ISD::XOR)
16133 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16134 if (N1C && N1C->getAPIntValue() == 1) {
16135 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16136 Op.getOperand(0).hasOneUse();
16141 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16142 bool addTest = true;
16143 SDValue Chain = Op.getOperand(0);
16144 SDValue Cond = Op.getOperand(1);
16145 SDValue Dest = Op.getOperand(2);
16148 bool Inverted = false;
16150 if (Cond.getOpcode() == ISD::SETCC) {
16151 // Check for setcc([su]{add,sub,mul}o == 0).
16152 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16153 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16154 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16155 Cond.getOperand(0).getResNo() == 1 &&
16156 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16157 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16158 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16159 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16160 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16161 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16163 Cond = Cond.getOperand(0);
16165 SDValue NewCond = LowerSETCC(Cond, DAG);
16166 if (NewCond.getNode())
16171 // FIXME: LowerXALUO doesn't handle these!!
16172 else if (Cond.getOpcode() == X86ISD::ADD ||
16173 Cond.getOpcode() == X86ISD::SUB ||
16174 Cond.getOpcode() == X86ISD::SMUL ||
16175 Cond.getOpcode() == X86ISD::UMUL)
16176 Cond = LowerXALUO(Cond, DAG);
16179 // Look pass (and (setcc_carry (cmp ...)), 1).
16180 if (Cond.getOpcode() == ISD::AND &&
16181 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16182 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16183 if (C && C->getAPIntValue() == 1)
16184 Cond = Cond.getOperand(0);
16187 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16188 // setting operand in place of the X86ISD::SETCC.
16189 unsigned CondOpcode = Cond.getOpcode();
16190 if (CondOpcode == X86ISD::SETCC ||
16191 CondOpcode == X86ISD::SETCC_CARRY) {
16192 CC = Cond.getOperand(0);
16194 SDValue Cmp = Cond.getOperand(1);
16195 unsigned Opc = Cmp.getOpcode();
16196 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16197 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16201 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16205 // These can only come from an arithmetic instruction with overflow,
16206 // e.g. SADDO, UADDO.
16207 Cond = Cond.getNode()->getOperand(1);
16213 CondOpcode = Cond.getOpcode();
16214 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16215 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16216 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16217 Cond.getOperand(0).getValueType() != MVT::i8)) {
16218 SDValue LHS = Cond.getOperand(0);
16219 SDValue RHS = Cond.getOperand(1);
16220 unsigned X86Opcode;
16223 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16224 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16226 switch (CondOpcode) {
16227 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16231 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16234 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16235 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16239 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16242 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16243 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16244 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16245 default: llvm_unreachable("unexpected overflowing operator");
16248 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16249 if (CondOpcode == ISD::UMULO)
16250 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16253 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16255 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16257 if (CondOpcode == ISD::UMULO)
16258 Cond = X86Op.getValue(2);
16260 Cond = X86Op.getValue(1);
16262 CC = DAG.getConstant(X86Cond, MVT::i8);
16266 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16267 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16268 if (CondOpc == ISD::OR) {
16269 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16270 // two branches instead of an explicit OR instruction with a
16272 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16273 isX86LogicalCmp(Cmp)) {
16274 CC = Cond.getOperand(0).getOperand(0);
16275 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16276 Chain, Dest, CC, Cmp);
16277 CC = Cond.getOperand(1).getOperand(0);
16281 } else { // ISD::AND
16282 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16283 // two branches instead of an explicit AND instruction with a
16284 // separate test. However, we only do this if this block doesn't
16285 // have a fall-through edge, because this requires an explicit
16286 // jmp when the condition is false.
16287 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16288 isX86LogicalCmp(Cmp) &&
16289 Op.getNode()->hasOneUse()) {
16290 X86::CondCode CCode =
16291 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16292 CCode = X86::GetOppositeBranchCondition(CCode);
16293 CC = DAG.getConstant(CCode, MVT::i8);
16294 SDNode *User = *Op.getNode()->use_begin();
16295 // Look for an unconditional branch following this conditional branch.
16296 // We need this because we need to reverse the successors in order
16297 // to implement FCMP_OEQ.
16298 if (User->getOpcode() == ISD::BR) {
16299 SDValue FalseBB = User->getOperand(1);
16301 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16302 assert(NewBR == User);
16306 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16307 Chain, Dest, CC, Cmp);
16308 X86::CondCode CCode =
16309 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16310 CCode = X86::GetOppositeBranchCondition(CCode);
16311 CC = DAG.getConstant(CCode, MVT::i8);
16317 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16318 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16319 // It should be transformed during dag combiner except when the condition
16320 // is set by a arithmetics with overflow node.
16321 X86::CondCode CCode =
16322 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16323 CCode = X86::GetOppositeBranchCondition(CCode);
16324 CC = DAG.getConstant(CCode, MVT::i8);
16325 Cond = Cond.getOperand(0).getOperand(1);
16327 } else if (Cond.getOpcode() == ISD::SETCC &&
16328 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16329 // For FCMP_OEQ, we can emit
16330 // two branches instead of an explicit AND instruction with a
16331 // separate test. However, we only do this if this block doesn't
16332 // have a fall-through edge, because this requires an explicit
16333 // jmp when the condition is false.
16334 if (Op.getNode()->hasOneUse()) {
16335 SDNode *User = *Op.getNode()->use_begin();
16336 // Look for an unconditional branch following this conditional branch.
16337 // We need this because we need to reverse the successors in order
16338 // to implement FCMP_OEQ.
16339 if (User->getOpcode() == ISD::BR) {
16340 SDValue FalseBB = User->getOperand(1);
16342 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16343 assert(NewBR == User);
16347 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16348 Cond.getOperand(0), Cond.getOperand(1));
16349 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16350 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16351 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16352 Chain, Dest, CC, Cmp);
16353 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16358 } else if (Cond.getOpcode() == ISD::SETCC &&
16359 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16360 // For FCMP_UNE, we can emit
16361 // two branches instead of an explicit AND instruction with a
16362 // separate test. However, we only do this if this block doesn't
16363 // have a fall-through edge, because this requires an explicit
16364 // jmp when the condition is false.
16365 if (Op.getNode()->hasOneUse()) {
16366 SDNode *User = *Op.getNode()->use_begin();
16367 // Look for an unconditional branch following this conditional branch.
16368 // We need this because we need to reverse the successors in order
16369 // to implement FCMP_UNE.
16370 if (User->getOpcode() == ISD::BR) {
16371 SDValue FalseBB = User->getOperand(1);
16373 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16374 assert(NewBR == User);
16377 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16378 Cond.getOperand(0), Cond.getOperand(1));
16379 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16380 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16381 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16382 Chain, Dest, CC, Cmp);
16383 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16393 // Look pass the truncate if the high bits are known zero.
16394 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16395 Cond = Cond.getOperand(0);
16397 // We know the result of AND is compared against zero. Try to match
16399 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16400 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16401 if (NewSetCC.getNode()) {
16402 CC = NewSetCC.getOperand(0);
16403 Cond = NewSetCC.getOperand(1);
16410 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16411 CC = DAG.getConstant(X86Cond, MVT::i8);
16412 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16414 Cond = ConvertCmpIfNecessary(Cond, DAG);
16415 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16416 Chain, Dest, CC, Cond);
16419 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16420 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16421 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16422 // that the guard pages used by the OS virtual memory manager are allocated in
16423 // correct sequence.
16425 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16426 SelectionDAG &DAG) const {
16427 MachineFunction &MF = DAG.getMachineFunction();
16428 bool SplitStack = MF.shouldSplitStack();
16429 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16434 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16435 SDNode* Node = Op.getNode();
16437 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16438 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16439 " not tell us which reg is the stack pointer!");
16440 EVT VT = Node->getValueType(0);
16441 SDValue Tmp1 = SDValue(Node, 0);
16442 SDValue Tmp2 = SDValue(Node, 1);
16443 SDValue Tmp3 = Node->getOperand(2);
16444 SDValue Chain = Tmp1.getOperand(0);
16446 // Chain the dynamic stack allocation so that it doesn't modify the stack
16447 // pointer when other instructions are using the stack.
16448 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16451 SDValue Size = Tmp2.getOperand(1);
16452 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16453 Chain = SP.getValue(1);
16454 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16455 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16456 unsigned StackAlign = TFI.getStackAlignment();
16457 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16458 if (Align > StackAlign)
16459 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16460 DAG.getConstant(-(uint64_t)Align, VT));
16461 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16463 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16464 DAG.getIntPtrConstant(0, true), SDValue(),
16467 SDValue Ops[2] = { Tmp1, Tmp2 };
16468 return DAG.getMergeValues(Ops, dl);
16472 SDValue Chain = Op.getOperand(0);
16473 SDValue Size = Op.getOperand(1);
16474 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16475 EVT VT = Op.getNode()->getValueType(0);
16477 bool Is64Bit = Subtarget->is64Bit();
16478 EVT SPTy = getPointerTy();
16481 MachineRegisterInfo &MRI = MF.getRegInfo();
16484 // The 64 bit implementation of segmented stacks needs to clobber both r10
16485 // r11. This makes it impossible to use it along with nested parameters.
16486 const Function *F = MF.getFunction();
16488 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16490 if (I->hasNestAttr())
16491 report_fatal_error("Cannot use segmented stacks with functions that "
16492 "have nested arguments.");
16495 const TargetRegisterClass *AddrRegClass =
16496 getRegClassFor(getPointerTy());
16497 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16498 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16499 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16500 DAG.getRegister(Vreg, SPTy));
16501 SDValue Ops1[2] = { Value, Chain };
16502 return DAG.getMergeValues(Ops1, dl);
16505 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16507 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16508 Flag = Chain.getValue(1);
16509 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16511 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16513 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16514 DAG.getSubtarget().getRegisterInfo());
16515 unsigned SPReg = RegInfo->getStackRegister();
16516 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16517 Chain = SP.getValue(1);
16520 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16521 DAG.getConstant(-(uint64_t)Align, VT));
16522 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16525 SDValue Ops1[2] = { SP, Chain };
16526 return DAG.getMergeValues(Ops1, dl);
16530 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16531 MachineFunction &MF = DAG.getMachineFunction();
16532 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16534 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16537 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16538 // vastart just stores the address of the VarArgsFrameIndex slot into the
16539 // memory location argument.
16540 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16542 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16543 MachinePointerInfo(SV), false, false, 0);
16547 // gp_offset (0 - 6 * 8)
16548 // fp_offset (48 - 48 + 8 * 16)
16549 // overflow_arg_area (point to parameters coming in memory).
16551 SmallVector<SDValue, 8> MemOps;
16552 SDValue FIN = Op.getOperand(1);
16554 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16555 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16557 FIN, MachinePointerInfo(SV), false, false, 0);
16558 MemOps.push_back(Store);
16561 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16562 FIN, DAG.getIntPtrConstant(4));
16563 Store = DAG.getStore(Op.getOperand(0), DL,
16564 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16566 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16567 MemOps.push_back(Store);
16569 // Store ptr to overflow_arg_area
16570 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16571 FIN, DAG.getIntPtrConstant(4));
16572 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16574 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16575 MachinePointerInfo(SV, 8),
16577 MemOps.push_back(Store);
16579 // Store ptr to reg_save_area.
16580 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16581 FIN, DAG.getIntPtrConstant(8));
16582 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16584 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16585 MachinePointerInfo(SV, 16), false, false, 0);
16586 MemOps.push_back(Store);
16587 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16590 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16591 assert(Subtarget->is64Bit() &&
16592 "LowerVAARG only handles 64-bit va_arg!");
16593 assert((Subtarget->isTargetLinux() ||
16594 Subtarget->isTargetDarwin()) &&
16595 "Unhandled target in LowerVAARG");
16596 assert(Op.getNode()->getNumOperands() == 4);
16597 SDValue Chain = Op.getOperand(0);
16598 SDValue SrcPtr = Op.getOperand(1);
16599 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16600 unsigned Align = Op.getConstantOperandVal(3);
16603 EVT ArgVT = Op.getNode()->getValueType(0);
16604 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16605 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16608 // Decide which area this value should be read from.
16609 // TODO: Implement the AMD64 ABI in its entirety. This simple
16610 // selection mechanism works only for the basic types.
16611 if (ArgVT == MVT::f80) {
16612 llvm_unreachable("va_arg for f80 not yet implemented");
16613 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16614 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16615 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16616 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16618 llvm_unreachable("Unhandled argument type in LowerVAARG");
16621 if (ArgMode == 2) {
16622 // Sanity Check: Make sure using fp_offset makes sense.
16623 assert(!DAG.getTarget().Options.UseSoftFloat &&
16624 !(DAG.getMachineFunction()
16625 .getFunction()->getAttributes()
16626 .hasAttribute(AttributeSet::FunctionIndex,
16627 Attribute::NoImplicitFloat)) &&
16628 Subtarget->hasSSE1());
16631 // Insert VAARG_64 node into the DAG
16632 // VAARG_64 returns two values: Variable Argument Address, Chain
16633 SmallVector<SDValue, 11> InstOps;
16634 InstOps.push_back(Chain);
16635 InstOps.push_back(SrcPtr);
16636 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16637 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16638 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16639 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16640 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16641 VTs, InstOps, MVT::i64,
16642 MachinePointerInfo(SV),
16644 /*Volatile=*/false,
16646 /*WriteMem=*/true);
16647 Chain = VAARG.getValue(1);
16649 // Load the next argument and return it
16650 return DAG.getLoad(ArgVT, dl,
16653 MachinePointerInfo(),
16654 false, false, false, 0);
16657 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16658 SelectionDAG &DAG) {
16659 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16660 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16661 SDValue Chain = Op.getOperand(0);
16662 SDValue DstPtr = Op.getOperand(1);
16663 SDValue SrcPtr = Op.getOperand(2);
16664 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16665 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16668 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16669 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16671 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16674 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16675 // amount is a constant. Takes immediate version of shift as input.
16676 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16677 SDValue SrcOp, uint64_t ShiftAmt,
16678 SelectionDAG &DAG) {
16679 MVT ElementType = VT.getVectorElementType();
16681 // Fold this packed shift into its first operand if ShiftAmt is 0.
16685 // Check for ShiftAmt >= element width
16686 if (ShiftAmt >= ElementType.getSizeInBits()) {
16687 if (Opc == X86ISD::VSRAI)
16688 ShiftAmt = ElementType.getSizeInBits() - 1;
16690 return DAG.getConstant(0, VT);
16693 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16694 && "Unknown target vector shift-by-constant node");
16696 // Fold this packed vector shift into a build vector if SrcOp is a
16697 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16698 if (VT == SrcOp.getSimpleValueType() &&
16699 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16700 SmallVector<SDValue, 8> Elts;
16701 unsigned NumElts = SrcOp->getNumOperands();
16702 ConstantSDNode *ND;
16705 default: llvm_unreachable(nullptr);
16706 case X86ISD::VSHLI:
16707 for (unsigned i=0; i!=NumElts; ++i) {
16708 SDValue CurrentOp = SrcOp->getOperand(i);
16709 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16710 Elts.push_back(CurrentOp);
16713 ND = cast<ConstantSDNode>(CurrentOp);
16714 const APInt &C = ND->getAPIntValue();
16715 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16718 case X86ISD::VSRLI:
16719 for (unsigned i=0; i!=NumElts; ++i) {
16720 SDValue CurrentOp = SrcOp->getOperand(i);
16721 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16722 Elts.push_back(CurrentOp);
16725 ND = cast<ConstantSDNode>(CurrentOp);
16726 const APInt &C = ND->getAPIntValue();
16727 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16730 case X86ISD::VSRAI:
16731 for (unsigned i=0; i!=NumElts; ++i) {
16732 SDValue CurrentOp = SrcOp->getOperand(i);
16733 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16734 Elts.push_back(CurrentOp);
16737 ND = cast<ConstantSDNode>(CurrentOp);
16738 const APInt &C = ND->getAPIntValue();
16739 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16744 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16747 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16750 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16751 // may or may not be a constant. Takes immediate version of shift as input.
16752 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16753 SDValue SrcOp, SDValue ShAmt,
16754 SelectionDAG &DAG) {
16755 MVT SVT = ShAmt.getSimpleValueType();
16756 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16758 // Catch shift-by-constant.
16759 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16760 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16761 CShAmt->getZExtValue(), DAG);
16763 // Change opcode to non-immediate version
16765 default: llvm_unreachable("Unknown target vector shift node");
16766 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16767 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16768 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16771 const X86Subtarget &Subtarget =
16772 DAG.getTarget().getSubtarget<X86Subtarget>();
16773 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16774 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16775 // Let the shuffle legalizer expand this shift amount node.
16776 SDValue Op0 = ShAmt.getOperand(0);
16777 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16778 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16780 // Need to build a vector containing shift amount.
16781 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16782 SmallVector<SDValue, 4> ShOps;
16783 ShOps.push_back(ShAmt);
16784 if (SVT == MVT::i32) {
16785 ShOps.push_back(DAG.getConstant(0, SVT));
16786 ShOps.push_back(DAG.getUNDEF(SVT));
16788 ShOps.push_back(DAG.getUNDEF(SVT));
16790 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16791 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16794 // The return type has to be a 128-bit type with the same element
16795 // type as the input type.
16796 MVT EltVT = VT.getVectorElementType();
16797 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16799 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16800 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16803 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16804 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16805 /// necessary casting for \p Mask when lowering masking intrinsics.
16806 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16807 SDValue PreservedSrc,
16808 const X86Subtarget *Subtarget,
16809 SelectionDAG &DAG) {
16810 EVT VT = Op.getValueType();
16811 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16812 MVT::i1, VT.getVectorNumElements());
16813 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16814 Mask.getValueType().getSizeInBits());
16817 assert(MaskVT.isSimple() && "invalid mask type");
16819 if (isAllOnes(Mask))
16822 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16823 // are extracted by EXTRACT_SUBVECTOR.
16824 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16825 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16826 DAG.getIntPtrConstant(0));
16828 switch (Op.getOpcode()) {
16830 case X86ISD::PCMPEQM:
16831 case X86ISD::PCMPGTM:
16833 case X86ISD::CMPMU:
16834 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16836 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16837 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16838 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16841 /// \brief Creates an SDNode for a predicated scalar operation.
16842 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16843 /// The mask is comming as MVT::i8 and it should be truncated
16844 /// to MVT::i1 while lowering masking intrinsics.
16845 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16846 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16847 /// a scalar instruction.
16848 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16849 SDValue PreservedSrc,
16850 const X86Subtarget *Subtarget,
16851 SelectionDAG &DAG) {
16852 if (isAllOnes(Mask))
16855 EVT VT = Op.getValueType();
16857 // The mask should be of type MVT::i1
16858 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16860 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16861 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16862 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16865 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16867 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16868 case Intrinsic::x86_fma_vfmadd_ps:
16869 case Intrinsic::x86_fma_vfmadd_pd:
16870 case Intrinsic::x86_fma_vfmadd_ps_256:
16871 case Intrinsic::x86_fma_vfmadd_pd_256:
16872 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16873 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16874 return X86ISD::FMADD;
16875 case Intrinsic::x86_fma_vfmsub_ps:
16876 case Intrinsic::x86_fma_vfmsub_pd:
16877 case Intrinsic::x86_fma_vfmsub_ps_256:
16878 case Intrinsic::x86_fma_vfmsub_pd_256:
16879 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16880 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16881 return X86ISD::FMSUB;
16882 case Intrinsic::x86_fma_vfnmadd_ps:
16883 case Intrinsic::x86_fma_vfnmadd_pd:
16884 case Intrinsic::x86_fma_vfnmadd_ps_256:
16885 case Intrinsic::x86_fma_vfnmadd_pd_256:
16886 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16887 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16888 return X86ISD::FNMADD;
16889 case Intrinsic::x86_fma_vfnmsub_ps:
16890 case Intrinsic::x86_fma_vfnmsub_pd:
16891 case Intrinsic::x86_fma_vfnmsub_ps_256:
16892 case Intrinsic::x86_fma_vfnmsub_pd_256:
16893 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16894 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16895 return X86ISD::FNMSUB;
16896 case Intrinsic::x86_fma_vfmaddsub_ps:
16897 case Intrinsic::x86_fma_vfmaddsub_pd:
16898 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16899 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16900 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16901 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16902 return X86ISD::FMADDSUB;
16903 case Intrinsic::x86_fma_vfmsubadd_ps:
16904 case Intrinsic::x86_fma_vfmsubadd_pd:
16905 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16906 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16907 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16908 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16909 return X86ISD::FMSUBADD;
16913 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16914 SelectionDAG &DAG) {
16916 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16917 EVT VT = Op.getValueType();
16918 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16920 switch(IntrData->Type) {
16921 case INTR_TYPE_1OP:
16922 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16923 case INTR_TYPE_2OP:
16924 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16926 case INTR_TYPE_3OP:
16927 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16928 Op.getOperand(2), Op.getOperand(3));
16929 case INTR_TYPE_1OP_MASK_RM: {
16930 SDValue Src = Op.getOperand(1);
16931 SDValue Src0 = Op.getOperand(2);
16932 SDValue Mask = Op.getOperand(3);
16933 SDValue RoundingMode = Op.getOperand(4);
16934 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16936 Mask, Src0, Subtarget, DAG);
16938 case INTR_TYPE_SCALAR_MASK_RM: {
16939 SDValue Src1 = Op.getOperand(1);
16940 SDValue Src2 = Op.getOperand(2);
16941 SDValue Src0 = Op.getOperand(3);
16942 SDValue Mask = Op.getOperand(4);
16943 SDValue RoundingMode = Op.getOperand(5);
16944 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16946 Mask, Src0, Subtarget, DAG);
16948 case INTR_TYPE_2OP_MASK: {
16949 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16951 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16954 case CMP_MASK_CC: {
16955 // Comparison intrinsics with masks.
16956 // Example of transformation:
16957 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16958 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16960 // (v8i1 (insert_subvector undef,
16961 // (v2i1 (and (PCMPEQM %a, %b),
16962 // (extract_subvector
16963 // (v8i1 (bitcast %mask)), 0))), 0))))
16964 EVT VT = Op.getOperand(1).getValueType();
16965 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16966 VT.getVectorNumElements());
16967 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16968 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16969 Mask.getValueType().getSizeInBits());
16971 if (IntrData->Type == CMP_MASK_CC) {
16972 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16973 Op.getOperand(2), Op.getOperand(3));
16975 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16976 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16979 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16980 DAG.getTargetConstant(0, MaskVT),
16982 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16983 DAG.getUNDEF(BitcastVT), CmpMask,
16984 DAG.getIntPtrConstant(0));
16985 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16987 case COMI: { // Comparison intrinsics
16988 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16989 SDValue LHS = Op.getOperand(1);
16990 SDValue RHS = Op.getOperand(2);
16991 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16992 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16993 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16994 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16995 DAG.getConstant(X86CC, MVT::i8), Cond);
16996 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16999 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
17000 Op.getOperand(1), Op.getOperand(2), DAG);
17002 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17003 Op.getSimpleValueType(),
17005 Op.getOperand(2), DAG),
17006 Op.getOperand(4), Op.getOperand(3), Subtarget,
17008 case COMPRESS_EXPAND_IN_REG: {
17009 SDValue Mask = Op.getOperand(3);
17010 SDValue DataToCompress = Op.getOperand(1);
17011 SDValue PassThru = Op.getOperand(2);
17012 if (isAllOnes(Mask)) // return data as is
17013 return Op.getOperand(1);
17014 EVT VT = Op.getValueType();
17015 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17016 VT.getVectorNumElements());
17017 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17018 Mask.getValueType().getSizeInBits());
17020 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17021 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17022 DAG.getIntPtrConstant(0));
17024 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17028 SDValue Mask = Op.getOperand(3);
17029 EVT VT = Op.getValueType();
17030 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17031 VT.getVectorNumElements());
17032 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17033 Mask.getValueType().getSizeInBits());
17035 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17036 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17037 DAG.getIntPtrConstant(0));
17038 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17043 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17044 dl, Op.getValueType(),
17048 Op.getOperand(4), Op.getOperand(1),
17057 default: return SDValue(); // Don't custom lower most intrinsics.
17059 case Intrinsic::x86_avx512_mask_valign_q_512:
17060 case Intrinsic::x86_avx512_mask_valign_d_512:
17061 // Vector source operands are swapped.
17062 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17063 Op.getValueType(), Op.getOperand(2),
17066 Op.getOperand(5), Op.getOperand(4),
17069 // ptest and testp intrinsics. The intrinsic these come from are designed to
17070 // return an integer value, not just an instruction so lower it to the ptest
17071 // or testp pattern and a setcc for the result.
17072 case Intrinsic::x86_sse41_ptestz:
17073 case Intrinsic::x86_sse41_ptestc:
17074 case Intrinsic::x86_sse41_ptestnzc:
17075 case Intrinsic::x86_avx_ptestz_256:
17076 case Intrinsic::x86_avx_ptestc_256:
17077 case Intrinsic::x86_avx_ptestnzc_256:
17078 case Intrinsic::x86_avx_vtestz_ps:
17079 case Intrinsic::x86_avx_vtestc_ps:
17080 case Intrinsic::x86_avx_vtestnzc_ps:
17081 case Intrinsic::x86_avx_vtestz_pd:
17082 case Intrinsic::x86_avx_vtestc_pd:
17083 case Intrinsic::x86_avx_vtestnzc_pd:
17084 case Intrinsic::x86_avx_vtestz_ps_256:
17085 case Intrinsic::x86_avx_vtestc_ps_256:
17086 case Intrinsic::x86_avx_vtestnzc_ps_256:
17087 case Intrinsic::x86_avx_vtestz_pd_256:
17088 case Intrinsic::x86_avx_vtestc_pd_256:
17089 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17090 bool IsTestPacked = false;
17093 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17094 case Intrinsic::x86_avx_vtestz_ps:
17095 case Intrinsic::x86_avx_vtestz_pd:
17096 case Intrinsic::x86_avx_vtestz_ps_256:
17097 case Intrinsic::x86_avx_vtestz_pd_256:
17098 IsTestPacked = true; // Fallthrough
17099 case Intrinsic::x86_sse41_ptestz:
17100 case Intrinsic::x86_avx_ptestz_256:
17102 X86CC = X86::COND_E;
17104 case Intrinsic::x86_avx_vtestc_ps:
17105 case Intrinsic::x86_avx_vtestc_pd:
17106 case Intrinsic::x86_avx_vtestc_ps_256:
17107 case Intrinsic::x86_avx_vtestc_pd_256:
17108 IsTestPacked = true; // Fallthrough
17109 case Intrinsic::x86_sse41_ptestc:
17110 case Intrinsic::x86_avx_ptestc_256:
17112 X86CC = X86::COND_B;
17114 case Intrinsic::x86_avx_vtestnzc_ps:
17115 case Intrinsic::x86_avx_vtestnzc_pd:
17116 case Intrinsic::x86_avx_vtestnzc_ps_256:
17117 case Intrinsic::x86_avx_vtestnzc_pd_256:
17118 IsTestPacked = true; // Fallthrough
17119 case Intrinsic::x86_sse41_ptestnzc:
17120 case Intrinsic::x86_avx_ptestnzc_256:
17122 X86CC = X86::COND_A;
17126 SDValue LHS = Op.getOperand(1);
17127 SDValue RHS = Op.getOperand(2);
17128 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17129 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17130 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17131 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17132 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17134 case Intrinsic::x86_avx512_kortestz_w:
17135 case Intrinsic::x86_avx512_kortestc_w: {
17136 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17137 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17138 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17139 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17140 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17141 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17142 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17145 case Intrinsic::x86_sse42_pcmpistria128:
17146 case Intrinsic::x86_sse42_pcmpestria128:
17147 case Intrinsic::x86_sse42_pcmpistric128:
17148 case Intrinsic::x86_sse42_pcmpestric128:
17149 case Intrinsic::x86_sse42_pcmpistrio128:
17150 case Intrinsic::x86_sse42_pcmpestrio128:
17151 case Intrinsic::x86_sse42_pcmpistris128:
17152 case Intrinsic::x86_sse42_pcmpestris128:
17153 case Intrinsic::x86_sse42_pcmpistriz128:
17154 case Intrinsic::x86_sse42_pcmpestriz128: {
17158 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17159 case Intrinsic::x86_sse42_pcmpistria128:
17160 Opcode = X86ISD::PCMPISTRI;
17161 X86CC = X86::COND_A;
17163 case Intrinsic::x86_sse42_pcmpestria128:
17164 Opcode = X86ISD::PCMPESTRI;
17165 X86CC = X86::COND_A;
17167 case Intrinsic::x86_sse42_pcmpistric128:
17168 Opcode = X86ISD::PCMPISTRI;
17169 X86CC = X86::COND_B;
17171 case Intrinsic::x86_sse42_pcmpestric128:
17172 Opcode = X86ISD::PCMPESTRI;
17173 X86CC = X86::COND_B;
17175 case Intrinsic::x86_sse42_pcmpistrio128:
17176 Opcode = X86ISD::PCMPISTRI;
17177 X86CC = X86::COND_O;
17179 case Intrinsic::x86_sse42_pcmpestrio128:
17180 Opcode = X86ISD::PCMPESTRI;
17181 X86CC = X86::COND_O;
17183 case Intrinsic::x86_sse42_pcmpistris128:
17184 Opcode = X86ISD::PCMPISTRI;
17185 X86CC = X86::COND_S;
17187 case Intrinsic::x86_sse42_pcmpestris128:
17188 Opcode = X86ISD::PCMPESTRI;
17189 X86CC = X86::COND_S;
17191 case Intrinsic::x86_sse42_pcmpistriz128:
17192 Opcode = X86ISD::PCMPISTRI;
17193 X86CC = X86::COND_E;
17195 case Intrinsic::x86_sse42_pcmpestriz128:
17196 Opcode = X86ISD::PCMPESTRI;
17197 X86CC = X86::COND_E;
17200 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17201 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17202 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17203 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17204 DAG.getConstant(X86CC, MVT::i8),
17205 SDValue(PCMP.getNode(), 1));
17206 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17209 case Intrinsic::x86_sse42_pcmpistri128:
17210 case Intrinsic::x86_sse42_pcmpestri128: {
17212 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17213 Opcode = X86ISD::PCMPISTRI;
17215 Opcode = X86ISD::PCMPESTRI;
17217 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17218 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17219 return DAG.getNode(Opcode, dl, VTs, NewOps);
17222 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17223 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17224 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17225 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17226 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17227 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17228 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17229 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17230 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17231 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17232 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17233 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17234 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17235 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17236 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17237 dl, Op.getValueType(),
17241 Op.getOperand(4), Op.getOperand(1),
17247 case Intrinsic::x86_fma_vfmadd_ps:
17248 case Intrinsic::x86_fma_vfmadd_pd:
17249 case Intrinsic::x86_fma_vfmsub_ps:
17250 case Intrinsic::x86_fma_vfmsub_pd:
17251 case Intrinsic::x86_fma_vfnmadd_ps:
17252 case Intrinsic::x86_fma_vfnmadd_pd:
17253 case Intrinsic::x86_fma_vfnmsub_ps:
17254 case Intrinsic::x86_fma_vfnmsub_pd:
17255 case Intrinsic::x86_fma_vfmaddsub_ps:
17256 case Intrinsic::x86_fma_vfmaddsub_pd:
17257 case Intrinsic::x86_fma_vfmsubadd_ps:
17258 case Intrinsic::x86_fma_vfmsubadd_pd:
17259 case Intrinsic::x86_fma_vfmadd_ps_256:
17260 case Intrinsic::x86_fma_vfmadd_pd_256:
17261 case Intrinsic::x86_fma_vfmsub_ps_256:
17262 case Intrinsic::x86_fma_vfmsub_pd_256:
17263 case Intrinsic::x86_fma_vfnmadd_ps_256:
17264 case Intrinsic::x86_fma_vfnmadd_pd_256:
17265 case Intrinsic::x86_fma_vfnmsub_ps_256:
17266 case Intrinsic::x86_fma_vfnmsub_pd_256:
17267 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17268 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17269 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17270 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17271 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17272 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17276 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17277 SDValue Src, SDValue Mask, SDValue Base,
17278 SDValue Index, SDValue ScaleOp, SDValue Chain,
17279 const X86Subtarget * Subtarget) {
17281 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17282 assert(C && "Invalid scale type");
17283 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17284 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17285 Index.getSimpleValueType().getVectorNumElements());
17287 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17289 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17291 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17292 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17293 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17294 SDValue Segment = DAG.getRegister(0, MVT::i32);
17295 if (Src.getOpcode() == ISD::UNDEF)
17296 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17297 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17298 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17299 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17300 return DAG.getMergeValues(RetOps, dl);
17303 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17304 SDValue Src, SDValue Mask, SDValue Base,
17305 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17307 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17308 assert(C && "Invalid scale type");
17309 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17310 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17311 SDValue Segment = DAG.getRegister(0, MVT::i32);
17312 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17313 Index.getSimpleValueType().getVectorNumElements());
17315 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17317 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17319 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17320 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17321 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17322 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17323 return SDValue(Res, 1);
17326 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17327 SDValue Mask, SDValue Base, SDValue Index,
17328 SDValue ScaleOp, SDValue Chain) {
17330 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17331 assert(C && "Invalid scale type");
17332 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17333 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17334 SDValue Segment = DAG.getRegister(0, MVT::i32);
17336 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17338 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17340 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17342 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17343 //SDVTList VTs = DAG.getVTList(MVT::Other);
17344 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17345 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17346 return SDValue(Res, 0);
17349 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17350 // read performance monitor counters (x86_rdpmc).
17351 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17352 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17353 SmallVectorImpl<SDValue> &Results) {
17354 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17355 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17358 // The ECX register is used to select the index of the performance counter
17360 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17362 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17364 // Reads the content of a 64-bit performance counter and returns it in the
17365 // registers EDX:EAX.
17366 if (Subtarget->is64Bit()) {
17367 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17368 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17371 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17372 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17375 Chain = HI.getValue(1);
17377 if (Subtarget->is64Bit()) {
17378 // The EAX register is loaded with the low-order 32 bits. The EDX register
17379 // is loaded with the supported high-order bits of the counter.
17380 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17381 DAG.getConstant(32, MVT::i8));
17382 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17383 Results.push_back(Chain);
17387 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17388 SDValue Ops[] = { LO, HI };
17389 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17390 Results.push_back(Pair);
17391 Results.push_back(Chain);
17394 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17395 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17396 // also used to custom lower READCYCLECOUNTER nodes.
17397 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17398 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17399 SmallVectorImpl<SDValue> &Results) {
17400 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17401 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17404 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17405 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17406 // and the EAX register is loaded with the low-order 32 bits.
17407 if (Subtarget->is64Bit()) {
17408 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17409 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17412 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17413 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17416 SDValue Chain = HI.getValue(1);
17418 if (Opcode == X86ISD::RDTSCP_DAG) {
17419 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17421 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17422 // the ECX register. Add 'ecx' explicitly to the chain.
17423 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17425 // Explicitly store the content of ECX at the location passed in input
17426 // to the 'rdtscp' intrinsic.
17427 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17428 MachinePointerInfo(), false, false, 0);
17431 if (Subtarget->is64Bit()) {
17432 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17433 // the EAX register is loaded with the low-order 32 bits.
17434 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17435 DAG.getConstant(32, MVT::i8));
17436 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17437 Results.push_back(Chain);
17441 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17442 SDValue Ops[] = { LO, HI };
17443 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17444 Results.push_back(Pair);
17445 Results.push_back(Chain);
17448 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17449 SelectionDAG &DAG) {
17450 SmallVector<SDValue, 2> Results;
17452 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17454 return DAG.getMergeValues(Results, DL);
17458 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17459 SelectionDAG &DAG) {
17460 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17462 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17467 switch(IntrData->Type) {
17469 llvm_unreachable("Unknown Intrinsic Type");
17473 // Emit the node with the right value type.
17474 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17475 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17477 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17478 // Otherwise return the value from Rand, which is always 0, casted to i32.
17479 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17480 DAG.getConstant(1, Op->getValueType(1)),
17481 DAG.getConstant(X86::COND_B, MVT::i32),
17482 SDValue(Result.getNode(), 1) };
17483 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17484 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17487 // Return { result, isValid, chain }.
17488 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17489 SDValue(Result.getNode(), 2));
17492 //gather(v1, mask, index, base, scale);
17493 SDValue Chain = Op.getOperand(0);
17494 SDValue Src = Op.getOperand(2);
17495 SDValue Base = Op.getOperand(3);
17496 SDValue Index = Op.getOperand(4);
17497 SDValue Mask = Op.getOperand(5);
17498 SDValue Scale = Op.getOperand(6);
17499 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17503 //scatter(base, mask, index, v1, scale);
17504 SDValue Chain = Op.getOperand(0);
17505 SDValue Base = Op.getOperand(2);
17506 SDValue Mask = Op.getOperand(3);
17507 SDValue Index = Op.getOperand(4);
17508 SDValue Src = Op.getOperand(5);
17509 SDValue Scale = Op.getOperand(6);
17510 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17513 SDValue Hint = Op.getOperand(6);
17515 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17516 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17517 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17518 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17519 SDValue Chain = Op.getOperand(0);
17520 SDValue Mask = Op.getOperand(2);
17521 SDValue Index = Op.getOperand(3);
17522 SDValue Base = Op.getOperand(4);
17523 SDValue Scale = Op.getOperand(5);
17524 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17526 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17528 SmallVector<SDValue, 2> Results;
17529 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17530 return DAG.getMergeValues(Results, dl);
17532 // Read Performance Monitoring Counters.
17534 SmallVector<SDValue, 2> Results;
17535 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17536 return DAG.getMergeValues(Results, dl);
17538 // XTEST intrinsics.
17540 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17541 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17542 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17543 DAG.getConstant(X86::COND_NE, MVT::i8),
17545 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17546 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17547 Ret, SDValue(InTrans.getNode(), 1));
17551 SmallVector<SDValue, 2> Results;
17552 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17553 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17554 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17555 DAG.getConstant(-1, MVT::i8));
17556 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17557 Op.getOperand(4), GenCF.getValue(1));
17558 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17559 Op.getOperand(5), MachinePointerInfo(),
17561 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17562 DAG.getConstant(X86::COND_B, MVT::i8),
17564 Results.push_back(SetCC);
17565 Results.push_back(Store);
17566 return DAG.getMergeValues(Results, dl);
17568 case COMPRESS_TO_MEM: {
17570 SDValue Mask = Op.getOperand(4);
17571 SDValue DataToCompress = Op.getOperand(3);
17572 SDValue Addr = Op.getOperand(2);
17573 SDValue Chain = Op.getOperand(0);
17575 if (isAllOnes(Mask)) // return just a store
17576 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17577 MachinePointerInfo(), false, false, 0);
17579 EVT VT = DataToCompress.getValueType();
17580 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17581 VT.getVectorNumElements());
17582 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17583 Mask.getValueType().getSizeInBits());
17584 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17585 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17586 DAG.getIntPtrConstant(0));
17588 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17589 DataToCompress, DAG.getUNDEF(VT));
17590 return DAG.getStore(Chain, dl, Compressed, Addr,
17591 MachinePointerInfo(), false, false, 0);
17593 case EXPAND_FROM_MEM: {
17595 SDValue Mask = Op.getOperand(4);
17596 SDValue PathThru = Op.getOperand(3);
17597 SDValue Addr = Op.getOperand(2);
17598 SDValue Chain = Op.getOperand(0);
17599 EVT VT = Op.getValueType();
17601 if (isAllOnes(Mask)) // return just a load
17602 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17604 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17605 VT.getVectorNumElements());
17606 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17607 Mask.getValueType().getSizeInBits());
17608 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17609 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17610 DAG.getIntPtrConstant(0));
17612 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17613 false, false, false, 0);
17615 SmallVector<SDValue, 2> Results;
17616 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17618 Results.push_back(Chain);
17619 return DAG.getMergeValues(Results, dl);
17624 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17625 SelectionDAG &DAG) const {
17626 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17627 MFI->setReturnAddressIsTaken(true);
17629 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17632 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17634 EVT PtrVT = getPointerTy();
17637 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17638 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17639 DAG.getSubtarget().getRegisterInfo());
17640 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17641 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17642 DAG.getNode(ISD::ADD, dl, PtrVT,
17643 FrameAddr, Offset),
17644 MachinePointerInfo(), false, false, false, 0);
17647 // Just load the return address.
17648 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17649 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17650 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17653 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17654 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17655 MFI->setFrameAddressIsTaken(true);
17657 EVT VT = Op.getValueType();
17658 SDLoc dl(Op); // FIXME probably not meaningful
17659 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17660 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17661 DAG.getSubtarget().getRegisterInfo());
17662 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17663 DAG.getMachineFunction());
17664 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17665 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17666 "Invalid Frame Register!");
17667 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17669 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17670 MachinePointerInfo(),
17671 false, false, false, 0);
17675 // FIXME? Maybe this could be a TableGen attribute on some registers and
17676 // this table could be generated automatically from RegInfo.
17677 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17679 unsigned Reg = StringSwitch<unsigned>(RegName)
17680 .Case("esp", X86::ESP)
17681 .Case("rsp", X86::RSP)
17685 report_fatal_error("Invalid register name global variable");
17688 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17689 SelectionDAG &DAG) const {
17690 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17691 DAG.getSubtarget().getRegisterInfo());
17692 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17695 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17696 SDValue Chain = Op.getOperand(0);
17697 SDValue Offset = Op.getOperand(1);
17698 SDValue Handler = Op.getOperand(2);
17701 EVT PtrVT = getPointerTy();
17702 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17703 DAG.getSubtarget().getRegisterInfo());
17704 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17705 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17706 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17707 "Invalid Frame Register!");
17708 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17709 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17711 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17712 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17713 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17714 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17716 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17718 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17719 DAG.getRegister(StoreAddrReg, PtrVT));
17722 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17723 SelectionDAG &DAG) const {
17725 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17726 DAG.getVTList(MVT::i32, MVT::Other),
17727 Op.getOperand(0), Op.getOperand(1));
17730 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17731 SelectionDAG &DAG) const {
17733 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17734 Op.getOperand(0), Op.getOperand(1));
17737 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17738 return Op.getOperand(0);
17741 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17742 SelectionDAG &DAG) const {
17743 SDValue Root = Op.getOperand(0);
17744 SDValue Trmp = Op.getOperand(1); // trampoline
17745 SDValue FPtr = Op.getOperand(2); // nested function
17746 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17749 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17750 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17752 if (Subtarget->is64Bit()) {
17753 SDValue OutChains[6];
17755 // Large code-model.
17756 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17757 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17759 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17760 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17762 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17764 // Load the pointer to the nested function into R11.
17765 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17766 SDValue Addr = Trmp;
17767 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17768 Addr, MachinePointerInfo(TrmpAddr),
17771 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17772 DAG.getConstant(2, MVT::i64));
17773 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17774 MachinePointerInfo(TrmpAddr, 2),
17777 // Load the 'nest' parameter value into R10.
17778 // R10 is specified in X86CallingConv.td
17779 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17780 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17781 DAG.getConstant(10, MVT::i64));
17782 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17783 Addr, MachinePointerInfo(TrmpAddr, 10),
17786 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17787 DAG.getConstant(12, MVT::i64));
17788 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17789 MachinePointerInfo(TrmpAddr, 12),
17792 // Jump to the nested function.
17793 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17794 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17795 DAG.getConstant(20, MVT::i64));
17796 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17797 Addr, MachinePointerInfo(TrmpAddr, 20),
17800 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17801 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17802 DAG.getConstant(22, MVT::i64));
17803 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17804 MachinePointerInfo(TrmpAddr, 22),
17807 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17809 const Function *Func =
17810 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17811 CallingConv::ID CC = Func->getCallingConv();
17816 llvm_unreachable("Unsupported calling convention");
17817 case CallingConv::C:
17818 case CallingConv::X86_StdCall: {
17819 // Pass 'nest' parameter in ECX.
17820 // Must be kept in sync with X86CallingConv.td
17821 NestReg = X86::ECX;
17823 // Check that ECX wasn't needed by an 'inreg' parameter.
17824 FunctionType *FTy = Func->getFunctionType();
17825 const AttributeSet &Attrs = Func->getAttributes();
17827 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17828 unsigned InRegCount = 0;
17831 for (FunctionType::param_iterator I = FTy->param_begin(),
17832 E = FTy->param_end(); I != E; ++I, ++Idx)
17833 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17834 // FIXME: should only count parameters that are lowered to integers.
17835 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17837 if (InRegCount > 2) {
17838 report_fatal_error("Nest register in use - reduce number of inreg"
17844 case CallingConv::X86_FastCall:
17845 case CallingConv::X86_ThisCall:
17846 case CallingConv::Fast:
17847 // Pass 'nest' parameter in EAX.
17848 // Must be kept in sync with X86CallingConv.td
17849 NestReg = X86::EAX;
17853 SDValue OutChains[4];
17854 SDValue Addr, Disp;
17856 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17857 DAG.getConstant(10, MVT::i32));
17858 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17860 // This is storing the opcode for MOV32ri.
17861 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17862 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17863 OutChains[0] = DAG.getStore(Root, dl,
17864 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17865 Trmp, MachinePointerInfo(TrmpAddr),
17868 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17869 DAG.getConstant(1, MVT::i32));
17870 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17871 MachinePointerInfo(TrmpAddr, 1),
17874 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17875 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17876 DAG.getConstant(5, MVT::i32));
17877 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17878 MachinePointerInfo(TrmpAddr, 5),
17881 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17882 DAG.getConstant(6, MVT::i32));
17883 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17884 MachinePointerInfo(TrmpAddr, 6),
17887 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17891 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17892 SelectionDAG &DAG) const {
17894 The rounding mode is in bits 11:10 of FPSR, and has the following
17896 00 Round to nearest
17901 FLT_ROUNDS, on the other hand, expects the following:
17908 To perform the conversion, we do:
17909 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17912 MachineFunction &MF = DAG.getMachineFunction();
17913 const TargetMachine &TM = MF.getTarget();
17914 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17915 unsigned StackAlignment = TFI.getStackAlignment();
17916 MVT VT = Op.getSimpleValueType();
17919 // Save FP Control Word to stack slot
17920 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17921 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17923 MachineMemOperand *MMO =
17924 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17925 MachineMemOperand::MOStore, 2, 2);
17927 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17928 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17929 DAG.getVTList(MVT::Other),
17930 Ops, MVT::i16, MMO);
17932 // Load FP Control Word from stack slot
17933 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17934 MachinePointerInfo(), false, false, false, 0);
17936 // Transform as necessary
17938 DAG.getNode(ISD::SRL, DL, MVT::i16,
17939 DAG.getNode(ISD::AND, DL, MVT::i16,
17940 CWD, DAG.getConstant(0x800, MVT::i16)),
17941 DAG.getConstant(11, MVT::i8));
17943 DAG.getNode(ISD::SRL, DL, MVT::i16,
17944 DAG.getNode(ISD::AND, DL, MVT::i16,
17945 CWD, DAG.getConstant(0x400, MVT::i16)),
17946 DAG.getConstant(9, MVT::i8));
17949 DAG.getNode(ISD::AND, DL, MVT::i16,
17950 DAG.getNode(ISD::ADD, DL, MVT::i16,
17951 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17952 DAG.getConstant(1, MVT::i16)),
17953 DAG.getConstant(3, MVT::i16));
17955 return DAG.getNode((VT.getSizeInBits() < 16 ?
17956 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17959 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17960 MVT VT = Op.getSimpleValueType();
17962 unsigned NumBits = VT.getSizeInBits();
17965 Op = Op.getOperand(0);
17966 if (VT == MVT::i8) {
17967 // Zero extend to i32 since there is not an i8 bsr.
17969 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17972 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17973 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17974 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17976 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17979 DAG.getConstant(NumBits+NumBits-1, OpVT),
17980 DAG.getConstant(X86::COND_E, MVT::i8),
17983 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17985 // Finally xor with NumBits-1.
17986 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17989 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17993 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17994 MVT VT = Op.getSimpleValueType();
17996 unsigned NumBits = VT.getSizeInBits();
17999 Op = Op.getOperand(0);
18000 if (VT == MVT::i8) {
18001 // Zero extend to i32 since there is not an i8 bsr.
18003 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18006 // Issue a bsr (scan bits in reverse).
18007 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18008 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18010 // And xor with NumBits-1.
18011 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18014 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18018 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18019 MVT VT = Op.getSimpleValueType();
18020 unsigned NumBits = VT.getSizeInBits();
18022 Op = Op.getOperand(0);
18024 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18025 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18026 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18028 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18031 DAG.getConstant(NumBits, VT),
18032 DAG.getConstant(X86::COND_E, MVT::i8),
18035 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18038 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18039 // ones, and then concatenate the result back.
18040 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18041 MVT VT = Op.getSimpleValueType();
18043 assert(VT.is256BitVector() && VT.isInteger() &&
18044 "Unsupported value type for operation");
18046 unsigned NumElems = VT.getVectorNumElements();
18049 // Extract the LHS vectors
18050 SDValue LHS = Op.getOperand(0);
18051 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18052 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18054 // Extract the RHS vectors
18055 SDValue RHS = Op.getOperand(1);
18056 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18057 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18059 MVT EltVT = VT.getVectorElementType();
18060 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18062 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18063 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18064 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18067 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18068 assert(Op.getSimpleValueType().is256BitVector() &&
18069 Op.getSimpleValueType().isInteger() &&
18070 "Only handle AVX 256-bit vector integer operation");
18071 return Lower256IntArith(Op, DAG);
18074 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18075 assert(Op.getSimpleValueType().is256BitVector() &&
18076 Op.getSimpleValueType().isInteger() &&
18077 "Only handle AVX 256-bit vector integer operation");
18078 return Lower256IntArith(Op, DAG);
18081 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18082 SelectionDAG &DAG) {
18084 MVT VT = Op.getSimpleValueType();
18086 // Decompose 256-bit ops into smaller 128-bit ops.
18087 if (VT.is256BitVector() && !Subtarget->hasInt256())
18088 return Lower256IntArith(Op, DAG);
18090 SDValue A = Op.getOperand(0);
18091 SDValue B = Op.getOperand(1);
18093 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18094 if (VT == MVT::v4i32) {
18095 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18096 "Should not custom lower when pmuldq is available!");
18098 // Extract the odd parts.
18099 static const int UnpackMask[] = { 1, -1, 3, -1 };
18100 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18101 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18103 // Multiply the even parts.
18104 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18105 // Now multiply odd parts.
18106 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18108 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18109 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18111 // Merge the two vectors back together with a shuffle. This expands into 2
18113 static const int ShufMask[] = { 0, 4, 2, 6 };
18114 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18117 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18118 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18120 // Ahi = psrlqi(a, 32);
18121 // Bhi = psrlqi(b, 32);
18123 // AloBlo = pmuludq(a, b);
18124 // AloBhi = pmuludq(a, Bhi);
18125 // AhiBlo = pmuludq(Ahi, b);
18127 // AloBhi = psllqi(AloBhi, 32);
18128 // AhiBlo = psllqi(AhiBlo, 32);
18129 // return AloBlo + AloBhi + AhiBlo;
18131 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18132 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18134 // Bit cast to 32-bit vectors for MULUDQ
18135 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18136 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18137 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18138 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18139 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18140 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18142 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18143 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18144 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18146 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18147 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18149 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18150 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18153 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18154 assert(Subtarget->isTargetWin64() && "Unexpected target");
18155 EVT VT = Op.getValueType();
18156 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18157 "Unexpected return type for lowering");
18161 switch (Op->getOpcode()) {
18162 default: llvm_unreachable("Unexpected request for libcall!");
18163 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18164 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18165 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18166 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18167 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18168 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18172 SDValue InChain = DAG.getEntryNode();
18174 TargetLowering::ArgListTy Args;
18175 TargetLowering::ArgListEntry Entry;
18176 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18177 EVT ArgVT = Op->getOperand(i).getValueType();
18178 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18179 "Unexpected argument type for lowering");
18180 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18181 Entry.Node = StackPtr;
18182 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18184 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18185 Entry.Ty = PointerType::get(ArgTy,0);
18186 Entry.isSExt = false;
18187 Entry.isZExt = false;
18188 Args.push_back(Entry);
18191 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18194 TargetLowering::CallLoweringInfo CLI(DAG);
18195 CLI.setDebugLoc(dl).setChain(InChain)
18196 .setCallee(getLibcallCallingConv(LC),
18197 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18198 Callee, std::move(Args), 0)
18199 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18201 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18202 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18205 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18206 SelectionDAG &DAG) {
18207 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18208 EVT VT = Op0.getValueType();
18211 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18212 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18214 // PMULxD operations multiply each even value (starting at 0) of LHS with
18215 // the related value of RHS and produce a widen result.
18216 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18217 // => <2 x i64> <ae|cg>
18219 // In other word, to have all the results, we need to perform two PMULxD:
18220 // 1. one with the even values.
18221 // 2. one with the odd values.
18222 // To achieve #2, with need to place the odd values at an even position.
18224 // Place the odd value at an even position (basically, shift all values 1
18225 // step to the left):
18226 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18227 // <a|b|c|d> => <b|undef|d|undef>
18228 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18229 // <e|f|g|h> => <f|undef|h|undef>
18230 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18232 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18234 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18235 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18237 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18238 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18239 // => <2 x i64> <ae|cg>
18240 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18241 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18242 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18243 // => <2 x i64> <bf|dh>
18244 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18245 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18247 // Shuffle it back into the right order.
18248 SDValue Highs, Lows;
18249 if (VT == MVT::v8i32) {
18250 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18251 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18252 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18253 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18255 const int HighMask[] = {1, 5, 3, 7};
18256 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18257 const int LowMask[] = {0, 4, 2, 6};
18258 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18261 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18262 // unsigned multiply.
18263 if (IsSigned && !Subtarget->hasSSE41()) {
18265 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18266 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18267 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18268 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18269 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18271 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18272 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18275 // The first result of MUL_LOHI is actually the low value, followed by the
18277 SDValue Ops[] = {Lows, Highs};
18278 return DAG.getMergeValues(Ops, dl);
18281 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18282 const X86Subtarget *Subtarget) {
18283 MVT VT = Op.getSimpleValueType();
18285 SDValue R = Op.getOperand(0);
18286 SDValue Amt = Op.getOperand(1);
18288 // Optimize shl/srl/sra with constant shift amount.
18289 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18290 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18291 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18293 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18294 (Subtarget->hasInt256() &&
18295 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18296 (Subtarget->hasAVX512() &&
18297 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18298 if (Op.getOpcode() == ISD::SHL)
18299 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18301 if (Op.getOpcode() == ISD::SRL)
18302 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18304 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18305 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18309 if (VT == MVT::v16i8) {
18310 if (Op.getOpcode() == ISD::SHL) {
18311 // Make a large shift.
18312 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18313 MVT::v8i16, R, ShiftAmt,
18315 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18316 // Zero out the rightmost bits.
18317 SmallVector<SDValue, 16> V(16,
18318 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18320 return DAG.getNode(ISD::AND, dl, VT, SHL,
18321 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18323 if (Op.getOpcode() == ISD::SRL) {
18324 // Make a large shift.
18325 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18326 MVT::v8i16, R, ShiftAmt,
18328 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18329 // Zero out the leftmost bits.
18330 SmallVector<SDValue, 16> V(16,
18331 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18333 return DAG.getNode(ISD::AND, dl, VT, SRL,
18334 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18336 if (Op.getOpcode() == ISD::SRA) {
18337 if (ShiftAmt == 7) {
18338 // R s>> 7 === R s< 0
18339 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18340 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18343 // R s>> a === ((R u>> a) ^ m) - m
18344 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18345 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18347 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18348 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18349 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18352 llvm_unreachable("Unknown shift opcode.");
18355 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18356 if (Op.getOpcode() == ISD::SHL) {
18357 // Make a large shift.
18358 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18359 MVT::v16i16, R, ShiftAmt,
18361 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18362 // Zero out the rightmost bits.
18363 SmallVector<SDValue, 32> V(32,
18364 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18366 return DAG.getNode(ISD::AND, dl, VT, SHL,
18367 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18369 if (Op.getOpcode() == ISD::SRL) {
18370 // Make a large shift.
18371 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18372 MVT::v16i16, R, ShiftAmt,
18374 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18375 // Zero out the leftmost bits.
18376 SmallVector<SDValue, 32> V(32,
18377 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18379 return DAG.getNode(ISD::AND, dl, VT, SRL,
18380 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18382 if (Op.getOpcode() == ISD::SRA) {
18383 if (ShiftAmt == 7) {
18384 // R s>> 7 === R s< 0
18385 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18386 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18389 // R s>> a === ((R u>> a) ^ m) - m
18390 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18391 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18393 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18394 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18395 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18398 llvm_unreachable("Unknown shift opcode.");
18403 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18404 if (!Subtarget->is64Bit() &&
18405 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18406 Amt.getOpcode() == ISD::BITCAST &&
18407 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18408 Amt = Amt.getOperand(0);
18409 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18410 VT.getVectorNumElements();
18411 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18412 uint64_t ShiftAmt = 0;
18413 for (unsigned i = 0; i != Ratio; ++i) {
18414 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18418 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18420 // Check remaining shift amounts.
18421 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18422 uint64_t ShAmt = 0;
18423 for (unsigned j = 0; j != Ratio; ++j) {
18424 ConstantSDNode *C =
18425 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18429 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18431 if (ShAmt != ShiftAmt)
18434 switch (Op.getOpcode()) {
18436 llvm_unreachable("Unknown shift opcode!");
18438 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18441 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18444 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18452 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18453 const X86Subtarget* Subtarget) {
18454 MVT VT = Op.getSimpleValueType();
18456 SDValue R = Op.getOperand(0);
18457 SDValue Amt = Op.getOperand(1);
18459 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18460 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18461 (Subtarget->hasInt256() &&
18462 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18463 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18464 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18466 EVT EltVT = VT.getVectorElementType();
18468 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18469 // Check if this build_vector node is doing a splat.
18470 // If so, then set BaseShAmt equal to the splat value.
18471 BaseShAmt = BV->getSplatValue();
18472 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18473 BaseShAmt = SDValue();
18475 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18476 Amt = Amt.getOperand(0);
18478 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18479 if (SVN && SVN->isSplat()) {
18480 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18481 SDValue InVec = Amt.getOperand(0);
18482 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18483 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18484 "Unexpected shuffle index found!");
18485 BaseShAmt = InVec.getOperand(SplatIdx);
18486 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18487 if (ConstantSDNode *C =
18488 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18489 if (C->getZExtValue() == SplatIdx)
18490 BaseShAmt = InVec.getOperand(1);
18495 // Avoid introducing an extract element from a shuffle.
18496 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18497 DAG.getIntPtrConstant(SplatIdx));
18501 if (BaseShAmt.getNode()) {
18502 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18503 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18504 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18505 else if (EltVT.bitsLT(MVT::i32))
18506 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18508 switch (Op.getOpcode()) {
18510 llvm_unreachable("Unknown shift opcode!");
18512 switch (VT.SimpleTy) {
18513 default: return SDValue();
18522 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18525 switch (VT.SimpleTy) {
18526 default: return SDValue();
18533 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18536 switch (VT.SimpleTy) {
18537 default: return SDValue();
18546 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18552 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18553 if (!Subtarget->is64Bit() &&
18554 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18555 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18556 Amt.getOpcode() == ISD::BITCAST &&
18557 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18558 Amt = Amt.getOperand(0);
18559 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18560 VT.getVectorNumElements();
18561 std::vector<SDValue> Vals(Ratio);
18562 for (unsigned i = 0; i != Ratio; ++i)
18563 Vals[i] = Amt.getOperand(i);
18564 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18565 for (unsigned j = 0; j != Ratio; ++j)
18566 if (Vals[j] != Amt.getOperand(i + j))
18569 switch (Op.getOpcode()) {
18571 llvm_unreachable("Unknown shift opcode!");
18573 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18575 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18577 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18584 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18585 SelectionDAG &DAG) {
18586 MVT VT = Op.getSimpleValueType();
18588 SDValue R = Op.getOperand(0);
18589 SDValue Amt = Op.getOperand(1);
18592 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18593 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18595 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18599 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18603 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18605 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18606 if (Subtarget->hasInt256()) {
18607 if (Op.getOpcode() == ISD::SRL &&
18608 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18609 VT == MVT::v4i64 || VT == MVT::v8i32))
18611 if (Op.getOpcode() == ISD::SHL &&
18612 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18613 VT == MVT::v4i64 || VT == MVT::v8i32))
18615 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18619 // If possible, lower this packed shift into a vector multiply instead of
18620 // expanding it into a sequence of scalar shifts.
18621 // Do this only if the vector shift count is a constant build_vector.
18622 if (Op.getOpcode() == ISD::SHL &&
18623 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18624 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18625 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18626 SmallVector<SDValue, 8> Elts;
18627 EVT SVT = VT.getScalarType();
18628 unsigned SVTBits = SVT.getSizeInBits();
18629 const APInt &One = APInt(SVTBits, 1);
18630 unsigned NumElems = VT.getVectorNumElements();
18632 for (unsigned i=0; i !=NumElems; ++i) {
18633 SDValue Op = Amt->getOperand(i);
18634 if (Op->getOpcode() == ISD::UNDEF) {
18635 Elts.push_back(Op);
18639 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18640 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18641 uint64_t ShAmt = C.getZExtValue();
18642 if (ShAmt >= SVTBits) {
18643 Elts.push_back(DAG.getUNDEF(SVT));
18646 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18648 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18649 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18652 // Lower SHL with variable shift amount.
18653 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18654 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18656 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18657 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18658 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18659 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18662 // If possible, lower this shift as a sequence of two shifts by
18663 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18665 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18667 // Could be rewritten as:
18668 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18670 // The advantage is that the two shifts from the example would be
18671 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18672 // the vector shift into four scalar shifts plus four pairs of vector
18674 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18675 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18676 unsigned TargetOpcode = X86ISD::MOVSS;
18677 bool CanBeSimplified;
18678 // The splat value for the first packed shift (the 'X' from the example).
18679 SDValue Amt1 = Amt->getOperand(0);
18680 // The splat value for the second packed shift (the 'Y' from the example).
18681 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18682 Amt->getOperand(2);
18684 // See if it is possible to replace this node with a sequence of
18685 // two shifts followed by a MOVSS/MOVSD
18686 if (VT == MVT::v4i32) {
18687 // Check if it is legal to use a MOVSS.
18688 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18689 Amt2 == Amt->getOperand(3);
18690 if (!CanBeSimplified) {
18691 // Otherwise, check if we can still simplify this node using a MOVSD.
18692 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18693 Amt->getOperand(2) == Amt->getOperand(3);
18694 TargetOpcode = X86ISD::MOVSD;
18695 Amt2 = Amt->getOperand(2);
18698 // Do similar checks for the case where the machine value type
18700 CanBeSimplified = Amt1 == Amt->getOperand(1);
18701 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18702 CanBeSimplified = Amt2 == Amt->getOperand(i);
18704 if (!CanBeSimplified) {
18705 TargetOpcode = X86ISD::MOVSD;
18706 CanBeSimplified = true;
18707 Amt2 = Amt->getOperand(4);
18708 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18709 CanBeSimplified = Amt1 == Amt->getOperand(i);
18710 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18711 CanBeSimplified = Amt2 == Amt->getOperand(j);
18715 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18716 isa<ConstantSDNode>(Amt2)) {
18717 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18718 EVT CastVT = MVT::v4i32;
18720 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18721 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18723 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18724 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18725 if (TargetOpcode == X86ISD::MOVSD)
18726 CastVT = MVT::v2i64;
18727 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18728 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18729 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18731 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18735 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18736 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18739 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18740 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18742 // Turn 'a' into a mask suitable for VSELECT
18743 SDValue VSelM = DAG.getConstant(0x80, VT);
18744 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18745 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18747 SDValue CM1 = DAG.getConstant(0x0f, VT);
18748 SDValue CM2 = DAG.getConstant(0x3f, VT);
18750 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18751 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18752 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18753 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18754 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18757 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18758 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18759 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18761 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18762 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18763 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18764 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18765 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18768 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18769 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18770 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18772 // return VSELECT(r, r+r, a);
18773 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18774 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18778 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18779 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18780 // solution better.
18781 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18782 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18784 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18785 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18786 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18787 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18788 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18791 // Decompose 256-bit shifts into smaller 128-bit shifts.
18792 if (VT.is256BitVector()) {
18793 unsigned NumElems = VT.getVectorNumElements();
18794 MVT EltVT = VT.getVectorElementType();
18795 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18797 // Extract the two vectors
18798 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18799 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18801 // Recreate the shift amount vectors
18802 SDValue Amt1, Amt2;
18803 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18804 // Constant shift amount
18805 SmallVector<SDValue, 4> Amt1Csts;
18806 SmallVector<SDValue, 4> Amt2Csts;
18807 for (unsigned i = 0; i != NumElems/2; ++i)
18808 Amt1Csts.push_back(Amt->getOperand(i));
18809 for (unsigned i = NumElems/2; i != NumElems; ++i)
18810 Amt2Csts.push_back(Amt->getOperand(i));
18812 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18813 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18815 // Variable shift amount
18816 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18817 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18820 // Issue new vector shifts for the smaller types
18821 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18822 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18824 // Concatenate the result back
18825 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18831 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18832 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18833 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18834 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18835 // has only one use.
18836 SDNode *N = Op.getNode();
18837 SDValue LHS = N->getOperand(0);
18838 SDValue RHS = N->getOperand(1);
18839 unsigned BaseOp = 0;
18842 switch (Op.getOpcode()) {
18843 default: llvm_unreachable("Unknown ovf instruction!");
18845 // A subtract of one will be selected as a INC. Note that INC doesn't
18846 // set CF, so we can't do this for UADDO.
18847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18849 BaseOp = X86ISD::INC;
18850 Cond = X86::COND_O;
18853 BaseOp = X86ISD::ADD;
18854 Cond = X86::COND_O;
18857 BaseOp = X86ISD::ADD;
18858 Cond = X86::COND_B;
18861 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18862 // set CF, so we can't do this for USUBO.
18863 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18865 BaseOp = X86ISD::DEC;
18866 Cond = X86::COND_O;
18869 BaseOp = X86ISD::SUB;
18870 Cond = X86::COND_O;
18873 BaseOp = X86ISD::SUB;
18874 Cond = X86::COND_B;
18877 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18878 Cond = X86::COND_O;
18880 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18881 if (N->getValueType(0) == MVT::i8) {
18882 BaseOp = X86ISD::UMUL8;
18883 Cond = X86::COND_O;
18886 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18888 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18891 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18892 DAG.getConstant(X86::COND_O, MVT::i32),
18893 SDValue(Sum.getNode(), 2));
18895 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18899 // Also sets EFLAGS.
18900 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18901 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18904 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18905 DAG.getConstant(Cond, MVT::i32),
18906 SDValue(Sum.getNode(), 1));
18908 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18911 // Sign extension of the low part of vector elements. This may be used either
18912 // when sign extend instructions are not available or if the vector element
18913 // sizes already match the sign-extended size. If the vector elements are in
18914 // their pre-extended size and sign extend instructions are available, that will
18915 // be handled by LowerSIGN_EXTEND.
18916 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18917 SelectionDAG &DAG) const {
18919 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18920 MVT VT = Op.getSimpleValueType();
18922 if (!Subtarget->hasSSE2() || !VT.isVector())
18925 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18926 ExtraVT.getScalarType().getSizeInBits();
18928 switch (VT.SimpleTy) {
18929 default: return SDValue();
18932 if (!Subtarget->hasFp256())
18934 if (!Subtarget->hasInt256()) {
18935 // needs to be split
18936 unsigned NumElems = VT.getVectorNumElements();
18938 // Extract the LHS vectors
18939 SDValue LHS = Op.getOperand(0);
18940 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18941 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18943 MVT EltVT = VT.getVectorElementType();
18944 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18946 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18947 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18948 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18950 SDValue Extra = DAG.getValueType(ExtraVT);
18952 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18953 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18955 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18960 SDValue Op0 = Op.getOperand(0);
18962 // This is a sign extension of some low part of vector elements without
18963 // changing the size of the vector elements themselves:
18964 // Shift-Left + Shift-Right-Algebraic.
18965 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18967 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18973 /// Returns true if the operand type is exactly twice the native width, and
18974 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18975 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18976 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18977 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18978 const X86Subtarget &Subtarget =
18979 getTargetMachine().getSubtarget<X86Subtarget>();
18980 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18983 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18984 else if (OpWidth == 128)
18985 return Subtarget.hasCmpxchg16b();
18990 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18991 return needsCmpXchgNb(SI->getValueOperand()->getType());
18994 // Note: this turns large loads into lock cmpxchg8b/16b.
18995 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18996 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18997 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18998 return needsCmpXchgNb(PTy->getElementType());
19001 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19002 const X86Subtarget &Subtarget =
19003 getTargetMachine().getSubtarget<X86Subtarget>();
19004 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19005 const Type *MemType = AI->getType();
19007 // If the operand is too big, we must see if cmpxchg8/16b is available
19008 // and default to library calls otherwise.
19009 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19010 return needsCmpXchgNb(MemType);
19012 AtomicRMWInst::BinOp Op = AI->getOperation();
19015 llvm_unreachable("Unknown atomic operation");
19016 case AtomicRMWInst::Xchg:
19017 case AtomicRMWInst::Add:
19018 case AtomicRMWInst::Sub:
19019 // It's better to use xadd, xsub or xchg for these in all cases.
19021 case AtomicRMWInst::Or:
19022 case AtomicRMWInst::And:
19023 case AtomicRMWInst::Xor:
19024 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19025 // prefix to a normal instruction for these operations.
19026 return !AI->use_empty();
19027 case AtomicRMWInst::Nand:
19028 case AtomicRMWInst::Max:
19029 case AtomicRMWInst::Min:
19030 case AtomicRMWInst::UMax:
19031 case AtomicRMWInst::UMin:
19032 // These always require a non-trivial set of data operations on x86. We must
19033 // use a cmpxchg loop.
19038 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19039 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19040 // no-sse2). There isn't any reason to disable it if the target processor
19042 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19046 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19047 const X86Subtarget &Subtarget =
19048 getTargetMachine().getSubtarget<X86Subtarget>();
19049 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19050 const Type *MemType = AI->getType();
19051 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19052 // there is no benefit in turning such RMWs into loads, and it is actually
19053 // harmful as it introduces a mfence.
19054 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19057 auto Builder = IRBuilder<>(AI);
19058 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19059 auto SynchScope = AI->getSynchScope();
19060 // We must restrict the ordering to avoid generating loads with Release or
19061 // ReleaseAcquire orderings.
19062 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19063 auto Ptr = AI->getPointerOperand();
19065 // Before the load we need a fence. Here is an example lifted from
19066 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19069 // x.store(1, relaxed);
19070 // r1 = y.fetch_add(0, release);
19072 // y.fetch_add(42, acquire);
19073 // r2 = x.load(relaxed);
19074 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19075 // lowered to just a load without a fence. A mfence flushes the store buffer,
19076 // making the optimization clearly correct.
19077 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19078 // otherwise, we might be able to be more agressive on relaxed idempotent
19079 // rmw. In practice, they do not look useful, so we don't try to be
19080 // especially clever.
19081 if (SynchScope == SingleThread) {
19082 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19083 // the IR level, so we must wrap it in an intrinsic.
19085 } else if (hasMFENCE(Subtarget)) {
19086 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19087 Intrinsic::x86_sse2_mfence);
19088 Builder.CreateCall(MFence);
19090 // FIXME: it might make sense to use a locked operation here but on a
19091 // different cache-line to prevent cache-line bouncing. In practice it
19092 // is probably a small win, and x86 processors without mfence are rare
19093 // enough that we do not bother.
19097 // Finally we can emit the atomic load.
19098 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19099 AI->getType()->getPrimitiveSizeInBits());
19100 Loaded->setAtomic(Order, SynchScope);
19101 AI->replaceAllUsesWith(Loaded);
19102 AI->eraseFromParent();
19106 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19107 SelectionDAG &DAG) {
19109 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19110 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19111 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19112 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19114 // The only fence that needs an instruction is a sequentially-consistent
19115 // cross-thread fence.
19116 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19117 if (hasMFENCE(*Subtarget))
19118 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19120 SDValue Chain = Op.getOperand(0);
19121 SDValue Zero = DAG.getConstant(0, MVT::i32);
19123 DAG.getRegister(X86::ESP, MVT::i32), // Base
19124 DAG.getTargetConstant(1, MVT::i8), // Scale
19125 DAG.getRegister(0, MVT::i32), // Index
19126 DAG.getTargetConstant(0, MVT::i32), // Disp
19127 DAG.getRegister(0, MVT::i32), // Segment.
19131 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19132 return SDValue(Res, 0);
19135 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19136 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19139 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19140 SelectionDAG &DAG) {
19141 MVT T = Op.getSimpleValueType();
19145 switch(T.SimpleTy) {
19146 default: llvm_unreachable("Invalid value type!");
19147 case MVT::i8: Reg = X86::AL; size = 1; break;
19148 case MVT::i16: Reg = X86::AX; size = 2; break;
19149 case MVT::i32: Reg = X86::EAX; size = 4; break;
19151 assert(Subtarget->is64Bit() && "Node not type legal!");
19152 Reg = X86::RAX; size = 8;
19155 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19156 Op.getOperand(2), SDValue());
19157 SDValue Ops[] = { cpIn.getValue(0),
19160 DAG.getTargetConstant(size, MVT::i8),
19161 cpIn.getValue(1) };
19162 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19163 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19164 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19168 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19169 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19170 MVT::i32, cpOut.getValue(2));
19171 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19172 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19174 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19175 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19176 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19180 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19181 SelectionDAG &DAG) {
19182 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19183 MVT DstVT = Op.getSimpleValueType();
19185 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19186 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19187 if (DstVT != MVT::f64)
19188 // This conversion needs to be expanded.
19191 SDValue InVec = Op->getOperand(0);
19193 unsigned NumElts = SrcVT.getVectorNumElements();
19194 EVT SVT = SrcVT.getVectorElementType();
19196 // Widen the vector in input in the case of MVT::v2i32.
19197 // Example: from MVT::v2i32 to MVT::v4i32.
19198 SmallVector<SDValue, 16> Elts;
19199 for (unsigned i = 0, e = NumElts; i != e; ++i)
19200 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19201 DAG.getIntPtrConstant(i)));
19203 // Explicitly mark the extra elements as Undef.
19204 SDValue Undef = DAG.getUNDEF(SVT);
19205 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19206 Elts.push_back(Undef);
19208 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19209 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19210 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19211 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19212 DAG.getIntPtrConstant(0));
19215 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19216 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19217 assert((DstVT == MVT::i64 ||
19218 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19219 "Unexpected custom BITCAST");
19220 // i64 <=> MMX conversions are Legal.
19221 if (SrcVT==MVT::i64 && DstVT.isVector())
19223 if (DstVT==MVT::i64 && SrcVT.isVector())
19225 // MMX <=> MMX conversions are Legal.
19226 if (SrcVT.isVector() && DstVT.isVector())
19228 // All other conversions need to be expanded.
19232 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19233 SelectionDAG &DAG) {
19234 SDNode *Node = Op.getNode();
19237 Op = Op.getOperand(0);
19238 EVT VT = Op.getValueType();
19239 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19240 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19242 unsigned NumElts = VT.getVectorNumElements();
19243 EVT EltVT = VT.getVectorElementType();
19244 unsigned Len = EltVT.getSizeInBits();
19246 // This is the vectorized version of the "best" algorithm from
19247 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19248 // with a minor tweak to use a series of adds + shifts instead of vector
19249 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19251 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19252 // v8i32 => Always profitable
19254 // FIXME: There a couple of possible improvements:
19256 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19257 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19259 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19260 "CTPOP not implemented for this vector element type.");
19262 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19263 // extra legalization.
19264 bool NeedsBitcast = EltVT == MVT::i32;
19265 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19267 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19268 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19269 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19271 // v = v - ((v >> 1) & 0x55555555...)
19272 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19273 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19274 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19276 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19278 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19279 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19281 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19283 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19284 if (VT != And.getValueType())
19285 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19286 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19288 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19289 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19290 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19291 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19292 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19294 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19295 if (NeedsBitcast) {
19296 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19297 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19298 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19301 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19302 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19303 if (VT != AndRHS.getValueType()) {
19304 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19305 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19307 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19309 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19310 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19311 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19312 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19313 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19315 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19316 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19317 if (NeedsBitcast) {
19318 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19319 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19321 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19322 if (VT != And.getValueType())
19323 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19325 // The algorithm mentioned above uses:
19326 // v = (v * 0x01010101...) >> (Len - 8)
19328 // Change it to use vector adds + vector shifts which yield faster results on
19329 // Haswell than using vector integer multiplication.
19331 // For i32 elements:
19332 // v = v + (v >> 8)
19333 // v = v + (v >> 16)
19335 // For i64 elements:
19336 // v = v + (v >> 8)
19337 // v = v + (v >> 16)
19338 // v = v + (v >> 32)
19341 SmallVector<SDValue, 8> Csts;
19342 for (unsigned i = 8; i <= Len/2; i *= 2) {
19343 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19344 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19345 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19346 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19350 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19351 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19352 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19353 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19354 if (NeedsBitcast) {
19355 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19356 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19358 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19359 if (VT != And.getValueType())
19360 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19365 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19366 SDNode *Node = Op.getNode();
19368 EVT T = Node->getValueType(0);
19369 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19370 DAG.getConstant(0, T), Node->getOperand(2));
19371 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19372 cast<AtomicSDNode>(Node)->getMemoryVT(),
19373 Node->getOperand(0),
19374 Node->getOperand(1), negOp,
19375 cast<AtomicSDNode>(Node)->getMemOperand(),
19376 cast<AtomicSDNode>(Node)->getOrdering(),
19377 cast<AtomicSDNode>(Node)->getSynchScope());
19380 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19381 SDNode *Node = Op.getNode();
19383 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19385 // Convert seq_cst store -> xchg
19386 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19387 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19388 // (The only way to get a 16-byte store is cmpxchg16b)
19389 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19390 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19391 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19392 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19393 cast<AtomicSDNode>(Node)->getMemoryVT(),
19394 Node->getOperand(0),
19395 Node->getOperand(1), Node->getOperand(2),
19396 cast<AtomicSDNode>(Node)->getMemOperand(),
19397 cast<AtomicSDNode>(Node)->getOrdering(),
19398 cast<AtomicSDNode>(Node)->getSynchScope());
19399 return Swap.getValue(1);
19401 // Other atomic stores have a simple pattern.
19405 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19406 EVT VT = Op.getNode()->getSimpleValueType(0);
19408 // Let legalize expand this if it isn't a legal type yet.
19409 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19412 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19415 bool ExtraOp = false;
19416 switch (Op.getOpcode()) {
19417 default: llvm_unreachable("Invalid code");
19418 case ISD::ADDC: Opc = X86ISD::ADD; break;
19419 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19420 case ISD::SUBC: Opc = X86ISD::SUB; break;
19421 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19425 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19427 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19428 Op.getOperand(1), Op.getOperand(2));
19431 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19432 SelectionDAG &DAG) {
19433 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19435 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19436 // which returns the values as { float, float } (in XMM0) or
19437 // { double, double } (which is returned in XMM0, XMM1).
19439 SDValue Arg = Op.getOperand(0);
19440 EVT ArgVT = Arg.getValueType();
19441 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19443 TargetLowering::ArgListTy Args;
19444 TargetLowering::ArgListEntry Entry;
19448 Entry.isSExt = false;
19449 Entry.isZExt = false;
19450 Args.push_back(Entry);
19452 bool isF64 = ArgVT == MVT::f64;
19453 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19454 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19455 // the results are returned via SRet in memory.
19456 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19458 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19460 Type *RetTy = isF64
19461 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19462 : (Type*)VectorType::get(ArgTy, 4);
19464 TargetLowering::CallLoweringInfo CLI(DAG);
19465 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19466 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19468 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19471 // Returned in xmm0 and xmm1.
19472 return CallResult.first;
19474 // Returned in bits 0:31 and 32:64 xmm0.
19475 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19476 CallResult.first, DAG.getIntPtrConstant(0));
19477 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19478 CallResult.first, DAG.getIntPtrConstant(1));
19479 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19480 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19483 /// LowerOperation - Provide custom lowering hooks for some operations.
19485 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19486 switch (Op.getOpcode()) {
19487 default: llvm_unreachable("Should not custom lower this!");
19488 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19489 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19490 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19491 return LowerCMP_SWAP(Op, Subtarget, DAG);
19492 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19493 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19494 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19495 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19496 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19497 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19498 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19499 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19500 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19501 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19502 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19503 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19504 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19505 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19506 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19507 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19508 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19509 case ISD::SHL_PARTS:
19510 case ISD::SRA_PARTS:
19511 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19512 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19513 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19514 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19515 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19516 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19517 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19518 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19519 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19520 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19521 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19523 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19524 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19525 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19526 case ISD::SETCC: return LowerSETCC(Op, DAG);
19527 case ISD::SELECT: return LowerSELECT(Op, DAG);
19528 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19529 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19530 case ISD::VASTART: return LowerVASTART(Op, DAG);
19531 case ISD::VAARG: return LowerVAARG(Op, DAG);
19532 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19533 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19534 case ISD::INTRINSIC_VOID:
19535 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19536 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19537 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19538 case ISD::FRAME_TO_ARGS_OFFSET:
19539 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19540 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19541 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19542 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19543 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19544 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19545 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19546 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19547 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19548 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19549 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19550 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19551 case ISD::UMUL_LOHI:
19552 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19555 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19561 case ISD::UMULO: return LowerXALUO(Op, DAG);
19562 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19563 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19567 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19568 case ISD::ADD: return LowerADD(Op, DAG);
19569 case ISD::SUB: return LowerSUB(Op, DAG);
19570 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19574 /// ReplaceNodeResults - Replace a node with an illegal result type
19575 /// with a new node built out of custom code.
19576 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19577 SmallVectorImpl<SDValue>&Results,
19578 SelectionDAG &DAG) const {
19580 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19581 switch (N->getOpcode()) {
19583 llvm_unreachable("Do not know how to custom type legalize this operation!");
19584 case ISD::SIGN_EXTEND_INREG:
19589 // We don't want to expand or promote these.
19596 case ISD::UDIVREM: {
19597 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19598 Results.push_back(V);
19601 case ISD::FP_TO_SINT:
19602 case ISD::FP_TO_UINT: {
19603 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19605 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19608 std::pair<SDValue,SDValue> Vals =
19609 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19610 SDValue FIST = Vals.first, StackSlot = Vals.second;
19611 if (FIST.getNode()) {
19612 EVT VT = N->getValueType(0);
19613 // Return a load from the stack slot.
19614 if (StackSlot.getNode())
19615 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19616 MachinePointerInfo(),
19617 false, false, false, 0));
19619 Results.push_back(FIST);
19623 case ISD::UINT_TO_FP: {
19624 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19625 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19626 N->getValueType(0) != MVT::v2f32)
19628 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19630 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19632 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19633 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19634 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19635 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19636 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19637 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19640 case ISD::FP_ROUND: {
19641 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19643 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19644 Results.push_back(V);
19647 case ISD::INTRINSIC_W_CHAIN: {
19648 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19650 default : llvm_unreachable("Do not know how to custom type "
19651 "legalize this intrinsic operation!");
19652 case Intrinsic::x86_rdtsc:
19653 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19655 case Intrinsic::x86_rdtscp:
19656 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19658 case Intrinsic::x86_rdpmc:
19659 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19662 case ISD::READCYCLECOUNTER: {
19663 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19666 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19667 EVT T = N->getValueType(0);
19668 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19669 bool Regs64bit = T == MVT::i128;
19670 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19671 SDValue cpInL, cpInH;
19672 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19673 DAG.getConstant(0, HalfT));
19674 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19675 DAG.getConstant(1, HalfT));
19676 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19677 Regs64bit ? X86::RAX : X86::EAX,
19679 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19680 Regs64bit ? X86::RDX : X86::EDX,
19681 cpInH, cpInL.getValue(1));
19682 SDValue swapInL, swapInH;
19683 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19684 DAG.getConstant(0, HalfT));
19685 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19686 DAG.getConstant(1, HalfT));
19687 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19688 Regs64bit ? X86::RBX : X86::EBX,
19689 swapInL, cpInH.getValue(1));
19690 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19691 Regs64bit ? X86::RCX : X86::ECX,
19692 swapInH, swapInL.getValue(1));
19693 SDValue Ops[] = { swapInH.getValue(0),
19695 swapInH.getValue(1) };
19696 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19697 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19698 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19699 X86ISD::LCMPXCHG8_DAG;
19700 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19701 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19702 Regs64bit ? X86::RAX : X86::EAX,
19703 HalfT, Result.getValue(1));
19704 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19705 Regs64bit ? X86::RDX : X86::EDX,
19706 HalfT, cpOutL.getValue(2));
19707 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19709 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19710 MVT::i32, cpOutH.getValue(2));
19712 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19713 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19714 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19716 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19717 Results.push_back(Success);
19718 Results.push_back(EFLAGS.getValue(1));
19721 case ISD::ATOMIC_SWAP:
19722 case ISD::ATOMIC_LOAD_ADD:
19723 case ISD::ATOMIC_LOAD_SUB:
19724 case ISD::ATOMIC_LOAD_AND:
19725 case ISD::ATOMIC_LOAD_OR:
19726 case ISD::ATOMIC_LOAD_XOR:
19727 case ISD::ATOMIC_LOAD_NAND:
19728 case ISD::ATOMIC_LOAD_MIN:
19729 case ISD::ATOMIC_LOAD_MAX:
19730 case ISD::ATOMIC_LOAD_UMIN:
19731 case ISD::ATOMIC_LOAD_UMAX:
19732 case ISD::ATOMIC_LOAD: {
19733 // Delegate to generic TypeLegalization. Situations we can really handle
19734 // should have already been dealt with by AtomicExpandPass.cpp.
19737 case ISD::BITCAST: {
19738 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19739 EVT DstVT = N->getValueType(0);
19740 EVT SrcVT = N->getOperand(0)->getValueType(0);
19742 if (SrcVT != MVT::f64 ||
19743 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19746 unsigned NumElts = DstVT.getVectorNumElements();
19747 EVT SVT = DstVT.getVectorElementType();
19748 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19749 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19750 MVT::v2f64, N->getOperand(0));
19751 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19753 if (ExperimentalVectorWideningLegalization) {
19754 // If we are legalizing vectors by widening, we already have the desired
19755 // legal vector type, just return it.
19756 Results.push_back(ToVecInt);
19760 SmallVector<SDValue, 8> Elts;
19761 for (unsigned i = 0, e = NumElts; i != e; ++i)
19762 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19763 ToVecInt, DAG.getIntPtrConstant(i)));
19765 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19770 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19772 default: return nullptr;
19773 case X86ISD::BSF: return "X86ISD::BSF";
19774 case X86ISD::BSR: return "X86ISD::BSR";
19775 case X86ISD::SHLD: return "X86ISD::SHLD";
19776 case X86ISD::SHRD: return "X86ISD::SHRD";
19777 case X86ISD::FAND: return "X86ISD::FAND";
19778 case X86ISD::FANDN: return "X86ISD::FANDN";
19779 case X86ISD::FOR: return "X86ISD::FOR";
19780 case X86ISD::FXOR: return "X86ISD::FXOR";
19781 case X86ISD::FSRL: return "X86ISD::FSRL";
19782 case X86ISD::FILD: return "X86ISD::FILD";
19783 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19784 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19785 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19786 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19787 case X86ISD::FLD: return "X86ISD::FLD";
19788 case X86ISD::FST: return "X86ISD::FST";
19789 case X86ISD::CALL: return "X86ISD::CALL";
19790 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19791 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19792 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19793 case X86ISD::BT: return "X86ISD::BT";
19794 case X86ISD::CMP: return "X86ISD::CMP";
19795 case X86ISD::COMI: return "X86ISD::COMI";
19796 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19797 case X86ISD::CMPM: return "X86ISD::CMPM";
19798 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19799 case X86ISD::SETCC: return "X86ISD::SETCC";
19800 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19801 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19802 case X86ISD::CMOV: return "X86ISD::CMOV";
19803 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19804 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19805 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19806 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19807 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19808 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19809 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19810 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19811 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19812 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19813 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19814 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19815 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19816 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19817 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19818 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19819 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19820 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19821 case X86ISD::HADD: return "X86ISD::HADD";
19822 case X86ISD::HSUB: return "X86ISD::HSUB";
19823 case X86ISD::FHADD: return "X86ISD::FHADD";
19824 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19825 case X86ISD::UMAX: return "X86ISD::UMAX";
19826 case X86ISD::UMIN: return "X86ISD::UMIN";
19827 case X86ISD::SMAX: return "X86ISD::SMAX";
19828 case X86ISD::SMIN: return "X86ISD::SMIN";
19829 case X86ISD::FMAX: return "X86ISD::FMAX";
19830 case X86ISD::FMIN: return "X86ISD::FMIN";
19831 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19832 case X86ISD::FMINC: return "X86ISD::FMINC";
19833 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19834 case X86ISD::FRCP: return "X86ISD::FRCP";
19835 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19836 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19837 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19838 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19839 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19840 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19841 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19842 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19843 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19844 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19845 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19846 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19847 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19848 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19849 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19850 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19851 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19852 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19853 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19854 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19855 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19856 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19857 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19858 case X86ISD::VSHL: return "X86ISD::VSHL";
19859 case X86ISD::VSRL: return "X86ISD::VSRL";
19860 case X86ISD::VSRA: return "X86ISD::VSRA";
19861 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19862 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19863 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19864 case X86ISD::CMPP: return "X86ISD::CMPP";
19865 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19866 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19867 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19868 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19869 case X86ISD::ADD: return "X86ISD::ADD";
19870 case X86ISD::SUB: return "X86ISD::SUB";
19871 case X86ISD::ADC: return "X86ISD::ADC";
19872 case X86ISD::SBB: return "X86ISD::SBB";
19873 case X86ISD::SMUL: return "X86ISD::SMUL";
19874 case X86ISD::UMUL: return "X86ISD::UMUL";
19875 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19876 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19877 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19878 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19879 case X86ISD::INC: return "X86ISD::INC";
19880 case X86ISD::DEC: return "X86ISD::DEC";
19881 case X86ISD::OR: return "X86ISD::OR";
19882 case X86ISD::XOR: return "X86ISD::XOR";
19883 case X86ISD::AND: return "X86ISD::AND";
19884 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19885 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19886 case X86ISD::PTEST: return "X86ISD::PTEST";
19887 case X86ISD::TESTP: return "X86ISD::TESTP";
19888 case X86ISD::TESTM: return "X86ISD::TESTM";
19889 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19890 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19891 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19892 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19893 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19894 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19895 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19896 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19897 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19898 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19899 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19900 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19901 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19902 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19903 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19904 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19905 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19906 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19907 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19908 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19909 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19910 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19911 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19912 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19913 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19914 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19915 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19916 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19917 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19918 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19919 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19920 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19921 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19922 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19923 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19924 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19925 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19926 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19927 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19928 case X86ISD::SAHF: return "X86ISD::SAHF";
19929 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19930 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19931 case X86ISD::FMADD: return "X86ISD::FMADD";
19932 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19933 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19934 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19935 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19936 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19937 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19938 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19939 case X86ISD::XTEST: return "X86ISD::XTEST";
19940 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19941 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19942 case X86ISD::SELECT: return "X86ISD::SELECT";
19946 // isLegalAddressingMode - Return true if the addressing mode represented
19947 // by AM is legal for this target, for a load/store of the specified type.
19948 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19950 // X86 supports extremely general addressing modes.
19951 CodeModel::Model M = getTargetMachine().getCodeModel();
19952 Reloc::Model R = getTargetMachine().getRelocationModel();
19954 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19955 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19960 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19962 // If a reference to this global requires an extra load, we can't fold it.
19963 if (isGlobalStubReference(GVFlags))
19966 // If BaseGV requires a register for the PIC base, we cannot also have a
19967 // BaseReg specified.
19968 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19971 // If lower 4G is not available, then we must use rip-relative addressing.
19972 if ((M != CodeModel::Small || R != Reloc::Static) &&
19973 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19977 switch (AM.Scale) {
19983 // These scales always work.
19988 // These scales are formed with basereg+scalereg. Only accept if there is
19993 default: // Other stuff never works.
20000 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20001 unsigned Bits = Ty->getScalarSizeInBits();
20003 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20004 // particularly cheaper than those without.
20008 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20009 // variable shifts just as cheap as scalar ones.
20010 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20013 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20014 // fully general vector.
20018 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20019 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20021 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20022 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20023 return NumBits1 > NumBits2;
20026 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20027 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20030 if (!isTypeLegal(EVT::getEVT(Ty1)))
20033 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20035 // Assuming the caller doesn't have a zeroext or signext return parameter,
20036 // truncation all the way down to i1 is valid.
20040 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20041 return isInt<32>(Imm);
20044 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20045 // Can also use sub to handle negated immediates.
20046 return isInt<32>(Imm);
20049 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20050 if (!VT1.isInteger() || !VT2.isInteger())
20052 unsigned NumBits1 = VT1.getSizeInBits();
20053 unsigned NumBits2 = VT2.getSizeInBits();
20054 return NumBits1 > NumBits2;
20057 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20058 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20059 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20062 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20063 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20064 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20067 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20068 EVT VT1 = Val.getValueType();
20069 if (isZExtFree(VT1, VT2))
20072 if (Val.getOpcode() != ISD::LOAD)
20075 if (!VT1.isSimple() || !VT1.isInteger() ||
20076 !VT2.isSimple() || !VT2.isInteger())
20079 switch (VT1.getSimpleVT().SimpleTy) {
20084 // X86 has 8, 16, and 32-bit zero-extending loads.
20092 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20093 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20096 VT = VT.getScalarType();
20098 if (!VT.isSimple())
20101 switch (VT.getSimpleVT().SimpleTy) {
20112 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20113 // i16 instructions are longer (0x66 prefix) and potentially slower.
20114 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20117 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20118 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20119 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20120 /// are assumed to be legal.
20122 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20124 if (!VT.isSimple())
20127 MVT SVT = VT.getSimpleVT();
20129 // Very little shuffling can be done for 64-bit vectors right now.
20130 if (VT.getSizeInBits() == 64)
20133 // If this is a single-input shuffle with no 128 bit lane crossings we can
20134 // lower it into pshufb.
20135 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20136 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20137 bool isLegal = true;
20138 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20139 if (M[I] >= (int)SVT.getVectorNumElements() ||
20140 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20149 // FIXME: blends, shifts.
20150 return (SVT.getVectorNumElements() == 2 ||
20151 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20152 isMOVLMask(M, SVT) ||
20153 isCommutedMOVLMask(M, SVT) ||
20154 isMOVHLPSMask(M, SVT) ||
20155 isSHUFPMask(M, SVT) ||
20156 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20157 isPSHUFDMask(M, SVT) ||
20158 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20159 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20160 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20161 isPALIGNRMask(M, SVT, Subtarget) ||
20162 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20163 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20164 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20165 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20166 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20167 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20171 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20173 if (!VT.isSimple())
20176 MVT SVT = VT.getSimpleVT();
20177 unsigned NumElts = SVT.getVectorNumElements();
20178 // FIXME: This collection of masks seems suspect.
20181 if (NumElts == 4 && SVT.is128BitVector()) {
20182 return (isMOVLMask(Mask, SVT) ||
20183 isCommutedMOVLMask(Mask, SVT, true) ||
20184 isSHUFPMask(Mask, SVT) ||
20185 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20186 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20187 Subtarget->hasInt256()));
20192 //===----------------------------------------------------------------------===//
20193 // X86 Scheduler Hooks
20194 //===----------------------------------------------------------------------===//
20196 /// Utility function to emit xbegin specifying the start of an RTM region.
20197 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20198 const TargetInstrInfo *TII) {
20199 DebugLoc DL = MI->getDebugLoc();
20201 const BasicBlock *BB = MBB->getBasicBlock();
20202 MachineFunction::iterator I = MBB;
20205 // For the v = xbegin(), we generate
20216 MachineBasicBlock *thisMBB = MBB;
20217 MachineFunction *MF = MBB->getParent();
20218 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20219 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20220 MF->insert(I, mainMBB);
20221 MF->insert(I, sinkMBB);
20223 // Transfer the remainder of BB and its successor edges to sinkMBB.
20224 sinkMBB->splice(sinkMBB->begin(), MBB,
20225 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20226 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20230 // # fallthrough to mainMBB
20231 // # abortion to sinkMBB
20232 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20233 thisMBB->addSuccessor(mainMBB);
20234 thisMBB->addSuccessor(sinkMBB);
20238 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20239 mainMBB->addSuccessor(sinkMBB);
20242 // EAX is live into the sinkMBB
20243 sinkMBB->addLiveIn(X86::EAX);
20244 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20245 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20248 MI->eraseFromParent();
20252 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20253 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20254 // in the .td file.
20255 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20256 const TargetInstrInfo *TII) {
20258 switch (MI->getOpcode()) {
20259 default: llvm_unreachable("illegal opcode!");
20260 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20261 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20262 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20263 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20264 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20265 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20266 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20267 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20270 DebugLoc dl = MI->getDebugLoc();
20271 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20273 unsigned NumArgs = MI->getNumOperands();
20274 for (unsigned i = 1; i < NumArgs; ++i) {
20275 MachineOperand &Op = MI->getOperand(i);
20276 if (!(Op.isReg() && Op.isImplicit()))
20277 MIB.addOperand(Op);
20279 if (MI->hasOneMemOperand())
20280 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20282 BuildMI(*BB, MI, dl,
20283 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20284 .addReg(X86::XMM0);
20286 MI->eraseFromParent();
20290 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20291 // defs in an instruction pattern
20292 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20293 const TargetInstrInfo *TII) {
20295 switch (MI->getOpcode()) {
20296 default: llvm_unreachable("illegal opcode!");
20297 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20298 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20299 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20300 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20301 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20302 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20303 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20304 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20307 DebugLoc dl = MI->getDebugLoc();
20308 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20310 unsigned NumArgs = MI->getNumOperands(); // remove the results
20311 for (unsigned i = 1; i < NumArgs; ++i) {
20312 MachineOperand &Op = MI->getOperand(i);
20313 if (!(Op.isReg() && Op.isImplicit()))
20314 MIB.addOperand(Op);
20316 if (MI->hasOneMemOperand())
20317 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20319 BuildMI(*BB, MI, dl,
20320 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20323 MI->eraseFromParent();
20327 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20328 const TargetInstrInfo *TII,
20329 const X86Subtarget* Subtarget) {
20330 DebugLoc dl = MI->getDebugLoc();
20332 // Address into RAX/EAX, other two args into ECX, EDX.
20333 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20334 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20335 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20336 for (int i = 0; i < X86::AddrNumOperands; ++i)
20337 MIB.addOperand(MI->getOperand(i));
20339 unsigned ValOps = X86::AddrNumOperands;
20340 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20341 .addReg(MI->getOperand(ValOps).getReg());
20342 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20343 .addReg(MI->getOperand(ValOps+1).getReg());
20345 // The instruction doesn't actually take any operands though.
20346 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20348 MI->eraseFromParent(); // The pseudo is gone now.
20352 MachineBasicBlock *
20353 X86TargetLowering::EmitVAARG64WithCustomInserter(
20355 MachineBasicBlock *MBB) const {
20356 // Emit va_arg instruction on X86-64.
20358 // Operands to this pseudo-instruction:
20359 // 0 ) Output : destination address (reg)
20360 // 1-5) Input : va_list address (addr, i64mem)
20361 // 6 ) ArgSize : Size (in bytes) of vararg type
20362 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20363 // 8 ) Align : Alignment of type
20364 // 9 ) EFLAGS (implicit-def)
20366 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20367 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20369 unsigned DestReg = MI->getOperand(0).getReg();
20370 MachineOperand &Base = MI->getOperand(1);
20371 MachineOperand &Scale = MI->getOperand(2);
20372 MachineOperand &Index = MI->getOperand(3);
20373 MachineOperand &Disp = MI->getOperand(4);
20374 MachineOperand &Segment = MI->getOperand(5);
20375 unsigned ArgSize = MI->getOperand(6).getImm();
20376 unsigned ArgMode = MI->getOperand(7).getImm();
20377 unsigned Align = MI->getOperand(8).getImm();
20379 // Memory Reference
20380 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20381 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20382 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20384 // Machine Information
20385 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20386 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20387 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20388 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20389 DebugLoc DL = MI->getDebugLoc();
20391 // struct va_list {
20394 // i64 overflow_area (address)
20395 // i64 reg_save_area (address)
20397 // sizeof(va_list) = 24
20398 // alignment(va_list) = 8
20400 unsigned TotalNumIntRegs = 6;
20401 unsigned TotalNumXMMRegs = 8;
20402 bool UseGPOffset = (ArgMode == 1);
20403 bool UseFPOffset = (ArgMode == 2);
20404 unsigned MaxOffset = TotalNumIntRegs * 8 +
20405 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20407 /* Align ArgSize to a multiple of 8 */
20408 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20409 bool NeedsAlign = (Align > 8);
20411 MachineBasicBlock *thisMBB = MBB;
20412 MachineBasicBlock *overflowMBB;
20413 MachineBasicBlock *offsetMBB;
20414 MachineBasicBlock *endMBB;
20416 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20417 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20418 unsigned OffsetReg = 0;
20420 if (!UseGPOffset && !UseFPOffset) {
20421 // If we only pull from the overflow region, we don't create a branch.
20422 // We don't need to alter control flow.
20423 OffsetDestReg = 0; // unused
20424 OverflowDestReg = DestReg;
20426 offsetMBB = nullptr;
20427 overflowMBB = thisMBB;
20430 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20431 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20432 // If not, pull from overflow_area. (branch to overflowMBB)
20437 // offsetMBB overflowMBB
20442 // Registers for the PHI in endMBB
20443 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20444 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20446 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20447 MachineFunction *MF = MBB->getParent();
20448 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20449 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20450 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20452 MachineFunction::iterator MBBIter = MBB;
20455 // Insert the new basic blocks
20456 MF->insert(MBBIter, offsetMBB);
20457 MF->insert(MBBIter, overflowMBB);
20458 MF->insert(MBBIter, endMBB);
20460 // Transfer the remainder of MBB and its successor edges to endMBB.
20461 endMBB->splice(endMBB->begin(), thisMBB,
20462 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20463 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20465 // Make offsetMBB and overflowMBB successors of thisMBB
20466 thisMBB->addSuccessor(offsetMBB);
20467 thisMBB->addSuccessor(overflowMBB);
20469 // endMBB is a successor of both offsetMBB and overflowMBB
20470 offsetMBB->addSuccessor(endMBB);
20471 overflowMBB->addSuccessor(endMBB);
20473 // Load the offset value into a register
20474 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20475 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20479 .addDisp(Disp, UseFPOffset ? 4 : 0)
20480 .addOperand(Segment)
20481 .setMemRefs(MMOBegin, MMOEnd);
20483 // Check if there is enough room left to pull this argument.
20484 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20486 .addImm(MaxOffset + 8 - ArgSizeA8);
20488 // Branch to "overflowMBB" if offset >= max
20489 // Fall through to "offsetMBB" otherwise
20490 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20491 .addMBB(overflowMBB);
20494 // In offsetMBB, emit code to use the reg_save_area.
20496 assert(OffsetReg != 0);
20498 // Read the reg_save_area address.
20499 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20500 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20505 .addOperand(Segment)
20506 .setMemRefs(MMOBegin, MMOEnd);
20508 // Zero-extend the offset
20509 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20510 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20513 .addImm(X86::sub_32bit);
20515 // Add the offset to the reg_save_area to get the final address.
20516 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20517 .addReg(OffsetReg64)
20518 .addReg(RegSaveReg);
20520 // Compute the offset for the next argument
20521 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20522 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20524 .addImm(UseFPOffset ? 16 : 8);
20526 // Store it back into the va_list.
20527 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20531 .addDisp(Disp, UseFPOffset ? 4 : 0)
20532 .addOperand(Segment)
20533 .addReg(NextOffsetReg)
20534 .setMemRefs(MMOBegin, MMOEnd);
20537 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20542 // Emit code to use overflow area
20545 // Load the overflow_area address into a register.
20546 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20547 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20552 .addOperand(Segment)
20553 .setMemRefs(MMOBegin, MMOEnd);
20555 // If we need to align it, do so. Otherwise, just copy the address
20556 // to OverflowDestReg.
20558 // Align the overflow address
20559 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20560 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20562 // aligned_addr = (addr + (align-1)) & ~(align-1)
20563 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20564 .addReg(OverflowAddrReg)
20567 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20569 .addImm(~(uint64_t)(Align-1));
20571 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20572 .addReg(OverflowAddrReg);
20575 // Compute the next overflow address after this argument.
20576 // (the overflow address should be kept 8-byte aligned)
20577 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20578 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20579 .addReg(OverflowDestReg)
20580 .addImm(ArgSizeA8);
20582 // Store the new overflow address.
20583 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20588 .addOperand(Segment)
20589 .addReg(NextAddrReg)
20590 .setMemRefs(MMOBegin, MMOEnd);
20592 // If we branched, emit the PHI to the front of endMBB.
20594 BuildMI(*endMBB, endMBB->begin(), DL,
20595 TII->get(X86::PHI), DestReg)
20596 .addReg(OffsetDestReg).addMBB(offsetMBB)
20597 .addReg(OverflowDestReg).addMBB(overflowMBB);
20600 // Erase the pseudo instruction
20601 MI->eraseFromParent();
20606 MachineBasicBlock *
20607 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20609 MachineBasicBlock *MBB) const {
20610 // Emit code to save XMM registers to the stack. The ABI says that the
20611 // number of registers to save is given in %al, so it's theoretically
20612 // possible to do an indirect jump trick to avoid saving all of them,
20613 // however this code takes a simpler approach and just executes all
20614 // of the stores if %al is non-zero. It's less code, and it's probably
20615 // easier on the hardware branch predictor, and stores aren't all that
20616 // expensive anyway.
20618 // Create the new basic blocks. One block contains all the XMM stores,
20619 // and one block is the final destination regardless of whether any
20620 // stores were performed.
20621 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20622 MachineFunction *F = MBB->getParent();
20623 MachineFunction::iterator MBBIter = MBB;
20625 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20626 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20627 F->insert(MBBIter, XMMSaveMBB);
20628 F->insert(MBBIter, EndMBB);
20630 // Transfer the remainder of MBB and its successor edges to EndMBB.
20631 EndMBB->splice(EndMBB->begin(), MBB,
20632 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20633 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20635 // The original block will now fall through to the XMM save block.
20636 MBB->addSuccessor(XMMSaveMBB);
20637 // The XMMSaveMBB will fall through to the end block.
20638 XMMSaveMBB->addSuccessor(EndMBB);
20640 // Now add the instructions.
20641 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20642 DebugLoc DL = MI->getDebugLoc();
20644 unsigned CountReg = MI->getOperand(0).getReg();
20645 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20646 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20648 if (!Subtarget->isTargetWin64()) {
20649 // If %al is 0, branch around the XMM save block.
20650 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20651 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20652 MBB->addSuccessor(EndMBB);
20655 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20656 // that was just emitted, but clearly shouldn't be "saved".
20657 assert((MI->getNumOperands() <= 3 ||
20658 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20659 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20660 && "Expected last argument to be EFLAGS");
20661 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20662 // In the XMM save block, save all the XMM argument registers.
20663 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20664 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20665 MachineMemOperand *MMO =
20666 F->getMachineMemOperand(
20667 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20668 MachineMemOperand::MOStore,
20669 /*Size=*/16, /*Align=*/16);
20670 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20671 .addFrameIndex(RegSaveFrameIndex)
20672 .addImm(/*Scale=*/1)
20673 .addReg(/*IndexReg=*/0)
20674 .addImm(/*Disp=*/Offset)
20675 .addReg(/*Segment=*/0)
20676 .addReg(MI->getOperand(i).getReg())
20677 .addMemOperand(MMO);
20680 MI->eraseFromParent(); // The pseudo instruction is gone now.
20685 // The EFLAGS operand of SelectItr might be missing a kill marker
20686 // because there were multiple uses of EFLAGS, and ISel didn't know
20687 // which to mark. Figure out whether SelectItr should have had a
20688 // kill marker, and set it if it should. Returns the correct kill
20690 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20691 MachineBasicBlock* BB,
20692 const TargetRegisterInfo* TRI) {
20693 // Scan forward through BB for a use/def of EFLAGS.
20694 MachineBasicBlock::iterator miI(std::next(SelectItr));
20695 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20696 const MachineInstr& mi = *miI;
20697 if (mi.readsRegister(X86::EFLAGS))
20699 if (mi.definesRegister(X86::EFLAGS))
20700 break; // Should have kill-flag - update below.
20703 // If we hit the end of the block, check whether EFLAGS is live into a
20705 if (miI == BB->end()) {
20706 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20707 sEnd = BB->succ_end();
20708 sItr != sEnd; ++sItr) {
20709 MachineBasicBlock* succ = *sItr;
20710 if (succ->isLiveIn(X86::EFLAGS))
20715 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20716 // out. SelectMI should have a kill flag on EFLAGS.
20717 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20721 MachineBasicBlock *
20722 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20723 MachineBasicBlock *BB) const {
20724 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20725 DebugLoc DL = MI->getDebugLoc();
20727 // To "insert" a SELECT_CC instruction, we actually have to insert the
20728 // diamond control-flow pattern. The incoming instruction knows the
20729 // destination vreg to set, the condition code register to branch on, the
20730 // true/false values to select between, and a branch opcode to use.
20731 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20732 MachineFunction::iterator It = BB;
20738 // cmpTY ccX, r1, r2
20740 // fallthrough --> copy0MBB
20741 MachineBasicBlock *thisMBB = BB;
20742 MachineFunction *F = BB->getParent();
20743 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20744 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20745 F->insert(It, copy0MBB);
20746 F->insert(It, sinkMBB);
20748 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20749 // live into the sink and copy blocks.
20750 const TargetRegisterInfo *TRI =
20751 BB->getParent()->getSubtarget().getRegisterInfo();
20752 if (!MI->killsRegister(X86::EFLAGS) &&
20753 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20754 copy0MBB->addLiveIn(X86::EFLAGS);
20755 sinkMBB->addLiveIn(X86::EFLAGS);
20758 // Transfer the remainder of BB and its successor edges to sinkMBB.
20759 sinkMBB->splice(sinkMBB->begin(), BB,
20760 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20761 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20763 // Add the true and fallthrough blocks as its successors.
20764 BB->addSuccessor(copy0MBB);
20765 BB->addSuccessor(sinkMBB);
20767 // Create the conditional branch instruction.
20769 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20770 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20773 // %FalseValue = ...
20774 // # fallthrough to sinkMBB
20775 copy0MBB->addSuccessor(sinkMBB);
20778 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20780 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20781 TII->get(X86::PHI), MI->getOperand(0).getReg())
20782 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20783 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20785 MI->eraseFromParent(); // The pseudo instruction is gone now.
20789 MachineBasicBlock *
20790 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20791 MachineBasicBlock *BB) const {
20792 MachineFunction *MF = BB->getParent();
20793 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20794 DebugLoc DL = MI->getDebugLoc();
20795 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20797 assert(MF->shouldSplitStack());
20799 const bool Is64Bit = Subtarget->is64Bit();
20800 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20802 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20803 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20806 // ... [Till the alloca]
20807 // If stacklet is not large enough, jump to mallocMBB
20810 // Allocate by subtracting from RSP
20811 // Jump to continueMBB
20814 // Allocate by call to runtime
20818 // [rest of original BB]
20821 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20822 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20823 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20825 MachineRegisterInfo &MRI = MF->getRegInfo();
20826 const TargetRegisterClass *AddrRegClass =
20827 getRegClassFor(getPointerTy());
20829 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20830 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20831 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20832 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20833 sizeVReg = MI->getOperand(1).getReg(),
20834 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20836 MachineFunction::iterator MBBIter = BB;
20839 MF->insert(MBBIter, bumpMBB);
20840 MF->insert(MBBIter, mallocMBB);
20841 MF->insert(MBBIter, continueMBB);
20843 continueMBB->splice(continueMBB->begin(), BB,
20844 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20845 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20847 // Add code to the main basic block to check if the stack limit has been hit,
20848 // and if so, jump to mallocMBB otherwise to bumpMBB.
20849 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20850 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20851 .addReg(tmpSPVReg).addReg(sizeVReg);
20852 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20853 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20854 .addReg(SPLimitVReg);
20855 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20857 // bumpMBB simply decreases the stack pointer, since we know the current
20858 // stacklet has enough space.
20859 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20860 .addReg(SPLimitVReg);
20861 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20862 .addReg(SPLimitVReg);
20863 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20865 // Calls into a routine in libgcc to allocate more space from the heap.
20866 const uint32_t *RegMask = MF->getTarget()
20867 .getSubtargetImpl()
20868 ->getRegisterInfo()
20869 ->getCallPreservedMask(CallingConv::C);
20871 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20873 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20874 .addExternalSymbol("__morestack_allocate_stack_space")
20875 .addRegMask(RegMask)
20876 .addReg(X86::RDI, RegState::Implicit)
20877 .addReg(X86::RAX, RegState::ImplicitDefine);
20878 } else if (Is64Bit) {
20879 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20881 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20882 .addExternalSymbol("__morestack_allocate_stack_space")
20883 .addRegMask(RegMask)
20884 .addReg(X86::EDI, RegState::Implicit)
20885 .addReg(X86::EAX, RegState::ImplicitDefine);
20887 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20889 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20890 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20891 .addExternalSymbol("__morestack_allocate_stack_space")
20892 .addRegMask(RegMask)
20893 .addReg(X86::EAX, RegState::ImplicitDefine);
20897 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20900 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20901 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20902 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20904 // Set up the CFG correctly.
20905 BB->addSuccessor(bumpMBB);
20906 BB->addSuccessor(mallocMBB);
20907 mallocMBB->addSuccessor(continueMBB);
20908 bumpMBB->addSuccessor(continueMBB);
20910 // Take care of the PHI nodes.
20911 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20912 MI->getOperand(0).getReg())
20913 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20914 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20916 // Delete the original pseudo instruction.
20917 MI->eraseFromParent();
20920 return continueMBB;
20923 MachineBasicBlock *
20924 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20925 MachineBasicBlock *BB) const {
20926 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20927 DebugLoc DL = MI->getDebugLoc();
20929 assert(!Subtarget->isTargetMachO());
20931 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20932 // non-trivial part is impdef of ESP.
20934 if (Subtarget->isTargetWin64()) {
20935 if (Subtarget->isTargetCygMing()) {
20936 // ___chkstk(Mingw64):
20937 // Clobbers R10, R11, RAX and EFLAGS.
20939 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20940 .addExternalSymbol("___chkstk")
20941 .addReg(X86::RAX, RegState::Implicit)
20942 .addReg(X86::RSP, RegState::Implicit)
20943 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20944 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20945 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20947 // __chkstk(MSVCRT): does not update stack pointer.
20948 // Clobbers R10, R11 and EFLAGS.
20949 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20950 .addExternalSymbol("__chkstk")
20951 .addReg(X86::RAX, RegState::Implicit)
20952 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20953 // RAX has the offset to be subtracted from RSP.
20954 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20959 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20960 Subtarget->isTargetWindowsItanium())
20964 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20965 .addExternalSymbol(StackProbeSymbol)
20966 .addReg(X86::EAX, RegState::Implicit)
20967 .addReg(X86::ESP, RegState::Implicit)
20968 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20969 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20970 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20973 MI->eraseFromParent(); // The pseudo instruction is gone now.
20977 MachineBasicBlock *
20978 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20979 MachineBasicBlock *BB) const {
20980 // This is pretty easy. We're taking the value that we received from
20981 // our load from the relocation, sticking it in either RDI (x86-64)
20982 // or EAX and doing an indirect call. The return value will then
20983 // be in the normal return register.
20984 MachineFunction *F = BB->getParent();
20985 const X86InstrInfo *TII =
20986 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20987 DebugLoc DL = MI->getDebugLoc();
20989 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20990 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20992 // Get a register mask for the lowered call.
20993 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20994 // proper register mask.
20995 const uint32_t *RegMask = F->getTarget()
20996 .getSubtargetImpl()
20997 ->getRegisterInfo()
20998 ->getCallPreservedMask(CallingConv::C);
20999 if (Subtarget->is64Bit()) {
21000 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21001 TII->get(X86::MOV64rm), X86::RDI)
21003 .addImm(0).addReg(0)
21004 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21005 MI->getOperand(3).getTargetFlags())
21007 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21008 addDirectMem(MIB, X86::RDI);
21009 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21010 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21011 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21012 TII->get(X86::MOV32rm), X86::EAX)
21014 .addImm(0).addReg(0)
21015 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21016 MI->getOperand(3).getTargetFlags())
21018 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21019 addDirectMem(MIB, X86::EAX);
21020 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21022 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21023 TII->get(X86::MOV32rm), X86::EAX)
21024 .addReg(TII->getGlobalBaseReg(F))
21025 .addImm(0).addReg(0)
21026 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21027 MI->getOperand(3).getTargetFlags())
21029 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21030 addDirectMem(MIB, X86::EAX);
21031 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21034 MI->eraseFromParent(); // The pseudo instruction is gone now.
21038 MachineBasicBlock *
21039 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21040 MachineBasicBlock *MBB) const {
21041 DebugLoc DL = MI->getDebugLoc();
21042 MachineFunction *MF = MBB->getParent();
21043 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21044 MachineRegisterInfo &MRI = MF->getRegInfo();
21046 const BasicBlock *BB = MBB->getBasicBlock();
21047 MachineFunction::iterator I = MBB;
21050 // Memory Reference
21051 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21052 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21055 unsigned MemOpndSlot = 0;
21057 unsigned CurOp = 0;
21059 DstReg = MI->getOperand(CurOp++).getReg();
21060 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21061 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21062 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21063 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21065 MemOpndSlot = CurOp;
21067 MVT PVT = getPointerTy();
21068 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21069 "Invalid Pointer Size!");
21071 // For v = setjmp(buf), we generate
21074 // buf[LabelOffset] = restoreMBB
21075 // SjLjSetup restoreMBB
21081 // v = phi(main, restore)
21084 // if base pointer being used, load it from frame
21087 MachineBasicBlock *thisMBB = MBB;
21088 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21089 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21090 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21091 MF->insert(I, mainMBB);
21092 MF->insert(I, sinkMBB);
21093 MF->push_back(restoreMBB);
21095 MachineInstrBuilder MIB;
21097 // Transfer the remainder of BB and its successor edges to sinkMBB.
21098 sinkMBB->splice(sinkMBB->begin(), MBB,
21099 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21100 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21103 unsigned PtrStoreOpc = 0;
21104 unsigned LabelReg = 0;
21105 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21106 Reloc::Model RM = MF->getTarget().getRelocationModel();
21107 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21108 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21110 // Prepare IP either in reg or imm.
21111 if (!UseImmLabel) {
21112 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21113 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21114 LabelReg = MRI.createVirtualRegister(PtrRC);
21115 if (Subtarget->is64Bit()) {
21116 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21120 .addMBB(restoreMBB)
21123 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21124 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21125 .addReg(XII->getGlobalBaseReg(MF))
21128 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21132 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21134 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21135 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21136 if (i == X86::AddrDisp)
21137 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21139 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21142 MIB.addReg(LabelReg);
21144 MIB.addMBB(restoreMBB);
21145 MIB.setMemRefs(MMOBegin, MMOEnd);
21147 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21148 .addMBB(restoreMBB);
21150 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21151 MF->getSubtarget().getRegisterInfo());
21152 MIB.addRegMask(RegInfo->getNoPreservedMask());
21153 thisMBB->addSuccessor(mainMBB);
21154 thisMBB->addSuccessor(restoreMBB);
21158 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21159 mainMBB->addSuccessor(sinkMBB);
21162 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21163 TII->get(X86::PHI), DstReg)
21164 .addReg(mainDstReg).addMBB(mainMBB)
21165 .addReg(restoreDstReg).addMBB(restoreMBB);
21168 if (RegInfo->hasBasePointer(*MF)) {
21169 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21170 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21171 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21172 X86FI->setRestoreBasePointer(MF);
21173 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21174 unsigned BasePtr = RegInfo->getBaseRegister();
21175 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21176 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21177 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21178 .setMIFlag(MachineInstr::FrameSetup);
21180 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21181 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21182 restoreMBB->addSuccessor(sinkMBB);
21184 MI->eraseFromParent();
21188 MachineBasicBlock *
21189 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21190 MachineBasicBlock *MBB) const {
21191 DebugLoc DL = MI->getDebugLoc();
21192 MachineFunction *MF = MBB->getParent();
21193 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21194 MachineRegisterInfo &MRI = MF->getRegInfo();
21196 // Memory Reference
21197 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21198 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21200 MVT PVT = getPointerTy();
21201 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21202 "Invalid Pointer Size!");
21204 const TargetRegisterClass *RC =
21205 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21206 unsigned Tmp = MRI.createVirtualRegister(RC);
21207 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21208 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21209 MF->getSubtarget().getRegisterInfo());
21210 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21211 unsigned SP = RegInfo->getStackRegister();
21213 MachineInstrBuilder MIB;
21215 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21216 const int64_t SPOffset = 2 * PVT.getStoreSize();
21218 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21219 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21222 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21223 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21224 MIB.addOperand(MI->getOperand(i));
21225 MIB.setMemRefs(MMOBegin, MMOEnd);
21227 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21228 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21229 if (i == X86::AddrDisp)
21230 MIB.addDisp(MI->getOperand(i), LabelOffset);
21232 MIB.addOperand(MI->getOperand(i));
21234 MIB.setMemRefs(MMOBegin, MMOEnd);
21236 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21237 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21238 if (i == X86::AddrDisp)
21239 MIB.addDisp(MI->getOperand(i), SPOffset);
21241 MIB.addOperand(MI->getOperand(i));
21243 MIB.setMemRefs(MMOBegin, MMOEnd);
21245 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21247 MI->eraseFromParent();
21251 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21252 // accumulator loops. Writing back to the accumulator allows the coalescer
21253 // to remove extra copies in the loop.
21254 MachineBasicBlock *
21255 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21256 MachineBasicBlock *MBB) const {
21257 MachineOperand &AddendOp = MI->getOperand(3);
21259 // Bail out early if the addend isn't a register - we can't switch these.
21260 if (!AddendOp.isReg())
21263 MachineFunction &MF = *MBB->getParent();
21264 MachineRegisterInfo &MRI = MF.getRegInfo();
21266 // Check whether the addend is defined by a PHI:
21267 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21268 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21269 if (!AddendDef.isPHI())
21272 // Look for the following pattern:
21274 // %addend = phi [%entry, 0], [%loop, %result]
21276 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21280 // %addend = phi [%entry, 0], [%loop, %result]
21282 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21284 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21285 assert(AddendDef.getOperand(i).isReg());
21286 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21287 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21288 if (&PHISrcInst == MI) {
21289 // Found a matching instruction.
21290 unsigned NewFMAOpc = 0;
21291 switch (MI->getOpcode()) {
21292 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21293 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21294 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21295 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21296 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21297 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21298 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21299 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21300 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21301 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21302 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21303 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21304 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21305 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21306 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21307 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21308 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21309 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21310 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21311 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21313 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21314 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21315 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21316 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21317 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21318 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21319 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21320 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21321 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21322 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21323 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21324 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21325 default: llvm_unreachable("Unrecognized FMA variant.");
21328 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21329 MachineInstrBuilder MIB =
21330 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21331 .addOperand(MI->getOperand(0))
21332 .addOperand(MI->getOperand(3))
21333 .addOperand(MI->getOperand(2))
21334 .addOperand(MI->getOperand(1));
21335 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21336 MI->eraseFromParent();
21343 MachineBasicBlock *
21344 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21345 MachineBasicBlock *BB) const {
21346 switch (MI->getOpcode()) {
21347 default: llvm_unreachable("Unexpected instr type to insert");
21348 case X86::TAILJMPd64:
21349 case X86::TAILJMPr64:
21350 case X86::TAILJMPm64:
21351 llvm_unreachable("TAILJMP64 would not be touched here.");
21352 case X86::TCRETURNdi64:
21353 case X86::TCRETURNri64:
21354 case X86::TCRETURNmi64:
21356 case X86::WIN_ALLOCA:
21357 return EmitLoweredWinAlloca(MI, BB);
21358 case X86::SEG_ALLOCA_32:
21359 case X86::SEG_ALLOCA_64:
21360 return EmitLoweredSegAlloca(MI, BB);
21361 case X86::TLSCall_32:
21362 case X86::TLSCall_64:
21363 return EmitLoweredTLSCall(MI, BB);
21364 case X86::CMOV_GR8:
21365 case X86::CMOV_FR32:
21366 case X86::CMOV_FR64:
21367 case X86::CMOV_V4F32:
21368 case X86::CMOV_V2F64:
21369 case X86::CMOV_V2I64:
21370 case X86::CMOV_V8F32:
21371 case X86::CMOV_V4F64:
21372 case X86::CMOV_V4I64:
21373 case X86::CMOV_V16F32:
21374 case X86::CMOV_V8F64:
21375 case X86::CMOV_V8I64:
21376 case X86::CMOV_GR16:
21377 case X86::CMOV_GR32:
21378 case X86::CMOV_RFP32:
21379 case X86::CMOV_RFP64:
21380 case X86::CMOV_RFP80:
21381 return EmitLoweredSelect(MI, BB);
21383 case X86::FP32_TO_INT16_IN_MEM:
21384 case X86::FP32_TO_INT32_IN_MEM:
21385 case X86::FP32_TO_INT64_IN_MEM:
21386 case X86::FP64_TO_INT16_IN_MEM:
21387 case X86::FP64_TO_INT32_IN_MEM:
21388 case X86::FP64_TO_INT64_IN_MEM:
21389 case X86::FP80_TO_INT16_IN_MEM:
21390 case X86::FP80_TO_INT32_IN_MEM:
21391 case X86::FP80_TO_INT64_IN_MEM: {
21392 MachineFunction *F = BB->getParent();
21393 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21394 DebugLoc DL = MI->getDebugLoc();
21396 // Change the floating point control register to use "round towards zero"
21397 // mode when truncating to an integer value.
21398 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21399 addFrameReference(BuildMI(*BB, MI, DL,
21400 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21402 // Load the old value of the high byte of the control word...
21404 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21405 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21408 // Set the high part to be round to zero...
21409 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21412 // Reload the modified control word now...
21413 addFrameReference(BuildMI(*BB, MI, DL,
21414 TII->get(X86::FLDCW16m)), CWFrameIdx);
21416 // Restore the memory image of control word to original value
21417 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21420 // Get the X86 opcode to use.
21422 switch (MI->getOpcode()) {
21423 default: llvm_unreachable("illegal opcode!");
21424 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21425 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21426 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21427 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21428 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21429 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21430 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21431 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21432 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21436 MachineOperand &Op = MI->getOperand(0);
21438 AM.BaseType = X86AddressMode::RegBase;
21439 AM.Base.Reg = Op.getReg();
21441 AM.BaseType = X86AddressMode::FrameIndexBase;
21442 AM.Base.FrameIndex = Op.getIndex();
21444 Op = MI->getOperand(1);
21446 AM.Scale = Op.getImm();
21447 Op = MI->getOperand(2);
21449 AM.IndexReg = Op.getImm();
21450 Op = MI->getOperand(3);
21451 if (Op.isGlobal()) {
21452 AM.GV = Op.getGlobal();
21454 AM.Disp = Op.getImm();
21456 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21457 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21459 // Reload the original control word now.
21460 addFrameReference(BuildMI(*BB, MI, DL,
21461 TII->get(X86::FLDCW16m)), CWFrameIdx);
21463 MI->eraseFromParent(); // The pseudo instruction is gone now.
21466 // String/text processing lowering.
21467 case X86::PCMPISTRM128REG:
21468 case X86::VPCMPISTRM128REG:
21469 case X86::PCMPISTRM128MEM:
21470 case X86::VPCMPISTRM128MEM:
21471 case X86::PCMPESTRM128REG:
21472 case X86::VPCMPESTRM128REG:
21473 case X86::PCMPESTRM128MEM:
21474 case X86::VPCMPESTRM128MEM:
21475 assert(Subtarget->hasSSE42() &&
21476 "Target must have SSE4.2 or AVX features enabled");
21477 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21479 // String/text processing lowering.
21480 case X86::PCMPISTRIREG:
21481 case X86::VPCMPISTRIREG:
21482 case X86::PCMPISTRIMEM:
21483 case X86::VPCMPISTRIMEM:
21484 case X86::PCMPESTRIREG:
21485 case X86::VPCMPESTRIREG:
21486 case X86::PCMPESTRIMEM:
21487 case X86::VPCMPESTRIMEM:
21488 assert(Subtarget->hasSSE42() &&
21489 "Target must have SSE4.2 or AVX features enabled");
21490 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21492 // Thread synchronization.
21494 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21499 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21501 case X86::VASTART_SAVE_XMM_REGS:
21502 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21504 case X86::VAARG_64:
21505 return EmitVAARG64WithCustomInserter(MI, BB);
21507 case X86::EH_SjLj_SetJmp32:
21508 case X86::EH_SjLj_SetJmp64:
21509 return emitEHSjLjSetJmp(MI, BB);
21511 case X86::EH_SjLj_LongJmp32:
21512 case X86::EH_SjLj_LongJmp64:
21513 return emitEHSjLjLongJmp(MI, BB);
21515 case TargetOpcode::STATEPOINT:
21516 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21517 // this point in the process. We diverge later.
21518 return emitPatchPoint(MI, BB);
21520 case TargetOpcode::STACKMAP:
21521 case TargetOpcode::PATCHPOINT:
21522 return emitPatchPoint(MI, BB);
21524 case X86::VFMADDPDr213r:
21525 case X86::VFMADDPSr213r:
21526 case X86::VFMADDSDr213r:
21527 case X86::VFMADDSSr213r:
21528 case X86::VFMSUBPDr213r:
21529 case X86::VFMSUBPSr213r:
21530 case X86::VFMSUBSDr213r:
21531 case X86::VFMSUBSSr213r:
21532 case X86::VFNMADDPDr213r:
21533 case X86::VFNMADDPSr213r:
21534 case X86::VFNMADDSDr213r:
21535 case X86::VFNMADDSSr213r:
21536 case X86::VFNMSUBPDr213r:
21537 case X86::VFNMSUBPSr213r:
21538 case X86::VFNMSUBSDr213r:
21539 case X86::VFNMSUBSSr213r:
21540 case X86::VFMADDSUBPDr213r:
21541 case X86::VFMADDSUBPSr213r:
21542 case X86::VFMSUBADDPDr213r:
21543 case X86::VFMSUBADDPSr213r:
21544 case X86::VFMADDPDr213rY:
21545 case X86::VFMADDPSr213rY:
21546 case X86::VFMSUBPDr213rY:
21547 case X86::VFMSUBPSr213rY:
21548 case X86::VFNMADDPDr213rY:
21549 case X86::VFNMADDPSr213rY:
21550 case X86::VFNMSUBPDr213rY:
21551 case X86::VFNMSUBPSr213rY:
21552 case X86::VFMADDSUBPDr213rY:
21553 case X86::VFMADDSUBPSr213rY:
21554 case X86::VFMSUBADDPDr213rY:
21555 case X86::VFMSUBADDPSr213rY:
21556 return emitFMA3Instr(MI, BB);
21560 //===----------------------------------------------------------------------===//
21561 // X86 Optimization Hooks
21562 //===----------------------------------------------------------------------===//
21564 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21567 const SelectionDAG &DAG,
21568 unsigned Depth) const {
21569 unsigned BitWidth = KnownZero.getBitWidth();
21570 unsigned Opc = Op.getOpcode();
21571 assert((Opc >= ISD::BUILTIN_OP_END ||
21572 Opc == ISD::INTRINSIC_WO_CHAIN ||
21573 Opc == ISD::INTRINSIC_W_CHAIN ||
21574 Opc == ISD::INTRINSIC_VOID) &&
21575 "Should use MaskedValueIsZero if you don't know whether Op"
21576 " is a target node!");
21578 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21592 // These nodes' second result is a boolean.
21593 if (Op.getResNo() == 0)
21596 case X86ISD::SETCC:
21597 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21599 case ISD::INTRINSIC_WO_CHAIN: {
21600 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21601 unsigned NumLoBits = 0;
21604 case Intrinsic::x86_sse_movmsk_ps:
21605 case Intrinsic::x86_avx_movmsk_ps_256:
21606 case Intrinsic::x86_sse2_movmsk_pd:
21607 case Intrinsic::x86_avx_movmsk_pd_256:
21608 case Intrinsic::x86_mmx_pmovmskb:
21609 case Intrinsic::x86_sse2_pmovmskb_128:
21610 case Intrinsic::x86_avx2_pmovmskb: {
21611 // High bits of movmskp{s|d}, pmovmskb are known zero.
21613 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21614 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21615 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21616 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21617 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21618 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21619 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21620 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21622 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21631 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21633 const SelectionDAG &,
21634 unsigned Depth) const {
21635 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21636 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21637 return Op.getValueType().getScalarType().getSizeInBits();
21643 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21644 /// node is a GlobalAddress + offset.
21645 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21646 const GlobalValue* &GA,
21647 int64_t &Offset) const {
21648 if (N->getOpcode() == X86ISD::Wrapper) {
21649 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21650 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21651 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21655 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21658 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21659 /// same as extracting the high 128-bit part of 256-bit vector and then
21660 /// inserting the result into the low part of a new 256-bit vector
21661 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21662 EVT VT = SVOp->getValueType(0);
21663 unsigned NumElems = VT.getVectorNumElements();
21665 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21666 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21667 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21668 SVOp->getMaskElt(j) >= 0)
21674 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21675 /// same as extracting the low 128-bit part of 256-bit vector and then
21676 /// inserting the result into the high part of a new 256-bit vector
21677 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21678 EVT VT = SVOp->getValueType(0);
21679 unsigned NumElems = VT.getVectorNumElements();
21681 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21682 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21683 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21684 SVOp->getMaskElt(j) >= 0)
21690 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21691 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21692 TargetLowering::DAGCombinerInfo &DCI,
21693 const X86Subtarget* Subtarget) {
21695 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21696 SDValue V1 = SVOp->getOperand(0);
21697 SDValue V2 = SVOp->getOperand(1);
21698 EVT VT = SVOp->getValueType(0);
21699 unsigned NumElems = VT.getVectorNumElements();
21701 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21702 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21706 // V UNDEF BUILD_VECTOR UNDEF
21708 // CONCAT_VECTOR CONCAT_VECTOR
21711 // RESULT: V + zero extended
21713 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21714 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21715 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21718 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21721 // To match the shuffle mask, the first half of the mask should
21722 // be exactly the first vector, and all the rest a splat with the
21723 // first element of the second one.
21724 for (unsigned i = 0; i != NumElems/2; ++i)
21725 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21726 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21729 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21730 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21731 if (Ld->hasNUsesOfValue(1, 0)) {
21732 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21733 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21735 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21737 Ld->getPointerInfo(),
21738 Ld->getAlignment(),
21739 false/*isVolatile*/, true/*ReadMem*/,
21740 false/*WriteMem*/);
21742 // Make sure the newly-created LOAD is in the same position as Ld in
21743 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21744 // and update uses of Ld's output chain to use the TokenFactor.
21745 if (Ld->hasAnyUseOfValue(1)) {
21746 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21747 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21748 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21749 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21750 SDValue(ResNode.getNode(), 1));
21753 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21757 // Emit a zeroed vector and insert the desired subvector on its
21759 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21760 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21761 return DCI.CombineTo(N, InsV);
21764 //===--------------------------------------------------------------------===//
21765 // Combine some shuffles into subvector extracts and inserts:
21768 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21769 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21770 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21771 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21772 return DCI.CombineTo(N, InsV);
21775 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21776 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21777 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21778 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21779 return DCI.CombineTo(N, InsV);
21785 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21788 /// This is the leaf of the recursive combinine below. When we have found some
21789 /// chain of single-use x86 shuffle instructions and accumulated the combined
21790 /// shuffle mask represented by them, this will try to pattern match that mask
21791 /// into either a single instruction if there is a special purpose instruction
21792 /// for this operation, or into a PSHUFB instruction which is a fully general
21793 /// instruction but should only be used to replace chains over a certain depth.
21794 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21795 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21796 TargetLowering::DAGCombinerInfo &DCI,
21797 const X86Subtarget *Subtarget) {
21798 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21800 // Find the operand that enters the chain. Note that multiple uses are OK
21801 // here, we're not going to remove the operand we find.
21802 SDValue Input = Op.getOperand(0);
21803 while (Input.getOpcode() == ISD::BITCAST)
21804 Input = Input.getOperand(0);
21806 MVT VT = Input.getSimpleValueType();
21807 MVT RootVT = Root.getSimpleValueType();
21810 // Just remove no-op shuffle masks.
21811 if (Mask.size() == 1) {
21812 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21817 // Use the float domain if the operand type is a floating point type.
21818 bool FloatDomain = VT.isFloatingPoint();
21820 // For floating point shuffles, we don't have free copies in the shuffle
21821 // instructions or the ability to load as part of the instruction, so
21822 // canonicalize their shuffles to UNPCK or MOV variants.
21824 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21825 // vectors because it can have a load folded into it that UNPCK cannot. This
21826 // doesn't preclude something switching to the shorter encoding post-RA.
21828 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21829 bool Lo = Mask.equals(0, 0);
21832 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21833 // is no slower than UNPCKLPD but has the option to fold the input operand
21834 // into even an unaligned memory load.
21835 if (Lo && Subtarget->hasSSE3()) {
21836 Shuffle = X86ISD::MOVDDUP;
21837 ShuffleVT = MVT::v2f64;
21839 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21840 // than the UNPCK variants.
21841 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21842 ShuffleVT = MVT::v4f32;
21844 if (Depth == 1 && Root->getOpcode() == Shuffle)
21845 return false; // Nothing to do!
21846 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21847 DCI.AddToWorklist(Op.getNode());
21848 if (Shuffle == X86ISD::MOVDDUP)
21849 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21851 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21852 DCI.AddToWorklist(Op.getNode());
21853 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21857 if (Subtarget->hasSSE3() &&
21858 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21859 bool Lo = Mask.equals(0, 0, 2, 2);
21860 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21861 MVT ShuffleVT = MVT::v4f32;
21862 if (Depth == 1 && Root->getOpcode() == Shuffle)
21863 return false; // Nothing to do!
21864 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21865 DCI.AddToWorklist(Op.getNode());
21866 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21867 DCI.AddToWorklist(Op.getNode());
21868 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21872 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21873 bool Lo = Mask.equals(0, 0, 1, 1);
21874 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21875 MVT ShuffleVT = MVT::v4f32;
21876 if (Depth == 1 && Root->getOpcode() == Shuffle)
21877 return false; // Nothing to do!
21878 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21879 DCI.AddToWorklist(Op.getNode());
21880 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21881 DCI.AddToWorklist(Op.getNode());
21882 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21888 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21889 // variants as none of these have single-instruction variants that are
21890 // superior to the UNPCK formulation.
21891 if (!FloatDomain &&
21892 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21893 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21894 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21895 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21897 bool Lo = Mask[0] == 0;
21898 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21899 if (Depth == 1 && Root->getOpcode() == Shuffle)
21900 return false; // Nothing to do!
21902 switch (Mask.size()) {
21904 ShuffleVT = MVT::v8i16;
21907 ShuffleVT = MVT::v16i8;
21910 llvm_unreachable("Impossible mask size!");
21912 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21913 DCI.AddToWorklist(Op.getNode());
21914 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21915 DCI.AddToWorklist(Op.getNode());
21916 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21921 // Don't try to re-form single instruction chains under any circumstances now
21922 // that we've done encoding canonicalization for them.
21926 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21927 // can replace them with a single PSHUFB instruction profitably. Intel's
21928 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21929 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21930 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21931 SmallVector<SDValue, 16> PSHUFBMask;
21932 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21933 int Ratio = 16 / Mask.size();
21934 for (unsigned i = 0; i < 16; ++i) {
21935 if (Mask[i / Ratio] == SM_SentinelUndef) {
21936 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21939 int M = Mask[i / Ratio] != SM_SentinelZero
21940 ? Ratio * Mask[i / Ratio] + i % Ratio
21942 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21944 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21945 DCI.AddToWorklist(Op.getNode());
21946 SDValue PSHUFBMaskOp =
21947 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21948 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21949 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21950 DCI.AddToWorklist(Op.getNode());
21951 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21956 // Failed to find any combines.
21960 /// \brief Fully generic combining of x86 shuffle instructions.
21962 /// This should be the last combine run over the x86 shuffle instructions. Once
21963 /// they have been fully optimized, this will recursively consider all chains
21964 /// of single-use shuffle instructions, build a generic model of the cumulative
21965 /// shuffle operation, and check for simpler instructions which implement this
21966 /// operation. We use this primarily for two purposes:
21968 /// 1) Collapse generic shuffles to specialized single instructions when
21969 /// equivalent. In most cases, this is just an encoding size win, but
21970 /// sometimes we will collapse multiple generic shuffles into a single
21971 /// special-purpose shuffle.
21972 /// 2) Look for sequences of shuffle instructions with 3 or more total
21973 /// instructions, and replace them with the slightly more expensive SSSE3
21974 /// PSHUFB instruction if available. We do this as the last combining step
21975 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21976 /// a suitable short sequence of other instructions. The PHUFB will either
21977 /// use a register or have to read from memory and so is slightly (but only
21978 /// slightly) more expensive than the other shuffle instructions.
21980 /// Because this is inherently a quadratic operation (for each shuffle in
21981 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21982 /// This should never be an issue in practice as the shuffle lowering doesn't
21983 /// produce sequences of more than 8 instructions.
21985 /// FIXME: We will currently miss some cases where the redundant shuffling
21986 /// would simplify under the threshold for PSHUFB formation because of
21987 /// combine-ordering. To fix this, we should do the redundant instruction
21988 /// combining in this recursive walk.
21989 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21990 ArrayRef<int> RootMask,
21991 int Depth, bool HasPSHUFB,
21993 TargetLowering::DAGCombinerInfo &DCI,
21994 const X86Subtarget *Subtarget) {
21995 // Bound the depth of our recursive combine because this is ultimately
21996 // quadratic in nature.
22000 // Directly rip through bitcasts to find the underlying operand.
22001 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22002 Op = Op.getOperand(0);
22004 MVT VT = Op.getSimpleValueType();
22005 if (!VT.isVector())
22006 return false; // Bail if we hit a non-vector.
22007 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22008 // version should be added.
22009 if (VT.getSizeInBits() != 128)
22012 assert(Root.getSimpleValueType().isVector() &&
22013 "Shuffles operate on vector types!");
22014 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22015 "Can only combine shuffles of the same vector register size.");
22017 if (!isTargetShuffle(Op.getOpcode()))
22019 SmallVector<int, 16> OpMask;
22021 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22022 // We only can combine unary shuffles which we can decode the mask for.
22023 if (!HaveMask || !IsUnary)
22026 assert(VT.getVectorNumElements() == OpMask.size() &&
22027 "Different mask size from vector size!");
22028 assert(((RootMask.size() > OpMask.size() &&
22029 RootMask.size() % OpMask.size() == 0) ||
22030 (OpMask.size() > RootMask.size() &&
22031 OpMask.size() % RootMask.size() == 0) ||
22032 OpMask.size() == RootMask.size()) &&
22033 "The smaller number of elements must divide the larger.");
22034 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22035 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22036 assert(((RootRatio == 1 && OpRatio == 1) ||
22037 (RootRatio == 1) != (OpRatio == 1)) &&
22038 "Must not have a ratio for both incoming and op masks!");
22040 SmallVector<int, 16> Mask;
22041 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22043 // Merge this shuffle operation's mask into our accumulated mask. Note that
22044 // this shuffle's mask will be the first applied to the input, followed by the
22045 // root mask to get us all the way to the root value arrangement. The reason
22046 // for this order is that we are recursing up the operation chain.
22047 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22048 int RootIdx = i / RootRatio;
22049 if (RootMask[RootIdx] < 0) {
22050 // This is a zero or undef lane, we're done.
22051 Mask.push_back(RootMask[RootIdx]);
22055 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22056 int OpIdx = RootMaskedIdx / OpRatio;
22057 if (OpMask[OpIdx] < 0) {
22058 // The incoming lanes are zero or undef, it doesn't matter which ones we
22060 Mask.push_back(OpMask[OpIdx]);
22064 // Ok, we have non-zero lanes, map them through.
22065 Mask.push_back(OpMask[OpIdx] * OpRatio +
22066 RootMaskedIdx % OpRatio);
22069 // See if we can recurse into the operand to combine more things.
22070 switch (Op.getOpcode()) {
22071 case X86ISD::PSHUFB:
22073 case X86ISD::PSHUFD:
22074 case X86ISD::PSHUFHW:
22075 case X86ISD::PSHUFLW:
22076 if (Op.getOperand(0).hasOneUse() &&
22077 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22078 HasPSHUFB, DAG, DCI, Subtarget))
22082 case X86ISD::UNPCKL:
22083 case X86ISD::UNPCKH:
22084 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22085 // We can't check for single use, we have to check that this shuffle is the only user.
22086 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22087 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22088 HasPSHUFB, DAG, DCI, Subtarget))
22093 // Minor canonicalization of the accumulated shuffle mask to make it easier
22094 // to match below. All this does is detect masks with squential pairs of
22095 // elements, and shrink them to the half-width mask. It does this in a loop
22096 // so it will reduce the size of the mask to the minimal width mask which
22097 // performs an equivalent shuffle.
22098 SmallVector<int, 16> WidenedMask;
22099 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22100 Mask = std::move(WidenedMask);
22101 WidenedMask.clear();
22104 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22108 /// \brief Get the PSHUF-style mask from PSHUF node.
22110 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22111 /// PSHUF-style masks that can be reused with such instructions.
22112 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22113 SmallVector<int, 4> Mask;
22115 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22119 switch (N.getOpcode()) {
22120 case X86ISD::PSHUFD:
22122 case X86ISD::PSHUFLW:
22125 case X86ISD::PSHUFHW:
22126 Mask.erase(Mask.begin(), Mask.begin() + 4);
22127 for (int &M : Mask)
22131 llvm_unreachable("No valid shuffle instruction found!");
22135 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22137 /// We walk up the chain and look for a combinable shuffle, skipping over
22138 /// shuffles that we could hoist this shuffle's transformation past without
22139 /// altering anything.
22141 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22143 TargetLowering::DAGCombinerInfo &DCI) {
22144 assert(N.getOpcode() == X86ISD::PSHUFD &&
22145 "Called with something other than an x86 128-bit half shuffle!");
22148 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22149 // of the shuffles in the chain so that we can form a fresh chain to replace
22151 SmallVector<SDValue, 8> Chain;
22152 SDValue V = N.getOperand(0);
22153 for (; V.hasOneUse(); V = V.getOperand(0)) {
22154 switch (V.getOpcode()) {
22156 return SDValue(); // Nothing combined!
22159 // Skip bitcasts as we always know the type for the target specific
22163 case X86ISD::PSHUFD:
22164 // Found another dword shuffle.
22167 case X86ISD::PSHUFLW:
22168 // Check that the low words (being shuffled) are the identity in the
22169 // dword shuffle, and the high words are self-contained.
22170 if (Mask[0] != 0 || Mask[1] != 1 ||
22171 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22174 Chain.push_back(V);
22177 case X86ISD::PSHUFHW:
22178 // Check that the high words (being shuffled) are the identity in the
22179 // dword shuffle, and the low words are self-contained.
22180 if (Mask[2] != 2 || Mask[3] != 3 ||
22181 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22184 Chain.push_back(V);
22187 case X86ISD::UNPCKL:
22188 case X86ISD::UNPCKH:
22189 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22190 // shuffle into a preceding word shuffle.
22191 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22194 // Search for a half-shuffle which we can combine with.
22195 unsigned CombineOp =
22196 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22197 if (V.getOperand(0) != V.getOperand(1) ||
22198 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22200 Chain.push_back(V);
22201 V = V.getOperand(0);
22203 switch (V.getOpcode()) {
22205 return SDValue(); // Nothing to combine.
22207 case X86ISD::PSHUFLW:
22208 case X86ISD::PSHUFHW:
22209 if (V.getOpcode() == CombineOp)
22212 Chain.push_back(V);
22216 V = V.getOperand(0);
22220 } while (V.hasOneUse());
22223 // Break out of the loop if we break out of the switch.
22227 if (!V.hasOneUse())
22228 // We fell out of the loop without finding a viable combining instruction.
22231 // Merge this node's mask and our incoming mask.
22232 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22233 for (int &M : Mask)
22235 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22236 getV4X86ShuffleImm8ForMask(Mask, DAG));
22238 // Rebuild the chain around this new shuffle.
22239 while (!Chain.empty()) {
22240 SDValue W = Chain.pop_back_val();
22242 if (V.getValueType() != W.getOperand(0).getValueType())
22243 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22245 switch (W.getOpcode()) {
22247 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22249 case X86ISD::UNPCKL:
22250 case X86ISD::UNPCKH:
22251 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22254 case X86ISD::PSHUFD:
22255 case X86ISD::PSHUFLW:
22256 case X86ISD::PSHUFHW:
22257 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22261 if (V.getValueType() != N.getValueType())
22262 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22264 // Return the new chain to replace N.
22268 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22270 /// We walk up the chain, skipping shuffles of the other half and looking
22271 /// through shuffles which switch halves trying to find a shuffle of the same
22272 /// pair of dwords.
22273 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22275 TargetLowering::DAGCombinerInfo &DCI) {
22277 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22278 "Called with something other than an x86 128-bit half shuffle!");
22280 unsigned CombineOpcode = N.getOpcode();
22282 // Walk up a single-use chain looking for a combinable shuffle.
22283 SDValue V = N.getOperand(0);
22284 for (; V.hasOneUse(); V = V.getOperand(0)) {
22285 switch (V.getOpcode()) {
22287 return false; // Nothing combined!
22290 // Skip bitcasts as we always know the type for the target specific
22294 case X86ISD::PSHUFLW:
22295 case X86ISD::PSHUFHW:
22296 if (V.getOpcode() == CombineOpcode)
22299 // Other-half shuffles are no-ops.
22302 // Break out of the loop if we break out of the switch.
22306 if (!V.hasOneUse())
22307 // We fell out of the loop without finding a viable combining instruction.
22310 // Combine away the bottom node as its shuffle will be accumulated into
22311 // a preceding shuffle.
22312 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22314 // Record the old value.
22317 // Merge this node's mask and our incoming mask (adjusted to account for all
22318 // the pshufd instructions encountered).
22319 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22320 for (int &M : Mask)
22322 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22323 getV4X86ShuffleImm8ForMask(Mask, DAG));
22325 // Check that the shuffles didn't cancel each other out. If not, we need to
22326 // combine to the new one.
22328 // Replace the combinable shuffle with the combined one, updating all users
22329 // so that we re-evaluate the chain here.
22330 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22335 /// \brief Try to combine x86 target specific shuffles.
22336 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22337 TargetLowering::DAGCombinerInfo &DCI,
22338 const X86Subtarget *Subtarget) {
22340 MVT VT = N.getSimpleValueType();
22341 SmallVector<int, 4> Mask;
22343 switch (N.getOpcode()) {
22344 case X86ISD::PSHUFD:
22345 case X86ISD::PSHUFLW:
22346 case X86ISD::PSHUFHW:
22347 Mask = getPSHUFShuffleMask(N);
22348 assert(Mask.size() == 4);
22354 // Nuke no-op shuffles that show up after combining.
22355 if (isNoopShuffleMask(Mask))
22356 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22358 // Look for simplifications involving one or two shuffle instructions.
22359 SDValue V = N.getOperand(0);
22360 switch (N.getOpcode()) {
22363 case X86ISD::PSHUFLW:
22364 case X86ISD::PSHUFHW:
22365 assert(VT == MVT::v8i16);
22368 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22369 return SDValue(); // We combined away this shuffle, so we're done.
22371 // See if this reduces to a PSHUFD which is no more expensive and can
22372 // combine with more operations. Note that it has to at least flip the
22373 // dwords as otherwise it would have been removed as a no-op.
22374 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22375 int DMask[] = {0, 1, 2, 3};
22376 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22377 DMask[DOffset + 0] = DOffset + 1;
22378 DMask[DOffset + 1] = DOffset + 0;
22379 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22380 DCI.AddToWorklist(V.getNode());
22381 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22382 getV4X86ShuffleImm8ForMask(DMask, DAG));
22383 DCI.AddToWorklist(V.getNode());
22384 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22387 // Look for shuffle patterns which can be implemented as a single unpack.
22388 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22389 // only works when we have a PSHUFD followed by two half-shuffles.
22390 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22391 (V.getOpcode() == X86ISD::PSHUFLW ||
22392 V.getOpcode() == X86ISD::PSHUFHW) &&
22393 V.getOpcode() != N.getOpcode() &&
22395 SDValue D = V.getOperand(0);
22396 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22397 D = D.getOperand(0);
22398 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22399 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22400 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22401 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22402 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22404 for (int i = 0; i < 4; ++i) {
22405 WordMask[i + NOffset] = Mask[i] + NOffset;
22406 WordMask[i + VOffset] = VMask[i] + VOffset;
22408 // Map the word mask through the DWord mask.
22410 for (int i = 0; i < 8; ++i)
22411 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22412 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22413 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22414 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22415 std::begin(UnpackLoMask)) ||
22416 std::equal(std::begin(MappedMask), std::end(MappedMask),
22417 std::begin(UnpackHiMask))) {
22418 // We can replace all three shuffles with an unpack.
22419 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22420 DCI.AddToWorklist(V.getNode());
22421 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22423 DL, MVT::v8i16, V, V);
22430 case X86ISD::PSHUFD:
22431 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22440 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22442 /// We combine this directly on the abstract vector shuffle nodes so it is
22443 /// easier to generically match. We also insert dummy vector shuffle nodes for
22444 /// the operands which explicitly discard the lanes which are unused by this
22445 /// operation to try to flow through the rest of the combiner the fact that
22446 /// they're unused.
22447 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22449 EVT VT = N->getValueType(0);
22451 // We only handle target-independent shuffles.
22452 // FIXME: It would be easy and harmless to use the target shuffle mask
22453 // extraction tool to support more.
22454 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22457 auto *SVN = cast<ShuffleVectorSDNode>(N);
22458 ArrayRef<int> Mask = SVN->getMask();
22459 SDValue V1 = N->getOperand(0);
22460 SDValue V2 = N->getOperand(1);
22462 // We require the first shuffle operand to be the SUB node, and the second to
22463 // be the ADD node.
22464 // FIXME: We should support the commuted patterns.
22465 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22468 // If there are other uses of these operations we can't fold them.
22469 if (!V1->hasOneUse() || !V2->hasOneUse())
22472 // Ensure that both operations have the same operands. Note that we can
22473 // commute the FADD operands.
22474 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22475 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22476 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22479 // We're looking for blends between FADD and FSUB nodes. We insist on these
22480 // nodes being lined up in a specific expected pattern.
22481 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22482 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22483 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22486 // Only specific types are legal at this point, assert so we notice if and
22487 // when these change.
22488 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22489 VT == MVT::v4f64) &&
22490 "Unknown vector type encountered!");
22492 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22495 /// PerformShuffleCombine - Performs several different shuffle combines.
22496 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22497 TargetLowering::DAGCombinerInfo &DCI,
22498 const X86Subtarget *Subtarget) {
22500 SDValue N0 = N->getOperand(0);
22501 SDValue N1 = N->getOperand(1);
22502 EVT VT = N->getValueType(0);
22504 // Don't create instructions with illegal types after legalize types has run.
22505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22506 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22509 // If we have legalized the vector types, look for blends of FADD and FSUB
22510 // nodes that we can fuse into an ADDSUB node.
22511 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22512 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22515 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22516 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22517 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22518 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22520 // During Type Legalization, when promoting illegal vector types,
22521 // the backend might introduce new shuffle dag nodes and bitcasts.
22523 // This code performs the following transformation:
22524 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22525 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22527 // We do this only if both the bitcast and the BINOP dag nodes have
22528 // one use. Also, perform this transformation only if the new binary
22529 // operation is legal. This is to avoid introducing dag nodes that
22530 // potentially need to be further expanded (or custom lowered) into a
22531 // less optimal sequence of dag nodes.
22532 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22533 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22534 N0.getOpcode() == ISD::BITCAST) {
22535 SDValue BC0 = N0.getOperand(0);
22536 EVT SVT = BC0.getValueType();
22537 unsigned Opcode = BC0.getOpcode();
22538 unsigned NumElts = VT.getVectorNumElements();
22540 if (BC0.hasOneUse() && SVT.isVector() &&
22541 SVT.getVectorNumElements() * 2 == NumElts &&
22542 TLI.isOperationLegal(Opcode, VT)) {
22543 bool CanFold = false;
22555 unsigned SVTNumElts = SVT.getVectorNumElements();
22556 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22557 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22558 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22559 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22560 CanFold = SVOp->getMaskElt(i) < 0;
22563 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22564 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22565 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22566 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22571 // Only handle 128 wide vector from here on.
22572 if (!VT.is128BitVector())
22575 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22576 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22577 // consecutive, non-overlapping, and in the right order.
22578 SmallVector<SDValue, 16> Elts;
22579 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22580 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22582 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22586 if (isTargetShuffle(N->getOpcode())) {
22588 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22589 if (Shuffle.getNode())
22592 // Try recursively combining arbitrary sequences of x86 shuffle
22593 // instructions into higher-order shuffles. We do this after combining
22594 // specific PSHUF instruction sequences into their minimal form so that we
22595 // can evaluate how many specialized shuffle instructions are involved in
22596 // a particular chain.
22597 SmallVector<int, 1> NonceMask; // Just a placeholder.
22598 NonceMask.push_back(0);
22599 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22600 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22602 return SDValue(); // This routine will use CombineTo to replace N.
22608 /// PerformTruncateCombine - Converts truncate operation to
22609 /// a sequence of vector shuffle operations.
22610 /// It is possible when we truncate 256-bit vector to 128-bit vector
22611 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22612 TargetLowering::DAGCombinerInfo &DCI,
22613 const X86Subtarget *Subtarget) {
22617 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22618 /// specific shuffle of a load can be folded into a single element load.
22619 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22620 /// shuffles have been custom lowered so we need to handle those here.
22621 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22622 TargetLowering::DAGCombinerInfo &DCI) {
22623 if (DCI.isBeforeLegalizeOps())
22626 SDValue InVec = N->getOperand(0);
22627 SDValue EltNo = N->getOperand(1);
22629 if (!isa<ConstantSDNode>(EltNo))
22632 EVT OriginalVT = InVec.getValueType();
22634 if (InVec.getOpcode() == ISD::BITCAST) {
22635 // Don't duplicate a load with other uses.
22636 if (!InVec.hasOneUse())
22638 EVT BCVT = InVec.getOperand(0).getValueType();
22639 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22641 InVec = InVec.getOperand(0);
22644 EVT CurrentVT = InVec.getValueType();
22646 if (!isTargetShuffle(InVec.getOpcode()))
22649 // Don't duplicate a load with other uses.
22650 if (!InVec.hasOneUse())
22653 SmallVector<int, 16> ShuffleMask;
22655 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22656 ShuffleMask, UnaryShuffle))
22659 // Select the input vector, guarding against out of range extract vector.
22660 unsigned NumElems = CurrentVT.getVectorNumElements();
22661 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22662 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22663 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22664 : InVec.getOperand(1);
22666 // If inputs to shuffle are the same for both ops, then allow 2 uses
22667 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22669 if (LdNode.getOpcode() == ISD::BITCAST) {
22670 // Don't duplicate a load with other uses.
22671 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22674 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22675 LdNode = LdNode.getOperand(0);
22678 if (!ISD::isNormalLoad(LdNode.getNode()))
22681 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22683 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22686 EVT EltVT = N->getValueType(0);
22687 // If there's a bitcast before the shuffle, check if the load type and
22688 // alignment is valid.
22689 unsigned Align = LN0->getAlignment();
22690 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22691 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22692 EltVT.getTypeForEVT(*DAG.getContext()));
22694 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22697 // All checks match so transform back to vector_shuffle so that DAG combiner
22698 // can finish the job
22701 // Create shuffle node taking into account the case that its a unary shuffle
22702 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22703 : InVec.getOperand(1);
22704 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22705 InVec.getOperand(0), Shuffle,
22707 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22708 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22712 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22713 /// generation and convert it from being a bunch of shuffles and extracts
22714 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22715 /// storing the value and loading scalars back, while for x64 we should
22716 /// use 64-bit extracts and shifts.
22717 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22718 TargetLowering::DAGCombinerInfo &DCI) {
22719 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22720 if (NewOp.getNode())
22723 SDValue InputVector = N->getOperand(0);
22725 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22726 // from mmx to v2i32 has a single usage.
22727 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22728 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22729 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22730 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22731 N->getValueType(0),
22732 InputVector.getNode()->getOperand(0));
22734 // Only operate on vectors of 4 elements, where the alternative shuffling
22735 // gets to be more expensive.
22736 if (InputVector.getValueType() != MVT::v4i32)
22739 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22740 // single use which is a sign-extend or zero-extend, and all elements are
22742 SmallVector<SDNode *, 4> Uses;
22743 unsigned ExtractedElements = 0;
22744 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22745 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22746 if (UI.getUse().getResNo() != InputVector.getResNo())
22749 SDNode *Extract = *UI;
22750 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22753 if (Extract->getValueType(0) != MVT::i32)
22755 if (!Extract->hasOneUse())
22757 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22758 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22760 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22763 // Record which element was extracted.
22764 ExtractedElements |=
22765 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22767 Uses.push_back(Extract);
22770 // If not all the elements were used, this may not be worthwhile.
22771 if (ExtractedElements != 15)
22774 // Ok, we've now decided to do the transformation.
22775 // If 64-bit shifts are legal, use the extract-shift sequence,
22776 // otherwise bounce the vector off the cache.
22777 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22779 SDLoc dl(InputVector);
22781 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22782 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22783 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22784 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22785 DAG.getConstant(0, VecIdxTy));
22786 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22787 DAG.getConstant(1, VecIdxTy));
22789 SDValue ShAmt = DAG.getConstant(32,
22790 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22791 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22792 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22793 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22794 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22795 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22796 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22798 // Store the value to a temporary stack slot.
22799 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22800 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22801 MachinePointerInfo(), false, false, 0);
22803 EVT ElementType = InputVector.getValueType().getVectorElementType();
22804 unsigned EltSize = ElementType.getSizeInBits() / 8;
22806 // Replace each use (extract) with a load of the appropriate element.
22807 for (unsigned i = 0; i < 4; ++i) {
22808 uint64_t Offset = EltSize * i;
22809 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22811 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22812 StackPtr, OffsetVal);
22814 // Load the scalar.
22815 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22816 ScalarAddr, MachinePointerInfo(),
22817 false, false, false, 0);
22822 // Replace the extracts
22823 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22824 UE = Uses.end(); UI != UE; ++UI) {
22825 SDNode *Extract = *UI;
22827 SDValue Idx = Extract->getOperand(1);
22828 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22829 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22832 // The replacement was made in place; don't return anything.
22836 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22837 static std::pair<unsigned, bool>
22838 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22839 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22840 if (!VT.isVector())
22841 return std::make_pair(0, false);
22843 bool NeedSplit = false;
22844 switch (VT.getSimpleVT().SimpleTy) {
22845 default: return std::make_pair(0, false);
22848 if (!Subtarget->hasVLX())
22849 return std::make_pair(0, false);
22853 if (!Subtarget->hasBWI())
22854 return std::make_pair(0, false);
22858 if (!Subtarget->hasAVX512())
22859 return std::make_pair(0, false);
22864 if (!Subtarget->hasAVX2())
22866 if (!Subtarget->hasAVX())
22867 return std::make_pair(0, false);
22872 if (!Subtarget->hasSSE2())
22873 return std::make_pair(0, false);
22876 // SSE2 has only a small subset of the operations.
22877 bool hasUnsigned = Subtarget->hasSSE41() ||
22878 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22879 bool hasSigned = Subtarget->hasSSE41() ||
22880 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22882 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22885 // Check for x CC y ? x : y.
22886 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22887 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22892 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22895 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22898 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22901 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22903 // Check for x CC y ? y : x -- a min/max with reversed arms.
22904 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22905 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22910 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22913 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22916 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22919 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22923 return std::make_pair(Opc, NeedSplit);
22927 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22928 const X86Subtarget *Subtarget) {
22930 SDValue Cond = N->getOperand(0);
22931 SDValue LHS = N->getOperand(1);
22932 SDValue RHS = N->getOperand(2);
22934 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22935 SDValue CondSrc = Cond->getOperand(0);
22936 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22937 Cond = CondSrc->getOperand(0);
22940 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22943 // A vselect where all conditions and data are constants can be optimized into
22944 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22945 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22946 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22949 unsigned MaskValue = 0;
22950 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22953 MVT VT = N->getSimpleValueType(0);
22954 unsigned NumElems = VT.getVectorNumElements();
22955 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22956 for (unsigned i = 0; i < NumElems; ++i) {
22957 // Be sure we emit undef where we can.
22958 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22959 ShuffleMask[i] = -1;
22961 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22964 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22965 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22967 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22970 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22972 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22973 TargetLowering::DAGCombinerInfo &DCI,
22974 const X86Subtarget *Subtarget) {
22976 SDValue Cond = N->getOperand(0);
22977 // Get the LHS/RHS of the select.
22978 SDValue LHS = N->getOperand(1);
22979 SDValue RHS = N->getOperand(2);
22980 EVT VT = LHS.getValueType();
22981 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22983 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22984 // instructions match the semantics of the common C idiom x<y?x:y but not
22985 // x<=y?x:y, because of how they handle negative zero (which can be
22986 // ignored in unsafe-math mode).
22987 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22988 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22989 (Subtarget->hasSSE2() ||
22990 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22991 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22993 unsigned Opcode = 0;
22994 // Check for x CC y ? x : y.
22995 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22996 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23000 // Converting this to a min would handle NaNs incorrectly, and swapping
23001 // the operands would cause it to handle comparisons between positive
23002 // and negative zero incorrectly.
23003 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23004 if (!DAG.getTarget().Options.UnsafeFPMath &&
23005 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23007 std::swap(LHS, RHS);
23009 Opcode = X86ISD::FMIN;
23012 // Converting this to a min would handle comparisons between positive
23013 // and negative zero incorrectly.
23014 if (!DAG.getTarget().Options.UnsafeFPMath &&
23015 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23017 Opcode = X86ISD::FMIN;
23020 // Converting this to a min would handle both negative zeros and NaNs
23021 // incorrectly, but we can swap the operands to fix both.
23022 std::swap(LHS, RHS);
23026 Opcode = X86ISD::FMIN;
23030 // Converting this to a max would handle comparisons between positive
23031 // and negative zero incorrectly.
23032 if (!DAG.getTarget().Options.UnsafeFPMath &&
23033 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23035 Opcode = X86ISD::FMAX;
23038 // Converting this to a max would handle NaNs incorrectly, and swapping
23039 // the operands would cause it to handle comparisons between positive
23040 // and negative zero incorrectly.
23041 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23042 if (!DAG.getTarget().Options.UnsafeFPMath &&
23043 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23045 std::swap(LHS, RHS);
23047 Opcode = X86ISD::FMAX;
23050 // Converting this to a max would handle both negative zeros and NaNs
23051 // incorrectly, but we can swap the operands to fix both.
23052 std::swap(LHS, RHS);
23056 Opcode = X86ISD::FMAX;
23059 // Check for x CC y ? y : x -- a min/max with reversed arms.
23060 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23061 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23065 // Converting this to a min would handle comparisons between positive
23066 // and negative zero incorrectly, and swapping the operands would
23067 // cause it to handle NaNs incorrectly.
23068 if (!DAG.getTarget().Options.UnsafeFPMath &&
23069 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23070 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23072 std::swap(LHS, RHS);
23074 Opcode = X86ISD::FMIN;
23077 // Converting this to a min would handle NaNs incorrectly.
23078 if (!DAG.getTarget().Options.UnsafeFPMath &&
23079 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23081 Opcode = X86ISD::FMIN;
23084 // Converting this to a min would handle both negative zeros and NaNs
23085 // incorrectly, but we can swap the operands to fix both.
23086 std::swap(LHS, RHS);
23090 Opcode = X86ISD::FMIN;
23094 // Converting this to a max would handle NaNs incorrectly.
23095 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23097 Opcode = X86ISD::FMAX;
23100 // Converting this to a max would handle comparisons between positive
23101 // and negative zero incorrectly, and swapping the operands would
23102 // cause it to handle NaNs incorrectly.
23103 if (!DAG.getTarget().Options.UnsafeFPMath &&
23104 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23105 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23107 std::swap(LHS, RHS);
23109 Opcode = X86ISD::FMAX;
23112 // Converting this to a max would handle both negative zeros and NaNs
23113 // incorrectly, but we can swap the operands to fix both.
23114 std::swap(LHS, RHS);
23118 Opcode = X86ISD::FMAX;
23124 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23127 EVT CondVT = Cond.getValueType();
23128 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23129 CondVT.getVectorElementType() == MVT::i1) {
23130 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23131 // lowering on KNL. In this case we convert it to
23132 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23133 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23134 // Since SKX these selects have a proper lowering.
23135 EVT OpVT = LHS.getValueType();
23136 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23137 (OpVT.getVectorElementType() == MVT::i8 ||
23138 OpVT.getVectorElementType() == MVT::i16) &&
23139 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23140 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23141 DCI.AddToWorklist(Cond.getNode());
23142 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23145 // If this is a select between two integer constants, try to do some
23147 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23148 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23149 // Don't do this for crazy integer types.
23150 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23151 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23152 // so that TrueC (the true value) is larger than FalseC.
23153 bool NeedsCondInvert = false;
23155 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23156 // Efficiently invertible.
23157 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23158 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23159 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23160 NeedsCondInvert = true;
23161 std::swap(TrueC, FalseC);
23164 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23165 if (FalseC->getAPIntValue() == 0 &&
23166 TrueC->getAPIntValue().isPowerOf2()) {
23167 if (NeedsCondInvert) // Invert the condition if needed.
23168 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23169 DAG.getConstant(1, Cond.getValueType()));
23171 // Zero extend the condition if needed.
23172 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23174 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23175 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23176 DAG.getConstant(ShAmt, MVT::i8));
23179 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23180 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23181 if (NeedsCondInvert) // Invert the condition if needed.
23182 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23183 DAG.getConstant(1, Cond.getValueType()));
23185 // Zero extend the condition if needed.
23186 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23187 FalseC->getValueType(0), Cond);
23188 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23189 SDValue(FalseC, 0));
23192 // Optimize cases that will turn into an LEA instruction. This requires
23193 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23194 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23195 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23196 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23198 bool isFastMultiplier = false;
23200 switch ((unsigned char)Diff) {
23202 case 1: // result = add base, cond
23203 case 2: // result = lea base( , cond*2)
23204 case 3: // result = lea base(cond, cond*2)
23205 case 4: // result = lea base( , cond*4)
23206 case 5: // result = lea base(cond, cond*4)
23207 case 8: // result = lea base( , cond*8)
23208 case 9: // result = lea base(cond, cond*8)
23209 isFastMultiplier = true;
23214 if (isFastMultiplier) {
23215 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23216 if (NeedsCondInvert) // Invert the condition if needed.
23217 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23218 DAG.getConstant(1, Cond.getValueType()));
23220 // Zero extend the condition if needed.
23221 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23223 // Scale the condition by the difference.
23225 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23226 DAG.getConstant(Diff, Cond.getValueType()));
23228 // Add the base if non-zero.
23229 if (FalseC->getAPIntValue() != 0)
23230 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23231 SDValue(FalseC, 0));
23238 // Canonicalize max and min:
23239 // (x > y) ? x : y -> (x >= y) ? x : y
23240 // (x < y) ? x : y -> (x <= y) ? x : y
23241 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23242 // the need for an extra compare
23243 // against zero. e.g.
23244 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23246 // testl %edi, %edi
23248 // cmovgl %edi, %eax
23252 // cmovsl %eax, %edi
23253 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23254 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23255 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23256 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23261 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23262 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23263 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23264 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23269 // Early exit check
23270 if (!TLI.isTypeLegal(VT))
23273 // Match VSELECTs into subs with unsigned saturation.
23274 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23275 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23276 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23277 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23278 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23280 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23281 // left side invert the predicate to simplify logic below.
23283 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23285 CC = ISD::getSetCCInverse(CC, true);
23286 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23290 if (Other.getNode() && Other->getNumOperands() == 2 &&
23291 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23292 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23293 SDValue CondRHS = Cond->getOperand(1);
23295 // Look for a general sub with unsigned saturation first.
23296 // x >= y ? x-y : 0 --> subus x, y
23297 // x > y ? x-y : 0 --> subus x, y
23298 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23299 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23300 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23302 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23303 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23304 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23305 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23306 // If the RHS is a constant we have to reverse the const
23307 // canonicalization.
23308 // x > C-1 ? x+-C : 0 --> subus x, C
23309 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23310 CondRHSConst->getAPIntValue() ==
23311 (-OpRHSConst->getAPIntValue() - 1))
23312 return DAG.getNode(
23313 X86ISD::SUBUS, DL, VT, OpLHS,
23314 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23316 // Another special case: If C was a sign bit, the sub has been
23317 // canonicalized into a xor.
23318 // FIXME: Would it be better to use computeKnownBits to determine
23319 // whether it's safe to decanonicalize the xor?
23320 // x s< 0 ? x^C : 0 --> subus x, C
23321 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23322 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23323 OpRHSConst->getAPIntValue().isSignBit())
23324 // Note that we have to rebuild the RHS constant here to ensure we
23325 // don't rely on particular values of undef lanes.
23326 return DAG.getNode(
23327 X86ISD::SUBUS, DL, VT, OpLHS,
23328 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23333 // Try to match a min/max vector operation.
23334 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23335 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23336 unsigned Opc = ret.first;
23337 bool NeedSplit = ret.second;
23339 if (Opc && NeedSplit) {
23340 unsigned NumElems = VT.getVectorNumElements();
23341 // Extract the LHS vectors
23342 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23343 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23345 // Extract the RHS vectors
23346 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23347 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23349 // Create min/max for each subvector
23350 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23351 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23353 // Merge the result
23354 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23356 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23359 // Simplify vector selection if condition value type matches vselect
23361 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23362 assert(Cond.getValueType().isVector() &&
23363 "vector select expects a vector selector!");
23365 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23366 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23368 // Try invert the condition if true value is not all 1s and false value
23370 if (!TValIsAllOnes && !FValIsAllZeros &&
23371 // Check if the selector will be produced by CMPP*/PCMP*
23372 Cond.getOpcode() == ISD::SETCC &&
23373 // Check if SETCC has already been promoted
23374 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23375 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23376 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23378 if (TValIsAllZeros || FValIsAllOnes) {
23379 SDValue CC = Cond.getOperand(2);
23380 ISD::CondCode NewCC =
23381 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23382 Cond.getOperand(0).getValueType().isInteger());
23383 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23384 std::swap(LHS, RHS);
23385 TValIsAllOnes = FValIsAllOnes;
23386 FValIsAllZeros = TValIsAllZeros;
23390 if (TValIsAllOnes || FValIsAllZeros) {
23393 if (TValIsAllOnes && FValIsAllZeros)
23395 else if (TValIsAllOnes)
23396 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23397 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23398 else if (FValIsAllZeros)
23399 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23400 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23402 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23406 // If we know that this node is legal then we know that it is going to be
23407 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23408 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23409 // to simplify previous instructions.
23410 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23411 !DCI.isBeforeLegalize() &&
23412 // We explicitly check against v8i16 and v16i16 because, although
23413 // they're marked as Custom, they might only be legal when Cond is a
23414 // build_vector of constants. This will be taken care in a later
23416 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23417 VT != MVT::v8i16) &&
23418 // Don't optimize vector of constants. Those are handled by
23419 // the generic code and all the bits must be properly set for
23420 // the generic optimizer.
23421 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23422 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23424 // Don't optimize vector selects that map to mask-registers.
23428 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23429 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23431 APInt KnownZero, KnownOne;
23432 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23433 DCI.isBeforeLegalizeOps());
23434 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23435 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23437 // If we changed the computation somewhere in the DAG, this change
23438 // will affect all users of Cond.
23439 // Make sure it is fine and update all the nodes so that we do not
23440 // use the generic VSELECT anymore. Otherwise, we may perform
23441 // wrong optimizations as we messed up with the actual expectation
23442 // for the vector boolean values.
23443 if (Cond != TLO.Old) {
23444 // Check all uses of that condition operand to check whether it will be
23445 // consumed by non-BLEND instructions, which may depend on all bits are
23447 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23449 if (I->getOpcode() != ISD::VSELECT)
23450 // TODO: Add other opcodes eventually lowered into BLEND.
23453 // Update all the users of the condition, before committing the change,
23454 // so that the VSELECT optimizations that expect the correct vector
23455 // boolean value will not be triggered.
23456 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23458 DAG.ReplaceAllUsesOfValueWith(
23460 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23461 Cond, I->getOperand(1), I->getOperand(2)));
23462 DCI.CommitTargetLoweringOpt(TLO);
23465 // At this point, only Cond is changed. Change the condition
23466 // just for N to keep the opportunity to optimize all other
23467 // users their own way.
23468 DAG.ReplaceAllUsesOfValueWith(
23470 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23471 TLO.New, N->getOperand(1), N->getOperand(2)));
23476 // We should generate an X86ISD::BLENDI from a vselect if its argument
23477 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23478 // constants. This specific pattern gets generated when we split a
23479 // selector for a 512 bit vector in a machine without AVX512 (but with
23480 // 256-bit vectors), during legalization:
23482 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23484 // Iff we find this pattern and the build_vectors are built from
23485 // constants, we translate the vselect into a shuffle_vector that we
23486 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23487 if ((N->getOpcode() == ISD::VSELECT ||
23488 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23489 !DCI.isBeforeLegalize()) {
23490 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23491 if (Shuffle.getNode())
23498 // Check whether a boolean test is testing a boolean value generated by
23499 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23502 // Simplify the following patterns:
23503 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23504 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23505 // to (Op EFLAGS Cond)
23507 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23508 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23509 // to (Op EFLAGS !Cond)
23511 // where Op could be BRCOND or CMOV.
23513 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23514 // Quit if not CMP and SUB with its value result used.
23515 if (Cmp.getOpcode() != X86ISD::CMP &&
23516 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23519 // Quit if not used as a boolean value.
23520 if (CC != X86::COND_E && CC != X86::COND_NE)
23523 // Check CMP operands. One of them should be 0 or 1 and the other should be
23524 // an SetCC or extended from it.
23525 SDValue Op1 = Cmp.getOperand(0);
23526 SDValue Op2 = Cmp.getOperand(1);
23529 const ConstantSDNode* C = nullptr;
23530 bool needOppositeCond = (CC == X86::COND_E);
23531 bool checkAgainstTrue = false; // Is it a comparison against 1?
23533 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23535 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23537 else // Quit if all operands are not constants.
23540 if (C->getZExtValue() == 1) {
23541 needOppositeCond = !needOppositeCond;
23542 checkAgainstTrue = true;
23543 } else if (C->getZExtValue() != 0)
23544 // Quit if the constant is neither 0 or 1.
23547 bool truncatedToBoolWithAnd = false;
23548 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23549 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23550 SetCC.getOpcode() == ISD::TRUNCATE ||
23551 SetCC.getOpcode() == ISD::AND) {
23552 if (SetCC.getOpcode() == ISD::AND) {
23554 ConstantSDNode *CS;
23555 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23556 CS->getZExtValue() == 1)
23558 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23559 CS->getZExtValue() == 1)
23563 SetCC = SetCC.getOperand(OpIdx);
23564 truncatedToBoolWithAnd = true;
23566 SetCC = SetCC.getOperand(0);
23569 switch (SetCC.getOpcode()) {
23570 case X86ISD::SETCC_CARRY:
23571 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23572 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23573 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23574 // truncated to i1 using 'and'.
23575 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23577 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23578 "Invalid use of SETCC_CARRY!");
23580 case X86ISD::SETCC:
23581 // Set the condition code or opposite one if necessary.
23582 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23583 if (needOppositeCond)
23584 CC = X86::GetOppositeBranchCondition(CC);
23585 return SetCC.getOperand(1);
23586 case X86ISD::CMOV: {
23587 // Check whether false/true value has canonical one, i.e. 0 or 1.
23588 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23589 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23590 // Quit if true value is not a constant.
23593 // Quit if false value is not a constant.
23595 SDValue Op = SetCC.getOperand(0);
23596 // Skip 'zext' or 'trunc' node.
23597 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23598 Op.getOpcode() == ISD::TRUNCATE)
23599 Op = Op.getOperand(0);
23600 // A special case for rdrand/rdseed, where 0 is set if false cond is
23602 if ((Op.getOpcode() != X86ISD::RDRAND &&
23603 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23606 // Quit if false value is not the constant 0 or 1.
23607 bool FValIsFalse = true;
23608 if (FVal && FVal->getZExtValue() != 0) {
23609 if (FVal->getZExtValue() != 1)
23611 // If FVal is 1, opposite cond is needed.
23612 needOppositeCond = !needOppositeCond;
23613 FValIsFalse = false;
23615 // Quit if TVal is not the constant opposite of FVal.
23616 if (FValIsFalse && TVal->getZExtValue() != 1)
23618 if (!FValIsFalse && TVal->getZExtValue() != 0)
23620 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23621 if (needOppositeCond)
23622 CC = X86::GetOppositeBranchCondition(CC);
23623 return SetCC.getOperand(3);
23630 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23631 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23632 TargetLowering::DAGCombinerInfo &DCI,
23633 const X86Subtarget *Subtarget) {
23636 // If the flag operand isn't dead, don't touch this CMOV.
23637 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23640 SDValue FalseOp = N->getOperand(0);
23641 SDValue TrueOp = N->getOperand(1);
23642 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23643 SDValue Cond = N->getOperand(3);
23645 if (CC == X86::COND_E || CC == X86::COND_NE) {
23646 switch (Cond.getOpcode()) {
23650 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23651 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23652 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23658 Flags = checkBoolTestSetCCCombine(Cond, CC);
23659 if (Flags.getNode() &&
23660 // Extra check as FCMOV only supports a subset of X86 cond.
23661 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23662 SDValue Ops[] = { FalseOp, TrueOp,
23663 DAG.getConstant(CC, MVT::i8), Flags };
23664 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23667 // If this is a select between two integer constants, try to do some
23668 // optimizations. Note that the operands are ordered the opposite of SELECT
23670 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23671 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23672 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23673 // larger than FalseC (the false value).
23674 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23675 CC = X86::GetOppositeBranchCondition(CC);
23676 std::swap(TrueC, FalseC);
23677 std::swap(TrueOp, FalseOp);
23680 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23681 // This is efficient for any integer data type (including i8/i16) and
23683 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23684 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23685 DAG.getConstant(CC, MVT::i8), Cond);
23687 // Zero extend the condition if needed.
23688 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23690 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23691 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23692 DAG.getConstant(ShAmt, MVT::i8));
23693 if (N->getNumValues() == 2) // Dead flag value?
23694 return DCI.CombineTo(N, Cond, SDValue());
23698 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23699 // for any integer data type, including i8/i16.
23700 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23701 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23702 DAG.getConstant(CC, MVT::i8), Cond);
23704 // Zero extend the condition if needed.
23705 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23706 FalseC->getValueType(0), Cond);
23707 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23708 SDValue(FalseC, 0));
23710 if (N->getNumValues() == 2) // Dead flag value?
23711 return DCI.CombineTo(N, Cond, SDValue());
23715 // Optimize cases that will turn into an LEA instruction. This requires
23716 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23717 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23718 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23719 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23721 bool isFastMultiplier = false;
23723 switch ((unsigned char)Diff) {
23725 case 1: // result = add base, cond
23726 case 2: // result = lea base( , cond*2)
23727 case 3: // result = lea base(cond, cond*2)
23728 case 4: // result = lea base( , cond*4)
23729 case 5: // result = lea base(cond, cond*4)
23730 case 8: // result = lea base( , cond*8)
23731 case 9: // result = lea base(cond, cond*8)
23732 isFastMultiplier = true;
23737 if (isFastMultiplier) {
23738 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23739 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23740 DAG.getConstant(CC, MVT::i8), Cond);
23741 // Zero extend the condition if needed.
23742 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23744 // Scale the condition by the difference.
23746 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23747 DAG.getConstant(Diff, Cond.getValueType()));
23749 // Add the base if non-zero.
23750 if (FalseC->getAPIntValue() != 0)
23751 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23752 SDValue(FalseC, 0));
23753 if (N->getNumValues() == 2) // Dead flag value?
23754 return DCI.CombineTo(N, Cond, SDValue());
23761 // Handle these cases:
23762 // (select (x != c), e, c) -> select (x != c), e, x),
23763 // (select (x == c), c, e) -> select (x == c), x, e)
23764 // where the c is an integer constant, and the "select" is the combination
23765 // of CMOV and CMP.
23767 // The rationale for this change is that the conditional-move from a constant
23768 // needs two instructions, however, conditional-move from a register needs
23769 // only one instruction.
23771 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23772 // some instruction-combining opportunities. This opt needs to be
23773 // postponed as late as possible.
23775 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23776 // the DCI.xxxx conditions are provided to postpone the optimization as
23777 // late as possible.
23779 ConstantSDNode *CmpAgainst = nullptr;
23780 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23781 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23782 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23784 if (CC == X86::COND_NE &&
23785 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23786 CC = X86::GetOppositeBranchCondition(CC);
23787 std::swap(TrueOp, FalseOp);
23790 if (CC == X86::COND_E &&
23791 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23792 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23793 DAG.getConstant(CC, MVT::i8), Cond };
23794 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23802 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23803 const X86Subtarget *Subtarget) {
23804 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23806 default: return SDValue();
23807 // SSE/AVX/AVX2 blend intrinsics.
23808 case Intrinsic::x86_avx2_pblendvb:
23809 case Intrinsic::x86_avx2_pblendw:
23810 case Intrinsic::x86_avx2_pblendd_128:
23811 case Intrinsic::x86_avx2_pblendd_256:
23812 // Don't try to simplify this intrinsic if we don't have AVX2.
23813 if (!Subtarget->hasAVX2())
23816 case Intrinsic::x86_avx_blend_pd_256:
23817 case Intrinsic::x86_avx_blend_ps_256:
23818 case Intrinsic::x86_avx_blendv_pd_256:
23819 case Intrinsic::x86_avx_blendv_ps_256:
23820 // Don't try to simplify this intrinsic if we don't have AVX.
23821 if (!Subtarget->hasAVX())
23824 case Intrinsic::x86_sse41_pblendw:
23825 case Intrinsic::x86_sse41_blendpd:
23826 case Intrinsic::x86_sse41_blendps:
23827 case Intrinsic::x86_sse41_blendvps:
23828 case Intrinsic::x86_sse41_blendvpd:
23829 case Intrinsic::x86_sse41_pblendvb: {
23830 SDValue Op0 = N->getOperand(1);
23831 SDValue Op1 = N->getOperand(2);
23832 SDValue Mask = N->getOperand(3);
23834 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23835 if (!Subtarget->hasSSE41())
23838 // fold (blend A, A, Mask) -> A
23841 // fold (blend A, B, allZeros) -> A
23842 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23844 // fold (blend A, B, allOnes) -> B
23845 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23848 // Simplify the case where the mask is a constant i32 value.
23849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23850 if (C->isNullValue())
23852 if (C->isAllOnesValue())
23859 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23860 case Intrinsic::x86_sse2_psrai_w:
23861 case Intrinsic::x86_sse2_psrai_d:
23862 case Intrinsic::x86_avx2_psrai_w:
23863 case Intrinsic::x86_avx2_psrai_d:
23864 case Intrinsic::x86_sse2_psra_w:
23865 case Intrinsic::x86_sse2_psra_d:
23866 case Intrinsic::x86_avx2_psra_w:
23867 case Intrinsic::x86_avx2_psra_d: {
23868 SDValue Op0 = N->getOperand(1);
23869 SDValue Op1 = N->getOperand(2);
23870 EVT VT = Op0.getValueType();
23871 assert(VT.isVector() && "Expected a vector type!");
23873 if (isa<BuildVectorSDNode>(Op1))
23874 Op1 = Op1.getOperand(0);
23876 if (!isa<ConstantSDNode>(Op1))
23879 EVT SVT = VT.getVectorElementType();
23880 unsigned SVTBits = SVT.getSizeInBits();
23882 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23883 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23884 uint64_t ShAmt = C.getZExtValue();
23886 // Don't try to convert this shift into a ISD::SRA if the shift
23887 // count is bigger than or equal to the element size.
23888 if (ShAmt >= SVTBits)
23891 // Trivial case: if the shift count is zero, then fold this
23892 // into the first operand.
23896 // Replace this packed shift intrinsic with a target independent
23898 SDValue Splat = DAG.getConstant(C, VT);
23899 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23904 /// PerformMulCombine - Optimize a single multiply with constant into two
23905 /// in order to implement it with two cheaper instructions, e.g.
23906 /// LEA + SHL, LEA + LEA.
23907 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23908 TargetLowering::DAGCombinerInfo &DCI) {
23909 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23912 EVT VT = N->getValueType(0);
23913 if (VT != MVT::i64)
23916 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23919 uint64_t MulAmt = C->getZExtValue();
23920 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23923 uint64_t MulAmt1 = 0;
23924 uint64_t MulAmt2 = 0;
23925 if ((MulAmt % 9) == 0) {
23927 MulAmt2 = MulAmt / 9;
23928 } else if ((MulAmt % 5) == 0) {
23930 MulAmt2 = MulAmt / 5;
23931 } else if ((MulAmt % 3) == 0) {
23933 MulAmt2 = MulAmt / 3;
23936 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23939 if (isPowerOf2_64(MulAmt2) &&
23940 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23941 // If second multiplifer is pow2, issue it first. We want the multiply by
23942 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23944 std::swap(MulAmt1, MulAmt2);
23947 if (isPowerOf2_64(MulAmt1))
23948 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23949 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23951 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23952 DAG.getConstant(MulAmt1, VT));
23954 if (isPowerOf2_64(MulAmt2))
23955 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23956 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23958 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23959 DAG.getConstant(MulAmt2, VT));
23961 // Do not add new nodes to DAG combiner worklist.
23962 DCI.CombineTo(N, NewMul, false);
23967 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23968 SDValue N0 = N->getOperand(0);
23969 SDValue N1 = N->getOperand(1);
23970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23971 EVT VT = N0.getValueType();
23973 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23974 // since the result of setcc_c is all zero's or all ones.
23975 if (VT.isInteger() && !VT.isVector() &&
23976 N1C && N0.getOpcode() == ISD::AND &&
23977 N0.getOperand(1).getOpcode() == ISD::Constant) {
23978 SDValue N00 = N0.getOperand(0);
23979 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23980 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23981 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23982 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23983 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23984 APInt ShAmt = N1C->getAPIntValue();
23985 Mask = Mask.shl(ShAmt);
23987 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23988 N00, DAG.getConstant(Mask, VT));
23992 // Hardware support for vector shifts is sparse which makes us scalarize the
23993 // vector operations in many cases. Also, on sandybridge ADD is faster than
23995 // (shl V, 1) -> add V,V
23996 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23997 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23998 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23999 // We shift all of the values by one. In many cases we do not have
24000 // hardware support for this operation. This is better expressed as an ADD
24002 if (N1SplatC->getZExtValue() == 1)
24003 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24009 /// \brief Returns a vector of 0s if the node in input is a vector logical
24010 /// shift by a constant amount which is known to be bigger than or equal
24011 /// to the vector element size in bits.
24012 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24013 const X86Subtarget *Subtarget) {
24014 EVT VT = N->getValueType(0);
24016 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24017 (!Subtarget->hasInt256() ||
24018 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24021 SDValue Amt = N->getOperand(1);
24023 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24024 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24025 APInt ShiftAmt = AmtSplat->getAPIntValue();
24026 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24028 // SSE2/AVX2 logical shifts always return a vector of 0s
24029 // if the shift amount is bigger than or equal to
24030 // the element size. The constant shift amount will be
24031 // encoded as a 8-bit immediate.
24032 if (ShiftAmt.trunc(8).uge(MaxAmount))
24033 return getZeroVector(VT, Subtarget, DAG, DL);
24039 /// PerformShiftCombine - Combine shifts.
24040 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24041 TargetLowering::DAGCombinerInfo &DCI,
24042 const X86Subtarget *Subtarget) {
24043 if (N->getOpcode() == ISD::SHL) {
24044 SDValue V = PerformSHLCombine(N, DAG);
24045 if (V.getNode()) return V;
24048 if (N->getOpcode() != ISD::SRA) {
24049 // Try to fold this logical shift into a zero vector.
24050 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24051 if (V.getNode()) return V;
24057 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24058 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24059 // and friends. Likewise for OR -> CMPNEQSS.
24060 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24061 TargetLowering::DAGCombinerInfo &DCI,
24062 const X86Subtarget *Subtarget) {
24065 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24066 // we're requiring SSE2 for both.
24067 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24068 SDValue N0 = N->getOperand(0);
24069 SDValue N1 = N->getOperand(1);
24070 SDValue CMP0 = N0->getOperand(1);
24071 SDValue CMP1 = N1->getOperand(1);
24074 // The SETCCs should both refer to the same CMP.
24075 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24078 SDValue CMP00 = CMP0->getOperand(0);
24079 SDValue CMP01 = CMP0->getOperand(1);
24080 EVT VT = CMP00.getValueType();
24082 if (VT == MVT::f32 || VT == MVT::f64) {
24083 bool ExpectingFlags = false;
24084 // Check for any users that want flags:
24085 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24086 !ExpectingFlags && UI != UE; ++UI)
24087 switch (UI->getOpcode()) {
24092 ExpectingFlags = true;
24094 case ISD::CopyToReg:
24095 case ISD::SIGN_EXTEND:
24096 case ISD::ZERO_EXTEND:
24097 case ISD::ANY_EXTEND:
24101 if (!ExpectingFlags) {
24102 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24103 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24105 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24106 X86::CondCode tmp = cc0;
24111 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24112 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24113 // FIXME: need symbolic constants for these magic numbers.
24114 // See X86ATTInstPrinter.cpp:printSSECC().
24115 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24116 if (Subtarget->hasAVX512()) {
24117 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24118 CMP01, DAG.getConstant(x86cc, MVT::i8));
24119 if (N->getValueType(0) != MVT::i1)
24120 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24124 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24125 CMP00.getValueType(), CMP00, CMP01,
24126 DAG.getConstant(x86cc, MVT::i8));
24128 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24129 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24131 if (is64BitFP && !Subtarget->is64Bit()) {
24132 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24133 // 64-bit integer, since that's not a legal type. Since
24134 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24135 // bits, but can do this little dance to extract the lowest 32 bits
24136 // and work with those going forward.
24137 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24139 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24141 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24142 Vector32, DAG.getIntPtrConstant(0));
24146 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24147 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24148 DAG.getConstant(1, IntVT));
24149 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24150 return OneBitOfTruth;
24158 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24159 /// so it can be folded inside ANDNP.
24160 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24161 EVT VT = N->getValueType(0);
24163 // Match direct AllOnes for 128 and 256-bit vectors
24164 if (ISD::isBuildVectorAllOnes(N))
24167 // Look through a bit convert.
24168 if (N->getOpcode() == ISD::BITCAST)
24169 N = N->getOperand(0).getNode();
24171 // Sometimes the operand may come from a insert_subvector building a 256-bit
24173 if (VT.is256BitVector() &&
24174 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24175 SDValue V1 = N->getOperand(0);
24176 SDValue V2 = N->getOperand(1);
24178 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24179 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24180 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24181 ISD::isBuildVectorAllOnes(V2.getNode()))
24188 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24189 // register. In most cases we actually compare or select YMM-sized registers
24190 // and mixing the two types creates horrible code. This method optimizes
24191 // some of the transition sequences.
24192 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24193 TargetLowering::DAGCombinerInfo &DCI,
24194 const X86Subtarget *Subtarget) {
24195 EVT VT = N->getValueType(0);
24196 if (!VT.is256BitVector())
24199 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24200 N->getOpcode() == ISD::ZERO_EXTEND ||
24201 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24203 SDValue Narrow = N->getOperand(0);
24204 EVT NarrowVT = Narrow->getValueType(0);
24205 if (!NarrowVT.is128BitVector())
24208 if (Narrow->getOpcode() != ISD::XOR &&
24209 Narrow->getOpcode() != ISD::AND &&
24210 Narrow->getOpcode() != ISD::OR)
24213 SDValue N0 = Narrow->getOperand(0);
24214 SDValue N1 = Narrow->getOperand(1);
24217 // The Left side has to be a trunc.
24218 if (N0.getOpcode() != ISD::TRUNCATE)
24221 // The type of the truncated inputs.
24222 EVT WideVT = N0->getOperand(0)->getValueType(0);
24226 // The right side has to be a 'trunc' or a constant vector.
24227 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24228 ConstantSDNode *RHSConstSplat = nullptr;
24229 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24230 RHSConstSplat = RHSBV->getConstantSplatNode();
24231 if (!RHSTrunc && !RHSConstSplat)
24234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24236 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24239 // Set N0 and N1 to hold the inputs to the new wide operation.
24240 N0 = N0->getOperand(0);
24241 if (RHSConstSplat) {
24242 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24243 SDValue(RHSConstSplat, 0));
24244 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24245 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24246 } else if (RHSTrunc) {
24247 N1 = N1->getOperand(0);
24250 // Generate the wide operation.
24251 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24252 unsigned Opcode = N->getOpcode();
24254 case ISD::ANY_EXTEND:
24256 case ISD::ZERO_EXTEND: {
24257 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24258 APInt Mask = APInt::getAllOnesValue(InBits);
24259 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24260 return DAG.getNode(ISD::AND, DL, VT,
24261 Op, DAG.getConstant(Mask, VT));
24263 case ISD::SIGN_EXTEND:
24264 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24265 Op, DAG.getValueType(NarrowVT));
24267 llvm_unreachable("Unexpected opcode");
24271 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24272 TargetLowering::DAGCombinerInfo &DCI,
24273 const X86Subtarget *Subtarget) {
24274 EVT VT = N->getValueType(0);
24275 if (DCI.isBeforeLegalizeOps())
24278 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24282 // Create BEXTR instructions
24283 // BEXTR is ((X >> imm) & (2**size-1))
24284 if (VT == MVT::i32 || VT == MVT::i64) {
24285 SDValue N0 = N->getOperand(0);
24286 SDValue N1 = N->getOperand(1);
24289 // Check for BEXTR.
24290 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24291 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24292 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24293 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24294 if (MaskNode && ShiftNode) {
24295 uint64_t Mask = MaskNode->getZExtValue();
24296 uint64_t Shift = ShiftNode->getZExtValue();
24297 if (isMask_64(Mask)) {
24298 uint64_t MaskSize = CountPopulation_64(Mask);
24299 if (Shift + MaskSize <= VT.getSizeInBits())
24300 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24301 DAG.getConstant(Shift | (MaskSize << 8), VT));
24309 // Want to form ANDNP nodes:
24310 // 1) In the hopes of then easily combining them with OR and AND nodes
24311 // to form PBLEND/PSIGN.
24312 // 2) To match ANDN packed intrinsics
24313 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24316 SDValue N0 = N->getOperand(0);
24317 SDValue N1 = N->getOperand(1);
24320 // Check LHS for vnot
24321 if (N0.getOpcode() == ISD::XOR &&
24322 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24323 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24324 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24326 // Check RHS for vnot
24327 if (N1.getOpcode() == ISD::XOR &&
24328 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24329 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24330 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24335 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24336 TargetLowering::DAGCombinerInfo &DCI,
24337 const X86Subtarget *Subtarget) {
24338 if (DCI.isBeforeLegalizeOps())
24341 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24345 SDValue N0 = N->getOperand(0);
24346 SDValue N1 = N->getOperand(1);
24347 EVT VT = N->getValueType(0);
24349 // look for psign/blend
24350 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24351 if (!Subtarget->hasSSSE3() ||
24352 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24355 // Canonicalize pandn to RHS
24356 if (N0.getOpcode() == X86ISD::ANDNP)
24358 // or (and (m, y), (pandn m, x))
24359 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24360 SDValue Mask = N1.getOperand(0);
24361 SDValue X = N1.getOperand(1);
24363 if (N0.getOperand(0) == Mask)
24364 Y = N0.getOperand(1);
24365 if (N0.getOperand(1) == Mask)
24366 Y = N0.getOperand(0);
24368 // Check to see if the mask appeared in both the AND and ANDNP and
24372 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24373 // Look through mask bitcast.
24374 if (Mask.getOpcode() == ISD::BITCAST)
24375 Mask = Mask.getOperand(0);
24376 if (X.getOpcode() == ISD::BITCAST)
24377 X = X.getOperand(0);
24378 if (Y.getOpcode() == ISD::BITCAST)
24379 Y = Y.getOperand(0);
24381 EVT MaskVT = Mask.getValueType();
24383 // Validate that the Mask operand is a vector sra node.
24384 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24385 // there is no psrai.b
24386 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24387 unsigned SraAmt = ~0;
24388 if (Mask.getOpcode() == ISD::SRA) {
24389 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24390 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24391 SraAmt = AmtConst->getZExtValue();
24392 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24393 SDValue SraC = Mask.getOperand(1);
24394 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24396 if ((SraAmt + 1) != EltBits)
24401 // Now we know we at least have a plendvb with the mask val. See if
24402 // we can form a psignb/w/d.
24403 // psign = x.type == y.type == mask.type && y = sub(0, x);
24404 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24405 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24406 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24407 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24408 "Unsupported VT for PSIGN");
24409 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24410 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24412 // PBLENDVB only available on SSE 4.1
24413 if (!Subtarget->hasSSE41())
24416 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24418 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24419 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24420 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24421 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24422 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24426 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24429 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24430 MachineFunction &MF = DAG.getMachineFunction();
24431 bool OptForSize = MF.getFunction()->getAttributes().
24432 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24434 // SHLD/SHRD instructions have lower register pressure, but on some
24435 // platforms they have higher latency than the equivalent
24436 // series of shifts/or that would otherwise be generated.
24437 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24438 // have higher latencies and we are not optimizing for size.
24439 if (!OptForSize && Subtarget->isSHLDSlow())
24442 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24444 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24446 if (!N0.hasOneUse() || !N1.hasOneUse())
24449 SDValue ShAmt0 = N0.getOperand(1);
24450 if (ShAmt0.getValueType() != MVT::i8)
24452 SDValue ShAmt1 = N1.getOperand(1);
24453 if (ShAmt1.getValueType() != MVT::i8)
24455 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24456 ShAmt0 = ShAmt0.getOperand(0);
24457 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24458 ShAmt1 = ShAmt1.getOperand(0);
24461 unsigned Opc = X86ISD::SHLD;
24462 SDValue Op0 = N0.getOperand(0);
24463 SDValue Op1 = N1.getOperand(0);
24464 if (ShAmt0.getOpcode() == ISD::SUB) {
24465 Opc = X86ISD::SHRD;
24466 std::swap(Op0, Op1);
24467 std::swap(ShAmt0, ShAmt1);
24470 unsigned Bits = VT.getSizeInBits();
24471 if (ShAmt1.getOpcode() == ISD::SUB) {
24472 SDValue Sum = ShAmt1.getOperand(0);
24473 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24474 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24475 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24476 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24477 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24478 return DAG.getNode(Opc, DL, VT,
24480 DAG.getNode(ISD::TRUNCATE, DL,
24483 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24484 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24486 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24487 return DAG.getNode(Opc, DL, VT,
24488 N0.getOperand(0), N1.getOperand(0),
24489 DAG.getNode(ISD::TRUNCATE, DL,
24496 // Generate NEG and CMOV for integer abs.
24497 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24498 EVT VT = N->getValueType(0);
24500 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24501 // 8-bit integer abs to NEG and CMOV.
24502 if (VT.isInteger() && VT.getSizeInBits() == 8)
24505 SDValue N0 = N->getOperand(0);
24506 SDValue N1 = N->getOperand(1);
24509 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24510 // and change it to SUB and CMOV.
24511 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24512 N0.getOpcode() == ISD::ADD &&
24513 N0.getOperand(1) == N1 &&
24514 N1.getOpcode() == ISD::SRA &&
24515 N1.getOperand(0) == N0.getOperand(0))
24516 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24517 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24518 // Generate SUB & CMOV.
24519 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24520 DAG.getConstant(0, VT), N0.getOperand(0));
24522 SDValue Ops[] = { N0.getOperand(0), Neg,
24523 DAG.getConstant(X86::COND_GE, MVT::i8),
24524 SDValue(Neg.getNode(), 1) };
24525 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24530 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24531 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24532 TargetLowering::DAGCombinerInfo &DCI,
24533 const X86Subtarget *Subtarget) {
24534 if (DCI.isBeforeLegalizeOps())
24537 if (Subtarget->hasCMov()) {
24538 SDValue RV = performIntegerAbsCombine(N, DAG);
24546 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24547 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24548 TargetLowering::DAGCombinerInfo &DCI,
24549 const X86Subtarget *Subtarget) {
24550 LoadSDNode *Ld = cast<LoadSDNode>(N);
24551 EVT RegVT = Ld->getValueType(0);
24552 EVT MemVT = Ld->getMemoryVT();
24554 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24556 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24557 // into two 16-byte operations.
24558 ISD::LoadExtType Ext = Ld->getExtensionType();
24559 unsigned Alignment = Ld->getAlignment();
24560 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24561 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24562 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24563 unsigned NumElems = RegVT.getVectorNumElements();
24567 SDValue Ptr = Ld->getBasePtr();
24568 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24570 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24572 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24573 Ld->getPointerInfo(), Ld->isVolatile(),
24574 Ld->isNonTemporal(), Ld->isInvariant(),
24576 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24577 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24578 Ld->getPointerInfo(), Ld->isVolatile(),
24579 Ld->isNonTemporal(), Ld->isInvariant(),
24580 std::min(16U, Alignment));
24581 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24583 Load2.getValue(1));
24585 SDValue NewVec = DAG.getUNDEF(RegVT);
24586 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24587 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24588 return DCI.CombineTo(N, NewVec, TF, true);
24594 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24595 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24596 const X86Subtarget *Subtarget) {
24597 StoreSDNode *St = cast<StoreSDNode>(N);
24598 EVT VT = St->getValue().getValueType();
24599 EVT StVT = St->getMemoryVT();
24601 SDValue StoredVal = St->getOperand(1);
24602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24604 // If we are saving a concatenation of two XMM registers and 32-byte stores
24605 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24606 unsigned Alignment = St->getAlignment();
24607 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24608 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24609 StVT == VT && !IsAligned) {
24610 unsigned NumElems = VT.getVectorNumElements();
24614 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24615 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24617 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24618 SDValue Ptr0 = St->getBasePtr();
24619 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24621 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24622 St->getPointerInfo(), St->isVolatile(),
24623 St->isNonTemporal(), Alignment);
24624 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24625 St->getPointerInfo(), St->isVolatile(),
24626 St->isNonTemporal(),
24627 std::min(16U, Alignment));
24628 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24631 // Optimize trunc store (of multiple scalars) to shuffle and store.
24632 // First, pack all of the elements in one place. Next, store to memory
24633 // in fewer chunks.
24634 if (St->isTruncatingStore() && VT.isVector()) {
24635 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24636 unsigned NumElems = VT.getVectorNumElements();
24637 assert(StVT != VT && "Cannot truncate to the same type");
24638 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24639 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24641 // From, To sizes and ElemCount must be pow of two
24642 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24643 // We are going to use the original vector elt for storing.
24644 // Accumulated smaller vector elements must be a multiple of the store size.
24645 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24647 unsigned SizeRatio = FromSz / ToSz;
24649 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24651 // Create a type on which we perform the shuffle
24652 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24653 StVT.getScalarType(), NumElems*SizeRatio);
24655 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24657 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24658 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24659 for (unsigned i = 0; i != NumElems; ++i)
24660 ShuffleVec[i] = i * SizeRatio;
24662 // Can't shuffle using an illegal type.
24663 if (!TLI.isTypeLegal(WideVecVT))
24666 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24667 DAG.getUNDEF(WideVecVT),
24669 // At this point all of the data is stored at the bottom of the
24670 // register. We now need to save it to mem.
24672 // Find the largest store unit
24673 MVT StoreType = MVT::i8;
24674 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24675 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24676 MVT Tp = (MVT::SimpleValueType)tp;
24677 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24681 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24682 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24683 (64 <= NumElems * ToSz))
24684 StoreType = MVT::f64;
24686 // Bitcast the original vector into a vector of store-size units
24687 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24688 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24689 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24690 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24691 SmallVector<SDValue, 8> Chains;
24692 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24693 TLI.getPointerTy());
24694 SDValue Ptr = St->getBasePtr();
24696 // Perform one or more big stores into memory.
24697 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24698 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24699 StoreType, ShuffWide,
24700 DAG.getIntPtrConstant(i));
24701 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24702 St->getPointerInfo(), St->isVolatile(),
24703 St->isNonTemporal(), St->getAlignment());
24704 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24705 Chains.push_back(Ch);
24708 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24711 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24712 // the FP state in cases where an emms may be missing.
24713 // A preferable solution to the general problem is to figure out the right
24714 // places to insert EMMS. This qualifies as a quick hack.
24716 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24717 if (VT.getSizeInBits() != 64)
24720 const Function *F = DAG.getMachineFunction().getFunction();
24721 bool NoImplicitFloatOps = F->getAttributes().
24722 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24723 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24724 && Subtarget->hasSSE2();
24725 if ((VT.isVector() ||
24726 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24727 isa<LoadSDNode>(St->getValue()) &&
24728 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24729 St->getChain().hasOneUse() && !St->isVolatile()) {
24730 SDNode* LdVal = St->getValue().getNode();
24731 LoadSDNode *Ld = nullptr;
24732 int TokenFactorIndex = -1;
24733 SmallVector<SDValue, 8> Ops;
24734 SDNode* ChainVal = St->getChain().getNode();
24735 // Must be a store of a load. We currently handle two cases: the load
24736 // is a direct child, and it's under an intervening TokenFactor. It is
24737 // possible to dig deeper under nested TokenFactors.
24738 if (ChainVal == LdVal)
24739 Ld = cast<LoadSDNode>(St->getChain());
24740 else if (St->getValue().hasOneUse() &&
24741 ChainVal->getOpcode() == ISD::TokenFactor) {
24742 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24743 if (ChainVal->getOperand(i).getNode() == LdVal) {
24744 TokenFactorIndex = i;
24745 Ld = cast<LoadSDNode>(St->getValue());
24747 Ops.push_back(ChainVal->getOperand(i));
24751 if (!Ld || !ISD::isNormalLoad(Ld))
24754 // If this is not the MMX case, i.e. we are just turning i64 load/store
24755 // into f64 load/store, avoid the transformation if there are multiple
24756 // uses of the loaded value.
24757 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24762 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24763 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24765 if (Subtarget->is64Bit() || F64IsLegal) {
24766 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24767 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24768 Ld->getPointerInfo(), Ld->isVolatile(),
24769 Ld->isNonTemporal(), Ld->isInvariant(),
24770 Ld->getAlignment());
24771 SDValue NewChain = NewLd.getValue(1);
24772 if (TokenFactorIndex != -1) {
24773 Ops.push_back(NewChain);
24774 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24776 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24777 St->getPointerInfo(),
24778 St->isVolatile(), St->isNonTemporal(),
24779 St->getAlignment());
24782 // Otherwise, lower to two pairs of 32-bit loads / stores.
24783 SDValue LoAddr = Ld->getBasePtr();
24784 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24785 DAG.getConstant(4, MVT::i32));
24787 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24788 Ld->getPointerInfo(),
24789 Ld->isVolatile(), Ld->isNonTemporal(),
24790 Ld->isInvariant(), Ld->getAlignment());
24791 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24792 Ld->getPointerInfo().getWithOffset(4),
24793 Ld->isVolatile(), Ld->isNonTemporal(),
24795 MinAlign(Ld->getAlignment(), 4));
24797 SDValue NewChain = LoLd.getValue(1);
24798 if (TokenFactorIndex != -1) {
24799 Ops.push_back(LoLd);
24800 Ops.push_back(HiLd);
24801 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24804 LoAddr = St->getBasePtr();
24805 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24806 DAG.getConstant(4, MVT::i32));
24808 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24809 St->getPointerInfo(),
24810 St->isVolatile(), St->isNonTemporal(),
24811 St->getAlignment());
24812 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24813 St->getPointerInfo().getWithOffset(4),
24815 St->isNonTemporal(),
24816 MinAlign(St->getAlignment(), 4));
24817 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24822 /// Return 'true' if this vector operation is "horizontal"
24823 /// and return the operands for the horizontal operation in LHS and RHS. A
24824 /// horizontal operation performs the binary operation on successive elements
24825 /// of its first operand, then on successive elements of its second operand,
24826 /// returning the resulting values in a vector. For example, if
24827 /// A = < float a0, float a1, float a2, float a3 >
24829 /// B = < float b0, float b1, float b2, float b3 >
24830 /// then the result of doing a horizontal operation on A and B is
24831 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24832 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24833 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24834 /// set to A, RHS to B, and the routine returns 'true'.
24835 /// Note that the binary operation should have the property that if one of the
24836 /// operands is UNDEF then the result is UNDEF.
24837 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24838 // Look for the following pattern: if
24839 // A = < float a0, float a1, float a2, float a3 >
24840 // B = < float b0, float b1, float b2, float b3 >
24842 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24843 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24844 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24845 // which is A horizontal-op B.
24847 // At least one of the operands should be a vector shuffle.
24848 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24849 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24852 MVT VT = LHS.getSimpleValueType();
24854 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24855 "Unsupported vector type for horizontal add/sub");
24857 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24858 // operate independently on 128-bit lanes.
24859 unsigned NumElts = VT.getVectorNumElements();
24860 unsigned NumLanes = VT.getSizeInBits()/128;
24861 unsigned NumLaneElts = NumElts / NumLanes;
24862 assert((NumLaneElts % 2 == 0) &&
24863 "Vector type should have an even number of elements in each lane");
24864 unsigned HalfLaneElts = NumLaneElts/2;
24866 // View LHS in the form
24867 // LHS = VECTOR_SHUFFLE A, B, LMask
24868 // If LHS is not a shuffle then pretend it is the shuffle
24869 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24870 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24873 SmallVector<int, 16> LMask(NumElts);
24874 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24875 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24876 A = LHS.getOperand(0);
24877 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24878 B = LHS.getOperand(1);
24879 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24880 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24882 if (LHS.getOpcode() != ISD::UNDEF)
24884 for (unsigned i = 0; i != NumElts; ++i)
24888 // Likewise, view RHS in the form
24889 // RHS = VECTOR_SHUFFLE C, D, RMask
24891 SmallVector<int, 16> RMask(NumElts);
24892 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24893 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24894 C = RHS.getOperand(0);
24895 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24896 D = RHS.getOperand(1);
24897 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24898 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24900 if (RHS.getOpcode() != ISD::UNDEF)
24902 for (unsigned i = 0; i != NumElts; ++i)
24906 // Check that the shuffles are both shuffling the same vectors.
24907 if (!(A == C && B == D) && !(A == D && B == C))
24910 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24911 if (!A.getNode() && !B.getNode())
24914 // If A and B occur in reverse order in RHS, then "swap" them (which means
24915 // rewriting the mask).
24917 CommuteVectorShuffleMask(RMask, NumElts);
24919 // At this point LHS and RHS are equivalent to
24920 // LHS = VECTOR_SHUFFLE A, B, LMask
24921 // RHS = VECTOR_SHUFFLE A, B, RMask
24922 // Check that the masks correspond to performing a horizontal operation.
24923 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24924 for (unsigned i = 0; i != NumLaneElts; ++i) {
24925 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24927 // Ignore any UNDEF components.
24928 if (LIdx < 0 || RIdx < 0 ||
24929 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24930 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24933 // Check that successive elements are being operated on. If not, this is
24934 // not a horizontal operation.
24935 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24936 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24937 if (!(LIdx == Index && RIdx == Index + 1) &&
24938 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24943 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24944 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24948 /// Do target-specific dag combines on floating point adds.
24949 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24950 const X86Subtarget *Subtarget) {
24951 EVT VT = N->getValueType(0);
24952 SDValue LHS = N->getOperand(0);
24953 SDValue RHS = N->getOperand(1);
24955 // Try to synthesize horizontal adds from adds of shuffles.
24956 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24957 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24958 isHorizontalBinOp(LHS, RHS, true))
24959 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24963 /// Do target-specific dag combines on floating point subs.
24964 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24965 const X86Subtarget *Subtarget) {
24966 EVT VT = N->getValueType(0);
24967 SDValue LHS = N->getOperand(0);
24968 SDValue RHS = N->getOperand(1);
24970 // Try to synthesize horizontal subs from subs of shuffles.
24971 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24972 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24973 isHorizontalBinOp(LHS, RHS, false))
24974 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24978 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24979 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24980 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24981 // F[X]OR(0.0, x) -> x
24982 // F[X]OR(x, 0.0) -> x
24983 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24984 if (C->getValueAPF().isPosZero())
24985 return N->getOperand(1);
24986 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24987 if (C->getValueAPF().isPosZero())
24988 return N->getOperand(0);
24992 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24993 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24994 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24996 // Only perform optimizations if UnsafeMath is used.
24997 if (!DAG.getTarget().Options.UnsafeFPMath)
25000 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25001 // into FMINC and FMAXC, which are Commutative operations.
25002 unsigned NewOp = 0;
25003 switch (N->getOpcode()) {
25004 default: llvm_unreachable("unknown opcode");
25005 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25006 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25009 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25010 N->getOperand(0), N->getOperand(1));
25013 /// Do target-specific dag combines on X86ISD::FAND nodes.
25014 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25015 // FAND(0.0, x) -> 0.0
25016 // FAND(x, 0.0) -> 0.0
25017 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25018 if (C->getValueAPF().isPosZero())
25019 return N->getOperand(0);
25020 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25021 if (C->getValueAPF().isPosZero())
25022 return N->getOperand(1);
25026 /// Do target-specific dag combines on X86ISD::FANDN nodes
25027 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25028 // FANDN(x, 0.0) -> 0.0
25029 // FANDN(0.0, x) -> x
25030 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25031 if (C->getValueAPF().isPosZero())
25032 return N->getOperand(1);
25033 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25034 if (C->getValueAPF().isPosZero())
25035 return N->getOperand(1);
25039 static SDValue PerformBTCombine(SDNode *N,
25041 TargetLowering::DAGCombinerInfo &DCI) {
25042 // BT ignores high bits in the bit index operand.
25043 SDValue Op1 = N->getOperand(1);
25044 if (Op1.hasOneUse()) {
25045 unsigned BitWidth = Op1.getValueSizeInBits();
25046 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25047 APInt KnownZero, KnownOne;
25048 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25049 !DCI.isBeforeLegalizeOps());
25050 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25051 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25052 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25053 DCI.CommitTargetLoweringOpt(TLO);
25058 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25059 SDValue Op = N->getOperand(0);
25060 if (Op.getOpcode() == ISD::BITCAST)
25061 Op = Op.getOperand(0);
25062 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25063 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25064 VT.getVectorElementType().getSizeInBits() ==
25065 OpVT.getVectorElementType().getSizeInBits()) {
25066 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25071 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25072 const X86Subtarget *Subtarget) {
25073 EVT VT = N->getValueType(0);
25074 if (!VT.isVector())
25077 SDValue N0 = N->getOperand(0);
25078 SDValue N1 = N->getOperand(1);
25079 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25082 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25083 // both SSE and AVX2 since there is no sign-extended shift right
25084 // operation on a vector with 64-bit elements.
25085 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25086 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25087 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25088 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25089 SDValue N00 = N0.getOperand(0);
25091 // EXTLOAD has a better solution on AVX2,
25092 // it may be replaced with X86ISD::VSEXT node.
25093 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25094 if (!ISD::isNormalLoad(N00.getNode()))
25097 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25098 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25100 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25106 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25107 TargetLowering::DAGCombinerInfo &DCI,
25108 const X86Subtarget *Subtarget) {
25109 SDValue N0 = N->getOperand(0);
25110 EVT VT = N->getValueType(0);
25112 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25113 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25114 // This exposes the sext to the sdivrem lowering, so that it directly extends
25115 // from AH (which we otherwise need to do contortions to access).
25116 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25117 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25119 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25120 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25121 N0.getOperand(0), N0.getOperand(1));
25122 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25123 return R.getValue(1);
25126 if (!DCI.isBeforeLegalizeOps())
25129 if (!Subtarget->hasFp256())
25132 if (VT.isVector() && VT.getSizeInBits() == 256) {
25133 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25141 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25142 const X86Subtarget* Subtarget) {
25144 EVT VT = N->getValueType(0);
25146 // Let legalize expand this if it isn't a legal type yet.
25147 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25150 EVT ScalarVT = VT.getScalarType();
25151 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25152 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25155 SDValue A = N->getOperand(0);
25156 SDValue B = N->getOperand(1);
25157 SDValue C = N->getOperand(2);
25159 bool NegA = (A.getOpcode() == ISD::FNEG);
25160 bool NegB = (B.getOpcode() == ISD::FNEG);
25161 bool NegC = (C.getOpcode() == ISD::FNEG);
25163 // Negative multiplication when NegA xor NegB
25164 bool NegMul = (NegA != NegB);
25166 A = A.getOperand(0);
25168 B = B.getOperand(0);
25170 C = C.getOperand(0);
25174 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25176 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25178 return DAG.getNode(Opcode, dl, VT, A, B, C);
25181 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25182 TargetLowering::DAGCombinerInfo &DCI,
25183 const X86Subtarget *Subtarget) {
25184 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25185 // (and (i32 x86isd::setcc_carry), 1)
25186 // This eliminates the zext. This transformation is necessary because
25187 // ISD::SETCC is always legalized to i8.
25189 SDValue N0 = N->getOperand(0);
25190 EVT VT = N->getValueType(0);
25192 if (N0.getOpcode() == ISD::AND &&
25194 N0.getOperand(0).hasOneUse()) {
25195 SDValue N00 = N0.getOperand(0);
25196 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25197 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25198 if (!C || C->getZExtValue() != 1)
25200 return DAG.getNode(ISD::AND, dl, VT,
25201 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25202 N00.getOperand(0), N00.getOperand(1)),
25203 DAG.getConstant(1, VT));
25207 if (N0.getOpcode() == ISD::TRUNCATE &&
25209 N0.getOperand(0).hasOneUse()) {
25210 SDValue N00 = N0.getOperand(0);
25211 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25212 return DAG.getNode(ISD::AND, dl, VT,
25213 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25214 N00.getOperand(0), N00.getOperand(1)),
25215 DAG.getConstant(1, VT));
25218 if (VT.is256BitVector()) {
25219 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25224 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25225 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25226 // This exposes the zext to the udivrem lowering, so that it directly extends
25227 // from AH (which we otherwise need to do contortions to access).
25228 if (N0.getOpcode() == ISD::UDIVREM &&
25229 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25230 (VT == MVT::i32 || VT == MVT::i64)) {
25231 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25232 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25233 N0.getOperand(0), N0.getOperand(1));
25234 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25235 return R.getValue(1);
25241 // Optimize x == -y --> x+y == 0
25242 // x != -y --> x+y != 0
25243 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25244 const X86Subtarget* Subtarget) {
25245 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25246 SDValue LHS = N->getOperand(0);
25247 SDValue RHS = N->getOperand(1);
25248 EVT VT = N->getValueType(0);
25251 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25252 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25253 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25254 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25255 LHS.getValueType(), RHS, LHS.getOperand(1));
25256 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25257 addV, DAG.getConstant(0, addV.getValueType()), CC);
25259 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25261 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25262 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25263 RHS.getValueType(), LHS, RHS.getOperand(1));
25264 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25265 addV, DAG.getConstant(0, addV.getValueType()), CC);
25268 if (VT.getScalarType() == MVT::i1) {
25269 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25270 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25271 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25272 if (!IsSEXT0 && !IsVZero0)
25274 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25275 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25276 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25278 if (!IsSEXT1 && !IsVZero1)
25281 if (IsSEXT0 && IsVZero1) {
25282 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25283 if (CC == ISD::SETEQ)
25284 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25285 return LHS.getOperand(0);
25287 if (IsSEXT1 && IsVZero0) {
25288 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25289 if (CC == ISD::SETEQ)
25290 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25291 return RHS.getOperand(0);
25298 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25299 const X86Subtarget *Subtarget) {
25301 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25302 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25303 "X86insertps is only defined for v4x32");
25305 SDValue Ld = N->getOperand(1);
25306 if (MayFoldLoad(Ld)) {
25307 // Extract the countS bits from the immediate so we can get the proper
25308 // address when narrowing the vector load to a specific element.
25309 // When the second source op is a memory address, interps doesn't use
25310 // countS and just gets an f32 from that address.
25311 unsigned DestIndex =
25312 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25313 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25317 // Create this as a scalar to vector to match the instruction pattern.
25318 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25319 // countS bits are ignored when loading from memory on insertps, which
25320 // means we don't need to explicitly set them to 0.
25321 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25322 LoadScalarToVector, N->getOperand(2));
25325 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25326 // as "sbb reg,reg", since it can be extended without zext and produces
25327 // an all-ones bit which is more useful than 0/1 in some cases.
25328 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25331 return DAG.getNode(ISD::AND, DL, VT,
25332 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25333 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25334 DAG.getConstant(1, VT));
25335 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25336 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25337 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25338 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25341 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25342 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25343 TargetLowering::DAGCombinerInfo &DCI,
25344 const X86Subtarget *Subtarget) {
25346 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25347 SDValue EFLAGS = N->getOperand(1);
25349 if (CC == X86::COND_A) {
25350 // Try to convert COND_A into COND_B in an attempt to facilitate
25351 // materializing "setb reg".
25353 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25354 // cannot take an immediate as its first operand.
25356 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25357 EFLAGS.getValueType().isInteger() &&
25358 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25359 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25360 EFLAGS.getNode()->getVTList(),
25361 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25362 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25363 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25367 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25368 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25370 if (CC == X86::COND_B)
25371 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25375 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25376 if (Flags.getNode()) {
25377 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25378 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25384 // Optimize branch condition evaluation.
25386 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25387 TargetLowering::DAGCombinerInfo &DCI,
25388 const X86Subtarget *Subtarget) {
25390 SDValue Chain = N->getOperand(0);
25391 SDValue Dest = N->getOperand(1);
25392 SDValue EFLAGS = N->getOperand(3);
25393 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25397 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25398 if (Flags.getNode()) {
25399 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25400 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25407 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25408 SelectionDAG &DAG) {
25409 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25410 // optimize away operation when it's from a constant.
25412 // The general transformation is:
25413 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25414 // AND(VECTOR_CMP(x,y), constant2)
25415 // constant2 = UNARYOP(constant)
25417 // Early exit if this isn't a vector operation, the operand of the
25418 // unary operation isn't a bitwise AND, or if the sizes of the operations
25419 // aren't the same.
25420 EVT VT = N->getValueType(0);
25421 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25422 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25423 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25426 // Now check that the other operand of the AND is a constant. We could
25427 // make the transformation for non-constant splats as well, but it's unclear
25428 // that would be a benefit as it would not eliminate any operations, just
25429 // perform one more step in scalar code before moving to the vector unit.
25430 if (BuildVectorSDNode *BV =
25431 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25432 // Bail out if the vector isn't a constant.
25433 if (!BV->isConstant())
25436 // Everything checks out. Build up the new and improved node.
25438 EVT IntVT = BV->getValueType(0);
25439 // Create a new constant of the appropriate type for the transformed
25441 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25442 // The AND node needs bitcasts to/from an integer vector type around it.
25443 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25444 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25445 N->getOperand(0)->getOperand(0), MaskConst);
25446 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25453 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25454 const X86TargetLowering *XTLI) {
25455 // First try to optimize away the conversion entirely when it's
25456 // conditionally from a constant. Vectors only.
25457 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25458 if (Res != SDValue())
25461 // Now move on to more general possibilities.
25462 SDValue Op0 = N->getOperand(0);
25463 EVT InVT = Op0->getValueType(0);
25465 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25466 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25468 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25469 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25470 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25473 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25474 // a 32-bit target where SSE doesn't support i64->FP operations.
25475 if (Op0.getOpcode() == ISD::LOAD) {
25476 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25477 EVT VT = Ld->getValueType(0);
25478 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25479 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25480 !XTLI->getSubtarget()->is64Bit() &&
25482 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25483 Ld->getChain(), Op0, DAG);
25484 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25491 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25492 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25493 X86TargetLowering::DAGCombinerInfo &DCI) {
25494 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25495 // the result is either zero or one (depending on the input carry bit).
25496 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25497 if (X86::isZeroNode(N->getOperand(0)) &&
25498 X86::isZeroNode(N->getOperand(1)) &&
25499 // We don't have a good way to replace an EFLAGS use, so only do this when
25501 SDValue(N, 1).use_empty()) {
25503 EVT VT = N->getValueType(0);
25504 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25505 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25506 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25507 DAG.getConstant(X86::COND_B,MVT::i8),
25509 DAG.getConstant(1, VT));
25510 return DCI.CombineTo(N, Res1, CarryOut);
25516 // fold (add Y, (sete X, 0)) -> adc 0, Y
25517 // (add Y, (setne X, 0)) -> sbb -1, Y
25518 // (sub (sete X, 0), Y) -> sbb 0, Y
25519 // (sub (setne X, 0), Y) -> adc -1, Y
25520 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25523 // Look through ZExts.
25524 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25525 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25528 SDValue SetCC = Ext.getOperand(0);
25529 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25532 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25533 if (CC != X86::COND_E && CC != X86::COND_NE)
25536 SDValue Cmp = SetCC.getOperand(1);
25537 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25538 !X86::isZeroNode(Cmp.getOperand(1)) ||
25539 !Cmp.getOperand(0).getValueType().isInteger())
25542 SDValue CmpOp0 = Cmp.getOperand(0);
25543 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25544 DAG.getConstant(1, CmpOp0.getValueType()));
25546 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25547 if (CC == X86::COND_NE)
25548 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25549 DL, OtherVal.getValueType(), OtherVal,
25550 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25551 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25552 DL, OtherVal.getValueType(), OtherVal,
25553 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25556 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25557 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25558 const X86Subtarget *Subtarget) {
25559 EVT VT = N->getValueType(0);
25560 SDValue Op0 = N->getOperand(0);
25561 SDValue Op1 = N->getOperand(1);
25563 // Try to synthesize horizontal adds from adds of shuffles.
25564 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25565 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25566 isHorizontalBinOp(Op0, Op1, true))
25567 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25569 return OptimizeConditionalInDecrement(N, DAG);
25572 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25573 const X86Subtarget *Subtarget) {
25574 SDValue Op0 = N->getOperand(0);
25575 SDValue Op1 = N->getOperand(1);
25577 // X86 can't encode an immediate LHS of a sub. See if we can push the
25578 // negation into a preceding instruction.
25579 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25580 // If the RHS of the sub is a XOR with one use and a constant, invert the
25581 // immediate. Then add one to the LHS of the sub so we can turn
25582 // X-Y -> X+~Y+1, saving one register.
25583 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25584 isa<ConstantSDNode>(Op1.getOperand(1))) {
25585 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25586 EVT VT = Op0.getValueType();
25587 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25589 DAG.getConstant(~XorC, VT));
25590 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25591 DAG.getConstant(C->getAPIntValue()+1, VT));
25595 // Try to synthesize horizontal adds from adds of shuffles.
25596 EVT VT = N->getValueType(0);
25597 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25598 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25599 isHorizontalBinOp(Op0, Op1, true))
25600 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25602 return OptimizeConditionalInDecrement(N, DAG);
25605 /// performVZEXTCombine - Performs build vector combines
25606 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25607 TargetLowering::DAGCombinerInfo &DCI,
25608 const X86Subtarget *Subtarget) {
25610 MVT VT = N->getSimpleValueType(0);
25611 SDValue Op = N->getOperand(0);
25612 MVT OpVT = Op.getSimpleValueType();
25613 MVT OpEltVT = OpVT.getVectorElementType();
25614 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25616 // (vzext (bitcast (vzext (x)) -> (vzext x)
25618 while (V.getOpcode() == ISD::BITCAST)
25619 V = V.getOperand(0);
25621 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25622 MVT InnerVT = V.getSimpleValueType();
25623 MVT InnerEltVT = InnerVT.getVectorElementType();
25625 // If the element sizes match exactly, we can just do one larger vzext. This
25626 // is always an exact type match as vzext operates on integer types.
25627 if (OpEltVT == InnerEltVT) {
25628 assert(OpVT == InnerVT && "Types must match for vzext!");
25629 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25632 // The only other way we can combine them is if only a single element of the
25633 // inner vzext is used in the input to the outer vzext.
25634 if (InnerEltVT.getSizeInBits() < InputBits)
25637 // In this case, the inner vzext is completely dead because we're going to
25638 // only look at bits inside of the low element. Just do the outer vzext on
25639 // a bitcast of the input to the inner.
25640 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25641 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25644 // Check if we can bypass extracting and re-inserting an element of an input
25645 // vector. Essentialy:
25646 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25647 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25648 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25649 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25650 SDValue ExtractedV = V.getOperand(0);
25651 SDValue OrigV = ExtractedV.getOperand(0);
25652 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25653 if (ExtractIdx->getZExtValue() == 0) {
25654 MVT OrigVT = OrigV.getSimpleValueType();
25655 // Extract a subvector if necessary...
25656 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25657 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25658 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25659 OrigVT.getVectorNumElements() / Ratio);
25660 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25661 DAG.getIntPtrConstant(0));
25663 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25664 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25671 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25672 DAGCombinerInfo &DCI) const {
25673 SelectionDAG &DAG = DCI.DAG;
25674 switch (N->getOpcode()) {
25676 case ISD::EXTRACT_VECTOR_ELT:
25677 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25680 case X86ISD::SHRUNKBLEND:
25681 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25682 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25683 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25684 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25685 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25686 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25689 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25690 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25691 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25692 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25693 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25694 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25695 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25696 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25697 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25699 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25701 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25702 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25703 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25704 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25705 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25706 case ISD::ANY_EXTEND:
25707 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25708 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25709 case ISD::SIGN_EXTEND_INREG:
25710 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25711 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25712 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25713 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25714 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25715 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25716 case X86ISD::SHUFP: // Handle all target specific shuffles
25717 case X86ISD::PALIGNR:
25718 case X86ISD::UNPCKH:
25719 case X86ISD::UNPCKL:
25720 case X86ISD::MOVHLPS:
25721 case X86ISD::MOVLHPS:
25722 case X86ISD::PSHUFB:
25723 case X86ISD::PSHUFD:
25724 case X86ISD::PSHUFHW:
25725 case X86ISD::PSHUFLW:
25726 case X86ISD::MOVSS:
25727 case X86ISD::MOVSD:
25728 case X86ISD::VPERMILPI:
25729 case X86ISD::VPERM2X128:
25730 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25731 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25732 case ISD::INTRINSIC_WO_CHAIN:
25733 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25734 case X86ISD::INSERTPS:
25735 return PerformINSERTPSCombine(N, DAG, Subtarget);
25736 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25742 /// isTypeDesirableForOp - Return true if the target has native support for
25743 /// the specified value type and it is 'desirable' to use the type for the
25744 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25745 /// instruction encodings are longer and some i16 instructions are slow.
25746 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25747 if (!isTypeLegal(VT))
25749 if (VT != MVT::i16)
25756 case ISD::SIGN_EXTEND:
25757 case ISD::ZERO_EXTEND:
25758 case ISD::ANY_EXTEND:
25771 /// IsDesirableToPromoteOp - This method query the target whether it is
25772 /// beneficial for dag combiner to promote the specified node. If true, it
25773 /// should return the desired promotion type by reference.
25774 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25775 EVT VT = Op.getValueType();
25776 if (VT != MVT::i16)
25779 bool Promote = false;
25780 bool Commute = false;
25781 switch (Op.getOpcode()) {
25784 LoadSDNode *LD = cast<LoadSDNode>(Op);
25785 // If the non-extending load has a single use and it's not live out, then it
25786 // might be folded.
25787 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25788 Op.hasOneUse()*/) {
25789 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25790 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25791 // The only case where we'd want to promote LOAD (rather then it being
25792 // promoted as an operand is when it's only use is liveout.
25793 if (UI->getOpcode() != ISD::CopyToReg)
25800 case ISD::SIGN_EXTEND:
25801 case ISD::ZERO_EXTEND:
25802 case ISD::ANY_EXTEND:
25807 SDValue N0 = Op.getOperand(0);
25808 // Look out for (store (shl (load), x)).
25809 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25822 SDValue N0 = Op.getOperand(0);
25823 SDValue N1 = Op.getOperand(1);
25824 if (!Commute && MayFoldLoad(N1))
25826 // Avoid disabling potential load folding opportunities.
25827 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25829 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25839 //===----------------------------------------------------------------------===//
25840 // X86 Inline Assembly Support
25841 //===----------------------------------------------------------------------===//
25844 // Helper to match a string separated by whitespace.
25845 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25846 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25848 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25849 StringRef piece(*args[i]);
25850 if (!s.startswith(piece)) // Check if the piece matches.
25853 s = s.substr(piece.size());
25854 StringRef::size_type pos = s.find_first_not_of(" \t");
25855 if (pos == 0) // We matched a prefix.
25863 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25866 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25868 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25869 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25870 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25871 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25873 if (AsmPieces.size() == 3)
25875 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25882 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25883 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25885 std::string AsmStr = IA->getAsmString();
25887 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25888 if (!Ty || Ty->getBitWidth() % 16 != 0)
25891 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25892 SmallVector<StringRef, 4> AsmPieces;
25893 SplitString(AsmStr, AsmPieces, ";\n");
25895 switch (AsmPieces.size()) {
25896 default: return false;
25898 // FIXME: this should verify that we are targeting a 486 or better. If not,
25899 // we will turn this bswap into something that will be lowered to logical
25900 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25901 // lower so don't worry about this.
25903 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25904 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25905 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25906 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25907 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25908 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25909 // No need to check constraints, nothing other than the equivalent of
25910 // "=r,0" would be valid here.
25911 return IntrinsicLowering::LowerToByteSwap(CI);
25914 // rorw $$8, ${0:w} --> llvm.bswap.i16
25915 if (CI->getType()->isIntegerTy(16) &&
25916 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25917 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25918 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25920 const std::string &ConstraintsStr = IA->getConstraintString();
25921 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25922 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25923 if (clobbersFlagRegisters(AsmPieces))
25924 return IntrinsicLowering::LowerToByteSwap(CI);
25928 if (CI->getType()->isIntegerTy(32) &&
25929 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25930 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25931 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25932 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25934 const std::string &ConstraintsStr = IA->getConstraintString();
25935 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25936 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25937 if (clobbersFlagRegisters(AsmPieces))
25938 return IntrinsicLowering::LowerToByteSwap(CI);
25941 if (CI->getType()->isIntegerTy(64)) {
25942 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25943 if (Constraints.size() >= 2 &&
25944 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25945 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25946 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25947 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25948 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25949 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25950 return IntrinsicLowering::LowerToByteSwap(CI);
25958 /// getConstraintType - Given a constraint letter, return the type of
25959 /// constraint it is for this target.
25960 X86TargetLowering::ConstraintType
25961 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25962 if (Constraint.size() == 1) {
25963 switch (Constraint[0]) {
25974 return C_RegisterClass;
25998 return TargetLowering::getConstraintType(Constraint);
26001 /// Examine constraint type and operand type and determine a weight value.
26002 /// This object must already have been set up with the operand type
26003 /// and the current alternative constraint selected.
26004 TargetLowering::ConstraintWeight
26005 X86TargetLowering::getSingleConstraintMatchWeight(
26006 AsmOperandInfo &info, const char *constraint) const {
26007 ConstraintWeight weight = CW_Invalid;
26008 Value *CallOperandVal = info.CallOperandVal;
26009 // If we don't have a value, we can't do a match,
26010 // but allow it at the lowest weight.
26011 if (!CallOperandVal)
26013 Type *type = CallOperandVal->getType();
26014 // Look at the constraint type.
26015 switch (*constraint) {
26017 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26028 if (CallOperandVal->getType()->isIntegerTy())
26029 weight = CW_SpecificReg;
26034 if (type->isFloatingPointTy())
26035 weight = CW_SpecificReg;
26038 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26039 weight = CW_SpecificReg;
26043 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26044 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26045 weight = CW_Register;
26048 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26049 if (C->getZExtValue() <= 31)
26050 weight = CW_Constant;
26054 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26055 if (C->getZExtValue() <= 63)
26056 weight = CW_Constant;
26060 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26061 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26062 weight = CW_Constant;
26066 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26067 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26068 weight = CW_Constant;
26072 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26073 if (C->getZExtValue() <= 3)
26074 weight = CW_Constant;
26078 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26079 if (C->getZExtValue() <= 0xff)
26080 weight = CW_Constant;
26085 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26086 weight = CW_Constant;
26090 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26091 if ((C->getSExtValue() >= -0x80000000LL) &&
26092 (C->getSExtValue() <= 0x7fffffffLL))
26093 weight = CW_Constant;
26097 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26098 if (C->getZExtValue() <= 0xffffffff)
26099 weight = CW_Constant;
26106 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26107 /// with another that has more specific requirements based on the type of the
26108 /// corresponding operand.
26109 const char *X86TargetLowering::
26110 LowerXConstraint(EVT ConstraintVT) const {
26111 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26112 // 'f' like normal targets.
26113 if (ConstraintVT.isFloatingPoint()) {
26114 if (Subtarget->hasSSE2())
26116 if (Subtarget->hasSSE1())
26120 return TargetLowering::LowerXConstraint(ConstraintVT);
26123 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26124 /// vector. If it is invalid, don't add anything to Ops.
26125 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26126 std::string &Constraint,
26127 std::vector<SDValue>&Ops,
26128 SelectionDAG &DAG) const {
26131 // Only support length 1 constraints for now.
26132 if (Constraint.length() > 1) return;
26134 char ConstraintLetter = Constraint[0];
26135 switch (ConstraintLetter) {
26138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26139 if (C->getZExtValue() <= 31) {
26140 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26147 if (C->getZExtValue() <= 63) {
26148 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26154 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26155 if (isInt<8>(C->getSExtValue())) {
26156 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26163 if (C->getZExtValue() <= 255) {
26164 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26170 // 32-bit signed value
26171 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26172 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26173 C->getSExtValue())) {
26174 // Widen to 64 bits here to get it sign extended.
26175 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26178 // FIXME gcc accepts some relocatable values here too, but only in certain
26179 // memory models; it's complicated.
26184 // 32-bit unsigned value
26185 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26186 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26187 C->getZExtValue())) {
26188 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26192 // FIXME gcc accepts some relocatable values here too, but only in certain
26193 // memory models; it's complicated.
26197 // Literal immediates are always ok.
26198 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26199 // Widen to 64 bits here to get it sign extended.
26200 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26204 // In any sort of PIC mode addresses need to be computed at runtime by
26205 // adding in a register or some sort of table lookup. These can't
26206 // be used as immediates.
26207 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26210 // If we are in non-pic codegen mode, we allow the address of a global (with
26211 // an optional displacement) to be used with 'i'.
26212 GlobalAddressSDNode *GA = nullptr;
26213 int64_t Offset = 0;
26215 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26217 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26218 Offset += GA->getOffset();
26220 } else if (Op.getOpcode() == ISD::ADD) {
26221 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26222 Offset += C->getZExtValue();
26223 Op = Op.getOperand(0);
26226 } else if (Op.getOpcode() == ISD::SUB) {
26227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26228 Offset += -C->getZExtValue();
26229 Op = Op.getOperand(0);
26234 // Otherwise, this isn't something we can handle, reject it.
26238 const GlobalValue *GV = GA->getGlobal();
26239 // If we require an extra load to get this address, as in PIC mode, we
26240 // can't accept it.
26241 if (isGlobalStubReference(
26242 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26245 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26246 GA->getValueType(0), Offset);
26251 if (Result.getNode()) {
26252 Ops.push_back(Result);
26255 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26258 std::pair<unsigned, const TargetRegisterClass*>
26259 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26261 // First, see if this is a constraint that directly corresponds to an LLVM
26263 if (Constraint.size() == 1) {
26264 // GCC Constraint Letters
26265 switch (Constraint[0]) {
26267 // TODO: Slight differences here in allocation order and leaving
26268 // RIP in the class. Do they matter any more here than they do
26269 // in the normal allocation?
26270 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26271 if (Subtarget->is64Bit()) {
26272 if (VT == MVT::i32 || VT == MVT::f32)
26273 return std::make_pair(0U, &X86::GR32RegClass);
26274 if (VT == MVT::i16)
26275 return std::make_pair(0U, &X86::GR16RegClass);
26276 if (VT == MVT::i8 || VT == MVT::i1)
26277 return std::make_pair(0U, &X86::GR8RegClass);
26278 if (VT == MVT::i64 || VT == MVT::f64)
26279 return std::make_pair(0U, &X86::GR64RegClass);
26282 // 32-bit fallthrough
26283 case 'Q': // Q_REGS
26284 if (VT == MVT::i32 || VT == MVT::f32)
26285 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26286 if (VT == MVT::i16)
26287 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26288 if (VT == MVT::i8 || VT == MVT::i1)
26289 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26290 if (VT == MVT::i64)
26291 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26293 case 'r': // GENERAL_REGS
26294 case 'l': // INDEX_REGS
26295 if (VT == MVT::i8 || VT == MVT::i1)
26296 return std::make_pair(0U, &X86::GR8RegClass);
26297 if (VT == MVT::i16)
26298 return std::make_pair(0U, &X86::GR16RegClass);
26299 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26300 return std::make_pair(0U, &X86::GR32RegClass);
26301 return std::make_pair(0U, &X86::GR64RegClass);
26302 case 'R': // LEGACY_REGS
26303 if (VT == MVT::i8 || VT == MVT::i1)
26304 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26305 if (VT == MVT::i16)
26306 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26307 if (VT == MVT::i32 || !Subtarget->is64Bit())
26308 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26309 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26310 case 'f': // FP Stack registers.
26311 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26312 // value to the correct fpstack register class.
26313 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26314 return std::make_pair(0U, &X86::RFP32RegClass);
26315 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26316 return std::make_pair(0U, &X86::RFP64RegClass);
26317 return std::make_pair(0U, &X86::RFP80RegClass);
26318 case 'y': // MMX_REGS if MMX allowed.
26319 if (!Subtarget->hasMMX()) break;
26320 return std::make_pair(0U, &X86::VR64RegClass);
26321 case 'Y': // SSE_REGS if SSE2 allowed
26322 if (!Subtarget->hasSSE2()) break;
26324 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26325 if (!Subtarget->hasSSE1()) break;
26327 switch (VT.SimpleTy) {
26329 // Scalar SSE types.
26332 return std::make_pair(0U, &X86::FR32RegClass);
26335 return std::make_pair(0U, &X86::FR64RegClass);
26343 return std::make_pair(0U, &X86::VR128RegClass);
26351 return std::make_pair(0U, &X86::VR256RegClass);
26356 return std::make_pair(0U, &X86::VR512RegClass);
26362 // Use the default implementation in TargetLowering to convert the register
26363 // constraint into a member of a register class.
26364 std::pair<unsigned, const TargetRegisterClass*> Res;
26365 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26367 // Not found as a standard register?
26369 // Map st(0) -> st(7) -> ST0
26370 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26371 tolower(Constraint[1]) == 's' &&
26372 tolower(Constraint[2]) == 't' &&
26373 Constraint[3] == '(' &&
26374 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26375 Constraint[5] == ')' &&
26376 Constraint[6] == '}') {
26378 Res.first = X86::FP0+Constraint[4]-'0';
26379 Res.second = &X86::RFP80RegClass;
26383 // GCC allows "st(0)" to be called just plain "st".
26384 if (StringRef("{st}").equals_lower(Constraint)) {
26385 Res.first = X86::FP0;
26386 Res.second = &X86::RFP80RegClass;
26391 if (StringRef("{flags}").equals_lower(Constraint)) {
26392 Res.first = X86::EFLAGS;
26393 Res.second = &X86::CCRRegClass;
26397 // 'A' means EAX + EDX.
26398 if (Constraint == "A") {
26399 Res.first = X86::EAX;
26400 Res.second = &X86::GR32_ADRegClass;
26406 // Otherwise, check to see if this is a register class of the wrong value
26407 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26408 // turn into {ax},{dx}.
26409 if (Res.second->hasType(VT))
26410 return Res; // Correct type already, nothing to do.
26412 // All of the single-register GCC register classes map their values onto
26413 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26414 // really want an 8-bit or 32-bit register, map to the appropriate register
26415 // class and return the appropriate register.
26416 if (Res.second == &X86::GR16RegClass) {
26417 if (VT == MVT::i8 || VT == MVT::i1) {
26418 unsigned DestReg = 0;
26419 switch (Res.first) {
26421 case X86::AX: DestReg = X86::AL; break;
26422 case X86::DX: DestReg = X86::DL; break;
26423 case X86::CX: DestReg = X86::CL; break;
26424 case X86::BX: DestReg = X86::BL; break;
26427 Res.first = DestReg;
26428 Res.second = &X86::GR8RegClass;
26430 } else if (VT == MVT::i32 || VT == MVT::f32) {
26431 unsigned DestReg = 0;
26432 switch (Res.first) {
26434 case X86::AX: DestReg = X86::EAX; break;
26435 case X86::DX: DestReg = X86::EDX; break;
26436 case X86::CX: DestReg = X86::ECX; break;
26437 case X86::BX: DestReg = X86::EBX; break;
26438 case X86::SI: DestReg = X86::ESI; break;
26439 case X86::DI: DestReg = X86::EDI; break;
26440 case X86::BP: DestReg = X86::EBP; break;
26441 case X86::SP: DestReg = X86::ESP; break;
26444 Res.first = DestReg;
26445 Res.second = &X86::GR32RegClass;
26447 } else if (VT == MVT::i64 || VT == MVT::f64) {
26448 unsigned DestReg = 0;
26449 switch (Res.first) {
26451 case X86::AX: DestReg = X86::RAX; break;
26452 case X86::DX: DestReg = X86::RDX; break;
26453 case X86::CX: DestReg = X86::RCX; break;
26454 case X86::BX: DestReg = X86::RBX; break;
26455 case X86::SI: DestReg = X86::RSI; break;
26456 case X86::DI: DestReg = X86::RDI; break;
26457 case X86::BP: DestReg = X86::RBP; break;
26458 case X86::SP: DestReg = X86::RSP; break;
26461 Res.first = DestReg;
26462 Res.second = &X86::GR64RegClass;
26465 } else if (Res.second == &X86::FR32RegClass ||
26466 Res.second == &X86::FR64RegClass ||
26467 Res.second == &X86::VR128RegClass ||
26468 Res.second == &X86::VR256RegClass ||
26469 Res.second == &X86::FR32XRegClass ||
26470 Res.second == &X86::FR64XRegClass ||
26471 Res.second == &X86::VR128XRegClass ||
26472 Res.second == &X86::VR256XRegClass ||
26473 Res.second == &X86::VR512RegClass) {
26474 // Handle references to XMM physical registers that got mapped into the
26475 // wrong class. This can happen with constraints like {xmm0} where the
26476 // target independent register mapper will just pick the first match it can
26477 // find, ignoring the required type.
26479 if (VT == MVT::f32 || VT == MVT::i32)
26480 Res.second = &X86::FR32RegClass;
26481 else if (VT == MVT::f64 || VT == MVT::i64)
26482 Res.second = &X86::FR64RegClass;
26483 else if (X86::VR128RegClass.hasType(VT))
26484 Res.second = &X86::VR128RegClass;
26485 else if (X86::VR256RegClass.hasType(VT))
26486 Res.second = &X86::VR256RegClass;
26487 else if (X86::VR512RegClass.hasType(VT))
26488 Res.second = &X86::VR512RegClass;
26494 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26496 // Scaling factors are not free at all.
26497 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26498 // will take 2 allocations in the out of order engine instead of 1
26499 // for plain addressing mode, i.e. inst (reg1).
26501 // vaddps (%rsi,%drx), %ymm0, %ymm1
26502 // Requires two allocations (one for the load, one for the computation)
26504 // vaddps (%rsi), %ymm0, %ymm1
26505 // Requires just 1 allocation, i.e., freeing allocations for other operations
26506 // and having less micro operations to execute.
26508 // For some X86 architectures, this is even worse because for instance for
26509 // stores, the complex addressing mode forces the instruction to use the
26510 // "load" ports instead of the dedicated "store" port.
26511 // E.g., on Haswell:
26512 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26513 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26514 if (isLegalAddressingMode(AM, Ty))
26515 // Scale represents reg2 * scale, thus account for 1
26516 // as soon as we use a second register.
26517 return AM.Scale != 0;
26521 bool X86TargetLowering::isTargetFTOL() const {
26522 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();