1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt();
172 X86ScalarSSEf32 = Subtarget->hasXMM();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
186 // For 64-bit since we have so many registers use the ILP scheduler, for
187 // 32-bit code use the register pressure specific scheduling.
188 if (Subtarget->is64Bit())
189 setSchedulingPreference(Sched::ILP);
191 setSchedulingPreference(Sched::RegPressure);
192 setStackPointerRegisterToSaveRestore(X86StackPtr);
194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
195 // Setup Windows compiler runtime calls.
196 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
198 setLibcallName(RTLIB::SREM_I64, "_allrem");
199 setLibcallName(RTLIB::UREM_I64, "_aullrem");
200 setLibcallName(RTLIB::MUL_I64, "_allmul");
201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
212 if (Subtarget->isTargetDarwin()) {
213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
214 setUseUnderscoreSetJmp(false);
215 setUseUnderscoreLongJmp(false);
216 } else if (Subtarget->isTargetMingw()) {
217 // MS runtime is weird: it exports _setjmp, but longjmp!
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(false);
221 setUseUnderscoreSetJmp(true);
222 setUseUnderscoreLongJmp(true);
225 // Set up the register classes.
226 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
227 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
228 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
229 if (Subtarget->is64Bit())
230 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
234 // We don't accept any truncstore of integer registers.
235 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
236 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
240 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
242 // SETOEQ and SETUNE require checking two conditions.
243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
259 } else if (!TM.Options.UseSoftFloat) {
260 // We have an algorithm for SSE2->double, and we turn this into a
261 // 64-bit FILD followed by conditional FADD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
263 // We have an algorithm for SSE2, and we turn this into a 64-bit
264 // FILD for other targets.
265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
273 if (!TM.Options.UseSoftFloat) {
274 // SSE has no i16 to fp conversion, only i32
275 if (X86ScalarSSEf32) {
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 // f32 and f64 cases are Legal, f80 case is not
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
289 // are Legal, f80 is custom lowered.
290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
298 if (X86ScalarSSEf32) {
299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
300 // f32 and f64 cases are Legal, f80 case is not
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
307 // Handle FP_TO_UINT by promoting the destination to a larger signed
309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
313 if (Subtarget->is64Bit()) {
314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
316 } else if (!TM.Options.UseSoftFloat) {
317 // Since AVX is a superset of SSE3, only check for SSE here.
318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
319 // Expand FP_TO_UINT into a select.
320 // FIXME: We would like to use a Custom expander here eventually to do
321 // the optimal thing for SSE vs. the default expansion in the legalizer.
322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
324 // With SSE3 we can use fisttpll to convert to a signed i64; without
325 // SSE, we're stuck with a fistpll.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0, e = 4; i != e; ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Expand);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i64 , Expand);
385 if (Subtarget->hasBMI()) {
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
388 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
389 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
390 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
395 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i8 , Expand);
396 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i16 , Expand);
397 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i64 , Expand);
399 if (Subtarget->hasLZCNT()) {
400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
402 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
403 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
404 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
405 if (Subtarget->is64Bit())
406 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
409 if (Subtarget->hasPOPCNT()) {
410 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
412 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
413 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
414 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
415 if (Subtarget->is64Bit())
416 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
419 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
420 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
422 // These should be promoted to a larger select which is supported.
423 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
424 // X86 wants to expand cmov itself.
425 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
426 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
427 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
428 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
429 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
430 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
431 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
434 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
435 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
436 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
437 if (Subtarget->is64Bit()) {
438 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
441 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
444 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
445 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
447 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
448 if (Subtarget->is64Bit())
449 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
450 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
451 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
452 if (Subtarget->is64Bit()) {
453 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
454 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
455 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
456 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
457 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
459 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
460 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
462 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
463 if (Subtarget->is64Bit()) {
464 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
466 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
469 if (Subtarget->hasXMM())
470 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
472 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
473 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
475 // On X86 and X86-64, atomic operations are lowered to locked instructions.
476 // Locked instructions, in turn, have implicit fence semantics (all memory
477 // operations are flushed before issuing the locked instruction, and they
478 // are not buffered), so we can fold away the common pattern of
479 // fence-atomic-fence.
480 setShouldFoldAtomicFences(true);
482 // Expand certain atomics
483 for (unsigned i = 0, e = 4; i != e; ++i) {
485 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
486 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
487 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
490 if (!Subtarget->is64Bit()) {
491 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
492 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
493 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
495 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
496 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
497 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
498 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
501 if (Subtarget->hasCmpxchg16b()) {
502 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
505 // FIXME - use subtarget debug flags
506 if (!Subtarget->isTargetDarwin() &&
507 !Subtarget->isTargetELF() &&
508 !Subtarget->isTargetCygMing()) {
509 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
512 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
513 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
514 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
515 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
516 if (Subtarget->is64Bit()) {
517 setExceptionPointerRegister(X86::RAX);
518 setExceptionSelectorRegister(X86::RDX);
520 setExceptionPointerRegister(X86::EAX);
521 setExceptionSelectorRegister(X86::EDX);
523 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
524 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
526 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
527 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
529 setOperationAction(ISD::TRAP, MVT::Other, Legal);
531 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
532 setOperationAction(ISD::VASTART , MVT::Other, Custom);
533 setOperationAction(ISD::VAEND , MVT::Other, Expand);
534 if (Subtarget->is64Bit()) {
535 setOperationAction(ISD::VAARG , MVT::Other, Custom);
536 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
538 setOperationAction(ISD::VAARG , MVT::Other, Expand);
539 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
542 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
543 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
545 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
546 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
547 MVT::i64 : MVT::i32, Custom);
548 else if (TM.Options.EnableSegmentedStacks)
549 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
550 MVT::i64 : MVT::i32, Custom);
552 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
553 MVT::i64 : MVT::i32, Expand);
555 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
556 // f32 and f64 use SSE.
557 // Set up the FP register classes.
558 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
559 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
561 // Use ANDPD to simulate FABS.
562 setOperationAction(ISD::FABS , MVT::f64, Custom);
563 setOperationAction(ISD::FABS , MVT::f32, Custom);
565 // Use XORP to simulate FNEG.
566 setOperationAction(ISD::FNEG , MVT::f64, Custom);
567 setOperationAction(ISD::FNEG , MVT::f32, Custom);
569 // Use ANDPD and ORPD to simulate FCOPYSIGN.
570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
573 // Lower this to FGETSIGNx86 plus an AND.
574 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
575 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
577 // We don't support sin/cos/fmod
578 setOperationAction(ISD::FSIN , MVT::f64, Expand);
579 setOperationAction(ISD::FCOS , MVT::f64, Expand);
580 setOperationAction(ISD::FSIN , MVT::f32, Expand);
581 setOperationAction(ISD::FCOS , MVT::f32, Expand);
583 // Expand FP immediates into loads from the stack, except for the special
585 addLegalFPImmediate(APFloat(+0.0)); // xorpd
586 addLegalFPImmediate(APFloat(+0.0f)); // xorps
587 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
588 // Use SSE for f32, x87 for f64.
589 // Set up the FP register classes.
590 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
593 // Use ANDPS to simulate FABS.
594 setOperationAction(ISD::FABS , MVT::f32, Custom);
596 // Use XORP to simulate FNEG.
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
601 // Use ANDPS and ORPS to simulate FCOPYSIGN.
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
605 // We don't support sin/cos/fmod
606 setOperationAction(ISD::FSIN , MVT::f32, Expand);
607 setOperationAction(ISD::FCOS , MVT::f32, Expand);
609 // Special cases we handle for FP constants.
610 addLegalFPImmediate(APFloat(+0.0f)); // xorps
611 addLegalFPImmediate(APFloat(+0.0)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
616 if (!TM.Options.UnsafeFPMath) {
617 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
618 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
620 } else if (!TM.Options.UseSoftFloat) {
621 // f32 and f64 in x87.
622 // Set up the FP register classes.
623 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
624 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
626 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
627 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
628 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
629 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
631 if (!TM.Options.UnsafeFPMath) {
632 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
633 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
635 addLegalFPImmediate(APFloat(+0.0)); // FLD0
636 addLegalFPImmediate(APFloat(+1.0)); // FLD1
637 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
638 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
639 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
640 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
641 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
642 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
645 // We don't support FMA.
646 setOperationAction(ISD::FMA, MVT::f64, Expand);
647 setOperationAction(ISD::FMA, MVT::f32, Expand);
649 // Long double always uses X87.
650 if (!TM.Options.UseSoftFloat) {
651 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
652 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
653 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
655 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
656 addLegalFPImmediate(TmpFlt); // FLD0
658 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
661 APFloat TmpFlt2(+1.0);
662 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
664 addLegalFPImmediate(TmpFlt2); // FLD1
665 TmpFlt2.changeSign();
666 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
669 if (!TM.Options.UnsafeFPMath) {
670 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
671 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
674 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
675 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
676 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
677 setOperationAction(ISD::FRINT, MVT::f80, Expand);
678 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
679 setOperationAction(ISD::FMA, MVT::f80, Expand);
682 // Always use a library call for pow.
683 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
684 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
685 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
687 setOperationAction(ISD::FLOG, MVT::f80, Expand);
688 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
689 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
690 setOperationAction(ISD::FEXP, MVT::f80, Expand);
691 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
693 // First set operation action for all vector types to either promote
694 // (for widening) or expand (for scalarization). Then we will selectively
695 // turn on ones that can be effectively codegen'd.
696 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
697 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
698 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
713 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
715 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
716 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
750 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
755 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
756 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
757 setTruncStoreAction((MVT::SimpleValueType)VT,
758 (MVT::SimpleValueType)InnerVT, Expand);
759 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
760 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
761 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
764 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
765 // with -msoft-float, disable use of MMX as well.
766 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
767 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
768 // No operations on x86mmx supported, everything uses intrinsics.
771 // MMX-sized vectors (other than x86mmx) are expected to be expanded
772 // into smaller operations.
773 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
774 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
775 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
776 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
777 setOperationAction(ISD::AND, MVT::v8i8, Expand);
778 setOperationAction(ISD::AND, MVT::v4i16, Expand);
779 setOperationAction(ISD::AND, MVT::v2i32, Expand);
780 setOperationAction(ISD::AND, MVT::v1i64, Expand);
781 setOperationAction(ISD::OR, MVT::v8i8, Expand);
782 setOperationAction(ISD::OR, MVT::v4i16, Expand);
783 setOperationAction(ISD::OR, MVT::v2i32, Expand);
784 setOperationAction(ISD::OR, MVT::v1i64, Expand);
785 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
786 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
787 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
788 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
789 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
790 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
791 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
792 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
793 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
794 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
795 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
796 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
797 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
798 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
799 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
800 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
801 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
803 if (!TM.Options.UseSoftFloat && Subtarget->hasXMM()) {
804 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
806 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
807 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
808 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
809 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
810 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
811 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
812 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
813 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
814 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
815 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
816 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
817 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
820 if (!TM.Options.UseSoftFloat && Subtarget->hasXMMInt()) {
821 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
823 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
824 // registers cannot be used even for integer operations.
825 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
826 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
827 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
828 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
830 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
831 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
832 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
833 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
834 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
835 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
836 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
837 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
838 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
839 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
840 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
841 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
842 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
843 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
844 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
845 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
847 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
848 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
849 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
850 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
852 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
853 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
854 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
858 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
859 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
860 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
861 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
862 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
866 EVT VT = (MVT::SimpleValueType)i;
867 // Do not attempt to custom lower non-power-of-2 vectors
868 if (!isPowerOf2_32(VT.getVectorNumElements()))
870 // Do not attempt to custom lower non-128-bit vectors
871 if (!VT.is128BitVector())
873 setOperationAction(ISD::BUILD_VECTOR,
874 VT.getSimpleVT().SimpleTy, Custom);
875 setOperationAction(ISD::VECTOR_SHUFFLE,
876 VT.getSimpleVT().SimpleTy, Custom);
877 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
878 VT.getSimpleVT().SimpleTy, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
882 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
884 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
888 if (Subtarget->is64Bit()) {
889 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
893 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
894 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
895 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
898 // Do not attempt to promote non-128-bit vectors
899 if (!VT.is128BitVector())
902 setOperationAction(ISD::AND, SVT, Promote);
903 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
904 setOperationAction(ISD::OR, SVT, Promote);
905 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
906 setOperationAction(ISD::XOR, SVT, Promote);
907 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
908 setOperationAction(ISD::LOAD, SVT, Promote);
909 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
910 setOperationAction(ISD::SELECT, SVT, Promote);
911 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
914 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
926 if (Subtarget->hasSSE41orAVX()) {
927 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
928 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
929 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
930 setOperationAction(ISD::FRINT, MVT::f32, Legal);
931 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
932 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
933 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
934 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
935 setOperationAction(ISD::FRINT, MVT::f64, Legal);
936 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
938 // FIXME: Do we need to handle scalar-to-vector here?
939 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
941 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
942 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
943 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
944 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
945 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
947 // i8 and i16 vectors are custom , because the source register and source
948 // source memory operand types are not the same width. f32 vectors are
949 // custom since the immediate controlling the insert encodes additional
951 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
952 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
953 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
954 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
957 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
958 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
959 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
961 // FIXME: these should be Legal but thats only for the case where
962 // the index is constant. For now custom expand to deal with that
963 if (Subtarget->is64Bit()) {
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
969 if (Subtarget->hasXMMInt()) {
970 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
971 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
973 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
974 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
976 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
977 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
979 if (Subtarget->hasAVX2()) {
980 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
981 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
983 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
984 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
986 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
988 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
989 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
991 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
992 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
994 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
998 if (Subtarget->hasSSE42orAVX())
999 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1001 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1002 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1003 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1004 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1005 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1006 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1007 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1009 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1010 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1011 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1013 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1014 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1015 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1016 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1017 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1018 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1020 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1021 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1022 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1023 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1024 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1025 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1027 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1028 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1029 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1031 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1032 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1033 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1034 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1035 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1036 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1038 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1039 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1041 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1042 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1044 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1045 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1047 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1048 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1049 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1050 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1052 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1053 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1054 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1056 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1057 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1058 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1059 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1061 if (Subtarget->hasAVX2()) {
1062 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1063 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1064 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1065 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1067 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1068 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1069 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1070 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1072 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1073 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1074 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1075 // Don't lower v32i8 because there is no 128-bit byte mul
1077 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1079 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1080 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1083 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1087 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1088 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1089 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1090 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1092 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1093 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1094 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1095 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1097 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1098 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1099 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1100 // Don't lower v32i8 because there is no 128-bit byte mul
1102 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1103 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1111 // Custom lower several nodes for 256-bit types.
1112 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1113 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1114 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1117 // Extract subvector is special because the value type
1118 // (result) is 128-bit but the source is 256-bit wide.
1119 if (VT.is128BitVector())
1120 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1122 // Do not attempt to custom lower other non-256-bit vectors
1123 if (!VT.is256BitVector())
1126 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1127 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1130 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1131 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1134 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1135 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1136 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1139 // Do not attempt to promote non-256-bit vectors
1140 if (!VT.is256BitVector())
1143 setOperationAction(ISD::AND, SVT, Promote);
1144 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1145 setOperationAction(ISD::OR, SVT, Promote);
1146 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1147 setOperationAction(ISD::XOR, SVT, Promote);
1148 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1149 setOperationAction(ISD::LOAD, SVT, Promote);
1150 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1151 setOperationAction(ISD::SELECT, SVT, Promote);
1152 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1156 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1157 // of this type with custom code.
1158 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1159 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1160 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1163 // We want to custom lower some of our intrinsics.
1164 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1167 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1168 // handle type legalization for these operations here.
1170 // FIXME: We really should do custom legalization for addition and
1171 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1172 // than generic legalization for 64-bit multiplication-with-overflow, though.
1173 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1174 // Add/Sub/Mul with overflow operations are custom lowered.
1176 setOperationAction(ISD::SADDO, VT, Custom);
1177 setOperationAction(ISD::UADDO, VT, Custom);
1178 setOperationAction(ISD::SSUBO, VT, Custom);
1179 setOperationAction(ISD::USUBO, VT, Custom);
1180 setOperationAction(ISD::SMULO, VT, Custom);
1181 setOperationAction(ISD::UMULO, VT, Custom);
1184 // There are no 8-bit 3-address imul/mul instructions
1185 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1186 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1188 if (!Subtarget->is64Bit()) {
1189 // These libcalls are not available in 32-bit.
1190 setLibcallName(RTLIB::SHL_I128, 0);
1191 setLibcallName(RTLIB::SRL_I128, 0);
1192 setLibcallName(RTLIB::SRA_I128, 0);
1195 // We have target-specific dag combine patterns for the following nodes:
1196 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1197 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1198 setTargetDAGCombine(ISD::BUILD_VECTOR);
1199 setTargetDAGCombine(ISD::VSELECT);
1200 setTargetDAGCombine(ISD::SELECT);
1201 setTargetDAGCombine(ISD::SHL);
1202 setTargetDAGCombine(ISD::SRA);
1203 setTargetDAGCombine(ISD::SRL);
1204 setTargetDAGCombine(ISD::OR);
1205 setTargetDAGCombine(ISD::AND);
1206 setTargetDAGCombine(ISD::ADD);
1207 setTargetDAGCombine(ISD::FADD);
1208 setTargetDAGCombine(ISD::FSUB);
1209 setTargetDAGCombine(ISD::SUB);
1210 setTargetDAGCombine(ISD::LOAD);
1211 setTargetDAGCombine(ISD::STORE);
1212 setTargetDAGCombine(ISD::ZERO_EXTEND);
1213 setTargetDAGCombine(ISD::SINT_TO_FP);
1214 if (Subtarget->is64Bit())
1215 setTargetDAGCombine(ISD::MUL);
1216 if (Subtarget->hasBMI())
1217 setTargetDAGCombine(ISD::XOR);
1219 computeRegisterProperties();
1221 // On Darwin, -Os means optimize for size without hurting performance,
1222 // do not reduce the limit.
1223 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1224 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1225 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1226 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1227 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1228 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1229 setPrefLoopAlignment(4); // 2^4 bytes.
1230 benefitFromCodePlacementOpt = true;
1232 setPrefFunctionAlignment(4); // 2^4 bytes.
1236 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1237 if (!VT.isVector()) return MVT::i8;
1238 return VT.changeVectorElementTypeToInteger();
1242 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1243 /// the desired ByVal argument alignment.
1244 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1247 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1248 if (VTy->getBitWidth() == 128)
1250 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1251 unsigned EltAlign = 0;
1252 getMaxByValAlign(ATy->getElementType(), EltAlign);
1253 if (EltAlign > MaxAlign)
1254 MaxAlign = EltAlign;
1255 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1256 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1257 unsigned EltAlign = 0;
1258 getMaxByValAlign(STy->getElementType(i), EltAlign);
1259 if (EltAlign > MaxAlign)
1260 MaxAlign = EltAlign;
1268 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1269 /// function arguments in the caller parameter area. For X86, aggregates
1270 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1271 /// are at 4-byte boundaries.
1272 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1273 if (Subtarget->is64Bit()) {
1274 // Max of 8 and alignment of type.
1275 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1282 if (Subtarget->hasXMM())
1283 getMaxByValAlign(Ty, Align);
1287 /// getOptimalMemOpType - Returns the target specific optimal type for load
1288 /// and store operations as a result of memset, memcpy, and memmove
1289 /// lowering. If DstAlign is zero that means it's safe to destination
1290 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1291 /// means there isn't a need to check it against alignment requirement,
1292 /// probably because the source does not need to be loaded. If
1293 /// 'IsZeroVal' is true, that means it's safe to return a
1294 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1295 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1296 /// constant so it does not need to be loaded.
1297 /// It returns EVT::Other if the type should be determined using generic
1298 /// target-independent logic.
1300 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1301 unsigned DstAlign, unsigned SrcAlign,
1304 MachineFunction &MF) const {
1305 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1306 // linux. This is because the stack realignment code can't handle certain
1307 // cases like PR2962. This should be removed when PR2962 is fixed.
1308 const Function *F = MF.getFunction();
1310 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1312 (Subtarget->isUnalignedMemAccessFast() ||
1313 ((DstAlign == 0 || DstAlign >= 16) &&
1314 (SrcAlign == 0 || SrcAlign >= 16))) &&
1315 Subtarget->getStackAlignment() >= 16) {
1316 if (Subtarget->hasAVX() &&
1317 Subtarget->getStackAlignment() >= 32)
1319 if (Subtarget->hasXMMInt())
1321 if (Subtarget->hasXMM())
1323 } else if (!MemcpyStrSrc && Size >= 8 &&
1324 !Subtarget->is64Bit() &&
1325 Subtarget->getStackAlignment() >= 8 &&
1326 Subtarget->hasXMMInt()) {
1327 // Do not use f64 to lower memcpy if source is string constant. It's
1328 // better to use i32 to avoid the loads.
1332 if (Subtarget->is64Bit() && Size >= 8)
1337 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1338 /// current function. The returned value is a member of the
1339 /// MachineJumpTableInfo::JTEntryKind enum.
1340 unsigned X86TargetLowering::getJumpTableEncoding() const {
1341 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1343 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1344 Subtarget->isPICStyleGOT())
1345 return MachineJumpTableInfo::EK_Custom32;
1347 // Otherwise, use the normal jump table encoding heuristics.
1348 return TargetLowering::getJumpTableEncoding();
1352 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1353 const MachineBasicBlock *MBB,
1354 unsigned uid,MCContext &Ctx) const{
1355 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1356 Subtarget->isPICStyleGOT());
1357 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1359 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1360 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1363 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1365 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1366 SelectionDAG &DAG) const {
1367 if (!Subtarget->is64Bit())
1368 // This doesn't have DebugLoc associated with it, but is not really the
1369 // same as a Register.
1370 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1374 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1375 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1377 const MCExpr *X86TargetLowering::
1378 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1379 MCContext &Ctx) const {
1380 // X86-64 uses RIP relative addressing based on the jump table label.
1381 if (Subtarget->isPICStyleRIPRel())
1382 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1384 // Otherwise, the reference is relative to the PIC base.
1385 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1388 // FIXME: Why this routine is here? Move to RegInfo!
1389 std::pair<const TargetRegisterClass*, uint8_t>
1390 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1391 const TargetRegisterClass *RRC = 0;
1393 switch (VT.getSimpleVT().SimpleTy) {
1395 return TargetLowering::findRepresentativeClass(VT);
1396 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1397 RRC = (Subtarget->is64Bit()
1398 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1401 RRC = X86::VR64RegisterClass;
1403 case MVT::f32: case MVT::f64:
1404 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1405 case MVT::v4f32: case MVT::v2f64:
1406 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1408 RRC = X86::VR128RegisterClass;
1411 return std::make_pair(RRC, Cost);
1414 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1415 unsigned &Offset) const {
1416 if (!Subtarget->isTargetLinux())
1419 if (Subtarget->is64Bit()) {
1420 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1422 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1435 //===----------------------------------------------------------------------===//
1436 // Return Value Calling Convention Implementation
1437 //===----------------------------------------------------------------------===//
1439 #include "X86GenCallingConv.inc"
1442 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1443 MachineFunction &MF, bool isVarArg,
1444 const SmallVectorImpl<ISD::OutputArg> &Outs,
1445 LLVMContext &Context) const {
1446 SmallVector<CCValAssign, 16> RVLocs;
1447 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1449 return CCInfo.CheckReturn(Outs, RetCC_X86);
1453 X86TargetLowering::LowerReturn(SDValue Chain,
1454 CallingConv::ID CallConv, bool isVarArg,
1455 const SmallVectorImpl<ISD::OutputArg> &Outs,
1456 const SmallVectorImpl<SDValue> &OutVals,
1457 DebugLoc dl, SelectionDAG &DAG) const {
1458 MachineFunction &MF = DAG.getMachineFunction();
1459 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1461 SmallVector<CCValAssign, 16> RVLocs;
1462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1463 RVLocs, *DAG.getContext());
1464 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1466 // Add the regs to the liveout set for the function.
1467 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1468 for (unsigned i = 0; i != RVLocs.size(); ++i)
1469 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1470 MRI.addLiveOut(RVLocs[i].getLocReg());
1474 SmallVector<SDValue, 6> RetOps;
1475 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1476 // Operand #1 = Bytes To Pop
1477 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1480 // Copy the result values into the output registers.
1481 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1482 CCValAssign &VA = RVLocs[i];
1483 assert(VA.isRegLoc() && "Can only return in registers!");
1484 SDValue ValToCopy = OutVals[i];
1485 EVT ValVT = ValToCopy.getValueType();
1487 // If this is x86-64, and we disabled SSE, we can't return FP values,
1488 // or SSE or MMX vectors.
1489 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1490 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1491 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1492 report_fatal_error("SSE register return with SSE disabled");
1494 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1495 // llvm-gcc has never done it right and no one has noticed, so this
1496 // should be OK for now.
1497 if (ValVT == MVT::f64 &&
1498 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1499 report_fatal_error("SSE2 register return with SSE2 disabled");
1501 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1502 // the RET instruction and handled by the FP Stackifier.
1503 if (VA.getLocReg() == X86::ST0 ||
1504 VA.getLocReg() == X86::ST1) {
1505 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1506 // change the value to the FP stack register class.
1507 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1508 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1509 RetOps.push_back(ValToCopy);
1510 // Don't emit a copytoreg.
1514 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1515 // which is returned in RAX / RDX.
1516 if (Subtarget->is64Bit()) {
1517 if (ValVT == MVT::x86mmx) {
1518 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1519 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1520 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1522 // If we don't have SSE2 available, convert to v4f32 so the generated
1523 // register is legal.
1524 if (!Subtarget->hasXMMInt())
1525 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1530 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1531 Flag = Chain.getValue(1);
1534 // The x86-64 ABI for returning structs by value requires that we copy
1535 // the sret argument into %rax for the return. We saved the argument into
1536 // a virtual register in the entry block, so now we copy the value out
1538 if (Subtarget->is64Bit() &&
1539 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1540 MachineFunction &MF = DAG.getMachineFunction();
1541 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1542 unsigned Reg = FuncInfo->getSRetReturnReg();
1544 "SRetReturnReg should have been set in LowerFormalArguments().");
1545 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1547 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1548 Flag = Chain.getValue(1);
1550 // RAX now acts like a return value.
1551 MRI.addLiveOut(X86::RAX);
1554 RetOps[0] = Chain; // Update chain.
1556 // Add the flag if we have it.
1558 RetOps.push_back(Flag);
1560 return DAG.getNode(X86ISD::RET_FLAG, dl,
1561 MVT::Other, &RetOps[0], RetOps.size());
1564 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1565 if (N->getNumValues() != 1)
1567 if (!N->hasNUsesOfValue(1, 0))
1570 SDNode *Copy = *N->use_begin();
1571 if (Copy->getOpcode() != ISD::CopyToReg &&
1572 Copy->getOpcode() != ISD::FP_EXTEND)
1575 bool HasRet = false;
1576 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1578 if (UI->getOpcode() != X86ISD::RET_FLAG)
1587 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1588 ISD::NodeType ExtendKind) const {
1590 // TODO: Is this also valid on 32-bit?
1591 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1592 ReturnMVT = MVT::i8;
1594 ReturnMVT = MVT::i32;
1596 EVT MinVT = getRegisterType(Context, ReturnMVT);
1597 return VT.bitsLT(MinVT) ? MinVT : VT;
1600 /// LowerCallResult - Lower the result values of a call into the
1601 /// appropriate copies out of appropriate physical registers.
1604 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1605 CallingConv::ID CallConv, bool isVarArg,
1606 const SmallVectorImpl<ISD::InputArg> &Ins,
1607 DebugLoc dl, SelectionDAG &DAG,
1608 SmallVectorImpl<SDValue> &InVals) const {
1610 // Assign locations to each value returned by this call.
1611 SmallVector<CCValAssign, 16> RVLocs;
1612 bool Is64Bit = Subtarget->is64Bit();
1613 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1614 getTargetMachine(), RVLocs, *DAG.getContext());
1615 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1617 // Copy all of the result registers out of their specified physreg.
1618 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1619 CCValAssign &VA = RVLocs[i];
1620 EVT CopyVT = VA.getValVT();
1622 // If this is x86-64, and we disabled SSE, we can't return FP values
1623 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1624 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1625 report_fatal_error("SSE register return with SSE disabled");
1630 // If this is a call to a function that returns an fp value on the floating
1631 // point stack, we must guarantee the the value is popped from the stack, so
1632 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1633 // if the return value is not used. We use the FpPOP_RETVAL instruction
1635 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1636 // If we prefer to use the value in xmm registers, copy it out as f80 and
1637 // use a truncate to move it from fp stack reg to xmm reg.
1638 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1639 SDValue Ops[] = { Chain, InFlag };
1640 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1641 MVT::Other, MVT::Glue, Ops, 2), 1);
1642 Val = Chain.getValue(0);
1644 // Round the f80 to the right size, which also moves it to the appropriate
1646 if (CopyVT != VA.getValVT())
1647 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1648 // This truncation won't change the value.
1649 DAG.getIntPtrConstant(1));
1651 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1652 CopyVT, InFlag).getValue(1);
1653 Val = Chain.getValue(0);
1655 InFlag = Chain.getValue(2);
1656 InVals.push_back(Val);
1663 //===----------------------------------------------------------------------===//
1664 // C & StdCall & Fast Calling Convention implementation
1665 //===----------------------------------------------------------------------===//
1666 // StdCall calling convention seems to be standard for many Windows' API
1667 // routines and around. It differs from C calling convention just a little:
1668 // callee should clean up the stack, not caller. Symbols should be also
1669 // decorated in some fancy way :) It doesn't support any vector arguments.
1670 // For info on fast calling convention see Fast Calling Convention (tail call)
1671 // implementation LowerX86_32FastCCCallTo.
1673 /// CallIsStructReturn - Determines whether a call uses struct return
1675 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1679 return Outs[0].Flags.isSRet();
1682 /// ArgsAreStructReturn - Determines whether a function uses struct
1683 /// return semantics.
1685 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1689 return Ins[0].Flags.isSRet();
1692 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1693 /// by "Src" to address "Dst" with size and alignment information specified by
1694 /// the specific parameter attribute. The copy will be passed as a byval
1695 /// function parameter.
1697 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1698 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1700 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1702 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1703 /*isVolatile*/false, /*AlwaysInline=*/true,
1704 MachinePointerInfo(), MachinePointerInfo());
1707 /// IsTailCallConvention - Return true if the calling convention is one that
1708 /// supports tail call optimization.
1709 static bool IsTailCallConvention(CallingConv::ID CC) {
1710 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1713 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1714 if (!CI->isTailCall())
1718 CallingConv::ID CalleeCC = CS.getCallingConv();
1719 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1725 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1726 /// a tailcall target by changing its ABI.
1727 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1728 bool GuaranteedTailCallOpt) {
1729 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1733 X86TargetLowering::LowerMemArgument(SDValue Chain,
1734 CallingConv::ID CallConv,
1735 const SmallVectorImpl<ISD::InputArg> &Ins,
1736 DebugLoc dl, SelectionDAG &DAG,
1737 const CCValAssign &VA,
1738 MachineFrameInfo *MFI,
1740 // Create the nodes corresponding to a load from this parameter slot.
1741 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1742 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1743 getTargetMachine().Options.GuaranteedTailCallOpt);
1744 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1747 // If value is passed by pointer we have address passed instead of the value
1749 if (VA.getLocInfo() == CCValAssign::Indirect)
1750 ValVT = VA.getLocVT();
1752 ValVT = VA.getValVT();
1754 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1755 // changed with more analysis.
1756 // In case of tail call optimization mark all arguments mutable. Since they
1757 // could be overwritten by lowering of arguments in case of a tail call.
1758 if (Flags.isByVal()) {
1759 unsigned Bytes = Flags.getByValSize();
1760 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1761 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1762 return DAG.getFrameIndex(FI, getPointerTy());
1764 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1765 VA.getLocMemOffset(), isImmutable);
1766 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1767 return DAG.getLoad(ValVT, dl, Chain, FIN,
1768 MachinePointerInfo::getFixedStack(FI),
1769 false, false, false, 0);
1774 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1775 CallingConv::ID CallConv,
1777 const SmallVectorImpl<ISD::InputArg> &Ins,
1780 SmallVectorImpl<SDValue> &InVals)
1782 MachineFunction &MF = DAG.getMachineFunction();
1783 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1785 const Function* Fn = MF.getFunction();
1786 if (Fn->hasExternalLinkage() &&
1787 Subtarget->isTargetCygMing() &&
1788 Fn->getName() == "main")
1789 FuncInfo->setForceFramePointer(true);
1791 MachineFrameInfo *MFI = MF.getFrameInfo();
1792 bool Is64Bit = Subtarget->is64Bit();
1793 bool IsWin64 = Subtarget->isTargetWin64();
1795 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1796 "Var args not supported with calling convention fastcc or ghc");
1798 // Assign locations to all of the incoming arguments.
1799 SmallVector<CCValAssign, 16> ArgLocs;
1800 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1801 ArgLocs, *DAG.getContext());
1803 // Allocate shadow area for Win64
1805 CCInfo.AllocateStack(32, 8);
1808 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1810 unsigned LastVal = ~0U;
1812 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1813 CCValAssign &VA = ArgLocs[i];
1814 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1816 assert(VA.getValNo() != LastVal &&
1817 "Don't support value assigned to multiple locs yet");
1819 LastVal = VA.getValNo();
1821 if (VA.isRegLoc()) {
1822 EVT RegVT = VA.getLocVT();
1823 TargetRegisterClass *RC = NULL;
1824 if (RegVT == MVT::i32)
1825 RC = X86::GR32RegisterClass;
1826 else if (Is64Bit && RegVT == MVT::i64)
1827 RC = X86::GR64RegisterClass;
1828 else if (RegVT == MVT::f32)
1829 RC = X86::FR32RegisterClass;
1830 else if (RegVT == MVT::f64)
1831 RC = X86::FR64RegisterClass;
1832 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1833 RC = X86::VR256RegisterClass;
1834 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1835 RC = X86::VR128RegisterClass;
1836 else if (RegVT == MVT::x86mmx)
1837 RC = X86::VR64RegisterClass;
1839 llvm_unreachable("Unknown argument type!");
1841 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1842 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1844 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1845 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1847 if (VA.getLocInfo() == CCValAssign::SExt)
1848 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1849 DAG.getValueType(VA.getValVT()));
1850 else if (VA.getLocInfo() == CCValAssign::ZExt)
1851 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1852 DAG.getValueType(VA.getValVT()));
1853 else if (VA.getLocInfo() == CCValAssign::BCvt)
1854 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1856 if (VA.isExtInLoc()) {
1857 // Handle MMX values passed in XMM regs.
1858 if (RegVT.isVector()) {
1859 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1862 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1865 assert(VA.isMemLoc());
1866 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1869 // If value is passed via pointer - do a load.
1870 if (VA.getLocInfo() == CCValAssign::Indirect)
1871 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1872 MachinePointerInfo(), false, false, false, 0);
1874 InVals.push_back(ArgValue);
1877 // The x86-64 ABI for returning structs by value requires that we copy
1878 // the sret argument into %rax for the return. Save the argument into
1879 // a virtual register so that we can access it from the return points.
1880 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1881 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1882 unsigned Reg = FuncInfo->getSRetReturnReg();
1884 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1885 FuncInfo->setSRetReturnReg(Reg);
1887 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1888 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1891 unsigned StackSize = CCInfo.getNextStackOffset();
1892 // Align stack specially for tail calls.
1893 if (FuncIsMadeTailCallSafe(CallConv,
1894 MF.getTarget().Options.GuaranteedTailCallOpt))
1895 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1897 // If the function takes variable number of arguments, make a frame index for
1898 // the start of the first vararg value... for expansion of llvm.va_start.
1900 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1901 CallConv != CallingConv::X86_ThisCall)) {
1902 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1905 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1907 // FIXME: We should really autogenerate these arrays
1908 static const unsigned GPR64ArgRegsWin64[] = {
1909 X86::RCX, X86::RDX, X86::R8, X86::R9
1911 static const unsigned GPR64ArgRegs64Bit[] = {
1912 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1914 static const unsigned XMMArgRegs64Bit[] = {
1915 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1916 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1918 const unsigned *GPR64ArgRegs;
1919 unsigned NumXMMRegs = 0;
1922 // The XMM registers which might contain var arg parameters are shadowed
1923 // in their paired GPR. So we only need to save the GPR to their home
1925 TotalNumIntRegs = 4;
1926 GPR64ArgRegs = GPR64ArgRegsWin64;
1928 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1929 GPR64ArgRegs = GPR64ArgRegs64Bit;
1931 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1933 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1936 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1937 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1938 "SSE register cannot be used when SSE is disabled!");
1939 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1940 NoImplicitFloatOps) &&
1941 "SSE register cannot be used when SSE is disabled!");
1942 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1943 !Subtarget->hasXMM())
1944 // Kernel mode asks for SSE to be disabled, so don't push them
1946 TotalNumXMMRegs = 0;
1949 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1950 // Get to the caller-allocated home save location. Add 8 to account
1951 // for the return address.
1952 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1953 FuncInfo->setRegSaveFrameIndex(
1954 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1955 // Fixup to set vararg frame on shadow area (4 x i64).
1957 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1959 // For X86-64, if there are vararg parameters that are passed via
1960 // registers, then we must store them to their spots on the stack so they
1961 // may be loaded by deferencing the result of va_next.
1962 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1963 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1964 FuncInfo->setRegSaveFrameIndex(
1965 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1969 // Store the integer parameter registers.
1970 SmallVector<SDValue, 8> MemOps;
1971 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1973 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1974 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1975 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1976 DAG.getIntPtrConstant(Offset));
1977 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1978 X86::GR64RegisterClass);
1979 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1981 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1982 MachinePointerInfo::getFixedStack(
1983 FuncInfo->getRegSaveFrameIndex(), Offset),
1985 MemOps.push_back(Store);
1989 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1990 // Now store the XMM (fp + vector) parameter registers.
1991 SmallVector<SDValue, 11> SaveXMMOps;
1992 SaveXMMOps.push_back(Chain);
1994 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1995 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1996 SaveXMMOps.push_back(ALVal);
1998 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1999 FuncInfo->getRegSaveFrameIndex()));
2000 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2001 FuncInfo->getVarArgsFPOffset()));
2003 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2004 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2005 X86::VR128RegisterClass);
2006 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2007 SaveXMMOps.push_back(Val);
2009 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2011 &SaveXMMOps[0], SaveXMMOps.size()));
2014 if (!MemOps.empty())
2015 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2016 &MemOps[0], MemOps.size());
2020 // Some CCs need callee pop.
2021 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2022 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2023 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2025 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2026 // If this is an sret function, the return should pop the hidden pointer.
2027 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
2028 FuncInfo->setBytesToPopOnReturn(4);
2032 // RegSaveFrameIndex is X86-64 only.
2033 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2034 if (CallConv == CallingConv::X86_FastCall ||
2035 CallConv == CallingConv::X86_ThisCall)
2036 // fastcc functions can't have varargs.
2037 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2040 FuncInfo->setArgumentStackSize(StackSize);
2046 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2047 SDValue StackPtr, SDValue Arg,
2048 DebugLoc dl, SelectionDAG &DAG,
2049 const CCValAssign &VA,
2050 ISD::ArgFlagsTy Flags) const {
2051 unsigned LocMemOffset = VA.getLocMemOffset();
2052 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2053 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2054 if (Flags.isByVal())
2055 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2057 return DAG.getStore(Chain, dl, Arg, PtrOff,
2058 MachinePointerInfo::getStack(LocMemOffset),
2062 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2063 /// optimization is performed and it is required.
2065 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2066 SDValue &OutRetAddr, SDValue Chain,
2067 bool IsTailCall, bool Is64Bit,
2068 int FPDiff, DebugLoc dl) const {
2069 // Adjust the Return address stack slot.
2070 EVT VT = getPointerTy();
2071 OutRetAddr = getReturnAddressFrameIndex(DAG);
2073 // Load the "old" Return address.
2074 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2075 false, false, false, 0);
2076 return SDValue(OutRetAddr.getNode(), 1);
2079 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2080 /// optimization is performed and it is required (FPDiff!=0).
2082 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2083 SDValue Chain, SDValue RetAddrFrIdx,
2084 bool Is64Bit, int FPDiff, DebugLoc dl) {
2085 // Store the return address to the appropriate stack slot.
2086 if (!FPDiff) return Chain;
2087 // Calculate the new stack slot for the return address.
2088 int SlotSize = Is64Bit ? 8 : 4;
2089 int NewReturnAddrFI =
2090 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2091 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2092 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2093 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2094 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2100 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2101 CallingConv::ID CallConv, bool isVarArg,
2103 const SmallVectorImpl<ISD::OutputArg> &Outs,
2104 const SmallVectorImpl<SDValue> &OutVals,
2105 const SmallVectorImpl<ISD::InputArg> &Ins,
2106 DebugLoc dl, SelectionDAG &DAG,
2107 SmallVectorImpl<SDValue> &InVals) const {
2108 MachineFunction &MF = DAG.getMachineFunction();
2109 bool Is64Bit = Subtarget->is64Bit();
2110 bool IsWin64 = Subtarget->isTargetWin64();
2111 bool IsStructRet = CallIsStructReturn(Outs);
2112 bool IsSibcall = false;
2115 // Check if it's really possible to do a tail call.
2116 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2117 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2118 Outs, OutVals, Ins, DAG);
2120 // Sibcalls are automatically detected tailcalls which do not require
2122 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2129 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2130 "Var args not supported with calling convention fastcc or ghc");
2132 // Analyze operands of the call, assigning locations to each operand.
2133 SmallVector<CCValAssign, 16> ArgLocs;
2134 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2135 ArgLocs, *DAG.getContext());
2137 // Allocate shadow area for Win64
2139 CCInfo.AllocateStack(32, 8);
2142 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2144 // Get a count of how many bytes are to be pushed on the stack.
2145 unsigned NumBytes = CCInfo.getNextStackOffset();
2147 // This is a sibcall. The memory operands are available in caller's
2148 // own caller's stack.
2150 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2151 IsTailCallConvention(CallConv))
2152 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2155 if (isTailCall && !IsSibcall) {
2156 // Lower arguments at fp - stackoffset + fpdiff.
2157 unsigned NumBytesCallerPushed =
2158 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2159 FPDiff = NumBytesCallerPushed - NumBytes;
2161 // Set the delta of movement of the returnaddr stackslot.
2162 // But only set if delta is greater than previous delta.
2163 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2164 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2168 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2170 SDValue RetAddrFrIdx;
2171 // Load return address for tail calls.
2172 if (isTailCall && FPDiff)
2173 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2174 Is64Bit, FPDiff, dl);
2176 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2177 SmallVector<SDValue, 8> MemOpChains;
2180 // Walk the register/memloc assignments, inserting copies/loads. In the case
2181 // of tail call optimization arguments are handle later.
2182 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2183 CCValAssign &VA = ArgLocs[i];
2184 EVT RegVT = VA.getLocVT();
2185 SDValue Arg = OutVals[i];
2186 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2187 bool isByVal = Flags.isByVal();
2189 // Promote the value if needed.
2190 switch (VA.getLocInfo()) {
2191 default: llvm_unreachable("Unknown loc info!");
2192 case CCValAssign::Full: break;
2193 case CCValAssign::SExt:
2194 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2196 case CCValAssign::ZExt:
2197 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2199 case CCValAssign::AExt:
2200 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2201 // Special case: passing MMX values in XMM registers.
2202 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2203 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2204 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2206 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2208 case CCValAssign::BCvt:
2209 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2211 case CCValAssign::Indirect: {
2212 // Store the argument.
2213 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2214 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2215 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2216 MachinePointerInfo::getFixedStack(FI),
2223 if (VA.isRegLoc()) {
2224 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2225 if (isVarArg && IsWin64) {
2226 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2227 // shadow reg if callee is a varargs function.
2228 unsigned ShadowReg = 0;
2229 switch (VA.getLocReg()) {
2230 case X86::XMM0: ShadowReg = X86::RCX; break;
2231 case X86::XMM1: ShadowReg = X86::RDX; break;
2232 case X86::XMM2: ShadowReg = X86::R8; break;
2233 case X86::XMM3: ShadowReg = X86::R9; break;
2236 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2238 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2239 assert(VA.isMemLoc());
2240 if (StackPtr.getNode() == 0)
2241 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2242 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2243 dl, DAG, VA, Flags));
2247 if (!MemOpChains.empty())
2248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2249 &MemOpChains[0], MemOpChains.size());
2251 // Build a sequence of copy-to-reg nodes chained together with token chain
2252 // and flag operands which copy the outgoing args into registers.
2254 // Tail call byval lowering might overwrite argument registers so in case of
2255 // tail call optimization the copies to registers are lowered later.
2257 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2258 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2259 RegsToPass[i].second, InFlag);
2260 InFlag = Chain.getValue(1);
2263 if (Subtarget->isPICStyleGOT()) {
2264 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2267 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2268 DAG.getNode(X86ISD::GlobalBaseReg,
2269 DebugLoc(), getPointerTy()),
2271 InFlag = Chain.getValue(1);
2273 // If we are tail calling and generating PIC/GOT style code load the
2274 // address of the callee into ECX. The value in ecx is used as target of
2275 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2276 // for tail calls on PIC/GOT architectures. Normally we would just put the
2277 // address of GOT into ebx and then call target@PLT. But for tail calls
2278 // ebx would be restored (since ebx is callee saved) before jumping to the
2281 // Note: The actual moving to ECX is done further down.
2282 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2283 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2284 !G->getGlobal()->hasProtectedVisibility())
2285 Callee = LowerGlobalAddress(Callee, DAG);
2286 else if (isa<ExternalSymbolSDNode>(Callee))
2287 Callee = LowerExternalSymbol(Callee, DAG);
2291 if (Is64Bit && isVarArg && !IsWin64) {
2292 // From AMD64 ABI document:
2293 // For calls that may call functions that use varargs or stdargs
2294 // (prototype-less calls or calls to functions containing ellipsis (...) in
2295 // the declaration) %al is used as hidden argument to specify the number
2296 // of SSE registers used. The contents of %al do not need to match exactly
2297 // the number of registers, but must be an ubound on the number of SSE
2298 // registers used and is in the range 0 - 8 inclusive.
2300 // Count the number of XMM registers allocated.
2301 static const unsigned XMMArgRegs[] = {
2302 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2303 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2305 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2306 assert((Subtarget->hasXMM() || !NumXMMRegs)
2307 && "SSE registers cannot be used when SSE is disabled");
2309 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2310 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2311 InFlag = Chain.getValue(1);
2315 // For tail calls lower the arguments to the 'real' stack slot.
2317 // Force all the incoming stack arguments to be loaded from the stack
2318 // before any new outgoing arguments are stored to the stack, because the
2319 // outgoing stack slots may alias the incoming argument stack slots, and
2320 // the alias isn't otherwise explicit. This is slightly more conservative
2321 // than necessary, because it means that each store effectively depends
2322 // on every argument instead of just those arguments it would clobber.
2323 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2325 SmallVector<SDValue, 8> MemOpChains2;
2328 // Do not flag preceding copytoreg stuff together with the following stuff.
2330 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2331 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2332 CCValAssign &VA = ArgLocs[i];
2335 assert(VA.isMemLoc());
2336 SDValue Arg = OutVals[i];
2337 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2338 // Create frame index.
2339 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2340 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2341 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2342 FIN = DAG.getFrameIndex(FI, getPointerTy());
2344 if (Flags.isByVal()) {
2345 // Copy relative to framepointer.
2346 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2347 if (StackPtr.getNode() == 0)
2348 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2350 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2352 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2356 // Store relative to framepointer.
2357 MemOpChains2.push_back(
2358 DAG.getStore(ArgChain, dl, Arg, FIN,
2359 MachinePointerInfo::getFixedStack(FI),
2365 if (!MemOpChains2.empty())
2366 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2367 &MemOpChains2[0], MemOpChains2.size());
2369 // Copy arguments to their registers.
2370 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2371 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2372 RegsToPass[i].second, InFlag);
2373 InFlag = Chain.getValue(1);
2377 // Store the return address to the appropriate stack slot.
2378 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2382 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2383 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2384 // In the 64-bit large code model, we have to make all calls
2385 // through a register, since the call instruction's 32-bit
2386 // pc-relative offset may not be large enough to hold the whole
2388 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2389 // If the callee is a GlobalAddress node (quite common, every direct call
2390 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2393 // We should use extra load for direct calls to dllimported functions in
2395 const GlobalValue *GV = G->getGlobal();
2396 if (!GV->hasDLLImportLinkage()) {
2397 unsigned char OpFlags = 0;
2398 bool ExtraLoad = false;
2399 unsigned WrapperKind = ISD::DELETED_NODE;
2401 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2402 // external symbols most go through the PLT in PIC mode. If the symbol
2403 // has hidden or protected visibility, or if it is static or local, then
2404 // we don't need to use the PLT - we can directly call it.
2405 if (Subtarget->isTargetELF() &&
2406 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2407 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2408 OpFlags = X86II::MO_PLT;
2409 } else if (Subtarget->isPICStyleStubAny() &&
2410 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2411 (!Subtarget->getTargetTriple().isMacOSX() ||
2412 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2413 // PC-relative references to external symbols should go through $stub,
2414 // unless we're building with the leopard linker or later, which
2415 // automatically synthesizes these stubs.
2416 OpFlags = X86II::MO_DARWIN_STUB;
2417 } else if (Subtarget->isPICStyleRIPRel() &&
2418 isa<Function>(GV) &&
2419 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2420 // If the function is marked as non-lazy, generate an indirect call
2421 // which loads from the GOT directly. This avoids runtime overhead
2422 // at the cost of eager binding (and one extra byte of encoding).
2423 OpFlags = X86II::MO_GOTPCREL;
2424 WrapperKind = X86ISD::WrapperRIP;
2428 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2429 G->getOffset(), OpFlags);
2431 // Add a wrapper if needed.
2432 if (WrapperKind != ISD::DELETED_NODE)
2433 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2434 // Add extra indirection if needed.
2436 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2437 MachinePointerInfo::getGOT(),
2438 false, false, false, 0);
2440 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2441 unsigned char OpFlags = 0;
2443 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2444 // external symbols should go through the PLT.
2445 if (Subtarget->isTargetELF() &&
2446 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2447 OpFlags = X86II::MO_PLT;
2448 } else if (Subtarget->isPICStyleStubAny() &&
2449 (!Subtarget->getTargetTriple().isMacOSX() ||
2450 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2451 // PC-relative references to external symbols should go through $stub,
2452 // unless we're building with the leopard linker or later, which
2453 // automatically synthesizes these stubs.
2454 OpFlags = X86II::MO_DARWIN_STUB;
2457 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2461 // Returns a chain & a flag for retval copy to use.
2462 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2463 SmallVector<SDValue, 8> Ops;
2465 if (!IsSibcall && isTailCall) {
2466 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2467 DAG.getIntPtrConstant(0, true), InFlag);
2468 InFlag = Chain.getValue(1);
2471 Ops.push_back(Chain);
2472 Ops.push_back(Callee);
2475 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2477 // Add argument registers to the end of the list so that they are known live
2479 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2480 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2481 RegsToPass[i].second.getValueType()));
2483 // Add an implicit use GOT pointer in EBX.
2484 if (!isTailCall && Subtarget->isPICStyleGOT())
2485 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2487 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2488 if (Is64Bit && isVarArg && !IsWin64)
2489 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2491 if (InFlag.getNode())
2492 Ops.push_back(InFlag);
2496 //// If this is the first return lowered for this function, add the regs
2497 //// to the liveout set for the function.
2498 // This isn't right, although it's probably harmless on x86; liveouts
2499 // should be computed from returns not tail calls. Consider a void
2500 // function making a tail call to a function returning int.
2501 return DAG.getNode(X86ISD::TC_RETURN, dl,
2502 NodeTys, &Ops[0], Ops.size());
2505 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2506 InFlag = Chain.getValue(1);
2508 // Create the CALLSEQ_END node.
2509 unsigned NumBytesForCalleeToPush;
2510 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2511 getTargetMachine().Options.GuaranteedTailCallOpt))
2512 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2513 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2514 // If this is a call to a struct-return function, the callee
2515 // pops the hidden struct pointer, so we have to push it back.
2516 // This is common for Darwin/X86, Linux & Mingw32 targets.
2517 NumBytesForCalleeToPush = 4;
2519 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2521 // Returns a flag for retval copy to use.
2523 Chain = DAG.getCALLSEQ_END(Chain,
2524 DAG.getIntPtrConstant(NumBytes, true),
2525 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2528 InFlag = Chain.getValue(1);
2531 // Handle result values, copying them out of physregs into vregs that we
2533 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2534 Ins, dl, DAG, InVals);
2538 //===----------------------------------------------------------------------===//
2539 // Fast Calling Convention (tail call) implementation
2540 //===----------------------------------------------------------------------===//
2542 // Like std call, callee cleans arguments, convention except that ECX is
2543 // reserved for storing the tail called function address. Only 2 registers are
2544 // free for argument passing (inreg). Tail call optimization is performed
2546 // * tailcallopt is enabled
2547 // * caller/callee are fastcc
2548 // On X86_64 architecture with GOT-style position independent code only local
2549 // (within module) calls are supported at the moment.
2550 // To keep the stack aligned according to platform abi the function
2551 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2552 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2553 // If a tail called function callee has more arguments than the caller the
2554 // caller needs to make sure that there is room to move the RETADDR to. This is
2555 // achieved by reserving an area the size of the argument delta right after the
2556 // original REtADDR, but before the saved framepointer or the spilled registers
2557 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2569 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2570 /// for a 16 byte align requirement.
2572 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2573 SelectionDAG& DAG) const {
2574 MachineFunction &MF = DAG.getMachineFunction();
2575 const TargetMachine &TM = MF.getTarget();
2576 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2577 unsigned StackAlignment = TFI.getStackAlignment();
2578 uint64_t AlignMask = StackAlignment - 1;
2579 int64_t Offset = StackSize;
2580 uint64_t SlotSize = TD->getPointerSize();
2581 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2582 // Number smaller than 12 so just add the difference.
2583 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2585 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2586 Offset = ((~AlignMask) & Offset) + StackAlignment +
2587 (StackAlignment-SlotSize);
2592 /// MatchingStackOffset - Return true if the given stack call argument is
2593 /// already available in the same position (relatively) of the caller's
2594 /// incoming argument stack.
2596 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2597 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2598 const X86InstrInfo *TII) {
2599 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2601 if (Arg.getOpcode() == ISD::CopyFromReg) {
2602 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2603 if (!TargetRegisterInfo::isVirtualRegister(VR))
2605 MachineInstr *Def = MRI->getVRegDef(VR);
2608 if (!Flags.isByVal()) {
2609 if (!TII->isLoadFromStackSlot(Def, FI))
2612 unsigned Opcode = Def->getOpcode();
2613 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2614 Def->getOperand(1).isFI()) {
2615 FI = Def->getOperand(1).getIndex();
2616 Bytes = Flags.getByValSize();
2620 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2621 if (Flags.isByVal())
2622 // ByVal argument is passed in as a pointer but it's now being
2623 // dereferenced. e.g.
2624 // define @foo(%struct.X* %A) {
2625 // tail call @bar(%struct.X* byval %A)
2628 SDValue Ptr = Ld->getBasePtr();
2629 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2632 FI = FINode->getIndex();
2633 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2634 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2635 FI = FINode->getIndex();
2636 Bytes = Flags.getByValSize();
2640 assert(FI != INT_MAX);
2641 if (!MFI->isFixedObjectIndex(FI))
2643 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2646 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2647 /// for tail call optimization. Targets which want to do tail call
2648 /// optimization should implement this function.
2650 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2651 CallingConv::ID CalleeCC,
2653 bool isCalleeStructRet,
2654 bool isCallerStructRet,
2655 const SmallVectorImpl<ISD::OutputArg> &Outs,
2656 const SmallVectorImpl<SDValue> &OutVals,
2657 const SmallVectorImpl<ISD::InputArg> &Ins,
2658 SelectionDAG& DAG) const {
2659 if (!IsTailCallConvention(CalleeCC) &&
2660 CalleeCC != CallingConv::C)
2663 // If -tailcallopt is specified, make fastcc functions tail-callable.
2664 const MachineFunction &MF = DAG.getMachineFunction();
2665 const Function *CallerF = DAG.getMachineFunction().getFunction();
2666 CallingConv::ID CallerCC = CallerF->getCallingConv();
2667 bool CCMatch = CallerCC == CalleeCC;
2669 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2670 if (IsTailCallConvention(CalleeCC) && CCMatch)
2675 // Look for obvious safe cases to perform tail call optimization that do not
2676 // require ABI changes. This is what gcc calls sibcall.
2678 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2679 // emit a special epilogue.
2680 if (RegInfo->needsStackRealignment(MF))
2683 // Also avoid sibcall optimization if either caller or callee uses struct
2684 // return semantics.
2685 if (isCalleeStructRet || isCallerStructRet)
2688 // An stdcall caller is expected to clean up its arguments; the callee
2689 // isn't going to do that.
2690 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2693 // Do not sibcall optimize vararg calls unless all arguments are passed via
2695 if (isVarArg && !Outs.empty()) {
2697 // Optimizing for varargs on Win64 is unlikely to be safe without
2698 // additional testing.
2699 if (Subtarget->isTargetWin64())
2702 SmallVector<CCValAssign, 16> ArgLocs;
2703 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2704 getTargetMachine(), ArgLocs, *DAG.getContext());
2706 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2707 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2708 if (!ArgLocs[i].isRegLoc())
2712 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2713 // Therefore if it's not used by the call it is not safe to optimize this into
2715 bool Unused = false;
2716 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2723 SmallVector<CCValAssign, 16> RVLocs;
2724 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2725 getTargetMachine(), RVLocs, *DAG.getContext());
2726 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2727 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2728 CCValAssign &VA = RVLocs[i];
2729 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2734 // If the calling conventions do not match, then we'd better make sure the
2735 // results are returned in the same way as what the caller expects.
2737 SmallVector<CCValAssign, 16> RVLocs1;
2738 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2739 getTargetMachine(), RVLocs1, *DAG.getContext());
2740 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2742 SmallVector<CCValAssign, 16> RVLocs2;
2743 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2744 getTargetMachine(), RVLocs2, *DAG.getContext());
2745 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2747 if (RVLocs1.size() != RVLocs2.size())
2749 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2750 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2752 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2754 if (RVLocs1[i].isRegLoc()) {
2755 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2758 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2764 // If the callee takes no arguments then go on to check the results of the
2766 if (!Outs.empty()) {
2767 // Check if stack adjustment is needed. For now, do not do this if any
2768 // argument is passed on the stack.
2769 SmallVector<CCValAssign, 16> ArgLocs;
2770 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2771 getTargetMachine(), ArgLocs, *DAG.getContext());
2773 // Allocate shadow area for Win64
2774 if (Subtarget->isTargetWin64()) {
2775 CCInfo.AllocateStack(32, 8);
2778 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2779 if (CCInfo.getNextStackOffset()) {
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2784 // Check if the arguments are already laid out in the right way as
2785 // the caller's fixed stack objects.
2786 MachineFrameInfo *MFI = MF.getFrameInfo();
2787 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2788 const X86InstrInfo *TII =
2789 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2790 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2791 CCValAssign &VA = ArgLocs[i];
2792 SDValue Arg = OutVals[i];
2793 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2794 if (VA.getLocInfo() == CCValAssign::Indirect)
2796 if (!VA.isRegLoc()) {
2797 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2804 // If the tailcall address may be in a register, then make sure it's
2805 // possible to register allocate for it. In 32-bit, the call address can
2806 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2807 // callee-saved registers are restored. These happen to be the same
2808 // registers used to pass 'inreg' arguments so watch out for those.
2809 if (!Subtarget->is64Bit() &&
2810 !isa<GlobalAddressSDNode>(Callee) &&
2811 !isa<ExternalSymbolSDNode>(Callee)) {
2812 unsigned NumInRegs = 0;
2813 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2814 CCValAssign &VA = ArgLocs[i];
2817 unsigned Reg = VA.getLocReg();
2820 case X86::EAX: case X86::EDX: case X86::ECX:
2821 if (++NumInRegs == 3)
2833 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2834 return X86::createFastISel(funcInfo);
2838 //===----------------------------------------------------------------------===//
2839 // Other Lowering Hooks
2840 //===----------------------------------------------------------------------===//
2842 static bool MayFoldLoad(SDValue Op) {
2843 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2846 static bool MayFoldIntoStore(SDValue Op) {
2847 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2850 static bool isTargetShuffle(unsigned Opcode) {
2852 default: return false;
2853 case X86ISD::PSHUFD:
2854 case X86ISD::PSHUFHW:
2855 case X86ISD::PSHUFLW:
2856 case X86ISD::SHUFPD:
2857 case X86ISD::PALIGN:
2858 case X86ISD::SHUFPS:
2859 case X86ISD::MOVLHPS:
2860 case X86ISD::MOVLHPD:
2861 case X86ISD::MOVHLPS:
2862 case X86ISD::MOVLPS:
2863 case X86ISD::MOVLPD:
2864 case X86ISD::MOVSHDUP:
2865 case X86ISD::MOVSLDUP:
2866 case X86ISD::MOVDDUP:
2869 case X86ISD::UNPCKL:
2870 case X86ISD::UNPCKH:
2871 case X86ISD::VPERMILP:
2872 case X86ISD::VPERM2X128:
2878 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2879 SDValue V1, SelectionDAG &DAG) {
2881 default: llvm_unreachable("Unknown x86 shuffle node");
2882 case X86ISD::MOVSHDUP:
2883 case X86ISD::MOVSLDUP:
2884 case X86ISD::MOVDDUP:
2885 return DAG.getNode(Opc, dl, VT, V1);
2891 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2892 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2894 default: llvm_unreachable("Unknown x86 shuffle node");
2895 case X86ISD::PSHUFD:
2896 case X86ISD::PSHUFHW:
2897 case X86ISD::PSHUFLW:
2898 case X86ISD::VPERMILP:
2899 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2905 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2906 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2908 default: llvm_unreachable("Unknown x86 shuffle node");
2909 case X86ISD::PALIGN:
2910 case X86ISD::SHUFPD:
2911 case X86ISD::SHUFPS:
2912 case X86ISD::VPERM2X128:
2913 return DAG.getNode(Opc, dl, VT, V1, V2,
2914 DAG.getConstant(TargetMask, MVT::i8));
2919 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2920 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2922 default: llvm_unreachable("Unknown x86 shuffle node");
2923 case X86ISD::MOVLHPS:
2924 case X86ISD::MOVLHPD:
2925 case X86ISD::MOVHLPS:
2926 case X86ISD::MOVLPS:
2927 case X86ISD::MOVLPD:
2930 case X86ISD::UNPCKL:
2931 case X86ISD::UNPCKH:
2932 return DAG.getNode(Opc, dl, VT, V1, V2);
2937 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2938 MachineFunction &MF = DAG.getMachineFunction();
2939 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2940 int ReturnAddrIndex = FuncInfo->getRAIndex();
2942 if (ReturnAddrIndex == 0) {
2943 // Set up a frame object for the return address.
2944 uint64_t SlotSize = TD->getPointerSize();
2945 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2947 FuncInfo->setRAIndex(ReturnAddrIndex);
2950 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2954 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2955 bool hasSymbolicDisplacement) {
2956 // Offset should fit into 32 bit immediate field.
2957 if (!isInt<32>(Offset))
2960 // If we don't have a symbolic displacement - we don't have any extra
2962 if (!hasSymbolicDisplacement)
2965 // FIXME: Some tweaks might be needed for medium code model.
2966 if (M != CodeModel::Small && M != CodeModel::Kernel)
2969 // For small code model we assume that latest object is 16MB before end of 31
2970 // bits boundary. We may also accept pretty large negative constants knowing
2971 // that all objects are in the positive half of address space.
2972 if (M == CodeModel::Small && Offset < 16*1024*1024)
2975 // For kernel code model we know that all object resist in the negative half
2976 // of 32bits address space. We may not accept negative offsets, since they may
2977 // be just off and we may accept pretty large positive ones.
2978 if (M == CodeModel::Kernel && Offset > 0)
2984 /// isCalleePop - Determines whether the callee is required to pop its
2985 /// own arguments. Callee pop is necessary to support tail calls.
2986 bool X86::isCalleePop(CallingConv::ID CallingConv,
2987 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2991 switch (CallingConv) {
2994 case CallingConv::X86_StdCall:
2996 case CallingConv::X86_FastCall:
2998 case CallingConv::X86_ThisCall:
3000 case CallingConv::Fast:
3002 case CallingConv::GHC:
3007 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3008 /// specific condition code, returning the condition code and the LHS/RHS of the
3009 /// comparison to make.
3010 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3011 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3013 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3014 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3015 // X > -1 -> X == 0, jump !sign.
3016 RHS = DAG.getConstant(0, RHS.getValueType());
3017 return X86::COND_NS;
3018 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3019 // X < 0 -> X == 0, jump on sign.
3021 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3023 RHS = DAG.getConstant(0, RHS.getValueType());
3024 return X86::COND_LE;
3028 switch (SetCCOpcode) {
3029 default: llvm_unreachable("Invalid integer condition!");
3030 case ISD::SETEQ: return X86::COND_E;
3031 case ISD::SETGT: return X86::COND_G;
3032 case ISD::SETGE: return X86::COND_GE;
3033 case ISD::SETLT: return X86::COND_L;
3034 case ISD::SETLE: return X86::COND_LE;
3035 case ISD::SETNE: return X86::COND_NE;
3036 case ISD::SETULT: return X86::COND_B;
3037 case ISD::SETUGT: return X86::COND_A;
3038 case ISD::SETULE: return X86::COND_BE;
3039 case ISD::SETUGE: return X86::COND_AE;
3043 // First determine if it is required or is profitable to flip the operands.
3045 // If LHS is a foldable load, but RHS is not, flip the condition.
3046 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3047 !ISD::isNON_EXTLoad(RHS.getNode())) {
3048 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3049 std::swap(LHS, RHS);
3052 switch (SetCCOpcode) {
3058 std::swap(LHS, RHS);
3062 // On a floating point condition, the flags are set as follows:
3064 // 0 | 0 | 0 | X > Y
3065 // 0 | 0 | 1 | X < Y
3066 // 1 | 0 | 0 | X == Y
3067 // 1 | 1 | 1 | unordered
3068 switch (SetCCOpcode) {
3069 default: llvm_unreachable("Condcode should be pre-legalized away");
3071 case ISD::SETEQ: return X86::COND_E;
3072 case ISD::SETOLT: // flipped
3074 case ISD::SETGT: return X86::COND_A;
3075 case ISD::SETOLE: // flipped
3077 case ISD::SETGE: return X86::COND_AE;
3078 case ISD::SETUGT: // flipped
3080 case ISD::SETLT: return X86::COND_B;
3081 case ISD::SETUGE: // flipped
3083 case ISD::SETLE: return X86::COND_BE;
3085 case ISD::SETNE: return X86::COND_NE;
3086 case ISD::SETUO: return X86::COND_P;
3087 case ISD::SETO: return X86::COND_NP;
3089 case ISD::SETUNE: return X86::COND_INVALID;
3093 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3094 /// code. Current x86 isa includes the following FP cmov instructions:
3095 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3096 static bool hasFPCMov(unsigned X86CC) {
3112 /// isFPImmLegal - Returns true if the target can instruction select the
3113 /// specified FP immediate natively. If false, the legalizer will
3114 /// materialize the FP immediate as a load from a constant pool.
3115 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3116 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3117 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3123 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3124 /// the specified range (L, H].
3125 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3126 return (Val < 0) || (Val >= Low && Val < Hi);
3129 /// isUndefOrInRange - Return true if every element in Mask, begining
3130 /// from position Pos and ending in Pos+Size, falls within the specified
3131 /// range (L, L+Pos]. or is undef.
3132 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3133 int Pos, int Size, int Low, int Hi) {
3134 for (int i = Pos, e = Pos+Size; i != e; ++i)
3135 if (!isUndefOrInRange(Mask[i], Low, Hi))
3140 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3141 /// specified value.
3142 static bool isUndefOrEqual(int Val, int CmpVal) {
3143 if (Val < 0 || Val == CmpVal)
3148 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3149 /// from position Pos and ending in Pos+Size, falls within the specified
3150 /// sequential range (L, L+Pos]. or is undef.
3151 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3152 int Pos, int Size, int Low) {
3153 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3154 if (!isUndefOrEqual(Mask[i], Low))
3159 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3160 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3161 /// the second operand.
3162 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3163 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3164 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3165 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3166 return (Mask[0] < 2 && Mask[1] < 2);
3170 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3171 SmallVector<int, 8> M;
3173 return ::isPSHUFDMask(M, N->getValueType(0));
3176 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3177 /// is suitable for input to PSHUFHW.
3178 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3179 if (VT != MVT::v8i16)
3182 // Lower quadword copied in order or undef.
3183 for (int i = 0; i != 4; ++i)
3184 if (Mask[i] >= 0 && Mask[i] != i)
3187 // Upper quadword shuffled.
3188 for (int i = 4; i != 8; ++i)
3189 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3195 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3196 SmallVector<int, 8> M;
3198 return ::isPSHUFHWMask(M, N->getValueType(0));
3201 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3202 /// is suitable for input to PSHUFLW.
3203 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3204 if (VT != MVT::v8i16)
3207 // Upper quadword copied in order.
3208 for (int i = 4; i != 8; ++i)
3209 if (Mask[i] >= 0 && Mask[i] != i)
3212 // Lower quadword shuffled.
3213 for (int i = 0; i != 4; ++i)
3220 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3221 SmallVector<int, 8> M;
3223 return ::isPSHUFLWMask(M, N->getValueType(0));
3226 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3227 /// is suitable for input to PALIGNR.
3228 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3229 bool hasSSSE3OrAVX) {
3230 int i, e = VT.getVectorNumElements();
3231 if (VT.getSizeInBits() != 128)
3234 // Do not handle v2i64 / v2f64 shuffles with palignr.
3235 if (e < 4 || !hasSSSE3OrAVX)
3238 for (i = 0; i != e; ++i)
3242 // All undef, not a palignr.
3246 // Make sure we're shifting in the right direction.
3250 int s = Mask[i] - i;
3252 // Check the rest of the elements to see if they are consecutive.
3253 for (++i; i != e; ++i) {
3255 if (m >= 0 && m != s+i)
3261 /// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand
3262 /// specifies a shuffle of elements that is suitable for input to 256-bit
3264 static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3265 bool HasAVX, bool Commuted = false) {
3266 int NumElems = VT.getVectorNumElements();
3268 if (!HasAVX || VT.getSizeInBits() != 256)
3271 if (NumElems != 4 && NumElems != 8)
3274 // VSHUFPSY divides the resulting vector into 4 chunks.
3275 // The sources are also splitted into 4 chunks, and each destination
3276 // chunk must come from a different source chunk.
3278 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3279 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3281 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3282 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3284 // VSHUFPDY divides the resulting vector into 4 chunks.
3285 // The sources are also splitted into 4 chunks, and each destination
3286 // chunk must come from a different source chunk.
3288 // SRC1 => X3 X2 X1 X0
3289 // SRC2 => Y3 Y2 Y1 Y0
3291 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3293 unsigned QuarterSize = NumElems/4;
3294 unsigned HalfSize = QuarterSize*2;
3295 for (unsigned l = 0; l != 2; ++l) {
3296 unsigned LaneStart = l*HalfSize;
3297 for (unsigned s = 0; s != 2; ++s) {
3298 unsigned QuarterStart = s*QuarterSize;
3299 unsigned Src = (Commuted) ? (1-s) : s;
3300 unsigned SrcStart = Src*NumElems + LaneStart;
3301 for (unsigned i = 0; i != QuarterSize; ++i) {
3302 int Idx = Mask[i+QuarterStart+LaneStart];
3303 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize))
3305 // For VSHUFPSY, the mask of the second half must be the same as the first
3306 // but with the appropriate offsets. This works in the same way as
3307 // VPERMILPS works with masks.
3308 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0)
3310 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+HalfSize))
3319 /// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle
3320 /// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions.
3321 static unsigned getShuffleVSHUFPYImmediate(SDNode *N) {
3322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3323 EVT VT = SVOp->getValueType(0);
3324 int NumElems = VT.getVectorNumElements();
3326 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types");
3327 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types");
3329 int HalfSize = NumElems/2;
3330 unsigned Mul = (NumElems == 8) ? 2 : 1;
3332 for (int i = 0; i != NumElems; ++i) {
3333 int Elt = SVOp->getMaskElt(i);
3338 // For VSHUFPSY, the mask of the first half must be equal to the second one.
3339 if (NumElems == 8) Shamt %= HalfSize;
3340 Mask |= Elt << (Shamt*Mul);
3346 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3347 /// the two vector operands have swapped position.
3348 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3349 unsigned NumElems) {
3350 for (unsigned i = 0; i != NumElems; ++i) {
3354 else if (idx < (int)NumElems)
3355 Mask[i] = idx + NumElems;
3357 Mask[i] = idx - NumElems;
3361 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3362 /// specifies a shuffle of elements that is suitable for input to 128-bit
3363 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3364 /// reverse of what x86 shuffles want.
3365 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3366 bool Commuted = false) {
3367 unsigned NumElems = VT.getVectorNumElements();
3369 if (VT.getSizeInBits() != 128)
3372 if (NumElems != 2 && NumElems != 4)
3375 unsigned Half = NumElems / 2;
3376 unsigned SrcStart = Commuted ? NumElems : 0;
3377 for (unsigned i = 0; i != Half; ++i)
3378 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3380 SrcStart = Commuted ? 0 : NumElems;
3381 for (unsigned i = Half; i != NumElems; ++i)
3382 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3388 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3389 SmallVector<int, 8> M;
3391 return ::isSHUFPMask(M, N->getValueType(0));
3394 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3395 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3396 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3397 EVT VT = N->getValueType(0);
3398 unsigned NumElems = VT.getVectorNumElements();
3400 if (VT.getSizeInBits() != 128)
3406 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3407 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3408 isUndefOrEqual(N->getMaskElt(1), 7) &&
3409 isUndefOrEqual(N->getMaskElt(2), 2) &&
3410 isUndefOrEqual(N->getMaskElt(3), 3);
3413 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3414 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3416 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3417 EVT VT = N->getValueType(0);
3418 unsigned NumElems = VT.getVectorNumElements();
3420 if (VT.getSizeInBits() != 128)
3426 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3427 isUndefOrEqual(N->getMaskElt(1), 3) &&
3428 isUndefOrEqual(N->getMaskElt(2), 2) &&
3429 isUndefOrEqual(N->getMaskElt(3), 3);
3432 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3433 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3434 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3435 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3437 if (NumElems != 2 && NumElems != 4)
3440 for (unsigned i = 0; i < NumElems/2; ++i)
3441 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3444 for (unsigned i = NumElems/2; i < NumElems; ++i)
3445 if (!isUndefOrEqual(N->getMaskElt(i), i))
3451 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3452 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3453 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3454 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3456 if ((NumElems != 2 && NumElems != 4)
3457 || N->getValueType(0).getSizeInBits() > 128)
3460 for (unsigned i = 0; i < NumElems/2; ++i)
3461 if (!isUndefOrEqual(N->getMaskElt(i), i))
3464 for (unsigned i = 0; i < NumElems/2; ++i)
3465 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3471 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3472 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3473 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3474 bool HasAVX2, bool V2IsSplat = false) {
3475 int NumElts = VT.getVectorNumElements();
3477 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3478 "Unsupported vector type for unpckh");
3480 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3481 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3484 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3485 // independently on 128-bit lanes.
3486 unsigned NumLanes = VT.getSizeInBits()/128;
3487 unsigned NumLaneElts = NumElts/NumLanes;
3490 unsigned End = NumLaneElts;
3491 for (unsigned s = 0; s < NumLanes; ++s) {
3492 for (unsigned i = Start, j = s * NumLaneElts;
3496 int BitI1 = Mask[i+1];
3497 if (!isUndefOrEqual(BitI, j))
3500 if (!isUndefOrEqual(BitI1, NumElts))
3503 if (!isUndefOrEqual(BitI1, j + NumElts))
3507 // Process the next 128 bits.
3508 Start += NumLaneElts;
3515 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3516 SmallVector<int, 8> M;
3518 return ::isUNPCKLMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3521 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3522 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3523 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3524 bool HasAVX2, bool V2IsSplat = false) {
3525 int NumElts = VT.getVectorNumElements();
3527 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3528 "Unsupported vector type for unpckh");
3530 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3531 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3534 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3535 // independently on 128-bit lanes.
3536 unsigned NumLanes = VT.getSizeInBits()/128;
3537 unsigned NumLaneElts = NumElts/NumLanes;
3540 unsigned End = NumLaneElts;
3541 for (unsigned l = 0; l != NumLanes; ++l) {
3542 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3543 i != End; i += 2, ++j) {
3545 int BitI1 = Mask[i+1];
3546 if (!isUndefOrEqual(BitI, j))
3549 if (isUndefOrEqual(BitI1, NumElts))
3552 if (!isUndefOrEqual(BitI1, j+NumElts))
3556 // Process the next 128 bits.
3557 Start += NumLaneElts;
3563 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3564 SmallVector<int, 8> M;
3566 return ::isUNPCKHMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3569 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3570 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3572 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3573 int NumElems = VT.getVectorNumElements();
3574 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3577 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3578 // FIXME: Need a better way to get rid of this, there's no latency difference
3579 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3580 // the former later. We should also remove the "_undef" special mask.
3581 if (NumElems == 4 && VT.getSizeInBits() == 256)
3584 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3585 // independently on 128-bit lanes.
3586 unsigned NumLanes = VT.getSizeInBits() / 128;
3587 unsigned NumLaneElts = NumElems / NumLanes;
3589 for (unsigned s = 0; s < NumLanes; ++s) {
3590 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3591 i != NumLaneElts * (s + 1);
3594 int BitI1 = Mask[i+1];
3596 if (!isUndefOrEqual(BitI, j))
3598 if (!isUndefOrEqual(BitI1, j))
3606 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3607 SmallVector<int, 8> M;
3609 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3612 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3613 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3615 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3616 int NumElems = VT.getVectorNumElements();
3617 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3620 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3622 int BitI1 = Mask[i+1];
3623 if (!isUndefOrEqual(BitI, j))
3625 if (!isUndefOrEqual(BitI1, j))
3631 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3632 SmallVector<int, 8> M;
3634 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3637 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3638 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3639 /// MOVSD, and MOVD, i.e. setting the lowest element.
3640 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3641 if (VT.getVectorElementType().getSizeInBits() < 32)
3644 int NumElts = VT.getVectorNumElements();
3646 if (!isUndefOrEqual(Mask[0], NumElts))
3649 for (int i = 1; i < NumElts; ++i)
3650 if (!isUndefOrEqual(Mask[i], i))
3656 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3657 SmallVector<int, 8> M;
3659 return ::isMOVLMask(M, N->getValueType(0));
3662 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3663 /// as permutations between 128-bit chunks or halves. As an example: this
3665 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3666 /// The first half comes from the second half of V1 and the second half from the
3667 /// the second half of V2.
3668 static bool isVPERM2X128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3670 if (!HasAVX || VT.getSizeInBits() != 256)
3673 // The shuffle result is divided into half A and half B. In total the two
3674 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3675 // B must come from C, D, E or F.
3676 int HalfSize = VT.getVectorNumElements()/2;
3677 bool MatchA = false, MatchB = false;
3679 // Check if A comes from one of C, D, E, F.
3680 for (int Half = 0; Half < 4; ++Half) {
3681 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3687 // Check if B comes from one of C, D, E, F.
3688 for (int Half = 0; Half < 4; ++Half) {
3689 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3695 return MatchA && MatchB;
3698 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3699 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3700 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3701 EVT VT = SVOp->getValueType(0);
3703 int HalfSize = VT.getVectorNumElements()/2;
3705 int FstHalf = 0, SndHalf = 0;
3706 for (int i = 0; i < HalfSize; ++i) {
3707 if (SVOp->getMaskElt(i) > 0) {
3708 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3712 for (int i = HalfSize; i < HalfSize*2; ++i) {
3713 if (SVOp->getMaskElt(i) > 0) {
3714 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3719 return (FstHalf | (SndHalf << 4));
3722 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3723 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3724 /// Note that VPERMIL mask matching is different depending whether theunderlying
3725 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3726 /// to the same elements of the low, but to the higher half of the source.
3727 /// In VPERMILPD the two lanes could be shuffled independently of each other
3728 /// with the same restriction that lanes can't be crossed.
3729 static bool isVPERMILPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3731 int NumElts = VT.getVectorNumElements();
3732 int NumLanes = VT.getSizeInBits()/128;
3737 // Only match 256-bit with 32/64-bit types
3738 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3741 int LaneSize = NumElts/NumLanes;
3742 for (int l = 0; l != NumLanes; ++l) {
3743 int LaneStart = l*LaneSize;
3744 for (int i = 0; i != LaneSize; ++i) {
3745 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize))
3747 if (NumElts == 4 || l == 0)
3749 // VPERMILPS handling
3752 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneSize))
3760 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3761 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3762 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3763 EVT VT = SVOp->getValueType(0);
3765 int NumElts = VT.getVectorNumElements();
3766 int NumLanes = VT.getSizeInBits()/128;
3767 int LaneSize = NumElts/NumLanes;
3769 // Although the mask is equal for both lanes do it twice to get the cases
3770 // where a mask will match because the same mask element is undef on the
3771 // first half but valid on the second. This would get pathological cases
3772 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3773 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3775 for (int i = 0; i != NumElts; ++i) {
3776 int MaskElt = SVOp->getMaskElt(i);
3779 MaskElt %= LaneSize;
3781 // VPERMILPSY, the mask of the first half must be equal to the second one
3782 if (NumElts == 8) Shamt %= LaneSize;
3783 Mask |= MaskElt << (Shamt*Shift);
3789 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3790 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3791 /// element of vector 2 and the other elements to come from vector 1 in order.
3792 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3793 bool V2IsSplat = false, bool V2IsUndef = false) {
3794 int NumOps = VT.getVectorNumElements();
3795 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3798 if (!isUndefOrEqual(Mask[0], 0))
3801 for (int i = 1; i < NumOps; ++i)
3802 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3803 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3804 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3810 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3811 bool V2IsUndef = false) {
3812 SmallVector<int, 8> M;
3814 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3817 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3818 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3819 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3820 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3821 const X86Subtarget *Subtarget) {
3822 if (!Subtarget->hasSSE3orAVX())
3825 // The second vector must be undef
3826 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3829 EVT VT = N->getValueType(0);
3830 unsigned NumElems = VT.getVectorNumElements();
3832 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3833 (VT.getSizeInBits() == 256 && NumElems != 8))
3836 // "i+1" is the value the indexed mask element must have
3837 for (unsigned i = 0; i < NumElems; i += 2)
3838 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3839 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3845 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3846 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3847 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3848 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3849 const X86Subtarget *Subtarget) {
3850 if (!Subtarget->hasSSE3orAVX())
3853 // The second vector must be undef
3854 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3857 EVT VT = N->getValueType(0);
3858 unsigned NumElems = VT.getVectorNumElements();
3860 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3861 (VT.getSizeInBits() == 256 && NumElems != 8))
3864 // "i" is the value the indexed mask element must have
3865 for (unsigned i = 0; i < NumElems; i += 2)
3866 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3867 !isUndefOrEqual(N->getMaskElt(i+1), i))
3873 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3874 /// specifies a shuffle of elements that is suitable for input to 256-bit
3875 /// version of MOVDDUP.
3876 static bool isMOVDDUPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3878 int NumElts = VT.getVectorNumElements();
3880 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3883 for (int i = 0; i != NumElts/2; ++i)
3884 if (!isUndefOrEqual(Mask[i], 0))
3886 for (int i = NumElts/2; i != NumElts; ++i)
3887 if (!isUndefOrEqual(Mask[i], NumElts/2))
3892 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3893 /// specifies a shuffle of elements that is suitable for input to 128-bit
3894 /// version of MOVDDUP.
3895 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3896 EVT VT = N->getValueType(0);
3898 if (VT.getSizeInBits() != 128)
3901 int e = VT.getVectorNumElements() / 2;
3902 for (int i = 0; i < e; ++i)
3903 if (!isUndefOrEqual(N->getMaskElt(i), i))
3905 for (int i = 0; i < e; ++i)
3906 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3911 /// isVEXTRACTF128Index - Return true if the specified
3912 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3913 /// suitable for input to VEXTRACTF128.
3914 bool X86::isVEXTRACTF128Index(SDNode *N) {
3915 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3918 // The index should be aligned on a 128-bit boundary.
3920 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3922 unsigned VL = N->getValueType(0).getVectorNumElements();
3923 unsigned VBits = N->getValueType(0).getSizeInBits();
3924 unsigned ElSize = VBits / VL;
3925 bool Result = (Index * ElSize) % 128 == 0;
3930 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3931 /// operand specifies a subvector insert that is suitable for input to
3933 bool X86::isVINSERTF128Index(SDNode *N) {
3934 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3937 // The index should be aligned on a 128-bit boundary.
3939 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3941 unsigned VL = N->getValueType(0).getVectorNumElements();
3942 unsigned VBits = N->getValueType(0).getSizeInBits();
3943 unsigned ElSize = VBits / VL;
3944 bool Result = (Index * ElSize) % 128 == 0;
3949 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3950 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3951 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3952 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3953 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3955 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3957 for (int i = 0; i < NumOperands; ++i) {
3958 int Val = SVOp->getMaskElt(NumOperands-i-1);
3959 if (Val < 0) Val = 0;
3960 if (Val >= NumOperands) Val -= NumOperands;
3962 if (i != NumOperands - 1)
3968 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3969 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3970 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3971 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3973 // 8 nodes, but we only care about the last 4.
3974 for (unsigned i = 7; i >= 4; --i) {
3975 int Val = SVOp->getMaskElt(i);
3984 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3985 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3986 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3987 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3989 // 8 nodes, but we only care about the first 4.
3990 for (int i = 3; i >= 0; --i) {
3991 int Val = SVOp->getMaskElt(i);
4000 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4001 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4002 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4003 EVT VT = SVOp->getValueType(0);
4004 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4008 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4009 Val = SVOp->getMaskElt(i);
4013 assert(Val - i > 0 && "PALIGNR imm should be positive");
4014 return (Val - i) * EltSize;
4017 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4018 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4020 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4021 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4022 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4025 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4027 EVT VecVT = N->getOperand(0).getValueType();
4028 EVT ElVT = VecVT.getVectorElementType();
4030 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4031 return Index / NumElemsPerChunk;
4034 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4035 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4037 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4038 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4039 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4042 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4044 EVT VecVT = N->getValueType(0);
4045 EVT ElVT = VecVT.getVectorElementType();
4047 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4048 return Index / NumElemsPerChunk;
4051 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4053 bool X86::isZeroNode(SDValue Elt) {
4054 return ((isa<ConstantSDNode>(Elt) &&
4055 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4056 (isa<ConstantFPSDNode>(Elt) &&
4057 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4060 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4061 /// their permute mask.
4062 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4063 SelectionDAG &DAG) {
4064 EVT VT = SVOp->getValueType(0);
4065 unsigned NumElems = VT.getVectorNumElements();
4066 SmallVector<int, 8> MaskVec;
4068 for (unsigned i = 0; i != NumElems; ++i) {
4069 int idx = SVOp->getMaskElt(i);
4071 MaskVec.push_back(idx);
4072 else if (idx < (int)NumElems)
4073 MaskVec.push_back(idx + NumElems);
4075 MaskVec.push_back(idx - NumElems);
4077 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4078 SVOp->getOperand(0), &MaskVec[0]);
4081 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4082 /// match movhlps. The lower half elements should come from upper half of
4083 /// V1 (and in order), and the upper half elements should come from the upper
4084 /// half of V2 (and in order).
4085 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4086 EVT VT = Op->getValueType(0);
4087 if (VT.getSizeInBits() != 128)
4089 if (VT.getVectorNumElements() != 4)
4091 for (unsigned i = 0, e = 2; i != e; ++i)
4092 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4094 for (unsigned i = 2; i != 4; ++i)
4095 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4100 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4101 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4103 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4104 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4106 N = N->getOperand(0).getNode();
4107 if (!ISD::isNON_EXTLoad(N))
4110 *LD = cast<LoadSDNode>(N);
4114 // Test whether the given value is a vector value which will be legalized
4116 static bool WillBeConstantPoolLoad(SDNode *N) {
4117 if (N->getOpcode() != ISD::BUILD_VECTOR)
4120 // Check for any non-constant elements.
4121 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4122 switch (N->getOperand(i).getNode()->getOpcode()) {
4124 case ISD::ConstantFP:
4131 // Vectors of all-zeros and all-ones are materialized with special
4132 // instructions rather than being loaded.
4133 return !ISD::isBuildVectorAllZeros(N) &&
4134 !ISD::isBuildVectorAllOnes(N);
4137 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4138 /// match movlp{s|d}. The lower half elements should come from lower half of
4139 /// V1 (and in order), and the upper half elements should come from the upper
4140 /// half of V2 (and in order). And since V1 will become the source of the
4141 /// MOVLP, it must be either a vector load or a scalar load to vector.
4142 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4143 ShuffleVectorSDNode *Op) {
4144 EVT VT = Op->getValueType(0);
4145 if (VT.getSizeInBits() != 128)
4148 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4150 // Is V2 is a vector load, don't do this transformation. We will try to use
4151 // load folding shufps op.
4152 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4155 unsigned NumElems = VT.getVectorNumElements();
4157 if (NumElems != 2 && NumElems != 4)
4159 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4160 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4162 for (unsigned i = NumElems/2; i != NumElems; ++i)
4163 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4168 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4170 static bool isSplatVector(SDNode *N) {
4171 if (N->getOpcode() != ISD::BUILD_VECTOR)
4174 SDValue SplatValue = N->getOperand(0);
4175 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4176 if (N->getOperand(i) != SplatValue)
4181 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4182 /// to an zero vector.
4183 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4184 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4185 SDValue V1 = N->getOperand(0);
4186 SDValue V2 = N->getOperand(1);
4187 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4188 for (unsigned i = 0; i != NumElems; ++i) {
4189 int Idx = N->getMaskElt(i);
4190 if (Idx >= (int)NumElems) {
4191 unsigned Opc = V2.getOpcode();
4192 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4194 if (Opc != ISD::BUILD_VECTOR ||
4195 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4197 } else if (Idx >= 0) {
4198 unsigned Opc = V1.getOpcode();
4199 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4201 if (Opc != ISD::BUILD_VECTOR ||
4202 !X86::isZeroNode(V1.getOperand(Idx)))
4209 /// getZeroVector - Returns a vector of specified type with all zero elements.
4211 static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG,
4213 assert(VT.isVector() && "Expected a vector type");
4215 // Always build SSE zero vectors as <4 x i32> bitcasted
4216 // to their dest type. This ensures they get CSE'd.
4218 if (VT.getSizeInBits() == 128) { // SSE
4219 if (HasXMMInt) { // SSE2
4220 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4221 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4223 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4224 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4226 } else if (VT.getSizeInBits() == 256) { // AVX
4227 // 256-bit logic and arithmetic instructions in AVX are
4228 // all floating-point, no support for integer ops. Default
4229 // to emitting fp zeroed vectors then.
4230 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4231 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4232 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4234 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4237 /// getOnesVector - Returns a vector of specified type with all bits set.
4238 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4239 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4240 /// Then bitcast to their original type, ensuring they get CSE'd.
4241 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4243 assert(VT.isVector() && "Expected a vector type");
4244 assert((VT.is128BitVector() || VT.is256BitVector())
4245 && "Expected a 128-bit or 256-bit vector type");
4247 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4249 if (VT.getSizeInBits() == 256) {
4250 if (HasAVX2) { // AVX2
4251 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4254 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4255 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4256 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4257 Vec = Insert128BitVector(InsV, Vec,
4258 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4264 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4267 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4268 /// that point to V2 points to its first element.
4269 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4270 EVT VT = SVOp->getValueType(0);
4271 unsigned NumElems = VT.getVectorNumElements();
4273 bool Changed = false;
4274 SmallVector<int, 8> MaskVec;
4275 SVOp->getMask(MaskVec);
4277 for (unsigned i = 0; i != NumElems; ++i) {
4278 if (MaskVec[i] > (int)NumElems) {
4279 MaskVec[i] = NumElems;
4284 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4285 SVOp->getOperand(1), &MaskVec[0]);
4286 return SDValue(SVOp, 0);
4289 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4290 /// operation of specified width.
4291 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4293 unsigned NumElems = VT.getVectorNumElements();
4294 SmallVector<int, 8> Mask;
4295 Mask.push_back(NumElems);
4296 for (unsigned i = 1; i != NumElems; ++i)
4298 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4301 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4302 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4304 unsigned NumElems = VT.getVectorNumElements();
4305 SmallVector<int, 8> Mask;
4306 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4308 Mask.push_back(i + NumElems);
4310 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4313 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4314 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4316 unsigned NumElems = VT.getVectorNumElements();
4317 unsigned Half = NumElems/2;
4318 SmallVector<int, 8> Mask;
4319 for (unsigned i = 0; i != Half; ++i) {
4320 Mask.push_back(i + Half);
4321 Mask.push_back(i + NumElems + Half);
4323 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4326 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4327 // a generic shuffle instruction because the target has no such instructions.
4328 // Generate shuffles which repeat i16 and i8 several times until they can be
4329 // represented by v4f32 and then be manipulated by target suported shuffles.
4330 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4331 EVT VT = V.getValueType();
4332 int NumElems = VT.getVectorNumElements();
4333 DebugLoc dl = V.getDebugLoc();
4335 while (NumElems > 4) {
4336 if (EltNo < NumElems/2) {
4337 V = getUnpackl(DAG, dl, VT, V, V);
4339 V = getUnpackh(DAG, dl, VT, V, V);
4340 EltNo -= NumElems/2;
4347 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4348 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4349 EVT VT = V.getValueType();
4350 DebugLoc dl = V.getDebugLoc();
4351 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4352 && "Vector size not supported");
4354 if (VT.getSizeInBits() == 128) {
4355 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4356 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4357 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4360 // To use VPERMILPS to splat scalars, the second half of indicies must
4361 // refer to the higher part, which is a duplication of the lower one,
4362 // because VPERMILPS can only handle in-lane permutations.
4363 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4364 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4366 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4367 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4371 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4374 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4375 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4376 EVT SrcVT = SV->getValueType(0);
4377 SDValue V1 = SV->getOperand(0);
4378 DebugLoc dl = SV->getDebugLoc();
4380 int EltNo = SV->getSplatIndex();
4381 int NumElems = SrcVT.getVectorNumElements();
4382 unsigned Size = SrcVT.getSizeInBits();
4384 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4385 "Unknown how to promote splat for type");
4387 // Extract the 128-bit part containing the splat element and update
4388 // the splat element index when it refers to the higher register.
4390 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4391 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4393 EltNo -= NumElems/2;
4396 // All i16 and i8 vector types can't be used directly by a generic shuffle
4397 // instruction because the target has no such instruction. Generate shuffles
4398 // which repeat i16 and i8 several times until they fit in i32, and then can
4399 // be manipulated by target suported shuffles.
4400 EVT EltVT = SrcVT.getVectorElementType();
4401 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4402 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4404 // Recreate the 256-bit vector and place the same 128-bit vector
4405 // into the low and high part. This is necessary because we want
4406 // to use VPERM* to shuffle the vectors
4408 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4409 DAG.getConstant(0, MVT::i32), DAG, dl);
4410 V1 = Insert128BitVector(InsV, V1,
4411 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4414 return getLegalSplat(DAG, V1, EltNo);
4417 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4418 /// vector of zero or undef vector. This produces a shuffle where the low
4419 /// element of V2 is swizzled into the zero/undef vector, landing at element
4420 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4421 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4422 bool isZero, bool HasXMMInt,
4423 SelectionDAG &DAG) {
4424 EVT VT = V2.getValueType();
4426 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4427 unsigned NumElems = VT.getVectorNumElements();
4428 SmallVector<int, 16> MaskVec;
4429 for (unsigned i = 0; i != NumElems; ++i)
4430 // If this is the insertion idx, put the low elt of V2 here.
4431 MaskVec.push_back(i == Idx ? NumElems : i);
4432 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4435 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4436 /// element of the result of the vector shuffle.
4437 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4440 return SDValue(); // Limit search depth.
4442 SDValue V = SDValue(N, 0);
4443 EVT VT = V.getValueType();
4444 unsigned Opcode = V.getOpcode();
4446 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4447 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4448 Index = SV->getMaskElt(Index);
4451 return DAG.getUNDEF(VT.getVectorElementType());
4453 int NumElems = VT.getVectorNumElements();
4454 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4455 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4458 // Recurse into target specific vector shuffles to find scalars.
4459 if (isTargetShuffle(Opcode)) {
4460 int NumElems = VT.getVectorNumElements();
4461 SmallVector<unsigned, 16> ShuffleMask;
4465 case X86ISD::SHUFPS:
4466 case X86ISD::SHUFPD:
4467 ImmN = N->getOperand(N->getNumOperands()-1);
4468 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4471 case X86ISD::UNPCKH:
4472 DecodeUNPCKHMask(VT, ShuffleMask);
4474 case X86ISD::UNPCKL:
4475 DecodeUNPCKLMask(VT, ShuffleMask);
4477 case X86ISD::MOVHLPS:
4478 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4480 case X86ISD::MOVLHPS:
4481 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4483 case X86ISD::PSHUFD:
4484 ImmN = N->getOperand(N->getNumOperands()-1);
4485 DecodePSHUFMask(NumElems,
4486 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4489 case X86ISD::PSHUFHW:
4490 ImmN = N->getOperand(N->getNumOperands()-1);
4491 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4494 case X86ISD::PSHUFLW:
4495 ImmN = N->getOperand(N->getNumOperands()-1);
4496 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4500 case X86ISD::MOVSD: {
4501 // The index 0 always comes from the first element of the second source,
4502 // this is why MOVSS and MOVSD are used in the first place. The other
4503 // elements come from the other positions of the first source vector.
4504 unsigned OpNum = (Index == 0) ? 1 : 0;
4505 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4508 case X86ISD::VPERMILP:
4509 ImmN = N->getOperand(N->getNumOperands()-1);
4510 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4513 case X86ISD::VPERM2X128:
4514 ImmN = N->getOperand(N->getNumOperands()-1);
4515 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4518 case X86ISD::MOVDDUP:
4519 case X86ISD::MOVLHPD:
4520 case X86ISD::MOVLPD:
4521 case X86ISD::MOVLPS:
4522 case X86ISD::MOVSHDUP:
4523 case X86ISD::MOVSLDUP:
4524 case X86ISD::PALIGN:
4525 return SDValue(); // Not yet implemented.
4527 assert(0 && "unknown target shuffle node");
4531 Index = ShuffleMask[Index];
4533 return DAG.getUNDEF(VT.getVectorElementType());
4535 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4536 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4540 // Actual nodes that may contain scalar elements
4541 if (Opcode == ISD::BITCAST) {
4542 V = V.getOperand(0);
4543 EVT SrcVT = V.getValueType();
4544 unsigned NumElems = VT.getVectorNumElements();
4546 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4550 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4551 return (Index == 0) ? V.getOperand(0)
4552 : DAG.getUNDEF(VT.getVectorElementType());
4554 if (V.getOpcode() == ISD::BUILD_VECTOR)
4555 return V.getOperand(Index);
4560 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4561 /// shuffle operation which come from a consecutively from a zero. The
4562 /// search can start in two different directions, from left or right.
4564 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4565 bool ZerosFromLeft, SelectionDAG &DAG) {
4568 while (i < NumElems) {
4569 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4570 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4571 if (!(Elt.getNode() &&
4572 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4580 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4581 /// MaskE correspond consecutively to elements from one of the vector operands,
4582 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4584 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4585 int OpIdx, int NumElems, unsigned &OpNum) {
4586 bool SeenV1 = false;
4587 bool SeenV2 = false;
4589 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4590 int Idx = SVOp->getMaskElt(i);
4591 // Ignore undef indicies
4600 // Only accept consecutive elements from the same vector
4601 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4605 OpNum = SeenV1 ? 0 : 1;
4609 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4610 /// logical left shift of a vector.
4611 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4612 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4613 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4614 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4615 false /* check zeros from right */, DAG);
4621 // Considering the elements in the mask that are not consecutive zeros,
4622 // check if they consecutively come from only one of the source vectors.
4624 // V1 = {X, A, B, C} 0
4626 // vector_shuffle V1, V2 <1, 2, 3, X>
4628 if (!isShuffleMaskConsecutive(SVOp,
4629 0, // Mask Start Index
4630 NumElems-NumZeros-1, // Mask End Index
4631 NumZeros, // Where to start looking in the src vector
4632 NumElems, // Number of elements in vector
4633 OpSrc)) // Which source operand ?
4638 ShVal = SVOp->getOperand(OpSrc);
4642 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4643 /// logical left shift of a vector.
4644 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4645 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4646 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4647 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4648 true /* check zeros from left */, DAG);
4654 // Considering the elements in the mask that are not consecutive zeros,
4655 // check if they consecutively come from only one of the source vectors.
4657 // 0 { A, B, X, X } = V2
4659 // vector_shuffle V1, V2 <X, X, 4, 5>
4661 if (!isShuffleMaskConsecutive(SVOp,
4662 NumZeros, // Mask Start Index
4663 NumElems-1, // Mask End Index
4664 0, // Where to start looking in the src vector
4665 NumElems, // Number of elements in vector
4666 OpSrc)) // Which source operand ?
4671 ShVal = SVOp->getOperand(OpSrc);
4675 /// isVectorShift - Returns true if the shuffle can be implemented as a
4676 /// logical left or right shift of a vector.
4677 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4678 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4679 // Although the logic below support any bitwidth size, there are no
4680 // shift instructions which handle more than 128-bit vectors.
4681 if (SVOp->getValueType(0).getSizeInBits() > 128)
4684 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4685 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4691 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4693 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4694 unsigned NumNonZero, unsigned NumZero,
4696 const TargetLowering &TLI) {
4700 DebugLoc dl = Op.getDebugLoc();
4703 for (unsigned i = 0; i < 16; ++i) {
4704 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4705 if (ThisIsNonZero && First) {
4707 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4709 V = DAG.getUNDEF(MVT::v8i16);
4714 SDValue ThisElt(0, 0), LastElt(0, 0);
4715 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4716 if (LastIsNonZero) {
4717 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4718 MVT::i16, Op.getOperand(i-1));
4720 if (ThisIsNonZero) {
4721 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4722 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4723 ThisElt, DAG.getConstant(8, MVT::i8));
4725 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4729 if (ThisElt.getNode())
4730 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4731 DAG.getIntPtrConstant(i/2));
4735 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4738 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4740 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4741 unsigned NumNonZero, unsigned NumZero,
4743 const TargetLowering &TLI) {
4747 DebugLoc dl = Op.getDebugLoc();
4750 for (unsigned i = 0; i < 8; ++i) {
4751 bool isNonZero = (NonZeros & (1 << i)) != 0;
4755 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4757 V = DAG.getUNDEF(MVT::v8i16);
4760 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4761 MVT::v8i16, V, Op.getOperand(i),
4762 DAG.getIntPtrConstant(i));
4769 /// getVShift - Return a vector logical shift node.
4771 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4772 unsigned NumBits, SelectionDAG &DAG,
4773 const TargetLowering &TLI, DebugLoc dl) {
4774 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4775 EVT ShVT = MVT::v2i64;
4776 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4777 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4778 return DAG.getNode(ISD::BITCAST, dl, VT,
4779 DAG.getNode(Opc, dl, ShVT, SrcOp,
4780 DAG.getConstant(NumBits,
4781 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4785 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4786 SelectionDAG &DAG) const {
4788 // Check if the scalar load can be widened into a vector load. And if
4789 // the address is "base + cst" see if the cst can be "absorbed" into
4790 // the shuffle mask.
4791 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4792 SDValue Ptr = LD->getBasePtr();
4793 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4795 EVT PVT = LD->getValueType(0);
4796 if (PVT != MVT::i32 && PVT != MVT::f32)
4801 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4802 FI = FINode->getIndex();
4804 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4805 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4806 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4807 Offset = Ptr.getConstantOperandVal(1);
4808 Ptr = Ptr.getOperand(0);
4813 // FIXME: 256-bit vector instructions don't require a strict alignment,
4814 // improve this code to support it better.
4815 unsigned RequiredAlign = VT.getSizeInBits()/8;
4816 SDValue Chain = LD->getChain();
4817 // Make sure the stack object alignment is at least 16 or 32.
4818 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4819 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4820 if (MFI->isFixedObjectIndex(FI)) {
4821 // Can't change the alignment. FIXME: It's possible to compute
4822 // the exact stack offset and reference FI + adjust offset instead.
4823 // If someone *really* cares about this. That's the way to implement it.
4826 MFI->setObjectAlignment(FI, RequiredAlign);
4830 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4831 // Ptr + (Offset & ~15).
4834 if ((Offset % RequiredAlign) & 3)
4836 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4838 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4839 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4841 int EltNo = (Offset - StartOffset) >> 2;
4842 int NumElems = VT.getVectorNumElements();
4844 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4845 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4846 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4847 LD->getPointerInfo().getWithOffset(StartOffset),
4848 false, false, false, 0);
4850 // Canonicalize it to a v4i32 or v8i32 shuffle.
4851 SmallVector<int, 8> Mask;
4852 for (int i = 0; i < NumElems; ++i)
4853 Mask.push_back(EltNo);
4855 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4856 return DAG.getNode(ISD::BITCAST, dl, NVT,
4857 DAG.getVectorShuffle(CanonVT, dl, V1,
4858 DAG.getUNDEF(CanonVT),&Mask[0]));
4864 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4865 /// vector of type 'VT', see if the elements can be replaced by a single large
4866 /// load which has the same value as a build_vector whose operands are 'elts'.
4868 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4870 /// FIXME: we'd also like to handle the case where the last elements are zero
4871 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4872 /// There's even a handy isZeroNode for that purpose.
4873 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4874 DebugLoc &DL, SelectionDAG &DAG) {
4875 EVT EltVT = VT.getVectorElementType();
4876 unsigned NumElems = Elts.size();
4878 LoadSDNode *LDBase = NULL;
4879 unsigned LastLoadedElt = -1U;
4881 // For each element in the initializer, see if we've found a load or an undef.
4882 // If we don't find an initial load element, or later load elements are
4883 // non-consecutive, bail out.
4884 for (unsigned i = 0; i < NumElems; ++i) {
4885 SDValue Elt = Elts[i];
4887 if (!Elt.getNode() ||
4888 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4891 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4893 LDBase = cast<LoadSDNode>(Elt.getNode());
4897 if (Elt.getOpcode() == ISD::UNDEF)
4900 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4901 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4906 // If we have found an entire vector of loads and undefs, then return a large
4907 // load of the entire vector width starting at the base pointer. If we found
4908 // consecutive loads for the low half, generate a vzext_load node.
4909 if (LastLoadedElt == NumElems - 1) {
4910 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4911 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4912 LDBase->getPointerInfo(),
4913 LDBase->isVolatile(), LDBase->isNonTemporal(),
4914 LDBase->isInvariant(), 0);
4915 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4916 LDBase->getPointerInfo(),
4917 LDBase->isVolatile(), LDBase->isNonTemporal(),
4918 LDBase->isInvariant(), LDBase->getAlignment());
4919 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4920 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4921 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4922 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4924 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4925 LDBase->getPointerInfo(),
4926 LDBase->getAlignment(),
4927 false/*isVolatile*/, true/*ReadMem*/,
4929 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4934 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4935 /// a vbroadcast node. We support two patterns:
4936 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4937 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4939 /// The scalar load node is returned when a pattern is found,
4940 /// or SDValue() otherwise.
4941 static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) {
4942 EVT VT = Op.getValueType();
4945 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4946 V = V.getOperand(0);
4948 //A suspected load to be broadcasted.
4951 switch (V.getOpcode()) {
4953 // Unknown pattern found.
4956 case ISD::BUILD_VECTOR: {
4957 // The BUILD_VECTOR node must be a splat.
4958 if (!isSplatVector(V.getNode()))
4961 Ld = V.getOperand(0);
4963 // The suspected load node has several users. Make sure that all
4964 // of its users are from the BUILD_VECTOR node.
4965 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4970 case ISD::VECTOR_SHUFFLE: {
4971 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4973 // Shuffles must have a splat mask where the first element is
4975 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4978 SDValue Sc = Op.getOperand(0);
4979 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4982 Ld = Sc.getOperand(0);
4984 // The scalar_to_vector node and the suspected
4985 // load node must have exactly one user.
4986 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4992 // The scalar source must be a normal load.
4993 if (!ISD::isNormalLoad(Ld.getNode()))
4996 bool Is256 = VT.getSizeInBits() == 256;
4997 bool Is128 = VT.getSizeInBits() == 128;
4998 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5001 // VBroadcast to YMM
5002 if (Is256 && (ScalarSize == 8 || ScalarSize == 16 ||
5003 ScalarSize == 32 || ScalarSize == 64 ))
5006 // VBroadcast to XMM
5007 if (Is128 && (ScalarSize == 8 || ScalarSize == 32 ||
5008 ScalarSize == 16 || ScalarSize == 64 ))
5012 // VBroadcast to YMM
5013 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5016 // VBroadcast to XMM
5017 if (Is128 && (ScalarSize == 32))
5021 // Unsupported broadcast.
5026 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5027 DebugLoc dl = Op.getDebugLoc();
5029 EVT VT = Op.getValueType();
5030 EVT ExtVT = VT.getVectorElementType();
5031 unsigned NumElems = Op.getNumOperands();
5033 // Vectors containing all zeros can be matched by pxor and xorps later
5034 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5035 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5036 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5037 if (Op.getValueType() == MVT::v4i32 ||
5038 Op.getValueType() == MVT::v8i32)
5041 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl);
5044 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5045 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5046 // vpcmpeqd on 256-bit vectors.
5047 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5048 if (Op.getValueType() == MVT::v4i32 ||
5049 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
5052 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
5055 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
5056 if (Subtarget->hasAVX() && LD.getNode())
5057 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5059 unsigned EVTBits = ExtVT.getSizeInBits();
5061 unsigned NumZero = 0;
5062 unsigned NumNonZero = 0;
5063 unsigned NonZeros = 0;
5064 bool IsAllConstants = true;
5065 SmallSet<SDValue, 8> Values;
5066 for (unsigned i = 0; i < NumElems; ++i) {
5067 SDValue Elt = Op.getOperand(i);
5068 if (Elt.getOpcode() == ISD::UNDEF)
5071 if (Elt.getOpcode() != ISD::Constant &&
5072 Elt.getOpcode() != ISD::ConstantFP)
5073 IsAllConstants = false;
5074 if (X86::isZeroNode(Elt))
5077 NonZeros |= (1 << i);
5082 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5083 if (NumNonZero == 0)
5084 return DAG.getUNDEF(VT);
5086 // Special case for single non-zero, non-undef, element.
5087 if (NumNonZero == 1) {
5088 unsigned Idx = CountTrailingZeros_32(NonZeros);
5089 SDValue Item = Op.getOperand(Idx);
5091 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5092 // the value are obviously zero, truncate the value to i32 and do the
5093 // insertion that way. Only do this if the value is non-constant or if the
5094 // value is a constant being inserted into element 0. It is cheaper to do
5095 // a constant pool load than it is to do a movd + shuffle.
5096 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5097 (!IsAllConstants || Idx == 0)) {
5098 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5100 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5101 EVT VecVT = MVT::v4i32;
5102 unsigned VecElts = 4;
5104 // Truncate the value (which may itself be a constant) to i32, and
5105 // convert it to a vector with movd (S2V+shuffle to zero extend).
5106 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5107 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5108 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5109 Subtarget->hasXMMInt(), DAG);
5111 // Now we have our 32-bit value zero extended in the low element of
5112 // a vector. If Idx != 0, swizzle it into place.
5114 SmallVector<int, 4> Mask;
5115 Mask.push_back(Idx);
5116 for (unsigned i = 1; i != VecElts; ++i)
5118 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5119 DAG.getUNDEF(Item.getValueType()),
5122 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5126 // If we have a constant or non-constant insertion into the low element of
5127 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5128 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5129 // depending on what the source datatype is.
5132 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5133 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5134 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5135 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5136 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5137 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(),
5139 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5140 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5141 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5142 EVT MiddleVT = MVT::v4i32;
5143 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5144 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5145 Subtarget->hasXMMInt(), DAG);
5146 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5150 // Is it a vector logical left shift?
5151 if (NumElems == 2 && Idx == 1 &&
5152 X86::isZeroNode(Op.getOperand(0)) &&
5153 !X86::isZeroNode(Op.getOperand(1))) {
5154 unsigned NumBits = VT.getSizeInBits();
5155 return getVShift(true, VT,
5156 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5157 VT, Op.getOperand(1)),
5158 NumBits/2, DAG, *this, dl);
5161 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5164 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5165 // is a non-constant being inserted into an element other than the low one,
5166 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5167 // movd/movss) to move this into the low element, then shuffle it into
5169 if (EVTBits == 32) {
5170 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5172 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5173 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5174 Subtarget->hasXMMInt(), DAG);
5175 SmallVector<int, 8> MaskVec;
5176 for (unsigned i = 0; i < NumElems; i++)
5177 MaskVec.push_back(i == Idx ? 0 : 1);
5178 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5182 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5183 if (Values.size() == 1) {
5184 if (EVTBits == 32) {
5185 // Instead of a shuffle like this:
5186 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5187 // Check if it's possible to issue this instead.
5188 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5189 unsigned Idx = CountTrailingZeros_32(NonZeros);
5190 SDValue Item = Op.getOperand(Idx);
5191 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5192 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5197 // A vector full of immediates; various special cases are already
5198 // handled, so this is best done with a single constant-pool load.
5202 // For AVX-length vectors, build the individual 128-bit pieces and use
5203 // shuffles to put them in place.
5204 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5205 SmallVector<SDValue, 32> V;
5206 for (unsigned i = 0; i < NumElems; ++i)
5207 V.push_back(Op.getOperand(i));
5209 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5211 // Build both the lower and upper subvector.
5212 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5213 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5216 // Recreate the wider vector with the lower and upper part.
5217 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5218 DAG.getConstant(0, MVT::i32), DAG, dl);
5219 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5223 // Let legalizer expand 2-wide build_vectors.
5224 if (EVTBits == 64) {
5225 if (NumNonZero == 1) {
5226 // One half is zero or undef.
5227 unsigned Idx = CountTrailingZeros_32(NonZeros);
5228 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5229 Op.getOperand(Idx));
5230 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5231 Subtarget->hasXMMInt(), DAG);
5236 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5237 if (EVTBits == 8 && NumElems == 16) {
5238 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5240 if (V.getNode()) return V;
5243 if (EVTBits == 16 && NumElems == 8) {
5244 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5246 if (V.getNode()) return V;
5249 // If element VT is == 32 bits, turn it into a number of shuffles.
5250 SmallVector<SDValue, 8> V;
5252 if (NumElems == 4 && NumZero > 0) {
5253 for (unsigned i = 0; i < 4; ++i) {
5254 bool isZero = !(NonZeros & (1 << i));
5256 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
5258 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5261 for (unsigned i = 0; i < 2; ++i) {
5262 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5265 V[i] = V[i*2]; // Must be a zero vector.
5268 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5271 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5274 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5279 SmallVector<int, 8> MaskVec;
5280 bool Reverse = (NonZeros & 0x3) == 2;
5281 for (unsigned i = 0; i < 2; ++i)
5282 MaskVec.push_back(Reverse ? 1-i : i);
5283 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5284 for (unsigned i = 0; i < 2; ++i)
5285 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5286 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5289 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5290 // Check for a build vector of consecutive loads.
5291 for (unsigned i = 0; i < NumElems; ++i)
5292 V[i] = Op.getOperand(i);
5294 // Check for elements which are consecutive loads.
5295 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5299 // For SSE 4.1, use insertps to put the high elements into the low element.
5300 if (getSubtarget()->hasSSE41orAVX()) {
5302 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5303 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5305 Result = DAG.getUNDEF(VT);
5307 for (unsigned i = 1; i < NumElems; ++i) {
5308 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5309 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5310 Op.getOperand(i), DAG.getIntPtrConstant(i));
5315 // Otherwise, expand into a number of unpckl*, start by extending each of
5316 // our (non-undef) elements to the full vector width with the element in the
5317 // bottom slot of the vector (which generates no code for SSE).
5318 for (unsigned i = 0; i < NumElems; ++i) {
5319 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5320 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5322 V[i] = DAG.getUNDEF(VT);
5325 // Next, we iteratively mix elements, e.g. for v4f32:
5326 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5327 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5328 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5329 unsigned EltStride = NumElems >> 1;
5330 while (EltStride != 0) {
5331 for (unsigned i = 0; i < EltStride; ++i) {
5332 // If V[i+EltStride] is undef and this is the first round of mixing,
5333 // then it is safe to just drop this shuffle: V[i] is already in the
5334 // right place, the one element (since it's the first round) being
5335 // inserted as undef can be dropped. This isn't safe for successive
5336 // rounds because they will permute elements within both vectors.
5337 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5338 EltStride == NumElems/2)
5341 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5350 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5351 // them in a MMX register. This is better than doing a stack convert.
5352 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5353 DebugLoc dl = Op.getDebugLoc();
5354 EVT ResVT = Op.getValueType();
5356 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5357 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5359 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5360 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5361 InVec = Op.getOperand(1);
5362 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5363 unsigned NumElts = ResVT.getVectorNumElements();
5364 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5365 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5366 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5368 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5369 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5370 Mask[0] = 0; Mask[1] = 2;
5371 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5373 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5376 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5377 // to create 256-bit vectors from two other 128-bit ones.
5378 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5379 DebugLoc dl = Op.getDebugLoc();
5380 EVT ResVT = Op.getValueType();
5382 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5384 SDValue V1 = Op.getOperand(0);
5385 SDValue V2 = Op.getOperand(1);
5386 unsigned NumElems = ResVT.getVectorNumElements();
5388 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5389 DAG.getConstant(0, MVT::i32), DAG, dl);
5390 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5395 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5396 EVT ResVT = Op.getValueType();
5398 assert(Op.getNumOperands() == 2);
5399 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5400 "Unsupported CONCAT_VECTORS for value type");
5402 // We support concatenate two MMX registers and place them in a MMX register.
5403 // This is better than doing a stack convert.
5404 if (ResVT.is128BitVector())
5405 return LowerMMXCONCAT_VECTORS(Op, DAG);
5407 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5408 // from two other 128-bit ones.
5409 return LowerAVXCONCAT_VECTORS(Op, DAG);
5412 // v8i16 shuffles - Prefer shuffles in the following order:
5413 // 1. [all] pshuflw, pshufhw, optional move
5414 // 2. [ssse3] 1 x pshufb
5415 // 3. [ssse3] 2 x pshufb + 1 x por
5416 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5418 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5419 SelectionDAG &DAG) const {
5420 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5421 SDValue V1 = SVOp->getOperand(0);
5422 SDValue V2 = SVOp->getOperand(1);
5423 DebugLoc dl = SVOp->getDebugLoc();
5424 SmallVector<int, 8> MaskVals;
5426 // Determine if more than 1 of the words in each of the low and high quadwords
5427 // of the result come from the same quadword of one of the two inputs. Undef
5428 // mask values count as coming from any quadword, for better codegen.
5429 unsigned LoQuad[] = { 0, 0, 0, 0 };
5430 unsigned HiQuad[] = { 0, 0, 0, 0 };
5431 BitVector InputQuads(4);
5432 for (unsigned i = 0; i < 8; ++i) {
5433 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5434 int EltIdx = SVOp->getMaskElt(i);
5435 MaskVals.push_back(EltIdx);
5444 InputQuads.set(EltIdx / 4);
5447 int BestLoQuad = -1;
5448 unsigned MaxQuad = 1;
5449 for (unsigned i = 0; i < 4; ++i) {
5450 if (LoQuad[i] > MaxQuad) {
5452 MaxQuad = LoQuad[i];
5456 int BestHiQuad = -1;
5458 for (unsigned i = 0; i < 4; ++i) {
5459 if (HiQuad[i] > MaxQuad) {
5461 MaxQuad = HiQuad[i];
5465 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5466 // of the two input vectors, shuffle them into one input vector so only a
5467 // single pshufb instruction is necessary. If There are more than 2 input
5468 // quads, disable the next transformation since it does not help SSSE3.
5469 bool V1Used = InputQuads[0] || InputQuads[1];
5470 bool V2Used = InputQuads[2] || InputQuads[3];
5471 if (Subtarget->hasSSSE3orAVX()) {
5472 if (InputQuads.count() == 2 && V1Used && V2Used) {
5473 BestLoQuad = InputQuads.find_first();
5474 BestHiQuad = InputQuads.find_next(BestLoQuad);
5476 if (InputQuads.count() > 2) {
5482 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5483 // the shuffle mask. If a quad is scored as -1, that means that it contains
5484 // words from all 4 input quadwords.
5486 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5487 SmallVector<int, 8> MaskV;
5488 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5489 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5490 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5491 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5492 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5493 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5495 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5496 // source words for the shuffle, to aid later transformations.
5497 bool AllWordsInNewV = true;
5498 bool InOrder[2] = { true, true };
5499 for (unsigned i = 0; i != 8; ++i) {
5500 int idx = MaskVals[i];
5502 InOrder[i/4] = false;
5503 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5505 AllWordsInNewV = false;
5509 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5510 if (AllWordsInNewV) {
5511 for (int i = 0; i != 8; ++i) {
5512 int idx = MaskVals[i];
5515 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5516 if ((idx != i) && idx < 4)
5518 if ((idx != i) && idx > 3)
5527 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5528 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5529 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5530 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5531 unsigned TargetMask = 0;
5532 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5533 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5534 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5535 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5536 V1 = NewV.getOperand(0);
5537 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5541 // If we have SSSE3, and all words of the result are from 1 input vector,
5542 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5543 // is present, fall back to case 4.
5544 if (Subtarget->hasSSSE3orAVX()) {
5545 SmallVector<SDValue,16> pshufbMask;
5547 // If we have elements from both input vectors, set the high bit of the
5548 // shuffle mask element to zero out elements that come from V2 in the V1
5549 // mask, and elements that come from V1 in the V2 mask, so that the two
5550 // results can be OR'd together.
5551 bool TwoInputs = V1Used && V2Used;
5552 for (unsigned i = 0; i != 8; ++i) {
5553 int EltIdx = MaskVals[i] * 2;
5554 if (TwoInputs && (EltIdx >= 16)) {
5555 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5556 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5559 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5560 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5562 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5563 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5564 DAG.getNode(ISD::BUILD_VECTOR, dl,
5565 MVT::v16i8, &pshufbMask[0], 16));
5567 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5569 // Calculate the shuffle mask for the second input, shuffle it, and
5570 // OR it with the first shuffled input.
5572 for (unsigned i = 0; i != 8; ++i) {
5573 int EltIdx = MaskVals[i] * 2;
5575 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5576 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5579 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5580 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5582 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5583 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5584 DAG.getNode(ISD::BUILD_VECTOR, dl,
5585 MVT::v16i8, &pshufbMask[0], 16));
5586 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5587 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5590 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5591 // and update MaskVals with new element order.
5592 BitVector InOrder(8);
5593 if (BestLoQuad >= 0) {
5594 SmallVector<int, 8> MaskV;
5595 for (int i = 0; i != 4; ++i) {
5596 int idx = MaskVals[i];
5598 MaskV.push_back(-1);
5600 } else if ((idx / 4) == BestLoQuad) {
5601 MaskV.push_back(idx & 3);
5604 MaskV.push_back(-1);
5607 for (unsigned i = 4; i != 8; ++i)
5609 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5612 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5613 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5615 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5619 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5620 // and update MaskVals with the new element order.
5621 if (BestHiQuad >= 0) {
5622 SmallVector<int, 8> MaskV;
5623 for (unsigned i = 0; i != 4; ++i)
5625 for (unsigned i = 4; i != 8; ++i) {
5626 int idx = MaskVals[i];
5628 MaskV.push_back(-1);
5630 } else if ((idx / 4) == BestHiQuad) {
5631 MaskV.push_back((idx & 3) + 4);
5634 MaskV.push_back(-1);
5637 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5640 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5641 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5643 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5647 // In case BestHi & BestLo were both -1, which means each quadword has a word
5648 // from each of the four input quadwords, calculate the InOrder bitvector now
5649 // before falling through to the insert/extract cleanup.
5650 if (BestLoQuad == -1 && BestHiQuad == -1) {
5652 for (int i = 0; i != 8; ++i)
5653 if (MaskVals[i] < 0 || MaskVals[i] == i)
5657 // The other elements are put in the right place using pextrw and pinsrw.
5658 for (unsigned i = 0; i != 8; ++i) {
5661 int EltIdx = MaskVals[i];
5664 SDValue ExtOp = (EltIdx < 8)
5665 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5666 DAG.getIntPtrConstant(EltIdx))
5667 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5668 DAG.getIntPtrConstant(EltIdx - 8));
5669 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5670 DAG.getIntPtrConstant(i));
5675 // v16i8 shuffles - Prefer shuffles in the following order:
5676 // 1. [ssse3] 1 x pshufb
5677 // 2. [ssse3] 2 x pshufb + 1 x por
5678 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5680 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5682 const X86TargetLowering &TLI) {
5683 SDValue V1 = SVOp->getOperand(0);
5684 SDValue V2 = SVOp->getOperand(1);
5685 DebugLoc dl = SVOp->getDebugLoc();
5686 SmallVector<int, 16> MaskVals;
5687 SVOp->getMask(MaskVals);
5689 // If we have SSSE3, case 1 is generated when all result bytes come from
5690 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5691 // present, fall back to case 3.
5692 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5695 for (unsigned i = 0; i < 16; ++i) {
5696 int EltIdx = MaskVals[i];
5705 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5706 if (TLI.getSubtarget()->hasSSSE3orAVX()) {
5707 SmallVector<SDValue,16> pshufbMask;
5709 // If all result elements are from one input vector, then only translate
5710 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5712 // Otherwise, we have elements from both input vectors, and must zero out
5713 // elements that come from V2 in the first mask, and V1 in the second mask
5714 // so that we can OR them together.
5715 bool TwoInputs = !(V1Only || V2Only);
5716 for (unsigned i = 0; i != 16; ++i) {
5717 int EltIdx = MaskVals[i];
5718 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5719 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5722 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5724 // If all the elements are from V2, assign it to V1 and return after
5725 // building the first pshufb.
5728 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5729 DAG.getNode(ISD::BUILD_VECTOR, dl,
5730 MVT::v16i8, &pshufbMask[0], 16));
5734 // Calculate the shuffle mask for the second input, shuffle it, and
5735 // OR it with the first shuffled input.
5737 for (unsigned i = 0; i != 16; ++i) {
5738 int EltIdx = MaskVals[i];
5740 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5743 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5745 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5746 DAG.getNode(ISD::BUILD_VECTOR, dl,
5747 MVT::v16i8, &pshufbMask[0], 16));
5748 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5751 // No SSSE3 - Calculate in place words and then fix all out of place words
5752 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5753 // the 16 different words that comprise the two doublequadword input vectors.
5754 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5755 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5756 SDValue NewV = V2Only ? V2 : V1;
5757 for (int i = 0; i != 8; ++i) {
5758 int Elt0 = MaskVals[i*2];
5759 int Elt1 = MaskVals[i*2+1];
5761 // This word of the result is all undef, skip it.
5762 if (Elt0 < 0 && Elt1 < 0)
5765 // This word of the result is already in the correct place, skip it.
5766 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5768 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5771 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5772 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5775 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5776 // using a single extract together, load it and store it.
5777 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5778 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5779 DAG.getIntPtrConstant(Elt1 / 2));
5780 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5781 DAG.getIntPtrConstant(i));
5785 // If Elt1 is defined, extract it from the appropriate source. If the
5786 // source byte is not also odd, shift the extracted word left 8 bits
5787 // otherwise clear the bottom 8 bits if we need to do an or.
5789 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5790 DAG.getIntPtrConstant(Elt1 / 2));
5791 if ((Elt1 & 1) == 0)
5792 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5794 TLI.getShiftAmountTy(InsElt.getValueType())));
5796 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5797 DAG.getConstant(0xFF00, MVT::i16));
5799 // If Elt0 is defined, extract it from the appropriate source. If the
5800 // source byte is not also even, shift the extracted word right 8 bits. If
5801 // Elt1 was also defined, OR the extracted values together before
5802 // inserting them in the result.
5804 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5805 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5806 if ((Elt0 & 1) != 0)
5807 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5809 TLI.getShiftAmountTy(InsElt0.getValueType())));
5811 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5812 DAG.getConstant(0x00FF, MVT::i16));
5813 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5816 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5817 DAG.getIntPtrConstant(i));
5819 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5822 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5823 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5824 /// done when every pair / quad of shuffle mask elements point to elements in
5825 /// the right sequence. e.g.
5826 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5828 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5829 SelectionDAG &DAG, DebugLoc dl) {
5830 EVT VT = SVOp->getValueType(0);
5831 SDValue V1 = SVOp->getOperand(0);
5832 SDValue V2 = SVOp->getOperand(1);
5833 unsigned NumElems = VT.getVectorNumElements();
5834 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5836 switch (VT.getSimpleVT().SimpleTy) {
5837 default: assert(false && "Unexpected!");
5838 case MVT::v4f32: NewVT = MVT::v2f64; break;
5839 case MVT::v4i32: NewVT = MVT::v2i64; break;
5840 case MVT::v8i16: NewVT = MVT::v4i32; break;
5841 case MVT::v16i8: NewVT = MVT::v4i32; break;
5844 int Scale = NumElems / NewWidth;
5845 SmallVector<int, 8> MaskVec;
5846 for (unsigned i = 0; i < NumElems; i += Scale) {
5848 for (int j = 0; j < Scale; ++j) {
5849 int EltIdx = SVOp->getMaskElt(i+j);
5853 StartIdx = EltIdx - (EltIdx % Scale);
5854 if (EltIdx != StartIdx + j)
5858 MaskVec.push_back(-1);
5860 MaskVec.push_back(StartIdx / Scale);
5863 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5864 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5865 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5868 /// getVZextMovL - Return a zero-extending vector move low node.
5870 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5871 SDValue SrcOp, SelectionDAG &DAG,
5872 const X86Subtarget *Subtarget, DebugLoc dl) {
5873 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5874 LoadSDNode *LD = NULL;
5875 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5876 LD = dyn_cast<LoadSDNode>(SrcOp);
5878 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5880 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5881 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5882 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5883 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5884 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5886 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5887 return DAG.getNode(ISD::BITCAST, dl, VT,
5888 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5889 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5897 return DAG.getNode(ISD::BITCAST, dl, VT,
5898 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5899 DAG.getNode(ISD::BITCAST, dl,
5903 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5904 /// shuffle node referes to only one lane in the sources.
5905 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5906 EVT VT = SVOp->getValueType(0);
5907 int NumElems = VT.getVectorNumElements();
5908 int HalfSize = NumElems/2;
5909 SmallVector<int, 16> M;
5911 bool MatchA = false, MatchB = false;
5913 for (int l = 0; l < NumElems*2; l += HalfSize) {
5914 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5920 for (int l = 0; l < NumElems*2; l += HalfSize) {
5921 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5927 return MatchA && MatchB;
5930 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5931 /// which could not be matched by any known target speficic shuffle
5933 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5934 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5935 // If each half of a vector shuffle node referes to only one lane in the
5936 // source vectors, extract each used 128-bit lane and shuffle them using
5937 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5938 // the work to the legalizer.
5939 DebugLoc dl = SVOp->getDebugLoc();
5940 EVT VT = SVOp->getValueType(0);
5941 int NumElems = VT.getVectorNumElements();
5942 int HalfSize = NumElems/2;
5944 // Extract the reference for each half
5945 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5946 int FstVecOpNum = 0, SndVecOpNum = 0;
5947 for (int i = 0; i < HalfSize; ++i) {
5948 int Elt = SVOp->getMaskElt(i);
5949 if (SVOp->getMaskElt(i) < 0)
5951 FstVecOpNum = Elt/NumElems;
5952 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5955 for (int i = HalfSize; i < NumElems; ++i) {
5956 int Elt = SVOp->getMaskElt(i);
5957 if (SVOp->getMaskElt(i) < 0)
5959 SndVecOpNum = Elt/NumElems;
5960 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5964 // Extract the subvectors
5965 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5966 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5967 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5968 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5970 // Generate 128-bit shuffles
5971 SmallVector<int, 16> MaskV1, MaskV2;
5972 for (int i = 0; i < HalfSize; ++i) {
5973 int Elt = SVOp->getMaskElt(i);
5974 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5976 for (int i = HalfSize; i < NumElems; ++i) {
5977 int Elt = SVOp->getMaskElt(i);
5978 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5981 EVT NVT = V1.getValueType();
5982 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5983 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5985 // Concatenate the result back
5986 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5987 DAG.getConstant(0, MVT::i32), DAG, dl);
5988 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5995 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5996 /// 4 elements, and match them with several different shuffle types.
5998 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5999 SDValue V1 = SVOp->getOperand(0);
6000 SDValue V2 = SVOp->getOperand(1);
6001 DebugLoc dl = SVOp->getDebugLoc();
6002 EVT VT = SVOp->getValueType(0);
6004 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6006 SmallVector<std::pair<int, int>, 8> Locs;
6008 SmallVector<int, 8> Mask1(4U, -1);
6009 SmallVector<int, 8> PermMask;
6010 SVOp->getMask(PermMask);
6014 for (unsigned i = 0; i != 4; ++i) {
6015 int Idx = PermMask[i];
6017 Locs[i] = std::make_pair(-1, -1);
6019 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6021 Locs[i] = std::make_pair(0, NumLo);
6025 Locs[i] = std::make_pair(1, NumHi);
6027 Mask1[2+NumHi] = Idx;
6033 if (NumLo <= 2 && NumHi <= 2) {
6034 // If no more than two elements come from either vector. This can be
6035 // implemented with two shuffles. First shuffle gather the elements.
6036 // The second shuffle, which takes the first shuffle as both of its
6037 // vector operands, put the elements into the right order.
6038 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6040 SmallVector<int, 8> Mask2(4U, -1);
6042 for (unsigned i = 0; i != 4; ++i) {
6043 if (Locs[i].first == -1)
6046 unsigned Idx = (i < 2) ? 0 : 4;
6047 Idx += Locs[i].first * 2 + Locs[i].second;
6052 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6053 } else if (NumLo == 3 || NumHi == 3) {
6054 // Otherwise, we must have three elements from one vector, call it X, and
6055 // one element from the other, call it Y. First, use a shufps to build an
6056 // intermediate vector with the one element from Y and the element from X
6057 // that will be in the same half in the final destination (the indexes don't
6058 // matter). Then, use a shufps to build the final vector, taking the half
6059 // containing the element from Y from the intermediate, and the other half
6062 // Normalize it so the 3 elements come from V1.
6063 CommuteVectorShuffleMask(PermMask, 4);
6067 // Find the element from V2.
6069 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6070 int Val = PermMask[HiIndex];
6077 Mask1[0] = PermMask[HiIndex];
6079 Mask1[2] = PermMask[HiIndex^1];
6081 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6084 Mask1[0] = PermMask[0];
6085 Mask1[1] = PermMask[1];
6086 Mask1[2] = HiIndex & 1 ? 6 : 4;
6087 Mask1[3] = HiIndex & 1 ? 4 : 6;
6088 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6090 Mask1[0] = HiIndex & 1 ? 2 : 0;
6091 Mask1[1] = HiIndex & 1 ? 0 : 2;
6092 Mask1[2] = PermMask[2];
6093 Mask1[3] = PermMask[3];
6098 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6102 // Break it into (shuffle shuffle_hi, shuffle_lo).
6105 SmallVector<int,8> LoMask(4U, -1);
6106 SmallVector<int,8> HiMask(4U, -1);
6108 SmallVector<int,8> *MaskPtr = &LoMask;
6109 unsigned MaskIdx = 0;
6112 for (unsigned i = 0; i != 4; ++i) {
6119 int Idx = PermMask[i];
6121 Locs[i] = std::make_pair(-1, -1);
6122 } else if (Idx < 4) {
6123 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6124 (*MaskPtr)[LoIdx] = Idx;
6127 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6128 (*MaskPtr)[HiIdx] = Idx;
6133 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6134 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6135 SmallVector<int, 8> MaskOps;
6136 for (unsigned i = 0; i != 4; ++i) {
6137 if (Locs[i].first == -1) {
6138 MaskOps.push_back(-1);
6140 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6141 MaskOps.push_back(Idx);
6144 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6147 static bool MayFoldVectorLoad(SDValue V) {
6148 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6149 V = V.getOperand(0);
6150 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6151 V = V.getOperand(0);
6152 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6153 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6154 // BUILD_VECTOR (load), undef
6155 V = V.getOperand(0);
6161 // FIXME: the version above should always be used. Since there's
6162 // a bug where several vector shuffles can't be folded because the
6163 // DAG is not updated during lowering and a node claims to have two
6164 // uses while it only has one, use this version, and let isel match
6165 // another instruction if the load really happens to have more than
6166 // one use. Remove this version after this bug get fixed.
6167 // rdar://8434668, PR8156
6168 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6169 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6170 V = V.getOperand(0);
6171 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6172 V = V.getOperand(0);
6173 if (ISD::isNormalLoad(V.getNode()))
6178 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6179 /// a vector extract, and if both can be later optimized into a single load.
6180 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6181 /// here because otherwise a target specific shuffle node is going to be
6182 /// emitted for this shuffle, and the optimization not done.
6183 /// FIXME: This is probably not the best approach, but fix the problem
6184 /// until the right path is decided.
6186 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6187 const TargetLowering &TLI) {
6188 EVT VT = V.getValueType();
6189 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6191 // Be sure that the vector shuffle is present in a pattern like this:
6192 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6196 SDNode *N = *V.getNode()->use_begin();
6197 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6200 SDValue EltNo = N->getOperand(1);
6201 if (!isa<ConstantSDNode>(EltNo))
6204 // If the bit convert changed the number of elements, it is unsafe
6205 // to examine the mask.
6206 bool HasShuffleIntoBitcast = false;
6207 if (V.getOpcode() == ISD::BITCAST) {
6208 EVT SrcVT = V.getOperand(0).getValueType();
6209 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6211 V = V.getOperand(0);
6212 HasShuffleIntoBitcast = true;
6215 // Select the input vector, guarding against out of range extract vector.
6216 unsigned NumElems = VT.getVectorNumElements();
6217 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6218 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6219 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6221 // Skip one more bit_convert if necessary
6222 if (V.getOpcode() == ISD::BITCAST)
6223 V = V.getOperand(0);
6225 if (ISD::isNormalLoad(V.getNode())) {
6226 // Is the original load suitable?
6227 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6229 // FIXME: avoid the multi-use bug that is preventing lots of
6230 // of foldings to be detected, this is still wrong of course, but
6231 // give the temporary desired behavior, and if it happens that
6232 // the load has real more uses, during isel it will not fold, and
6233 // will generate poor code.
6234 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6237 if (!HasShuffleIntoBitcast)
6240 // If there's a bitcast before the shuffle, check if the load type and
6241 // alignment is valid.
6242 unsigned Align = LN0->getAlignment();
6244 TLI.getTargetData()->getABITypeAlignment(
6245 VT.getTypeForEVT(*DAG.getContext()));
6247 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6255 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6256 EVT VT = Op.getValueType();
6258 // Canonizalize to v2f64.
6259 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6260 return DAG.getNode(ISD::BITCAST, dl, VT,
6261 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6266 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6268 SDValue V1 = Op.getOperand(0);
6269 SDValue V2 = Op.getOperand(1);
6270 EVT VT = Op.getValueType();
6272 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6274 if (HasXMMInt && VT == MVT::v2f64)
6275 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6277 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6278 return DAG.getNode(ISD::BITCAST, dl, VT,
6279 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6280 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6281 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6285 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6286 SDValue V1 = Op.getOperand(0);
6287 SDValue V2 = Op.getOperand(1);
6288 EVT VT = Op.getValueType();
6290 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6291 "unsupported shuffle type");
6293 if (V2.getOpcode() == ISD::UNDEF)
6297 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6300 static inline unsigned getSHUFPOpcode(EVT VT) {
6301 switch(VT.getSimpleVT().SimpleTy) {
6302 case MVT::v8i32: // Use fp unit for int unpack.
6304 case MVT::v4i32: // Use fp unit for int unpack.
6305 case MVT::v4f32: return X86ISD::SHUFPS;
6306 case MVT::v4i64: // Use fp unit for int unpack.
6308 case MVT::v2i64: // Use fp unit for int unpack.
6309 case MVT::v2f64: return X86ISD::SHUFPD;
6311 llvm_unreachable("Unknown type for shufp*");
6317 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) {
6318 SDValue V1 = Op.getOperand(0);
6319 SDValue V2 = Op.getOperand(1);
6320 EVT VT = Op.getValueType();
6321 unsigned NumElems = VT.getVectorNumElements();
6323 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6324 // operand of these instructions is only memory, so check if there's a
6325 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6327 bool CanFoldLoad = false;
6329 // Trivial case, when V2 comes from a load.
6330 if (MayFoldVectorLoad(V2))
6333 // When V1 is a load, it can be folded later into a store in isel, example:
6334 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6336 // (MOVLPSmr addr:$src1, VR128:$src2)
6337 // So, recognize this potential and also use MOVLPS or MOVLPD
6338 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6341 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6343 if (HasXMMInt && NumElems == 2)
6344 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6347 // If we don't care about the second element, procede to use movss.
6348 if (SVOp->getMaskElt(1) != -1)
6349 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6352 // movl and movlp will both match v2i64, but v2i64 is never matched by
6353 // movl earlier because we make it strict to avoid messing with the movlp load
6354 // folding logic (see the code above getMOVLP call). Match it here then,
6355 // this is horrible, but will stay like this until we move all shuffle
6356 // matching to x86 specific nodes. Note that for the 1st condition all
6357 // types are matched with movsd.
6359 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6360 // as to remove this logic from here, as much as possible
6361 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6362 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6363 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6366 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6368 // Invert the operand order and use SHUFPS to match it.
6369 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6370 X86::getShuffleSHUFImmediate(SVOp), DAG);
6374 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6375 const TargetLowering &TLI,
6376 const X86Subtarget *Subtarget) {
6377 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6378 EVT VT = Op.getValueType();
6379 DebugLoc dl = Op.getDebugLoc();
6380 SDValue V1 = Op.getOperand(0);
6381 SDValue V2 = Op.getOperand(1);
6383 if (isZeroShuffle(SVOp))
6384 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
6386 // Handle splat operations
6387 if (SVOp->isSplat()) {
6388 unsigned NumElem = VT.getVectorNumElements();
6389 int Size = VT.getSizeInBits();
6390 // Special case, this is the only place now where it's allowed to return
6391 // a vector_shuffle operation without using a target specific node, because
6392 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6393 // this be moved to DAGCombine instead?
6394 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6397 // Use vbroadcast whenever the splat comes from a foldable load
6398 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
6399 if (Subtarget->hasAVX() && LD.getNode())
6400 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6402 // Handle splats by matching through known shuffle masks
6403 if ((Size == 128 && NumElem <= 4) ||
6404 (Size == 256 && NumElem < 8))
6407 // All remaning splats are promoted to target supported vector shuffles.
6408 return PromoteSplat(SVOp, DAG);
6411 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6413 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6414 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6415 if (NewOp.getNode())
6416 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6417 } else if ((VT == MVT::v4i32 ||
6418 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) {
6419 // FIXME: Figure out a cleaner way to do this.
6420 // Try to make use of movq to zero out the top part.
6421 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6422 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6423 if (NewOp.getNode()) {
6424 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6425 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6426 DAG, Subtarget, dl);
6428 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6429 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6430 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6431 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6432 DAG, Subtarget, dl);
6439 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6440 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6441 SDValue V1 = Op.getOperand(0);
6442 SDValue V2 = Op.getOperand(1);
6443 EVT VT = Op.getValueType();
6444 DebugLoc dl = Op.getDebugLoc();
6445 unsigned NumElems = VT.getVectorNumElements();
6446 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6447 bool V1IsSplat = false;
6448 bool V2IsSplat = false;
6449 bool HasXMMInt = Subtarget->hasXMMInt();
6450 bool HasAVX = Subtarget->hasAVX();
6451 bool HasAVX2 = Subtarget->hasAVX2();
6452 MachineFunction &MF = DAG.getMachineFunction();
6453 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6455 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6457 assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef");
6459 // Vector shuffle lowering takes 3 steps:
6461 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6462 // narrowing and commutation of operands should be handled.
6463 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6465 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6466 // so the shuffle can be broken into other shuffles and the legalizer can
6467 // try the lowering again.
6469 // The general idea is that no vector_shuffle operation should be left to
6470 // be matched during isel, all of them must be converted to a target specific
6473 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6474 // narrowing and commutation of operands should be handled. The actual code
6475 // doesn't include all of those, work in progress...
6476 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6477 if (NewOp.getNode())
6480 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6481 // unpckh_undef). Only use pshufd if speed is more important than size.
6482 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6483 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6484 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6485 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6487 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() &&
6488 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6489 return getMOVDDup(Op, dl, V1, DAG);
6491 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6492 return getMOVHighToLow(Op, dl, DAG);
6494 // Use to match splats
6495 if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6496 (VT == MVT::v2f64 || VT == MVT::v2i64))
6497 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6499 if (X86::isPSHUFDMask(SVOp)) {
6500 // The actual implementation will match the mask in the if above and then
6501 // during isel it can match several different instructions, not only pshufd
6502 // as its name says, sad but true, emulate the behavior for now...
6503 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6504 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6506 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6508 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32))
6509 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6511 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6515 // Check if this can be converted into a logical shift.
6516 bool isLeft = false;
6519 bool isShift = HasXMMInt && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6520 if (isShift && ShVal.hasOneUse()) {
6521 // If the shifted value has multiple uses, it may be cheaper to use
6522 // v_set0 + movlhps or movhlps, etc.
6523 EVT EltVT = VT.getVectorElementType();
6524 ShAmt *= EltVT.getSizeInBits();
6525 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6528 if (X86::isMOVLMask(SVOp)) {
6529 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6530 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6531 if (!X86::isMOVLPMask(SVOp)) {
6532 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64))
6533 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6535 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6536 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6540 // FIXME: fold these into legal mask.
6541 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6542 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt);
6544 if (X86::isMOVHLPSMask(SVOp))
6545 return getMOVHighToLow(Op, dl, DAG);
6547 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6548 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6550 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6551 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6553 if (X86::isMOVLPMask(SVOp))
6554 return getMOVLP(Op, dl, DAG, HasXMMInt);
6556 if (ShouldXformToMOVHLPS(SVOp) ||
6557 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6558 return CommuteVectorShuffle(SVOp, DAG);
6561 // No better options. Use a vshl / vsrl.
6562 EVT EltVT = VT.getVectorElementType();
6563 ShAmt *= EltVT.getSizeInBits();
6564 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6567 bool Commuted = false;
6568 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6569 // 1,1,1,1 -> v8i16 though.
6570 V1IsSplat = isSplatVector(V1.getNode());
6571 V2IsSplat = isSplatVector(V2.getNode());
6573 // Canonicalize the splat or undef, if present, to be on the RHS.
6574 if (V1IsSplat && !V2IsSplat) {
6575 Op = CommuteVectorShuffle(SVOp, DAG);
6576 SVOp = cast<ShuffleVectorSDNode>(Op);
6577 V1 = SVOp->getOperand(0);
6578 V2 = SVOp->getOperand(1);
6579 std::swap(V1IsSplat, V2IsSplat);
6583 SmallVector<int, 32> M;
6586 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6587 // Shuffling low element of v1 into undef, just return v1.
6590 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6591 // the instruction selector will not match, so get a canonical MOVL with
6592 // swapped operands to undo the commute.
6593 return getMOVL(DAG, dl, VT, V2, V1);
6596 if (isUNPCKLMask(M, VT, HasAVX2))
6597 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6599 if (isUNPCKHMask(M, VT, HasAVX2))
6600 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6603 // Normalize mask so all entries that point to V2 points to its first
6604 // element then try to match unpck{h|l} again. If match, return a
6605 // new vector_shuffle with the corrected mask.
6606 SDValue NewMask = NormalizeMask(SVOp, DAG);
6607 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6608 if (NSVOp != SVOp) {
6609 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6611 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6618 // Commute is back and try unpck* again.
6619 // FIXME: this seems wrong.
6620 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6621 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6623 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6624 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6626 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6627 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6630 // Normalize the node to match x86 shuffle ops if needed
6631 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) ||
6632 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true)))
6633 return CommuteVectorShuffle(SVOp, DAG);
6635 // The checks below are all present in isShuffleMaskLegal, but they are
6636 // inlined here right now to enable us to directly emit target specific
6637 // nodes, and remove one by one until they don't return Op anymore.
6639 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()))
6640 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6641 getShufflePALIGNRImmediate(SVOp),
6644 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6645 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6646 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6647 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6650 if (isPSHUFHWMask(M, VT))
6651 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6652 X86::getShufflePSHUFHWImmediate(SVOp),
6655 if (isPSHUFLWMask(M, VT))
6656 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6657 X86::getShufflePSHUFLWImmediate(SVOp),
6660 if (isSHUFPMask(M, VT))
6661 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6662 X86::getShuffleSHUFImmediate(SVOp), DAG);
6664 if (isUNPCKL_v_undef_Mask(M, VT))
6665 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6666 if (isUNPCKH_v_undef_Mask(M, VT))
6667 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6669 //===--------------------------------------------------------------------===//
6670 // Generate target specific nodes for 128 or 256-bit shuffles only
6671 // supported in the AVX instruction set.
6674 // Handle VMOVDDUPY permutations
6675 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6676 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6678 // Handle VPERMILPS/D* permutations
6679 if (isVPERMILPMask(M, VT, HasAVX))
6680 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6681 getShuffleVPERMILPImmediate(SVOp), DAG);
6683 // Handle VPERM2F128/VPERM2I128 permutations
6684 if (isVPERM2X128Mask(M, VT, HasAVX))
6685 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6686 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6688 // Handle VSHUFPS/DY permutations
6689 if (isVSHUFPYMask(M, VT, HasAVX))
6690 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6691 getShuffleVSHUFPYImmediate(SVOp), DAG);
6693 //===--------------------------------------------------------------------===//
6694 // Since no target specific shuffle was selected for this generic one,
6695 // lower it into other known shuffles. FIXME: this isn't true yet, but
6696 // this is the plan.
6699 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6700 if (VT == MVT::v8i16) {
6701 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6702 if (NewOp.getNode())
6706 if (VT == MVT::v16i8) {
6707 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6708 if (NewOp.getNode())
6712 // Handle all 128-bit wide vectors with 4 elements, and match them with
6713 // several different shuffle types.
6714 if (NumElems == 4 && VT.getSizeInBits() == 128)
6715 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6717 // Handle general 256-bit shuffles
6718 if (VT.is256BitVector())
6719 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6725 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6726 SelectionDAG &DAG) const {
6727 EVT VT = Op.getValueType();
6728 DebugLoc dl = Op.getDebugLoc();
6730 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6733 if (VT.getSizeInBits() == 8) {
6734 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6735 Op.getOperand(0), Op.getOperand(1));
6736 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6737 DAG.getValueType(VT));
6738 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6739 } else if (VT.getSizeInBits() == 16) {
6740 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6741 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6743 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6744 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6745 DAG.getNode(ISD::BITCAST, dl,
6749 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6750 Op.getOperand(0), Op.getOperand(1));
6751 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6752 DAG.getValueType(VT));
6753 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6754 } else if (VT == MVT::f32) {
6755 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6756 // the result back to FR32 register. It's only worth matching if the
6757 // result has a single use which is a store or a bitcast to i32. And in
6758 // the case of a store, it's not worth it if the index is a constant 0,
6759 // because a MOVSSmr can be used instead, which is smaller and faster.
6760 if (!Op.hasOneUse())
6762 SDNode *User = *Op.getNode()->use_begin();
6763 if ((User->getOpcode() != ISD::STORE ||
6764 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6765 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6766 (User->getOpcode() != ISD::BITCAST ||
6767 User->getValueType(0) != MVT::i32))
6769 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6770 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6773 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6774 } else if (VT == MVT::i32 || VT == MVT::i64) {
6775 // ExtractPS/pextrq works with constant index.
6776 if (isa<ConstantSDNode>(Op.getOperand(1)))
6784 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6785 SelectionDAG &DAG) const {
6786 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6789 SDValue Vec = Op.getOperand(0);
6790 EVT VecVT = Vec.getValueType();
6792 // If this is a 256-bit vector result, first extract the 128-bit vector and
6793 // then extract the element from the 128-bit vector.
6794 if (VecVT.getSizeInBits() == 256) {
6795 DebugLoc dl = Op.getNode()->getDebugLoc();
6796 unsigned NumElems = VecVT.getVectorNumElements();
6797 SDValue Idx = Op.getOperand(1);
6798 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6800 // Get the 128-bit vector.
6801 bool Upper = IdxVal >= NumElems/2;
6802 Vec = Extract128BitVector(Vec,
6803 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6805 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6806 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6809 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6811 if (Subtarget->hasSSE41orAVX()) {
6812 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6817 EVT VT = Op.getValueType();
6818 DebugLoc dl = Op.getDebugLoc();
6819 // TODO: handle v16i8.
6820 if (VT.getSizeInBits() == 16) {
6821 SDValue Vec = Op.getOperand(0);
6822 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6824 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6825 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6826 DAG.getNode(ISD::BITCAST, dl,
6829 // Transform it so it match pextrw which produces a 32-bit result.
6830 EVT EltVT = MVT::i32;
6831 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6832 Op.getOperand(0), Op.getOperand(1));
6833 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6834 DAG.getValueType(VT));
6835 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6836 } else if (VT.getSizeInBits() == 32) {
6837 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6841 // SHUFPS the element to the lowest double word, then movss.
6842 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6843 EVT VVT = Op.getOperand(0).getValueType();
6844 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6845 DAG.getUNDEF(VVT), Mask);
6846 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6847 DAG.getIntPtrConstant(0));
6848 } else if (VT.getSizeInBits() == 64) {
6849 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6850 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6851 // to match extract_elt for f64.
6852 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6856 // UNPCKHPD the element to the lowest double word, then movsd.
6857 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6858 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6859 int Mask[2] = { 1, -1 };
6860 EVT VVT = Op.getOperand(0).getValueType();
6861 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6862 DAG.getUNDEF(VVT), Mask);
6863 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6864 DAG.getIntPtrConstant(0));
6871 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6872 SelectionDAG &DAG) const {
6873 EVT VT = Op.getValueType();
6874 EVT EltVT = VT.getVectorElementType();
6875 DebugLoc dl = Op.getDebugLoc();
6877 SDValue N0 = Op.getOperand(0);
6878 SDValue N1 = Op.getOperand(1);
6879 SDValue N2 = Op.getOperand(2);
6881 if (VT.getSizeInBits() == 256)
6884 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6885 isa<ConstantSDNode>(N2)) {
6887 if (VT == MVT::v8i16)
6888 Opc = X86ISD::PINSRW;
6889 else if (VT == MVT::v16i8)
6890 Opc = X86ISD::PINSRB;
6892 Opc = X86ISD::PINSRB;
6894 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6896 if (N1.getValueType() != MVT::i32)
6897 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6898 if (N2.getValueType() != MVT::i32)
6899 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6900 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6901 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6902 // Bits [7:6] of the constant are the source select. This will always be
6903 // zero here. The DAG Combiner may combine an extract_elt index into these
6904 // bits. For example (insert (extract, 3), 2) could be matched by putting
6905 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6906 // Bits [5:4] of the constant are the destination select. This is the
6907 // value of the incoming immediate.
6908 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6909 // combine either bitwise AND or insert of float 0.0 to set these bits.
6910 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6911 // Create this as a scalar to vector..
6912 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6913 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6914 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6915 isa<ConstantSDNode>(N2)) {
6916 // PINSR* works with constant index.
6923 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6924 EVT VT = Op.getValueType();
6925 EVT EltVT = VT.getVectorElementType();
6927 DebugLoc dl = Op.getDebugLoc();
6928 SDValue N0 = Op.getOperand(0);
6929 SDValue N1 = Op.getOperand(1);
6930 SDValue N2 = Op.getOperand(2);
6932 // If this is a 256-bit vector result, first extract the 128-bit vector,
6933 // insert the element into the extracted half and then place it back.
6934 if (VT.getSizeInBits() == 256) {
6935 if (!isa<ConstantSDNode>(N2))
6938 // Get the desired 128-bit vector half.
6939 unsigned NumElems = VT.getVectorNumElements();
6940 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6941 bool Upper = IdxVal >= NumElems/2;
6942 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6943 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6945 // Insert the element into the desired half.
6946 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6947 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6949 // Insert the changed part back to the 256-bit vector
6950 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6953 if (Subtarget->hasSSE41orAVX())
6954 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6956 if (EltVT == MVT::i8)
6959 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6960 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6961 // as its second argument.
6962 if (N1.getValueType() != MVT::i32)
6963 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6964 if (N2.getValueType() != MVT::i32)
6965 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6966 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6972 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6973 LLVMContext *Context = DAG.getContext();
6974 DebugLoc dl = Op.getDebugLoc();
6975 EVT OpVT = Op.getValueType();
6977 // If this is a 256-bit vector result, first insert into a 128-bit
6978 // vector and then insert into the 256-bit vector.
6979 if (OpVT.getSizeInBits() > 128) {
6980 // Insert into a 128-bit vector.
6981 EVT VT128 = EVT::getVectorVT(*Context,
6982 OpVT.getVectorElementType(),
6983 OpVT.getVectorNumElements() / 2);
6985 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6987 // Insert the 128-bit vector.
6988 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6989 DAG.getConstant(0, MVT::i32),
6993 if (Op.getValueType() == MVT::v1i64 &&
6994 Op.getOperand(0).getValueType() == MVT::i64)
6995 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6997 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6998 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6999 "Expected an SSE type!");
7000 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7001 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7004 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7005 // a simple subregister reference or explicit instructions to grab
7006 // upper bits of a vector.
7008 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7009 if (Subtarget->hasAVX()) {
7010 DebugLoc dl = Op.getNode()->getDebugLoc();
7011 SDValue Vec = Op.getNode()->getOperand(0);
7012 SDValue Idx = Op.getNode()->getOperand(1);
7014 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7015 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7016 return Extract128BitVector(Vec, Idx, DAG, dl);
7022 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7023 // simple superregister reference or explicit instructions to insert
7024 // the upper bits of a vector.
7026 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7027 if (Subtarget->hasAVX()) {
7028 DebugLoc dl = Op.getNode()->getDebugLoc();
7029 SDValue Vec = Op.getNode()->getOperand(0);
7030 SDValue SubVec = Op.getNode()->getOperand(1);
7031 SDValue Idx = Op.getNode()->getOperand(2);
7033 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7034 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7035 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7041 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7042 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7043 // one of the above mentioned nodes. It has to be wrapped because otherwise
7044 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7045 // be used to form addressing mode. These wrapped nodes will be selected
7048 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7049 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7051 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7053 unsigned char OpFlag = 0;
7054 unsigned WrapperKind = X86ISD::Wrapper;
7055 CodeModel::Model M = getTargetMachine().getCodeModel();
7057 if (Subtarget->isPICStyleRIPRel() &&
7058 (M == CodeModel::Small || M == CodeModel::Kernel))
7059 WrapperKind = X86ISD::WrapperRIP;
7060 else if (Subtarget->isPICStyleGOT())
7061 OpFlag = X86II::MO_GOTOFF;
7062 else if (Subtarget->isPICStyleStubPIC())
7063 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7065 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7067 CP->getOffset(), OpFlag);
7068 DebugLoc DL = CP->getDebugLoc();
7069 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7070 // With PIC, the address is actually $g + Offset.
7072 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7073 DAG.getNode(X86ISD::GlobalBaseReg,
7074 DebugLoc(), getPointerTy()),
7081 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7082 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7084 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7086 unsigned char OpFlag = 0;
7087 unsigned WrapperKind = X86ISD::Wrapper;
7088 CodeModel::Model M = getTargetMachine().getCodeModel();
7090 if (Subtarget->isPICStyleRIPRel() &&
7091 (M == CodeModel::Small || M == CodeModel::Kernel))
7092 WrapperKind = X86ISD::WrapperRIP;
7093 else if (Subtarget->isPICStyleGOT())
7094 OpFlag = X86II::MO_GOTOFF;
7095 else if (Subtarget->isPICStyleStubPIC())
7096 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7098 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7100 DebugLoc DL = JT->getDebugLoc();
7101 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7103 // With PIC, the address is actually $g + Offset.
7105 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7106 DAG.getNode(X86ISD::GlobalBaseReg,
7107 DebugLoc(), getPointerTy()),
7114 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7115 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7117 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7119 unsigned char OpFlag = 0;
7120 unsigned WrapperKind = X86ISD::Wrapper;
7121 CodeModel::Model M = getTargetMachine().getCodeModel();
7123 if (Subtarget->isPICStyleRIPRel() &&
7124 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7125 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7126 OpFlag = X86II::MO_GOTPCREL;
7127 WrapperKind = X86ISD::WrapperRIP;
7128 } else if (Subtarget->isPICStyleGOT()) {
7129 OpFlag = X86II::MO_GOT;
7130 } else if (Subtarget->isPICStyleStubPIC()) {
7131 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7132 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7133 OpFlag = X86II::MO_DARWIN_NONLAZY;
7136 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7138 DebugLoc DL = Op.getDebugLoc();
7139 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7142 // With PIC, the address is actually $g + Offset.
7143 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7144 !Subtarget->is64Bit()) {
7145 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7146 DAG.getNode(X86ISD::GlobalBaseReg,
7147 DebugLoc(), getPointerTy()),
7151 // For symbols that require a load from a stub to get the address, emit the
7153 if (isGlobalStubReference(OpFlag))
7154 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7155 MachinePointerInfo::getGOT(), false, false, false, 0);
7161 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7162 // Create the TargetBlockAddressAddress node.
7163 unsigned char OpFlags =
7164 Subtarget->ClassifyBlockAddressReference();
7165 CodeModel::Model M = getTargetMachine().getCodeModel();
7166 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7167 DebugLoc dl = Op.getDebugLoc();
7168 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7169 /*isTarget=*/true, OpFlags);
7171 if (Subtarget->isPICStyleRIPRel() &&
7172 (M == CodeModel::Small || M == CodeModel::Kernel))
7173 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7175 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7177 // With PIC, the address is actually $g + Offset.
7178 if (isGlobalRelativeToPICBase(OpFlags)) {
7179 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7180 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7188 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7190 SelectionDAG &DAG) const {
7191 // Create the TargetGlobalAddress node, folding in the constant
7192 // offset if it is legal.
7193 unsigned char OpFlags =
7194 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7195 CodeModel::Model M = getTargetMachine().getCodeModel();
7197 if (OpFlags == X86II::MO_NO_FLAG &&
7198 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7199 // A direct static reference to a global.
7200 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7203 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7206 if (Subtarget->isPICStyleRIPRel() &&
7207 (M == CodeModel::Small || M == CodeModel::Kernel))
7208 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7210 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7212 // With PIC, the address is actually $g + Offset.
7213 if (isGlobalRelativeToPICBase(OpFlags)) {
7214 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7215 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7219 // For globals that require a load from a stub to get the address, emit the
7221 if (isGlobalStubReference(OpFlags))
7222 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7223 MachinePointerInfo::getGOT(), false, false, false, 0);
7225 // If there was a non-zero offset that we didn't fold, create an explicit
7228 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7229 DAG.getConstant(Offset, getPointerTy()));
7235 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7236 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7237 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7238 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7242 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7243 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7244 unsigned char OperandFlags) {
7245 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7246 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7247 DebugLoc dl = GA->getDebugLoc();
7248 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7249 GA->getValueType(0),
7253 SDValue Ops[] = { Chain, TGA, *InFlag };
7254 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7256 SDValue Ops[] = { Chain, TGA };
7257 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7260 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7261 MFI->setAdjustsStack(true);
7263 SDValue Flag = Chain.getValue(1);
7264 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7267 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7269 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7272 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7273 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7274 DAG.getNode(X86ISD::GlobalBaseReg,
7275 DebugLoc(), PtrVT), InFlag);
7276 InFlag = Chain.getValue(1);
7278 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7281 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7283 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7285 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7286 X86::RAX, X86II::MO_TLSGD);
7289 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7290 // "local exec" model.
7291 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7292 const EVT PtrVT, TLSModel::Model model,
7294 DebugLoc dl = GA->getDebugLoc();
7296 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7297 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7298 is64Bit ? 257 : 256));
7300 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7301 DAG.getIntPtrConstant(0),
7302 MachinePointerInfo(Ptr),
7303 false, false, false, 0);
7305 unsigned char OperandFlags = 0;
7306 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7308 unsigned WrapperKind = X86ISD::Wrapper;
7309 if (model == TLSModel::LocalExec) {
7310 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7311 } else if (is64Bit) {
7312 assert(model == TLSModel::InitialExec);
7313 OperandFlags = X86II::MO_GOTTPOFF;
7314 WrapperKind = X86ISD::WrapperRIP;
7316 assert(model == TLSModel::InitialExec);
7317 OperandFlags = X86II::MO_INDNTPOFF;
7320 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7322 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7323 GA->getValueType(0),
7324 GA->getOffset(), OperandFlags);
7325 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7327 if (model == TLSModel::InitialExec)
7328 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7329 MachinePointerInfo::getGOT(), false, false, false, 0);
7331 // The address of the thread local variable is the add of the thread
7332 // pointer with the offset of the variable.
7333 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7337 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7339 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7340 const GlobalValue *GV = GA->getGlobal();
7342 if (Subtarget->isTargetELF()) {
7343 // TODO: implement the "local dynamic" model
7344 // TODO: implement the "initial exec"model for pic executables
7346 // If GV is an alias then use the aliasee for determining
7347 // thread-localness.
7348 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7349 GV = GA->resolveAliasedGlobal(false);
7351 TLSModel::Model model
7352 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7355 case TLSModel::GeneralDynamic:
7356 case TLSModel::LocalDynamic: // not implemented
7357 if (Subtarget->is64Bit())
7358 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7359 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7361 case TLSModel::InitialExec:
7362 case TLSModel::LocalExec:
7363 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7364 Subtarget->is64Bit());
7366 } else if (Subtarget->isTargetDarwin()) {
7367 // Darwin only has one model of TLS. Lower to that.
7368 unsigned char OpFlag = 0;
7369 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7370 X86ISD::WrapperRIP : X86ISD::Wrapper;
7372 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7374 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7375 !Subtarget->is64Bit();
7377 OpFlag = X86II::MO_TLVP_PIC_BASE;
7379 OpFlag = X86II::MO_TLVP;
7380 DebugLoc DL = Op.getDebugLoc();
7381 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7382 GA->getValueType(0),
7383 GA->getOffset(), OpFlag);
7384 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7386 // With PIC32, the address is actually $g + Offset.
7388 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7389 DAG.getNode(X86ISD::GlobalBaseReg,
7390 DebugLoc(), getPointerTy()),
7393 // Lowering the machine isd will make sure everything is in the right
7395 SDValue Chain = DAG.getEntryNode();
7396 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7397 SDValue Args[] = { Chain, Offset };
7398 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7400 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7401 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7402 MFI->setAdjustsStack(true);
7404 // And our return value (tls address) is in the standard call return value
7406 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7407 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7412 "TLS not implemented for this target.");
7414 llvm_unreachable("Unreachable");
7419 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7420 /// take a 2 x i32 value to shift plus a shift amount.
7421 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7422 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7423 EVT VT = Op.getValueType();
7424 unsigned VTBits = VT.getSizeInBits();
7425 DebugLoc dl = Op.getDebugLoc();
7426 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7427 SDValue ShOpLo = Op.getOperand(0);
7428 SDValue ShOpHi = Op.getOperand(1);
7429 SDValue ShAmt = Op.getOperand(2);
7430 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7431 DAG.getConstant(VTBits - 1, MVT::i8))
7432 : DAG.getConstant(0, VT);
7435 if (Op.getOpcode() == ISD::SHL_PARTS) {
7436 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7437 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7439 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7440 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7443 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7444 DAG.getConstant(VTBits, MVT::i8));
7445 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7446 AndNode, DAG.getConstant(0, MVT::i8));
7449 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7450 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7451 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7453 if (Op.getOpcode() == ISD::SHL_PARTS) {
7454 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7455 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7457 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7458 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7461 SDValue Ops[2] = { Lo, Hi };
7462 return DAG.getMergeValues(Ops, 2, dl);
7465 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7466 SelectionDAG &DAG) const {
7467 EVT SrcVT = Op.getOperand(0).getValueType();
7469 if (SrcVT.isVector())
7472 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7473 "Unknown SINT_TO_FP to lower!");
7475 // These are really Legal; return the operand so the caller accepts it as
7477 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7479 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7480 Subtarget->is64Bit()) {
7484 DebugLoc dl = Op.getDebugLoc();
7485 unsigned Size = SrcVT.getSizeInBits()/8;
7486 MachineFunction &MF = DAG.getMachineFunction();
7487 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7488 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7489 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7491 MachinePointerInfo::getFixedStack(SSFI),
7493 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7496 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7498 SelectionDAG &DAG) const {
7500 DebugLoc DL = Op.getDebugLoc();
7502 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7504 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7506 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7508 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7510 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7511 MachineMemOperand *MMO;
7513 int SSFI = FI->getIndex();
7515 DAG.getMachineFunction()
7516 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7517 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7519 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7520 StackSlot = StackSlot.getOperand(1);
7522 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7523 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7525 Tys, Ops, array_lengthof(Ops),
7529 Chain = Result.getValue(1);
7530 SDValue InFlag = Result.getValue(2);
7532 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7533 // shouldn't be necessary except that RFP cannot be live across
7534 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7535 MachineFunction &MF = DAG.getMachineFunction();
7536 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7537 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7538 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7539 Tys = DAG.getVTList(MVT::Other);
7541 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7543 MachineMemOperand *MMO =
7544 DAG.getMachineFunction()
7545 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7546 MachineMemOperand::MOStore, SSFISize, SSFISize);
7548 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7549 Ops, array_lengthof(Ops),
7550 Op.getValueType(), MMO);
7551 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7552 MachinePointerInfo::getFixedStack(SSFI),
7553 false, false, false, 0);
7559 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7560 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7561 SelectionDAG &DAG) const {
7562 // This algorithm is not obvious. Here it is in C code, more or less:
7564 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7565 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7566 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7568 // Copy ints to xmm registers.
7569 __m128i xh = _mm_cvtsi32_si128( hi );
7570 __m128i xl = _mm_cvtsi32_si128( lo );
7572 // Combine into low half of a single xmm register.
7573 __m128i x = _mm_unpacklo_epi32( xh, xl );
7577 // Merge in appropriate exponents to give the integer bits the right
7579 x = _mm_unpacklo_epi32( x, exp );
7581 // Subtract away the biases to deal with the IEEE-754 double precision
7583 d = _mm_sub_pd( (__m128d) x, bias );
7585 // All conversions up to here are exact. The correctly rounded result is
7586 // calculated using the current rounding mode using the following
7588 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7589 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7590 // store doesn't really need to be here (except
7591 // maybe to zero the other double)
7596 DebugLoc dl = Op.getDebugLoc();
7597 LLVMContext *Context = DAG.getContext();
7599 // Build some magic constants.
7600 SmallVector<Constant*,4> CV0;
7601 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7602 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7603 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7604 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7605 Constant *C0 = ConstantVector::get(CV0);
7606 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7608 SmallVector<Constant*,2> CV1;
7610 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7612 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7613 Constant *C1 = ConstantVector::get(CV1);
7614 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7616 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7617 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7619 DAG.getIntPtrConstant(1)));
7620 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7621 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7623 DAG.getIntPtrConstant(0)));
7624 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7625 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7626 MachinePointerInfo::getConstantPool(),
7627 false, false, false, 16);
7628 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7629 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7630 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7631 MachinePointerInfo::getConstantPool(),
7632 false, false, false, 16);
7633 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7635 // Add the halves; easiest way is to swap them into another reg first.
7636 int ShufMask[2] = { 1, -1 };
7637 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7638 DAG.getUNDEF(MVT::v2f64), ShufMask);
7639 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7640 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7641 DAG.getIntPtrConstant(0));
7644 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7645 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7646 SelectionDAG &DAG) const {
7647 DebugLoc dl = Op.getDebugLoc();
7648 // FP constant to bias correct the final result.
7649 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7652 // Load the 32-bit value into an XMM register.
7653 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7656 // Zero out the upper parts of the register.
7657 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(),
7660 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7661 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7662 DAG.getIntPtrConstant(0));
7664 // Or the load with the bias.
7665 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7666 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7667 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7669 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7670 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7671 MVT::v2f64, Bias)));
7672 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7673 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7674 DAG.getIntPtrConstant(0));
7676 // Subtract the bias.
7677 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7679 // Handle final rounding.
7680 EVT DestVT = Op.getValueType();
7682 if (DestVT.bitsLT(MVT::f64)) {
7683 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7684 DAG.getIntPtrConstant(0));
7685 } else if (DestVT.bitsGT(MVT::f64)) {
7686 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7689 // Handle final rounding.
7693 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7694 SelectionDAG &DAG) const {
7695 SDValue N0 = Op.getOperand(0);
7696 DebugLoc dl = Op.getDebugLoc();
7698 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7699 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7700 // the optimization here.
7701 if (DAG.SignBitIsZero(N0))
7702 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7704 EVT SrcVT = N0.getValueType();
7705 EVT DstVT = Op.getValueType();
7706 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7707 return LowerUINT_TO_FP_i64(Op, DAG);
7708 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7709 return LowerUINT_TO_FP_i32(Op, DAG);
7711 // Make a 64-bit buffer, and use it to build an FILD.
7712 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7713 if (SrcVT == MVT::i32) {
7714 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7715 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7716 getPointerTy(), StackSlot, WordOff);
7717 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7718 StackSlot, MachinePointerInfo(),
7720 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7721 OffsetSlot, MachinePointerInfo(),
7723 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7727 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7728 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7729 StackSlot, MachinePointerInfo(),
7731 // For i64 source, we need to add the appropriate power of 2 if the input
7732 // was negative. This is the same as the optimization in
7733 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7734 // we must be careful to do the computation in x87 extended precision, not
7735 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7736 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7737 MachineMemOperand *MMO =
7738 DAG.getMachineFunction()
7739 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7740 MachineMemOperand::MOLoad, 8, 8);
7742 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7743 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7744 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7747 APInt FF(32, 0x5F800000ULL);
7749 // Check whether the sign bit is set.
7750 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7751 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7754 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7755 SDValue FudgePtr = DAG.getConstantPool(
7756 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7759 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7760 SDValue Zero = DAG.getIntPtrConstant(0);
7761 SDValue Four = DAG.getIntPtrConstant(4);
7762 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7764 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7766 // Load the value out, extending it from f32 to f80.
7767 // FIXME: Avoid the extend by constructing the right constant pool?
7768 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7769 FudgePtr, MachinePointerInfo::getConstantPool(),
7770 MVT::f32, false, false, 4);
7771 // Extend everything to 80 bits to force it to be done on x87.
7772 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7773 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7776 std::pair<SDValue,SDValue> X86TargetLowering::
7777 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7778 DebugLoc DL = Op.getDebugLoc();
7780 EVT DstTy = Op.getValueType();
7783 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7787 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7788 DstTy.getSimpleVT() >= MVT::i16 &&
7789 "Unknown FP_TO_SINT to lower!");
7791 // These are really Legal.
7792 if (DstTy == MVT::i32 &&
7793 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7794 return std::make_pair(SDValue(), SDValue());
7795 if (Subtarget->is64Bit() &&
7796 DstTy == MVT::i64 &&
7797 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7798 return std::make_pair(SDValue(), SDValue());
7800 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7802 MachineFunction &MF = DAG.getMachineFunction();
7803 unsigned MemSize = DstTy.getSizeInBits()/8;
7804 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7805 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7810 switch (DstTy.getSimpleVT().SimpleTy) {
7811 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7812 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7813 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7814 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7817 SDValue Chain = DAG.getEntryNode();
7818 SDValue Value = Op.getOperand(0);
7819 EVT TheVT = Op.getOperand(0).getValueType();
7820 if (isScalarFPTypeInSSEReg(TheVT)) {
7821 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7822 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7823 MachinePointerInfo::getFixedStack(SSFI),
7825 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7827 Chain, StackSlot, DAG.getValueType(TheVT)
7830 MachineMemOperand *MMO =
7831 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7832 MachineMemOperand::MOLoad, MemSize, MemSize);
7833 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7835 Chain = Value.getValue(1);
7836 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7837 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7840 MachineMemOperand *MMO =
7841 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7842 MachineMemOperand::MOStore, MemSize, MemSize);
7844 // Build the FP_TO_INT*_IN_MEM
7845 SDValue Ops[] = { Chain, Value, StackSlot };
7846 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7847 Ops, 3, DstTy, MMO);
7849 return std::make_pair(FIST, StackSlot);
7852 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7853 SelectionDAG &DAG) const {
7854 if (Op.getValueType().isVector())
7857 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7858 SDValue FIST = Vals.first, StackSlot = Vals.second;
7859 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7860 if (FIST.getNode() == 0) return Op;
7863 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7864 FIST, StackSlot, MachinePointerInfo(),
7865 false, false, false, 0);
7868 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7869 SelectionDAG &DAG) const {
7870 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7871 SDValue FIST = Vals.first, StackSlot = Vals.second;
7872 assert(FIST.getNode() && "Unexpected failure");
7875 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7876 FIST, StackSlot, MachinePointerInfo(),
7877 false, false, false, 0);
7880 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7881 SelectionDAG &DAG) const {
7882 LLVMContext *Context = DAG.getContext();
7883 DebugLoc dl = Op.getDebugLoc();
7884 EVT VT = Op.getValueType();
7887 EltVT = VT.getVectorElementType();
7888 SmallVector<Constant*,4> CV;
7889 if (EltVT == MVT::f64) {
7890 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7893 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7896 Constant *C = ConstantVector::get(CV);
7897 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7898 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7899 MachinePointerInfo::getConstantPool(),
7900 false, false, false, 16);
7901 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7904 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7905 LLVMContext *Context = DAG.getContext();
7906 DebugLoc dl = Op.getDebugLoc();
7907 EVT VT = Op.getValueType();
7909 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7910 if (VT.isVector()) {
7911 EltVT = VT.getVectorElementType();
7912 NumElts = VT.getVectorNumElements();
7914 SmallVector<Constant*,8> CV;
7915 if (EltVT == MVT::f64) {
7916 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7917 CV.assign(NumElts, C);
7919 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7920 CV.assign(NumElts, C);
7922 Constant *C = ConstantVector::get(CV);
7923 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7924 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7925 MachinePointerInfo::getConstantPool(),
7926 false, false, false, 16);
7927 if (VT.isVector()) {
7928 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7929 return DAG.getNode(ISD::BITCAST, dl, VT,
7930 DAG.getNode(ISD::XOR, dl, XORVT,
7931 DAG.getNode(ISD::BITCAST, dl, XORVT,
7933 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7935 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7939 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7940 LLVMContext *Context = DAG.getContext();
7941 SDValue Op0 = Op.getOperand(0);
7942 SDValue Op1 = Op.getOperand(1);
7943 DebugLoc dl = Op.getDebugLoc();
7944 EVT VT = Op.getValueType();
7945 EVT SrcVT = Op1.getValueType();
7947 // If second operand is smaller, extend it first.
7948 if (SrcVT.bitsLT(VT)) {
7949 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7952 // And if it is bigger, shrink it first.
7953 if (SrcVT.bitsGT(VT)) {
7954 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7958 // At this point the operands and the result should have the same
7959 // type, and that won't be f80 since that is not custom lowered.
7961 // First get the sign bit of second operand.
7962 SmallVector<Constant*,4> CV;
7963 if (SrcVT == MVT::f64) {
7964 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7965 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7967 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7968 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7970 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7972 Constant *C = ConstantVector::get(CV);
7973 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7974 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7975 MachinePointerInfo::getConstantPool(),
7976 false, false, false, 16);
7977 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7979 // Shift sign bit right or left if the two operands have different types.
7980 if (SrcVT.bitsGT(VT)) {
7981 // Op0 is MVT::f32, Op1 is MVT::f64.
7982 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7983 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7984 DAG.getConstant(32, MVT::i32));
7985 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7986 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7987 DAG.getIntPtrConstant(0));
7990 // Clear first operand sign bit.
7992 if (VT == MVT::f64) {
7993 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7994 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7996 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7997 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7998 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8001 C = ConstantVector::get(CV);
8002 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8003 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8004 MachinePointerInfo::getConstantPool(),
8005 false, false, false, 16);
8006 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8008 // Or the value with the sign bit.
8009 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8012 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8013 SDValue N0 = Op.getOperand(0);
8014 DebugLoc dl = Op.getDebugLoc();
8015 EVT VT = Op.getValueType();
8017 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8018 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8019 DAG.getConstant(1, VT));
8020 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8023 /// Emit nodes that will be selected as "test Op0,Op0", or something
8025 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8026 SelectionDAG &DAG) const {
8027 DebugLoc dl = Op.getDebugLoc();
8029 // CF and OF aren't always set the way we want. Determine which
8030 // of these we need.
8031 bool NeedCF = false;
8032 bool NeedOF = false;
8035 case X86::COND_A: case X86::COND_AE:
8036 case X86::COND_B: case X86::COND_BE:
8039 case X86::COND_G: case X86::COND_GE:
8040 case X86::COND_L: case X86::COND_LE:
8041 case X86::COND_O: case X86::COND_NO:
8046 // See if we can use the EFLAGS value from the operand instead of
8047 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8048 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8049 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8050 // Emit a CMP with 0, which is the TEST pattern.
8051 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8052 DAG.getConstant(0, Op.getValueType()));
8054 unsigned Opcode = 0;
8055 unsigned NumOperands = 0;
8056 switch (Op.getNode()->getOpcode()) {
8058 // Due to an isel shortcoming, be conservative if this add is likely to be
8059 // selected as part of a load-modify-store instruction. When the root node
8060 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8061 // uses of other nodes in the match, such as the ADD in this case. This
8062 // leads to the ADD being left around and reselected, with the result being
8063 // two adds in the output. Alas, even if none our users are stores, that
8064 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8065 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8066 // climbing the DAG back to the root, and it doesn't seem to be worth the
8068 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8069 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8070 if (UI->getOpcode() != ISD::CopyToReg &&
8071 UI->getOpcode() != ISD::SETCC &&
8072 UI->getOpcode() != ISD::STORE)
8075 if (ConstantSDNode *C =
8076 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8077 // An add of one will be selected as an INC.
8078 if (C->getAPIntValue() == 1) {
8079 Opcode = X86ISD::INC;
8084 // An add of negative one (subtract of one) will be selected as a DEC.
8085 if (C->getAPIntValue().isAllOnesValue()) {
8086 Opcode = X86ISD::DEC;
8092 // Otherwise use a regular EFLAGS-setting add.
8093 Opcode = X86ISD::ADD;
8097 // If the primary and result isn't used, don't bother using X86ISD::AND,
8098 // because a TEST instruction will be better.
8099 bool NonFlagUse = false;
8100 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8101 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8103 unsigned UOpNo = UI.getOperandNo();
8104 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8105 // Look pass truncate.
8106 UOpNo = User->use_begin().getOperandNo();
8107 User = *User->use_begin();
8110 if (User->getOpcode() != ISD::BRCOND &&
8111 User->getOpcode() != ISD::SETCC &&
8112 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8125 // Due to the ISEL shortcoming noted above, be conservative if this op is
8126 // likely to be selected as part of a load-modify-store instruction.
8127 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8128 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8129 if (UI->getOpcode() == ISD::STORE)
8132 // Otherwise use a regular EFLAGS-setting instruction.
8133 switch (Op.getNode()->getOpcode()) {
8134 default: llvm_unreachable("unexpected operator!");
8135 case ISD::SUB: Opcode = X86ISD::SUB; break;
8136 case ISD::OR: Opcode = X86ISD::OR; break;
8137 case ISD::XOR: Opcode = X86ISD::XOR; break;
8138 case ISD::AND: Opcode = X86ISD::AND; break;
8150 return SDValue(Op.getNode(), 1);
8157 // Emit a CMP with 0, which is the TEST pattern.
8158 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8159 DAG.getConstant(0, Op.getValueType()));
8161 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8162 SmallVector<SDValue, 4> Ops;
8163 for (unsigned i = 0; i != NumOperands; ++i)
8164 Ops.push_back(Op.getOperand(i));
8166 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8167 DAG.ReplaceAllUsesWith(Op, New);
8168 return SDValue(New.getNode(), 1);
8171 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8173 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8174 SelectionDAG &DAG) const {
8175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8176 if (C->getAPIntValue() == 0)
8177 return EmitTest(Op0, X86CC, DAG);
8179 DebugLoc dl = Op0.getDebugLoc();
8180 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8183 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8184 /// if it's possible.
8185 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8186 DebugLoc dl, SelectionDAG &DAG) const {
8187 SDValue Op0 = And.getOperand(0);
8188 SDValue Op1 = And.getOperand(1);
8189 if (Op0.getOpcode() == ISD::TRUNCATE)
8190 Op0 = Op0.getOperand(0);
8191 if (Op1.getOpcode() == ISD::TRUNCATE)
8192 Op1 = Op1.getOperand(0);
8195 if (Op1.getOpcode() == ISD::SHL)
8196 std::swap(Op0, Op1);
8197 if (Op0.getOpcode() == ISD::SHL) {
8198 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8199 if (And00C->getZExtValue() == 1) {
8200 // If we looked past a truncate, check that it's only truncating away
8202 unsigned BitWidth = Op0.getValueSizeInBits();
8203 unsigned AndBitWidth = And.getValueSizeInBits();
8204 if (BitWidth > AndBitWidth) {
8205 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8206 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8207 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8211 RHS = Op0.getOperand(1);
8213 } else if (Op1.getOpcode() == ISD::Constant) {
8214 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8215 uint64_t AndRHSVal = AndRHS->getZExtValue();
8216 SDValue AndLHS = Op0;
8218 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8219 LHS = AndLHS.getOperand(0);
8220 RHS = AndLHS.getOperand(1);
8223 // Use BT if the immediate can't be encoded in a TEST instruction.
8224 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8226 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8230 if (LHS.getNode()) {
8231 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8232 // instruction. Since the shift amount is in-range-or-undefined, we know
8233 // that doing a bittest on the i32 value is ok. We extend to i32 because
8234 // the encoding for the i16 version is larger than the i32 version.
8235 // Also promote i16 to i32 for performance / code size reason.
8236 if (LHS.getValueType() == MVT::i8 ||
8237 LHS.getValueType() == MVT::i16)
8238 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8240 // If the operand types disagree, extend the shift amount to match. Since
8241 // BT ignores high bits (like shifts) we can use anyextend.
8242 if (LHS.getValueType() != RHS.getValueType())
8243 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8245 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8246 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8247 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8248 DAG.getConstant(Cond, MVT::i8), BT);
8254 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8256 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8258 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8259 SDValue Op0 = Op.getOperand(0);
8260 SDValue Op1 = Op.getOperand(1);
8261 DebugLoc dl = Op.getDebugLoc();
8262 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8264 // Optimize to BT if possible.
8265 // Lower (X & (1 << N)) == 0 to BT(X, N).
8266 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8267 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8268 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8269 Op1.getOpcode() == ISD::Constant &&
8270 cast<ConstantSDNode>(Op1)->isNullValue() &&
8271 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8272 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8273 if (NewSetCC.getNode())
8277 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8279 if (Op1.getOpcode() == ISD::Constant &&
8280 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8281 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8282 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8284 // If the input is a setcc, then reuse the input setcc or use a new one with
8285 // the inverted condition.
8286 if (Op0.getOpcode() == X86ISD::SETCC) {
8287 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8288 bool Invert = (CC == ISD::SETNE) ^
8289 cast<ConstantSDNode>(Op1)->isNullValue();
8290 if (!Invert) return Op0;
8292 CCode = X86::GetOppositeBranchCondition(CCode);
8293 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8294 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8298 bool isFP = Op1.getValueType().isFloatingPoint();
8299 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8300 if (X86CC == X86::COND_INVALID)
8303 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8304 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8305 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8308 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8309 // ones, and then concatenate the result back.
8310 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8311 EVT VT = Op.getValueType();
8313 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8314 "Unsupported value type for operation");
8316 int NumElems = VT.getVectorNumElements();
8317 DebugLoc dl = Op.getDebugLoc();
8318 SDValue CC = Op.getOperand(2);
8319 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8320 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8322 // Extract the LHS vectors
8323 SDValue LHS = Op.getOperand(0);
8324 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8325 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8327 // Extract the RHS vectors
8328 SDValue RHS = Op.getOperand(1);
8329 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8330 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8332 // Issue the operation on the smaller types and concatenate the result back
8333 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8334 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8335 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8336 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8337 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8341 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8343 SDValue Op0 = Op.getOperand(0);
8344 SDValue Op1 = Op.getOperand(1);
8345 SDValue CC = Op.getOperand(2);
8346 EVT VT = Op.getValueType();
8347 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8348 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8349 DebugLoc dl = Op.getDebugLoc();
8353 EVT EltVT = Op0.getValueType().getVectorElementType();
8354 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8356 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8359 // SSE Condition code mapping:
8368 switch (SetCCOpcode) {
8371 case ISD::SETEQ: SSECC = 0; break;
8373 case ISD::SETGT: Swap = true; // Fallthrough
8375 case ISD::SETOLT: SSECC = 1; break;
8377 case ISD::SETGE: Swap = true; // Fallthrough
8379 case ISD::SETOLE: SSECC = 2; break;
8380 case ISD::SETUO: SSECC = 3; break;
8382 case ISD::SETNE: SSECC = 4; break;
8383 case ISD::SETULE: Swap = true;
8384 case ISD::SETUGE: SSECC = 5; break;
8385 case ISD::SETULT: Swap = true;
8386 case ISD::SETUGT: SSECC = 6; break;
8387 case ISD::SETO: SSECC = 7; break;
8390 std::swap(Op0, Op1);
8392 // In the two special cases we can't handle, emit two comparisons.
8394 if (SetCCOpcode == ISD::SETUEQ) {
8396 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8397 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8398 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8399 } else if (SetCCOpcode == ISD::SETONE) {
8401 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8402 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8403 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8405 llvm_unreachable("Illegal FP comparison");
8407 // Handle all other FP comparisons here.
8408 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8411 // Break 256-bit integer vector compare into smaller ones.
8412 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8413 return Lower256IntVSETCC(Op, DAG);
8415 // We are handling one of the integer comparisons here. Since SSE only has
8416 // GT and EQ comparisons for integer, swapping operands and multiple
8417 // operations may be required for some comparisons.
8418 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8419 bool Swap = false, Invert = false, FlipSigns = false;
8421 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8423 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8424 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8425 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8426 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8429 switch (SetCCOpcode) {
8431 case ISD::SETNE: Invert = true;
8432 case ISD::SETEQ: Opc = EQOpc; break;
8433 case ISD::SETLT: Swap = true;
8434 case ISD::SETGT: Opc = GTOpc; break;
8435 case ISD::SETGE: Swap = true;
8436 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8437 case ISD::SETULT: Swap = true;
8438 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8439 case ISD::SETUGE: Swap = true;
8440 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8443 std::swap(Op0, Op1);
8445 // Check that the operation in question is available (most are plain SSE2,
8446 // but PCMPGTQ and PCMPEQQ have different requirements).
8447 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42orAVX())
8449 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41orAVX())
8452 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8453 // bits of the inputs before performing those operations.
8455 EVT EltVT = VT.getVectorElementType();
8456 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8458 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8459 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8461 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8462 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8465 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8467 // If the logical-not of the result is required, perform that now.
8469 Result = DAG.getNOT(dl, Result, VT);
8474 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8475 static bool isX86LogicalCmp(SDValue Op) {
8476 unsigned Opc = Op.getNode()->getOpcode();
8477 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8479 if (Op.getResNo() == 1 &&
8480 (Opc == X86ISD::ADD ||
8481 Opc == X86ISD::SUB ||
8482 Opc == X86ISD::ADC ||
8483 Opc == X86ISD::SBB ||
8484 Opc == X86ISD::SMUL ||
8485 Opc == X86ISD::UMUL ||
8486 Opc == X86ISD::INC ||
8487 Opc == X86ISD::DEC ||
8488 Opc == X86ISD::OR ||
8489 Opc == X86ISD::XOR ||
8490 Opc == X86ISD::AND))
8493 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8499 static bool isZero(SDValue V) {
8500 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8501 return C && C->isNullValue();
8504 static bool isAllOnes(SDValue V) {
8505 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8506 return C && C->isAllOnesValue();
8509 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8510 bool addTest = true;
8511 SDValue Cond = Op.getOperand(0);
8512 SDValue Op1 = Op.getOperand(1);
8513 SDValue Op2 = Op.getOperand(2);
8514 DebugLoc DL = Op.getDebugLoc();
8517 if (Cond.getOpcode() == ISD::SETCC) {
8518 SDValue NewCond = LowerSETCC(Cond, DAG);
8519 if (NewCond.getNode())
8523 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8524 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8525 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8526 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8527 if (Cond.getOpcode() == X86ISD::SETCC &&
8528 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8529 isZero(Cond.getOperand(1).getOperand(1))) {
8530 SDValue Cmp = Cond.getOperand(1);
8532 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8534 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8535 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8536 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8538 SDValue CmpOp0 = Cmp.getOperand(0);
8539 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8540 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8542 SDValue Res = // Res = 0 or -1.
8543 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8544 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8546 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8547 Res = DAG.getNOT(DL, Res, Res.getValueType());
8549 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8550 if (N2C == 0 || !N2C->isNullValue())
8551 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8556 // Look past (and (setcc_carry (cmp ...)), 1).
8557 if (Cond.getOpcode() == ISD::AND &&
8558 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8559 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8560 if (C && C->getAPIntValue() == 1)
8561 Cond = Cond.getOperand(0);
8564 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8565 // setting operand in place of the X86ISD::SETCC.
8566 unsigned CondOpcode = Cond.getOpcode();
8567 if (CondOpcode == X86ISD::SETCC ||
8568 CondOpcode == X86ISD::SETCC_CARRY) {
8569 CC = Cond.getOperand(0);
8571 SDValue Cmp = Cond.getOperand(1);
8572 unsigned Opc = Cmp.getOpcode();
8573 EVT VT = Op.getValueType();
8575 bool IllegalFPCMov = false;
8576 if (VT.isFloatingPoint() && !VT.isVector() &&
8577 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8578 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8580 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8581 Opc == X86ISD::BT) { // FIXME
8585 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8586 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8587 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8588 Cond.getOperand(0).getValueType() != MVT::i8)) {
8589 SDValue LHS = Cond.getOperand(0);
8590 SDValue RHS = Cond.getOperand(1);
8594 switch (CondOpcode) {
8595 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8596 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8597 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8598 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8599 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8600 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8601 default: llvm_unreachable("unexpected overflowing operator");
8603 if (CondOpcode == ISD::UMULO)
8604 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8607 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8609 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8611 if (CondOpcode == ISD::UMULO)
8612 Cond = X86Op.getValue(2);
8614 Cond = X86Op.getValue(1);
8616 CC = DAG.getConstant(X86Cond, MVT::i8);
8621 // Look pass the truncate.
8622 if (Cond.getOpcode() == ISD::TRUNCATE)
8623 Cond = Cond.getOperand(0);
8625 // We know the result of AND is compared against zero. Try to match
8627 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8628 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8629 if (NewSetCC.getNode()) {
8630 CC = NewSetCC.getOperand(0);
8631 Cond = NewSetCC.getOperand(1);
8638 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8639 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8642 // a < b ? -1 : 0 -> RES = ~setcc_carry
8643 // a < b ? 0 : -1 -> RES = setcc_carry
8644 // a >= b ? -1 : 0 -> RES = setcc_carry
8645 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8646 if (Cond.getOpcode() == X86ISD::CMP) {
8647 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8649 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8650 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8651 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8652 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8653 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8654 return DAG.getNOT(DL, Res, Res.getValueType());
8659 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8660 // condition is true.
8661 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8662 SDValue Ops[] = { Op2, Op1, CC, Cond };
8663 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8666 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8667 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8668 // from the AND / OR.
8669 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8670 Opc = Op.getOpcode();
8671 if (Opc != ISD::OR && Opc != ISD::AND)
8673 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8674 Op.getOperand(0).hasOneUse() &&
8675 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8676 Op.getOperand(1).hasOneUse());
8679 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8680 // 1 and that the SETCC node has a single use.
8681 static bool isXor1OfSetCC(SDValue Op) {
8682 if (Op.getOpcode() != ISD::XOR)
8684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8685 if (N1C && N1C->getAPIntValue() == 1) {
8686 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8687 Op.getOperand(0).hasOneUse();
8692 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8693 bool addTest = true;
8694 SDValue Chain = Op.getOperand(0);
8695 SDValue Cond = Op.getOperand(1);
8696 SDValue Dest = Op.getOperand(2);
8697 DebugLoc dl = Op.getDebugLoc();
8699 bool Inverted = false;
8701 if (Cond.getOpcode() == ISD::SETCC) {
8702 // Check for setcc([su]{add,sub,mul}o == 0).
8703 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8704 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8705 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8706 Cond.getOperand(0).getResNo() == 1 &&
8707 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8708 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8709 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8710 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8711 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8712 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8714 Cond = Cond.getOperand(0);
8716 SDValue NewCond = LowerSETCC(Cond, DAG);
8717 if (NewCond.getNode())
8722 // FIXME: LowerXALUO doesn't handle these!!
8723 else if (Cond.getOpcode() == X86ISD::ADD ||
8724 Cond.getOpcode() == X86ISD::SUB ||
8725 Cond.getOpcode() == X86ISD::SMUL ||
8726 Cond.getOpcode() == X86ISD::UMUL)
8727 Cond = LowerXALUO(Cond, DAG);
8730 // Look pass (and (setcc_carry (cmp ...)), 1).
8731 if (Cond.getOpcode() == ISD::AND &&
8732 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8733 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8734 if (C && C->getAPIntValue() == 1)
8735 Cond = Cond.getOperand(0);
8738 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8739 // setting operand in place of the X86ISD::SETCC.
8740 unsigned CondOpcode = Cond.getOpcode();
8741 if (CondOpcode == X86ISD::SETCC ||
8742 CondOpcode == X86ISD::SETCC_CARRY) {
8743 CC = Cond.getOperand(0);
8745 SDValue Cmp = Cond.getOperand(1);
8746 unsigned Opc = Cmp.getOpcode();
8747 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8748 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8752 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8756 // These can only come from an arithmetic instruction with overflow,
8757 // e.g. SADDO, UADDO.
8758 Cond = Cond.getNode()->getOperand(1);
8764 CondOpcode = Cond.getOpcode();
8765 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8766 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8767 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8768 Cond.getOperand(0).getValueType() != MVT::i8)) {
8769 SDValue LHS = Cond.getOperand(0);
8770 SDValue RHS = Cond.getOperand(1);
8774 switch (CondOpcode) {
8775 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8776 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8777 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8778 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8779 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8780 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8781 default: llvm_unreachable("unexpected overflowing operator");
8784 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8785 if (CondOpcode == ISD::UMULO)
8786 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8789 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8791 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8793 if (CondOpcode == ISD::UMULO)
8794 Cond = X86Op.getValue(2);
8796 Cond = X86Op.getValue(1);
8798 CC = DAG.getConstant(X86Cond, MVT::i8);
8802 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8803 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8804 if (CondOpc == ISD::OR) {
8805 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8806 // two branches instead of an explicit OR instruction with a
8808 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8809 isX86LogicalCmp(Cmp)) {
8810 CC = Cond.getOperand(0).getOperand(0);
8811 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8812 Chain, Dest, CC, Cmp);
8813 CC = Cond.getOperand(1).getOperand(0);
8817 } else { // ISD::AND
8818 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8819 // two branches instead of an explicit AND instruction with a
8820 // separate test. However, we only do this if this block doesn't
8821 // have a fall-through edge, because this requires an explicit
8822 // jmp when the condition is false.
8823 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8824 isX86LogicalCmp(Cmp) &&
8825 Op.getNode()->hasOneUse()) {
8826 X86::CondCode CCode =
8827 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8828 CCode = X86::GetOppositeBranchCondition(CCode);
8829 CC = DAG.getConstant(CCode, MVT::i8);
8830 SDNode *User = *Op.getNode()->use_begin();
8831 // Look for an unconditional branch following this conditional branch.
8832 // We need this because we need to reverse the successors in order
8833 // to implement FCMP_OEQ.
8834 if (User->getOpcode() == ISD::BR) {
8835 SDValue FalseBB = User->getOperand(1);
8837 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8838 assert(NewBR == User);
8842 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8843 Chain, Dest, CC, Cmp);
8844 X86::CondCode CCode =
8845 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8846 CCode = X86::GetOppositeBranchCondition(CCode);
8847 CC = DAG.getConstant(CCode, MVT::i8);
8853 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8854 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8855 // It should be transformed during dag combiner except when the condition
8856 // is set by a arithmetics with overflow node.
8857 X86::CondCode CCode =
8858 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8859 CCode = X86::GetOppositeBranchCondition(CCode);
8860 CC = DAG.getConstant(CCode, MVT::i8);
8861 Cond = Cond.getOperand(0).getOperand(1);
8863 } else if (Cond.getOpcode() == ISD::SETCC &&
8864 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8865 // For FCMP_OEQ, we can emit
8866 // two branches instead of an explicit AND instruction with a
8867 // separate test. However, we only do this if this block doesn't
8868 // have a fall-through edge, because this requires an explicit
8869 // jmp when the condition is false.
8870 if (Op.getNode()->hasOneUse()) {
8871 SDNode *User = *Op.getNode()->use_begin();
8872 // Look for an unconditional branch following this conditional branch.
8873 // We need this because we need to reverse the successors in order
8874 // to implement FCMP_OEQ.
8875 if (User->getOpcode() == ISD::BR) {
8876 SDValue FalseBB = User->getOperand(1);
8878 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8879 assert(NewBR == User);
8883 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8884 Cond.getOperand(0), Cond.getOperand(1));
8885 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8886 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8887 Chain, Dest, CC, Cmp);
8888 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8893 } else if (Cond.getOpcode() == ISD::SETCC &&
8894 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8895 // For FCMP_UNE, we can emit
8896 // two branches instead of an explicit AND instruction with a
8897 // separate test. However, we only do this if this block doesn't
8898 // have a fall-through edge, because this requires an explicit
8899 // jmp when the condition is false.
8900 if (Op.getNode()->hasOneUse()) {
8901 SDNode *User = *Op.getNode()->use_begin();
8902 // Look for an unconditional branch following this conditional branch.
8903 // We need this because we need to reverse the successors in order
8904 // to implement FCMP_UNE.
8905 if (User->getOpcode() == ISD::BR) {
8906 SDValue FalseBB = User->getOperand(1);
8908 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8909 assert(NewBR == User);
8912 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8913 Cond.getOperand(0), Cond.getOperand(1));
8914 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8915 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8916 Chain, Dest, CC, Cmp);
8917 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8927 // Look pass the truncate.
8928 if (Cond.getOpcode() == ISD::TRUNCATE)
8929 Cond = Cond.getOperand(0);
8931 // We know the result of AND is compared against zero. Try to match
8933 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8934 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8935 if (NewSetCC.getNode()) {
8936 CC = NewSetCC.getOperand(0);
8937 Cond = NewSetCC.getOperand(1);
8944 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8945 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8947 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8948 Chain, Dest, CC, Cond);
8952 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8953 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8954 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8955 // that the guard pages used by the OS virtual memory manager are allocated in
8956 // correct sequence.
8958 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8959 SelectionDAG &DAG) const {
8960 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8961 getTargetMachine().Options.EnableSegmentedStacks) &&
8962 "This should be used only on Windows targets or when segmented stacks "
8964 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8965 DebugLoc dl = Op.getDebugLoc();
8968 SDValue Chain = Op.getOperand(0);
8969 SDValue Size = Op.getOperand(1);
8970 // FIXME: Ensure alignment here
8972 bool Is64Bit = Subtarget->is64Bit();
8973 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8975 if (getTargetMachine().Options.EnableSegmentedStacks) {
8976 MachineFunction &MF = DAG.getMachineFunction();
8977 MachineRegisterInfo &MRI = MF.getRegInfo();
8980 // The 64 bit implementation of segmented stacks needs to clobber both r10
8981 // r11. This makes it impossible to use it along with nested parameters.
8982 const Function *F = MF.getFunction();
8984 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8986 if (I->hasNestAttr())
8987 report_fatal_error("Cannot use segmented stacks with functions that "
8988 "have nested arguments.");
8991 const TargetRegisterClass *AddrRegClass =
8992 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8993 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8994 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8995 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8996 DAG.getRegister(Vreg, SPTy));
8997 SDValue Ops1[2] = { Value, Chain };
8998 return DAG.getMergeValues(Ops1, 2, dl);
9001 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9003 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9004 Flag = Chain.getValue(1);
9005 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9007 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9008 Flag = Chain.getValue(1);
9010 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9012 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9013 return DAG.getMergeValues(Ops1, 2, dl);
9017 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9018 MachineFunction &MF = DAG.getMachineFunction();
9019 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9021 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9022 DebugLoc DL = Op.getDebugLoc();
9024 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9025 // vastart just stores the address of the VarArgsFrameIndex slot into the
9026 // memory location argument.
9027 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9029 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9030 MachinePointerInfo(SV), false, false, 0);
9034 // gp_offset (0 - 6 * 8)
9035 // fp_offset (48 - 48 + 8 * 16)
9036 // overflow_arg_area (point to parameters coming in memory).
9038 SmallVector<SDValue, 8> MemOps;
9039 SDValue FIN = Op.getOperand(1);
9041 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9042 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9044 FIN, MachinePointerInfo(SV), false, false, 0);
9045 MemOps.push_back(Store);
9048 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9049 FIN, DAG.getIntPtrConstant(4));
9050 Store = DAG.getStore(Op.getOperand(0), DL,
9051 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9053 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9054 MemOps.push_back(Store);
9056 // Store ptr to overflow_arg_area
9057 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9058 FIN, DAG.getIntPtrConstant(4));
9059 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9061 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9062 MachinePointerInfo(SV, 8),
9064 MemOps.push_back(Store);
9066 // Store ptr to reg_save_area.
9067 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9068 FIN, DAG.getIntPtrConstant(8));
9069 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9071 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9072 MachinePointerInfo(SV, 16), false, false, 0);
9073 MemOps.push_back(Store);
9074 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9075 &MemOps[0], MemOps.size());
9078 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9079 assert(Subtarget->is64Bit() &&
9080 "LowerVAARG only handles 64-bit va_arg!");
9081 assert((Subtarget->isTargetLinux() ||
9082 Subtarget->isTargetDarwin()) &&
9083 "Unhandled target in LowerVAARG");
9084 assert(Op.getNode()->getNumOperands() == 4);
9085 SDValue Chain = Op.getOperand(0);
9086 SDValue SrcPtr = Op.getOperand(1);
9087 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9088 unsigned Align = Op.getConstantOperandVal(3);
9089 DebugLoc dl = Op.getDebugLoc();
9091 EVT ArgVT = Op.getNode()->getValueType(0);
9092 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9093 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9096 // Decide which area this value should be read from.
9097 // TODO: Implement the AMD64 ABI in its entirety. This simple
9098 // selection mechanism works only for the basic types.
9099 if (ArgVT == MVT::f80) {
9100 llvm_unreachable("va_arg for f80 not yet implemented");
9101 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9102 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9103 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9104 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9106 llvm_unreachable("Unhandled argument type in LowerVAARG");
9110 // Sanity Check: Make sure using fp_offset makes sense.
9111 assert(!getTargetMachine().Options.UseSoftFloat &&
9112 !(DAG.getMachineFunction()
9113 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9114 Subtarget->hasXMM());
9117 // Insert VAARG_64 node into the DAG
9118 // VAARG_64 returns two values: Variable Argument Address, Chain
9119 SmallVector<SDValue, 11> InstOps;
9120 InstOps.push_back(Chain);
9121 InstOps.push_back(SrcPtr);
9122 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9123 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9124 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9125 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9126 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9127 VTs, &InstOps[0], InstOps.size(),
9129 MachinePointerInfo(SV),
9134 Chain = VAARG.getValue(1);
9136 // Load the next argument and return it
9137 return DAG.getLoad(ArgVT, dl,
9140 MachinePointerInfo(),
9141 false, false, false, 0);
9144 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9145 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9146 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9147 SDValue Chain = Op.getOperand(0);
9148 SDValue DstPtr = Op.getOperand(1);
9149 SDValue SrcPtr = Op.getOperand(2);
9150 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9151 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9152 DebugLoc DL = Op.getDebugLoc();
9154 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9155 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9157 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9161 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9162 DebugLoc dl = Op.getDebugLoc();
9163 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9165 default: return SDValue(); // Don't custom lower most intrinsics.
9166 // Comparison intrinsics.
9167 case Intrinsic::x86_sse_comieq_ss:
9168 case Intrinsic::x86_sse_comilt_ss:
9169 case Intrinsic::x86_sse_comile_ss:
9170 case Intrinsic::x86_sse_comigt_ss:
9171 case Intrinsic::x86_sse_comige_ss:
9172 case Intrinsic::x86_sse_comineq_ss:
9173 case Intrinsic::x86_sse_ucomieq_ss:
9174 case Intrinsic::x86_sse_ucomilt_ss:
9175 case Intrinsic::x86_sse_ucomile_ss:
9176 case Intrinsic::x86_sse_ucomigt_ss:
9177 case Intrinsic::x86_sse_ucomige_ss:
9178 case Intrinsic::x86_sse_ucomineq_ss:
9179 case Intrinsic::x86_sse2_comieq_sd:
9180 case Intrinsic::x86_sse2_comilt_sd:
9181 case Intrinsic::x86_sse2_comile_sd:
9182 case Intrinsic::x86_sse2_comigt_sd:
9183 case Intrinsic::x86_sse2_comige_sd:
9184 case Intrinsic::x86_sse2_comineq_sd:
9185 case Intrinsic::x86_sse2_ucomieq_sd:
9186 case Intrinsic::x86_sse2_ucomilt_sd:
9187 case Intrinsic::x86_sse2_ucomile_sd:
9188 case Intrinsic::x86_sse2_ucomigt_sd:
9189 case Intrinsic::x86_sse2_ucomige_sd:
9190 case Intrinsic::x86_sse2_ucomineq_sd: {
9192 ISD::CondCode CC = ISD::SETCC_INVALID;
9195 case Intrinsic::x86_sse_comieq_ss:
9196 case Intrinsic::x86_sse2_comieq_sd:
9200 case Intrinsic::x86_sse_comilt_ss:
9201 case Intrinsic::x86_sse2_comilt_sd:
9205 case Intrinsic::x86_sse_comile_ss:
9206 case Intrinsic::x86_sse2_comile_sd:
9210 case Intrinsic::x86_sse_comigt_ss:
9211 case Intrinsic::x86_sse2_comigt_sd:
9215 case Intrinsic::x86_sse_comige_ss:
9216 case Intrinsic::x86_sse2_comige_sd:
9220 case Intrinsic::x86_sse_comineq_ss:
9221 case Intrinsic::x86_sse2_comineq_sd:
9225 case Intrinsic::x86_sse_ucomieq_ss:
9226 case Intrinsic::x86_sse2_ucomieq_sd:
9227 Opc = X86ISD::UCOMI;
9230 case Intrinsic::x86_sse_ucomilt_ss:
9231 case Intrinsic::x86_sse2_ucomilt_sd:
9232 Opc = X86ISD::UCOMI;
9235 case Intrinsic::x86_sse_ucomile_ss:
9236 case Intrinsic::x86_sse2_ucomile_sd:
9237 Opc = X86ISD::UCOMI;
9240 case Intrinsic::x86_sse_ucomigt_ss:
9241 case Intrinsic::x86_sse2_ucomigt_sd:
9242 Opc = X86ISD::UCOMI;
9245 case Intrinsic::x86_sse_ucomige_ss:
9246 case Intrinsic::x86_sse2_ucomige_sd:
9247 Opc = X86ISD::UCOMI;
9250 case Intrinsic::x86_sse_ucomineq_ss:
9251 case Intrinsic::x86_sse2_ucomineq_sd:
9252 Opc = X86ISD::UCOMI;
9257 SDValue LHS = Op.getOperand(1);
9258 SDValue RHS = Op.getOperand(2);
9259 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9260 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9261 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9262 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9263 DAG.getConstant(X86CC, MVT::i8), Cond);
9264 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9266 // Arithmetic intrinsics.
9267 case Intrinsic::x86_sse3_hadd_ps:
9268 case Intrinsic::x86_sse3_hadd_pd:
9269 case Intrinsic::x86_avx_hadd_ps_256:
9270 case Intrinsic::x86_avx_hadd_pd_256:
9271 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9272 Op.getOperand(1), Op.getOperand(2));
9273 case Intrinsic::x86_sse3_hsub_ps:
9274 case Intrinsic::x86_sse3_hsub_pd:
9275 case Intrinsic::x86_avx_hsub_ps_256:
9276 case Intrinsic::x86_avx_hsub_pd_256:
9277 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9278 Op.getOperand(1), Op.getOperand(2));
9279 case Intrinsic::x86_avx2_psllv_d:
9280 case Intrinsic::x86_avx2_psllv_q:
9281 case Intrinsic::x86_avx2_psllv_d_256:
9282 case Intrinsic::x86_avx2_psllv_q_256:
9283 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9284 Op.getOperand(1), Op.getOperand(2));
9285 case Intrinsic::x86_avx2_psrlv_d:
9286 case Intrinsic::x86_avx2_psrlv_q:
9287 case Intrinsic::x86_avx2_psrlv_d_256:
9288 case Intrinsic::x86_avx2_psrlv_q_256:
9289 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9290 Op.getOperand(1), Op.getOperand(2));
9291 case Intrinsic::x86_avx2_psrav_d:
9292 case Intrinsic::x86_avx2_psrav_d_256:
9293 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9294 Op.getOperand(1), Op.getOperand(2));
9296 // ptest and testp intrinsics. The intrinsic these come from are designed to
9297 // return an integer value, not just an instruction so lower it to the ptest
9298 // or testp pattern and a setcc for the result.
9299 case Intrinsic::x86_sse41_ptestz:
9300 case Intrinsic::x86_sse41_ptestc:
9301 case Intrinsic::x86_sse41_ptestnzc:
9302 case Intrinsic::x86_avx_ptestz_256:
9303 case Intrinsic::x86_avx_ptestc_256:
9304 case Intrinsic::x86_avx_ptestnzc_256:
9305 case Intrinsic::x86_avx_vtestz_ps:
9306 case Intrinsic::x86_avx_vtestc_ps:
9307 case Intrinsic::x86_avx_vtestnzc_ps:
9308 case Intrinsic::x86_avx_vtestz_pd:
9309 case Intrinsic::x86_avx_vtestc_pd:
9310 case Intrinsic::x86_avx_vtestnzc_pd:
9311 case Intrinsic::x86_avx_vtestz_ps_256:
9312 case Intrinsic::x86_avx_vtestc_ps_256:
9313 case Intrinsic::x86_avx_vtestnzc_ps_256:
9314 case Intrinsic::x86_avx_vtestz_pd_256:
9315 case Intrinsic::x86_avx_vtestc_pd_256:
9316 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9317 bool IsTestPacked = false;
9320 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9321 case Intrinsic::x86_avx_vtestz_ps:
9322 case Intrinsic::x86_avx_vtestz_pd:
9323 case Intrinsic::x86_avx_vtestz_ps_256:
9324 case Intrinsic::x86_avx_vtestz_pd_256:
9325 IsTestPacked = true; // Fallthrough
9326 case Intrinsic::x86_sse41_ptestz:
9327 case Intrinsic::x86_avx_ptestz_256:
9329 X86CC = X86::COND_E;
9331 case Intrinsic::x86_avx_vtestc_ps:
9332 case Intrinsic::x86_avx_vtestc_pd:
9333 case Intrinsic::x86_avx_vtestc_ps_256:
9334 case Intrinsic::x86_avx_vtestc_pd_256:
9335 IsTestPacked = true; // Fallthrough
9336 case Intrinsic::x86_sse41_ptestc:
9337 case Intrinsic::x86_avx_ptestc_256:
9339 X86CC = X86::COND_B;
9341 case Intrinsic::x86_avx_vtestnzc_ps:
9342 case Intrinsic::x86_avx_vtestnzc_pd:
9343 case Intrinsic::x86_avx_vtestnzc_ps_256:
9344 case Intrinsic::x86_avx_vtestnzc_pd_256:
9345 IsTestPacked = true; // Fallthrough
9346 case Intrinsic::x86_sse41_ptestnzc:
9347 case Intrinsic::x86_avx_ptestnzc_256:
9349 X86CC = X86::COND_A;
9353 SDValue LHS = Op.getOperand(1);
9354 SDValue RHS = Op.getOperand(2);
9355 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9356 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9357 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9358 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9359 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9362 // Fix vector shift instructions where the last operand is a non-immediate
9364 case Intrinsic::x86_avx2_pslli_w:
9365 case Intrinsic::x86_avx2_pslli_d:
9366 case Intrinsic::x86_avx2_pslli_q:
9367 case Intrinsic::x86_avx2_psrli_w:
9368 case Intrinsic::x86_avx2_psrli_d:
9369 case Intrinsic::x86_avx2_psrli_q:
9370 case Intrinsic::x86_avx2_psrai_w:
9371 case Intrinsic::x86_avx2_psrai_d:
9372 case Intrinsic::x86_sse2_pslli_w:
9373 case Intrinsic::x86_sse2_pslli_d:
9374 case Intrinsic::x86_sse2_pslli_q:
9375 case Intrinsic::x86_sse2_psrli_w:
9376 case Intrinsic::x86_sse2_psrli_d:
9377 case Intrinsic::x86_sse2_psrli_q:
9378 case Intrinsic::x86_sse2_psrai_w:
9379 case Intrinsic::x86_sse2_psrai_d:
9380 case Intrinsic::x86_mmx_pslli_w:
9381 case Intrinsic::x86_mmx_pslli_d:
9382 case Intrinsic::x86_mmx_pslli_q:
9383 case Intrinsic::x86_mmx_psrli_w:
9384 case Intrinsic::x86_mmx_psrli_d:
9385 case Intrinsic::x86_mmx_psrli_q:
9386 case Intrinsic::x86_mmx_psrai_w:
9387 case Intrinsic::x86_mmx_psrai_d: {
9388 SDValue ShAmt = Op.getOperand(2);
9389 if (isa<ConstantSDNode>(ShAmt))
9392 unsigned NewIntNo = 0;
9393 EVT ShAmtVT = MVT::v4i32;
9395 case Intrinsic::x86_sse2_pslli_w:
9396 NewIntNo = Intrinsic::x86_sse2_psll_w;
9398 case Intrinsic::x86_sse2_pslli_d:
9399 NewIntNo = Intrinsic::x86_sse2_psll_d;
9401 case Intrinsic::x86_sse2_pslli_q:
9402 NewIntNo = Intrinsic::x86_sse2_psll_q;
9404 case Intrinsic::x86_sse2_psrli_w:
9405 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9407 case Intrinsic::x86_sse2_psrli_d:
9408 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9410 case Intrinsic::x86_sse2_psrli_q:
9411 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9413 case Intrinsic::x86_sse2_psrai_w:
9414 NewIntNo = Intrinsic::x86_sse2_psra_w;
9416 case Intrinsic::x86_sse2_psrai_d:
9417 NewIntNo = Intrinsic::x86_sse2_psra_d;
9419 case Intrinsic::x86_avx2_pslli_w:
9420 NewIntNo = Intrinsic::x86_avx2_psll_w;
9422 case Intrinsic::x86_avx2_pslli_d:
9423 NewIntNo = Intrinsic::x86_avx2_psll_d;
9425 case Intrinsic::x86_avx2_pslli_q:
9426 NewIntNo = Intrinsic::x86_avx2_psll_q;
9428 case Intrinsic::x86_avx2_psrli_w:
9429 NewIntNo = Intrinsic::x86_avx2_psrl_w;
9431 case Intrinsic::x86_avx2_psrli_d:
9432 NewIntNo = Intrinsic::x86_avx2_psrl_d;
9434 case Intrinsic::x86_avx2_psrli_q:
9435 NewIntNo = Intrinsic::x86_avx2_psrl_q;
9437 case Intrinsic::x86_avx2_psrai_w:
9438 NewIntNo = Intrinsic::x86_avx2_psra_w;
9440 case Intrinsic::x86_avx2_psrai_d:
9441 NewIntNo = Intrinsic::x86_avx2_psra_d;
9444 ShAmtVT = MVT::v2i32;
9446 case Intrinsic::x86_mmx_pslli_w:
9447 NewIntNo = Intrinsic::x86_mmx_psll_w;
9449 case Intrinsic::x86_mmx_pslli_d:
9450 NewIntNo = Intrinsic::x86_mmx_psll_d;
9452 case Intrinsic::x86_mmx_pslli_q:
9453 NewIntNo = Intrinsic::x86_mmx_psll_q;
9455 case Intrinsic::x86_mmx_psrli_w:
9456 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9458 case Intrinsic::x86_mmx_psrli_d:
9459 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9461 case Intrinsic::x86_mmx_psrli_q:
9462 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9464 case Intrinsic::x86_mmx_psrai_w:
9465 NewIntNo = Intrinsic::x86_mmx_psra_w;
9467 case Intrinsic::x86_mmx_psrai_d:
9468 NewIntNo = Intrinsic::x86_mmx_psra_d;
9470 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9476 // The vector shift intrinsics with scalars uses 32b shift amounts but
9477 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9481 ShOps[1] = DAG.getConstant(0, MVT::i32);
9482 if (ShAmtVT == MVT::v4i32) {
9483 ShOps[2] = DAG.getUNDEF(MVT::i32);
9484 ShOps[3] = DAG.getUNDEF(MVT::i32);
9485 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9487 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9488 // FIXME this must be lowered to get rid of the invalid type.
9491 EVT VT = Op.getValueType();
9492 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9493 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9494 DAG.getConstant(NewIntNo, MVT::i32),
9495 Op.getOperand(1), ShAmt);
9500 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9501 SelectionDAG &DAG) const {
9502 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9503 MFI->setReturnAddressIsTaken(true);
9505 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9506 DebugLoc dl = Op.getDebugLoc();
9509 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9511 DAG.getConstant(TD->getPointerSize(),
9512 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9513 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9514 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9516 MachinePointerInfo(), false, false, false, 0);
9519 // Just load the return address.
9520 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9521 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9522 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9525 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9526 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9527 MFI->setFrameAddressIsTaken(true);
9529 EVT VT = Op.getValueType();
9530 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9531 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9532 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9533 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9535 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9536 MachinePointerInfo(),
9537 false, false, false, 0);
9541 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9542 SelectionDAG &DAG) const {
9543 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9546 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9547 MachineFunction &MF = DAG.getMachineFunction();
9548 SDValue Chain = Op.getOperand(0);
9549 SDValue Offset = Op.getOperand(1);
9550 SDValue Handler = Op.getOperand(2);
9551 DebugLoc dl = Op.getDebugLoc();
9553 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9554 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9556 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9558 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9559 DAG.getIntPtrConstant(TD->getPointerSize()));
9560 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9561 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9563 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9564 MF.getRegInfo().addLiveOut(StoreAddrReg);
9566 return DAG.getNode(X86ISD::EH_RETURN, dl,
9568 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9571 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9572 SelectionDAG &DAG) const {
9573 return Op.getOperand(0);
9576 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9577 SelectionDAG &DAG) const {
9578 SDValue Root = Op.getOperand(0);
9579 SDValue Trmp = Op.getOperand(1); // trampoline
9580 SDValue FPtr = Op.getOperand(2); // nested function
9581 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9582 DebugLoc dl = Op.getDebugLoc();
9584 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9586 if (Subtarget->is64Bit()) {
9587 SDValue OutChains[6];
9589 // Large code-model.
9590 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9591 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9593 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9594 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9596 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9598 // Load the pointer to the nested function into R11.
9599 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9600 SDValue Addr = Trmp;
9601 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9602 Addr, MachinePointerInfo(TrmpAddr),
9605 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9606 DAG.getConstant(2, MVT::i64));
9607 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9608 MachinePointerInfo(TrmpAddr, 2),
9611 // Load the 'nest' parameter value into R10.
9612 // R10 is specified in X86CallingConv.td
9613 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9614 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9615 DAG.getConstant(10, MVT::i64));
9616 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9617 Addr, MachinePointerInfo(TrmpAddr, 10),
9620 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9621 DAG.getConstant(12, MVT::i64));
9622 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9623 MachinePointerInfo(TrmpAddr, 12),
9626 // Jump to the nested function.
9627 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9628 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9629 DAG.getConstant(20, MVT::i64));
9630 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9631 Addr, MachinePointerInfo(TrmpAddr, 20),
9634 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9635 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9636 DAG.getConstant(22, MVT::i64));
9637 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9638 MachinePointerInfo(TrmpAddr, 22),
9641 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9643 const Function *Func =
9644 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9645 CallingConv::ID CC = Func->getCallingConv();
9650 llvm_unreachable("Unsupported calling convention");
9651 case CallingConv::C:
9652 case CallingConv::X86_StdCall: {
9653 // Pass 'nest' parameter in ECX.
9654 // Must be kept in sync with X86CallingConv.td
9657 // Check that ECX wasn't needed by an 'inreg' parameter.
9658 FunctionType *FTy = Func->getFunctionType();
9659 const AttrListPtr &Attrs = Func->getAttributes();
9661 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9662 unsigned InRegCount = 0;
9665 for (FunctionType::param_iterator I = FTy->param_begin(),
9666 E = FTy->param_end(); I != E; ++I, ++Idx)
9667 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9668 // FIXME: should only count parameters that are lowered to integers.
9669 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9671 if (InRegCount > 2) {
9672 report_fatal_error("Nest register in use - reduce number of inreg"
9678 case CallingConv::X86_FastCall:
9679 case CallingConv::X86_ThisCall:
9680 case CallingConv::Fast:
9681 // Pass 'nest' parameter in EAX.
9682 // Must be kept in sync with X86CallingConv.td
9687 SDValue OutChains[4];
9690 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9691 DAG.getConstant(10, MVT::i32));
9692 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9694 // This is storing the opcode for MOV32ri.
9695 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9696 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9697 OutChains[0] = DAG.getStore(Root, dl,
9698 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9699 Trmp, MachinePointerInfo(TrmpAddr),
9702 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9703 DAG.getConstant(1, MVT::i32));
9704 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9705 MachinePointerInfo(TrmpAddr, 1),
9708 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9709 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9710 DAG.getConstant(5, MVT::i32));
9711 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9712 MachinePointerInfo(TrmpAddr, 5),
9715 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9716 DAG.getConstant(6, MVT::i32));
9717 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9718 MachinePointerInfo(TrmpAddr, 6),
9721 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9725 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9726 SelectionDAG &DAG) const {
9728 The rounding mode is in bits 11:10 of FPSR, and has the following
9735 FLT_ROUNDS, on the other hand, expects the following:
9742 To perform the conversion, we do:
9743 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9746 MachineFunction &MF = DAG.getMachineFunction();
9747 const TargetMachine &TM = MF.getTarget();
9748 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9749 unsigned StackAlignment = TFI.getStackAlignment();
9750 EVT VT = Op.getValueType();
9751 DebugLoc DL = Op.getDebugLoc();
9753 // Save FP Control Word to stack slot
9754 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9755 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9758 MachineMemOperand *MMO =
9759 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9760 MachineMemOperand::MOStore, 2, 2);
9762 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9763 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9764 DAG.getVTList(MVT::Other),
9765 Ops, 2, MVT::i16, MMO);
9767 // Load FP Control Word from stack slot
9768 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9769 MachinePointerInfo(), false, false, false, 0);
9771 // Transform as necessary
9773 DAG.getNode(ISD::SRL, DL, MVT::i16,
9774 DAG.getNode(ISD::AND, DL, MVT::i16,
9775 CWD, DAG.getConstant(0x800, MVT::i16)),
9776 DAG.getConstant(11, MVT::i8));
9778 DAG.getNode(ISD::SRL, DL, MVT::i16,
9779 DAG.getNode(ISD::AND, DL, MVT::i16,
9780 CWD, DAG.getConstant(0x400, MVT::i16)),
9781 DAG.getConstant(9, MVT::i8));
9784 DAG.getNode(ISD::AND, DL, MVT::i16,
9785 DAG.getNode(ISD::ADD, DL, MVT::i16,
9786 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9787 DAG.getConstant(1, MVT::i16)),
9788 DAG.getConstant(3, MVT::i16));
9791 return DAG.getNode((VT.getSizeInBits() < 16 ?
9792 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9795 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9796 EVT VT = Op.getValueType();
9798 unsigned NumBits = VT.getSizeInBits();
9799 DebugLoc dl = Op.getDebugLoc();
9801 Op = Op.getOperand(0);
9802 if (VT == MVT::i8) {
9803 // Zero extend to i32 since there is not an i8 bsr.
9805 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9808 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9809 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9810 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9812 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9815 DAG.getConstant(NumBits+NumBits-1, OpVT),
9816 DAG.getConstant(X86::COND_E, MVT::i8),
9819 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9821 // Finally xor with NumBits-1.
9822 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9825 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9829 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9830 EVT VT = Op.getValueType();
9832 unsigned NumBits = VT.getSizeInBits();
9833 DebugLoc dl = Op.getDebugLoc();
9835 Op = Op.getOperand(0);
9836 if (VT == MVT::i8) {
9838 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9841 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9842 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9843 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9845 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9848 DAG.getConstant(NumBits, OpVT),
9849 DAG.getConstant(X86::COND_E, MVT::i8),
9852 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9855 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9859 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9860 // ones, and then concatenate the result back.
9861 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9862 EVT VT = Op.getValueType();
9864 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9865 "Unsupported value type for operation");
9867 int NumElems = VT.getVectorNumElements();
9868 DebugLoc dl = Op.getDebugLoc();
9869 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9870 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9872 // Extract the LHS vectors
9873 SDValue LHS = Op.getOperand(0);
9874 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9875 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9877 // Extract the RHS vectors
9878 SDValue RHS = Op.getOperand(1);
9879 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9880 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9882 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9883 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9885 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9886 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9887 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9890 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9891 assert(Op.getValueType().getSizeInBits() == 256 &&
9892 Op.getValueType().isInteger() &&
9893 "Only handle AVX 256-bit vector integer operation");
9894 return Lower256IntArith(Op, DAG);
9897 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9898 assert(Op.getValueType().getSizeInBits() == 256 &&
9899 Op.getValueType().isInteger() &&
9900 "Only handle AVX 256-bit vector integer operation");
9901 return Lower256IntArith(Op, DAG);
9904 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9905 EVT VT = Op.getValueType();
9907 // Decompose 256-bit ops into smaller 128-bit ops.
9908 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9909 return Lower256IntArith(Op, DAG);
9911 DebugLoc dl = Op.getDebugLoc();
9913 SDValue A = Op.getOperand(0);
9914 SDValue B = Op.getOperand(1);
9916 if (VT == MVT::v4i64) {
9917 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9919 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9920 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9921 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9922 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9923 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9925 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9926 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9927 // return AloBlo + AloBhi + AhiBlo;
9929 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9930 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9931 A, DAG.getConstant(32, MVT::i32));
9932 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9933 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9934 B, DAG.getConstant(32, MVT::i32));
9935 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9936 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9938 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9939 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9941 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9942 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9944 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9945 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9946 AloBhi, DAG.getConstant(32, MVT::i32));
9947 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9948 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9949 AhiBlo, DAG.getConstant(32, MVT::i32));
9950 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9951 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9955 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9957 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9958 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9959 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9960 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9961 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9963 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9964 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9965 // return AloBlo + AloBhi + AhiBlo;
9967 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9968 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9969 A, DAG.getConstant(32, MVT::i32));
9970 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9971 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9972 B, DAG.getConstant(32, MVT::i32));
9973 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9974 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9976 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9977 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9979 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9980 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9982 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9983 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9984 AloBhi, DAG.getConstant(32, MVT::i32));
9985 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9986 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9987 AhiBlo, DAG.getConstant(32, MVT::i32));
9988 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9989 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9993 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9995 EVT VT = Op.getValueType();
9996 DebugLoc dl = Op.getDebugLoc();
9997 SDValue R = Op.getOperand(0);
9998 SDValue Amt = Op.getOperand(1);
9999 LLVMContext *Context = DAG.getContext();
10001 if (!Subtarget->hasXMMInt())
10004 // Optimize shl/srl/sra with constant shift amount.
10005 if (isSplatVector(Amt.getNode())) {
10006 SDValue SclrAmt = Amt->getOperand(0);
10007 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10008 uint64_t ShiftAmt = C->getZExtValue();
10010 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
10011 // Make a large shift.
10013 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10014 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10015 R, DAG.getConstant(ShiftAmt, MVT::i32));
10016 // Zero out the rightmost bits.
10017 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10019 return DAG.getNode(ISD::AND, dl, VT, SHL,
10020 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10023 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
10024 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10025 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10026 R, DAG.getConstant(ShiftAmt, MVT::i32));
10028 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
10029 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10030 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10031 R, DAG.getConstant(ShiftAmt, MVT::i32));
10033 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
10034 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10035 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10036 R, DAG.getConstant(ShiftAmt, MVT::i32));
10038 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
10039 // Make a large shift.
10041 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10042 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10043 R, DAG.getConstant(ShiftAmt, MVT::i32));
10044 // Zero out the leftmost bits.
10045 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10047 return DAG.getNode(ISD::AND, dl, VT, SRL,
10048 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10051 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
10052 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10053 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10054 R, DAG.getConstant(ShiftAmt, MVT::i32));
10056 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
10057 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10058 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10059 R, DAG.getConstant(ShiftAmt, MVT::i32));
10061 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
10062 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10063 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10064 R, DAG.getConstant(ShiftAmt, MVT::i32));
10066 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
10067 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10068 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10069 R, DAG.getConstant(ShiftAmt, MVT::i32));
10071 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
10072 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10073 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10074 R, DAG.getConstant(ShiftAmt, MVT::i32));
10076 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
10077 if (ShiftAmt == 7) {
10078 // R s>> 7 === R s< 0
10079 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10080 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10083 // R s>> a === ((R u>> a) ^ m) - m
10084 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10085 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10087 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10088 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10089 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10093 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10094 if (Op.getOpcode() == ISD::SHL) {
10095 // Make a large shift.
10097 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10098 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
10099 R, DAG.getConstant(ShiftAmt, MVT::i32));
10100 // Zero out the rightmost bits.
10101 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10103 return DAG.getNode(ISD::AND, dl, VT, SHL,
10104 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10106 if (Op.getOpcode() == ISD::SRL) {
10107 // Make a large shift.
10109 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10110 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
10111 R, DAG.getConstant(ShiftAmt, MVT::i32));
10112 // Zero out the leftmost bits.
10113 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10115 return DAG.getNode(ISD::AND, dl, VT, SRL,
10116 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10118 if (Op.getOpcode() == ISD::SRA) {
10119 if (ShiftAmt == 7) {
10120 // R s>> 7 === R s< 0
10121 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10122 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10125 // R s>> a === ((R u>> a) ^ m) - m
10126 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10127 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10129 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10130 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10131 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10138 // Lower SHL with variable shift amount.
10139 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10140 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10141 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10142 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
10144 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10146 std::vector<Constant*> CV(4, CI);
10147 Constant *C = ConstantVector::get(CV);
10148 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10149 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10150 MachinePointerInfo::getConstantPool(),
10151 false, false, false, 16);
10153 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10154 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10155 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10156 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10158 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10160 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10161 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10162 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
10164 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
10165 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
10167 std::vector<Constant*> CVM1(16, CM1);
10168 std::vector<Constant*> CVM2(16, CM2);
10169 Constant *C = ConstantVector::get(CVM1);
10170 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10171 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10172 MachinePointerInfo::getConstantPool(),
10173 false, false, false, 16);
10175 // r = pblendv(r, psllw(r & (char16)15, 4), a);
10176 M = DAG.getNode(ISD::AND, dl, VT, R, M);
10177 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10178 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10179 DAG.getConstant(4, MVT::i32));
10180 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, M, R);
10182 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10184 C = ConstantVector::get(CVM2);
10185 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10186 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10187 MachinePointerInfo::getConstantPool(),
10188 false, false, false, 16);
10190 // r = pblendv(r, psllw(r & (char16)63, 2), a);
10191 M = DAG.getNode(ISD::AND, dl, VT, R, M);
10192 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10193 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10194 DAG.getConstant(2, MVT::i32));
10195 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, M, R);
10197 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10199 // return pblendv(r, r+r, a);
10200 R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
10201 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10205 // Decompose 256-bit shifts into smaller 128-bit shifts.
10206 if (VT.getSizeInBits() == 256) {
10207 int NumElems = VT.getVectorNumElements();
10208 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10209 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10211 // Extract the two vectors
10212 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10213 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10216 // Recreate the shift amount vectors
10217 SDValue Amt1, Amt2;
10218 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10219 // Constant shift amount
10220 SmallVector<SDValue, 4> Amt1Csts;
10221 SmallVector<SDValue, 4> Amt2Csts;
10222 for (int i = 0; i < NumElems/2; ++i)
10223 Amt1Csts.push_back(Amt->getOperand(i));
10224 for (int i = NumElems/2; i < NumElems; ++i)
10225 Amt2Csts.push_back(Amt->getOperand(i));
10227 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10228 &Amt1Csts[0], NumElems/2);
10229 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10230 &Amt2Csts[0], NumElems/2);
10232 // Variable shift amount
10233 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10234 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10238 // Issue new vector shifts for the smaller types
10239 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10240 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10242 // Concatenate the result back
10243 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10249 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10250 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10251 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10252 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10253 // has only one use.
10254 SDNode *N = Op.getNode();
10255 SDValue LHS = N->getOperand(0);
10256 SDValue RHS = N->getOperand(1);
10257 unsigned BaseOp = 0;
10259 DebugLoc DL = Op.getDebugLoc();
10260 switch (Op.getOpcode()) {
10261 default: llvm_unreachable("Unknown ovf instruction!");
10263 // A subtract of one will be selected as a INC. Note that INC doesn't
10264 // set CF, so we can't do this for UADDO.
10265 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10267 BaseOp = X86ISD::INC;
10268 Cond = X86::COND_O;
10271 BaseOp = X86ISD::ADD;
10272 Cond = X86::COND_O;
10275 BaseOp = X86ISD::ADD;
10276 Cond = X86::COND_B;
10279 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10280 // set CF, so we can't do this for USUBO.
10281 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10283 BaseOp = X86ISD::DEC;
10284 Cond = X86::COND_O;
10287 BaseOp = X86ISD::SUB;
10288 Cond = X86::COND_O;
10291 BaseOp = X86ISD::SUB;
10292 Cond = X86::COND_B;
10295 BaseOp = X86ISD::SMUL;
10296 Cond = X86::COND_O;
10298 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10299 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10301 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10304 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10305 DAG.getConstant(X86::COND_O, MVT::i32),
10306 SDValue(Sum.getNode(), 2));
10308 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10312 // Also sets EFLAGS.
10313 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10314 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10317 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10318 DAG.getConstant(Cond, MVT::i32),
10319 SDValue(Sum.getNode(), 1));
10321 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10324 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
10325 DebugLoc dl = Op.getDebugLoc();
10326 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10327 EVT VT = Op.getValueType();
10329 if (Subtarget->hasXMMInt() && VT.isVector()) {
10330 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10331 ExtraVT.getScalarType().getSizeInBits();
10332 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10334 unsigned SHLIntrinsicsID = 0;
10335 unsigned SRAIntrinsicsID = 0;
10336 switch (VT.getSimpleVT().SimpleTy) {
10340 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10341 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10344 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10345 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10349 if (!Subtarget->hasAVX())
10351 if (!Subtarget->hasAVX2()) {
10352 // needs to be split
10353 int NumElems = VT.getVectorNumElements();
10354 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10355 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10357 // Extract the LHS vectors
10358 SDValue LHS = Op.getOperand(0);
10359 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10360 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10362 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10363 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10365 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10366 int ExtraNumElems = ExtraVT.getVectorNumElements();
10367 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10369 SDValue Extra = DAG.getValueType(ExtraVT);
10371 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10372 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10374 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10376 if (VT == MVT::v8i32) {
10377 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
10378 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
10380 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
10381 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
10385 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10386 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10387 Op.getOperand(0), ShAmt);
10389 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10390 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10398 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10399 DebugLoc dl = Op.getDebugLoc();
10401 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10402 // There isn't any reason to disable it if the target processor supports it.
10403 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) {
10404 SDValue Chain = Op.getOperand(0);
10405 SDValue Zero = DAG.getConstant(0, MVT::i32);
10407 DAG.getRegister(X86::ESP, MVT::i32), // Base
10408 DAG.getTargetConstant(1, MVT::i8), // Scale
10409 DAG.getRegister(0, MVT::i32), // Index
10410 DAG.getTargetConstant(0, MVT::i32), // Disp
10411 DAG.getRegister(0, MVT::i32), // Segment.
10416 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10417 array_lengthof(Ops));
10418 return SDValue(Res, 0);
10421 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10423 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10425 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10426 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10427 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10428 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10430 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10431 if (!Op1 && !Op2 && !Op3 && Op4)
10432 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10434 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10435 if (Op1 && !Op2 && !Op3 && !Op4)
10436 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10438 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10440 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10443 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10444 SelectionDAG &DAG) const {
10445 DebugLoc dl = Op.getDebugLoc();
10446 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10447 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10448 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10449 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10451 // The only fence that needs an instruction is a sequentially-consistent
10452 // cross-thread fence.
10453 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10454 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10455 // no-sse2). There isn't any reason to disable it if the target processor
10457 if (Subtarget->hasXMMInt() || Subtarget->is64Bit())
10458 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10460 SDValue Chain = Op.getOperand(0);
10461 SDValue Zero = DAG.getConstant(0, MVT::i32);
10463 DAG.getRegister(X86::ESP, MVT::i32), // Base
10464 DAG.getTargetConstant(1, MVT::i8), // Scale
10465 DAG.getRegister(0, MVT::i32), // Index
10466 DAG.getTargetConstant(0, MVT::i32), // Disp
10467 DAG.getRegister(0, MVT::i32), // Segment.
10472 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10473 array_lengthof(Ops));
10474 return SDValue(Res, 0);
10477 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10478 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10482 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10483 EVT T = Op.getValueType();
10484 DebugLoc DL = Op.getDebugLoc();
10487 switch(T.getSimpleVT().SimpleTy) {
10489 assert(false && "Invalid value type!");
10490 case MVT::i8: Reg = X86::AL; size = 1; break;
10491 case MVT::i16: Reg = X86::AX; size = 2; break;
10492 case MVT::i32: Reg = X86::EAX; size = 4; break;
10494 assert(Subtarget->is64Bit() && "Node not type legal!");
10495 Reg = X86::RAX; size = 8;
10498 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10499 Op.getOperand(2), SDValue());
10500 SDValue Ops[] = { cpIn.getValue(0),
10503 DAG.getTargetConstant(size, MVT::i8),
10504 cpIn.getValue(1) };
10505 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10506 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10507 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10510 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10514 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10515 SelectionDAG &DAG) const {
10516 assert(Subtarget->is64Bit() && "Result not type legalized?");
10517 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10518 SDValue TheChain = Op.getOperand(0);
10519 DebugLoc dl = Op.getDebugLoc();
10520 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10521 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10522 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10524 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10525 DAG.getConstant(32, MVT::i8));
10527 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10530 return DAG.getMergeValues(Ops, 2, dl);
10533 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10534 SelectionDAG &DAG) const {
10535 EVT SrcVT = Op.getOperand(0).getValueType();
10536 EVT DstVT = Op.getValueType();
10537 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() &&
10538 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10539 assert((DstVT == MVT::i64 ||
10540 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10541 "Unexpected custom BITCAST");
10542 // i64 <=> MMX conversions are Legal.
10543 if (SrcVT==MVT::i64 && DstVT.isVector())
10545 if (DstVT==MVT::i64 && SrcVT.isVector())
10547 // MMX <=> MMX conversions are Legal.
10548 if (SrcVT.isVector() && DstVT.isVector())
10550 // All other conversions need to be expanded.
10554 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10555 SDNode *Node = Op.getNode();
10556 DebugLoc dl = Node->getDebugLoc();
10557 EVT T = Node->getValueType(0);
10558 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10559 DAG.getConstant(0, T), Node->getOperand(2));
10560 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10561 cast<AtomicSDNode>(Node)->getMemoryVT(),
10562 Node->getOperand(0),
10563 Node->getOperand(1), negOp,
10564 cast<AtomicSDNode>(Node)->getSrcValue(),
10565 cast<AtomicSDNode>(Node)->getAlignment(),
10566 cast<AtomicSDNode>(Node)->getOrdering(),
10567 cast<AtomicSDNode>(Node)->getSynchScope());
10570 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10571 SDNode *Node = Op.getNode();
10572 DebugLoc dl = Node->getDebugLoc();
10573 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10575 // Convert seq_cst store -> xchg
10576 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10577 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10578 // (The only way to get a 16-byte store is cmpxchg16b)
10579 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10580 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10581 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10582 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10583 cast<AtomicSDNode>(Node)->getMemoryVT(),
10584 Node->getOperand(0),
10585 Node->getOperand(1), Node->getOperand(2),
10586 cast<AtomicSDNode>(Node)->getMemOperand(),
10587 cast<AtomicSDNode>(Node)->getOrdering(),
10588 cast<AtomicSDNode>(Node)->getSynchScope());
10589 return Swap.getValue(1);
10591 // Other atomic stores have a simple pattern.
10595 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10596 EVT VT = Op.getNode()->getValueType(0);
10598 // Let legalize expand this if it isn't a legal type yet.
10599 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10602 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10605 bool ExtraOp = false;
10606 switch (Op.getOpcode()) {
10607 default: assert(0 && "Invalid code");
10608 case ISD::ADDC: Opc = X86ISD::ADD; break;
10609 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10610 case ISD::SUBC: Opc = X86ISD::SUB; break;
10611 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10615 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10617 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10618 Op.getOperand(1), Op.getOperand(2));
10621 /// LowerOperation - Provide custom lowering hooks for some operations.
10623 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10624 switch (Op.getOpcode()) {
10625 default: llvm_unreachable("Should not custom lower this!");
10626 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10627 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10628 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10629 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10630 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10631 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10632 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10633 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10634 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10635 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10636 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10637 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10638 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10639 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10640 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10641 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10642 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10643 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10644 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10645 case ISD::SHL_PARTS:
10646 case ISD::SRA_PARTS:
10647 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10648 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10649 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10650 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10651 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10652 case ISD::FABS: return LowerFABS(Op, DAG);
10653 case ISD::FNEG: return LowerFNEG(Op, DAG);
10654 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10655 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10656 case ISD::SETCC: return LowerSETCC(Op, DAG);
10657 case ISD::SELECT: return LowerSELECT(Op, DAG);
10658 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10659 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10660 case ISD::VASTART: return LowerVASTART(Op, DAG);
10661 case ISD::VAARG: return LowerVAARG(Op, DAG);
10662 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10663 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10664 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10665 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10666 case ISD::FRAME_TO_ARGS_OFFSET:
10667 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10668 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10669 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10670 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10671 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10672 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10673 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10674 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10675 case ISD::MUL: return LowerMUL(Op, DAG);
10678 case ISD::SHL: return LowerShift(Op, DAG);
10684 case ISD::UMULO: return LowerXALUO(Op, DAG);
10685 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10686 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10690 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10691 case ISD::ADD: return LowerADD(Op, DAG);
10692 case ISD::SUB: return LowerSUB(Op, DAG);
10696 static void ReplaceATOMIC_LOAD(SDNode *Node,
10697 SmallVectorImpl<SDValue> &Results,
10698 SelectionDAG &DAG) {
10699 DebugLoc dl = Node->getDebugLoc();
10700 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10702 // Convert wide load -> cmpxchg8b/cmpxchg16b
10703 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10704 // (The only way to get a 16-byte load is cmpxchg16b)
10705 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10706 SDValue Zero = DAG.getConstant(0, VT);
10707 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10708 Node->getOperand(0),
10709 Node->getOperand(1), Zero, Zero,
10710 cast<AtomicSDNode>(Node)->getMemOperand(),
10711 cast<AtomicSDNode>(Node)->getOrdering(),
10712 cast<AtomicSDNode>(Node)->getSynchScope());
10713 Results.push_back(Swap.getValue(0));
10714 Results.push_back(Swap.getValue(1));
10717 void X86TargetLowering::
10718 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10719 SelectionDAG &DAG, unsigned NewOp) const {
10720 DebugLoc dl = Node->getDebugLoc();
10721 assert (Node->getValueType(0) == MVT::i64 &&
10722 "Only know how to expand i64 atomics");
10724 SDValue Chain = Node->getOperand(0);
10725 SDValue In1 = Node->getOperand(1);
10726 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10727 Node->getOperand(2), DAG.getIntPtrConstant(0));
10728 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10729 Node->getOperand(2), DAG.getIntPtrConstant(1));
10730 SDValue Ops[] = { Chain, In1, In2L, In2H };
10731 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10733 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10734 cast<MemSDNode>(Node)->getMemOperand());
10735 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10736 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10737 Results.push_back(Result.getValue(2));
10740 /// ReplaceNodeResults - Replace a node with an illegal result type
10741 /// with a new node built out of custom code.
10742 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10743 SmallVectorImpl<SDValue>&Results,
10744 SelectionDAG &DAG) const {
10745 DebugLoc dl = N->getDebugLoc();
10746 switch (N->getOpcode()) {
10748 assert(false && "Do not know how to custom type legalize this operation!");
10750 case ISD::SIGN_EXTEND_INREG:
10755 // We don't want to expand or promote these.
10757 case ISD::FP_TO_SINT: {
10758 std::pair<SDValue,SDValue> Vals =
10759 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10760 SDValue FIST = Vals.first, StackSlot = Vals.second;
10761 if (FIST.getNode() != 0) {
10762 EVT VT = N->getValueType(0);
10763 // Return a load from the stack slot.
10764 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10765 MachinePointerInfo(),
10766 false, false, false, 0));
10770 case ISD::READCYCLECOUNTER: {
10771 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10772 SDValue TheChain = N->getOperand(0);
10773 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10774 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10776 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10778 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10779 SDValue Ops[] = { eax, edx };
10780 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10781 Results.push_back(edx.getValue(1));
10784 case ISD::ATOMIC_CMP_SWAP: {
10785 EVT T = N->getValueType(0);
10786 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10787 bool Regs64bit = T == MVT::i128;
10788 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10789 SDValue cpInL, cpInH;
10790 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10791 DAG.getConstant(0, HalfT));
10792 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10793 DAG.getConstant(1, HalfT));
10794 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10795 Regs64bit ? X86::RAX : X86::EAX,
10797 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10798 Regs64bit ? X86::RDX : X86::EDX,
10799 cpInH, cpInL.getValue(1));
10800 SDValue swapInL, swapInH;
10801 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10802 DAG.getConstant(0, HalfT));
10803 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10804 DAG.getConstant(1, HalfT));
10805 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10806 Regs64bit ? X86::RBX : X86::EBX,
10807 swapInL, cpInH.getValue(1));
10808 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10809 Regs64bit ? X86::RCX : X86::ECX,
10810 swapInH, swapInL.getValue(1));
10811 SDValue Ops[] = { swapInH.getValue(0),
10813 swapInH.getValue(1) };
10814 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10815 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10816 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10817 X86ISD::LCMPXCHG8_DAG;
10818 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10820 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10821 Regs64bit ? X86::RAX : X86::EAX,
10822 HalfT, Result.getValue(1));
10823 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10824 Regs64bit ? X86::RDX : X86::EDX,
10825 HalfT, cpOutL.getValue(2));
10826 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10827 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10828 Results.push_back(cpOutH.getValue(1));
10831 case ISD::ATOMIC_LOAD_ADD:
10832 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10834 case ISD::ATOMIC_LOAD_AND:
10835 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10837 case ISD::ATOMIC_LOAD_NAND:
10838 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10840 case ISD::ATOMIC_LOAD_OR:
10841 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10843 case ISD::ATOMIC_LOAD_SUB:
10844 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10846 case ISD::ATOMIC_LOAD_XOR:
10847 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10849 case ISD::ATOMIC_SWAP:
10850 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10852 case ISD::ATOMIC_LOAD:
10853 ReplaceATOMIC_LOAD(N, Results, DAG);
10857 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10859 default: return NULL;
10860 case X86ISD::BSF: return "X86ISD::BSF";
10861 case X86ISD::BSR: return "X86ISD::BSR";
10862 case X86ISD::SHLD: return "X86ISD::SHLD";
10863 case X86ISD::SHRD: return "X86ISD::SHRD";
10864 case X86ISD::FAND: return "X86ISD::FAND";
10865 case X86ISD::FOR: return "X86ISD::FOR";
10866 case X86ISD::FXOR: return "X86ISD::FXOR";
10867 case X86ISD::FSRL: return "X86ISD::FSRL";
10868 case X86ISD::FILD: return "X86ISD::FILD";
10869 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10870 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10871 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10872 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10873 case X86ISD::FLD: return "X86ISD::FLD";
10874 case X86ISD::FST: return "X86ISD::FST";
10875 case X86ISD::CALL: return "X86ISD::CALL";
10876 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10877 case X86ISD::BT: return "X86ISD::BT";
10878 case X86ISD::CMP: return "X86ISD::CMP";
10879 case X86ISD::COMI: return "X86ISD::COMI";
10880 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10881 case X86ISD::SETCC: return "X86ISD::SETCC";
10882 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10883 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10884 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10885 case X86ISD::CMOV: return "X86ISD::CMOV";
10886 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10887 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10888 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10889 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10890 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10891 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10892 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10893 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10894 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10895 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10896 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10897 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10898 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10899 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10900 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10901 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10902 case X86ISD::HADD: return "X86ISD::HADD";
10903 case X86ISD::HSUB: return "X86ISD::HSUB";
10904 case X86ISD::FHADD: return "X86ISD::FHADD";
10905 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10906 case X86ISD::FMAX: return "X86ISD::FMAX";
10907 case X86ISD::FMIN: return "X86ISD::FMIN";
10908 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10909 case X86ISD::FRCP: return "X86ISD::FRCP";
10910 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10911 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10912 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10913 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10914 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10915 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10916 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10917 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10918 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10919 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10920 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10921 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10922 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10923 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10924 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10925 case X86ISD::VSHL: return "X86ISD::VSHL";
10926 case X86ISD::VSRL: return "X86ISD::VSRL";
10927 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10928 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10929 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10930 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10931 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10932 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10933 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10934 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10935 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10936 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10937 case X86ISD::ADD: return "X86ISD::ADD";
10938 case X86ISD::SUB: return "X86ISD::SUB";
10939 case X86ISD::ADC: return "X86ISD::ADC";
10940 case X86ISD::SBB: return "X86ISD::SBB";
10941 case X86ISD::SMUL: return "X86ISD::SMUL";
10942 case X86ISD::UMUL: return "X86ISD::UMUL";
10943 case X86ISD::INC: return "X86ISD::INC";
10944 case X86ISD::DEC: return "X86ISD::DEC";
10945 case X86ISD::OR: return "X86ISD::OR";
10946 case X86ISD::XOR: return "X86ISD::XOR";
10947 case X86ISD::AND: return "X86ISD::AND";
10948 case X86ISD::ANDN: return "X86ISD::ANDN";
10949 case X86ISD::BLSI: return "X86ISD::BLSI";
10950 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10951 case X86ISD::BLSR: return "X86ISD::BLSR";
10952 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10953 case X86ISD::PTEST: return "X86ISD::PTEST";
10954 case X86ISD::TESTP: return "X86ISD::TESTP";
10955 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10956 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10957 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10958 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10959 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10960 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10961 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10962 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10963 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10964 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10965 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10966 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10967 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10968 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10969 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10970 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10971 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10972 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10973 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10974 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10975 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10976 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
10977 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
10978 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10979 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
10980 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
10981 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10982 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10983 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10984 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10985 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10989 // isLegalAddressingMode - Return true if the addressing mode represented
10990 // by AM is legal for this target, for a load/store of the specified type.
10991 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10993 // X86 supports extremely general addressing modes.
10994 CodeModel::Model M = getTargetMachine().getCodeModel();
10995 Reloc::Model R = getTargetMachine().getRelocationModel();
10997 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10998 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11003 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11005 // If a reference to this global requires an extra load, we can't fold it.
11006 if (isGlobalStubReference(GVFlags))
11009 // If BaseGV requires a register for the PIC base, we cannot also have a
11010 // BaseReg specified.
11011 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11014 // If lower 4G is not available, then we must use rip-relative addressing.
11015 if ((M != CodeModel::Small || R != Reloc::Static) &&
11016 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11020 switch (AM.Scale) {
11026 // These scales always work.
11031 // These scales are formed with basereg+scalereg. Only accept if there is
11036 default: // Other stuff never works.
11044 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11045 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11047 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11048 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11049 if (NumBits1 <= NumBits2)
11054 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11055 if (!VT1.isInteger() || !VT2.isInteger())
11057 unsigned NumBits1 = VT1.getSizeInBits();
11058 unsigned NumBits2 = VT2.getSizeInBits();
11059 if (NumBits1 <= NumBits2)
11064 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11065 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11066 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11069 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11070 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11071 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11074 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11075 // i16 instructions are longer (0x66 prefix) and potentially slower.
11076 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11079 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11080 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11081 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11082 /// are assumed to be legal.
11084 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11086 // Very little shuffling can be done for 64-bit vectors right now.
11087 if (VT.getSizeInBits() == 64)
11090 // FIXME: pshufb, blends, shifts.
11091 return (VT.getVectorNumElements() == 2 ||
11092 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11093 isMOVLMask(M, VT) ||
11094 isSHUFPMask(M, VT) ||
11095 isPSHUFDMask(M, VT) ||
11096 isPSHUFHWMask(M, VT) ||
11097 isPSHUFLWMask(M, VT) ||
11098 isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()) ||
11099 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11100 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11101 isUNPCKL_v_undef_Mask(M, VT) ||
11102 isUNPCKH_v_undef_Mask(M, VT));
11106 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11108 unsigned NumElts = VT.getVectorNumElements();
11109 // FIXME: This collection of masks seems suspect.
11112 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11113 return (isMOVLMask(Mask, VT) ||
11114 isCommutedMOVLMask(Mask, VT, true) ||
11115 isSHUFPMask(Mask, VT) ||
11116 isSHUFPMask(Mask, VT, /* Commuted */ true));
11121 //===----------------------------------------------------------------------===//
11122 // X86 Scheduler Hooks
11123 //===----------------------------------------------------------------------===//
11125 // private utility function
11126 MachineBasicBlock *
11127 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11128 MachineBasicBlock *MBB,
11135 TargetRegisterClass *RC,
11136 bool invSrc) const {
11137 // For the atomic bitwise operator, we generate
11140 // ld t1 = [bitinstr.addr]
11141 // op t2 = t1, [bitinstr.val]
11143 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11145 // fallthrough -->nextMBB
11146 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11147 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11148 MachineFunction::iterator MBBIter = MBB;
11151 /// First build the CFG
11152 MachineFunction *F = MBB->getParent();
11153 MachineBasicBlock *thisMBB = MBB;
11154 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11155 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11156 F->insert(MBBIter, newMBB);
11157 F->insert(MBBIter, nextMBB);
11159 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11160 nextMBB->splice(nextMBB->begin(), thisMBB,
11161 llvm::next(MachineBasicBlock::iterator(bInstr)),
11163 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11165 // Update thisMBB to fall through to newMBB
11166 thisMBB->addSuccessor(newMBB);
11168 // newMBB jumps to itself and fall through to nextMBB
11169 newMBB->addSuccessor(nextMBB);
11170 newMBB->addSuccessor(newMBB);
11172 // Insert instructions into newMBB based on incoming instruction
11173 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11174 "unexpected number of operands");
11175 DebugLoc dl = bInstr->getDebugLoc();
11176 MachineOperand& destOper = bInstr->getOperand(0);
11177 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11178 int numArgs = bInstr->getNumOperands() - 1;
11179 for (int i=0; i < numArgs; ++i)
11180 argOpers[i] = &bInstr->getOperand(i+1);
11182 // x86 address has 4 operands: base, index, scale, and displacement
11183 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11184 int valArgIndx = lastAddrIndx + 1;
11186 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11187 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11188 for (int i=0; i <= lastAddrIndx; ++i)
11189 (*MIB).addOperand(*argOpers[i]);
11191 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11193 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11198 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11199 assert((argOpers[valArgIndx]->isReg() ||
11200 argOpers[valArgIndx]->isImm()) &&
11201 "invalid operand");
11202 if (argOpers[valArgIndx]->isReg())
11203 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11205 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11207 (*MIB).addOperand(*argOpers[valArgIndx]);
11209 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11212 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11213 for (int i=0; i <= lastAddrIndx; ++i)
11214 (*MIB).addOperand(*argOpers[i]);
11216 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11217 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11218 bInstr->memoperands_end());
11220 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11221 MIB.addReg(EAXreg);
11224 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11226 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11230 // private utility function: 64 bit atomics on 32 bit host.
11231 MachineBasicBlock *
11232 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11233 MachineBasicBlock *MBB,
11238 bool invSrc) const {
11239 // For the atomic bitwise operator, we generate
11240 // thisMBB (instructions are in pairs, except cmpxchg8b)
11241 // ld t1,t2 = [bitinstr.addr]
11243 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11244 // op t5, t6 <- out1, out2, [bitinstr.val]
11245 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11246 // mov ECX, EBX <- t5, t6
11247 // mov EAX, EDX <- t1, t2
11248 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11249 // mov t3, t4 <- EAX, EDX
11251 // result in out1, out2
11252 // fallthrough -->nextMBB
11254 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11255 const unsigned LoadOpc = X86::MOV32rm;
11256 const unsigned NotOpc = X86::NOT32r;
11257 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11258 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11259 MachineFunction::iterator MBBIter = MBB;
11262 /// First build the CFG
11263 MachineFunction *F = MBB->getParent();
11264 MachineBasicBlock *thisMBB = MBB;
11265 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11266 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11267 F->insert(MBBIter, newMBB);
11268 F->insert(MBBIter, nextMBB);
11270 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11271 nextMBB->splice(nextMBB->begin(), thisMBB,
11272 llvm::next(MachineBasicBlock::iterator(bInstr)),
11274 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11276 // Update thisMBB to fall through to newMBB
11277 thisMBB->addSuccessor(newMBB);
11279 // newMBB jumps to itself and fall through to nextMBB
11280 newMBB->addSuccessor(nextMBB);
11281 newMBB->addSuccessor(newMBB);
11283 DebugLoc dl = bInstr->getDebugLoc();
11284 // Insert instructions into newMBB based on incoming instruction
11285 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11286 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11287 "unexpected number of operands");
11288 MachineOperand& dest1Oper = bInstr->getOperand(0);
11289 MachineOperand& dest2Oper = bInstr->getOperand(1);
11290 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11291 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11292 argOpers[i] = &bInstr->getOperand(i+2);
11294 // We use some of the operands multiple times, so conservatively just
11295 // clear any kill flags that might be present.
11296 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11297 argOpers[i]->setIsKill(false);
11300 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11301 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11303 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11304 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11305 for (int i=0; i <= lastAddrIndx; ++i)
11306 (*MIB).addOperand(*argOpers[i]);
11307 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11308 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11309 // add 4 to displacement.
11310 for (int i=0; i <= lastAddrIndx-2; ++i)
11311 (*MIB).addOperand(*argOpers[i]);
11312 MachineOperand newOp3 = *(argOpers[3]);
11313 if (newOp3.isImm())
11314 newOp3.setImm(newOp3.getImm()+4);
11316 newOp3.setOffset(newOp3.getOffset()+4);
11317 (*MIB).addOperand(newOp3);
11318 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11320 // t3/4 are defined later, at the bottom of the loop
11321 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11322 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11323 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11324 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11325 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11326 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11328 // The subsequent operations should be using the destination registers of
11329 //the PHI instructions.
11331 t1 = F->getRegInfo().createVirtualRegister(RC);
11332 t2 = F->getRegInfo().createVirtualRegister(RC);
11333 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11334 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11336 t1 = dest1Oper.getReg();
11337 t2 = dest2Oper.getReg();
11340 int valArgIndx = lastAddrIndx + 1;
11341 assert((argOpers[valArgIndx]->isReg() ||
11342 argOpers[valArgIndx]->isImm()) &&
11343 "invalid operand");
11344 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11345 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11346 if (argOpers[valArgIndx]->isReg())
11347 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11349 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11350 if (regOpcL != X86::MOV32rr)
11352 (*MIB).addOperand(*argOpers[valArgIndx]);
11353 assert(argOpers[valArgIndx + 1]->isReg() ==
11354 argOpers[valArgIndx]->isReg());
11355 assert(argOpers[valArgIndx + 1]->isImm() ==
11356 argOpers[valArgIndx]->isImm());
11357 if (argOpers[valArgIndx + 1]->isReg())
11358 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11360 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11361 if (regOpcH != X86::MOV32rr)
11363 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11365 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11367 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11370 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11372 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11375 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11376 for (int i=0; i <= lastAddrIndx; ++i)
11377 (*MIB).addOperand(*argOpers[i]);
11379 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11380 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11381 bInstr->memoperands_end());
11383 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11384 MIB.addReg(X86::EAX);
11385 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11386 MIB.addReg(X86::EDX);
11389 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11391 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11395 // private utility function
11396 MachineBasicBlock *
11397 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11398 MachineBasicBlock *MBB,
11399 unsigned cmovOpc) const {
11400 // For the atomic min/max operator, we generate
11403 // ld t1 = [min/max.addr]
11404 // mov t2 = [min/max.val]
11406 // cmov[cond] t2 = t1
11408 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11410 // fallthrough -->nextMBB
11412 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11413 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11414 MachineFunction::iterator MBBIter = MBB;
11417 /// First build the CFG
11418 MachineFunction *F = MBB->getParent();
11419 MachineBasicBlock *thisMBB = MBB;
11420 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11421 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11422 F->insert(MBBIter, newMBB);
11423 F->insert(MBBIter, nextMBB);
11425 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11426 nextMBB->splice(nextMBB->begin(), thisMBB,
11427 llvm::next(MachineBasicBlock::iterator(mInstr)),
11429 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11431 // Update thisMBB to fall through to newMBB
11432 thisMBB->addSuccessor(newMBB);
11434 // newMBB jumps to newMBB and fall through to nextMBB
11435 newMBB->addSuccessor(nextMBB);
11436 newMBB->addSuccessor(newMBB);
11438 DebugLoc dl = mInstr->getDebugLoc();
11439 // Insert instructions into newMBB based on incoming instruction
11440 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11441 "unexpected number of operands");
11442 MachineOperand& destOper = mInstr->getOperand(0);
11443 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11444 int numArgs = mInstr->getNumOperands() - 1;
11445 for (int i=0; i < numArgs; ++i)
11446 argOpers[i] = &mInstr->getOperand(i+1);
11448 // x86 address has 4 operands: base, index, scale, and displacement
11449 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11450 int valArgIndx = lastAddrIndx + 1;
11452 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11453 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11454 for (int i=0; i <= lastAddrIndx; ++i)
11455 (*MIB).addOperand(*argOpers[i]);
11457 // We only support register and immediate values
11458 assert((argOpers[valArgIndx]->isReg() ||
11459 argOpers[valArgIndx]->isImm()) &&
11460 "invalid operand");
11462 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11463 if (argOpers[valArgIndx]->isReg())
11464 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11466 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11467 (*MIB).addOperand(*argOpers[valArgIndx]);
11469 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11472 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11477 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11478 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11482 // Cmp and exchange if none has modified the memory location
11483 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11484 for (int i=0; i <= lastAddrIndx; ++i)
11485 (*MIB).addOperand(*argOpers[i]);
11487 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11488 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11489 mInstr->memoperands_end());
11491 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11492 MIB.addReg(X86::EAX);
11495 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11497 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11501 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11502 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11503 // in the .td file.
11504 MachineBasicBlock *
11505 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11506 unsigned numArgs, bool memArg) const {
11507 assert(Subtarget->hasSSE42orAVX() &&
11508 "Target must have SSE4.2 or AVX features enabled");
11510 DebugLoc dl = MI->getDebugLoc();
11511 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11513 if (!Subtarget->hasAVX()) {
11515 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11517 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11520 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11522 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11525 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11526 for (unsigned i = 0; i < numArgs; ++i) {
11527 MachineOperand &Op = MI->getOperand(i+1);
11528 if (!(Op.isReg() && Op.isImplicit()))
11529 MIB.addOperand(Op);
11531 BuildMI(*BB, MI, dl,
11532 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11533 MI->getOperand(0).getReg())
11534 .addReg(X86::XMM0);
11536 MI->eraseFromParent();
11540 MachineBasicBlock *
11541 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11542 DebugLoc dl = MI->getDebugLoc();
11543 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11545 // Address into RAX/EAX, other two args into ECX, EDX.
11546 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11547 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11548 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11549 for (int i = 0; i < X86::AddrNumOperands; ++i)
11550 MIB.addOperand(MI->getOperand(i));
11552 unsigned ValOps = X86::AddrNumOperands;
11553 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11554 .addReg(MI->getOperand(ValOps).getReg());
11555 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11556 .addReg(MI->getOperand(ValOps+1).getReg());
11558 // The instruction doesn't actually take any operands though.
11559 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11561 MI->eraseFromParent(); // The pseudo is gone now.
11565 MachineBasicBlock *
11566 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11567 DebugLoc dl = MI->getDebugLoc();
11568 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11570 // First arg in ECX, the second in EAX.
11571 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11572 .addReg(MI->getOperand(0).getReg());
11573 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11574 .addReg(MI->getOperand(1).getReg());
11576 // The instruction doesn't actually take any operands though.
11577 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11579 MI->eraseFromParent(); // The pseudo is gone now.
11583 MachineBasicBlock *
11584 X86TargetLowering::EmitVAARG64WithCustomInserter(
11586 MachineBasicBlock *MBB) const {
11587 // Emit va_arg instruction on X86-64.
11589 // Operands to this pseudo-instruction:
11590 // 0 ) Output : destination address (reg)
11591 // 1-5) Input : va_list address (addr, i64mem)
11592 // 6 ) ArgSize : Size (in bytes) of vararg type
11593 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11594 // 8 ) Align : Alignment of type
11595 // 9 ) EFLAGS (implicit-def)
11597 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11598 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11600 unsigned DestReg = MI->getOperand(0).getReg();
11601 MachineOperand &Base = MI->getOperand(1);
11602 MachineOperand &Scale = MI->getOperand(2);
11603 MachineOperand &Index = MI->getOperand(3);
11604 MachineOperand &Disp = MI->getOperand(4);
11605 MachineOperand &Segment = MI->getOperand(5);
11606 unsigned ArgSize = MI->getOperand(6).getImm();
11607 unsigned ArgMode = MI->getOperand(7).getImm();
11608 unsigned Align = MI->getOperand(8).getImm();
11610 // Memory Reference
11611 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11612 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11613 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11615 // Machine Information
11616 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11617 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11618 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11619 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11620 DebugLoc DL = MI->getDebugLoc();
11622 // struct va_list {
11625 // i64 overflow_area (address)
11626 // i64 reg_save_area (address)
11628 // sizeof(va_list) = 24
11629 // alignment(va_list) = 8
11631 unsigned TotalNumIntRegs = 6;
11632 unsigned TotalNumXMMRegs = 8;
11633 bool UseGPOffset = (ArgMode == 1);
11634 bool UseFPOffset = (ArgMode == 2);
11635 unsigned MaxOffset = TotalNumIntRegs * 8 +
11636 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11638 /* Align ArgSize to a multiple of 8 */
11639 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11640 bool NeedsAlign = (Align > 8);
11642 MachineBasicBlock *thisMBB = MBB;
11643 MachineBasicBlock *overflowMBB;
11644 MachineBasicBlock *offsetMBB;
11645 MachineBasicBlock *endMBB;
11647 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11648 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11649 unsigned OffsetReg = 0;
11651 if (!UseGPOffset && !UseFPOffset) {
11652 // If we only pull from the overflow region, we don't create a branch.
11653 // We don't need to alter control flow.
11654 OffsetDestReg = 0; // unused
11655 OverflowDestReg = DestReg;
11658 overflowMBB = thisMBB;
11661 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11662 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11663 // If not, pull from overflow_area. (branch to overflowMBB)
11668 // offsetMBB overflowMBB
11673 // Registers for the PHI in endMBB
11674 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11675 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11677 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11678 MachineFunction *MF = MBB->getParent();
11679 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11680 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11681 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11683 MachineFunction::iterator MBBIter = MBB;
11686 // Insert the new basic blocks
11687 MF->insert(MBBIter, offsetMBB);
11688 MF->insert(MBBIter, overflowMBB);
11689 MF->insert(MBBIter, endMBB);
11691 // Transfer the remainder of MBB and its successor edges to endMBB.
11692 endMBB->splice(endMBB->begin(), thisMBB,
11693 llvm::next(MachineBasicBlock::iterator(MI)),
11695 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11697 // Make offsetMBB and overflowMBB successors of thisMBB
11698 thisMBB->addSuccessor(offsetMBB);
11699 thisMBB->addSuccessor(overflowMBB);
11701 // endMBB is a successor of both offsetMBB and overflowMBB
11702 offsetMBB->addSuccessor(endMBB);
11703 overflowMBB->addSuccessor(endMBB);
11705 // Load the offset value into a register
11706 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11707 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11711 .addDisp(Disp, UseFPOffset ? 4 : 0)
11712 .addOperand(Segment)
11713 .setMemRefs(MMOBegin, MMOEnd);
11715 // Check if there is enough room left to pull this argument.
11716 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11718 .addImm(MaxOffset + 8 - ArgSizeA8);
11720 // Branch to "overflowMBB" if offset >= max
11721 // Fall through to "offsetMBB" otherwise
11722 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11723 .addMBB(overflowMBB);
11726 // In offsetMBB, emit code to use the reg_save_area.
11728 assert(OffsetReg != 0);
11730 // Read the reg_save_area address.
11731 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11732 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11737 .addOperand(Segment)
11738 .setMemRefs(MMOBegin, MMOEnd);
11740 // Zero-extend the offset
11741 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11742 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11745 .addImm(X86::sub_32bit);
11747 // Add the offset to the reg_save_area to get the final address.
11748 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11749 .addReg(OffsetReg64)
11750 .addReg(RegSaveReg);
11752 // Compute the offset for the next argument
11753 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11754 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11756 .addImm(UseFPOffset ? 16 : 8);
11758 // Store it back into the va_list.
11759 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11763 .addDisp(Disp, UseFPOffset ? 4 : 0)
11764 .addOperand(Segment)
11765 .addReg(NextOffsetReg)
11766 .setMemRefs(MMOBegin, MMOEnd);
11769 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11774 // Emit code to use overflow area
11777 // Load the overflow_area address into a register.
11778 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11779 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11784 .addOperand(Segment)
11785 .setMemRefs(MMOBegin, MMOEnd);
11787 // If we need to align it, do so. Otherwise, just copy the address
11788 // to OverflowDestReg.
11790 // Align the overflow address
11791 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11792 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11794 // aligned_addr = (addr + (align-1)) & ~(align-1)
11795 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11796 .addReg(OverflowAddrReg)
11799 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11801 .addImm(~(uint64_t)(Align-1));
11803 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11804 .addReg(OverflowAddrReg);
11807 // Compute the next overflow address after this argument.
11808 // (the overflow address should be kept 8-byte aligned)
11809 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11810 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11811 .addReg(OverflowDestReg)
11812 .addImm(ArgSizeA8);
11814 // Store the new overflow address.
11815 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11820 .addOperand(Segment)
11821 .addReg(NextAddrReg)
11822 .setMemRefs(MMOBegin, MMOEnd);
11824 // If we branched, emit the PHI to the front of endMBB.
11826 BuildMI(*endMBB, endMBB->begin(), DL,
11827 TII->get(X86::PHI), DestReg)
11828 .addReg(OffsetDestReg).addMBB(offsetMBB)
11829 .addReg(OverflowDestReg).addMBB(overflowMBB);
11832 // Erase the pseudo instruction
11833 MI->eraseFromParent();
11838 MachineBasicBlock *
11839 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11841 MachineBasicBlock *MBB) const {
11842 // Emit code to save XMM registers to the stack. The ABI says that the
11843 // number of registers to save is given in %al, so it's theoretically
11844 // possible to do an indirect jump trick to avoid saving all of them,
11845 // however this code takes a simpler approach and just executes all
11846 // of the stores if %al is non-zero. It's less code, and it's probably
11847 // easier on the hardware branch predictor, and stores aren't all that
11848 // expensive anyway.
11850 // Create the new basic blocks. One block contains all the XMM stores,
11851 // and one block is the final destination regardless of whether any
11852 // stores were performed.
11853 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11854 MachineFunction *F = MBB->getParent();
11855 MachineFunction::iterator MBBIter = MBB;
11857 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11858 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11859 F->insert(MBBIter, XMMSaveMBB);
11860 F->insert(MBBIter, EndMBB);
11862 // Transfer the remainder of MBB and its successor edges to EndMBB.
11863 EndMBB->splice(EndMBB->begin(), MBB,
11864 llvm::next(MachineBasicBlock::iterator(MI)),
11866 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11868 // The original block will now fall through to the XMM save block.
11869 MBB->addSuccessor(XMMSaveMBB);
11870 // The XMMSaveMBB will fall through to the end block.
11871 XMMSaveMBB->addSuccessor(EndMBB);
11873 // Now add the instructions.
11874 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11875 DebugLoc DL = MI->getDebugLoc();
11877 unsigned CountReg = MI->getOperand(0).getReg();
11878 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11879 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11881 if (!Subtarget->isTargetWin64()) {
11882 // If %al is 0, branch around the XMM save block.
11883 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11884 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11885 MBB->addSuccessor(EndMBB);
11888 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11889 // In the XMM save block, save all the XMM argument registers.
11890 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11891 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11892 MachineMemOperand *MMO =
11893 F->getMachineMemOperand(
11894 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11895 MachineMemOperand::MOStore,
11896 /*Size=*/16, /*Align=*/16);
11897 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11898 .addFrameIndex(RegSaveFrameIndex)
11899 .addImm(/*Scale=*/1)
11900 .addReg(/*IndexReg=*/0)
11901 .addImm(/*Disp=*/Offset)
11902 .addReg(/*Segment=*/0)
11903 .addReg(MI->getOperand(i).getReg())
11904 .addMemOperand(MMO);
11907 MI->eraseFromParent(); // The pseudo instruction is gone now.
11912 MachineBasicBlock *
11913 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11914 MachineBasicBlock *BB) const {
11915 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11916 DebugLoc DL = MI->getDebugLoc();
11918 // To "insert" a SELECT_CC instruction, we actually have to insert the
11919 // diamond control-flow pattern. The incoming instruction knows the
11920 // destination vreg to set, the condition code register to branch on, the
11921 // true/false values to select between, and a branch opcode to use.
11922 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11923 MachineFunction::iterator It = BB;
11929 // cmpTY ccX, r1, r2
11931 // fallthrough --> copy0MBB
11932 MachineBasicBlock *thisMBB = BB;
11933 MachineFunction *F = BB->getParent();
11934 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11935 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11936 F->insert(It, copy0MBB);
11937 F->insert(It, sinkMBB);
11939 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11940 // live into the sink and copy blocks.
11941 if (!MI->killsRegister(X86::EFLAGS)) {
11942 copy0MBB->addLiveIn(X86::EFLAGS);
11943 sinkMBB->addLiveIn(X86::EFLAGS);
11946 // Transfer the remainder of BB and its successor edges to sinkMBB.
11947 sinkMBB->splice(sinkMBB->begin(), BB,
11948 llvm::next(MachineBasicBlock::iterator(MI)),
11950 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11952 // Add the true and fallthrough blocks as its successors.
11953 BB->addSuccessor(copy0MBB);
11954 BB->addSuccessor(sinkMBB);
11956 // Create the conditional branch instruction.
11958 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11959 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11962 // %FalseValue = ...
11963 // # fallthrough to sinkMBB
11964 copy0MBB->addSuccessor(sinkMBB);
11967 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11969 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11970 TII->get(X86::PHI), MI->getOperand(0).getReg())
11971 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11972 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11974 MI->eraseFromParent(); // The pseudo instruction is gone now.
11978 MachineBasicBlock *
11979 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11980 bool Is64Bit) const {
11981 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11982 DebugLoc DL = MI->getDebugLoc();
11983 MachineFunction *MF = BB->getParent();
11984 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11986 assert(getTargetMachine().Options.EnableSegmentedStacks);
11988 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11989 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11992 // ... [Till the alloca]
11993 // If stacklet is not large enough, jump to mallocMBB
11996 // Allocate by subtracting from RSP
11997 // Jump to continueMBB
12000 // Allocate by call to runtime
12004 // [rest of original BB]
12007 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12008 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12009 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12011 MachineRegisterInfo &MRI = MF->getRegInfo();
12012 const TargetRegisterClass *AddrRegClass =
12013 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12015 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12016 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12017 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12018 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12019 sizeVReg = MI->getOperand(1).getReg(),
12020 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12022 MachineFunction::iterator MBBIter = BB;
12025 MF->insert(MBBIter, bumpMBB);
12026 MF->insert(MBBIter, mallocMBB);
12027 MF->insert(MBBIter, continueMBB);
12029 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12030 (MachineBasicBlock::iterator(MI)), BB->end());
12031 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12033 // Add code to the main basic block to check if the stack limit has been hit,
12034 // and if so, jump to mallocMBB otherwise to bumpMBB.
12035 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12036 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12037 .addReg(tmpSPVReg).addReg(sizeVReg);
12038 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12039 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12040 .addReg(SPLimitVReg);
12041 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12043 // bumpMBB simply decreases the stack pointer, since we know the current
12044 // stacklet has enough space.
12045 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12046 .addReg(SPLimitVReg);
12047 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12048 .addReg(SPLimitVReg);
12049 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12051 // Calls into a routine in libgcc to allocate more space from the heap.
12053 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12055 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12056 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12058 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12060 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12061 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12062 .addExternalSymbol("__morestack_allocate_stack_space");
12066 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12069 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12070 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12071 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12073 // Set up the CFG correctly.
12074 BB->addSuccessor(bumpMBB);
12075 BB->addSuccessor(mallocMBB);
12076 mallocMBB->addSuccessor(continueMBB);
12077 bumpMBB->addSuccessor(continueMBB);
12079 // Take care of the PHI nodes.
12080 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12081 MI->getOperand(0).getReg())
12082 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12083 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12085 // Delete the original pseudo instruction.
12086 MI->eraseFromParent();
12089 return continueMBB;
12092 MachineBasicBlock *
12093 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12094 MachineBasicBlock *BB) const {
12095 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12096 DebugLoc DL = MI->getDebugLoc();
12098 assert(!Subtarget->isTargetEnvMacho());
12100 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12101 // non-trivial part is impdef of ESP.
12103 if (Subtarget->isTargetWin64()) {
12104 if (Subtarget->isTargetCygMing()) {
12105 // ___chkstk(Mingw64):
12106 // Clobbers R10, R11, RAX and EFLAGS.
12108 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12109 .addExternalSymbol("___chkstk")
12110 .addReg(X86::RAX, RegState::Implicit)
12111 .addReg(X86::RSP, RegState::Implicit)
12112 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12113 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12114 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12116 // __chkstk(MSVCRT): does not update stack pointer.
12117 // Clobbers R10, R11 and EFLAGS.
12118 // FIXME: RAX(allocated size) might be reused and not killed.
12119 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12120 .addExternalSymbol("__chkstk")
12121 .addReg(X86::RAX, RegState::Implicit)
12122 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12123 // RAX has the offset to subtracted from RSP.
12124 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12129 const char *StackProbeSymbol =
12130 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12132 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12133 .addExternalSymbol(StackProbeSymbol)
12134 .addReg(X86::EAX, RegState::Implicit)
12135 .addReg(X86::ESP, RegState::Implicit)
12136 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12137 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12138 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12141 MI->eraseFromParent(); // The pseudo instruction is gone now.
12145 MachineBasicBlock *
12146 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12147 MachineBasicBlock *BB) const {
12148 // This is pretty easy. We're taking the value that we received from
12149 // our load from the relocation, sticking it in either RDI (x86-64)
12150 // or EAX and doing an indirect call. The return value will then
12151 // be in the normal return register.
12152 const X86InstrInfo *TII
12153 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12154 DebugLoc DL = MI->getDebugLoc();
12155 MachineFunction *F = BB->getParent();
12157 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12158 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12160 if (Subtarget->is64Bit()) {
12161 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12162 TII->get(X86::MOV64rm), X86::RDI)
12164 .addImm(0).addReg(0)
12165 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12166 MI->getOperand(3).getTargetFlags())
12168 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12169 addDirectMem(MIB, X86::RDI);
12170 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12171 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12172 TII->get(X86::MOV32rm), X86::EAX)
12174 .addImm(0).addReg(0)
12175 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12176 MI->getOperand(3).getTargetFlags())
12178 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12179 addDirectMem(MIB, X86::EAX);
12181 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12182 TII->get(X86::MOV32rm), X86::EAX)
12183 .addReg(TII->getGlobalBaseReg(F))
12184 .addImm(0).addReg(0)
12185 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12186 MI->getOperand(3).getTargetFlags())
12188 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12189 addDirectMem(MIB, X86::EAX);
12192 MI->eraseFromParent(); // The pseudo instruction is gone now.
12196 MachineBasicBlock *
12197 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12198 MachineBasicBlock *BB) const {
12199 switch (MI->getOpcode()) {
12200 default: assert(0 && "Unexpected instr type to insert");
12201 case X86::TAILJMPd64:
12202 case X86::TAILJMPr64:
12203 case X86::TAILJMPm64:
12204 assert(0 && "TAILJMP64 would not be touched here.");
12205 case X86::TCRETURNdi64:
12206 case X86::TCRETURNri64:
12207 case X86::TCRETURNmi64:
12208 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12209 // On AMD64, additional defs should be added before register allocation.
12210 if (!Subtarget->isTargetWin64()) {
12211 MI->addRegisterDefined(X86::RSI);
12212 MI->addRegisterDefined(X86::RDI);
12213 MI->addRegisterDefined(X86::XMM6);
12214 MI->addRegisterDefined(X86::XMM7);
12215 MI->addRegisterDefined(X86::XMM8);
12216 MI->addRegisterDefined(X86::XMM9);
12217 MI->addRegisterDefined(X86::XMM10);
12218 MI->addRegisterDefined(X86::XMM11);
12219 MI->addRegisterDefined(X86::XMM12);
12220 MI->addRegisterDefined(X86::XMM13);
12221 MI->addRegisterDefined(X86::XMM14);
12222 MI->addRegisterDefined(X86::XMM15);
12225 case X86::WIN_ALLOCA:
12226 return EmitLoweredWinAlloca(MI, BB);
12227 case X86::SEG_ALLOCA_32:
12228 return EmitLoweredSegAlloca(MI, BB, false);
12229 case X86::SEG_ALLOCA_64:
12230 return EmitLoweredSegAlloca(MI, BB, true);
12231 case X86::TLSCall_32:
12232 case X86::TLSCall_64:
12233 return EmitLoweredTLSCall(MI, BB);
12234 case X86::CMOV_GR8:
12235 case X86::CMOV_FR32:
12236 case X86::CMOV_FR64:
12237 case X86::CMOV_V4F32:
12238 case X86::CMOV_V2F64:
12239 case X86::CMOV_V2I64:
12240 case X86::CMOV_V8F32:
12241 case X86::CMOV_V4F64:
12242 case X86::CMOV_V4I64:
12243 case X86::CMOV_GR16:
12244 case X86::CMOV_GR32:
12245 case X86::CMOV_RFP32:
12246 case X86::CMOV_RFP64:
12247 case X86::CMOV_RFP80:
12248 return EmitLoweredSelect(MI, BB);
12250 case X86::FP32_TO_INT16_IN_MEM:
12251 case X86::FP32_TO_INT32_IN_MEM:
12252 case X86::FP32_TO_INT64_IN_MEM:
12253 case X86::FP64_TO_INT16_IN_MEM:
12254 case X86::FP64_TO_INT32_IN_MEM:
12255 case X86::FP64_TO_INT64_IN_MEM:
12256 case X86::FP80_TO_INT16_IN_MEM:
12257 case X86::FP80_TO_INT32_IN_MEM:
12258 case X86::FP80_TO_INT64_IN_MEM: {
12259 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12260 DebugLoc DL = MI->getDebugLoc();
12262 // Change the floating point control register to use "round towards zero"
12263 // mode when truncating to an integer value.
12264 MachineFunction *F = BB->getParent();
12265 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12266 addFrameReference(BuildMI(*BB, MI, DL,
12267 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12269 // Load the old value of the high byte of the control word...
12271 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12272 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12275 // Set the high part to be round to zero...
12276 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12279 // Reload the modified control word now...
12280 addFrameReference(BuildMI(*BB, MI, DL,
12281 TII->get(X86::FLDCW16m)), CWFrameIdx);
12283 // Restore the memory image of control word to original value
12284 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12287 // Get the X86 opcode to use.
12289 switch (MI->getOpcode()) {
12290 default: llvm_unreachable("illegal opcode!");
12291 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12292 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12293 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12294 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12295 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12296 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12297 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12298 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12299 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12303 MachineOperand &Op = MI->getOperand(0);
12305 AM.BaseType = X86AddressMode::RegBase;
12306 AM.Base.Reg = Op.getReg();
12308 AM.BaseType = X86AddressMode::FrameIndexBase;
12309 AM.Base.FrameIndex = Op.getIndex();
12311 Op = MI->getOperand(1);
12313 AM.Scale = Op.getImm();
12314 Op = MI->getOperand(2);
12316 AM.IndexReg = Op.getImm();
12317 Op = MI->getOperand(3);
12318 if (Op.isGlobal()) {
12319 AM.GV = Op.getGlobal();
12321 AM.Disp = Op.getImm();
12323 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12324 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12326 // Reload the original control word now.
12327 addFrameReference(BuildMI(*BB, MI, DL,
12328 TII->get(X86::FLDCW16m)), CWFrameIdx);
12330 MI->eraseFromParent(); // The pseudo instruction is gone now.
12333 // String/text processing lowering.
12334 case X86::PCMPISTRM128REG:
12335 case X86::VPCMPISTRM128REG:
12336 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12337 case X86::PCMPISTRM128MEM:
12338 case X86::VPCMPISTRM128MEM:
12339 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12340 case X86::PCMPESTRM128REG:
12341 case X86::VPCMPESTRM128REG:
12342 return EmitPCMP(MI, BB, 5, false /* in mem */);
12343 case X86::PCMPESTRM128MEM:
12344 case X86::VPCMPESTRM128MEM:
12345 return EmitPCMP(MI, BB, 5, true /* in mem */);
12347 // Thread synchronization.
12349 return EmitMonitor(MI, BB);
12351 return EmitMwait(MI, BB);
12353 // Atomic Lowering.
12354 case X86::ATOMAND32:
12355 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12356 X86::AND32ri, X86::MOV32rm,
12358 X86::NOT32r, X86::EAX,
12359 X86::GR32RegisterClass);
12360 case X86::ATOMOR32:
12361 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12362 X86::OR32ri, X86::MOV32rm,
12364 X86::NOT32r, X86::EAX,
12365 X86::GR32RegisterClass);
12366 case X86::ATOMXOR32:
12367 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12368 X86::XOR32ri, X86::MOV32rm,
12370 X86::NOT32r, X86::EAX,
12371 X86::GR32RegisterClass);
12372 case X86::ATOMNAND32:
12373 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12374 X86::AND32ri, X86::MOV32rm,
12376 X86::NOT32r, X86::EAX,
12377 X86::GR32RegisterClass, true);
12378 case X86::ATOMMIN32:
12379 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12380 case X86::ATOMMAX32:
12381 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12382 case X86::ATOMUMIN32:
12383 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12384 case X86::ATOMUMAX32:
12385 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12387 case X86::ATOMAND16:
12388 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12389 X86::AND16ri, X86::MOV16rm,
12391 X86::NOT16r, X86::AX,
12392 X86::GR16RegisterClass);
12393 case X86::ATOMOR16:
12394 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12395 X86::OR16ri, X86::MOV16rm,
12397 X86::NOT16r, X86::AX,
12398 X86::GR16RegisterClass);
12399 case X86::ATOMXOR16:
12400 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12401 X86::XOR16ri, X86::MOV16rm,
12403 X86::NOT16r, X86::AX,
12404 X86::GR16RegisterClass);
12405 case X86::ATOMNAND16:
12406 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12407 X86::AND16ri, X86::MOV16rm,
12409 X86::NOT16r, X86::AX,
12410 X86::GR16RegisterClass, true);
12411 case X86::ATOMMIN16:
12412 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12413 case X86::ATOMMAX16:
12414 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12415 case X86::ATOMUMIN16:
12416 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12417 case X86::ATOMUMAX16:
12418 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12420 case X86::ATOMAND8:
12421 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12422 X86::AND8ri, X86::MOV8rm,
12424 X86::NOT8r, X86::AL,
12425 X86::GR8RegisterClass);
12427 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12428 X86::OR8ri, X86::MOV8rm,
12430 X86::NOT8r, X86::AL,
12431 X86::GR8RegisterClass);
12432 case X86::ATOMXOR8:
12433 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12434 X86::XOR8ri, X86::MOV8rm,
12436 X86::NOT8r, X86::AL,
12437 X86::GR8RegisterClass);
12438 case X86::ATOMNAND8:
12439 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12440 X86::AND8ri, X86::MOV8rm,
12442 X86::NOT8r, X86::AL,
12443 X86::GR8RegisterClass, true);
12444 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12445 // This group is for 64-bit host.
12446 case X86::ATOMAND64:
12447 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12448 X86::AND64ri32, X86::MOV64rm,
12450 X86::NOT64r, X86::RAX,
12451 X86::GR64RegisterClass);
12452 case X86::ATOMOR64:
12453 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12454 X86::OR64ri32, X86::MOV64rm,
12456 X86::NOT64r, X86::RAX,
12457 X86::GR64RegisterClass);
12458 case X86::ATOMXOR64:
12459 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12460 X86::XOR64ri32, X86::MOV64rm,
12462 X86::NOT64r, X86::RAX,
12463 X86::GR64RegisterClass);
12464 case X86::ATOMNAND64:
12465 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12466 X86::AND64ri32, X86::MOV64rm,
12468 X86::NOT64r, X86::RAX,
12469 X86::GR64RegisterClass, true);
12470 case X86::ATOMMIN64:
12471 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12472 case X86::ATOMMAX64:
12473 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12474 case X86::ATOMUMIN64:
12475 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12476 case X86::ATOMUMAX64:
12477 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12479 // This group does 64-bit operations on a 32-bit host.
12480 case X86::ATOMAND6432:
12481 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12482 X86::AND32rr, X86::AND32rr,
12483 X86::AND32ri, X86::AND32ri,
12485 case X86::ATOMOR6432:
12486 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12487 X86::OR32rr, X86::OR32rr,
12488 X86::OR32ri, X86::OR32ri,
12490 case X86::ATOMXOR6432:
12491 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12492 X86::XOR32rr, X86::XOR32rr,
12493 X86::XOR32ri, X86::XOR32ri,
12495 case X86::ATOMNAND6432:
12496 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12497 X86::AND32rr, X86::AND32rr,
12498 X86::AND32ri, X86::AND32ri,
12500 case X86::ATOMADD6432:
12501 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12502 X86::ADD32rr, X86::ADC32rr,
12503 X86::ADD32ri, X86::ADC32ri,
12505 case X86::ATOMSUB6432:
12506 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12507 X86::SUB32rr, X86::SBB32rr,
12508 X86::SUB32ri, X86::SBB32ri,
12510 case X86::ATOMSWAP6432:
12511 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12512 X86::MOV32rr, X86::MOV32rr,
12513 X86::MOV32ri, X86::MOV32ri,
12515 case X86::VASTART_SAVE_XMM_REGS:
12516 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12518 case X86::VAARG_64:
12519 return EmitVAARG64WithCustomInserter(MI, BB);
12523 //===----------------------------------------------------------------------===//
12524 // X86 Optimization Hooks
12525 //===----------------------------------------------------------------------===//
12527 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12531 const SelectionDAG &DAG,
12532 unsigned Depth) const {
12533 unsigned Opc = Op.getOpcode();
12534 assert((Opc >= ISD::BUILTIN_OP_END ||
12535 Opc == ISD::INTRINSIC_WO_CHAIN ||
12536 Opc == ISD::INTRINSIC_W_CHAIN ||
12537 Opc == ISD::INTRINSIC_VOID) &&
12538 "Should use MaskedValueIsZero if you don't know whether Op"
12539 " is a target node!");
12541 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12555 // These nodes' second result is a boolean.
12556 if (Op.getResNo() == 0)
12559 case X86ISD::SETCC:
12560 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12561 Mask.getBitWidth() - 1);
12563 case ISD::INTRINSIC_WO_CHAIN: {
12564 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12565 unsigned NumLoBits = 0;
12568 case Intrinsic::x86_sse_movmsk_ps:
12569 case Intrinsic::x86_avx_movmsk_ps_256:
12570 case Intrinsic::x86_sse2_movmsk_pd:
12571 case Intrinsic::x86_avx_movmsk_pd_256:
12572 case Intrinsic::x86_mmx_pmovmskb:
12573 case Intrinsic::x86_sse2_pmovmskb_128: {
12574 // High bits of movmskp{s|d}, pmovmskb are known zero.
12576 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12577 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12578 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12579 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12580 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12581 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12583 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12584 Mask.getBitWidth() - NumLoBits);
12593 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12594 unsigned Depth) const {
12595 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12596 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12597 return Op.getValueType().getScalarType().getSizeInBits();
12603 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12604 /// node is a GlobalAddress + offset.
12605 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12606 const GlobalValue* &GA,
12607 int64_t &Offset) const {
12608 if (N->getOpcode() == X86ISD::Wrapper) {
12609 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12610 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12611 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12615 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12618 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12619 /// same as extracting the high 128-bit part of 256-bit vector and then
12620 /// inserting the result into the low part of a new 256-bit vector
12621 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12622 EVT VT = SVOp->getValueType(0);
12623 int NumElems = VT.getVectorNumElements();
12625 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12626 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12627 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12628 SVOp->getMaskElt(j) >= 0)
12634 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12635 /// same as extracting the low 128-bit part of 256-bit vector and then
12636 /// inserting the result into the high part of a new 256-bit vector
12637 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12638 EVT VT = SVOp->getValueType(0);
12639 int NumElems = VT.getVectorNumElements();
12641 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12642 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12643 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12644 SVOp->getMaskElt(j) >= 0)
12650 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12651 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12652 TargetLowering::DAGCombinerInfo &DCI) {
12653 DebugLoc dl = N->getDebugLoc();
12654 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12655 SDValue V1 = SVOp->getOperand(0);
12656 SDValue V2 = SVOp->getOperand(1);
12657 EVT VT = SVOp->getValueType(0);
12658 int NumElems = VT.getVectorNumElements();
12660 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12661 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12665 // V UNDEF BUILD_VECTOR UNDEF
12667 // CONCAT_VECTOR CONCAT_VECTOR
12670 // RESULT: V + zero extended
12672 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12673 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12674 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12677 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12680 // To match the shuffle mask, the first half of the mask should
12681 // be exactly the first vector, and all the rest a splat with the
12682 // first element of the second one.
12683 for (int i = 0; i < NumElems/2; ++i)
12684 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12685 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12688 // Emit a zeroed vector and insert the desired subvector on its
12690 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
12691 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12692 DAG.getConstant(0, MVT::i32), DAG, dl);
12693 return DCI.CombineTo(N, InsV);
12696 //===--------------------------------------------------------------------===//
12697 // Combine some shuffles into subvector extracts and inserts:
12700 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12701 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12702 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12704 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12705 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12706 return DCI.CombineTo(N, InsV);
12709 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12710 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12711 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12712 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12713 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12714 return DCI.CombineTo(N, InsV);
12720 /// PerformShuffleCombine - Performs several different shuffle combines.
12721 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12722 TargetLowering::DAGCombinerInfo &DCI,
12723 const X86Subtarget *Subtarget) {
12724 DebugLoc dl = N->getDebugLoc();
12725 EVT VT = N->getValueType(0);
12727 // Don't create instructions with illegal types after legalize types has run.
12728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12729 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12732 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12733 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12734 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12735 return PerformShuffleCombine256(N, DAG, DCI);
12737 // Only handle 128 wide vector from here on.
12738 if (VT.getSizeInBits() != 128)
12741 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12742 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12743 // consecutive, non-overlapping, and in the right order.
12744 SmallVector<SDValue, 16> Elts;
12745 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12746 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12748 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12751 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12752 /// generation and convert it from being a bunch of shuffles and extracts
12753 /// to a simple store and scalar loads to extract the elements.
12754 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12755 const TargetLowering &TLI) {
12756 SDValue InputVector = N->getOperand(0);
12758 // Only operate on vectors of 4 elements, where the alternative shuffling
12759 // gets to be more expensive.
12760 if (InputVector.getValueType() != MVT::v4i32)
12763 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12764 // single use which is a sign-extend or zero-extend, and all elements are
12766 SmallVector<SDNode *, 4> Uses;
12767 unsigned ExtractedElements = 0;
12768 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12769 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12770 if (UI.getUse().getResNo() != InputVector.getResNo())
12773 SDNode *Extract = *UI;
12774 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12777 if (Extract->getValueType(0) != MVT::i32)
12779 if (!Extract->hasOneUse())
12781 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12782 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12784 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12787 // Record which element was extracted.
12788 ExtractedElements |=
12789 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12791 Uses.push_back(Extract);
12794 // If not all the elements were used, this may not be worthwhile.
12795 if (ExtractedElements != 15)
12798 // Ok, we've now decided to do the transformation.
12799 DebugLoc dl = InputVector.getDebugLoc();
12801 // Store the value to a temporary stack slot.
12802 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12803 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12804 MachinePointerInfo(), false, false, 0);
12806 // Replace each use (extract) with a load of the appropriate element.
12807 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12808 UE = Uses.end(); UI != UE; ++UI) {
12809 SDNode *Extract = *UI;
12811 // cOMpute the element's address.
12812 SDValue Idx = Extract->getOperand(1);
12814 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12815 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12816 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12818 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12819 StackPtr, OffsetVal);
12821 // Load the scalar.
12822 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12823 ScalarAddr, MachinePointerInfo(),
12824 false, false, false, 0);
12826 // Replace the exact with the load.
12827 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12830 // The replacement was made in place; don't return anything.
12834 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12836 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12837 const X86Subtarget *Subtarget) {
12838 DebugLoc DL = N->getDebugLoc();
12839 SDValue Cond = N->getOperand(0);
12840 // Get the LHS/RHS of the select.
12841 SDValue LHS = N->getOperand(1);
12842 SDValue RHS = N->getOperand(2);
12843 EVT VT = LHS.getValueType();
12845 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12846 // instructions match the semantics of the common C idiom x<y?x:y but not
12847 // x<=y?x:y, because of how they handle negative zero (which can be
12848 // ignored in unsafe-math mode).
12849 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12850 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12851 (Subtarget->hasXMMInt() ||
12852 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12853 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12855 unsigned Opcode = 0;
12856 // Check for x CC y ? x : y.
12857 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12858 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12862 // Converting this to a min would handle NaNs incorrectly, and swapping
12863 // the operands would cause it to handle comparisons between positive
12864 // and negative zero incorrectly.
12865 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12866 if (!DAG.getTarget().Options.UnsafeFPMath &&
12867 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12869 std::swap(LHS, RHS);
12871 Opcode = X86ISD::FMIN;
12874 // Converting this to a min would handle comparisons between positive
12875 // and negative zero incorrectly.
12876 if (!DAG.getTarget().Options.UnsafeFPMath &&
12877 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12879 Opcode = X86ISD::FMIN;
12882 // Converting this to a min would handle both negative zeros and NaNs
12883 // incorrectly, but we can swap the operands to fix both.
12884 std::swap(LHS, RHS);
12888 Opcode = X86ISD::FMIN;
12892 // Converting this to a max would handle comparisons between positive
12893 // and negative zero incorrectly.
12894 if (!DAG.getTarget().Options.UnsafeFPMath &&
12895 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12897 Opcode = X86ISD::FMAX;
12900 // Converting this to a max would handle NaNs incorrectly, and swapping
12901 // the operands would cause it to handle comparisons between positive
12902 // and negative zero incorrectly.
12903 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12904 if (!DAG.getTarget().Options.UnsafeFPMath &&
12905 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12907 std::swap(LHS, RHS);
12909 Opcode = X86ISD::FMAX;
12912 // Converting this to a max would handle both negative zeros and NaNs
12913 // incorrectly, but we can swap the operands to fix both.
12914 std::swap(LHS, RHS);
12918 Opcode = X86ISD::FMAX;
12921 // Check for x CC y ? y : x -- a min/max with reversed arms.
12922 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12923 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12927 // Converting this to a min would handle comparisons between positive
12928 // and negative zero incorrectly, and swapping the operands would
12929 // cause it to handle NaNs incorrectly.
12930 if (!DAG.getTarget().Options.UnsafeFPMath &&
12931 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12932 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12934 std::swap(LHS, RHS);
12936 Opcode = X86ISD::FMIN;
12939 // Converting this to a min would handle NaNs incorrectly.
12940 if (!DAG.getTarget().Options.UnsafeFPMath &&
12941 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12943 Opcode = X86ISD::FMIN;
12946 // Converting this to a min would handle both negative zeros and NaNs
12947 // incorrectly, but we can swap the operands to fix both.
12948 std::swap(LHS, RHS);
12952 Opcode = X86ISD::FMIN;
12956 // Converting this to a max would handle NaNs incorrectly.
12957 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12959 Opcode = X86ISD::FMAX;
12962 // Converting this to a max would handle comparisons between positive
12963 // and negative zero incorrectly, and swapping the operands would
12964 // cause it to handle NaNs incorrectly.
12965 if (!DAG.getTarget().Options.UnsafeFPMath &&
12966 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12967 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12969 std::swap(LHS, RHS);
12971 Opcode = X86ISD::FMAX;
12974 // Converting this to a max would handle both negative zeros and NaNs
12975 // incorrectly, but we can swap the operands to fix both.
12976 std::swap(LHS, RHS);
12980 Opcode = X86ISD::FMAX;
12986 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12989 // If this is a select between two integer constants, try to do some
12991 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12992 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12993 // Don't do this for crazy integer types.
12994 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12995 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12996 // so that TrueC (the true value) is larger than FalseC.
12997 bool NeedsCondInvert = false;
12999 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13000 // Efficiently invertible.
13001 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13002 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13003 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13004 NeedsCondInvert = true;
13005 std::swap(TrueC, FalseC);
13008 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13009 if (FalseC->getAPIntValue() == 0 &&
13010 TrueC->getAPIntValue().isPowerOf2()) {
13011 if (NeedsCondInvert) // Invert the condition if needed.
13012 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13013 DAG.getConstant(1, Cond.getValueType()));
13015 // Zero extend the condition if needed.
13016 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13018 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13019 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13020 DAG.getConstant(ShAmt, MVT::i8));
13023 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13024 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13025 if (NeedsCondInvert) // Invert the condition if needed.
13026 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13027 DAG.getConstant(1, Cond.getValueType()));
13029 // Zero extend the condition if needed.
13030 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13031 FalseC->getValueType(0), Cond);
13032 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13033 SDValue(FalseC, 0));
13036 // Optimize cases that will turn into an LEA instruction. This requires
13037 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13038 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13039 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13040 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13042 bool isFastMultiplier = false;
13044 switch ((unsigned char)Diff) {
13046 case 1: // result = add base, cond
13047 case 2: // result = lea base( , cond*2)
13048 case 3: // result = lea base(cond, cond*2)
13049 case 4: // result = lea base( , cond*4)
13050 case 5: // result = lea base(cond, cond*4)
13051 case 8: // result = lea base( , cond*8)
13052 case 9: // result = lea base(cond, cond*8)
13053 isFastMultiplier = true;
13058 if (isFastMultiplier) {
13059 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13060 if (NeedsCondInvert) // Invert the condition if needed.
13061 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13062 DAG.getConstant(1, Cond.getValueType()));
13064 // Zero extend the condition if needed.
13065 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13067 // Scale the condition by the difference.
13069 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13070 DAG.getConstant(Diff, Cond.getValueType()));
13072 // Add the base if non-zero.
13073 if (FalseC->getAPIntValue() != 0)
13074 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13075 SDValue(FalseC, 0));
13085 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13086 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13087 TargetLowering::DAGCombinerInfo &DCI) {
13088 DebugLoc DL = N->getDebugLoc();
13090 // If the flag operand isn't dead, don't touch this CMOV.
13091 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13094 SDValue FalseOp = N->getOperand(0);
13095 SDValue TrueOp = N->getOperand(1);
13096 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13097 SDValue Cond = N->getOperand(3);
13098 if (CC == X86::COND_E || CC == X86::COND_NE) {
13099 switch (Cond.getOpcode()) {
13103 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13104 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13105 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13109 // If this is a select between two integer constants, try to do some
13110 // optimizations. Note that the operands are ordered the opposite of SELECT
13112 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13113 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13114 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13115 // larger than FalseC (the false value).
13116 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13117 CC = X86::GetOppositeBranchCondition(CC);
13118 std::swap(TrueC, FalseC);
13121 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13122 // This is efficient for any integer data type (including i8/i16) and
13124 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13125 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13126 DAG.getConstant(CC, MVT::i8), Cond);
13128 // Zero extend the condition if needed.
13129 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13131 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13132 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13133 DAG.getConstant(ShAmt, MVT::i8));
13134 if (N->getNumValues() == 2) // Dead flag value?
13135 return DCI.CombineTo(N, Cond, SDValue());
13139 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13140 // for any integer data type, including i8/i16.
13141 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13142 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13143 DAG.getConstant(CC, MVT::i8), Cond);
13145 // Zero extend the condition if needed.
13146 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13147 FalseC->getValueType(0), Cond);
13148 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13149 SDValue(FalseC, 0));
13151 if (N->getNumValues() == 2) // Dead flag value?
13152 return DCI.CombineTo(N, Cond, SDValue());
13156 // Optimize cases that will turn into an LEA instruction. This requires
13157 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13158 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13159 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13160 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13162 bool isFastMultiplier = false;
13164 switch ((unsigned char)Diff) {
13166 case 1: // result = add base, cond
13167 case 2: // result = lea base( , cond*2)
13168 case 3: // result = lea base(cond, cond*2)
13169 case 4: // result = lea base( , cond*4)
13170 case 5: // result = lea base(cond, cond*4)
13171 case 8: // result = lea base( , cond*8)
13172 case 9: // result = lea base(cond, cond*8)
13173 isFastMultiplier = true;
13178 if (isFastMultiplier) {
13179 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13180 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13181 DAG.getConstant(CC, MVT::i8), Cond);
13182 // Zero extend the condition if needed.
13183 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13185 // Scale the condition by the difference.
13187 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13188 DAG.getConstant(Diff, Cond.getValueType()));
13190 // Add the base if non-zero.
13191 if (FalseC->getAPIntValue() != 0)
13192 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13193 SDValue(FalseC, 0));
13194 if (N->getNumValues() == 2) // Dead flag value?
13195 return DCI.CombineTo(N, Cond, SDValue());
13205 /// PerformMulCombine - Optimize a single multiply with constant into two
13206 /// in order to implement it with two cheaper instructions, e.g.
13207 /// LEA + SHL, LEA + LEA.
13208 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13209 TargetLowering::DAGCombinerInfo &DCI) {
13210 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13213 EVT VT = N->getValueType(0);
13214 if (VT != MVT::i64)
13217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13220 uint64_t MulAmt = C->getZExtValue();
13221 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13224 uint64_t MulAmt1 = 0;
13225 uint64_t MulAmt2 = 0;
13226 if ((MulAmt % 9) == 0) {
13228 MulAmt2 = MulAmt / 9;
13229 } else if ((MulAmt % 5) == 0) {
13231 MulAmt2 = MulAmt / 5;
13232 } else if ((MulAmt % 3) == 0) {
13234 MulAmt2 = MulAmt / 3;
13237 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13238 DebugLoc DL = N->getDebugLoc();
13240 if (isPowerOf2_64(MulAmt2) &&
13241 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13242 // If second multiplifer is pow2, issue it first. We want the multiply by
13243 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13245 std::swap(MulAmt1, MulAmt2);
13248 if (isPowerOf2_64(MulAmt1))
13249 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13250 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13252 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13253 DAG.getConstant(MulAmt1, VT));
13255 if (isPowerOf2_64(MulAmt2))
13256 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13257 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13259 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13260 DAG.getConstant(MulAmt2, VT));
13262 // Do not add new nodes to DAG combiner worklist.
13263 DCI.CombineTo(N, NewMul, false);
13268 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13269 SDValue N0 = N->getOperand(0);
13270 SDValue N1 = N->getOperand(1);
13271 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13272 EVT VT = N0.getValueType();
13274 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13275 // since the result of setcc_c is all zero's or all ones.
13276 if (VT.isInteger() && !VT.isVector() &&
13277 N1C && N0.getOpcode() == ISD::AND &&
13278 N0.getOperand(1).getOpcode() == ISD::Constant) {
13279 SDValue N00 = N0.getOperand(0);
13280 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13281 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13282 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13283 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13284 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13285 APInt ShAmt = N1C->getAPIntValue();
13286 Mask = Mask.shl(ShAmt);
13288 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13289 N00, DAG.getConstant(Mask, VT));
13294 // Hardware support for vector shifts is sparse which makes us scalarize the
13295 // vector operations in many cases. Also, on sandybridge ADD is faster than
13297 // (shl V, 1) -> add V,V
13298 if (isSplatVector(N1.getNode())) {
13299 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13301 // We shift all of the values by one. In many cases we do not have
13302 // hardware support for this operation. This is better expressed as an ADD
13304 if (N1C && (1 == N1C->getZExtValue())) {
13305 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13312 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13314 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13315 const X86Subtarget *Subtarget) {
13316 EVT VT = N->getValueType(0);
13317 if (N->getOpcode() == ISD::SHL) {
13318 SDValue V = PerformSHLCombine(N, DAG);
13319 if (V.getNode()) return V;
13322 // On X86 with SSE2 support, we can transform this to a vector shift if
13323 // all elements are shifted by the same amount. We can't do this in legalize
13324 // because the a constant vector is typically transformed to a constant pool
13325 // so we have no knowledge of the shift amount.
13326 if (!Subtarget->hasXMMInt())
13329 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13330 (!Subtarget->hasAVX2() ||
13331 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13334 SDValue ShAmtOp = N->getOperand(1);
13335 EVT EltVT = VT.getVectorElementType();
13336 DebugLoc DL = N->getDebugLoc();
13337 SDValue BaseShAmt = SDValue();
13338 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13339 unsigned NumElts = VT.getVectorNumElements();
13341 for (; i != NumElts; ++i) {
13342 SDValue Arg = ShAmtOp.getOperand(i);
13343 if (Arg.getOpcode() == ISD::UNDEF) continue;
13347 for (; i != NumElts; ++i) {
13348 SDValue Arg = ShAmtOp.getOperand(i);
13349 if (Arg.getOpcode() == ISD::UNDEF) continue;
13350 if (Arg != BaseShAmt) {
13354 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13355 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13356 SDValue InVec = ShAmtOp.getOperand(0);
13357 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13358 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13360 for (; i != NumElts; ++i) {
13361 SDValue Arg = InVec.getOperand(i);
13362 if (Arg.getOpcode() == ISD::UNDEF) continue;
13366 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13368 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13369 if (C->getZExtValue() == SplatIdx)
13370 BaseShAmt = InVec.getOperand(1);
13373 if (BaseShAmt.getNode() == 0)
13374 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13375 DAG.getIntPtrConstant(0));
13379 // The shift amount is an i32.
13380 if (EltVT.bitsGT(MVT::i32))
13381 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13382 else if (EltVT.bitsLT(MVT::i32))
13383 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13385 // The shift amount is identical so we can do a vector shift.
13386 SDValue ValOp = N->getOperand(0);
13387 switch (N->getOpcode()) {
13389 llvm_unreachable("Unknown shift opcode!");
13392 if (VT == MVT::v2i64)
13393 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13394 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13396 if (VT == MVT::v4i32)
13397 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13398 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13400 if (VT == MVT::v8i16)
13401 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13402 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13404 if (VT == MVT::v4i64)
13405 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13406 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
13408 if (VT == MVT::v8i32)
13409 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13410 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
13412 if (VT == MVT::v16i16)
13413 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13414 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
13418 if (VT == MVT::v4i32)
13419 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13420 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13422 if (VT == MVT::v8i16)
13423 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13424 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13426 if (VT == MVT::v8i32)
13427 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13428 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
13430 if (VT == MVT::v16i16)
13431 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13432 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
13436 if (VT == MVT::v2i64)
13437 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13438 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13440 if (VT == MVT::v4i32)
13441 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13442 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13444 if (VT == MVT::v8i16)
13445 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13446 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13448 if (VT == MVT::v4i64)
13449 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13450 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
13452 if (VT == MVT::v8i32)
13453 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13454 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
13456 if (VT == MVT::v16i16)
13457 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13458 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
13466 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13467 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13468 // and friends. Likewise for OR -> CMPNEQSS.
13469 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13470 TargetLowering::DAGCombinerInfo &DCI,
13471 const X86Subtarget *Subtarget) {
13474 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13475 // we're requiring SSE2 for both.
13476 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13477 SDValue N0 = N->getOperand(0);
13478 SDValue N1 = N->getOperand(1);
13479 SDValue CMP0 = N0->getOperand(1);
13480 SDValue CMP1 = N1->getOperand(1);
13481 DebugLoc DL = N->getDebugLoc();
13483 // The SETCCs should both refer to the same CMP.
13484 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13487 SDValue CMP00 = CMP0->getOperand(0);
13488 SDValue CMP01 = CMP0->getOperand(1);
13489 EVT VT = CMP00.getValueType();
13491 if (VT == MVT::f32 || VT == MVT::f64) {
13492 bool ExpectingFlags = false;
13493 // Check for any users that want flags:
13494 for (SDNode::use_iterator UI = N->use_begin(),
13496 !ExpectingFlags && UI != UE; ++UI)
13497 switch (UI->getOpcode()) {
13502 ExpectingFlags = true;
13504 case ISD::CopyToReg:
13505 case ISD::SIGN_EXTEND:
13506 case ISD::ZERO_EXTEND:
13507 case ISD::ANY_EXTEND:
13511 if (!ExpectingFlags) {
13512 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13513 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13515 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13516 X86::CondCode tmp = cc0;
13521 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13522 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13523 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13524 X86ISD::NodeType NTOperator = is64BitFP ?
13525 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13526 // FIXME: need symbolic constants for these magic numbers.
13527 // See X86ATTInstPrinter.cpp:printSSECC().
13528 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13529 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13530 DAG.getConstant(x86cc, MVT::i8));
13531 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13533 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13534 DAG.getConstant(1, MVT::i32));
13535 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13536 return OneBitOfTruth;
13544 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13545 /// so it can be folded inside ANDNP.
13546 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13547 EVT VT = N->getValueType(0);
13549 // Match direct AllOnes for 128 and 256-bit vectors
13550 if (ISD::isBuildVectorAllOnes(N))
13553 // Look through a bit convert.
13554 if (N->getOpcode() == ISD::BITCAST)
13555 N = N->getOperand(0).getNode();
13557 // Sometimes the operand may come from a insert_subvector building a 256-bit
13559 if (VT.getSizeInBits() == 256 &&
13560 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13561 SDValue V1 = N->getOperand(0);
13562 SDValue V2 = N->getOperand(1);
13564 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13565 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13566 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13567 ISD::isBuildVectorAllOnes(V2.getNode()))
13574 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13575 TargetLowering::DAGCombinerInfo &DCI,
13576 const X86Subtarget *Subtarget) {
13577 if (DCI.isBeforeLegalizeOps())
13580 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13584 EVT VT = N->getValueType(0);
13586 // Create ANDN, BLSI, and BLSR instructions
13587 // BLSI is X & (-X)
13588 // BLSR is X & (X-1)
13589 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13590 SDValue N0 = N->getOperand(0);
13591 SDValue N1 = N->getOperand(1);
13592 DebugLoc DL = N->getDebugLoc();
13594 // Check LHS for not
13595 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13596 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13597 // Check RHS for not
13598 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13599 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13601 // Check LHS for neg
13602 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13603 isZero(N0.getOperand(0)))
13604 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13606 // Check RHS for neg
13607 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13608 isZero(N1.getOperand(0)))
13609 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13611 // Check LHS for X-1
13612 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13613 isAllOnes(N0.getOperand(1)))
13614 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13616 // Check RHS for X-1
13617 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13618 isAllOnes(N1.getOperand(1)))
13619 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13624 // Want to form ANDNP nodes:
13625 // 1) In the hopes of then easily combining them with OR and AND nodes
13626 // to form PBLEND/PSIGN.
13627 // 2) To match ANDN packed intrinsics
13628 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13631 SDValue N0 = N->getOperand(0);
13632 SDValue N1 = N->getOperand(1);
13633 DebugLoc DL = N->getDebugLoc();
13635 // Check LHS for vnot
13636 if (N0.getOpcode() == ISD::XOR &&
13637 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13638 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13639 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13641 // Check RHS for vnot
13642 if (N1.getOpcode() == ISD::XOR &&
13643 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13644 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13645 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13650 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13651 TargetLowering::DAGCombinerInfo &DCI,
13652 const X86Subtarget *Subtarget) {
13653 if (DCI.isBeforeLegalizeOps())
13656 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13660 EVT VT = N->getValueType(0);
13662 SDValue N0 = N->getOperand(0);
13663 SDValue N1 = N->getOperand(1);
13665 // look for psign/blend
13666 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13667 if (!Subtarget->hasSSSE3orAVX() ||
13668 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13671 // Canonicalize pandn to RHS
13672 if (N0.getOpcode() == X86ISD::ANDNP)
13674 // or (and (m, x), (pandn m, y))
13675 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13676 SDValue Mask = N1.getOperand(0);
13677 SDValue X = N1.getOperand(1);
13679 if (N0.getOperand(0) == Mask)
13680 Y = N0.getOperand(1);
13681 if (N0.getOperand(1) == Mask)
13682 Y = N0.getOperand(0);
13684 // Check to see if the mask appeared in both the AND and ANDNP and
13688 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13689 if (Mask.getOpcode() != ISD::BITCAST ||
13690 X.getOpcode() != ISD::BITCAST ||
13691 Y.getOpcode() != ISD::BITCAST)
13694 // Look through mask bitcast.
13695 Mask = Mask.getOperand(0);
13696 EVT MaskVT = Mask.getValueType();
13698 // Validate that the Mask operand is a vector sra node. The sra node
13699 // will be an intrinsic.
13700 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13703 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13704 // there is no psrai.b
13705 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13706 case Intrinsic::x86_sse2_psrai_w:
13707 case Intrinsic::x86_sse2_psrai_d:
13708 case Intrinsic::x86_avx2_psrai_w:
13709 case Intrinsic::x86_avx2_psrai_d:
13711 default: return SDValue();
13714 // Check that the SRA is all signbits.
13715 SDValue SraC = Mask.getOperand(2);
13716 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13717 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13718 if ((SraAmt + 1) != EltBits)
13721 DebugLoc DL = N->getDebugLoc();
13723 // Now we know we at least have a plendvb with the mask val. See if
13724 // we can form a psignb/w/d.
13725 // psign = x.type == y.type == mask.type && y = sub(0, x);
13726 X = X.getOperand(0);
13727 Y = Y.getOperand(0);
13728 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13729 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13730 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
13731 (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
13732 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
13733 Mask.getOperand(1));
13734 return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
13736 // PBLENDVB only available on SSE 4.1
13737 if (!Subtarget->hasSSE41orAVX())
13740 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13742 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13743 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13744 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13745 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13746 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13750 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13753 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13754 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13756 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13758 if (!N0.hasOneUse() || !N1.hasOneUse())
13761 SDValue ShAmt0 = N0.getOperand(1);
13762 if (ShAmt0.getValueType() != MVT::i8)
13764 SDValue ShAmt1 = N1.getOperand(1);
13765 if (ShAmt1.getValueType() != MVT::i8)
13767 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13768 ShAmt0 = ShAmt0.getOperand(0);
13769 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13770 ShAmt1 = ShAmt1.getOperand(0);
13772 DebugLoc DL = N->getDebugLoc();
13773 unsigned Opc = X86ISD::SHLD;
13774 SDValue Op0 = N0.getOperand(0);
13775 SDValue Op1 = N1.getOperand(0);
13776 if (ShAmt0.getOpcode() == ISD::SUB) {
13777 Opc = X86ISD::SHRD;
13778 std::swap(Op0, Op1);
13779 std::swap(ShAmt0, ShAmt1);
13782 unsigned Bits = VT.getSizeInBits();
13783 if (ShAmt1.getOpcode() == ISD::SUB) {
13784 SDValue Sum = ShAmt1.getOperand(0);
13785 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13786 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13787 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13788 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13789 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13790 return DAG.getNode(Opc, DL, VT,
13792 DAG.getNode(ISD::TRUNCATE, DL,
13795 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13796 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13798 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13799 return DAG.getNode(Opc, DL, VT,
13800 N0.getOperand(0), N1.getOperand(0),
13801 DAG.getNode(ISD::TRUNCATE, DL,
13808 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13809 TargetLowering::DAGCombinerInfo &DCI,
13810 const X86Subtarget *Subtarget) {
13811 if (DCI.isBeforeLegalizeOps())
13814 EVT VT = N->getValueType(0);
13816 if (VT != MVT::i32 && VT != MVT::i64)
13819 // Create BLSMSK instructions by finding X ^ (X-1)
13820 SDValue N0 = N->getOperand(0);
13821 SDValue N1 = N->getOperand(1);
13822 DebugLoc DL = N->getDebugLoc();
13824 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13825 isAllOnes(N0.getOperand(1)))
13826 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13828 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13829 isAllOnes(N1.getOperand(1)))
13830 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13835 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13836 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13837 const X86Subtarget *Subtarget) {
13838 LoadSDNode *Ld = cast<LoadSDNode>(N);
13839 EVT RegVT = Ld->getValueType(0);
13840 EVT MemVT = Ld->getMemoryVT();
13841 DebugLoc dl = Ld->getDebugLoc();
13842 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13844 ISD::LoadExtType Ext = Ld->getExtensionType();
13846 // If this is a vector EXT Load then attempt to optimize it using a
13847 // shuffle. We need SSE4 for the shuffles.
13848 // TODO: It is possible to support ZExt by zeroing the undef values
13849 // during the shuffle phase or after the shuffle.
13850 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13851 assert(MemVT != RegVT && "Cannot extend to the same type");
13852 assert(MemVT.isVector() && "Must load a vector from memory");
13854 unsigned NumElems = RegVT.getVectorNumElements();
13855 unsigned RegSz = RegVT.getSizeInBits();
13856 unsigned MemSz = MemVT.getSizeInBits();
13857 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13858 // All sizes must be a power of two
13859 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13861 // Attempt to load the original value using a single load op.
13862 // Find a scalar type which is equal to the loaded word size.
13863 MVT SclrLoadTy = MVT::i8;
13864 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13865 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13866 MVT Tp = (MVT::SimpleValueType)tp;
13867 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13873 // Proceed if a load word is found.
13874 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13876 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13877 RegSz/SclrLoadTy.getSizeInBits());
13879 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13880 RegSz/MemVT.getScalarType().getSizeInBits());
13881 // Can't shuffle using an illegal type.
13882 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13884 // Perform a single load.
13885 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13887 Ld->getPointerInfo(), Ld->isVolatile(),
13888 Ld->isNonTemporal(), Ld->isInvariant(),
13889 Ld->getAlignment());
13891 // Insert the word loaded into a vector.
13892 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13893 LoadUnitVecVT, ScalarLoad);
13895 // Bitcast the loaded value to a vector of the original element type, in
13896 // the size of the target vector type.
13897 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector);
13898 unsigned SizeRatio = RegSz/MemSz;
13900 // Redistribute the loaded elements into the different locations.
13901 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13902 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13904 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13905 DAG.getUNDEF(SlicedVec.getValueType()),
13906 ShuffleVec.data());
13908 // Bitcast to the requested type.
13909 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13910 // Replace the original load with the new sequence
13911 // and return the new chain.
13912 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13913 return SDValue(ScalarLoad.getNode(), 1);
13919 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13920 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13921 const X86Subtarget *Subtarget) {
13922 StoreSDNode *St = cast<StoreSDNode>(N);
13923 EVT VT = St->getValue().getValueType();
13924 EVT StVT = St->getMemoryVT();
13925 DebugLoc dl = St->getDebugLoc();
13926 SDValue StoredVal = St->getOperand(1);
13927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13929 // If we are saving a concatenation of two XMM registers, perform two stores.
13930 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13931 // 128-bit ones. If in the future the cost becomes only one memory access the
13932 // first version would be better.
13933 if (VT.getSizeInBits() == 256 &&
13934 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13935 StoredVal.getNumOperands() == 2) {
13937 SDValue Value0 = StoredVal.getOperand(0);
13938 SDValue Value1 = StoredVal.getOperand(1);
13940 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13941 SDValue Ptr0 = St->getBasePtr();
13942 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13944 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13945 St->getPointerInfo(), St->isVolatile(),
13946 St->isNonTemporal(), St->getAlignment());
13947 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13948 St->getPointerInfo(), St->isVolatile(),
13949 St->isNonTemporal(), St->getAlignment());
13950 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13953 // Optimize trunc store (of multiple scalars) to shuffle and store.
13954 // First, pack all of the elements in one place. Next, store to memory
13955 // in fewer chunks.
13956 if (St->isTruncatingStore() && VT.isVector()) {
13957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13958 unsigned NumElems = VT.getVectorNumElements();
13959 assert(StVT != VT && "Cannot truncate to the same type");
13960 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13961 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13963 // From, To sizes and ElemCount must be pow of two
13964 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13965 // We are going to use the original vector elt for storing.
13966 // Accumulated smaller vector elements must be a multiple of the store size.
13967 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
13969 unsigned SizeRatio = FromSz / ToSz;
13971 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13973 // Create a type on which we perform the shuffle
13974 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13975 StVT.getScalarType(), NumElems*SizeRatio);
13977 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13979 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13980 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13981 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13983 // Can't shuffle using an illegal type
13984 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13986 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13987 DAG.getUNDEF(WideVec.getValueType()),
13988 ShuffleVec.data());
13989 // At this point all of the data is stored at the bottom of the
13990 // register. We now need to save it to mem.
13992 // Find the largest store unit
13993 MVT StoreType = MVT::i8;
13994 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13995 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13996 MVT Tp = (MVT::SimpleValueType)tp;
13997 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14001 // Bitcast the original vector into a vector of store-size units
14002 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14003 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14004 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14005 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14006 SmallVector<SDValue, 8> Chains;
14007 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14008 TLI.getPointerTy());
14009 SDValue Ptr = St->getBasePtr();
14011 // Perform one or more big stores into memory.
14012 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14013 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14014 StoreType, ShuffWide,
14015 DAG.getIntPtrConstant(i));
14016 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14017 St->getPointerInfo(), St->isVolatile(),
14018 St->isNonTemporal(), St->getAlignment());
14019 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14020 Chains.push_back(Ch);
14023 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14028 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14029 // the FP state in cases where an emms may be missing.
14030 // A preferable solution to the general problem is to figure out the right
14031 // places to insert EMMS. This qualifies as a quick hack.
14033 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14034 if (VT.getSizeInBits() != 64)
14037 const Function *F = DAG.getMachineFunction().getFunction();
14038 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14039 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14040 && Subtarget->hasXMMInt();
14041 if ((VT.isVector() ||
14042 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14043 isa<LoadSDNode>(St->getValue()) &&
14044 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14045 St->getChain().hasOneUse() && !St->isVolatile()) {
14046 SDNode* LdVal = St->getValue().getNode();
14047 LoadSDNode *Ld = 0;
14048 int TokenFactorIndex = -1;
14049 SmallVector<SDValue, 8> Ops;
14050 SDNode* ChainVal = St->getChain().getNode();
14051 // Must be a store of a load. We currently handle two cases: the load
14052 // is a direct child, and it's under an intervening TokenFactor. It is
14053 // possible to dig deeper under nested TokenFactors.
14054 if (ChainVal == LdVal)
14055 Ld = cast<LoadSDNode>(St->getChain());
14056 else if (St->getValue().hasOneUse() &&
14057 ChainVal->getOpcode() == ISD::TokenFactor) {
14058 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14059 if (ChainVal->getOperand(i).getNode() == LdVal) {
14060 TokenFactorIndex = i;
14061 Ld = cast<LoadSDNode>(St->getValue());
14063 Ops.push_back(ChainVal->getOperand(i));
14067 if (!Ld || !ISD::isNormalLoad(Ld))
14070 // If this is not the MMX case, i.e. we are just turning i64 load/store
14071 // into f64 load/store, avoid the transformation if there are multiple
14072 // uses of the loaded value.
14073 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14076 DebugLoc LdDL = Ld->getDebugLoc();
14077 DebugLoc StDL = N->getDebugLoc();
14078 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14079 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14081 if (Subtarget->is64Bit() || F64IsLegal) {
14082 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14083 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14084 Ld->getPointerInfo(), Ld->isVolatile(),
14085 Ld->isNonTemporal(), Ld->isInvariant(),
14086 Ld->getAlignment());
14087 SDValue NewChain = NewLd.getValue(1);
14088 if (TokenFactorIndex != -1) {
14089 Ops.push_back(NewChain);
14090 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14093 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14094 St->getPointerInfo(),
14095 St->isVolatile(), St->isNonTemporal(),
14096 St->getAlignment());
14099 // Otherwise, lower to two pairs of 32-bit loads / stores.
14100 SDValue LoAddr = Ld->getBasePtr();
14101 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14102 DAG.getConstant(4, MVT::i32));
14104 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14105 Ld->getPointerInfo(),
14106 Ld->isVolatile(), Ld->isNonTemporal(),
14107 Ld->isInvariant(), Ld->getAlignment());
14108 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14109 Ld->getPointerInfo().getWithOffset(4),
14110 Ld->isVolatile(), Ld->isNonTemporal(),
14112 MinAlign(Ld->getAlignment(), 4));
14114 SDValue NewChain = LoLd.getValue(1);
14115 if (TokenFactorIndex != -1) {
14116 Ops.push_back(LoLd);
14117 Ops.push_back(HiLd);
14118 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14122 LoAddr = St->getBasePtr();
14123 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14124 DAG.getConstant(4, MVT::i32));
14126 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14127 St->getPointerInfo(),
14128 St->isVolatile(), St->isNonTemporal(),
14129 St->getAlignment());
14130 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14131 St->getPointerInfo().getWithOffset(4),
14133 St->isNonTemporal(),
14134 MinAlign(St->getAlignment(), 4));
14135 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14140 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14141 /// and return the operands for the horizontal operation in LHS and RHS. A
14142 /// horizontal operation performs the binary operation on successive elements
14143 /// of its first operand, then on successive elements of its second operand,
14144 /// returning the resulting values in a vector. For example, if
14145 /// A = < float a0, float a1, float a2, float a3 >
14147 /// B = < float b0, float b1, float b2, float b3 >
14148 /// then the result of doing a horizontal operation on A and B is
14149 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14150 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14151 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14152 /// set to A, RHS to B, and the routine returns 'true'.
14153 /// Note that the binary operation should have the property that if one of the
14154 /// operands is UNDEF then the result is UNDEF.
14155 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14156 // Look for the following pattern: if
14157 // A = < float a0, float a1, float a2, float a3 >
14158 // B = < float b0, float b1, float b2, float b3 >
14160 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14161 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14162 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14163 // which is A horizontal-op B.
14165 // At least one of the operands should be a vector shuffle.
14166 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14167 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14170 EVT VT = LHS.getValueType();
14172 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14173 "Unsupported vector type for horizontal add/sub");
14175 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14176 // operate independently on 128-bit lanes.
14177 unsigned NumElts = VT.getVectorNumElements();
14178 unsigned NumLanes = VT.getSizeInBits()/128;
14179 unsigned NumLaneElts = NumElts / NumLanes;
14180 assert((NumLaneElts % 2 == 0) &&
14181 "Vector type should have an even number of elements in each lane");
14182 unsigned HalfLaneElts = NumLaneElts/2;
14184 // View LHS in the form
14185 // LHS = VECTOR_SHUFFLE A, B, LMask
14186 // If LHS is not a shuffle then pretend it is the shuffle
14187 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14188 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14191 SmallVector<int, 16> LMask(NumElts);
14192 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14193 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14194 A = LHS.getOperand(0);
14195 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14196 B = LHS.getOperand(1);
14197 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask);
14199 if (LHS.getOpcode() != ISD::UNDEF)
14201 for (unsigned i = 0; i != NumElts; ++i)
14205 // Likewise, view RHS in the form
14206 // RHS = VECTOR_SHUFFLE C, D, RMask
14208 SmallVector<int, 16> RMask(NumElts);
14209 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14210 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14211 C = RHS.getOperand(0);
14212 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14213 D = RHS.getOperand(1);
14214 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask);
14216 if (RHS.getOpcode() != ISD::UNDEF)
14218 for (unsigned i = 0; i != NumElts; ++i)
14222 // Check that the shuffles are both shuffling the same vectors.
14223 if (!(A == C && B == D) && !(A == D && B == C))
14226 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14227 if (!A.getNode() && !B.getNode())
14230 // If A and B occur in reverse order in RHS, then "swap" them (which means
14231 // rewriting the mask).
14233 CommuteVectorShuffleMask(RMask, NumElts);
14235 // At this point LHS and RHS are equivalent to
14236 // LHS = VECTOR_SHUFFLE A, B, LMask
14237 // RHS = VECTOR_SHUFFLE A, B, RMask
14238 // Check that the masks correspond to performing a horizontal operation.
14239 for (unsigned i = 0; i != NumElts; ++i) {
14240 int LIdx = LMask[i], RIdx = RMask[i];
14242 // Ignore any UNDEF components.
14243 if (LIdx < 0 || RIdx < 0 ||
14244 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14245 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14248 // Check that successive elements are being operated on. If not, this is
14249 // not a horizontal operation.
14250 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14251 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14252 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14253 if (!(LIdx == Index && RIdx == Index + 1) &&
14254 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14258 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14259 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14263 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14264 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14265 const X86Subtarget *Subtarget) {
14266 EVT VT = N->getValueType(0);
14267 SDValue LHS = N->getOperand(0);
14268 SDValue RHS = N->getOperand(1);
14270 // Try to synthesize horizontal adds from adds of shuffles.
14271 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14272 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14273 isHorizontalBinOp(LHS, RHS, true))
14274 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14278 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14279 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14280 const X86Subtarget *Subtarget) {
14281 EVT VT = N->getValueType(0);
14282 SDValue LHS = N->getOperand(0);
14283 SDValue RHS = N->getOperand(1);
14285 // Try to synthesize horizontal subs from subs of shuffles.
14286 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14287 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14288 isHorizontalBinOp(LHS, RHS, false))
14289 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14293 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14294 /// X86ISD::FXOR nodes.
14295 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14296 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14297 // F[X]OR(0.0, x) -> x
14298 // F[X]OR(x, 0.0) -> x
14299 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14300 if (C->getValueAPF().isPosZero())
14301 return N->getOperand(1);
14302 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14303 if (C->getValueAPF().isPosZero())
14304 return N->getOperand(0);
14308 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14309 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14310 // FAND(0.0, x) -> 0.0
14311 // FAND(x, 0.0) -> 0.0
14312 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14313 if (C->getValueAPF().isPosZero())
14314 return N->getOperand(0);
14315 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14316 if (C->getValueAPF().isPosZero())
14317 return N->getOperand(1);
14321 static SDValue PerformBTCombine(SDNode *N,
14323 TargetLowering::DAGCombinerInfo &DCI) {
14324 // BT ignores high bits in the bit index operand.
14325 SDValue Op1 = N->getOperand(1);
14326 if (Op1.hasOneUse()) {
14327 unsigned BitWidth = Op1.getValueSizeInBits();
14328 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14329 APInt KnownZero, KnownOne;
14330 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14331 !DCI.isBeforeLegalizeOps());
14332 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14333 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14334 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14335 DCI.CommitTargetLoweringOpt(TLO);
14340 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14341 SDValue Op = N->getOperand(0);
14342 if (Op.getOpcode() == ISD::BITCAST)
14343 Op = Op.getOperand(0);
14344 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14345 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14346 VT.getVectorElementType().getSizeInBits() ==
14347 OpVT.getVectorElementType().getSizeInBits()) {
14348 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14353 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14354 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14355 // (and (i32 x86isd::setcc_carry), 1)
14356 // This eliminates the zext. This transformation is necessary because
14357 // ISD::SETCC is always legalized to i8.
14358 DebugLoc dl = N->getDebugLoc();
14359 SDValue N0 = N->getOperand(0);
14360 EVT VT = N->getValueType(0);
14361 if (N0.getOpcode() == ISD::AND &&
14363 N0.getOperand(0).hasOneUse()) {
14364 SDValue N00 = N0.getOperand(0);
14365 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14367 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14368 if (!C || C->getZExtValue() != 1)
14370 return DAG.getNode(ISD::AND, dl, VT,
14371 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14372 N00.getOperand(0), N00.getOperand(1)),
14373 DAG.getConstant(1, VT));
14379 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14380 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14381 unsigned X86CC = N->getConstantOperandVal(0);
14382 SDValue EFLAG = N->getOperand(1);
14383 DebugLoc DL = N->getDebugLoc();
14385 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14386 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14388 if (X86CC == X86::COND_B)
14389 return DAG.getNode(ISD::AND, DL, MVT::i8,
14390 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14391 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14392 DAG.getConstant(1, MVT::i8));
14397 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14398 const X86TargetLowering *XTLI) {
14399 SDValue Op0 = N->getOperand(0);
14400 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14401 // a 32-bit target where SSE doesn't support i64->FP operations.
14402 if (Op0.getOpcode() == ISD::LOAD) {
14403 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14404 EVT VT = Ld->getValueType(0);
14405 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14406 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14407 !XTLI->getSubtarget()->is64Bit() &&
14408 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14409 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14410 Ld->getChain(), Op0, DAG);
14411 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14418 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14419 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14420 X86TargetLowering::DAGCombinerInfo &DCI) {
14421 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14422 // the result is either zero or one (depending on the input carry bit).
14423 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14424 if (X86::isZeroNode(N->getOperand(0)) &&
14425 X86::isZeroNode(N->getOperand(1)) &&
14426 // We don't have a good way to replace an EFLAGS use, so only do this when
14428 SDValue(N, 1).use_empty()) {
14429 DebugLoc DL = N->getDebugLoc();
14430 EVT VT = N->getValueType(0);
14431 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14432 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14433 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14434 DAG.getConstant(X86::COND_B,MVT::i8),
14436 DAG.getConstant(1, VT));
14437 return DCI.CombineTo(N, Res1, CarryOut);
14443 // fold (add Y, (sete X, 0)) -> adc 0, Y
14444 // (add Y, (setne X, 0)) -> sbb -1, Y
14445 // (sub (sete X, 0), Y) -> sbb 0, Y
14446 // (sub (setne X, 0), Y) -> adc -1, Y
14447 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14448 DebugLoc DL = N->getDebugLoc();
14450 // Look through ZExts.
14451 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14452 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14455 SDValue SetCC = Ext.getOperand(0);
14456 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14459 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14460 if (CC != X86::COND_E && CC != X86::COND_NE)
14463 SDValue Cmp = SetCC.getOperand(1);
14464 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14465 !X86::isZeroNode(Cmp.getOperand(1)) ||
14466 !Cmp.getOperand(0).getValueType().isInteger())
14469 SDValue CmpOp0 = Cmp.getOperand(0);
14470 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14471 DAG.getConstant(1, CmpOp0.getValueType()));
14473 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14474 if (CC == X86::COND_NE)
14475 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14476 DL, OtherVal.getValueType(), OtherVal,
14477 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14478 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14479 DL, OtherVal.getValueType(), OtherVal,
14480 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14483 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14484 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14485 const X86Subtarget *Subtarget) {
14486 EVT VT = N->getValueType(0);
14487 SDValue Op0 = N->getOperand(0);
14488 SDValue Op1 = N->getOperand(1);
14490 // Try to synthesize horizontal adds from adds of shuffles.
14491 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14492 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) &&
14493 isHorizontalBinOp(Op0, Op1, true))
14494 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14496 return OptimizeConditionalInDecrement(N, DAG);
14499 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14500 const X86Subtarget *Subtarget) {
14501 SDValue Op0 = N->getOperand(0);
14502 SDValue Op1 = N->getOperand(1);
14504 // X86 can't encode an immediate LHS of a sub. See if we can push the
14505 // negation into a preceding instruction.
14506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14507 // If the RHS of the sub is a XOR with one use and a constant, invert the
14508 // immediate. Then add one to the LHS of the sub so we can turn
14509 // X-Y -> X+~Y+1, saving one register.
14510 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14511 isa<ConstantSDNode>(Op1.getOperand(1))) {
14512 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14513 EVT VT = Op0.getValueType();
14514 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14516 DAG.getConstant(~XorC, VT));
14517 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14518 DAG.getConstant(C->getAPIntValue()+1, VT));
14522 // Try to synthesize horizontal adds from adds of shuffles.
14523 EVT VT = N->getValueType(0);
14524 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14525 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14526 isHorizontalBinOp(Op0, Op1, true))
14527 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14529 return OptimizeConditionalInDecrement(N, DAG);
14532 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14533 DAGCombinerInfo &DCI) const {
14534 SelectionDAG &DAG = DCI.DAG;
14535 switch (N->getOpcode()) {
14537 case ISD::EXTRACT_VECTOR_ELT:
14538 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14540 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
14541 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14542 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14543 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14544 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14545 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14548 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14549 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14550 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14551 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14552 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14553 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14554 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14555 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14556 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14558 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14559 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14560 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14561 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14562 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14563 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14564 case X86ISD::SHUFPS: // Handle all target specific shuffles
14565 case X86ISD::SHUFPD:
14566 case X86ISD::PALIGN:
14567 case X86ISD::UNPCKH:
14568 case X86ISD::UNPCKL:
14569 case X86ISD::MOVHLPS:
14570 case X86ISD::MOVLHPS:
14571 case X86ISD::PSHUFD:
14572 case X86ISD::PSHUFHW:
14573 case X86ISD::PSHUFLW:
14574 case X86ISD::MOVSS:
14575 case X86ISD::MOVSD:
14576 case X86ISD::VPERMILP:
14577 case X86ISD::VPERM2X128:
14578 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14584 /// isTypeDesirableForOp - Return true if the target has native support for
14585 /// the specified value type and it is 'desirable' to use the type for the
14586 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14587 /// instruction encodings are longer and some i16 instructions are slow.
14588 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14589 if (!isTypeLegal(VT))
14591 if (VT != MVT::i16)
14598 case ISD::SIGN_EXTEND:
14599 case ISD::ZERO_EXTEND:
14600 case ISD::ANY_EXTEND:
14613 /// IsDesirableToPromoteOp - This method query the target whether it is
14614 /// beneficial for dag combiner to promote the specified node. If true, it
14615 /// should return the desired promotion type by reference.
14616 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14617 EVT VT = Op.getValueType();
14618 if (VT != MVT::i16)
14621 bool Promote = false;
14622 bool Commute = false;
14623 switch (Op.getOpcode()) {
14626 LoadSDNode *LD = cast<LoadSDNode>(Op);
14627 // If the non-extending load has a single use and it's not live out, then it
14628 // might be folded.
14629 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14630 Op.hasOneUse()*/) {
14631 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14632 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14633 // The only case where we'd want to promote LOAD (rather then it being
14634 // promoted as an operand is when it's only use is liveout.
14635 if (UI->getOpcode() != ISD::CopyToReg)
14642 case ISD::SIGN_EXTEND:
14643 case ISD::ZERO_EXTEND:
14644 case ISD::ANY_EXTEND:
14649 SDValue N0 = Op.getOperand(0);
14650 // Look out for (store (shl (load), x)).
14651 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14664 SDValue N0 = Op.getOperand(0);
14665 SDValue N1 = Op.getOperand(1);
14666 if (!Commute && MayFoldLoad(N1))
14668 // Avoid disabling potential load folding opportunities.
14669 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14671 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14681 //===----------------------------------------------------------------------===//
14682 // X86 Inline Assembly Support
14683 //===----------------------------------------------------------------------===//
14685 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14686 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14688 std::string AsmStr = IA->getAsmString();
14690 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14691 SmallVector<StringRef, 4> AsmPieces;
14692 SplitString(AsmStr, AsmPieces, ";\n");
14694 switch (AsmPieces.size()) {
14695 default: return false;
14697 AsmStr = AsmPieces[0];
14699 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
14701 // FIXME: this should verify that we are targeting a 486 or better. If not,
14702 // we will turn this bswap into something that will be lowered to logical ops
14703 // instead of emitting the bswap asm. For now, we don't support 486 or lower
14704 // so don't worry about this.
14706 if (AsmPieces.size() == 2 &&
14707 (AsmPieces[0] == "bswap" ||
14708 AsmPieces[0] == "bswapq" ||
14709 AsmPieces[0] == "bswapl") &&
14710 (AsmPieces[1] == "$0" ||
14711 AsmPieces[1] == "${0:q}")) {
14712 // No need to check constraints, nothing other than the equivalent of
14713 // "=r,0" would be valid here.
14714 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14715 if (!Ty || Ty->getBitWidth() % 16 != 0)
14717 return IntrinsicLowering::LowerToByteSwap(CI);
14719 // rorw $$8, ${0:w} --> llvm.bswap.i16
14720 if (CI->getType()->isIntegerTy(16) &&
14721 AsmPieces.size() == 3 &&
14722 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
14723 AsmPieces[1] == "$$8," &&
14724 AsmPieces[2] == "${0:w}" &&
14725 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14727 const std::string &ConstraintsStr = IA->getConstraintString();
14728 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14729 std::sort(AsmPieces.begin(), AsmPieces.end());
14730 if (AsmPieces.size() == 4 &&
14731 AsmPieces[0] == "~{cc}" &&
14732 AsmPieces[1] == "~{dirflag}" &&
14733 AsmPieces[2] == "~{flags}" &&
14734 AsmPieces[3] == "~{fpsr}") {
14735 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14736 if (!Ty || Ty->getBitWidth() % 16 != 0)
14738 return IntrinsicLowering::LowerToByteSwap(CI);
14743 if (CI->getType()->isIntegerTy(32) &&
14744 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14745 SmallVector<StringRef, 4> Words;
14746 SplitString(AsmPieces[0], Words, " \t,");
14747 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14748 Words[2] == "${0:w}") {
14750 SplitString(AsmPieces[1], Words, " \t,");
14751 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
14752 Words[2] == "$0") {
14754 SplitString(AsmPieces[2], Words, " \t,");
14755 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14756 Words[2] == "${0:w}") {
14758 const std::string &ConstraintsStr = IA->getConstraintString();
14759 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14760 std::sort(AsmPieces.begin(), AsmPieces.end());
14761 if (AsmPieces.size() == 4 &&
14762 AsmPieces[0] == "~{cc}" &&
14763 AsmPieces[1] == "~{dirflag}" &&
14764 AsmPieces[2] == "~{flags}" &&
14765 AsmPieces[3] == "~{fpsr}") {
14766 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14767 if (!Ty || Ty->getBitWidth() % 16 != 0)
14769 return IntrinsicLowering::LowerToByteSwap(CI);
14776 if (CI->getType()->isIntegerTy(64)) {
14777 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14778 if (Constraints.size() >= 2 &&
14779 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14780 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14781 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14782 SmallVector<StringRef, 4> Words;
14783 SplitString(AsmPieces[0], Words, " \t");
14784 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
14786 SplitString(AsmPieces[1], Words, " \t");
14787 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
14789 SplitString(AsmPieces[2], Words, " \t,");
14790 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
14791 Words[2] == "%edx") {
14792 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14793 if (!Ty || Ty->getBitWidth() % 16 != 0)
14795 return IntrinsicLowering::LowerToByteSwap(CI);
14808 /// getConstraintType - Given a constraint letter, return the type of
14809 /// constraint it is for this target.
14810 X86TargetLowering::ConstraintType
14811 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14812 if (Constraint.size() == 1) {
14813 switch (Constraint[0]) {
14824 return C_RegisterClass;
14848 return TargetLowering::getConstraintType(Constraint);
14851 /// Examine constraint type and operand type and determine a weight value.
14852 /// This object must already have been set up with the operand type
14853 /// and the current alternative constraint selected.
14854 TargetLowering::ConstraintWeight
14855 X86TargetLowering::getSingleConstraintMatchWeight(
14856 AsmOperandInfo &info, const char *constraint) const {
14857 ConstraintWeight weight = CW_Invalid;
14858 Value *CallOperandVal = info.CallOperandVal;
14859 // If we don't have a value, we can't do a match,
14860 // but allow it at the lowest weight.
14861 if (CallOperandVal == NULL)
14863 Type *type = CallOperandVal->getType();
14864 // Look at the constraint type.
14865 switch (*constraint) {
14867 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14878 if (CallOperandVal->getType()->isIntegerTy())
14879 weight = CW_SpecificReg;
14884 if (type->isFloatingPointTy())
14885 weight = CW_SpecificReg;
14888 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14889 weight = CW_SpecificReg;
14893 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14894 weight = CW_Register;
14897 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14898 if (C->getZExtValue() <= 31)
14899 weight = CW_Constant;
14903 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14904 if (C->getZExtValue() <= 63)
14905 weight = CW_Constant;
14909 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14910 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14911 weight = CW_Constant;
14915 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14916 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14917 weight = CW_Constant;
14921 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14922 if (C->getZExtValue() <= 3)
14923 weight = CW_Constant;
14927 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14928 if (C->getZExtValue() <= 0xff)
14929 weight = CW_Constant;
14934 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14935 weight = CW_Constant;
14939 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14940 if ((C->getSExtValue() >= -0x80000000LL) &&
14941 (C->getSExtValue() <= 0x7fffffffLL))
14942 weight = CW_Constant;
14946 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14947 if (C->getZExtValue() <= 0xffffffff)
14948 weight = CW_Constant;
14955 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14956 /// with another that has more specific requirements based on the type of the
14957 /// corresponding operand.
14958 const char *X86TargetLowering::
14959 LowerXConstraint(EVT ConstraintVT) const {
14960 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14961 // 'f' like normal targets.
14962 if (ConstraintVT.isFloatingPoint()) {
14963 if (Subtarget->hasXMMInt())
14965 if (Subtarget->hasXMM())
14969 return TargetLowering::LowerXConstraint(ConstraintVT);
14972 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14973 /// vector. If it is invalid, don't add anything to Ops.
14974 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14975 std::string &Constraint,
14976 std::vector<SDValue>&Ops,
14977 SelectionDAG &DAG) const {
14978 SDValue Result(0, 0);
14980 // Only support length 1 constraints for now.
14981 if (Constraint.length() > 1) return;
14983 char ConstraintLetter = Constraint[0];
14984 switch (ConstraintLetter) {
14987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14988 if (C->getZExtValue() <= 31) {
14989 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14995 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14996 if (C->getZExtValue() <= 63) {
14997 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15004 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15005 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15012 if (C->getZExtValue() <= 255) {
15013 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15019 // 32-bit signed value
15020 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15021 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15022 C->getSExtValue())) {
15023 // Widen to 64 bits here to get it sign extended.
15024 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15027 // FIXME gcc accepts some relocatable values here too, but only in certain
15028 // memory models; it's complicated.
15033 // 32-bit unsigned value
15034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15035 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15036 C->getZExtValue())) {
15037 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15041 // FIXME gcc accepts some relocatable values here too, but only in certain
15042 // memory models; it's complicated.
15046 // Literal immediates are always ok.
15047 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15048 // Widen to 64 bits here to get it sign extended.
15049 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15053 // In any sort of PIC mode addresses need to be computed at runtime by
15054 // adding in a register or some sort of table lookup. These can't
15055 // be used as immediates.
15056 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15059 // If we are in non-pic codegen mode, we allow the address of a global (with
15060 // an optional displacement) to be used with 'i'.
15061 GlobalAddressSDNode *GA = 0;
15062 int64_t Offset = 0;
15064 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15066 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15067 Offset += GA->getOffset();
15069 } else if (Op.getOpcode() == ISD::ADD) {
15070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15071 Offset += C->getZExtValue();
15072 Op = Op.getOperand(0);
15075 } else if (Op.getOpcode() == ISD::SUB) {
15076 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15077 Offset += -C->getZExtValue();
15078 Op = Op.getOperand(0);
15083 // Otherwise, this isn't something we can handle, reject it.
15087 const GlobalValue *GV = GA->getGlobal();
15088 // If we require an extra load to get this address, as in PIC mode, we
15089 // can't accept it.
15090 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15091 getTargetMachine())))
15094 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15095 GA->getValueType(0), Offset);
15100 if (Result.getNode()) {
15101 Ops.push_back(Result);
15104 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15107 std::pair<unsigned, const TargetRegisterClass*>
15108 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15110 // First, see if this is a constraint that directly corresponds to an LLVM
15112 if (Constraint.size() == 1) {
15113 // GCC Constraint Letters
15114 switch (Constraint[0]) {
15116 // TODO: Slight differences here in allocation order and leaving
15117 // RIP in the class. Do they matter any more here than they do
15118 // in the normal allocation?
15119 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15120 if (Subtarget->is64Bit()) {
15121 if (VT == MVT::i32 || VT == MVT::f32)
15122 return std::make_pair(0U, X86::GR32RegisterClass);
15123 else if (VT == MVT::i16)
15124 return std::make_pair(0U, X86::GR16RegisterClass);
15125 else if (VT == MVT::i8 || VT == MVT::i1)
15126 return std::make_pair(0U, X86::GR8RegisterClass);
15127 else if (VT == MVT::i64 || VT == MVT::f64)
15128 return std::make_pair(0U, X86::GR64RegisterClass);
15131 // 32-bit fallthrough
15132 case 'Q': // Q_REGS
15133 if (VT == MVT::i32 || VT == MVT::f32)
15134 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15135 else if (VT == MVT::i16)
15136 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15137 else if (VT == MVT::i8 || VT == MVT::i1)
15138 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15139 else if (VT == MVT::i64)
15140 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15142 case 'r': // GENERAL_REGS
15143 case 'l': // INDEX_REGS
15144 if (VT == MVT::i8 || VT == MVT::i1)
15145 return std::make_pair(0U, X86::GR8RegisterClass);
15146 if (VT == MVT::i16)
15147 return std::make_pair(0U, X86::GR16RegisterClass);
15148 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15149 return std::make_pair(0U, X86::GR32RegisterClass);
15150 return std::make_pair(0U, X86::GR64RegisterClass);
15151 case 'R': // LEGACY_REGS
15152 if (VT == MVT::i8 || VT == MVT::i1)
15153 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15154 if (VT == MVT::i16)
15155 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15156 if (VT == MVT::i32 || !Subtarget->is64Bit())
15157 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15158 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15159 case 'f': // FP Stack registers.
15160 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15161 // value to the correct fpstack register class.
15162 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15163 return std::make_pair(0U, X86::RFP32RegisterClass);
15164 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15165 return std::make_pair(0U, X86::RFP64RegisterClass);
15166 return std::make_pair(0U, X86::RFP80RegisterClass);
15167 case 'y': // MMX_REGS if MMX allowed.
15168 if (!Subtarget->hasMMX()) break;
15169 return std::make_pair(0U, X86::VR64RegisterClass);
15170 case 'Y': // SSE_REGS if SSE2 allowed
15171 if (!Subtarget->hasXMMInt()) break;
15173 case 'x': // SSE_REGS if SSE1 allowed
15174 if (!Subtarget->hasXMM()) break;
15176 switch (VT.getSimpleVT().SimpleTy) {
15178 // Scalar SSE types.
15181 return std::make_pair(0U, X86::FR32RegisterClass);
15184 return std::make_pair(0U, X86::FR64RegisterClass);
15192 return std::make_pair(0U, X86::VR128RegisterClass);
15198 // Use the default implementation in TargetLowering to convert the register
15199 // constraint into a member of a register class.
15200 std::pair<unsigned, const TargetRegisterClass*> Res;
15201 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15203 // Not found as a standard register?
15204 if (Res.second == 0) {
15205 // Map st(0) -> st(7) -> ST0
15206 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15207 tolower(Constraint[1]) == 's' &&
15208 tolower(Constraint[2]) == 't' &&
15209 Constraint[3] == '(' &&
15210 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15211 Constraint[5] == ')' &&
15212 Constraint[6] == '}') {
15214 Res.first = X86::ST0+Constraint[4]-'0';
15215 Res.second = X86::RFP80RegisterClass;
15219 // GCC allows "st(0)" to be called just plain "st".
15220 if (StringRef("{st}").equals_lower(Constraint)) {
15221 Res.first = X86::ST0;
15222 Res.second = X86::RFP80RegisterClass;
15227 if (StringRef("{flags}").equals_lower(Constraint)) {
15228 Res.first = X86::EFLAGS;
15229 Res.second = X86::CCRRegisterClass;
15233 // 'A' means EAX + EDX.
15234 if (Constraint == "A") {
15235 Res.first = X86::EAX;
15236 Res.second = X86::GR32_ADRegisterClass;
15242 // Otherwise, check to see if this is a register class of the wrong value
15243 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15244 // turn into {ax},{dx}.
15245 if (Res.second->hasType(VT))
15246 return Res; // Correct type already, nothing to do.
15248 // All of the single-register GCC register classes map their values onto
15249 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15250 // really want an 8-bit or 32-bit register, map to the appropriate register
15251 // class and return the appropriate register.
15252 if (Res.second == X86::GR16RegisterClass) {
15253 if (VT == MVT::i8) {
15254 unsigned DestReg = 0;
15255 switch (Res.first) {
15257 case X86::AX: DestReg = X86::AL; break;
15258 case X86::DX: DestReg = X86::DL; break;
15259 case X86::CX: DestReg = X86::CL; break;
15260 case X86::BX: DestReg = X86::BL; break;
15263 Res.first = DestReg;
15264 Res.second = X86::GR8RegisterClass;
15266 } else if (VT == MVT::i32) {
15267 unsigned DestReg = 0;
15268 switch (Res.first) {
15270 case X86::AX: DestReg = X86::EAX; break;
15271 case X86::DX: DestReg = X86::EDX; break;
15272 case X86::CX: DestReg = X86::ECX; break;
15273 case X86::BX: DestReg = X86::EBX; break;
15274 case X86::SI: DestReg = X86::ESI; break;
15275 case X86::DI: DestReg = X86::EDI; break;
15276 case X86::BP: DestReg = X86::EBP; break;
15277 case X86::SP: DestReg = X86::ESP; break;
15280 Res.first = DestReg;
15281 Res.second = X86::GR32RegisterClass;
15283 } else if (VT == MVT::i64) {
15284 unsigned DestReg = 0;
15285 switch (Res.first) {
15287 case X86::AX: DestReg = X86::RAX; break;
15288 case X86::DX: DestReg = X86::RDX; break;
15289 case X86::CX: DestReg = X86::RCX; break;
15290 case X86::BX: DestReg = X86::RBX; break;
15291 case X86::SI: DestReg = X86::RSI; break;
15292 case X86::DI: DestReg = X86::RDI; break;
15293 case X86::BP: DestReg = X86::RBP; break;
15294 case X86::SP: DestReg = X86::RSP; break;
15297 Res.first = DestReg;
15298 Res.second = X86::GR64RegisterClass;
15301 } else if (Res.second == X86::FR32RegisterClass ||
15302 Res.second == X86::FR64RegisterClass ||
15303 Res.second == X86::VR128RegisterClass) {
15304 // Handle references to XMM physical registers that got mapped into the
15305 // wrong class. This can happen with constraints like {xmm0} where the
15306 // target independent register mapper will just pick the first match it can
15307 // find, ignoring the required type.
15308 if (VT == MVT::f32)
15309 Res.second = X86::FR32RegisterClass;
15310 else if (VT == MVT::f64)
15311 Res.second = X86::FR64RegisterClass;
15312 else if (X86::VR128RegisterClass->hasType(VT))
15313 Res.second = X86::VR128RegisterClass;